The project designs, describes in VHDL and verifies by simulation a cache controller for a dual-core system. Each core has a private write-back cache; the two caches share one bus to main memory and are kept coherent by the MSI snoopy protocol. Honorable to mention that the project it's also currently in building.
cpp cache vhdl vivado cache-control cache-simulator cache-coherence cache-coherence-simulator dear-imgui-cpp cache-coherency msi-protocol
-
Updated
Nov 5, 2026 - VHDL