The repository implements MOESI protocol and contains multiple cores, interconnect and memory to understance how cache coherency works and impacts performance.
A cache coherence simulator for MESI, MOESI and Dragon Protocols.
Simulator that simulates multiprocessor caches and involved cache coherence protocols
This repository implements a scalable directory based cache coherence protocol.
Group Project Completed in CSE511:Computer Architecture course in IIITD during the Monsoon 2023 Semester. Professor: Sujay Deb
The project designs, describes in VHDL and verifies by simulation a cache controller for a dual-core system. Each core has a private write-back cache; the two caches share one bus to main memory and are kept coherent by the MSI snoopy protocol. Honorable to mention that the project it's also currently in building.
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