functional-verification

A Framework for Design and Verification of Image Processing Applications using UVM

A simple UVM example with DPI

Designing means to communicate as an SPI master, being a part of AXI interface

UVM-based functional verification of an APB-based UART Master Core RTL. Includes multi-agent environment, assertions, coverage collection, and multiple test scenarios (full/half duplex, parity, framing, timeout errors) achieving 100% functional coverage and protocol compliance.

Implements a simple UVM based testbench for a simple memory DUT.

A simple UVM testbench using UVM Connect and Octave

This repository is meant for learning UVM using SystemVerilog. Through a verification environment, some hardware verification concepts are applied for a calculator with the four basic operations.

Apply dataclasses concept to testbench automation in Python

A simple testbench with two refmods using UVM Connect

UVM VIP for Single Port RAM Synchronous Read/Write

A complete UVM-based verification environment for validating YAPP Router functionality using SystemVerilog and Cadence Xcelium, featuring advanced sequences, virtual interfaces, and coverage analysis.

UVM 1.2 Verification of Dual Clock Asynchronous FIFO

Language parser

SystemVerilog AXI4-Lite Slave IP with Hazard-Stalled FSM. Verified with 2M+ cycle randomized regression and 'Snoop & Serialize' collision handling.

UVM testbench for verifying a packet router using the YAPP (Yet Another Packet Protocol)

UVM verification of an 8×8 INT8 weight-stationary systolic-array ML accelerator — closed to 100% functional coverage on an open-source Verilator + UVM toolchain.

A Verilog RTL design of a 1x3 packet router with a complete UVM testbench for verification. Includes FIFO buffers, FSM control, assertions, coverage, and synthesis support.

Verification of Advanced Encryption Standard (AES-128) Using UVM

AMBA APB Slave implementation and self-checking verification in Verilog HDL using a modular RTL architecture and behavioral reference model.

Layered SystemVerilog testbench for verifying a parameterized Synchronous FIFO. Includes directed and constrained-random tests, functional coverage, assertions, and scoreboard-based checking.