GitHub - nelsoncsc/basic_uvmc_oct: A simple UVM testbench using UVM Connect and Octave · GitHub

Repository navigation

basic_uvmc_oct

Public

About

A simple UVM testbench using UVM Connect and Octave

functional-verification octave systemc systemverilog-hdl uvm

10 stars

2 watching

Report repository

Name		Name	Last commit message	Last commit date
trans		trans
LICENSE		LICENSE
Makefile		Makefile
README.md		README.md
comparator.sv		comparator.sv
env.sv		env.sv
external.cpp		external.cpp
myfile.txt		myfile.txt
packet_in.sv		packet_in.sv
packet_out.sv		packet_out.sv
path_tr.sv		path_tr.sv
reffunc.m		reffunc.m
refmod.cpp		refmod.cpp
refmod_low.cpp		refmod_low.cpp
refmod_oct.cpp		refmod_oct.cpp
sequence_in.sv		sequence_in.sv
sequencer.sv		sequencer.sv
test.sv		test.sv
top.cpp		top.cpp
top.sv		top.sv

Repository files navigation

#basic_uvmc_octave: a simple testbench with three refmods using UVM Connect and Octave https://sistenix.com/basic_uvmc_oct.html

About

A simple UVM testbench using UVM Connect and Octave

functional-verification octave systemc systemverilog-hdl uvm

10 stars

2 watching

Report repository

Releases

Packages

Contributors

Languages