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acp_7_x: enable ACP 7.X DMIC (PDM0/PDM1) capture, SDW+PDM topologies, and clk #11317

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acp_7_x: enable ACP 7.X DMIC (PDM0/PDM1) capture, SDW+PDM topologies, and clk #11317

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3e8f06f
acp_7_x: dma: set the host DMA channel count to 10
sneha-voona Oct 13, 2026
2aaa690
acp_7_x: memory: set the SRAM1 size to 0x3F4000
sneha-voona Oct 14, 2026
3694b9d
acp_7_x: memory: drop the SOF stack macros
sneha-voona Oct 16, 2026
6886866
acp_7_x: board: enable CONFIG_SYS_HEAP_BIG_ONLY
sneha-voona Oct 16, 2026
54553b8
dai: acp: add SOF_DAI_AMD_DMIC to DAI and DMA dispatch tables
DINESHKUMARK1 Oct 8, 2026
ceb4011
acp_7_x: board: enable DMIC DAI and DMA drivers
DINESHKUMARK1 Oct 8, 2026
bc7701c
tools: topology: add ACP 7.X SDW and PDM capture topologies
DINESHKUMARK1 Oct 8, 2026
fc9f2f0
acp_7_x: clk: add PMFW/CLKMUX tracing, fix duplicate PLL power-on
DINESHKUMARK1 Oct 14, 2026
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3 changes: 3 additions & 0 deletions app/boards/acp_7_x_adsp.conf
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Original file line number Diff line number Diff line change
Expand Up @@ -11,9 +11,11 @@ CONFIG_DMA=y
CONFIG_DMA_DOMAIN=n
CONFIG_ZEPHYR_NATIVE_DRIVERS=y
CONFIG_INTC_AMD_ACP=y
CONFIG_DMA_AMD_ACP_DMIC=y
CONFIG_DMA_AMD_ACP_HOST=y
CONFIG_DMA_AMD_ACP_SDW=y
CONFIG_DMA_AMD_ACP_SDW_CHANNEL_COUNT=64
CONFIG_DAI_AMD_DMIC=y
CONFIG_DMA_AMD_ACP_TDM=y
CONFIG_DAI_AMD_SDW=y
CONFIG_DAI_AMD_TDM=y
Expand Down Expand Up @@ -63,3 +65,4 @@ CONFIG_LOG_BACKEND_ACP=y
CONFIG_LOG_DEFAULT_LEVEL=3
CONFIG_LOG_MAX_LEVEL=3
CONFIG_SOF_LOG_LEVEL_INF=y
CONFIG_SYS_HEAP_BIG_ONLY=y
4 changes: 4 additions & 0 deletions src/audio/dai-zephyr.c
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Original file line number Diff line number Diff line change
Expand Up @@ -190,6 +190,10 @@ __cold int dai_set_config(struct dai *dai, struct ipc_config_dai *common_config,
cfg.type = DAI_IMX_MICFIL;
cfg_params = &sof_cfg->micfil;
break;
case SOF_DAI_AMD_DMIC:
cfg.type = DAI_AMD_DMIC;
cfg_params = &sof_cfg->acpdmic;
break;
case SOF_DAI_AMD_SDW:
cfg.type = DAI_AMD_SDW;
cfg_params = &sof_cfg->acpsdw;
Expand Down
21 changes: 21 additions & 0 deletions src/ipc/ipc3/dai.c
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Expand Up @@ -190,6 +190,27 @@ int ipc_dai_data_config(struct dai_data *dd, struct comp_dev *dev)
if (dd->dma_buffer)
audio_stream_set_frm_fmt(&dd->dma_buffer->stream,
dev->ipc_config.frame_fmt);
#if defined(CONFIG_AMD) && !defined(CONFIG_SOC_ACP_6_0)
{
struct acp_dma_dev_data *dmic_data = dd->dma->z_dev->data;
struct dmic_context *dmic_ctx;

/* Allocate coherent memory for DMIC context shared between
* IPC and DMA contexts.
*/
if (!dmic_data->dai_index_ptr) {
dmic_ctx = rzalloc(SOF_MEM_FLAG_USER | SOF_MEM_FLAG_COHERENT,
sizeof(*dmic_ctx));
if (!dmic_ctx) {
return -ENOMEM;
}
dmic_data->dai_index_ptr = dmic_ctx;
} else {
dmic_ctx = (struct dmic_context *)dmic_data->dai_index_ptr;
}
dmic_ctx->index = dd->dai->index;
}
#endif
break;
case SOF_DAI_AMD_BT:
case SOF_DAI_AMD_SP:
Expand Down
7 changes: 7 additions & 0 deletions src/lib/dai.c
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Original file line number Diff line number Diff line change
Expand Up @@ -187,6 +187,9 @@ const struct device *zephyr_dev[] = {
#if CONFIG_DAI_NXP_MICFIL
DT_FOREACH_STATUS_OKAY(nxp_dai_micfil, GET_DEVICE_LIST)
#endif
#if CONFIG_DAI_AMD_DMIC
DT_FOREACH_STATUS_OKAY(amd_dmic_dai, GET_DEVICE_LIST)
#endif
#if CONFIG_DAI_AMD_SDW
DT_FOREACH_STATUS_OKAY(amd_acp_sdw_dai, GET_DEVICE_LIST)
#endif
Expand Down Expand Up @@ -318,6 +321,10 @@ static void dai_set_device_params(struct dai *d)
d->dma_dev = SOF_DMA_DEV_HS | SOF_DMA_DEV_SP | SOF_DMA_DEV_BT;
d->dma_caps = SOF_DMA_CAP_HS | SOF_DMA_CAP_SP | SOF_DMA_CAP_BT;
break;
case SOF_DAI_AMD_DMIC:
d->dma_dev = SOF_DMA_DEV_DMIC;
d->dma_caps = SOF_DMA_CAP_DMIC;
break;
case SOF_DAI_AMD_TDM:
d->dma_dev = SOF_DMA_DEV_TDM;
d->dma_caps = SOF_DMA_CAP_TDM;
Expand Down
8 changes: 1 addition & 7 deletions src/platform/amd/acp_7_x/include/platform/lib/memory.h
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Original file line number Diff line number Diff line change
Expand Up @@ -29,7 +29,7 @@
#define DRAM1_BASE 0xE0010000
#define DRAM1_SIZE 0x10000
#define SRAM1_BASE 0x6000C000
#define SRAM1_SIZE 0x274000
#define SRAM1_SIZE 0x3F4000

#define DMA0_BASE PU_REGISTER_BASE
#define DMA0_SIZE 0x4
Expand Down Expand Up @@ -126,12 +126,6 @@
#define EXT_MANIFEST_ELF_BASE (LOG_ENTRY_ELF_BASE + LOG_ENTRY_ELF_SIZE)
#define EXT_MANIFEST_ELF_SIZE 0x2000000

/* Stack configuration */
#define SOF_STACK_SIZE (0x1000)
#define SOF_STACK_TOTAL_SIZE SOF_STACK_SIZE
#define SOF_STACK_END (DRAM1_BASE + DRAM1_SIZE - SOF_STACK_SIZE)
#define SOF_STACK_BASE (SOF_STACK_END + SOF_STACK_SIZE)

/* Mailbox configuration */
#define SRAM_OUTBOX_BASE SRAM0_BASE
#define SRAM_OUTBOX_SIZE 0x400
Expand Down
89 changes: 73 additions & 16 deletions src/platform/amd/acp_7_x/include/platform/platform_misc.h
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Original file line number Diff line number Diff line change
Expand Up @@ -20,6 +20,7 @@
#define ACP_DSP_SW_INTR_CNTL 0x1241860
#define ACP_DSP_SW_INTR_STAT 0x1241864
#define ACP_AXI2DAGB_SEM_0 0x12418F4
#define ACP_ERROR_STATUS 0x1241A88
#define ACP_SRBM_CLIENT_BASE_ADDR 0x1241BF0
#define ACP_SRBM_CLIENT_RDDATA 0x1241BF4
#define ACP_SRBM_CYCLE_STS 0x1241BF8
Expand All @@ -36,23 +37,43 @@
#define ACP_7X_SYSTEMPLL2P0_N3_BUS_CSR_SNAP_6_AI_FREQ_CTRL9_BRDS 0x6D20C

/* Registers from CLK6 block */
#define mmCLK6_PLL0_DFS0_CNTL 0x6D014
#define mmCLK6_PLL0_DFS0_STATUS 0x6D018
#define mmCLK6_PLL0_DFS1_CNTL 0x6D01C
#define mmCLK6_PLL0_DFS1_STATUS 0x6D020
#define mmCLK6_CLK0_BYPASS_CNTL 0x6D06C
#define mmCLK6_CLK1_BYPASS_CNTL 0x6D08C
#define mmCLK6_CLK_TICK_CNT_CONFIG_REG 0x6D188
#define mmCLK6_CLK0_CURRENT_CNT 0x6D190
#define mmCLK6_CLK1_CURRENT_CNT 0x6D194

#define ACP_CLK6_PLL0_DFS0_CNTL 0x6D014
#define ACP_CLK6_PLL0_DFS0_STATUS 0x6D018
#define ACP_CLK6_PLL0_DFS1_CNTL 0x6D01C
#define ACP_CLK6_PLL0_DFS1_STATUS 0x6D020
#define ACP_CLK6_CLK0_BYPASS_CNTL 0x6D06C
#define ACP_CLK6_CLK1_DS_CNTL 0x6D074
#define ACP_CLK6_CLK1_BYPASS_CNTL 0x6D08C
#define ACP_CLK6_CLK5_POSTDIV_CNTL 0x6D100
#define ACP_CLK6_CLK5_BYPASS_CNTL 0x6D10C
#define ACP_CLK6_PLL0_DFSBYPASS_CONTROL 0x6D180
#define ACP_CLK6_CLK_TICK_CNT_CONFIG_REG 0x6D188
#define ACP_CLK6_CLK0_CURRENT_CNT 0x6D190
#define ACP_CLK6_CLK1_CURRENT_CNT 0x6D194

#define ACP_DFS_BYPASS_ENTER_AUDIOCLK 0x00000001
#define ACP_DFS_BYPASS_ENTER_ACLK 0x00000002
#define ACP_DFS_BYPASS_EXIT_AUDIOCLK 0x00010000
#define ACP_DFS_BYPASS_EXIT_ACLK 0x00020000
#define ACP_CLK_BYPASS_SEL_AUDIO_PLL 0x0
#define ACP_CLK_BYPASS_SEL_LPPLL 0x4
#define ACP_CLK_BYPASS_SEL_REFCLK_24MHZ 0x5
#define ACP_CLK_DIV_BY_1 0x0
#define ACP_CLK_DIV_BY_16 0x4
#define ACP_CLKMUX_SEL 0x124102C
#define ACP_SW_48MHz_CLK_SEL 0x1241030
#define ACP_ACLK_AUDIOCLK_CTRL 0x1241464

#define ACP_DEEPSLEEP_DISABLE 0x0
#define ACP_DEEPSLEEP_ENABLE 0x3
#define ACP_SW_CLK_SEL_49152KHZ 0x1F
/* CLK6 register aliases without mm prefix for clock management code */
#define CLK6_PLL0_DFS0_CNTL mmCLK6_PLL0_DFS0_CNTL
#define CLK6_PLL0_DFS1_CNTL mmCLK6_PLL0_DFS1_CNTL
#define CLK6_PLL0_DFS1_STATUS mmCLK6_PLL0_DFS1_STATUS
#define CLK0_CURRENT_CNT mmCLK6_CLK0_CURRENT_CNT
#define CLK1_CURRENT_CNT mmCLK6_CLK1_CURRENT_CNT
#define CLK_TICK_CNT_CONFIG_REG mmCLK6_CLK_TICK_CNT_CONFIG_REG
#define CLK6_PLL0_DFS0_CNTL ACP_CLK6_PLL0_DFS0_CNTL
#define CLK6_PLL0_DFS1_CNTL ACP_CLK6_PLL0_DFS1_CNTL
#define CLK6_PLL0_DFS1_STATUS ACP_CLK6_PLL0_DFS1_STATUS
#define CLK0_CURRENT_CNT ACP_CLK6_CLK0_CURRENT_CNT
#define CLK1_CURRENT_CNT ACP_CLK6_CLK1_CURRENT_CNT
#define CLK_TICK_CNT_CONFIG_REG ACP_CLK6_CLK_TICK_CNT_CONFIG_REG

/* SYSTEMPLL2P0 register aliases without ACP_7X prefix */
#define SYSTEMPLL2P0_N3_BUS_CSR_SNAP_6_NON_AI_CTRL0_BRDS ACP_7X_SYSTEMPLL2P0_N3_BUS_CSR_SNAP_6_NON_AI_CTRL0_BRDS
Expand Down Expand Up @@ -478,6 +499,42 @@ typedef union clk6_clk_bypass_cntl_u {
float f32All;
} clk6_bypass_cntl_u_t;

typedef union clk6_clk_ds_cntl_u {
struct {
uint32_t CLK_DS_DIV_ID:4;
uint32_t CLK_ALLOW_DS:1;
uint32_t CLK_DS_DEGL_SET:3;
uint32_t CLK_DS_OVERRIDE:2;
uint32_t:22;
} bitfields, bits;
uint32_t u32All;
int32_t i32All;
float f32All;
} clk6_clk_ds_cntl_u_t;

typedef union clk6_clk_postdiv_cntl_u {
struct {
uint32_t CLK0_POSTDIV_DIV_ID:8;
uint32_t CLK0_POSTDIV_RAMP_DIS:1;
uint32_t:7;
uint32_t CLK0_POSTDIV_RAMP_STEP:4;
uint32_t:12;
} bitfields, bits;
uint32_t u32All;
int32_t i32All;
float f32All;
} clk6_clk_postdiv_cntl_u_t;

typedef union acp7x_clkmux_sel_u {
struct {
uint32_t DIV_SEL:4;
uint32_t:28;
} bitfields, bits;
uint32_t u32All;
int32_t i32All;
float f32All;
} acp7x_clkmux_sel_t;

typedef union acp_dsp_sw_intr_stat {
struct {
unsigned int host_to_dsp0_intr1_stat:1;
Expand Down
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