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acp_7_x: enable ACP 7.X DMIC (PDM0/PDM1) capture, SDW+PDM topologies, and clk - #11317
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ACP 7.x has 10 host DMA channels. ACP 7.0 keeps 8. Signed-off-by: DineshKumar Kalva <DineshKumar.Kalva@amd.com>
Shared SRAM is 4 MB and SRAM1 starts 48 KB above its base. Keep the SOF memory map and rimage SRAM zone on that window. Signed-off-by: DineshKumar Kalva <DineshKumar.Kalva@amd.com>
The ACP 7.x stack is placed by the Zephyr linker script. Remove the duplicate SOF_STACK_* macros from the platform memory header. Signed-off-by: DineshKumar Kalva <DineshKumar.Kalva@amd.com>
AMD has bigger heap so we need to enable this macro. Signed-off-by: DineshKumar Kalva <DineshKumar.Kalva@amd.com>
Route SOF_DAI_AMD_DMIC through the DAI and DMA layer: - dai-zephyr.c: map SOF_DAI_AMD_DMIC to DAI_AMD_DMIC and acpdmic - lib/dai.c: register amd_dmic_dai devices and set SOF_DMA_DEV_DMIC and SOF_DMA_CAP_DMIC in dai_set_device_params() - ipc3/dai.c: allocate a dmic_context for ACP 7.X and store the DAI index for the DMIC DMA driver - zephyr/lib/dma.c: add the acp_dmic_dma DMA array entry Signed-off-by: DineshKumar Kalva <DineshKumar.Kalva@amd.com>
Enable CONFIG_DMA_AMD_ACP_DMIC and CONFIG_DAI_AMD_DMIC for the ACP 7.X ADSP board so PDM capture can use the DMIC drivers. Signed-off-by: DineshKumar Kalva <DineshKumar.Kalva@amd.com>
Add sof-acp_7_x_sdw_pdm.m4 with the SoundWire headset, speaker, and SDW DMIC pipelines plus one ACP PDM capture backend. CMake builds four topologies from that file: - sof-acp7x-sdw-pdm-48k for PDM0 at 48000 - sof-acp7x-sdw-pdm1-16k, 48k, and 96k for PDM1 PDM0 is rejected unless the capture rate is 48000. Signed-off-by: DineshKumar Kalva <DineshKumar.Kalva@amd.com>
Add bounded PMFW mailbox response tracing (mp1_resp_name(), acp_pmfw_poll_response()) so PllPowerState requests show the PMFW response code and round-trip time instead of being silent. Add acp_clkmux_sel() plus the ACP_CLKMUX_SEL, clk6_clk_ds_cntl_u_t and clk6_clk_postdiv_cntl_u_t register definitions used by the AUDIOCLK/ACLK deep-sleep-disable and postdiv paths. Rename the ACP_CLKMUX_SEL bitfield member to DIV_SEL to avoid colliding with the register offset macro of the same name, and add the missing ACP_ prefix on CLK6_CLK1_BYPASS_CNTL that failed to build. Replace the hardcoded 0x1241A88 SMN error-status offset in change_clock_notify() with a named ACP_ERROR_STATUS macro, and the hardcoded tick-counter threshold 0x1E0 with ACP_CLK_MEASURE_THRESHOLD. Remove the duplicate mp1_mailbox_send() PLL power-on call from platform_init(): acp_change_clock_notify() already powers the PLL during the boot-time ACLK setup, so calling it twice was redundant. Not built on hardware; verified with xtensa-build-zephyr.py -p acp_7_x. Signed-off-by: DineshKumar Kalva <DineshKumar.Kalva@amd.com>
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Adds DMIC (PDM0/PDM1) capture support for the AMD ACP 7.X platform:
acp_7_x: dma: set the host DMA channel count to 10acp_7_x: memory: set the SRAM1 size to 0x3F4000acp_7_x: memory: drop the SOF stack macrosacp_7_x: board: enable CONFIG_SYS_HEAP_BIG_ONLYdai: acp: add SOF_DAI_AMD_DMIC to DAI and DMA dispatch tablesacp_7_x: board: enable DMIC DAI and DMA driverstools: topology: add ACP 7.X SDW and PDM capture topologiesacp_7_x: clk: add PMFW/CLKMUX tracing, fix duplicate PLL power-onDepends on the companion Zephyr PR for the ACP 7.X DMIC DAI/DMA drivers.