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Added support for reading patchliner e data (different chip layout) #43

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Merged
MichaelClerx merged 3 commits into from
Oct 8, 2026
Merged

Added support for reading patchliner e data (different chip layout) #43

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834455f
Added support for reading patchliner e data (different chip layout)
MichaelClerx Oct 5, 2026
8af2f63
Apply batched suggestions from code review
MichaelClerx Oct 8, 2026
25ef764
Added tests for row/column order of well names
MichaelClerx Oct 8, 2026
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21 changes: 14 additions & 7 deletions syncropatch_export/trace.py
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Original file line number Diff line number Diff line change
@@ -1,6 +1,5 @@
import json
import os
import string

import numpy as np

Expand Down Expand Up @@ -53,20 +52,28 @@ def __init__(self, filepath, json_file: str):
self.MeasurementLayout = TraceHeader['MeasurementLayout']
self.FileInformation = TraceHeader['FileInformation']

# Create (hardcoded) list-of-list of well names:
# Create list-of-list of well names, e.g. for SyncroPatch:
# [['A01', 'B01', ..., 'P01'],
# ['A02', 'B02', ..., 'P02'],
# ...
# ['A24', 'B24', ..., 'P24']]
# So a list of 24 lists with 16 entries each
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#
# "rows" here is columns in the above matrix!
self.WP_nRows = TraceHeader['Chiplayout']['WP_nRows']
self.WP_nCols = TraceHeader['Chiplayout']['WP_nCols']
if self.WP_nRows > 26:
raise NotImplementedError( # pragma: no cover
'Unsupported chip layout (more than 26 rows)')
if self.WP_nCols > 99:
raise NotImplementedError( # pragma: no cover
'Unsupported chip layout (more than 99 columns)')
abc = 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'
self.WELL_ID = np.array([
[lab + str(i).zfill(2) for lab in string.ascii_uppercase[:16]]
for i in range(1, 25)])
[f'{abc[i]}{j:>02}' for i in range(self.WP_nRows)]
for j in range(1, self.WP_nCols + 1)
])

self.NofSweeps = self.MeasurementLayout['NofSweeps']
self.WP_nRows = TraceHeader['Chiplayout']['WP_nRows']
self.WP_nCols = TraceHeader['Chiplayout']['WP_nCols']
self.nCols = self.MeasurementLayout['nCols']
self.NofSamples = self.MeasurementLayout['NofSamples']
self.Leakdata = self.MeasurementLayout['Leakdata']
Expand Down
15 changes: 11 additions & 4 deletions tests/test_trace_class.py
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Original file line number Diff line number Diff line change
Expand Up @@ -90,17 +90,24 @@ def test_get_QC(self):
self.assertGreater(len(QC_values), 0)

def test_get_traces(self):

# Check well ids
self.assertEqual(self.trace.WELL_ID[3, 2], 'C04')
self.assertEqual(len(self.trace.WELL_ID), 24)
self.assertEqual(len(self.trace.WELL_ID[0]), 16)

# Check voltage and time
v = self.trace.get_voltage()
ts = self.trace.get_times()
all_traces = self.trace.get_all_traces(leakcorrect=True)
all_traces = self.trace.get_all_traces()
# TODO: Check the output, numerically, by comparing a few points

self.assertTrue(np.all(np.isfinite(v)))
self.assertTrue(np.all(np.isfinite(ts)))

# Check traces
all_traces = self.trace.get_all_traces(leakcorrect=True)
all_traces = self.trace.get_all_traces()
for well, trace in all_traces.items():
self.assertTrue(np.all(np.isfinite(trace)))
# TODO: Check the output, numerically, by comparing a few points

# Test complex sweep selection
a = self.trace.get_trace_sweeps([-1, -2])
Expand Down
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