WIP: teensy41: add PJRC Teensy 4.1 platform support, Audio PLL scheduling, S/PDIF loopback, and ARM Cortex-M7 SIMD optimizations

[lgirdwood]

Summary

WIP: patches need split/squashed, contains commit from other PRs too.

Work in progress: Adds support for the PJRC Teensy 4.1 development board (NXP i.MX RT1062 Cortex-M7 @ 600 MHz with single-precision FPU, Audio PLL4, and eDMA) running Sound Open Firmware (SOF) with Zephyr USB Audio Class 2.0 (UAC2), and introduces Phase 1 & Phase 2 of ARM Cortex-M7 SIMD & DSP optimizations across hot-path audio processing modules.

All changes have been validated on a dual-board physical hardware test fixture (Board A Master Tx $\to$ Board B Slave Rx) over S/PDIF hardware loopback, achieving 140.81 dB SNR with 0 dropped frames.

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Key Changes

1. Platform Support (platform/teensy41 & app/boards/teensy41)

• NXP i.MX RT1062 Architecture:
  • Configures on-chip Audio PLL (PLL4) generating 688.128 MHz ($24\text{ MHz} \times (28 + 6720/10000)$).
  • Derived audio clocks:
    • SAI1 Clock: PreDiv /4, Podf /14 $\implies$ exact $12.288\text{ MHz}$ SAI1 MCLK ($256 \times 48\text{ kHz}$) and $1.536\text{ MHz}$ BCLK.
    • S/PDIF Clock: Root divided by 4 and 7 $\implies$ exact $24.576000\text{ MHz}$ clock root. S/PDIF internal divider divides by 8 $\implies$ exact $3.072000\text{ MHz}$ BMC bit clock ($64 \times 48.000\text{ kHz}$).
• Hardware S/PDIF Transceiver & eDMA:
  • Pin 14 (SPDIF_OUT) and Pin 15 (SPDIF_IN) configured with fast slew rate (0x10B1).
  • Zephyr eDMA driver configured for stereo ping-pong with atomic 8-byte transfers.
  • Idle state BMC carrier transmission (SPDIF_SCR_TXFIFO_CTRL(0)) maintaining receiver PLL lock when idle.
• Audio PLL-Driven Low-Latency (LL) Scheduling:
  • Period completion callbacks (dai_zephyr_dma_period_cb) from cyclic eDMA wake the LL scheduling thread every 48 audio frames (1.000 ms).
  • Automatically suppresses SysTick k_timer scheduling ticks while audio is active.
• UAC2 Double Buffer Replenishment:
  • Instant double buffer replenishment on USB buffer release preventing capture underflow/overflow.

2. ARM Cortex-M7 SIMD & DSP Acceleration Framework (include/sof/audio/arm_simd.h)

Provides Cortex-M DSP intrinsics and inline assembly primitives with generic portable fallbacks:

• Dual 16-bit packed multiply and multiply-accumulate: arm_smulbb, arm_smultt, arm_smlad, arm_smlald.
• Single-cycle 32x32 $\to$ 64-bit accumulate: arm_smlal, arm_smull.
• Dual 16-bit saturating addition: arm_qadd16.
• 32-bit saturating addition: arm_qadd.
• Branchless bit-accurate saturation: arm_sat_s16, arm_sat_s24.
• Most-significant 32x32 multiply with rounding: arm_smmulr.
• Halfword packing and extraction: arm_pkhbt, arm_pkhtb, arm_sxth.
• Leading zero count normalization: arm_clz.

3. Audio Module Optimizations (Phase 1 & Phase 2)

• volume & volume_with_peakvol:
  • S16 packed SIMD halfword processing, branchless S24/S32 math, and unrolled hardware float scaling (vmul.f32).
  • Branchless peak detection and volume metering.
• math/iir_df1 & math/iir_df2t:
  • 5-term MAC throughput in single-cycle operations via SMLAL (32x32 $\to$ 64-bit accumulate) and branchless saturation.
• eq_iir:
  • 64-sample block-accelerated IIR filtering maintaining filter state registers in ARM core registers.
• drc & drc_math:
  • Fast single-cycle CLZ leading-zero normalization, Horner polynomial evaluation with SMMULR, and unrolled compressor loop.
• math/fir & audio/eq_fir:
  • 4-tap unrolled FIR inner loops utilizing single-cycle SMLAL 64-bit MAC (fir_32x16).
  • Dual-sample fir_32x16_2x computing 2 consecutive samples per step, halving delay-line load operations.
  • S16, S24, and S32 2x streaming loops in eq_fir_arm.c.
• audio/mixer:
  • Dual 16-bit saturating add in 1 cycle via arm_qadd16.
  • 32-bit saturating add via arm_qadd, 24-bit saturation via arm_sat_s24, and unrolled single-precision vector addition (vadd.f32).
• audio/mixin_mixout:
  • IPC4 channel mixing accelerated with saturating SIMD adds and hardware gain multipliers (arm_smulbb, arm_smmulr, vfma.f32).
• audio/dcblock:
  • Single-pole highpass filter accelerated with 64-bit signed MAC (arm_smlal / SMULL) and hardware float (vfma.f32).
• audio/level_multiplier:
  • S16 dual-halfword processing (arm_smulbb/arm_smultt + arm_pkhbt), fast S24/S32 scaling (arm_smmulr), and dual-issue float scaling.
• audio/pcm_converter:
  • S16 $\leftrightarrow$ S24 / S32 / Float format transformations with S24 sign-extension handling for S/PDIF SOF_IPC_FRAME_S24_4LE.
  • Direct dispatch tables for IPC3 (pcm_func_map) and IPC4 (pcm_func_vc_map).

4. Diagnostic & Automated Pre-Commit Verification Tools (scripts/)

• scripts/test_teensy_loopback.py: Automated pre-commit verification tool supporting S/PDIF (--interface spdif) and SAI1 I2S (--interface i2s) loopback testing with FFT spectrum analysis, SNR calculation, and frame drop detection.
• scripts/teensy_diag.py: Diagnostic tool decoding RT1062 S/PDIF (SCR, SRPC, STC, SRFM, SIS, SIE) and SAI1 registers.
• scripts/teensy_flash.py: HalfKay USB HID bootloader flashing tool with auto-detect and USB port targeting.

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Hardware Verification & Results

Verified on physical Teensy 4.1 hardware (Board A Master Tx $\to$ Board B Slave Rx over S/PDIF hardware transceiver):

================================================================================
 TEENSY 4.1 PRE-COMMIT HARDWARE LOOPBACK VERIFICATION REPORT
================================================================================
 Interface Mode:   S/PDIF Hardware Transceiver (Pin 14 ALT3 Tx -> Pin 15 ALT3 Rx)
 Playback Card:    hw:10,0 (Audio A / Master Tx)
 Capture Card:     hw:11,0 (Audio B / Slave Rx)
 Audio Parameters: 1000.0 Hz sine @ 48000 Hz, 16-bit Stereo, 4.0s duration
 SNR Acceptance:   >= 70.0 dB
--------------------------------------------------------------------------------
 Channel 0 (Left):  Peak=1000.0 Hz, Amplitude=28000, SNR=140.81 dB [PASS]
 Channel 1 (Right): Peak=1000.0 Hz, Amplitude=28000, SNR=140.81 dB [PASS]
 Dropped Frames:   0 (Continuous streaming verified)
--------------------------------------------------------------------------------
 OVERALL RESULT:    PASS (Achieved 140.81 dB >= 70.0 dB threshold)
================================================================================

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[lgirdwood]

@dbaluta ARM SIMD in here.

[dbaluta]

Thanks @lgirdwood will have a look!

[dbaluta]

@lgirdwood this looks very promising tested the ARM SIMD instructions on imx8mp with M7 core, looks like the load for simple volume pipeline decreased by at least 30%. Also, looking to borrow an RT to do some more testing.