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drm/msm/dpu: fix pipe ordering for source-split planes #1258

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drm/msm/dpu: fix pipe ordering for source-split planes #1258

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c20b5b3
FROMLIST: drm/msm/dpu: split modes a single layer mixer cannot clock
Oct 8, 2026
d1f71e6
FROMLIST: drm/msm/dpu: do not assume a merged datapath when validatin…
Oct 8, 2026
f6171e5
FROMLIST: drm/msm/dpu: check mode against PINGPONG or DSC max width
Oct 8, 2026
69b8d1a
FROMLIST: drm/msm/dpu: filter writeback modes using writeback maxline…
Oct 8, 2026
42245e3
BACKPORT: drm/msm/dpu: remove max_mixer_width from catalog
Oct 8, 2026
4aa596b
FROMLIST: drm/msm/dpu: limit the mode width to a pipe if the LM has n…
Oct 8, 2026
53c1a7a
FROMLIST: drm/msm/dpu: keep SSPP priority order for split planes on D…
Oct 10, 2026
95d8148
FROMLIST: drm/msm/dpu: add SSPP op to program the source split order
Oct 10, 2026
66cf8d6
FROMLIST: drm/msm/dpu: program the source split order for split planes
Oct 10, 2026
cffd975
FROMLIST: drm/msm/dpu: add source split order op for DPU 13.x
Oct 10, 2026
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1 change: 0 additions & 1 deletion drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
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#define _DPU_10_0_SM8650_H

static const struct dpu_caps sm8650_dpu_caps = {
.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0xb,
.has_src_split = true,
.has_dim_layer = true,
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1 change: 0 additions & 1 deletion drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h
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#define _DPU_12_0_SM8750_H

static const struct dpu_caps sm8750_dpu_caps = {
.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0xb,
.has_src_split = true,
.has_dim_layer = true,
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1 change: 0 additions & 1 deletion drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h
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#define _DPU_12_2_GLYMUR_H

static const struct dpu_caps glymur_dpu_caps = {
.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0xb,
.has_src_split = true,
.has_dim_layer = true,
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1 change: 0 additions & 1 deletion drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapali.h
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#define _DPU_13_0_KAANAPALI_H

static const struct dpu_caps kaanapali_dpu_caps = {
.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0xb,
.has_src_split = true,
.has_dim_layer = true,
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1 change: 0 additions & 1 deletion drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h
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#define _DPU_1_14_MSM8937_H

static const struct dpu_caps msm8937_dpu_caps = {
.max_mixer_width = DEFAULT_DPU_LINE_WIDTH,
.max_mixer_blendstages = 0x4,
.max_linewidth = DEFAULT_DPU_LINE_WIDTH,
.pixel_ram_size = 40 * 1024,
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1 change: 0 additions & 1 deletion drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h
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#define _DPU_1_14_MSM8917_H

static const struct dpu_caps msm8917_dpu_caps = {
.max_mixer_width = DEFAULT_DPU_LINE_WIDTH,
.max_mixer_blendstages = 0x4,
.max_linewidth = DEFAULT_DPU_LINE_WIDTH,
.pixel_ram_size = 16 * 1024,
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1 change: 0 additions & 1 deletion drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h
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#define _DPU_1_16_MSM8953_H

static const struct dpu_caps msm8953_dpu_caps = {
.max_mixer_width = DEFAULT_DPU_LINE_WIDTH,
.max_mixer_blendstages = 0x4,
.max_linewidth = DEFAULT_DPU_LINE_WIDTH,
.pixel_ram_size = 40 * 1024,
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1 change: 0 additions & 1 deletion drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h
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#define _DPU_1_7_MSM8996_H

static const struct dpu_caps msm8996_dpu_caps = {
.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0x7,
.has_src_split = true,
.max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
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1 change: 0 additions & 1 deletion drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
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#define _DPU_3_0_MSM8998_H

static const struct dpu_caps msm8998_dpu_caps = {
.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0x7,
.has_src_split = true,
.has_dim_layer = true,
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1 change: 0 additions & 1 deletion drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h
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#define _DPU_3_2_SDM660_H

static const struct dpu_caps sdm660_dpu_caps = {
.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0x7,
.has_src_split = true,
.has_dim_layer = true,
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1 change: 0 additions & 1 deletion drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h
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#define _DPU_3_3_SDM630_H

static const struct dpu_caps sdm630_dpu_caps = {
.max_mixer_width = DEFAULT_DPU_LINE_WIDTH,
.max_mixer_blendstages = 0x7,
.has_src_split = true,
.has_dim_layer = true,
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1 change: 0 additions & 1 deletion drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
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#define _DPU_4_0_SDM845_H

static const struct dpu_caps sdm845_dpu_caps = {
.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0xb,
.has_src_split = true,
.has_dim_layer = true,
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1 change: 0 additions & 1 deletion drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
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#define _DPU_5_0_SM8150_H

static const struct dpu_caps sm8150_dpu_caps = {
.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0xb,
.has_src_split = true,
.has_dim_layer = true,
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1 change: 0 additions & 1 deletion drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
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#define _DPU_5_1_SC8180X_H

static const struct dpu_caps sc8180x_dpu_caps = {
.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0xb,
.has_src_split = true,
.has_dim_layer = true,
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1 change: 0 additions & 1 deletion drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
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#define _DPU_5_2_SM7150_H

static const struct dpu_caps sm7150_dpu_caps = {
.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0xb,
.has_src_split = true,
.has_dim_layer = true,
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1 change: 0 additions & 1 deletion drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
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#define _DPU_5_3_SM6150_H

static const struct dpu_caps sm6150_dpu_caps = {
.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0x9,
.has_dim_layer = true,
.has_idle_pc = true,
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1 change: 0 additions & 1 deletion drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
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#define _DPU_5_4_SM6125_H

static const struct dpu_caps sm6125_dpu_caps = {
.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0x6,
.has_dim_layer = true,
.has_idle_pc = true,
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1 change: 0 additions & 1 deletion drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
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#define _DPU_6_0_SM8250_H

static const struct dpu_caps sm8250_dpu_caps = {
.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0xb,
.has_src_split = true,
.has_dim_layer = true,
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1 change: 0 additions & 1 deletion drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
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#define _DPU_6_2_SC7180_H

static const struct dpu_caps sc7180_dpu_caps = {
.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0x9,
.has_dim_layer = true,
.has_idle_pc = true,
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1 change: 0 additions & 1 deletion drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
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#define _DPU_6_3_SM6115_H

static const struct dpu_caps sm6115_dpu_caps = {
.max_mixer_width = DEFAULT_DPU_LINE_WIDTH,
.max_mixer_blendstages = 0x4,
.has_dim_layer = true,
.has_idle_pc = true,
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1 change: 0 additions & 1 deletion drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
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#define _DPU_6_4_SM6350_H

static const struct dpu_caps sm6350_dpu_caps = {
.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0x7,
.has_src_split = true,
.has_dim_layer = true,
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1 change: 0 additions & 1 deletion drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
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#define _DPU_6_5_QCM2290_H

static const struct dpu_caps qcm2290_dpu_caps = {
.max_mixer_width = DEFAULT_DPU_LINE_WIDTH,
.max_mixer_blendstages = 0x4,
.has_dim_layer = true,
.has_idle_pc = true,
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1 change: 0 additions & 1 deletion drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
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#define _DPU_6_9_SM6375_H

static const struct dpu_caps sm6375_dpu_caps = {
.max_mixer_width = DEFAULT_DPU_LINE_WIDTH,
.max_mixer_blendstages = 0x4,
.has_dim_layer = true,
.has_idle_pc = true,
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1 change: 0 additions & 1 deletion drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
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#define _DPU_7_0_SM8350_H

static const struct dpu_caps sm8350_dpu_caps = {
.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0xb,
.has_src_split = true,
.has_dim_layer = true,
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1 change: 0 additions & 1 deletion drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
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#define _DPU_7_2_SC7280_H

static const struct dpu_caps sc7280_dpu_caps = {
.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0x7,
.has_dim_layer = true,
.has_idle_pc = true,
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1 change: 0 additions & 1 deletion drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
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#define _DPU_8_0_SC8280XP_H

static const struct dpu_caps sc8280xp_dpu_caps = {
.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 11,
.has_src_split = true,
.has_dim_layer = true,
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1 change: 0 additions & 1 deletion drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
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#define _DPU_8_1_SM8450_H

static const struct dpu_caps sm8450_dpu_caps = {
.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0xb,
.has_src_split = true,
.has_dim_layer = true,
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1 change: 0 additions & 1 deletion drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
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#define _DPU_8_4_SA8775P_H

static const struct dpu_caps sa8775p_dpu_caps = {
.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0xb,
.has_src_split = true,
.has_dim_layer = true,
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1 change: 0 additions & 1 deletion drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
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#define _DPU_9_0_SM8550_H

static const struct dpu_caps sm8550_dpu_caps = {
.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0xb,
.has_src_split = true,
.has_dim_layer = true,
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1 change: 0 additions & 1 deletion drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
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#define _DPU_9_1_SAR2130P_H

static const struct dpu_caps sar2130p_dpu_caps = {
.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0xb,
.has_src_split = true,
.has_dim_layer = true,
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1 change: 0 additions & 1 deletion drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
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#define _DPU_9_2_X1E80100_H

static const struct dpu_caps x1e80100_dpu_caps = {
.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0xb,
.has_src_split = true,
.has_dim_layer = true,
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