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drm/msm: Add Adreno GPU support for Mahua, Hawi and Maili - #2011

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drm/msm: Add Adreno GPU support for Mahua, Hawi and Maili#2011
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@kavishah27 kavishah27 commented Oct 9, 2026 •
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This series brings up the Adreno GPU/GMU on three new SoCs:

  • Mahua: Adreno X2-85, which shares its underlying HW IP with Glymur's
    Adreno X2-90. Includes a fix for Glymur's GMU compatible string, which
    was needed as a prerequisite before X2-85 could reuse the family
    detection logic correctly.
  • Hawi: Adreno 850, the next generation A8x GPU, adding a new Matrix ALU
    (MALU) block, a dedicated Bx power rail, and a GMU GDSC powered by MxG.
  • Maili: Adreno 845, closely related to the Hawi A850 but without the
    MALU unit.

Hawi and Maili also require several a6xx GMU dependency-vote fixes:
honoring the perfmode_bw threshold on A8x, correcting the secondary rail
vote in ARC votes, fixing RPMH dependency votes, factoring out the RPMh
arc-vote helpers for reuse, adding Bx rail support to GMU dependency
votes, clamping the MX dependency vote, and sending THINMEM config to
the GMU for A850.

CRs-fixed: 4704803

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qcomlnxci requested review from a team and Rajesh Kemisetti (quic-rajeshk) and removed request for a team October 9, 2026 13:12
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qcomlnxci requested a review from a team October 9, 2026 13:21
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CR: 4704803
Change Task: kernel.qli.0.0
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CR: 4704803
Change Task: kernel.qli.0.0
Error: GenAI Assisted field must be set before moving change tasks to Development Complete. Please provide GenAI information.

The change task for this CR could not be moved to Dev Complete because of the error above. Please resolve the issue in Orbit and re-run the failed Orbit check.

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Dev Completion validation failed

CR: 4704803
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Dev Completion validation failed

CR: 4704803
Change Task: kernel.qli.0.0
Error: Failed to validate change task completion. Status code: NotFound

The change task for this CR could not be moved to Dev Complete because of the error above. Please resolve the issue in Orbit and re-run the failed Orbit check.

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Dev Completion validation failed

CR: 4704803
Change Task: kernel.qli.0.0
Error: Failed to validate change task completion. Status code: NotFound

The change task for this CR could not be moved to Dev Complete because of the error above. Please resolve the issue in Orbit and re-run the failed Orbit check.

Jie Zhang and others added 13 commits October 9, 2026 21:04
Jie Zhang @kavishah27
FROMLIST: dt-bindings: display/msm/gmu: Fix Glymur's compatible
7ea4fd8 
The Glymur GMU compatible string was incorrectly documented as
qcom,adreno-gmu-x285.1. Fix it to use the correct string
qcom,adreno-gmu-x290.1.

Fixes: 7bc29d5 ("dt-bindings: display/msm/gmu: Add Adreno X2-85 GMU")
Signed-off-by: Jie Zhang <jie.zhang@oss.qualcomm.com>
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Signed-off-by: Kavisha Shah <kavishah@qti.qualcomm.com>
Link: https://lore.kernel.org/lkml/20260925-mahua-gpu-v1-1-0fa0bfd8d315@oss.qualcomm.com/
Jie Zhang @kavishah27
FROMLIST: drm/msm/a8xx: Add Mahua GPU support
f2e0341 
Add support for Mahua's Adreno X2-85 GPU, which shares the same
underlying HW IP with Glymur's Adreno X2-90 GPU. Rework
adreno_is_x285() as adreno_is_x285_family() since it doesn't
uniquely identify a single chip id anymore.

Signed-off-by: Jie Zhang <jie.zhang@oss.qualcomm.com>
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Signed-off-by: Kavisha Shah <kavishah@qti.qualcomm.com>
Link: https://lore.kernel.org/lkml/20260925-mahua-gpu-v1-3-0fa0bfd8d315@oss.qualcomm.com/
Jie Zhang @kavishah27
FROMLIST: dt-bindings: display/msm: gpu: Document Mahua GPU/GMU
f886be4 
Adreno X2-85 GPU found in mahua SoC belongs to the A8x family and
is a smaller variant of X2-90 with fewer slices and smaller internal
memories. Update the dt bindings documentation to describe this GPU
along with it's GMU.

Signed-off-by: Jie Zhang <jie.zhang@oss.qualcomm.com>
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Signed-off-by: Kavisha Shah <kavishah@qti.qualcomm.com>
Link: https://lore.kernel.org/lkml/20260925-mahua-gpu-v1-4-0fa0bfd8d315@oss.qualcomm.com/
@akhilpo-qcom @kavishah27
FROMLIST: drm/msm/a6xx: Honor perfmode_bw threshold on A8x
c3dd360 
Instead of voting ACV for all bw corners for A8x GPU, restrict it to BW
votes above the perfmode_bw threshold, similar to the A7x GPUs.

Fixes: 288a932 ("drm/msm/adreno: Introduce A8x GPU Support")
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Signed-off-by: Kavisha Shah <kavishah@qti.qualcomm.com>
Link: https://lore.kernel.org/lkml/20260923-hawi-gpu-v1-1-0c3c79a1a470@oss.qualcomm.com/
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
@akhilpo-qcom @kavishah27
FROMLIST: drm/msm/a6xx: Fix secondary rail vote in ARC votes
fce4fbf 
Using the requested level can pick a secondary corner lower than the one
required to support the chosen primary corner, under-voting the
dependent rail. To fix this, match against the selected primary voltage
instead.

Fixes: 4b565ca ("drm/msm: Add A6XX device support")
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Signed-off-by: Kavisha Shah <kavishah@qti.qualcomm.com>
Link: https://lore.kernel.org/lkml/20260923-hawi-gpu-v1-2-0c3c79a1a470@oss.qualcomm.com/
@akhilpo-qcom @kavishah27
FROMLIST: drm/msm/a6xx: Fix RPMH dependency votes
64434b2 
a6xx_gmu_rpmh_dep_votes_init() iterates the GPU frequency list
(gmu->gpu_freqs) but was passed gmu->dev to resolve each frequency to an
arc level. This results in generation of incorrect dependency votes
table. To fix this, pass gpu->pdev->dev, which owns the GPU OPP table.

Also, reorder the dependency vote init to improve clarity.

Fixes: 06cfbca ("drm/msm/a6xx: Share dependency vote table with GMU")
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Signed-off-by: Kavisha Shah <kavishah@qti.qualcomm.com>
Link: https://lore.kernel.org/lkml/20260923-hawi-gpu-v1-3-0c3c79a1a470@oss.qualcomm.com/
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
@akhilpo-qcom @kavishah27
FROMLIST: drm/msm/a6xx: Factor out RPMh arc-vote helpers
6485ee5 
The GMU RPMh vote construction repeats two patterns across
a6xx_gmu_rpmh_arc_votes_init() and a6xx_gmu_rpmh_dep_votes_init():
reading a cmd-db aux-data resource (with the same "halve the byte count
and reject empty" handling), and scanning an arc level array for the
first corner that satisfies a target level.

Refactor out a6xx_gmu_rpmh_read_arc() and a6xx_gmu_rpmh_arc_index() to
reduce code duplication and improve code readability.

Assisted-by: LLM
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Signed-off-by: Kavisha Shah <kavishah@qti.qualcomm.com>
Link: https://lore.kernel.org/lkml/20260923-hawi-gpu-v1-4-0c3c79a1a470@oss.qualcomm.com/
@akhilpo-qcom @kavishah27
FROMLIST: drm/msm/a6xx: Add BX rail support to GMU dependency votes
375f5ba 
Some A8x targets have a third memory rail (BX) in addition to GX and MX.
On these targets the GMU dependency vote carries a per-corner BX vote in
bits 25:20, which otherwise default to all-ones (no BX constraint).
Prepare BX vote field to pass this new voltage recommendation to GMU.

Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Signed-off-by: Kavisha Shah <kavishah@qti.qualcomm.com>
Link: https://lore.kernel.org/lkml/20260923-hawi-gpu-v1-5-0c3c79a1a470@oss.qualcomm.com/
@akhilpo-qcom @kavishah27
FROMLIST: drm/msm/a6xx: Clamp MX dependency vote
e08c126 
In some chipsets like Hawi, the GPU arc level can exceed the highest
available MX corner. In that case, use the highest non-zero MX vote instead
of failing GMU initialization.

Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Signed-off-by: Kavisha Shah <kavishah@qti.qualcomm.com>
Link: https://lore.kernel.org/lkml/20260923-hawi-gpu-v1-6-0c3c79a1a470@oss.qualcomm.com/
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Wangao Wang @kavishah27
FROMLIST: soc: qcom: ubwc: Add configuration for Hawi
8c6c6a4 
Add UBWC configuration data for the Hawi platform, which uses UBWC 7.0
and enables the required flags and highest bank bit settings.

This allows drivers to query the correct UBWC capabilities on Hawi.

Also add UBWC 7.0 support to the version tag helper so that
qcom_ubwc_version_tag() returns the correct tag for UBWC 7.0.

Signed-off-by: Wangao Wang <wangao.wang@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/lkml/20260812-ubwc_for_hawi_maili-v1-1-c29edecb3bd8@oss.qualcomm.com/
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Kavisha Shah <kavishah@qti.qualcomm.com>
@akhilpo-qcom @kavishah27
FROMLIST: drm/msm/a8xx: Add Adreno 850 support
edbbc60 
Adreno 850 is the next generation of A8x GPU present in Hawi SoC. It shares
the ADRENO_8XX_GEN2 family and slice architecture with A840, but has many
architectural improvements. There is a new block Matrix ALU (MALU) which
helps to accelerate certain compute workloads. Also, there is a new Bx rail
that powers a part of the GPU IP. GMU is now powered by a dedicated GDSC
powered by MxG rail.

Add a new catalog entry along with the necessary register lists and
additional changes to support the aforementioned new features.

Hawi SoC support UBWC v7.0, but GPU is unaffected by this upgrade.

Assisted-by: LLM
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Signed-off-by: Kavisha Shah <kavishah@qti.qualcomm.com>
Link: https://lore.kernel.org/lkml/20260923-hawi-gpu-v1-7-0c3c79a1a470@oss.qualcomm.com/
@akhilpo-qcom @kavishah27
FROMLIST: drm/msm/a6xx: Send THINMEM config to GMU for A850
8800df0 
Add HFI support for the GMU THINMEM_CFG feature and provide the
configuration value used by the Adreno 850 GPU in the catalog.

Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Signed-off-by: Kavisha Shah <kavishah@qti.qualcomm.com>
Link: https://lore.kernel.org/lkml/20260923-hawi-gpu-v1-8-0c3c79a1a470@oss.qualcomm.com/
@bvalluru12 @kavishah27
FROMLIST: drm/msm/a8xx: Add Adreno 845 support
7fb201e 
Adreno 845 GPU is present in the Maili SoC. It is very similar to Hawi GPU
(A850), except that it doesn't have a MALU unit. Add the necessary
register lists and a catalog entry to support this GPU.

Signed-off-by: Bhaskar Reddy Valluru <bvalluru@qti.qualcomm.com>
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Signed-off-by: Kavisha Shah <kavishah@qti.qualcomm.com>
Link: https://lore.kernel.org/lkml/20260923-hawi-gpu-v1-9-0c3c79a1a470@oss.qualcomm.com/
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Dev Completion validation failed

CR: 4704803
Change Task: kernel.qli.0.0
Error: Failed to validate change task completion. Status code: NotFound

The change task for this CR could not be moved to Dev Complete because of the error above. Please resolve the issue in Orbit and re-run the failed Orbit check.

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