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[hardware] 🐛 Use SEW bits of rs1 in widening .vx/.wx instructions - #514
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The lanes replicate the scalar operand at the instruction's vtype.vsew, which is 2*SEW for widening operations, and the ZExt2/SExt2 conversion applies only to vector operands, so rs1 bits above SEW leaked into the result. Extend rs1[SEW-1:0] in the dispatcher the way vs1 would be. Fixes pulp-platform#505 Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com> Signed-off-by: David Harris <David_Harris@hmc.edu>
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Fixes #505. Widening
.vx/.wxinstructions now use only the low SEW bits of rs1, zero- or sign-extended like a vs1 element. The lanes replicatescalar_opatvtype.vsew, which is 2*SEW for widening operations, and theOpQueueConversionZExt2/SExt2conversion applies only to vector operands, so the dispatcher extends rs1 itself.Verification (Verilator, NrLanes=4, VLEN=512): 30 cases at SEW 8/16/32 (
vwadd[u],vwsubu,vwmul[u/su],vwmacc[u/su/us].vx,vwaddu.wx) with rs1 bits above SEW set, checked against the RVV 1.0 definitions: 30 wrong on main, all correct with this change.Changelog
Fixed
.vx/.wxinstructions (Widening .vx/.wx instructions use rs1 bits above SEW #505)Checklist