[davidharrishmc]

Caution

This pull request was generated by an AI assistant (Claude Code) and has not been reviewed by a human. Please review it with that in mind.

Fixes #511. The dispatcher no longer applies the LMUL alignment check to operands that are always one register: the mask destination of integer and floating-point compares, vmadc and vmsbc; the mask operands of vmand.mm..vmxnor.mm and vmsbf/vmsif/vmsof.m; the vs2 of viota.m; vlm.v/vsm.v (EMUL = 1); and the vd/vs1 of single-width integer and floating-point reductions. The vmadc/vmsbc-specific check, which rejected vd equal to a source register and (at LMUL >= 2) non-overlapping registers, is replaced by the RVV 1.0 rule for every mask-producing instruction: vd may overlap a source group only at its lowest-numbered register. That rule keeps reserved overlaps such as vmseq.vv v5, v4, v6 at LMUL=2 illegal, which today only trap as a side effect of the alignment check.

Widening integer reductions are left to #478, which restructures the same OPIVV check, so the two will need a small rebase against each other.

Verification (Verilator, NrLanes=4, VLEN=512): a directed M-mode probe of 25 instructions. On main all 19 legal cases trap; with this change none do, the reserved cases (vredsum.vs v22, v19, v1, vmadc.vv v5, v4, v6, vmseq.vv v5, v4, v6, vmseq.vx v3, v2, a0, vmfeq.vv v5, v4, v6 at LMUL=2) still trap, and vmadc.vi v12, v12, -14 gives the expected carry mask. vwredsum.vs with an odd vd still traps until #478.

Changelog

Fixed

• Do not check LMUL alignment of operands that are one register, and let a mask destination overlap the lowest register of a source group, including for vmadc/vmsbc (Legal instructions with single-register operands (mask destinations, mask operands, vlm/vsm, reduction scalars) raise illegal instruction #511)

Checklist

• Automated tests pass (Ara's own test suite was not run; see Verification)
• Changelog updated
• Code style guideline is observed

[davidharrishmc]

Added 9277c04: forcing EMUL = 1 for vlm.v/vsm.v made the EMUL range check compare it with a fractional LMUL, so vlm.v at e16 mf4/mf2 raised illegal instruction (stock main runs it correctly). The check is now skipped for vlm.v/vsm.v. With it those loads match Spike, the #511 reproducer still passes all 25 checks, and the other probes that pass on main still pass.