Dev/bypass

.gitlab-ci.yml

@@ -173,6 +173,7 @@ test:
           - rlc-multi_producer_single_consumer_double_linked_list_M1_N1350_K10
           - rlc-multi_producer_single_consumer_double_linked_list_M1_N1350_K4_P2_C2_am_G1024_tbchk
           - rlc-multi_producer_single_consumer_double_linked_list_P1_C3_ul_ci
+          - l1-bypass
   script:
     # The vsim script writes a .rtlbinary marker here; monitor logs need the
     # core/noc/others subfolders. Build artifacts exclude sim/bin/logs/, so
@@ -207,6 +208,7 @@ test-dual:
           - gemv_M512_N128_K32
           - fmatmul-32b_M64_N64_K64
           - fft-32b_M1024_N16
+          - l1-bypass
   script:
     - mkdir -p sim/bin/logs sim/bin/logs/core sim/bin/logs/noc sim/bin/logs/others
     - chmod +x sim/bin/cachepool_cluster.vsim

Bender.lock

@@ -109,7 +109,7 @@ packages:
     - obi
     - register_interface
   insitu-cache:
-    revision: d7a526ebc965c3c9808f348b377d06f4479cc4ab
+    revision: a407d39c832aa514551d1d153d93b60bb5d3a6e5
     version: null
     source:
       Git: https://github.com/pulp-platform/Insitu-Cache.git

Bender.yml

@@ -26,6 +26,7 @@ export_include_dirs:
 
 sources:
   # Level 0
+  - hardware/src/cachepool_reqrsp_to_axi.sv
   - hardware/src/reqrsp_to_reg.sv
   - hardware/src/reqrsp_xbar.sv
   - hardware/src/tcdm_cache_interco.sv

config/README.md

@@ -108,13 +108,13 @@ subset; the "Define" column gives the SystemVerilog macro the `Makefile` emits
 | `addr_width` | `32` | `ADDR_WIDTH` | Core address width |
 | `bootrom_data_width` | `32` | — | Bootrom word width (used by `generate_bootrom.py`) |
 | `num_barrier_slots` | `2` | `NUM_BARRIER_SLOTS` | Independent hardware barrier slots |
-| `dram_type` | `HBM2` | `DRAM_TYPE` | DRAMSys model. One of `DDR3`, `DDR4`, `LPDDR4`, `HBM2`. Also sets the default `refill_data_width` |
+| `dram_type` | `HBM2` | `DRAM_TYPE` | DRAMSys model. One of `DDR3`, `DDR4`, `LPDDR4`, `HBM2` |
 
 ### Tile and L1 data cache
 
 | Parameter | Default | Define | Description |
 | --- | --- | --- | --- |
-| `refill_data_width` | auto from `dram_type` | `REFILL_DATA_WIDTH` | Refill interconnect data width. Default is 512 (HBM2), 256 (LPDDR4), 128 (otherwise) |
+| `refill_data_width` | 512 | `REFILL_DATA_WIDTH` | Refill interconnect data width. Must equal `l1d_cacheline_width`: refills are single beats (checked in `cachepool_cluster.sv`) |
 | `l1d_cacheline_width` | `512` | `L1D_CACHELINE_WIDTH` | Cache line width in bits |
 | `l1d_bank_factor` | `1` | — | Banks per core (derives `l1d_num_banks`) |
 | `l1d_coal_window` | `2` | `L1D_COAL_WINDOW` | Coalescing window of the request coalescer |

config/cachepool_4g.mk

@@ -91,7 +91,7 @@ snitch_max_trans ?= 16
 #####################
 ##  L2 Main Memory ##
 #####################
-# DRAM type (selects DRAMSys config and sets default refill_data_width)
+# DRAM type (selects DRAMSys config)
 dram_type ?= HBM2
 
 # L2 number of channels

config/cachepool_dual_4g.mk

@@ -97,7 +97,7 @@ num_barrier_slots ?= 4
 #####################
 ##  L2 Main Memory ##
 #####################
-# DRAM type (selects DRAMSys config and sets default refill_data_width)
+# DRAM type (selects DRAMSys config)
 dram_type ?= HBM2
 
 # L2 number of channels

config/cachepool_dual_fpu_16g.mk

@@ -97,7 +97,7 @@ num_barrier_slots ?= 4
 #####################
 ##  L2 Main Memory ##
 #####################
-# DRAM type (selects DRAMSys config and sets default refill_data_width)
+# DRAM type (selects DRAMSys config)
 dram_type ?= HBM2
 
 # L2 number of channels

config/cachepool_dual_fpu_4g.mk

@@ -97,7 +97,7 @@ num_barrier_slots ?= 4
 #####################
 ##  L2 Main Memory ##
 #####################
-# DRAM type (selects DRAMSys config and sets default refill_data_width)
+# DRAM type (selects DRAMSys config)
 dram_type ?= HBM2
 
 # L2 number of channels

config/cachepool_fpu_16g.mk

@@ -91,7 +91,7 @@ snitch_max_trans ?= 16
 #####################
 ##  L2 Main Memory ##
 #####################
-# DRAM type (selects DRAMSys config and sets default refill_data_width)
+# DRAM type (selects DRAMSys config)
 dram_type ?= HBM2
 
 # L2 number of channels

config/cachepool_fpu_16g_tiny.mk

@@ -91,7 +91,7 @@ snitch_max_trans ?= 16
 #####################
 ##  L2 Main Memory ##
 #####################
-# DRAM type (selects DRAMSys config and sets default refill_data_width)
+# DRAM type (selects DRAMSys config)
 dram_type ?= HBM2
 
 # L2 number of channels

config/cachepool_fpu_4g.mk

@@ -91,7 +91,7 @@ snitch_max_trans ?= 16
 #####################
 ##  L2 Main Memory ##
 #####################
-# DRAM type (selects DRAMSys config and sets default refill_data_width)
+# DRAM type (selects DRAMSys config)
 dram_type ?= HBM2
 
 # L2 number of channels

config/config.mk

@@ -26,20 +26,14 @@ include $(CACHEPOOL_DIR)/config/$(config).mk
 ##  DRAM Type       ##
 #####################
 
-# DRAM type used by DRAMSys and to auto-set refill_data_width.
+# DRAM type used by DRAMSys.
 # Supported values: DDR3, DDR4, LPDDR4, HBM2
 dram_type ?= HBM2
 
-# Auto-derive default refill data width from dram_type.
-# HBM variants: 512b (3600*16/1000 = 57.6B/cyc)
-# DDR variants: 128b (1866*8/1000 = 15B/cyc)
-ifeq ($(dram_type),HBM2)
-  refill_data_width_default := 512
-else ifeq ($(dram_type),LPDDR4)
-  refill_data_width_default := 256
-else
-  refill_data_width_default := 128
-endif
+# Refill data width: always one full 512b cache line per beat. The DRAM converters send
+# single beats only, and the L1 bypass path packs data + routing info into one beat.
+# DDR variants waste part of the width (1866*8/1000 = 15B/cyc of real bandwidth).
+refill_data_width_default := 512
 
 #########################
 ##  CachePool Cluster  ##
@@ -149,16 +143,16 @@ num_barrier_slots ?= 2
 # in cachepool_cluster.sv, and the cluster zero-extends refill_user_t onto the
 # (wider) AXI user port at the reqrsp_to_axi call site.
 #
-#   refill_user_t = bank_id(BankIDWidth) + tile_id(TileIDWidth)
-#                 + cache_info_t + burst_req_t
+#   refill_user_t = bypass(1) + bank_id(BankIDWidth) + tile_id(TileIDWidth)
+#                 + l2_src_id + cache_info_t + burst_req_t
 #   cache_info_t  = {for_write_pend, depth, way}   -- NOTE: NO tile_id inside.
 #
 # BankIDWidth depends only on cores-per-tile (constant across a tile-count
 # sweep with num_cores_per_tile fixed), not on the total tile count. So the
 # only tile-count-dependent term in refill_user_t is TileIDWidth =
 # clog2(NumTiles), and that's already added exactly once, downstream, by
 # cachepool_pkg.sv (SpatzAxiUserWidth = AXI_USER_WIDTH + clog2(NumTiles) +
-# bits(l2_id_t)) -- no need to also grow axi_user_width with NumTiles here.
+# bits(l2_id_t) + 1 for bypass) -- no need to also grow axi_user_width with NumTiles here.
 #
 # axi_user_base below is the width needed at NumTiles=1 (TileIDWidth=0),
 # i.e. bank_id + cache_info_t + burst_req_t only.

hardware/cachepool_peripheral/cachepool_peripheral.sv

@@ -129,6 +129,7 @@ module cachepool_peripheral
   assign reg_cfg.private_addr = reg2hw.l1d_addr.q;
   assign reg_cfg.xbar_offset  = reg2hw.xbar_offset.q;
   assign reg_cfg.prefetch_en  = reg2hw.icache_prefetch_enable.q;
+  assign reg_cfg.bypass_en    = reg2hw.l1d_bypass.q;
 
   // Committed settings, the copy every group-level register holds once a batch is done
   l1d_cfg_t            cfg_d,      cfg_q;
@@ -143,13 +144,14 @@ module cachepool_peripheral
 
   // A setting differing from its committed copy is a pending update; only the L1D instruction
   // waits for an explicit commit
-  logic l1d_insn_commit, xbar_update, private_update, addr_update, prefetch_update;
+  logic l1d_insn_commit, xbar_update, private_update, addr_update, prefetch_update, bypass_update;
 
   assign l1d_insn_commit = reg2hw.l1d_insn_commit.q;
   assign xbar_update     = (reg_cfg.xbar_offset  != cfg_q.xbar_offset);
   assign private_update  = (reg_cfg.l1d_private  != cfg_q.l1d_private);
   assign addr_update     = (reg_cfg.private_addr != cfg_q.private_addr);
   assign prefetch_update = (reg_cfg.prefetch_en  != cfg_q.prefetch_en);
+  assign bypass_update   = (reg_cfg.bypass_en    != cfg_q.bypass_en);
 
   // A batch carries one register and is only started while no batch is in flight; anything
   // else stays pending until the previous batch is done. INSN first.
@@ -208,6 +210,13 @@ module cachepool_peripheral
       data_d[0]         = reg_cfg.prefetch_en;
       busy_d            = 1'b1;
       start_d           = 1'b1;
+    end else if (bypass_update) begin
+      cfg_d.bypass_en   = reg_cfg.bypass_en;
+      reg_d             = GroupCfgL1dBypass;
+      data_d            = '0;
+      data_d[0]         = reg_cfg.bypass_en;
+      busy_d            = 1'b1;
+      start_d           = 1'b1;
     end
   end
 
@@ -229,7 +238,7 @@ module cachepool_peripheral
   // Busy from the cycle a commit or a changed setting is visible, so a status read right behind
   // the write never sees idle before the batch has started.
   assign hw2reg.l1d_flush_status.d = busy_q | l1d_insn_commit | xbar_update | private_update |
-                                     addr_update | prefetch_update;
+                                     addr_update | prefetch_update | bypass_update;
 
   // One 32-bit register per barrier slot; single register is enough at
   // group granularity (max 32 groups).

hardware/cachepool_peripheral/cachepool_peripheral_reg.hjson.tmpl

@@ -266,6 +266,20 @@
             desc: "Starting address of Private L1D Partition"
         }]
     },
+    {
+        name: "L1D_BYPASS",
+        desc: '''L1D bypass: requests from L1D_ADDR up (below the stack) skip the L1 data cache.
+                 Applied when the value changes, no commit needed; L1D_FLUSH_STATUS is busy until
+                 every group has applied it. '''
+        swaccess: "rw",
+        hwaccess: "hro",
+        resval: "0",
+        fields: [{
+            bits: "0:0",
+            name: "EN",
+            desc: "1: the private range (L1D_ADDR up to the stack) bypasses the L1D and goes to DRAM"
+        }]
+    },
     {
         name: "XBAR_OFFSET",
         desc: '''Cache xbar offset setting. Applied when the value changes, no commit

hardware/cachepool_peripheral/cachepool_peripheral_reg_pkg.sv

@@ -86,6 +86,10 @@
     logic [31:0] q;
   } cachepool_peripheral_reg2hw_l1d_addr_reg_t;
 
+  typedef struct packed {
+    logic        q;
+  } cachepool_peripheral_reg2hw_l1d_bypass_reg_t;
+
   typedef struct packed {
     logic [4:0]  q;
   } cachepool_peripheral_reg2hw_xbar_offset_reg_t;
@@ -118,22 +122,23 @@
 
   // Register -> HW type
   typedef struct packed {
-    cachepool_peripheral_reg2hw_hw_barrier_reg_t hw_barrier; // [348:317]
-    cachepool_peripheral_reg2hw_spatz_lock_acquire_reg_t spatz_lock_acquire; // [316:285]
-    cachepool_peripheral_reg2hw_spatz_lock_release_reg_t spatz_lock_release; // [284:253]
-    cachepool_peripheral_reg2hw_icache_prefetch_enable_reg_t icache_prefetch_enable; // [252:252]
-    cachepool_peripheral_reg2hw_spatz_status_reg_t spatz_status; // [251:251]
-    cachepool_peripheral_reg2hw_spatz_cycle_reg_t spatz_cycle; // [250:219]
-    cachepool_peripheral_reg2hw_cluster_boot_control_reg_t cluster_boot_control; // [218:187]
-    cachepool_peripheral_reg2hw_cluster_eoc_exit_reg_t cluster_eoc_exit; // [186:183]
-    cachepool_peripheral_reg2hw_cfg_l1d_spm_reg_t cfg_l1d_spm; // [182:173]
-    cachepool_peripheral_reg2hw_cfg_l1d_insn_reg_t cfg_l1d_insn; // [172:171]
-    cachepool_peripheral_reg2hw_cfg_l1d_tile_sel_mreg_t [1:0] cfg_l1d_tile_sel; // [170:107]
-    cachepool_peripheral_reg2hw_hw_barrier_participation_mask_mreg_t [1:0] hw_barrier_participation_mask; // [106:43]
-    cachepool_peripheral_reg2hw_l1d_spm_commit_reg_t l1d_spm_commit; // [42:42]
-    cachepool_peripheral_reg2hw_l1d_insn_commit_reg_t l1d_insn_commit; // [41:41]
-    cachepool_peripheral_reg2hw_l1d_private_reg_t l1d_private; // [40:37]
-    cachepool_peripheral_reg2hw_l1d_addr_reg_t l1d_addr; // [36:5]
+    cachepool_peripheral_reg2hw_hw_barrier_reg_t hw_barrier; // [349:318]
+    cachepool_peripheral_reg2hw_spatz_lock_acquire_reg_t spatz_lock_acquire; // [317:286]
+    cachepool_peripheral_reg2hw_spatz_lock_release_reg_t spatz_lock_release; // [285:254]
+    cachepool_peripheral_reg2hw_icache_prefetch_enable_reg_t icache_prefetch_enable; // [253:253]
+    cachepool_peripheral_reg2hw_spatz_status_reg_t spatz_status; // [252:252]
+    cachepool_peripheral_reg2hw_spatz_cycle_reg_t spatz_cycle; // [251:220]
+    cachepool_peripheral_reg2hw_cluster_boot_control_reg_t cluster_boot_control; // [219:188]
+    cachepool_peripheral_reg2hw_cluster_eoc_exit_reg_t cluster_eoc_exit; // [187:184]
+    cachepool_peripheral_reg2hw_cfg_l1d_spm_reg_t cfg_l1d_spm; // [183:174]
+    cachepool_peripheral_reg2hw_cfg_l1d_insn_reg_t cfg_l1d_insn; // [173:172]
+    cachepool_peripheral_reg2hw_cfg_l1d_tile_sel_mreg_t [1:0] cfg_l1d_tile_sel; // [171:108]
+    cachepool_peripheral_reg2hw_hw_barrier_participation_mask_mreg_t [1:0] hw_barrier_participation_mask; // [107:44]
+    cachepool_peripheral_reg2hw_l1d_spm_commit_reg_t l1d_spm_commit; // [43:43]
+    cachepool_peripheral_reg2hw_l1d_insn_commit_reg_t l1d_insn_commit; // [42:42]
+    cachepool_peripheral_reg2hw_l1d_private_reg_t l1d_private; // [41:38]
+    cachepool_peripheral_reg2hw_l1d_addr_reg_t l1d_addr; // [37:6]
+    cachepool_peripheral_reg2hw_l1d_bypass_reg_t l1d_bypass; // [5:5]
     cachepool_peripheral_reg2hw_xbar_offset_reg_t xbar_offset; // [4:0]
   } cachepool_peripheral_reg2hw_t;
 
@@ -167,7 +172,8 @@
   parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_L1D_FLUSH_STATUS_OFFSET = 7'h 40;
   parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_L1D_PRIVATE_OFFSET = 7'h 44;
   parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_L1D_ADDR_OFFSET = 7'h 48;
-  parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_XBAR_OFFSET_OFFSET = 7'h 4c;
+  parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_L1D_BYPASS_OFFSET = 7'h 4c;
+  parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_XBAR_OFFSET_OFFSET = 7'h 50;
 
   // Reset values for hwext registers and their fields
   parameter logic [31:0] CACHEPOOL_PERIPHERAL_HW_BARRIER_RESVAL = 32'h 0;
@@ -197,11 +203,12 @@
     CACHEPOOL_PERIPHERAL_L1D_FLUSH_STATUS,
     CACHEPOOL_PERIPHERAL_L1D_PRIVATE,
     CACHEPOOL_PERIPHERAL_L1D_ADDR,
+    CACHEPOOL_PERIPHERAL_L1D_BYPASS,
     CACHEPOOL_PERIPHERAL_XBAR_OFFSET
   } cachepool_peripheral_id_e;
 
   // Register width information to check illegal writes
-  parameter logic [3:0] CACHEPOOL_PERIPHERAL_PERMIT [20] = '{
+  parameter logic [3:0] CACHEPOOL_PERIPHERAL_PERMIT [21] = '{
     4'b 1111, // index[ 0] CACHEPOOL_PERIPHERAL_HW_BARRIER
     4'b 1111, // index[ 1] CACHEPOOL_PERIPHERAL_SPATZ_LOCK_ACQUIRE
     4'b 1111, // index[ 2] CACHEPOOL_PERIPHERAL_SPATZ_LOCK_RELEASE
@@ -221,7 +228,8 @@
     4'b 0001, // index[16] CACHEPOOL_PERIPHERAL_L1D_FLUSH_STATUS
     4'b 0001, // index[17] CACHEPOOL_PERIPHERAL_L1D_PRIVATE
     4'b 1111, // index[18] CACHEPOOL_PERIPHERAL_L1D_ADDR
-    4'b 0001  // index[19] CACHEPOOL_PERIPHERAL_XBAR_OFFSET
+    4'b 0001, // index[19] CACHEPOOL_PERIPHERAL_L1D_BYPASS
+    4'b 0001  // index[20] CACHEPOOL_PERIPHERAL_XBAR_OFFSET
   };
 
 endpackage