[DiyouS]

Hierarchical peripheral configuration and a narrow peripheral mesh

• Problem: the cluster peripheral drove the group config over wires that bypass the mesh, and all peripheral, UART and bootrom traffic squeezed through reqrsp_w2n_converter.
• Two-level configuration: cores program the cluster MMR, and the sender writes a group-level register block in each group in turn. Only the cache instruction keeps a commit register; the other settings apply when written, and XBAR_OFFSET_COMMIT is removed.
• Narrow mesh: a second independent mesh, built from stock floo_router and floo_tcdm_chimney, carries peripheral/UART accesses and config writes. The fields used to route responses back are compact, the tile and group muxes are reqrsp_xbar, and the wide mesh now carries
  requests one way only.
• Bootrom: as wide as the L2 refill, using lla; the converter is no longer used.
• Software: a fence before the end-of-computation write; header, library and READMEs updated.
• Checks and testing: assertions for unmapped addresses, AMOs, multi-word accesses and tied-off ports. The CI lists pass on fpu_4g, dual_fpu_4g, fpu_16g and dual_fpu_16g with performance within noise.

[Copilot]

🟡 Changes recommended

BootROM timing and shared register-bridge flow control can return stale data or lose responses.

2 open issues

• reqrsp_to_reg drops responses under backpressure · New
• Back-to-back BootROM refills can return stale data · New

What changed in this PR

Moves cluster configuration and peripheral traffic onto a dedicated narrow mesh, separating them from wide cache-refill traffic.

Changes:

• Adds group-level configuration registers and mesh-based distribution.
• Separates CSR/UART traffic and widens BootROM access to match refills.
• Updates runtime synchronization, register definitions, and build configuration.

File	Description
util/​scripts/​generate_bootrom.py	Aligns ROM contents to word width.
software/​snRuntime/​src/​platforms/​standalone/​start_snitch.S	Fences before end-of-computation writes.
software/​snRuntime/​src/​l1cache.c	Updates configuration ordering and completion waits.
software/​snRuntime/​README.md	Documents configuration completion semantics.
software/​snRuntime/​include/​l1cache.h	Removes obsolete crossbar commit API.
software/​snRuntime/​include/​cachepool_peripheral.h	Updates register offsets and barrier slots.
README.md	Describes hierarchical configuration.
Makefile	Exports configuration and BootROM parameters.
hardware/​src/​cachepool_tile.sv	Adds narrow hart routing and local tile selection.
hardware/​src/​cachepool_pkg.sv	Defines configuration registers and narrow-mesh types.
hardware/​src/​cachepool_group.sv	Separates peripheral traffic from refills.
hardware/​src/​cachepool_group_noc_wrapper.sv	Integrates narrow routers and group configuration.
hardware/​src/​cachepool_group_cfg.sv	Implements group configuration and flush completion.
hardware/​src/​cachepool_group_cfg_sender.sv	Distributes register writes across groups.
hardware/​src/​cachepool_cluster.sv	Connects the narrow mesh and wide BootROM path.
hardware/​cachepool_peripheral/​cachepool_peripheral.sv	Tracks configuration batches and completion.
hardware/​cachepool_peripheral/​cachepool_peripheral_reg.hjson.tmpl	Revises register semantics and reset parameters.
hardware/​cachepool_peripheral/​cachepool_peripheral_reg_top.sv	Updates generated register implementation.
hardware/​cachepool_peripheral/​cachepool_peripheral_reg_pkg.sv	Updates generated register types and offsets.
hardware/​bootrom/​bootrom.S	Avoids address loads through the GOT.
config/​config.mk	Adds shared configuration defaults.
config/​cachepool.hjson.tmpl	Exposes BootROM width.
Bender.yml	Registers new modules and removes converter source.
Bender.lock	Updates FlooNoC revision.

_{Review effort: Balanced}