Merge insitu cache and rlc sw dev

.gitlab-ci.yml

@@ -170,6 +170,8 @@ test:
           - fft-32b_M1024_N16
           - byte-enable
           - multi_producer_single_consumer_double_linked_list_M1_N1350_K10
+          - multi_producer_single_consumer_double_linked_list_M1_N1350_K4_P2_C2_am_G1024_tbchk
+          - multi_producer_single_consumer_double_linked_list_P1_C3_ul_ci
   script:
     # The vsim script writes a .rtlbinary marker here; monitor logs need the
     # core/noc/others subfolders. Build artifacts exclude sim/bin/logs/, so

Bender.lock

@@ -109,7 +109,7 @@ packages:
     - obi
     - register_interface
   insitu-cache:
-    revision: 189bf8cd5b7a49cde3b6aa5b75590ee15521eaf9
+    revision: d7a526ebc965c3c9808f348b377d06f4479cc4ab
     version: null
     source:
       Git: https://github.com/pulp-platform/Insitu-Cache.git
@@ -150,7 +150,7 @@ packages:
     dependencies:
     - tech_cells_generic
   spatz:
-    revision: f4741b0a5bcc49103bd8a3db8d51fdf76d240df7
+    revision: 6acbd2e0cb9131f870209d03ffb85c46fbd2ea9c
     version: null
     source:
       Git: https://github.com/pulp-platform/spatz.git

Makefile

@@ -160,18 +160,27 @@ SNRT_BOOTINFO_H := $(SOFTWARE_DIR)/snRuntime/include/snrt_bootinfo.h
 $(SNRT_BOOTINFO_H): $(SCRIPTS_DIR)/generate_bootdata.py $(HJSON_OUT) $(BOOTROM_DIR)/snrt_bootinfo.h.tpl
 	${PYTHON} $< -c $(HJSON_OUT) -d $(BOOTROM_DIR) -t snrt_bootinfo.h.tpl -o $@
 
+# BootROM compiler: the IIS GCC 9.5.0 wrapper when available, otherwise the repo toolchain.
+# Override with BOOTROM_GCC_PREFIX=<path>/riscv32-unknown-elf-
+BOOTROM_GCC_9_5 := riscv -riscv64-gcc-9.5.0 riscv64-unknown-elf-
+ifeq ($(shell $(BOOTROM_GCC_9_5)gcc --version >/dev/null 2>&1 && echo ok),ok)
+  BOOTROM_GCC_PREFIX ?= $(BOOTROM_GCC_9_5)
+else
+  BOOTROM_GCC_PREFIX ?= $(GCC_INSTALL_DIR)/bin/riscv32-unknown-elf-
+endif
+
 $(BOOTROM_DIR)/bootrom.elf $(BOOTROM_DIR)/bootrom.dump $(BOOTROM_DIR)/bootrom.bin: \
   $(BOOTROM_DIR)/bootrom.S $(BOOTROM_DIR)/bootdata_bootrom.cc $(BOOTROM_DIR)/bootrom.ld $(SNRT_BOOTINFO_H)
-	riscv -riscv64-gcc-9.5.0 riscv64-unknown-elf-gcc \
+	$(BOOTROM_GCC_PREFIX)gcc \
 		-mabi=ilp32 -march=rv32imaf -static -nostartfiles \
 		-T$(BOOTROM_DIR)/bootrom.ld \
 		$(BOOTROM_DIR)/bootrom.S \
 		$(BOOTROM_DIR)/bootdata_bootrom.cc \
 		-I$(SPATZ_DIR)/hw/ip/snitch_test/src \
 		-I$(SOFTWARE_DIR)/snRuntime/include \
 		-o $(BOOTROM_DIR)/bootrom.elf
-	riscv -riscv64-gcc-9.5.0 riscv64-unknown-elf-objdump -D $(BOOTROM_DIR)/bootrom.elf > $(BOOTROM_DIR)/bootrom.dump
-	riscv -riscv64-gcc-9.5.0 riscv64-unknown-elf-objcopy -O binary $(BOOTROM_DIR)/bootrom.elf $(BOOTROM_DIR)/bootrom.bin
+	$(BOOTROM_GCC_PREFIX)objdump -D $(BOOTROM_DIR)/bootrom.elf > $(BOOTROM_DIR)/bootrom.dump
+	$(BOOTROM_GCC_PREFIX)objcopy -O binary $(BOOTROM_DIR)/bootrom.elf $(BOOTROM_DIR)/bootrom.bin
 
 $(BOOTROM_DIR)/bootrom.sv: $(BOOTROM_DIR)/bootrom.bin $(BOOTROM_DIR)/bootdata.cc
 	${PYTHON} $(SCRIPTS_DIR)/generate_bootrom.py \

hardware/src/cachepool_tile.sv

@@ -1299,8 +1299,11 @@ module cachepool_tile
             automatic logic sel_found;
             automatic int unsigned sel_part_idx;
 
-            bank_req[col][bank_sel] = 1'b0;
-            bank_we[col][bank_sel] = 1'b0;
+            // Timing: we/req equal the OR of the part bits (the cascade prefers a write part),
+            // so take them directly instead of through the sel_part_idx mux, off the critical
+            // path tail. addr/wdata/be still use the mux.
+            bank_we[col][bank_sel]  = |part_we[col][bank_sel];
+            bank_req[col][bank_sel] = (|part_we[col][bank_sel]) | (|part_req[col][bank_sel]);
             bank_addr[col][bank_sel] = '0;
             bank_wdata[col][bank_sel] = '0;
             bank_be[col][bank_sel] = '0;
@@ -1323,8 +1326,6 @@ module cachepool_tile
             end
 
             if (sel_found) begin
-              bank_req[col][bank_sel] = 1'b1;
-              bank_we[col][bank_sel] = part_we[col][bank_sel][sel_part_idx];
               bank_addr[col][bank_sel] = part_addr[col][bank_sel][sel_part_idx];
               bank_wdata[col][bank_sel] = part_wdata[col][bank_sel][sel_part_idx];
               bank_be[col][bank_sel] = part_be[col][bank_sel][sel_part_idx];

software/rlc/multi_producer_single_consumer_double_linked_list/data/.gitignore

@@ -0,0 +1,2 @@
+# Generated data headers, reproduced by `make gen-data` from ../script/data_<params>.json
+*.h