CoreS3 / Core2 v1.1: do not power the board off while detection brings up the 5 V bus - #319
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On a weak USB supply (a port behind several hubs) with no battery, the inrush when the board's loads and the external 5V output come up pulls a DCDC output below 85% of its setting. The AXP2101 then powers itself off (REG21 = 0x20, DCDC under-voltage) and stays off until the power key is pressed; the backlight flashes once and the board is silent. Seen on the CoreS3 SE and Core2 v1.1. Disable the DCDC1-5 under-voltage power-off (REG23 bit4:0) at the start of the CoreS3 and Core2 v1.1 power sequences in board detection, before the LDOs, backlight and 5V output are switched on. A dip then resets the ESP32 through its brown-out detector instead, which recovers by itself. The DCDC over-voltage power-off (bit 5) and the VSYS under-voltage power-off (VOFF) stay enabled; when the supply cannot hold VSYS at all the PMIC still powers off (REG21 = 0x08).
When the SPI lines show no pull-up (e.g. a USB host module on the bus), detection enables the 5 V bus output. Setting BUS_OUT_EN together with BOOST_EN connects the empty BUS_OUT capacitance at once; on a weak USB supply (several hub levels deep, no battery) that pulls the AXP2101 DCDC under its threshold and the PMIC powers the board off before the display comes up. The power op list now enables only BOOST_EN, and the CoreS3 refine step (run right after the power ops) raises BUS_OUT_EN with 8 pulses of growing on-time first: each pulse is one 100 kHz register write plus i * 16 us, 1 ms apart. BUS_OUT has a constant discharge path, so short fixed pulses do not accumulate; once it passes about 1.7 V it is pulled up from VBUS even with BUS_OUT_EN = 0 and the final enable is a small step. This is the same sequence M5Unified uses in setExtOutput(). A write that fails during the ramp is followed by rewriting and reading back BUS_OUT_EN = 0 (up to three times): confirmed off stops (after a failed on-pulse) or continues the ramp, still on goes to the final enable, unreadable stops. The final enable is read back and retried, because a precharged BUS_OUT left with BUS_OUT_EN = 0 latches to VBUS and blocks later enables. Failures are logged; they do not fail detection, since losing the board (and the display) over the 5 V output would be worse and M5Unified enables it later. Checked on a CoreS3 SE (no battery, deep USB hub) with M5GFX_AUTODETECT_TEST_CORES3_FORCE_VBUS: plugging USB in powered the board off before, and starts it with the precharge.
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On a weak USB supply (several hubs deep, no battery), a CoreS3 SE could power itself off during board detection, before the display came up. The AXP2101 reported a DCDC under-voltage power-off (REG21 = 0x20).
Cause
When the SPI lines show no pull-up (for example with a USB host module attached), detection enables the 5 V bus output. The power op list set BUS_OUT_EN together with BOOST_EN, connecting the empty bus capacitance at once; the inrush pulls a DCDC output under 85 % and the PMIC latches off.
Change
setExtOutput(): 8 pulses of growing on-time (one 100 kHz register write plus i × 16 µs, 1 ms apart). Failures are logged and do not fail detection, since losing the board (and the display) over the 5 V output would be worse, and M5Unified enables the output later.Companion change in M5Unified: m5stack/M5Unified#381.
Checks
M5GFX_AUTODETECT_TEST_CORES3_FORCE_VBUSto force this path: before, plugging USB in powered the board off during detection; after, it starts, and a logic analyzer on the 5 V bus shows it crossing about 1.7 V within the first few pulses.