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fix: allow CircuitPython UART construction without parity - #317

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YashAnand69 wants to merge 2 commits into
fossasia:mainfrom
YashAnand69:fix/busio-uart-default-parity
Open

fix: allow CircuitPython UART construction without parity#317
YashAnand69 wants to merge 2 commits into
fossasia:mainfrom
YashAnand69:fix/busio-uart-default-parity

test: cover UART parity and stop-bit configuration

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