riscv32: spec compliance and regression test fix

[akifejaz]

This PR corrects the RISC-V32 GNU port as per spec and its QEMU virt support.

• The port uses 16-byte stack alignment at each C function call.
• Context paths preserve integer, floating-point, CSR, and program-counter state.
• Frame offsets use the slot*byte-size(base) format.
• Build guards reject unsupported ISA and ABI combinations.
• Startup code initializes gp and uses valid linker regions.
• CLINT code uses safe RV32 timer reads and writes.
• PLIC code masks unused sources and handles claim ID zero.
• The QEMU test checks timer, FPU, PC, time-slice, clock, and preemption behavior.

[akifejaz]

This and the following few PRs will be related to RISC-V CI enablement efforts. I'had discussed this in last Weekly meeting.

I've started testing the riscv ports with available tests and closely comparing implementations with respect to riscv spec.

Once the CI of riscv ports is running cleanly, I'll be processing with Cloud-V setup (RISC-V hardware CI)

cc @fdesbiens