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1. constraintforge constraintforge Public

   Production-grade FPGA timing constraint library for Xilinx UltraScale+. Modular, parametric XDC templates for high-speed digital design.

   Tcl 7 1

2. riscv-ooo-core riscv-ooo-core Public

   Full superscalar RV32I out-of-order processor with Tomasulos Algorithm, 7-stage pipeline, and UVM testbench. 1st Place + Special Jury Award — SanDisk Hardware Hackathon.

   Verilog 11

3. dev-tyagi-portfolio dev-tyagi-portfolio Public

   FPGA/RTL Design Engineer portfolio. WebGL 3D FPGA fabric, interactive UNIX terminal, FLIR thermal mode. Built with raw HTML, CSS, JS, Three.js.

   HTML 1

4. aml-sentinel aml-sentinel Public

   Anti-money laundering transaction graph analysis using ML — graph-based anomaly detection on financial networks

   Python 1

5. Bharat_SoC- Bharat_SoC- Public

   repo for all teh codes we made for Bharat SoC challenge

   Python 1

6. pmdc-fpga-motor-control pmdc-fpga-motor-control Public

   Real-time PMDC motor drive simulation on FPGA. Full closed-loop PID control in SystemVerilog, synthesized and verified on Zynq fabric.

   C 1