Issues

• saxpy example passes kernargs at the wrong offsets

  backend: AMDbug
  Zaneham/Booth#166 · Filter by author Zaneham opened on Aug 18, 2026

• Pip install booth

  enhancementTriton
  Zaneham/Booth#161 · Filter by author Zaneham opened on Aug 9, 2026

• Indexing an array member of a struct produces a GEP with a non-pointer result

  bug
  Zaneham/Booth#148 · Filter by author Zaneham opened on Jul 28, 2026

• Whether baby core kernels should use compressed instructions

  backend: Tensixquestion
  Zaneham/Booth#135 · Filter by author Zaneham opened on Jul 23, 2026

• RV32 mutual recursion is not detected

  backend: Tensixenhancement
  Zaneham/Booth#134 · Filter by author Zaneham opened on Jul 23, 2026

• Code buffer caps kernels at 16 KiB regardless of chip

  backend: Tensixenhancement
  Zaneham/Booth#133 · Filter by author Zaneham opened on Jul 23, 2026

• Atomics and warp primitives unimplemented on RV32

  backend: Tensixenhancement
  Zaneham/Booth#132 · Filter by author Zaneham opened on Jul 23, 2026

• __device__ globals refuse for want of a data segment

  backend: Tensixenhancement
  Zaneham/Booth#131 · Filter by author Zaneham opened on Jul 23, 2026

• Region TWA is declared but never allocated

  backend: Tensixenhancement
  Zaneham/Booth#130 · Filter by author Zaneham opened on Jul 23, 2026

• TDF fission never synthesises RDR and WRT bodies

  backend: Tensixenhancement
  Zaneham/Booth#129 · Filter by author Zaneham opened on Jul 23, 2026

• Lower BIR_FADD and friends to soft-float calls

  backend: Tensixenhancement
  Zaneham/Booth#128 · Filter by author Zaneham opened on Jul 23, 2026

• Float arithmetic needs i64 lowering as register pairs

  backend: Tensixenhancement
  Zaneham/Booth#127 · Filter by author Zaneham opened on Jul 23, 2026

• RV32 backend has no register allocator

  backend: Tensixoptimisation
  Zaneham/Booth#126 · Filter by author Zaneham opened on Jul 23, 2026

• BarraCUDA references throughout the project

  documentation
  Zaneham/Booth#122 · Filter by author Zaneham opened on Jul 16, 2026

• Tensix backend: emit string literal globals (Phase 2)

  enhancementhelp wanted
  Zaneham/Booth#95 · Filter by author Zaneham opened on May 24, 2026

• NVIDIA PTX backend: emit string literal globals as .const arrays

  enhancementhelp wanted
  Zaneham/Booth#94 · Filter by author Zaneham opened on May 24, 2026
  1

• AMD backend: emit string literal globals into .rodata (Phase 2)

  backend: AMDenhancement
  Zaneham/Booth#93 · Filter by author Zaneham opened on May 24, 2026

• Triton: tl.atomic_add and the atomic family

  enhancementgood first issueTriton
  Zaneham/Booth#83 · Filter by author Zaneham opened on May 21, 2026

• Triton: comparison chains preserve implicit AND semantics

  enhancementTriton
  Zaneham/Booth#81 · Filter by author Zaneham opened on May 21, 2026

• Triton: tuple unpacking on assignment

  enhancementgood first issueTriton
  Zaneham/Booth#80 · Filter by author Zaneham opened on May 21, 2026

• Triton: submodule access (tl.math.exp, tl.extra.libdevice.*)

  enhancementgood first issueTriton
  Zaneham/Booth#77 · Filter by author Zaneham opened on May 21, 2026

• Triton: honour mask= on tl.load and tl.store

  enhancementTriton
  Zaneham/Booth#76 · Filter by author Zaneham opened on May 21, 2026

• Triton: tl.zeros, tl.full, tl.zeros_like

  enhancementgood first issueTriton
  Zaneham/Booth#75 · Filter by author Zaneham opened on May 21, 2026

• Triton: subscript and slice lowering

  enhancementTriton
  Zaneham/Booth#73 · Filter by author Zaneham opened on May 21, 2026

• HIP: __lane_id() intrinsic

  enhancementgood first issueHIP
  Zaneham/Booth#67 · Filter by author Zaneham opened on May 19, 2026