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Stone Arch Silicon

A semiconductor-design community at the University of Minnesota.

Club website · Start ASIC 101 · Project and contributor guide

Find your starting point

You want to… Start here What is here
Learn the digital hardware flow ASIC 101 25 lessons taking an 8-bit ALU through RTL, verification, FPGA implementation, and ASIC physical design; course validation is ongoing
Read or improve the documentation ASIC docs The club documentation book and its source
Our IP Stone Arch Silicon IP Our collection of reusable IP Blocks
Explore numerical formats 8-bit posit Posit codec documentation and an interactive manual; currently a documentation project
Improve the publishing tools Documentation theme A shared mdBook theme
Find the club and maintain the site Club website source Website, project directory, and contributor entry points

Start building

New to the flow? Follow the ASIC 101 course map: setup → RTL → simulation → FPGA → synthesis and physical design → verification and handoff. Keep a record of the commands, tool versions, reports, and results you can reproduce.

To contribute, choose the repository that owns the work, read its README, and open an issue describing the change or a focused pull request with validation steps. Documentation fixes, reproducible examples, test cases, and clear engineering explanations all help.

Connected community

Explore ASIC Network for the broader community, analog and digital learning material, and shared silicon initiatives. Individual repository histories credit the contributors behind each project.

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  1. ASIC_101 ASIC_101 Public

    25-lesson ASIC design course: build and verify an 8-bit ALU, implement it in Vivado, then explore SKY130 RTL-to-GDSII with LibreLane.

    Verilog

  2. stone-arch-silicon stone-arch-silicon Public

    Stone Arch Silicon at the University of Minnesota: club website, semiconductor projects, and routes into hands-on chip design.

    HTML 1

  3. 8-Bit_Posit 8-Bit_Posit Public

    8-bit posit research documentation for UMN UROP, including an interactive codec manual; RTL and verification artifacts are not yet published here.

    HTML

  4. Mat_Mul_Systolic_Arrays Mat_Mul_Systolic_Arrays Public

    Stone Arch Silicon 2x2 systolic matrix multiplier: SystemVerilog RTL, Vivado project artifacts, and simulation documentation.

    JavaScript

Repositories

Showing 10 of 13 repositories

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