Update fearless_simd requirement from 0.7.0 to 1.0.0

[dependabot]

Updates the requirements on fearless_simd to permit the latest version.

Release notes

Sourced from fearless_simd's releases.

fearless_simd-v1.0.0

Crates.io | Docs

Fearless SIMD 1.0 is here! 🎉

This release has an MSRV of 1.89.

Added

• Added the optional #[simd] attribute in fearless_simd_macros 0.1.0 to annotate SIMD-generic functions. The first argument can be a SIMD token, vector, mask, reference, or user-defined wrapper implementing ExtractToken. The core library does not depend on the macro crate. (#347, #383 by @​Shnatsel)
• Added Native<S> to SimdFloatElement and SimdIntElement to select native-width vectors in scalar-generic code. (#378 by @​Shnatsel)
• Added the public ExtractToken trait for SIMD tokens, vectors, masks, references, and user-defined wrappers.
• Added reverse for all SIMD vector and mask types. (#356 by @​Shnatsel)
• Added rotate_elements_left and rotate_elements_right to mask types. Rotations wrap the offset, matching the existing non-mask vector operations. (#360 by @​Shnatsel)
• Added lane-wise saturating_add and saturating_sub for all integer vector types and backends. (#352 by @​Shnatsel)
• Added lane-wise count_ones and count_zeros operations for all integer vector types and backends. The result has the same vector type as the input, including for signed integers. (#345 by @​Shnatsel)
• Added reduce_min, reduce_max, reduce_min_precise, and reduce_max_precise for all non-mask vector types. The precise floating-point variants ignore quiet NaNs, returning NaN only when all lanes are quiet NaNs; signaling NaNs have implementation-defined behavior. (#358 by @​Shnatsel)
• Added reduce_sum and reduce_product for all non-mask vector types. Integer arithmetic wraps. Floating-point reductions use a fixed order that produces identical results across backends for a given vector type and lane count, except for NaN bit patterns. Summation limits each lane’s contribution to at most log2(N) roundings for N lanes. (#357, #361 by @​Shnatsel)
• Added mul_add_precise and mul_sub_precise for floating-point vectors. They guarantee the infinite-precision product-plus-add rounded once, including on SIMD levels without hardware fused multiply-add instructions. They are not susceptible to the bug in Rust’s standard library, std::simd, and musl libc that causes incorrect rounding for subnormal results. SSE4.2 gets SIMD emulation of these operations for better performance. (#323, #324 by @​Shnatsel)
• Documented the storage representation of the SIMD vector types. The documented representation will not change without a semver major version change. (#330 by @​danderson)
• Added TryFrom bounds to SimdIntElement, allowing attempted conversion from all primitive integer types. (#335 by @​danderson, @​Shnatsel)
• Added a security policy. Starting with v1.0, the latest Fearless SIMD version for each MSRV will receive security backports for at least three years after that Rust version was released. (#367 by @​Shnatsel, @​DJMcNab)

Changed

• Breaking change: witness() has moved from SimdBase and SimdMask to their new ExtractToken supertrait and has been renamed to token().
• Breaking change: SimdBase::N and SimdMask::N have been renamed to LEN, matching the std::simd naming. (#366 by @​Shnatsel)
• Breaking change: SimdBase::as_array now borrows the vector and returns an array reference, while owned extraction has moved to to_array. The old as_array_ref and as_array_mut methods have been replaced by as_array and as_mut_array, matching the std::simd API. (#351 by @​Shnatsel)
• Breaking change: abs has moved from SimdFloat to SimdBase and is now available on integer vectors. Signed integers use wrapping absolute value, leaving the minimum representable value unchanged; unsigned integers are unchanged. (#371 by @​Shnatsel)
• Simd::vectorize now marks its inner wrappers #[inline], allowing inlining into callers with compatible target features. (#347 by @​Shnatsel)
• Conversions between 64-bit integers and floating-point values have been optimized on x86, particularly for 256-bit AVX2 vectors. (#348 by @​Shnatsel)
• x86 code generation has been improved for 8-bit integer multiplication, 8-bit per-lane left shifts on AVX-512, and 8-bit and 16-bit integer unzip on SSE4.2 and AVX2. (#350 by @​Shnatsel)
• swizzle_dyn and swizzle_dyn_precise have been optimized on AVX2. On WebAssembly with relaxed-simd enabled, 128-bit swizzle_dyn now uses the relaxed swizzle instruction. (#322, #362 by @​Shnatsel)
• SimdMask::to_bitmask has been optimized on NEON, including dedicated implementations for wide masks. (#344 by @​Shnatsel)
• Mask reductions (any_true, all_true, any_false, and all_false) on masks wider than a native register now combine vector halves before reducing, avoiding branches and repeated scalar extraction. (#343 by @​Dr-Emann)
• Level::is_fallback is now marked inline, allowing callers to eliminate the function call when the result is a compile-time constant. (#336 by @​Dr-Emann)

Fixed

• Fixed a possible dispatch panic with custom x86 target-feature configurations by including adx in the AVX-512 feature checks that control AVX2 dispatch availability. (#377 by @​Shnatsel)
• Fixed fract on NEON for large finite values and infinities. Large finite values now return zero, and infinities return NaN, matching the other backends. (#365 by @​Shnatsel)
• Fixed the sign of zero returned by mul_sub on NEON for some combinations of signed inputs. (#323 by @​Shnatsel)
• Hardened the hidden kernel! implementation helpers so callers cannot bypass SIMD token and target-feature checks by invoking them directly. (#363 by @​Shnatsel)

Full Changelog: v0.7.0...fearless_simd-v1.0.0

Changelog

Sourced from fearless_simd's changelog.

[1.0.0][] (2026-09-21)

This release has an [MSRV][] of 1.89.

Added

• Added the optional #[simd] attribute in fearless_simd_macros 0.1.0 to annotate SIMD-generic functions. The first argument can be a SIMD token, vector, mask, reference, or user-defined wrapper implementing ExtractToken. The core library does not depend on the macro crate. (#347[], #383[] by [@​Shnatsel][])
• Added Native<S> to SimdFloatElement and SimdIntElement to select native-width vectors in scalar-generic code (#378[] by [@​Shnatsel][]).
• Added the public ExtractToken trait for SIMD tokens, vectors, masks, references, and user-defined wrappers.
• Added reverse for all SIMD vector and mask types. (#356[] by [@​Shnatsel][])
• Added rotate_elements_left and rotate_elements_right to mask types. Rotations wrap the offset, matching the existing non-mask vector operations. (#360[] by [@​Shnatsel][])
• Added lane-wise saturating_add and saturating_sub for all integer vector types and backends. (#352[] by [@​Shnatsel][])
• Added lane-wise count_ones and count_zeros operations for all integer vector types and backends. The result has the same vector type as the input, including for signed integers. (#345[] by [@​Shnatsel][])
• Added reduce_min, reduce_max, reduce_min_precise, and reduce_max_precise for all non-mask vector types. The precise floating-point variants ignore quiet NaNs, returning NaN only when all lanes are quiet NaNs; signaling NaNs have implementation-defined behavior. (#358[] by [@​Shnatsel][])
• Added reduce_sum and reduce_product for all non-mask vector types. Integer arithmetic wraps. Floating-point reductions use a fixed order that produces identical results across backends for a given vector type and lane count, except for NaN bit patterns. Summation limits each lane's contribution to at most log2(N) roundings for N lanes. (#357[], #361[] by [@​Shnatsel][])
• Added mul_add_precise and mul_sub_precise for floating-point vectors. They guarantee the infinite-precision product-plus-add rounded once, including on SIMD levels without hardware fused multiply-add instructions. They are not susceptible to the bug in Rust standard library, std::simd and musl libc that causes incorrect rounding for subnormal results. SSE4.2 gets SIMD emulation of these operations for better performance. (#323[], #324[] by [@​Shnatsel][])
• Documented the storage representation of the SIMD vector types. The documented representation will not change without a semver major version change. (#330[] by [@​danderson][])
• Added TryFrom bounds to SimdIntElement, allowing attempted conversion from all primitive integer types. (#335[] by [@​danderson][], [@​Shnatsel][])
• Added a security policy. Starting with v1.0, the latest Fearless SIMD version for each MSRV will receive security backports for at least three years after that Rust version was released. (#367[] by [@​Shnatsel][], [@​DJMcNab][])

Changed

• Breaking change: witness() has moved from SimdBase and SimdMask to their new ExtractToken supertrait and has been renamed to token().
• Breaking change: SimdBase::N and SimdMask::N have been renamed to LEN, matching the std::simd naming. (#366[] by [@​Shnatsel][])
• Breaking change: SimdBase::as_array now borrows the vector and returns an array reference, while owned extraction has moved to to_array. The old as_array_ref and as_array_mut methods have been replaced by as_array and as_mut_array, matching the std::simd API. (#351[] by [@​Shnatsel][])
• Breaking change: abs has moved from SimdFloat to SimdBase and is now available on integer vectors. Signed integers use wrapping absolute value, leaving the minimum representable value unchanged; unsigned integers are unchanged. (#371[] by [@​Shnatsel][])
• Simd::vectorize now marks its inner wrappers #[inline], allowing inlining into callers with compatible target features. (#347[] by [@​Shnatsel][])
• Conversions between 64-bit integers and floating-point values have been optimized on x86, particularly for 256-bit AVX2 vectors. (#348[] by [@​Shnatsel][])
• x86 code generation has been improved for 8-bit integer multiplication, 8-bit per-lane left shifts on AVX-512, and 8-bit and 16-bit integer unzip on SSE4.2 and AVX2. (#350[] by [@​Shnatsel][])
• swizzle_dyn and swizzle_dyn_precise have been optimized on AVX2. On WebAssembly with relaxed-simd enabled, 128-bit swizzle_dyn now uses the relaxed swizzle instruction. (#322[], #362[] by [@​Shnatsel][])
• SimdMask::to_bitmask has been optimized on NEON, including dedicated implementations for wide masks. (#344[] by [@​Shnatsel][])
• Mask reductions (any_true, all_true, any_false, and all_false) on masks wider than a native register now combine vector halves before reducing, avoiding branches and repeated scalar extraction. (#343[] by [@​Dr-Emann][])
• Level::is_fallback is now marked inline, allowing callers to eliminate the function call when the result is a compile-time constant. (#336[] by [@​Dr-Emann][])

Fixed

• Fixed a possible dispatch panic with custom x86 target-feature configurations by including adx in the AVX-512 feature checks that control AVX2 dispatch availability. (#377[] by [@​Shnatsel][])
• Fixed fract on NEON for large finite values and infinities. Large finite values now return zero, and infinities return NaN, matching the other backends. (#365[] by [@​Shnatsel][])
• Fixed the sign of zero returned by mul_sub on NEON for some combinations of signed inputs. (#323[] by [@​Shnatsel][])
• Hardened the hidden kernel! implementation helpers so callers cannot bypass SIMD token and target-feature checks by invoking them directly. (#363[] by [@​Shnatsel][])

[0.7.0][] (2026-08-11)

This release has an [MSRV][] of 1.89.

Added

• Added i64x2, i64x4, i64x8, u64x2, u64x4, and u64x8 vector types, the native-width i64s and u64s associated types, and 64-bit integer operations across all backends. (#253[], #310[] by [@​Shnatsel][])
• Added an Sse2 level. This is the new baseline for i686-* and x86_64-* targets, replacing Fallback. It is detected at runtime on Tier-2 i586-* targets. (#270[] by [@​Shnatsel][])
• Added shift_elements_left, shift_elements_right, rotate_elements_left, and rotate_elements_right to non-mask vectors. Shifts accept a padding element and fill the entire vector when the offset is at least its lane count; rotations wrap the offset. (#274[] by [@​Shnatsel][])

... (truncated)

Commits

• dcbd824 Release v1.0 (#389)
• 1eca45d Reword the advice on the proc macro usage (#387)
• 588a0b0 Add an example showing fully generic code (#388)
• 77db928 Bump to next release candidate (#386)
• 02a6320 Update changelog (#384)
• 00a878f Allow the first argument of #[simd] functions to be f32x4\<S> and such (#383)
• d1500b6 Add #[simd] macro (#347)
• bd9f7c7 Add a way to select the native SIMD vector width for a given scalar type (#378)
• 178d0e7 Minor fixes (#377)
• 418c86f Populate changelog for the next release (#374)
• Additional commits viewable in compare view

Dependabot will resolve any conflicts with this PR as long as you don't alter it yourself. You can also trigger a rebase manually by commenting @dependabot rebase.

---

Dependabot commands and options

You can trigger Dependabot actions by commenting on this PR:

• @dependabot rebase will rebase this PR
• @dependabot recreate will recreate this PR, overwriting any edits that have been made to it
• @dependabot show <dependency name> ignore conditions will show all of the ignore conditions of the specified dependency
• @dependabot ignore this major version will close this PR and stop Dependabot creating any more for this major version (unless you reopen the PR or upgrade to it yourself)
• @dependabot ignore this minor version will close this PR and stop Dependabot creating any more for this minor version (unless you reopen the PR or upgrade to it yourself)
• @dependabot ignore this dependency will close this PR and stop Dependabot creating any more for this dependency (unless you reopen the PR or upgrade to it yourself)