[VV0003]

Summary

Add experimental explicit TileOP PredicateCell producer/consumer adapters. This is not an element-if-only API and does not export/import element-if implicit masks.

• Private Predicate<Basis> carrier; compare_scalar<Mode> produces CUBE PredicateCell.
• scatter binds PredicateCell directly to MSCATTER_MASK without TCVT.
• atomic_add<Invert> uses MSCATTER_ADD ExecutionMask, not a new operation-owned source mask. Requires LLVM commit db000947b0cdf9c128d3880bb23ca7daac34d81a, already pushed to LinxISA/llvm-project dev-llvm15_56.
• Bounded initial scope: Local VEC CUBE_M32, static valid shape, FP32/S32/U32, S64/U64 byte offsets. No predicate composition, automatic GPR adaptation, M16, or cross-call/spill support.
• Synchronize guide, options.md, element-if distinctions, support status and operation pages. Add dedicated required-gate test step.

Related: PTO-ISA/pto-spec#349 (not closed; broader composition/spec wording questions remain).

Validation

• Source-to-object: F32/S32/U32 × physical columns 4/8; all six compile.
• Assembly shape: 2 ExecMaskPresent markers, MSCATTER.ADD inversion, direct explicit MSCATTER.MASK, no TCVT, no erroneous S64/NORM offset reload.
• New API suite + engine contract: 64/64 PASS on matching LLVM.
• LLVM/Clang new tests: 3/3 PASS (object, asm roundtrip and negative diagnostics).
• Full Python: candidate 139 / pristine 134 tests, both 2 FAIL + 1 ERROR + 7 SKIP; identical failure names (existing unsupported-dtype expectation, weight header spelling expectation, shallow /tmp ROOT.parents[2] test import).
• LLVM CodeGen/LinxV5 + MC/LinxV5: 319 PASS / 1 XFAIL / 50 existing FAIL, no new failures against recorded baseline.
• Complete Markdown example compiled to object, navigation links and diff-check PASS.

Model boundary

No model/ISA assertions changed. No model numerical or TopK RES_CHECK PASS claimed. Current SuperScalarModel main has an explicit non-TCI ExecutionMask rejection and multi-column CUBE explicit-mask restriction; these are tracked separately, not patched or bypassed here. FP32 timing capability is already tracked by SuperScalarModel #1046.

Please merge only after required CI is green; do not bypass the gate.

[VV0003]

Model capability follow-up: LinxISA/SuperScalarModel#1131 now tracks the pinned-main non-TCI ExecutionMask rejection and multi-column CUBE PredicateCell explicit-mask gap. Existing FP32 timing capability remains #1046. Do not treat this PR or MC roundtrip validation as model end-to-end acceptance.