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Multi-PE runtime, PE-domain participation and hosted gfrun adapter - #292
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The TileArray-slot continuation emitters (unary, scalar, scalar-subview, TCVT, binary) closed the B.IOT stream with L=1 on the math-input record and then bound the Local AssembleParentRef on a trailing source-form record with L=0. PTO-B-IOT-STREAM-001 requires the opposite: the final effective record carries L=1 (with any destination) and earlier records carry L=0, and B.IOT.asl makes any B.IOT after an L=1 record an illegal block. gfsim tolerated the sequence only because HandleBIOT does not enforce the after-L rule, so every assembled MIDDLE/LAST fragment was spec-illegal while still running. Pack the single math input and the parent register into one two-source final record with L=1 (unary, scalar, scalar-subview, TCVT); the binary continuation has three operands and keeps two records with L moved onto the parent record. This also matches the already-packed _ASS emitters in template_asm.hpp (convert/reduce/expand) and completes the binder compaction that #173 started for the region side. Requires the SuperScalarModel HandleBAssemble continuation to take the LAST source of the open binder as the ParentRef instead of requiring a single-source binder; the legacy two-record form stays accepted. fa_lowp_algB -O2: every assembled MIDDLE/LAST fragment now emits one packed B.IOT (B.IOT records 2673 -> 2299, -374); gfsim fourpe smoke: fault 0, Total Cycles 28454 -> 28270. Co-authored-by: LinxISA Automation <linxisa-automation@users.noreply.github.com>
Complete the binder compaction that #266 started. Three emitters still left packable records on the table: - pto_region_unary_subview_assemble / pto_region_tcvt_subview_assemble (SubTileView sources into TileArray slots): the MIDDLE/LAST continuation still emitted the old two-record form with L=1 on the math-input record. Pack the math input and the parent register into one two-source final record, matching the scalar-subview and plain (non-subview) forms #266 already compacted: B.IOT src, parent, mask=1111, last ; B.SUBVIEW 0, ... ; B.ASSEMBLE ... - PTO_FIXP_ACC_FOLD_LOCAL (non-MX TMATMUL.ACC option path, SrcMask==0 / OutMask==0): C stayed alone in the first record while the SHARED_B variant already pairs C with A. Pair C,A in the first record and let B (and CScale when enabled, carrying D) form the final record, saving one binder in the CScale branch (3 -> 2 records): B.IOT C, A ; B.IOT B, CScale, mask=1111, last, ->D Verified on a minimal repro covering all three sites (TEXP/TCVT subview-to-slot and TMATMUL_ACC + cscale); object gate 68/24 identical to the baseline; python suites green; fa_lowp_algB unaffected (its paths were already packed by #266). Co-authored-by: LinxISA Automation <linxisa-automation@users.noreply.github.com>
…0261026 # Conflicts: # test/tileop_api/compile.all
This was referenced Oct 26, 2026
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Summary
Reintroduces the multi-PE feature line into
linx, as one of the four integration-validated multi-PE branches (LLVMdev-llvm15_56@86330917bada, musllinx@fd2e263a, Linuxmain@b7c384b4acc2are already merged on their mainlines).Branch state
Up to date with
linx@c150817(includes #289 CubeM32 binary slot assembly and #291/#290 TCMP/TSEL shape contract); no conflicts.Validation
dev-llvm15_56@86330917bada: DType macro regression PASS, layout-interface selectors/operand schemas PASS,template_asm.hppLinx clang parse PASS, whitespace check PASS.Issue288CubeM32BinaryAssemblyandIssue290PartialCompareSelectcompile with the new mainline clang.Known seam (not covered by this gate)
TileArrayParticipantMask.cppand other PE-domain fixtures incompile.alldo not yet compile against post-#118 mainline LLVM (P1a requires one complete carrier publication, reproduced identically onc866da9d1b05); the integration validation used the multi-PE LLVM branch whose base predates #118. Adapting those fixtures to the #118 element-region contract is tracked as follow-up work.