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Add RISC-V architecture-specific string extraction support #75
Description
Overview
RISC-V is an emerging open-source instruction set architecture (ISA) that is rapidly gaining adoption across multiple domains including edge AI, datacenter accelerators, IoT, and cloud infrastructure. As of 2025, RISC-V has moved beyond niche/MCU applications with major industry players like Nvidia (CUDA support), Google, and AWS advancing RISC-V support.
This issue tracks the implementation of RISC-V architecture-specific features in Stringy's binary analysis capabilities to ensure optimal string extraction from RISC-V ELF binaries.
Context
StringyMcStringFace currently supports architecture-specific optimizations for:
- ARM64: Pointer authentication, tagged pointers
- x86-64: RIP-relative addressing hints
RISC-V binaries have unique characteristics that could benefit from specialized handling for more accurate string extraction and classification.
Current State
- ✅ Basic RISC-V support: The
goblincrate (v0.10.3) used by Stringy can parse RISC-V ELF binaries and expose machine constants (EM_RISCV) - ✅ ELF parsing: Existing ELF parser handles RISC-V ELF files generically
⚠️ Architecture-specific optimizations: No RISC-V-specific string extraction heuristics implemented
Proposed Solution
Phase 1: Research & Documentation
- Analyze RISC-V binary patterns and string storage conventions
- Study RISC-V calling conventions and ABI specifications
- Identify RISC-V-specific sections or metadata that aid string classification
- Document findings and determine optimization opportunities
Phase 2: Implementation
Implement RISC-V-specific enhancements as appropriate:
-
Relocation handling:
- RISC-V uses specific relocation types (R_RISCV_*) that may affect string references
- Consider handling compressed instructions (RVC extension) impact on string addressing
-
String addressing patterns:
- RISC-V uses PC-relative addressing for constants
- Analyze AUIPC + ADDI instruction pairs for loading string addresses
- Support for RISC-V's compressed instruction set (C extension) if relevant
-
ABI-specific conventions:
- RISC-V LP64/ILP32 ABI string parameter passing
- Register conventions for string arguments (a0-a7)
-
Section analysis:
- Verify standard ELF section weights apply to RISC-V binaries
- Adjust if RISC-V toolchains use different section naming conventions
Phase 3: Testing & Validation
- Create test fixtures with RISC-V binaries (32-bit and 64-bit)
- Compare extraction results with architecture-agnostic parsing
- Benchmark performance improvements
- Document any RISC-V-specific configuration options
Technical Considerations
RISC-V Variants
- RV32: 32-bit base integer instruction set
- RV64: 64-bit base integer instruction set
- Extensions: C (compressed), M (multiply/divide), A (atomic), F/D (floating-point)
- Different combinations may affect binary structure and string storage
Integration Points
- Extend
src/container/elf.rswith RISC-V architecture detection - Add RISC-V-specific classification logic if beneficial
- Update documentation in
docs/src/binary-formats.mdwith implementation details
Success Criteria
- RISC-V binaries are detected and classified correctly
- Architecture-specific optimizations (if any) are implemented and tested
- Test coverage includes RV32 and RV64 binaries with various extensions
- Documentation updated with RISC-V support details
- Performance benchmarks compare favorably to generic ELF parsing
References
- RISC-V ISA Specification: https://riscv.org/technical/specifications/
- RISC-V ELF psABI: https://github.com/riscv-non-isa/riscv-elf-psabi-doc
- goblin ELF documentation: https://docs.rs/goblin/latest/goblin/elf/
Notes
This issue is part of the broader effort to provide comprehensive cross-platform binary analysis. Given RISC-V's rapid adoption trajectory, early support positions Stringy as a forward-looking tool in the binary analysis ecosystem.
Related documentation: docs/src/binary-formats.md (Architecture-Specific Features section)
Activity
traycerai commentedon Nov 11, 2025
Plan
Observations
Stringy currently extracts strings generically by scanning sections and using basic heuristics. For RISC-V ELF binaries, opportunities exist to improve accuracy by analyzing RISC-V-specific relocation types (R_RISCV_) and instruction patterns like AUIPC + LOAD for PC-relative string references. The
goblincrate supports RISC-V relocations, enabling targeted enhancements. This will better classify strings as code-referenced vs. static data, especially in RV64 binaries with compressed instructions.</parameter\n>\nLeverage the existingArchitectureenum to dispatch RISC-V-specific logic in the string analyzer. Extend relocation processing to identify RISC-V string references and adjust string weights/classification. Implement pattern matching for common RISC-V addressing sequences without full disassembly. Update tests and docs to cover RV32/RV64 variants.</parameter\n>\nI reviewed the analyzer module structure, examined string extraction and relocation processing logic, researched RISC-V ELF psABI and relocation types via official specs, analyzed goblin's RISC-V support in ELF parsing, and identified integration points with the container parsers.</parameter\n>\n[\n{\n"path":"/tmp/github/issues/64295955_1066763615_1762833887830/src/analyzer/string.rs",\n"newPath":"",\n"operation":"MODIFY",\n"isDirectory":false,\n"changes":"Add RISC-V specific string extraction logic. Create aRiscVStringAnalyzerstruct or methods in the existing extractor.\n\n- When architecture isRiscV, scan relocations for types likeR_RISCV_32,R_RISCV_64,R_RISCV_PCREL_HI20(AUIPC),R_RISCV_PCREL_LO12(load/add).\n- For PC-relative pairs, trace to string sections (.rodata) and boost confidence scores for those strings.\n- Handle compressed instructions if relocations indicate C extension.\n- Integrate with existingStringInfoby adding areferenced_by_riscvflag or adjustingweight.\n\nRefer toContainerInfofor architecture andRelocationentries from ELF parser.",\n"referredFiles":["/tmp/github/issues/64295955_1066763615_1762833887830/src/types.rs", "/tmp/github/issues/64295955_1066763615_1762833887830/src/container/elf.rs"],\n"referredImageNames":[]\n},\n{\n"path":"/tmp/github/issues/64295955_1066763615_1762833887830/src/container/elf.rs",\n"newPath":"",\n"operation":"MODIFY",\n"isDirectory":false,\n"changes":"Enhance relocation parsing for RISC-V specifics. Ensure all R_RISCV_ types are mapped toRelocationTypeenum variants (add if missing:RiscV32,RiscV64,RiscVPcRelHi20,RiscVPcRelLo12, etc.).\n\nInparse_relocations(), usegoblin::elf::reloc::R_RISCVconstants to populate detailed type info.\n\nStore additional metadata like addend for PC-relative calcs to aid string tracing.\n\nUpdateContainerInfoto include architecture-aware relocation summaries if beneficial.",\n"referredFiles":["/tmp/github/issues/64295955_1066763615_1762833887830/src/types.rs"],\n"referredImageNames":[]\n},\n{\n"path":"/tmp/github/issues/64295955_1066763615_1762833887830/src/types.rs",\n"newPath":"",\n"operation":"MODIFY",\n"isDirectory":false,\n"changes":"ExtendRelocationTypeenum with RISC-V specific variants:\n-RiscVHi20\n-RiscVLo12\n-RiscV32\n-RiscV64\n-RiscVPcRel\n- etc., based on goblin constants.\n\nAdd derives for serialization.\n\nOptionally, addRiscVExtensionenum for C/M/A/F/D detection from ELF flags.",\n"referredFiles":[],\n"referredImageNames":[]\n},\n{\n"path":"/tmp/github/issues/64295955_1066763615_1762833887830/tests/integration_riscv.rs",\n"newPath":"",\n"operation":"NEW",\n"isDirectory":false,\n"changes":"Create new integration test file for RISC-V binaries.\n\n- Generate or include test fixtures for RV32 and RV64 ELF binaries (e.g., simple 'hello world' with strings).\n- Assert that RISC-V architecture is detected.\n- Verify enhanced string extraction identifies PC-relative referenced strings with higher confidence.\n- Test relocation parsing for AUIPC/LOAD patterns.\n- Compare output with generic extraction to show improvements.",\n"referredFiles":["/tmp/github/issues/64295955_1066763615_1762833887830/src/analyzer/string.rs"],\n"referredImageNames":[]\n},\n{\n"path":"/tmp/github/issues/64295955_1066763615_1762833887830/docs/src/binary-formats.md",\n"newPath":"",\n"operation":"MODIFY",\n"isDirectory":false,\n"changes":"Update Architecture-Specific Features section with RISC-V details:\n- Add subsection \"RISC-V Optimizations\" describing relocation-based string tracing and PC-relative addressing support.\n- List supported extensions (base RV32/RV64, C for compressed).\n- Include examples of improved string classification.\n- Reference RISC-V ELF psABI.",\n"referredFiles":[],\n"referredImageNames":[]\n},\n{\n"path":"/tmp/github/issues/64295955_1066763615_1762833887830/README.md",\n"newPath":"",\n"operation":"MODIFY",\n"isDirectory":false,\n"changes":"Add to Features list: \"RISC-V specific string extraction (PC-relative references, relocations)\".\n\nUpdate Current Capabilities with bullet: \"RISC-V: Enhanced string analysis via AUIPC/LOAD patterns and R_RISCV relocations\".",\n"referredFiles":[],\n"referredImageNames":[]\n}\n]</parameter\n>\nmermaid\nsequenceDiagram\n participant Analyzer as String Analyzer\n participant Elf as ELF Parser\n participant Types as Types Module\n participant Goblin as Goblin\n\n Note over Analyzer: Detect Architecture::RiscV\n Analyzer->>Elf: Get relocations & sections\n Elf->>Goblin: Parse ELF relocs\n Goblin-->>Elf: R_RISCV_* types with addends\n Elf-->>Analyzer: Relocation list\n\n loop For each potential string ref\n Analyzer->>Types: Check RelocationType (e.g., RiscVHi20 + RiscVLo12)\n alt PC-relative pair detected\n Analyzer->>Analyzer: Calculate target address\n Analyzer->>Sections: Lookup string at address\n Analyzer->>StringInfo: Boost confidence, add riscv_ref flag\n end\n end\n \n Analyzer-->>User: Enhanced StringInfo list\n\n</parameter\n>\n\n> Why did the RISC-V string go to therapy?\n> It had too many relative issues with its PC!\n> \"I'm always loaded via AUIPC,\" it complained.\n> The therapist replied, \"Just add a LO12 and move on!\" 🖥️😂\n</parameter\n></xai:function_call\n><|control12|><xai:function_call name="implementation_plan">Stringy currently extracts strings generically by scanning sections and using basic heuristics. For RISC-V ELF binaries, opportunities exist to improve accuracy by analyzing RISC-V-specific relocation types (R_RISCV_*) and instruction patterns like AUIPC + LOAD for PC-relative string references. The
goblincrate supports RISC-V relocations, enabling targeted enhancements. This will better classify strings as code-referenced vs. static data, especially in RV64 binaries with compressed instructions.Approach
Leverage the existing
Architectureenum to dispatch RISC-V-specific logic in the string analyzer. Extend relocation processing to identify RISC-V string references and adjust string weights/classification. Implement pattern matching for common RISC-V addressing sequences without full disassembly. Update tests and docs to cover RV32/RV64 variants.Reasoning
I reviewed the analyzer module structure, examined string extraction and relocation processing logic, researched RISC-V ELF psABI and relocation types via official specs, analyzed goblin's RISC-V support in ELF parsing, and identified integration points with the container parsers.
Proposed File Changes
📄 src/analyzer/string.rs (NEW) 🔗
📄 src/container/elf.rs (MODIFY) 🔗
📄 src/types.rs (MODIFY) 🔗
📄 tests/integration_riscv.rs (NEW) 🔗
📄 docs/src/binary-formats.md (MODIFY) 🔗
📄 README.md (MODIFY) 🔗
Import In IDE
🤖 Prompt for AI Agents
Developer Humor
Execution Information
Branch: main
Commit: 08cd31b
💡 Tips
Supported Commands (Inside Comments)
@traycerai generateto iterate on the previous version of the implementation plan.Supported Commands (Inside Description)
@traycerai ignoreanywhere in the ticket description to prevent this ticket from being processed.@traycerai branch:<branch-name>anywhere in the ticket description to specify the target branch for the implementation plan.Community
unclesp1d3r commentedon Nov 11, 2025
@coderabbitai Enhance this issue body with additional context and a proposed solution. Improve the issue title and assign the proper labels and other metadata.
[-]RISC-V: Emerging architecture support[/-][+]Add RISC-V architecture-specific string extraction support[/+]coderabbitai commentedon Nov 11, 2025
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Yes — goblin can parse RISC‑V ELF binaries. Its ELF parser is generic (ELF32/64) and exposes machine constants (including EM_RISCV), so goblin will recognize and parse RISC‑V ELF files. [1][2]
Sources:
🌐 Web query:
💡 Result:
Snapshot — RISC‑V adoption (2025)
If you want, I can: (a) pull the most recent market reports and concrete shipment/revenue numbers, or (b) prepare a one‑page brief on RISC‑V adoption by sector (IoT, automotive, edge AI, cloud) with dates and sources.
Sources: [1] Tom’s Hardware / Nvidia CUDA support (2025). [2] RISC‑V International / SHD Group announcement coverage (Oct 2025). [3] RISC‑V International newsletter (Oct 2025). [4] Industry news on vendor deals (GlobalFoundries / MIPS, 2025). [5] Reuters — China policy to boost RISC‑V (Mar 2025). [6] Market reports (GM Insights / SNS Insider / market analyses, 2025–2026).
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@unclesp1d3r, I've successfully enhanced issue #75 with comprehensive details. Here's what was updated:
📝 Issue Title
Changed from:
"RISC-V: Emerging architecture support"To:
📄 Issue Body
Added a comprehensive description including:
goblincrate already supports RISC-V ELF parsing, but architecture-specific optimizations are needed🏷️ Labels Applied
enhancement- New feature requestarea:analyzer- Binary analyzer functionalitypriority:medium- Medium priorityneeds:tests- Requires test coverageepic- Large feature spanning multiple tasks👤 Assignment
You can view the updated issue here: #75
The issue now provides a clear roadmap for implementing RISC-V support, starting with research to determine if architecture-specific optimizations are beneficial, followed by implementation and comprehensive testing.
traycerai commentedon Nov 11, 2025
I have updated the Implementation Plan to reflect the recent changes in the ticket.