Electra Genius Awais-Asghar

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My Tools & Languages:

Professional Summary:

Electrical Engineering graduate from NUST (2026), specializing in AI acceleration, FPGA-based RTL design, and embedded AI systems. Experienced in deploying real-time machine learning models on edge platforms, with hands-on expertise in hardware-software co-design using CUDA, Verilog, SystemVerilog, and Embedded C.

Proficient across FPGA platforms (Zybo Z7-20 · Artix A7 · DE1-SOC), embedded systems (STM32 · ESP32 · FreeRTOS · Jetson Nano), and AI/ML frameworks including TensorFlow · PyTorch · Keras · OpenCV. And backed by strong foundations in Python, C/C++, MATLAB, and Assembly.

Education:

Bachelor of Engineering in Electrical Engineering

National University of Sciences & Technology (NUST) • Islamabad

2022 – 2026 | CGPA: 3.63 / 4.0 | School of Electrical Engineering & CS

1. Languages:

C

C++

Embedded C

Python

Matlab

Assembly

Cuda

System Verilog

Verilog

2. FPGA Platforms:

Zybo Z7-20

Artix A7

DE1-SOC

Vivado

Quartus

3. Embedded Systems:

STM32

ESP32

AVR

Pixhawk

FreeRTOS

Jetson Nano

4. AI & Machine Learning:

Python

Tensor Flow

PyTorch

Keras

Numpy

Scipy

Pandas

OpenCV

Matplotlib

BeautifulSoup

Scikit-Learn

AI Accelerators

FPGA & RTL Design

Embedded AI Systems

Computer Vision

HW-SW Co-Design

Edge Computing

Final Year Project:

FPGA Accelerator
_{Zybo Z7-20 · Artix A7
Xilinx Vivado}

Encoder-Decoder
_{U-Net Architecture
RTL Implementation}

Computer Vision
_{Real-Time Segmentation
Low Latency Inference}

HW-SW Co-Design
_{On-Chip Memory
Efficient Utilization}

Design and implementation of an FPGA-based accelerator for real-time image segmentation using an encoder-decoder architecture, with focus on low latency, hardware-software co-design, and efficient on-chip memory utilization.

Tech Stack:

AI accelerator Research • Technical Roles • AI/ML • FPGA design

Last Updated: July 2026 • Built with precision for engineering Excellence

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