diff --git a/.github/workflows/daily-tests.yml b/.github/workflows/daily-tests.yml
index 139c946c3d84..8ea74fefa358 100644
--- a/.github/workflows/daily-tests.yml
+++ b/.github/workflows/daily-tests.yml
@@ -35,9 +35,6 @@ jobs:
   main-PR-workflows:
     uses: ./.github/workflows/pull-request.yml
 
-  XTOS-reproducible:
-    uses: ./.github/workflows/repro-build.yml
-
   rimage:
     uses: ./.github/workflows/rimage.yml
 
diff --git a/.github/workflows/repro-build.yml b/.github/workflows/repro-build.yml
deleted file mode 100644
index e1a122fde89e..000000000000
--- a/.github/workflows/repro-build.yml
+++ /dev/null
@@ -1,38 +0,0 @@
----
-# SPDX-License-Identifier: BSD-3-Clause
-# Tools that can save round-trips to github and a lot of time:
-#
-# yamllint -f parsable this.yml
-# pip3 install ruamel.yaml.cmd
-# yaml merge-expand this.yml exp.yml && diff -w -u this.yml exp.yml
-#
-# github.com also has a powerful web editor that can be used without
-# committing.
-
-name: Reproducible builds
-
-# yamllint disable-line rule:truthy
-on: [pull_request, workflow_dispatch, workflow_call]
-
-permissions:
-  contents: read
-
-# Group workflows together to cancel outdated runs, do not cancel manual runs
-concurrency:
-  group: "${{ github.workflow }}-${{ github.event_name }}-\
-          ${{ github.event_name == 'pull_request' && github.ref || github.run_id }}"
-  cancel-in-progress: true
-
-jobs:
-  main:
-    runs-on: ubuntu-26.04
-
-    steps:
-      - uses: actions/checkout@3d3c42e5aac5ba805825da76410c181273ba90b1  # v7.0.1
-        with: {fetch-depth: 0, submodules: recursive, filter: 'tree:0'}
-
-      - name: docker pull
-        run: docker pull thesofproject/sof &&  docker tag thesofproject/sof sof
-
-      - name: repro test
-        run: ./scripts/docker-run.sh ./scripts/test-repro-build.sh
diff --git a/.github/workflows/tools.yml b/.github/workflows/tools.yml
index b27f26694380..de2e50c5eb45 100644
--- a/.github/workflows/tools.yml
+++ b/.github/workflows/tools.yml
@@ -84,32 +84,3 @@ jobs:
         run: CMAKE_BUILD_TYPE=Release ./sof/scripts/build-tools.sh ||
              VERBOSE=1 NO_PROCESSORS=1 USE_XARGS=no
              CMAKE_BUILD_TYPE=Release ./sof/scripts/build-tools.sh
-
-
-  SOF-alsa-plugin:
-    # TODO: Update ubuntu to 26.04 when openvino situation is resolved
-    # It's not in the base ubuntu 26.04 OS and installation fails
-    # https://github.com/openvinotoolkit/openvino/issues/37509
-    runs-on: ubuntu-24.04
-    steps:
-      - uses: actions/checkout@3d3c42e5aac5ba805825da76410c181273ba90b1  # v7.0.1
-        with: {filter: 'tree:0'}
-
-      - name: apt install
-        run: sudo apt-get update;
-          sudo apt-get -y install ninja-build libasound2-dev
-
-      # One space character is enough to detect most quoting issues
-      - name: configure
-        run: cmake -GNinja -B 'build plugin' -S tools/plugin
-          -GNinja -Wdev -Werror=dev --warn-uninitialized
-
-      # Retry with -j1 in case of error because parallel builds drown error
-      # messages.
-      - name: build ExternalProjects first to avoid build race condition
-        run: cmake --build 'build plugin' -- sof_ep parser_ep ||
-             cmake --build 'build plugin' -- sof_ep parser_ep -j1
-
-      - name: Remaining build steps
-        run: cmake --build 'build plugin' ||
-             cmake --build 'build plugin' -j1
diff --git a/.github/workflows/zephyr.yml b/.github/workflows/zephyr.yml
index de055e5b25e2..9751b628a3c3 100644
--- a/.github/workflows/zephyr.yml
+++ b/.github/workflows/zephyr.yml
@@ -235,6 +235,19 @@ jobs:
             --no-tarball \
             ${{ matrix.build_opts }} ${{ matrix.IPC_platforms }}
 
+      # Informational only for now, see scripts/check_kernel_includes.py
+      - name: kernel/user-space include report
+        if: always()
+        env:
+          PLATFORMS: ${{ matrix.IPC_platforms }}
+        run: |
+          for p in $PLATFORMS; do
+            test -f build-"$p"/build.ninja || continue
+            printf '\n==== %s ====\n' "$p"
+            ZEPHYR_BASE="$(pwd)"/zephyr \
+              python3 sof/scripts/check_kernel_includes.py --summary build-"$p" || true
+          done
+
       - name: Upload build artifacts
         uses: actions/upload-artifact@043fb46d1a93c77aae656e7c1c64a875d1fc6a0a  # v7.0.1
         if: always()
diff --git a/CMakeLists.txt b/CMakeLists.txt
index 65747ffe1a8f..1fe6aa02b614 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -15,24 +15,21 @@ set(PYTHON3 "${Python3_EXECUTABLE}")
 
 option(BUILD_UNIT_TESTS "Build unit tests" OFF)
 option(BUILD_UNIT_TESTS_HOST "Build unit tests for host" OFF)
-option(BUILD_UNIT_TESTS_XTENSA_GCC "Build xtensa unit test using GCC" OFF)
-option(BUILD_CLANG_SCAN "Build for clang's scan-build" OFF)
 option(BUILD_COUNTERS "Enable build counter(s), timestamps and any other
 non-deterministic build features" OFF)
 
-if(CONFIG_LIBRARY OR BUILD_UNIT_TESTS_HOST OR CONFIG_ZEPHYR_POSIX)
-	set(ARCH host)
-else()
-	# firmware build supports only xtensa arch for now
-	set(ARCH xtensa)
+if(BUILD_UNIT_TESTS AND NOT BUILD_UNIT_TESTS_HOST)
+	message(FATAL_ERROR "Unit tests can only be built for the host, "
+		"use -DBUILD_UNIT_TESTS_HOST=ON")
 endif()
 
-# let user override built-in toolchains
-if(DEFINED CMAKE_TOOLCHAIN_FILE)
-	set(TOOLCHAIN "${CMAKE_TOOLCHAIN_FILE}")
-else()
-	include(scripts/cmake/${ARCH}-toolchain.cmake OPTIONAL)
+# The firmware is built with Zephyr (scripts/xtensa-build-zephyr.py), this
+# top-level project only builds the host library and the unit tests.
+if(NOT (CONFIG_LIBRARY OR BUILD_UNIT_TESTS_HOST OR CONFIG_ZEPHYR_POSIX))
+	message(FATAL_ERROR "The XTOS firmware build has been removed, "
+		"use scripts/xtensa-build-zephyr.py to build the firmware")
 endif()
+set(ARCH host)
 
 include(scripts/cmake/misc.cmake)
 
@@ -117,11 +114,7 @@ target_include_directories(sof_public_headers INTERFACE ${GENERATED_DIRECTORY}/i
 include(scripts/cmake/uuid-registry.cmake)
 
 if(CONFIG_LIBRARY)
-	if (CONFIG_LIBRARY_STATIC)
-		add_library(sof STATIC "")
-	else()
-		add_library(sof SHARED "")
-	endif()
+	add_library(sof STATIC "")
 	target_link_libraries(sof PRIVATE sof_options)
 	target_link_libraries(sof PRIVATE sof_static_libraries)
 	install(TARGETS sof DESTINATION lib)
@@ -153,39 +146,4 @@ if(BUILD_UNIT_TESTS)
 	enable_testing()
 	add_subdirectory(src/arch/${ARCH})
 	add_subdirectory(test)
-	# rest of this file is not needed for unit tests
-	return()
-endif()
-
-# for FW just install api folders
-install(
-	DIRECTORY
-		${PROJECT_SOURCE_DIR}/src/include/ipc
-		${PROJECT_SOURCE_DIR}/src/include/kernel
-		${PROJECT_SOURCE_DIR}/src/include/user
-		${RIMAGE_TOP}/src/include/sof/kernel
-		${RIMAGE_TOP}/src/include/sof/user
-	DESTINATION include/sof
-	PATTERN "*.h"
-)
-
-add_library(sof_ld_flags INTERFACE)
-add_library(sof_ld_scripts INTERFACE)
-
-target_include_directories(sof_public_headers INTERFACE ${PROJECT_SOURCE_DIR}/third_party_include)
-link_directories(${PROJECT_SOURCE_DIR}/third_party_libraries)
-
-# declare target with no sources to let cmake know about it
-add_executable(sof "")
-target_link_libraries(sof PRIVATE sof_options)
-target_link_libraries(sof PRIVATE sof_ld_scripts)
-target_link_libraries(sof PRIVATE sof_ld_flags)
-target_link_libraries(sof PRIVATE sof_static_libraries)
-
-if (BUILD_COUNTERS)
-sof_add_build_counter_rule()
 endif()
-
-add_subdirectory(src)
-
-sof_append_relative_path_definitions(sof)
diff --git a/CODEOWNERS b/CODEOWNERS
index 9cd3ec9bcb48..88e3eab8d843 100644
--- a/CODEOWNERS
+++ b/CODEOWNERS
@@ -16,7 +16,6 @@ src/include/ipc/**			@randerwang @tmleman @pblaszko
 src/include/ipc4/**			@randerwang @tmleman @pblaszko
 src/include/kernel/**			@thesofproject/steering-committee
 src/include/user/**			@thesofproject/steering-committee
-src/include/sof/debug/gdb/*		@abonislawski
 src/include/sof/audio/aria/*		@abonislawski
 src/include/sof/audio/kpb.h		@fkwasowi @iganakov
 src/include/sof/audio/mux.h		@fkwasowi
@@ -48,23 +47,20 @@ src/audio/module_adapter/*		@ranj063 @jxstelter
 src/audio/google/*			@thesofproject/google
 
 # platforms
-src/arch/xtensa/debug/gdb/*		@abonislawski
 src/platform/imx8/**			@dbaluta
 src/platform/amd/**			@bhiregoudar @sunilkumardommati
-src/platform/mt8195/**		@yaochunhung @kuanhsuncheng
+src/platform/mtk/**			@yaochunhung @kuanhsuncheng
 
 # drivers
 src/drivers/intel/dmic.c		@singalsu
 src/drivers/imx/**			@dbaluta
-src/drivers/dw/*			@lyakh
 src/drivers/amd/*			@bhiregoudar @sunilkumardommati
-src/drivers/mediatek/mt8195/*		@yaochunhung @kuanhsuncheng
+src/drivers/mediatek/**		@yaochunhung @kuanhsuncheng
 
 # other libs
 src/math/*				@singalsu
 src/ipc/*				@bardliao @tmleman @pblaszko
 # src/lib/*				TODO
-src/debug/gdb/*				@abonislawski
 src/schedule				@pblaszko @marcinszkudlinski @dbaluta @LaurentiuM1234
 
 # samples
@@ -92,9 +88,6 @@ zephyr/lib/cpu.c			@tmleman
 zephyr/lib/alloc.c			@dabekjakub
 zephyr/lib/regions_mm.c			@dabekjakub
 
-# installer
-# installer/**				TODO
-
 # CMake
 
 # Include only "top-level" CMakeLists.txt files; the other ones are just
diff --git a/Kconfig.sof b/Kconfig.sof
index df63811e652b..3c8d8af05db9 100644
--- a/Kconfig.sof
+++ b/Kconfig.sof
@@ -72,12 +72,6 @@ config DEBUG
 	help
 	  Select for debug build
 
-config GDB_DEBUG
-	bool "GDB Stub"
-	default n
-	help
-	  Select for GDB debugging
-
 config DEBUG_MEMORY_USAGE_SCAN
 	bool "Memory usage scan"
 	default y
diff --git a/doc/sof.doxygen.in b/doc/sof.doxygen.in
index 7aa4dc0dcc5e..02750d0f324f 100644
--- a/doc/sof.doxygen.in
+++ b/doc/sof.doxygen.in
@@ -17,7 +17,6 @@ INPUT            = @top_srcdir@/src/include/ipc \
                    @top_srcdir@/src/include/kernel \
                    @top_srcdir@/src/include/user \
                    @top_srcdir@/src/include/sof \
-                   @top_srcdir@/xtos/include \
                    @top_srcdir@/zephyr/include \
                    @top_srcdir@/doc/groups.dox \
                    @top_srcdir@/doc/mainpage.dox
@@ -62,7 +61,6 @@ PREDEFINED	 = "__attribute__(x)= " \
 		   "CONFIG_SOF_USERSPACE_USE_SHARED_HEAP=1" \
 		   "CONFIG_SOF_TELEMETRY_PERFORMANCE_MEASUREMENTS=1" \
 		   "CONFIG_INTEL_ADSP_DEBUG_SLOT_MANAGER=1" \
-		   "CONFIG_GDB_DEBUG=1" \
 		   "__DOXYGEN__=1" \
 		   "__coherent=" \
 		   "__syscall=" \
diff --git a/installer/.gitignore b/installer/.gitignore
deleted file mode 100644
index 24404a12cf22..000000000000
--- a/installer/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-/staging/sof*
diff --git a/installer/GNUmakefile b/installer/GNUmakefile
deleted file mode 100644
index 39eb635e4ebd..000000000000
--- a/installer/GNUmakefile
+++ /dev/null
@@ -1,348 +0,0 @@
-
-# SPDX-License-Identifier: BSD-3-Clause
-# Copyright(c) 2021 Intel Corporation
-
-
-.DEFAULT_GOAL := stage
-.PHONY: clean stage rsync tarball
-.PHONY: signed unsigned ldicts topologies tools build_tools
-.PHONY: compare signed_dummies
-
-# Override ?= variables in config.mk
--include config.mk
-
-# The default values of UNSIGNED_list and SIGNED_list used to be the
-# list of /lib/firmware/sof/ images and symbolic links officially
-# released by Intel at https://github.com/thesofproject/sof-bin
-#
-# All Intel firmware in this branch is now Zephyr-based. So this
-# Makefile is NOT used anymore for sof-bin releases. However it is still
-# useful as a single command, fully parallelized and much faster
-# alternative to build: (1) all XTOS platforms currently supported by
-# scripts/xtensa-build-zephyr.sh -a (2) all user space tools (3) all
-# topologies.
-#
-# Using this script still builds a pseudo /lib/firmware/sof/ tree
-# structure in the staging directory - ignore that.
-
-# Keep this line in sync with the DEFAULT_PLATFORMS in
-# xtensa-build-zephyr.sh -a
-UNSIGNED_list ?= imx8m rn rmb vangogh mt8186 mt8195
-
-
-# To find aliases, try in a Linux kernel git clone:
-#
-#   git grep 'sof-.*\.ri' -- sound/soc/
-
-# ALIAS_OTHER_KEY_list += adl adl-s rpl rpl-s
-
-# Not supported in the main branch anymore, go to stable-v2.3
-# UNSIGNED_list += bdw byt cht
-# SIGNED_list   += apl cnl icl jsl
-# ALIAS_SAME_KEY_list  += glk cfl cml
-# ALIAS_OTHER_KEY_list += ehl
-
-# Much older platforms
-# UNSIGNED_list += hsw sue
-# SIGNED_list += kbl skl
-
-# Sample way to create a symbolic link in /lib/firmware/sof/
-# This requires adl-s to be listed in some ALIAS_some_list above.
-# target_of_adl-s := tgl-h
-
-ALIAS_list := ${ALIAS_SAME_KEY_list} ${ALIAS_OTHER_KEY_list}
-
-$(info UNSIGNED_list = ${UNSIGNED_list} )
-$(info SIGNED_list   = ${SIGNED_list}   )
-$(info ALIAS_list    = ${ALIAS_list}    )
-
-ifeq (,${TOOLCHAIN})
-  ifeq (,${XTENSA_TOOLS_ROOT})
-    TOOLCHAIN := gcc
-  else
-    TOOLCHAIN := xcc
-  endif
-endif
-
-TREE_OPTS ?= --sort=size --dirsfirst
-INSTALL_OPTS ?= -D -p -m 0664
-
-# Keep SOF_VERSION optional
-
-SOF_VERSION ?= $(shell git describe --dirty)
-ifneq (${SOF_VERSION},)
-VERSION_DIR := ${SOF_VERSION}/
-VERSION_SUFFIX := -${SOF_VERSION}
-endif
-
-
-
-      ################################
-      ###  Top-level directories  ####
-      ################################
-
-# Our input:  build_*_?cc/ directories
-BUILDS_ROOT ?= ${CURDIR}/../installer-builds
-BUILD_TOOLS ?= ${BUILDS_ROOT}/build_tools
-
-STAGING_SOF ?= staging/sof
-STAGING_SOF_VERSION := ${STAGING_SOF}${VERSION_SUFFIX}
-
-STAGING_SOF_TPLG ?= staging/sof-tplg
-
-STAGING_TOOLS ?= staging/tools
-
-stage: signed unsigned ldicts aliases topologies tools
-	test -n "${UNSIGNED_list}${SIGNED_list}" # is there any FW to stage?
-ifneq (${STAGING_SOF_VERSION},${STAGING_SOF})
-	ln -sfT sof${VERSION_SUFFIX} ${STAGING_SOF}
-	test -e ${STAGING_SOF}
-endif
-	@file ${STAGING_SOF}
-	@tree ${TREE_OPTS} ${STAGING_SOF_VERSION}
-
-COMMUNITY	:= ${STAGING_SOF_VERSION}/community
-INTEL_SIGNED	:= ${STAGING_SOF_VERSION}/intel-signed
-${COMMUNITY} ${INTEL_SIGNED} ${BUILDS_ROOT} ${STAGING_SOF_VERSION}:
-	mkdir -p $@
-
-# The noise for incremental, do-nothing builds is incredible otherwise,
-# especially for build_tools
-GNUMAKEFLAGS = --no-print-directory
-
-      #####################################
-      ###    rsync to local or remote  ####
-      #####################################
-
-# Default value
-FW_DESTDIR ?= /lib/firmware/intel/
-
-# The rsync target does not depend on any other target so:
-# - it's possible to deploy a staging _subset_, e.g.: only topologies
-#   only,...
-# - "sudo make rsync" never builds as root by accident
-rsync:
-# The --mkpath option is too recent, dealing with both remote and local
-# would be complicated and this is also a safety against typos.
-	# The destination directory must already exist
-	rsync -a --info=progress2 staging/sof* "${FW_DESTDIR}"
-ifneq (${USER_DESTDIR},)
-	# TODO: add more user space binaries: sof-ctl, probes,...
-	# absorbe scripts/sof-target-install.sh
-	cd ${BUILD_TOOLS} && rsync -a ${TOOLS_RELPATHS} ${USER_DESTDIR}
-endif
-
-clean:
-	${RM} -r ${STAGING_SOF}* ${STAGING_SOF_TPLG}* ${STAGING_TOOLS}*
-	${RM} ${BUILDS_ROOT}/staging_sof_tree.txt
-
-cleanall: clean
-	${RM} -r "${BUILD_TOOLS}/" "${BUILDS_ROOT}"/build_*_?cc/
-
-
-      #####################################
-      ###           tarball            ####
-      #####################################
-
-tarball: stage
-	cd staging && tar cfz sof-build${VERSION_SUFFIX}.tgz \
-	  sof${VERSION_SUFFIX} sof-tplg${VERSION_SUFFIX} \
-	  tools${VERSION_SUFFIX}
-
-
-      #####################################
-      ###           Stage tools        ####
-      #####################################
-
-# This is only for the tarball, rsync takes the RELPATHS shortcut
-tools: build_tools
-	mkdir -p ${STAGING_TOOLS}${VERSION_SUFFIX}
-	cd ${BUILD_TOOLS} && \
-	  cp -p ${TOOLS_RELPATHS} ${CURDIR}/${STAGING_TOOLS}${VERSION_SUFFIX}
-
-   ##########################################################
-   ###  Stage sof-*.ri firmware files and symbolic links ####
-   ##########################################################
-
-#
-# 1. Stages all *.ri files
-#
-# 2. Create symbolic links, including (broken) intel-signed symbolic
-#    links that must be fixed in a final release, otherwise the release
-#    is incomplete. To check all symlinks: file $(find -type l)
-#
-
-# '%' is the platform name
-SIGNED_FWS := ${SIGNED_list:%=${COMMUNITY}/sof-%.ri}
-# $(info SIGNED_FWS = ${SIGNED_FWS})
-signed: ${SIGNED_FWS}
-${SIGNED_FWS}: ${COMMUNITY}/sof-%.ri:    \
-               ${BUILDS_ROOT}/build_%_${TOOLCHAIN}/sof.ri     \
-	     | ${COMMUNITY} ${INTEL_SIGNED}
-	install ${INSTALL_OPTS} $< $@
-	ln -sfT     intel-signed/sof-$*.ri ${STAGING_SOF_VERSION}/sof-$*.ri
-
-# '%' is the platform name
-UNSIGNED_FWS := ${UNSIGNED_list:%=${STAGING_SOF_VERSION}/sof-%.ri}
-# $(info UNSIGNED_FWS = ${UNSIGNED_FWS})
-unsigned: ${UNSIGNED_FWS}
-${UNSIGNED_FWS}: ${STAGING_SOF_VERSION}/sof-%.ri:   \
-                 ${BUILDS_ROOT}/build_%_${TOOLCHAIN}/sof.ri
-	install ${INSTALL_OPTS} $< $@
-
-
-BUILD_SOF_RIS := \
-      ${UNSIGNED_list:%=${BUILDS_ROOT}/build_%_${TOOLCHAIN}/sof.ri} \
-        ${SIGNED_list:%=${BUILDS_ROOT}/build_%_${TOOLCHAIN}/sof.ri}
-
-# When the build is not deterministic use this to reduce noise when testing
-# this Makefile.
-# Also very useful with XCC, see next comment.
-ifneq (true,${BUILD_ONLY_ONCE})
-.PHONY: ${BUILD_SOF_RIS}
-endif
-
-# Incremental builds are not possible with XCC because the entire
-# toolchain requires $XTENSA_SYSTEM but CMake does not support
-# build-time environment variables. In the future we could move the
-# XTENSA_SYSTEM values out of xtensa-build-all.sh and into some shared
-# config file included here.
-${BUILD_SOF_RIS}: ${BUILDS_ROOT}/build_%_${TOOLCHAIN}/sof.ri: | ${BUILDS_ROOT}
-	cd ${BUILDS_ROOT} && bdir="$$(dirname $@)" &&  \
-      if [ -e $${bdir}/build.ninja -o -e $${bdir}/Makefile ] && \
-          [ xcc != "${TOOLCHAIN}" ] ; then \
-        cmake --build $${bdir} -- bin; else \
-      $(CURDIR)/../scripts/xtensa-build-all.sh -i "${IPC_VERSION}" $*; fi
-
-
-       ########################################
-       ###  Stage *.ldc logger dictionaries ###
-       ########################################
-
-# '%' is the platform name
-LDICTS := ${UNSIGNED_list:%=${STAGING_SOF_VERSION}/sof-%.ldc} \
-            ${SIGNED_list:%=${STAGING_SOF_VERSION}/sof-%.ldc}
-# $(info LDICTS = ${LDICTS})
-ldicts: ${LDICTS}
-${LDICTS}: ${STAGING_SOF_VERSION}/sof-%.ldc:  \
-                                ${BUILDS_ROOT}/build_%_${TOOLCHAIN}/sof.ri
-	if test -e ${BUILDS_ROOT}/build_$*_${TOOLCHAIN}/sof.ldc; then \
-	install ${INSTALL_OPTS} ${BUILDS_ROOT}/build_$*_${TOOLCHAIN}/sof.ldc $@ ; \
-	else printf '# CONFIG_TRACE was disabled\n' > $@; fi
-
-
-        #######################################
-        ###  Platform -> platform aliases  ####
-        #######################################
-
-# '%' is the platform name
-COMM_ALIASES   := ${ALIAS_list:%=${STAGING_SOF_VERSION}/community/sof-%.ri}
-DICT_ALIASES   := ${ALIAS_list:%=${STAGING_SOF_VERSION}/sof-%.ldc}
-
-${COMM_ALIASES}: ${STAGING_SOF_VERSION}/community/sof-%.ri: | ${COMMUNITY}
-	ln -sfT sof-${target_of_$*}.ri $@
-
-${DICT_ALIASES}: ${STAGING_SOF_VERSION}/sof-%.ldc: | ${STAGING_SOF_VERSION}
-	ln -sfT sof-${target_of_$*}.ldc $@
-
-# ->intel-signed/ symlinks for platform aliases. The other, identical
-# looking ->intel-signed/ symlinks for the other, "normal" platforms are
-# created here but by the signed: target.
-#
-# Some have the same key, others just the code. We don't make any
-# difference, no platform re-direction here, this is merely pointing at
-# ->intel-signed/same.ri
-SIGNED_ALIASES := ${ALIAS_list:%=${STAGING_SOF_VERSION}/sof-%.ri}
-${SIGNED_ALIASES}: ${STAGING_SOF_VERSION}/sof-%.ri: | ${STAGING_SOF_VERSION}
-	ln -sfT intel-signed/sof-$*.ri $@
-
-# Platform indirection inside the intel-signed/ directory
-SIGNED_PLATFORM_ALIASES := ${ALIAS_SAME_KEY_list:%=${INTEL_SIGNED}/sof-%.ri}
-${SIGNED_PLATFORM_ALIASES}: ${INTEL_SIGNED}/sof-%.ri: | ${INTEL_SIGNED}
-	ln -sfT sof-${target_of_$*}.ri $@
-
-
-aliases: ${COMM_ALIASES} ${DICT_ALIASES} ${SIGNED_ALIASES} \
-         ${SIGNED_PLATFORM_ALIASES}
-
-            ##################################
-            ### Stage sof-tplg/ topologies ###
-            ##################################
-
-# The build is not deterministic; use this to reduce noise when testing
-# this Makefile
-ifneq (true,${BUILD_ONLY_ONCE})
-.PHONY: ${BUILD_TOOLS}
-endif
-
-# Deploy and release only "official", top-level topology files starting
-# with the 'sof-' prefix to avoid any experimental stuff.
-topologies: ${BUILD_TOOLS}
-	install ${INSTALL_OPTS}  -t ${STAGING_SOF_TPLG}${VERSION_SUFFIX}/ \
-               ${BUILD_TOOLS}/topology/sof-*.tplg
-ifneq (,${VERSION_SUFFIX})
-	ln -sfT sof-tplg${VERSION_SUFFIX} ${STAGING_SOF_TPLG}
-	test -e ${STAGING_SOF_TPLG}
-endif
-	@file ${STAGING_SOF_TPLG}
-	@tree ${TREE_OPTS} ${STAGING_SOF_TPLG}${VERSION_SUFFIX} | \
-            head -n 10; printf '├── ...\n..\n'
-
-
-             ######################
-             ### build-tools.sh ###
-             ######################
-
-TOOLS_RELPATHS  := ctl/sof-ctl  logger/sof-logger  probes/sof-probes
-TOOLS_TARGETS   := sof-ctl      sof-logger         sof-probes
-TOOLS_FLAGS     := -c           -l                 -p
-
-.PHONY: build_tools
-build_tools: ${BUILD_TOOLS}
-
-# We could use more targets rather than "set -e" with a multi-lines "for" loop.
-# That would be more flexible but also quite verbose.
-${BUILD_TOOLS}:
-	set -e; if test -e ${BUILD_TOOLS}/build.ninja || \
-                   test -e ${BUILD_TOOLS}/Makefile; then \
-        for i in topologies ${TOOLS_TARGETS}; do \
-          cmake --build ${BUILD_TOOLS} -- $$i; done; else         \
-          BUILD_TOOLS_DIR=${BUILD_TOOLS} ../scripts/build-tools.sh -T ${TOOLS_FLAGS} ; \
-        fi
-
-
-             ####################
-             ### Self-Testing ###
-             ####################
-
-COMPARE_REFS ?= /lib/firmware/intel
-
-checktree:
-	cd ${STAGING_SOF_VERSION} && \
-             tree -a -v --dirsfirst . >  ${BUILDS_ROOT}/staging_sof_tree.txt
-	diff -u tests/staging_sof${IPC_VERSION}_ref.txt ${BUILDS_ROOT}/staging_sof_tree.txt
-	# Check two random topologies are there
-	test -f ${STAGING_SOF_TPLG}/sof-imx8-wm8960.tplg
-	for t in sof-ctl sof-logger sof-probes; do \
-	   test -f ${STAGING_TOOLS}${VERSION_SUFFIX}/$${t}; done
-
-# Useful for testing this Makefile. COMPARE_REFS can be /lib/firmware,
-# sof-bin, a previous version of this Makefile,...
-# As the first arguments maybe symbolic links, their trailing slash is
-# critical.
-compare: stage
-	! diff -qr --no-dereference ${COMPARE_REFS}/sof/ \
-             ${STAGING_SOF_VERSION}/ \
-             | grep -v ' differ$$' # || true
-	! diff -qr --no-dereference ${COMPARE_REFS}/sof-tplg/ \
-             ${STAGING_SOF_TPLG}${VERSION_SUFFIX}/ \
-             | grep -v ' differ$$'
-
-# Invoke this manually to check symbolic links are correct
-SIGNED_DUMMIES := ${SIGNED_list:%=${INTEL_SIGNED}/sof-%.ri} \
-                   ${ALIAS_OTHER_KEY_list:%=${INTEL_SIGNED}/sof-%.ri}
-signed_dummies: ${SIGNED_DUMMIES}
-	! file $$(find staging -type l) | grep -i broken
-
-${SIGNED_DUMMIES}: | ${INTEL_SIGNED}
-	touch $@
diff --git a/installer/README.md b/installer/README.md
deleted file mode 100644
index 5819a4a80d89..000000000000
--- a/installer/README.md
+++ /dev/null
@@ -1,85 +0,0 @@
-The GNUmakefile in this directory prepares ``/lib/firmware/intel/sof/`` and
-``/lib/firmware/intel/sof-tplg/`` directories.
-
-It extracts what's needed from the output of the scripts
-``./scripts/xtensa-build-all.sh`` and ``./scripts/build-tools.sh -T
--l``. It automatically runs these scripts when needed for the platforms
-listed in config.mk and performs incremental builds when they have
-already been run.
-
-It does not copy anything to ``/lib/firmware/`` directly but to local,
-"staging" subdirectory first. The staging area can then be installed with
-rsync to a local or remote ``/lib/firmware/intel/`` or to a release
-location. This gives an opportunity to inspect the staging area and
-avoids running everything as root.
-
-The default target (re-)generates the staging area:
-
-    make -C installer/
-
-Then, to install the staging area:
-
-    sudo make -C installer/ rsync
-
-By default, the "rsync" target installs to the local
-``/lib/firmware/intel/`` directory. To install to a different host or
-different directory, copy the ``sample-config.mk`` file to ``config.mk``
-and follow the instructions inside the file. ``config.mk`` can also be
-used to change the list of platforms installed and a number of other
-Make variables. As usual with Make, many parameters can also be
-overridden on the command line.
-
-To stage and install in one go:
-
-    make -C installer/ stage rsync
-
-"stage" is the default target and it tries to stage everything:
-firmware, dictionaries and topologies. As usual with Make, it's possible
-to invoke individual targets. Find a list of targets at the top of
-GNUMakefile.
-
-You can use `make -jN stage` to build multiple platforms faster but do
-*not* `make -jN stage rsync` as this will start deploying before the
-builds are all complete. That's because we want the rsync target to be
-able to deploy subsets. Instead do: `make -jN somethings && make rsync`.
-
-Sample output:
-
-    staging/sof: symbolic link to sof-v1.6.1
-    staging/sof-v1.6.1/
-    ├── community/
-    │   ├── sof-tgl.ri
-    │   ├── sof-cnl.ri
-    │   ├── sof-icl.ri
-    │   ├── sof-jsl.ri
-    │   ├── sof-apl.ri
-    │   ├── sof-cfl.ri -> sof-cnl.ri
-    │   ├── sof-cml.ri -> sof-cnl.ri
-    │   ├── sof-ehl.ri -> sof-tgl.ri
-    │   └── sof-glk.ri -> sof-apl.ri
-    ├── intel-signed/
-    ├── sof-bdw.ri
-    ├── sof-cht.ri
-    ├── sof-byt.ri
-    ├── sof-cnl.ldc
-    ├── sof-tgl.ldc
-    ├── sof-icl.ldc
-    ├── sof-jsl.ldc
-    ├── sof-apl.ldc
-    ├── sof-bdw.ldc
-    ├── sof-byt.ldc
-    ├── sof-cht.ldc
-    ├── sof-apl.ri -> intel-signed/sof-apl.ri
-    ├── sof-cfl.ri -> intel-signed/sof-cfl.ri
-    ├── sof-cml.ri -> intel-signed/sof-cml.ri
-    ├── sof-cnl.ri -> intel-signed/sof-cnl.ri
-    ├── sof-ehl.ri -> intel-signed/sof-ehl.ri
-    ├── sof-glk.ri -> intel-signed/sof-glk.ri
-    ├── sof-icl.ri -> intel-signed/sof-icl.ri
-    ├── sof-jsl.ri -> intel-signed/sof-jsl.ri
-    ├── sof-tgl.ri -> intel-signed/sof-tgl.ri
-    ├── sof-cfl.ldc -> sof-cnl.ldc
-    ├── sof-cml.ldc -> sof-cnl.ldc
-    ├── sof-ehl.ldc -> sof-tgl.ldc
-    └── sof-glk.ldc -> sof-apl.ldc
-
diff --git a/installer/sample-config.mk b/installer/sample-config.mk
deleted file mode 100644
index 870f83a0a1ce..000000000000
--- a/installer/sample-config.mk
+++ /dev/null
@@ -1,37 +0,0 @@
-# To customize the installation, copy this file to config.mk and edit
-# it. Leave undefined to use default values.
-
-# As usual with Make, all these can also be passed as either CLI
-# arguments or environment variables.  Warning: undefined is NOT the
-# same as blank!
-
-# You MUST "make cleanall" after changing anything here
-
-# Everything is installed by default. To install and deploy fewer
-# patforms override the default lists like this:
-# UNSIGNED_list :=
-# SIGNED_list := apl tgl
-
-# The default FW_DESTDIR is the local /lib/firmware/intel directory
-# _remote := test-system.local
-# FW_DESTDIR     := root@${_remote}:/lib/firmware/intel
-# USER_DESTDIR   := ${_remote}:bin/
-
-# Passed to ./scripts/xtensa-build-all.sh -i
-# Ignored by incremental builds, MUST cleanall after changing this
-# IPC_VERSION    := IPC4
-
-# Define this empty for a plain sof/ directory and no sof -> sof-v1.2.3
-# symbolic links. This is _only_ to override the top-level directory
-# name; for sof_versions.h see version.cmake and try sof/.tarball-version
-# SOF_VERSION :=
-#
-# SOF_VERSION := $(shell git describe --tags )
-# SOF_VERSION := v1.6.14
-
-# Uncomment this to have the build_*_?cc/ directories at the top-level
-# BUILDS_ROOT := ${CURDIR}/..
-
-# The build is not deterministic; use this to reduce noise when testing
-# the installer/ itself
-# BUILD_ONLY_ONCE := true
diff --git a/installer/tests/staging_sofIPC4_ref.txt b/installer/tests/staging_sofIPC4_ref.txt
deleted file mode 100644
index 2cad7d207e4b..000000000000
--- a/installer/tests/staging_sofIPC4_ref.txt
+++ /dev/null
@@ -1,23 +0,0 @@
-.
-├── community
-│   ├── sof-adl-s.ri -> sof-tgl-h.ri
-│   ├── sof-adl.ri -> sof-tgl.ri
-│   ├── sof-rpl-s.ri -> sof-tgl-h.ri
-│   ├── sof-rpl.ri -> sof-tgl.ri
-│   ├── sof-tgl-h.ri
-│   └── sof-tgl.ri
-├── intel-signed
-├── sof-adl-s.ldc -> sof-tgl-h.ldc
-├── sof-adl-s.ri -> intel-signed/sof-adl-s.ri
-├── sof-adl.ldc -> sof-tgl.ldc
-├── sof-adl.ri -> intel-signed/sof-adl.ri
-├── sof-rpl-s.ldc -> sof-tgl-h.ldc
-├── sof-rpl-s.ri -> intel-signed/sof-rpl-s.ri
-├── sof-rpl.ldc -> sof-tgl.ldc
-├── sof-rpl.ri -> intel-signed/sof-rpl.ri
-├── sof-tgl-h.ldc
-├── sof-tgl-h.ri -> intel-signed/sof-tgl-h.ri
-├── sof-tgl.ldc
-└── sof-tgl.ri -> intel-signed/sof-tgl.ri
-
-2 directories, 18 files
diff --git a/installer/tests/staging_sof_ref.txt b/installer/tests/staging_sof_ref.txt
deleted file mode 100644
index 7a5f6a92d5e2..000000000000
--- a/installer/tests/staging_sof_ref.txt
+++ /dev/null
@@ -1,5 +0,0 @@
-.
-├── sof-imx8m.ldc
-└── sof-imx8m.ri
-
-0 directories, 2 files
diff --git a/posix/include/rtos/alloc.h b/posix/include/rtos/alloc.h
index adb3c93bf9dd..61541172c0c3 100644
--- a/posix/include/rtos/alloc.h
+++ b/posix/include/rtos/alloc.h
@@ -7,7 +7,7 @@
  */
 
 /**
- * \file xtos/include/rtos/alloc.h
+ * \file posix/include/rtos/alloc.h
  * \brief Memory Allocation API definition
  * \author Liam Girdwood <liam.r.girdwood@linux.intel.com>
  * \author Keyon Jie <yang.jie@linux.intel.com>
diff --git a/posix/include/rtos/cache.h b/posix/include/rtos/cache.h
index 914e61b52984..d8650efed9da 100644
--- a/posix/include/rtos/cache.h
+++ b/posix/include/rtos/cache.h
@@ -6,7 +6,7 @@
  */
 
 /**
- * \file xtos/include/rtos/cache.h
+ * \file posix/include/rtos/cache.h
  * \brief Cache header file
  * \authors Tomasz Lauda <tomasz.lauda@linux.intel.com>
  */
diff --git a/posix/include/sof/compiler_info.h b/posix/include/sof/compiler_info.h
index 9716575b7188..bbef98902725 100644
--- a/posix/include/sof/compiler_info.h
+++ b/posix/include/sof/compiler_info.h
@@ -6,7 +6,7 @@
  */
 
 /**
- * \file xtos/include/sof/compiler_info.h
+ * \file posix/include/sof/compiler_info.h
  * \brief Compiler version and name descriptor
  * \author Karol Trzcinski <karolx.trzcinski@linux.intel.com>
  */
diff --git a/posix/include/sof/lib/cpu.h b/posix/include/sof/lib/cpu.h
index d53e15e7535a..b6e0fadb22c0 100644
--- a/posix/include/sof/lib/cpu.h
+++ b/posix/include/sof/lib/cpu.h
@@ -6,7 +6,7 @@
  */
 
 /**
- * \file xtos/include/sof/lib/cpu.h
+ * \file posix/include/sof/lib/cpu.h
  * \brief CPU header file
  * \authors Tomasz Lauda <tomasz.lauda@linux.intel.com>
  */
diff --git a/posix/include/sof/lib/dai.h b/posix/include/sof/lib/dai.h
index 47677c19ae4c..ddaca778c79d 100644
--- a/posix/include/sof/lib/dai.h
+++ b/posix/include/sof/lib/dai.h
@@ -7,7 +7,7 @@
  */
 
 /**
- * \file xtos/include/sof/lib/dai.h
+ * \file posix/include/sof/lib/dai.h
  * \brief DAI Drivers definition
  * \author Liam Girdwood <liam.r.girdwood@linux.intel.com>
  * \author Keyon Jie <yang.jie@linux.intel.com>
diff --git a/posix/include/sof/lib/dma.h b/posix/include/sof/lib/dma.h
index 4ed6a7d26edd..3135cf72e58a 100644
--- a/posix/include/sof/lib/dma.h
+++ b/posix/include/sof/lib/dma.h
@@ -7,7 +7,7 @@
  */
 
 /**
- * \file xtos/include/sof/lib/dma.h
+ * \file posix/include/sof/lib/dma.h
  * \brief DMA Drivers definition
  * \author Liam Girdwood <liam.r.girdwood@linux.intel.com>
  * \author Keyon Jie <yang.jie@linux.intel.com>
diff --git a/posix/include/sof/lib/perf_cnt.h b/posix/include/sof/lib/perf_cnt.h
index bddda9c8e06b..dfc1eb5eda31 100644
--- a/posix/include/sof/lib/perf_cnt.h
+++ b/posix/include/sof/lib/perf_cnt.h
@@ -6,7 +6,7 @@
  */
 
 /**
- * \file xtos/include/sof/lib/perf_cnt.h
+ * \file posix/include/sof/lib/perf_cnt.h
  * \brief Simple performance counters
  * \author Marcin Maka <marcin.maka@linux.intel.com>
  */
diff --git a/posix/include/sof/lib/pm_runtime.h b/posix/include/sof/lib/pm_runtime.h
index 4e8cbfdf146f..c5ffd850509f 100644
--- a/posix/include/sof/lib/pm_runtime.h
+++ b/posix/include/sof/lib/pm_runtime.h
@@ -7,7 +7,7 @@
  */
 
 /**
- * \file xtos/include/sof/lib/pm_runtime.h
+ * \file posix/include/sof/lib/pm_runtime.h
  * \brief Runtime power management header file
  * \author Tomasz Lauda <tomasz.lauda@linux.intel.com>
  */
diff --git a/scripts/README.md b/scripts/README.md
index 8833eb33e21e..e00606437b4a 100644
--- a/scripts/README.md
+++ b/scripts/README.md
@@ -26,14 +26,6 @@ source ~/work/sof/.venv/bin/activate
 ./scripts/xtensa-build-zephyr.py -p ptl
 ```
 
-### Reproducible Output Builds (`test-repro-build.sh`)
-
-This script can be used to locally reproduce the exact build steps and environment of specific CI validation tests.
-
-```bash
-./scripts/test-repro-build.sh --help
-```
-
 ## Tools and Topologies
 
 Tooling and topology can be built together using one script. To build all topologies please run:
@@ -135,19 +127,9 @@ cd scripts/docker_build
 ./docker-build.sh
 ```
 
-After the container is built, it can be used to run the scripts.
-
-To build for tigerlake:
-
-```bash
-./scripts/docker-run.sh ./scripts/xtensa-build-all.sh -l tgl
-```
-
-or (this command may prompt for a password during rimage installation inside the container)
-
-```bash
-./scripts/docker-run.sh ./scripts/xtensa-build-all.sh tgl
-```
+After the container is built, it can be used to run the host scripts. The
+firmware is built with the Zephyr SDK container instead, see
+`zephyr/docker-run.sh`.
 
 To rebuild the topology and logger:
 
diff --git a/scripts/check_kernel_includes.py b/scripts/check_kernel_includes.py
new file mode 100755
index 000000000000..3db354bbfd7d
--- /dev/null
+++ b/scripts/check_kernel_includes.py
@@ -0,0 +1,165 @@
+#!/usr/bin/env python3
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2026 Intel Corporation.
+"""Report kernel-only headers included by user-space SOF code.
+
+SOF is being partitioned into DSP kernel code (Zephyr supervisor mode:
+hardware, interrupts, threads, memory domains, power management, DMA and
+DAI driver internals) and user-space code (pipelines, modules and IPC
+processing that can run in Zephyr user threads). User-space code must
+not depend on kernel-only headers, but today most of it does through
+transitive includes.
+
+This script measures that. It reads the dependency information that the
+build already recorded (``ninja -t deps``), so what is checked is exactly
+what was compiled, and matches every object built from a user-space
+source against the kernel-only header patterns in
+scripts/kernel_user_partition.txt.
+
+By default it only reports. With --strict it exits with an error when any
+user-space object includes a kernel-only header; that is meant for the
+later phases of the partition work, once the leaks have been removed.
+
+Usage:
+    check_kernel_includes.py [--strict] [--summary] <build-dir> [<build-dir>...]
+"""
+
+import argparse
+import fnmatch
+import os
+import subprocess
+import sys
+from collections import defaultdict
+
+SOF_ROOT = os.path.dirname(os.path.dirname(os.path.abspath(__file__)))
+DEFAULT_MANIFEST = os.path.join(SOF_ROOT, 'scripts', 'kernel_user_partition.txt')
+SOURCE_EXTS = ('.c', '.cpp', '.cc', '.S')
+
+
+def parse_manifest(path):
+	"""Return {section: [glob, ...]} from a simple '[section]' + glob list file."""
+	sections = defaultdict(list)
+	section = None
+	with open(path, encoding='utf-8') as f:
+		for line in f:
+			line = line.split('#', 1)[0].strip()
+			if not line:
+				continue
+			if line.startswith('[') and line.endswith(']'):
+				section = line[1:-1]
+				continue
+			if section is None:
+				sys.exit(f'{path}: pattern "{line}" outside of a [section]')
+			sections[section].append(line)
+	return sections
+
+
+def matches(relpath, patterns):
+	return any(fnmatch.fnmatchcase(relpath, p) for p in patterns)
+
+
+def ninja_deps(build_dir):
+	"""Yield (object, [dependencies]) from the ninja dependency log."""
+	try:
+		out = subprocess.run(['ninja', '-C', build_dir, '-t', 'deps'],
+				     check=True, capture_output=True, text=True).stdout
+	except (OSError, subprocess.CalledProcessError) as e:
+		sys.exit(f'{build_dir}: cannot read ninja dependency log: {e}')
+
+	obj, deps = None, []
+	for line in out.splitlines():
+		if line.startswith((' ', '\t')):
+			if obj is not None and line.strip():
+				deps.append(line.strip())
+		elif ': #deps' in line:
+			if obj is not None:
+				yield obj, deps
+			obj, deps = line.split(': #deps', 1)[0], []
+	if obj is not None:
+		yield obj, deps
+
+
+def relative_to(path, root):
+	path = os.path.realpath(path)
+	root = os.path.realpath(root)
+	if path == root or path.startswith(root + os.sep):
+		return os.path.relpath(path, root)
+	return None
+
+
+def check_build(build_dir, manifest, sof_root, zephyr_base):
+	"""Return {user source: set(kernel headers)} for one build directory."""
+	user_src = manifest['user-sources']
+	not_user = manifest['not-user-sources']
+	kernel_hdr = manifest['kernel-headers']
+	zephyr_hdr = manifest['zephyr-kernel-headers']
+
+	leaks = defaultdict(set)
+	if not os.path.exists(os.path.join(build_dir, 'build.ninja')):
+		sys.exit(f'{build_dir}: not a ninja build directory')
+
+	for _, deps in ninja_deps(build_dir):
+		src = next((d for d in deps if d.endswith(SOURCE_EXTS)), None)
+		rel_src = relative_to(src, sof_root) if src else None
+		if rel_src is None or not matches(rel_src, user_src) or matches(rel_src, not_user):
+			continue
+		for dep in deps:
+			rel = relative_to(dep, sof_root)
+			if rel is not None and matches(rel, kernel_hdr):
+				leaks[rel_src].add(rel)
+				continue
+			if zephyr_base:
+				rel = relative_to(dep, zephyr_base)
+				if rel is not None and matches(rel, zephyr_hdr):
+					leaks[rel_src].add('zephyr/' + rel)
+	return leaks
+
+
+def main():
+	parser = argparse.ArgumentParser(description=__doc__.split('\n', 1)[0])
+	parser.add_argument('build_dirs', nargs='+', metavar='build-dir')
+	parser.add_argument('--manifest', default=DEFAULT_MANIFEST)
+	parser.add_argument('--sof-root', default=SOF_ROOT,
+			    help='SOF source directory the build directories were built from')
+	parser.add_argument('--zephyr-base', default=os.environ.get('ZEPHYR_BASE',
+				os.path.join(os.path.dirname(SOF_ROOT), 'zephyr')))
+	parser.add_argument('--strict', action='store_true',
+			    help='exit with an error if any kernel-only header is included')
+	parser.add_argument('--summary', action='store_true',
+			    help='only print per-header counts, not every source file')
+	args = parser.parse_args()
+
+	manifest = parse_manifest(args.manifest)
+	zephyr_base = args.zephyr_base if os.path.isdir(args.zephyr_base) else None
+
+	leaks = defaultdict(set)
+	for build_dir in args.build_dirs:
+		for src, hdrs in check_build(build_dir, manifest, args.sof_root,
+						 zephyr_base).items():
+			leaks[src] |= hdrs
+
+	by_header = defaultdict(set)
+	for src, hdrs in leaks.items():
+		for hdr in hdrs:
+			by_header[hdr].add(src)
+
+	if not args.summary:
+		for src in sorted(leaks):
+			print(f'{src}:')
+			for hdr in sorted(leaks[src]):
+				print(f'\t{hdr}')
+		print()
+
+	print('Kernel-only headers included by user-space sources:')
+	for hdr, srcs in sorted(by_header.items(), key=lambda kv: (-len(kv[1]), kv[0])):
+		print(f'{len(srcs):5d}  {hdr}')
+	print(f'{len(leaks)} user-space source files include {len(by_header)} '
+	      f'kernel-only headers')
+
+	if args.strict and leaks:
+		return 1
+	return 0
+
+
+if __name__ == '__main__':
+	sys.exit(main())
diff --git a/scripts/cmake/kconfig.cmake b/scripts/cmake/kconfig.cmake
index 0472f606fcc1..f885598387bf 100644
--- a/scripts/cmake/kconfig.cmake
+++ b/scripts/cmake/kconfig.cmake
@@ -13,16 +13,14 @@ if(NOT INIT_CONFIG_found)
 set(INIT_CONFIG "initial.config" CACHE STRING "Initial .config file")
 
 # - ".' is the top source directory.
-# - "src/arch/${arch}/configs" is for convenience and compatibility with
-#   defconfigs.cmake.
+# - "src/arch/host/configs" holds the library (testbench) configurations
+#   and is also used by defconfigs.cmake.
+# - "test/cmocka/configs" holds the unit test configurations.
 # - First found wins.
-# - If two archs ever use the same platform_defconfig name then a full
-#   path must be used, e.g.: -DINIT_CONFIG=src/arch/myarch/collision_defconfig
+# - If two directories ever use the same defconfig name then a full
+#   path must be used, e.g.: -DINIT_CONFIG=test/cmocka/configs/collision_defconfig
 
-set(init_config_search_list ".")
-foreach(arch "xtensa" "host")
-list(APPEND init_config_search_list "src/arch/${arch}/configs")
-endforeach()
+set(init_config_search_list "." "src/arch/host/configs" "test/cmocka/configs")
 
 find_file(INIT_CONFIG_found
 	NAMES ${INIT_CONFIG}
diff --git a/scripts/cmake/xtensa-platform.cmake b/scripts/cmake/xtensa-platform.cmake
deleted file mode 100644
index b2285e524366..000000000000
--- a/scripts/cmake/xtensa-platform.cmake
+++ /dev/null
@@ -1,4 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-
-set(CMAKE_C_OUTPUT_EXTENSION ".o")
-set(CMAKE_ASM_OUTPUT_EXTENSION ".o")
diff --git a/scripts/cmake/xtensa-toolchain.cmake b/scripts/cmake/xtensa-toolchain.cmake
deleted file mode 100644
index 7bc29be3e434..000000000000
--- a/scripts/cmake/xtensa-toolchain.cmake
+++ /dev/null
@@ -1,99 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-if(TOOLCHAIN)
-	set(CROSS_COMPILE "${TOOLCHAIN}-")
-else()
-	message(FATAL_ERROR
-		" Please specify toolchain to use.\n"
-		" Examples:\n"
-		" 	1) cmake -DTOOLCHAIN=xt ...\n"
-		" 	2) cmake -DTOOLCHAIN=xtensa-cnl-elf ...\n"
-	)
-endif()
-
-if(BUILD_CLANG_SCAN)
-	# scan-build has to set its own compiler,
-	# so we need to unset current one
-	message(STATUS "Reset C Compiler for scan-build")
-	set(CMAKE_C_COMPILER)
-
-	# scan-build proxies only compiler, other tools are used directly
-	find_program(CMAKE_AR NAMES "${CROSS_COMPILE}ar" PATHS ENV PATH NO_DEFAULT_PATH)
-	find_program(CMAKE_RANLIB NAMES "${CROSS_COMPILE}ranlib" PATHS ENV PATH NO_DEFAULT_PATH)
-
-	set(XCC_TOOLS_VERSION "CLANG-SCAN-BUILD")
-
-	if(TOOLCHAIN STREQUAL "xt")
-		set(XCC 1)
-	endif()
-
-	return()
-endif()
-
-message(STATUS "Preparing Xtensa toolchain")
-
-set(CMAKE_USER_MAKE_RULES_OVERRIDE "${CMAKE_CURRENT_LIST_DIR}/xtensa-platform.cmake")
-
-set(CMAKE_SYSTEM_NAME Generic)
-set(CMAKE_SYSTEM_VERSION 1)
-
-set(CMAKE_ASM_COMPILER_FORCED 1)
-set(CMAKE_C_COMPILER_FORCED 1)
-
-set(CMAKE_ASM_COMPILER_ID GNU)
-set(CMAKE_C_COMPILER_ID GNU)
-
-# in case if *_FORCED variables are ignored,
-# try to just compile lib instead of executable
-set(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY)
-
-# xt toolchain only partially follows gcc convention
-if(TOOLCHAIN STREQUAL "xt")
-	set(XCC 1)
-endif()
-
-if(NOT DEFINED SOF_CC_BASE)
-set(SOF_CC_BASE "gcc")
-endif()
-# e.g.: "xt-" + "xcc"
-set(CMAKE_C_COMPILER ${CROSS_COMPILE}${SOF_CC_BASE})
-
-find_program(CMAKE_LD NAMES "${CROSS_COMPILE}ld" PATHS ENV PATH NO_DEFAULT_PATH)
-find_program(CMAKE_AR NAMES "${CROSS_COMPILE}ar" PATHS ENV PATH NO_DEFAULT_PATH)
-find_program(CMAKE_RANLIB NAMES "${CROSS_COMPILE}ranlib" PATHS ENV PATH NO_DEFAULT_PATH)
-find_program(CMAKE_OBJCOPY NAMES "${CROSS_COMPILE}objcopy" PATHS ENV PATH NO_DEFAULT_PATH)
-find_program(CMAKE_OBJDUMP NAMES "${CROSS_COMPILE}objdump" PATHS ENV PATH NO_DEFAULT_PATH)
-
-set(CMAKE_FIND_ROOT_PATH  ".")
-set(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER)
-set(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY)
-set(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY)
-
-if(XCC)
-	# get compiler description
-	execute_process(
-		COMMAND ${CMAKE_C_COMPILER} --show-config=config
-		OUTPUT_VARIABLE cc_config_output
-		OUTPUT_STRIP_TRAILING_WHITESPACE
-		RESULT_VARIABLE show_config_res
-	)
-	if(NOT ${show_config_res} EQUAL 0)
-		message(WARNING "${CMAKE_C_COMPILER} --show-config "
-		  "failed with: ${show_config_res}")
-	endif()
-
-	string(REGEX MATCH "[a-zA-Z]+-[0-9]+.[0-9]+-[a-zA-Z]*" XCC_TOOLS_VERSION "${cc_config_output}")
-	if(NOT XCC_TOOLS_VERSION)
-		message(WARNING
-		  "Couldn't get ${CMAKE_C_COMPILER} description,"
-		  " --show-config printed: '${cc_config_output}'")
-		set(XCC_TOOLS_VERSION "UNKNOWN-${CMAKE_SYSTEM_NAME}")
-	endif()
-else()
-	string(REGEX MATCH "([^\/\\]+)$" XCC_TOOLS_VERSION "${TOOLCHAIN}")
-endif()
-
-string(LENGTH "${XCC_TOOLS_VERSION}" XCC_TOOLS_VERSION_STR_LEN)
-math(EXPR XCC_TOOLS_VERSION_PADDING "(${XCC_TOOLS_VERSION_STR_LEN} + 1) % 4")
-if(XCC_TOOLS_VERSION_PADDING EQUAL 0)
-	set(XCC_TOOLS_VERSION "<${XCC_TOOLS_VERSION}>")
-endif()
diff --git a/scripts/docker_build/sof_builder/Dockerfile b/scripts/docker_build/sof_builder/Dockerfile
index 843b5a448663..52f48ade90ea 100644
--- a/scripts/docker_build/sof_builder/Dockerfile
+++ b/scripts/docker_build/sof_builder/Dockerfile
@@ -83,65 +83,18 @@ RUN mkdir -p "$HOME"/work/alsa && cd "$HOME"/work/alsa && \
 	chown -R sof:sof "$HOME" && \
 	echo "Stage1: alsa-lib, alsa-utils are done!"
 
-ARG GITHUB_SOF=https://github.com/thesofproject
-ARG XT_OVERLAY_REPO=$GITHUB_SOF/xtensa-overlay.git
-ARG CT_NG_REPO=$GITHUB_SOF/crosstool-ng.git
-# build cross compiler
 USER sof
-RUN cd "$HOME" && \
-	git clone $CLONE_DEFAULTS --branch sof-gcc10.2 $XT_OVERLAY_REPO && \
-	git clone $CLONE_DEFAULTS --branch sof-gcc10x $CT_NG_REPO && \
-	cd crosstool-ng && \
-	./bootstrap && ./configure --prefix=`pwd` && make && make install && \
-	for arch in byt hsw apl cnl imx imx8m imx8ulp rn rmb vangogh mt8186 mt8195 mt8188; do \
-		echo "$arch: ct-ng build start..." && \
-		cp config-${arch}-gcc10.2-gdb9 .config && \
-		# replace the build dist to save space
-		sed -i 's#${CT_TOP_DIR}\/builds#\/home\/sof\/work#g' .config && \
-		# gl_cv_func_getcwd_path_max=yes is used to avoid too-long confdir3/confdir3/...
-		gl_cv_func_getcwd_path_max=yes ./ct-ng build && \
-		./ct-ng distclean ; \
-	done && \
-	echo "Stage2: xtensa-overlay, crosstool-ng are done!"
-
-ENV PATH="/home/sof/work/xtensa-byt-elf/bin:${PATH}"
-ENV PATH="/home/sof/work/xtensa-hsw-elf/bin:${PATH}"
-ENV PATH="/home/sof/work/xtensa-apl-elf/bin:${PATH}"
-ENV PATH="/home/sof/work/xtensa-cnl-elf/bin:${PATH}"
-ENV PATH="/home/sof/work/xtensa-rn-elf/bin:${PATH}"
-ENV PATH="/home/sof/work/xtensa-rmb-elf/bin:${PATH}"
-ENV PATH="/home/sof/work/xtensa-vangogh-elf/bin:${PATH}"
-ENV PATH="/home/sof/work/xtensa-imx-elf/bin:${PATH}"
-ENV PATH="/home/sof/work/xtensa-imx8m-elf/bin:${PATH}"
-ENV PATH="/home/sof/work/xtensa-imx8ulp-elf/bin:${PATH}"
-ENV PATH="/home/sof/work/xtensa-mt8186-elf/bin:${PATH}"
-ENV PATH="/home/sof/work/xtensa-mt8195-elf/bin:${PATH}"
-ENV PATH="/home/sof/work/xtensa-mt8188-elf/bin:${PATH}"
-ENV PATH="/home/sof/work/xtensa-mt8196-elf/bin:${PATH}"
-
-ARG NEWLIB_REPO=https://github.com/jcmvbkbc/newlib-xtensa.git
-RUN cd "$HOME" && \
-	git clone $CLONE_DEFAULTS --branch xtensa $NEWLIB_REPO && \
-	cd newlib-xtensa && \
-	for arch in byt hsw apl cnl imx imx8m imx8ulp rn rmb vangogh mt8186 mt8195 mt8188; do \
-		./configure --target=xtensa-${arch}-elf \
-		--prefix=/home/sof/work/xtensa-root && \
-		make && make install && \
-		rm -rf etc/config.cache; \
-	done && \
-	echo "Stage3: newlib-xtensa is done!"
 
 # log all hashes for each repo to a file
 ARG SOF_WORK="$HOME"/work
 # FIXME: this will fail when any whitespace in SOF_WORK. bash array probably good option to consider
-ARG REPOS="$SOF_WORK/alsa/alsa-lib $SOF_WORK/alsa/alsa-utils $HOME/xtensa-overlay $HOME/crosstool-ng $HOME/newlib-xtensa"
+ARG REPOS="$SOF_WORK/alsa/alsa-lib $SOF_WORK/alsa/alsa-utils"
 ARG HASH_LIST="$SOF_WORK"/sof_docker_hash.txt
 RUN echo "Build date: $(date +%Y%m%d)" > "$HASH_LIST" && set -e && \
 	for repo in $REPOS; do \
 		cd "$repo"; pwd; git log --oneline -5; \
 	done >> "$HASH_LIST" && \
-	cd "$HOME" && rm -rf xtensa-overlay crosstool-ng newlib-xtensa; \
-	echo "Stage4: git versions saved and repos deleted."
+	echo "Stage2: git versions saved."
 
 # Create direcroties for the host machines sof directories to be mounted.
 RUN mkdir -p "$HOME"/work/sof.git
diff --git a/scripts/kernel_user_partition.txt b/scripts/kernel_user_partition.txt
new file mode 100644
index 000000000000..657492223121
--- /dev/null
+++ b/scripts/kernel_user_partition.txt
@@ -0,0 +1,72 @@
+# SPDX-License-Identifier: BSD-3-Clause
+#
+# Kernel / user-space partition of the SOF sources, used by
+# scripts/check_kernel_includes.py.
+#
+# Kernel code runs in Zephyr supervisor mode: hardware and MMIO access,
+# interrupts, thread and memory domain creation, cache/MMU, power and
+# clock management, DMA and DAI driver internals, IDC, LLEXT loading and
+# system call verification. User-space code is everything else and must
+# only use plain C, system-call backed Zephyr APIs and SOF system calls,
+# whether or not a given configuration actually runs it in user mode.
+#
+# Patterns are fnmatch globs relative to the SOF top directory, except
+# [zephyr-kernel-headers] which is relative to ZEPHYR_BASE. "*" also
+# matches "/".
+
+# Sources that must be user-space safe.
+[user-sources]
+src/audio/*
+src/math/*
+src/module/*
+src/samples/*
+src/ipc/ipc-helper.c
+src/ipc/ipc4/ams_helpers.c
+src/ipc/ipc4/dai.c
+src/ipc/ipc4/notification-user.c
+src/lib/objpool.c
+
+# Kernel sources inside the directories above.
+[not-user-sources]
+src/audio/base_fw.c
+src/audio/base_fw_intel.c
+src/audio/dai-legacy.c
+src/audio/host-legacy.c
+src/audio/intel_uaol.c
+src/audio/mic_privacy_manager/*
+src/audio/module_adapter/library/userspace_proxy.c
+
+# SOF headers that only kernel code may include.
+[kernel-headers]
+src/include/sof/drivers/*
+src/include/sof/platform.h
+src/include/sof/llext_manager.h
+src/include/sof/ipc/driver.h
+src/include/sof/trace/dma-trace.h
+src/include/sof/lib/agent.h
+src/include/sof/lib/cpu-clk-manager.h
+src/include/sof/lib/mailbox.h
+src/include/sof/lib/perf_cnt.h
+src/include/sof/lib/watchdog.h
+src/platform/*
+zephyr/include/rtos/clk.h
+zephyr/include/rtos/idc.h
+zephyr/include/rtos/init.h
+zephyr/include/rtos/interrupt.h
+zephyr/include/rtos/interrupt-legacy.h
+zephyr/include/rtos/timer.h
+zephyr/include/rtos/userspace_helper.h
+zephyr/include/sof/lib/dma-legacy.h
+zephyr/include/sof/lib/io.h
+zephyr/include/sof/lib/memory.h
+zephyr/include/sof/lib/mm_heap.h
+zephyr/include/sof/lib/pm_runtime.h
+zephyr/include/sof/lib/regions_mm.h
+zephyr/include/sof/lib/vpage.h
+
+# Zephyr headers that only kernel code may include: kernel internals and
+# driver APIs that are not system calls.
+[zephyr-kernel-headers]
+kernel/include/*
+include/zephyr/drivers/dma.h
+include/zephyr/pm/device_runtime.h
diff --git a/scripts/run-mocks.sh b/scripts/run-mocks.sh
index 168608d5b12f..a73f2d3e29a5 100755
--- a/scripts/run-mocks.sh
+++ b/scripts/run-mocks.sh
@@ -63,7 +63,7 @@ run_ut()
 	for test in ${TESTS}
 	do
 	    if [ x"$test" = x'build_ut/test/cmocka/src/lib/alloc/alloc' ]; then
-		printf 'SKIP alloc test until it is fixed on HOST (passes with xt-run)'
+		printf 'SKIP alloc test until it is fixed on HOST'
 		continue
 	    fi
 
diff --git a/scripts/scan/clang-scan-build-xtensa.sh b/scripts/scan/clang-scan-build-xtensa.sh
deleted file mode 100755
index 1c8cd27f2ec6..000000000000
--- a/scripts/scan/clang-scan-build-xtensa.sh
+++ /dev/null
@@ -1,96 +0,0 @@
-#!/bin/bash
-# SPDX-License-Identifier: BSD-3-Clause
-# Copyright(c) 2020 Intel Corporation. All rights reserved.
-# Author: Janusz Jankowski <janusz.jankowski@linux.intel.com>
-
-# This script configures & performs build for clang's static analyzer.
-
-set -eu
-
-function usage {
-	echo "Usage: $0 -t <toolchain> -c <config> -r <root_dir> [options]"
-	echo "        -t        Toolchain's name."
-	echo "        -c        Name of defconfig."
-	echo "        -r        Xtensa root dir."
-	echo "        [-j n]    Set number of make build jobs."
-	echo "        [-v]      Verbose output."
-	echo "Examples:"
-	echo "        $0 -t xt -c tigerlake \\"
-	echo "                -r \$CONFIG_PATH/xtensa-elf"
-	echo "        $0 -t xtensa-cnl-elf -c cannonlake \\"
-	echo "                -r \`pwd\`/../xtensa-cnl-elf"
-}
-
-if [ "$#" -eq 0 ]
-then
-	usage
-	exit 1
-fi
-
-TOOLCHAIN=""
-DEFCONFIG=""
-ROOT_DIR=""
-JOBS=$(nproc --all)
-VERBOSE_CMAKE=OFF
-VERBOSE_SCAN_BUILD=""
-
-while getopts "t:c:r:j:v" OPTION; do
-	case $OPTION in
-		t)
-			TOOLCHAIN=$OPTARG
-			;;
-		c)
-			DEFCONFIG=$OPTARG
-			;;
-		r)
-			ROOT_DIR=$OPTARG
-			;;
-		j)
-			JOBS=$OPTARG
-			;;
-		v)
-			VERBOSE_CMAKE=ON
-			VERBOSE_SCAN_BUILD="-v -v"
-			;;
-		*)
-			echo "Invalid options"
-			usage
-			exit 1
-			;;
-	esac
-done
-
-WORKDIR=`pwd`
-SCRIPT_DIR=$(realpath $(dirname $0))
-PROXY_COMPILER=$SCRIPT_DIR/proxy-gcc.sh
-
-BUILD_DIR=build_clang_scan_${DEFCONFIG}_${TOOLCHAIN}
-
-rm -fr $BUILD_DIR
-mkdir $BUILD_DIR
-cd $BUILD_DIR
-
-scan-build $VERBOSE_SCAN_BUILD cmake \
-	-DBUILD_CLANG_SCAN=ON \
-	-DTOOLCHAIN=$TOOLCHAIN \
-	-DROOT_DIR=$ROOT_DIR \
-	-DCMAKE_VERBOSE_MAKEFILE=$VERBOSE_CMAKE \
-	..
-
-make ${DEFCONFIG}_defconfig
-
-if [[ "$TOOLCHAIN" == "xt" ]]
-then
-	COMPILER=$TOOLCHAIN-xcc
-else
-	COMPILER=$TOOLCHAIN-gcc
-fi
-
-# There are flags that are needed by clang but don't work for xtensa compiler.
-# However clang tries to pass all flags to original compiler, so we need to put
-# proxy compiler in the middle that is going to filter out unsupported flags.
-PROXY_CC=$COMPILER PROXY_REMOVE_FLAGS=-m32 \
-	scan-build $VERBOSE_SCAN_BUILD --use-cc="$PROXY_COMPILER" -o report \
-	make sof -j$JOBS
-
-cd "$WORKDIR"
diff --git a/scripts/scan/proxy-gcc.sh b/scripts/scan/proxy-gcc.sh
deleted file mode 100755
index 9a8743b02be9..000000000000
--- a/scripts/scan/proxy-gcc.sh
+++ /dev/null
@@ -1,22 +0,0 @@
-#!/bin/bash
-# SPDX-License-Identifier: BSD-3-Clause
-# Copyright(c) 2020 Intel Corporation. All rights reserved.
-# Author: Janusz Jankowski <janusz.jankowski@linux.intel.com>
-
-# Utility for filtering flags passed to the compiler.
-
-set -e
-
-out_args=()
-
-for arg in "$@"; do
-	for target in $PROXY_REMOVE_FLAGS; do
-		if [[ $arg = $target ]]; then
-			continue 2
-		fi
-	done
-	out_args+=("$arg")
-done
-
-
-$PROXY_CC "${out_args[@]}"
diff --git a/scripts/test-repro-build.sh b/scripts/test-repro-build.sh
deleted file mode 100755
index 3a3cea4660fd..000000000000
--- a/scripts/test-repro-build.sh
+++ /dev/null
@@ -1,195 +0,0 @@
-#!/bin/bash
-# SPDX-License-Identifier: BSD-3-Clause
-# Copyright(c) 2021 Intel Corporation. All rights reserved.
-
-# This builds SOF twice with some environment variations and then
-# compares the binary outputs.
-
-# Big caveats:
-#
-# - Only -g0 is supported, no BUILD_PATH_PREFIX_MAP
-# - rimage uses the current date (day month year) in the
-#   signature.
-# - Starting from TGL, signatures also include a random salt.
-#
-# rimage makes sof.ri non-deterministic even when sof.elf is
-# deterministic. See https://github.com/thesofproject/rimage/issues/41
-# and below for more details and future directions.
-
-# The following, basic environment variations are currently tested:
-#
-#   - timestamps (obviously)
-#   - source directory
-#   - disorderfs
-
-# For a list of other, non-tested environment variations check the
-# "Achieve deterministic builds" list found at
-# https://reproducible-builds.org/docs/
-
-
-set -e
-
-
-SOF_TOP=$(cd "$(dirname "$0")"/.. && /bin/pwd)
-SOF_PARENT=$(cd "$SOF_TOP"/.. && /bin/pwd)
-
-
-SOF2="$SOF_PARENT"/sof-bind-mount-DO-NOT-DELETE
-# To avoid ripple effects and reduce the number of differences
-# considerably, replace "sof" with something of the same length:
-# SOF2="$SOF_PARENT"/sog
-
-PLATFS=(rmb)
-
-# diffoscope is great but it has hundreds of dependencies, too long to
-# install for CI so we don't use it here. This is just an alias
-# suggestion for local use. Requires less -R.
-diffo ()
-{
-    # Omitting $2 ("and") allows copy/paste of the output of diff -r
-    diffoscope --exclude-directory-metadata=recursive \
-               --text-color=always "$1" "$3"
-}
-
-hexdiff ()
-{
-    # cut -b10 removes the offset
-    diff --color=auto -U20 \
-         <(hexdump -vC "$1" | cut -b10- ) \
-         <(hexdump -vC "$2" | cut -b10- ) | less
-}
-
-init()
-{
-    # -E(xtended) regex
-    local excluded_endings=(
-        '\.log' /deps
-        '\.c?make' '\.ninja' /TargetDirectories.txt
-        /CMakeCache.txt /progress.marks /CMakeRulesHashes.txt /Makefile
-        /CMakeRuleHashes.txt /Makefile2
-        '/depend\.internal' /link.txt '\.includecache'
-        '/.ninja_deps' '/.ninja_log'
-        '.*\.c\.o\.d'
-        '/rimage_ep.*'
-        '/smex_ep.*'
-    )
-
-    # The signing process is not deterministic.
-    # Keep 'reproducible.ri' INCLUDED!
-    excluded_endings+=('/sof-[a-z-]{,6}\.rix?')
-    excluded_endings+=('/sof\.ri' '/sof-no-xman\.ri' )
-
-    GREP_EXCLUDE_ARGS=()
-    for fpath in "${excluded_endings[@]}"; do
-        GREP_EXCLUDE_ARGS+=('-e' "$fpath differ\$")
-    done
-
-    # For debug
-    # declare -p GREP_EXCLUDE_ARGS # exit
-}
-
-
-trap _unmount EXIT
-
-_unmount()
-{
-    set +e
-
-    if mount | grep -q "${SOF2}.*fuse"; then
-        umount "$SOF2"
-        rmdir "$SOF2"
-    fi
-}
-
-
-diff_some_files()
-{
-    local p f
-    ( set +e
-
-      for p in "${PLATFS[@]}"; do
-
-          # Compare some ELF section headers. Look at the smallest .c.o
-          # first
-          for f in CMakeFiles/sof.dir/src/arch/xtensa/init.c.o  sof; do
-
-              diff --report-identical-files  \
-                   {b0,b1}/build_"$p"_?cc/"$f" ||
-                  diff -u --ignore-matching-lines='file format ' \
-                       <(objdump -h b0/build_"$p"_?cc/"$f") \
-                       <(objdump -h b1/build_"$p"_?cc/"$f")
-
-          done
-
-          for f in generated/include/sof_versions.h sof.ri \
-                  src/arch/xtensa/reproducible.ri; do
-              diff -u --report-identical-files  \
-                   {b0,b1}/build_"$p"_?cc/"$f"
-              # report unsupported reproducible.ri
-              test -s b0/build_"$p"_?cc/"$f" ||
-                  printf '\t%s is EMPTY\n' b0/build_"$p"_?cc/"$f"
-          done
-
-      done
-      true
-    ) | sed -e 's/differ/DIFFER/g'
-}
-
-main()
-{
-    init
-
-    test -e "$SOF2"/CMakeLists.txt || {
-        mkdir -p "$SOF2"
-        # This will fail in Docker; Docker should provide this bind
-        # mount for us.
-        disorderfs "${SOF_TOP}" "$SOF2"
-    }
-
-    # Chances of name collisions with the user should be pretty small
-    rm -rf   reprobld/b0/ reprobld/b1/
-    mkdir -p reprobld/b0/ reprobld/b1/
-
-    local oldTZ="$TZ" # typically undefined, coming from some /etc file
-                      # instead.
-
-    export EXTRA_CFLAGS='-g0'
-
-    # Going once
-
-    export TZ='Pacific/Midway' # -11:00
-    "${SOF_TOP}"/scripts/xtensa-build-all.sh     "${PLATFS[@]}"
-    mv build_*_?cc reprobld/b0/
-
-
-    # Going twice
-
-    # Use this to "break" rimage that makes the date (in local time!
-    # BIOS fans?) part of the CSS signature. See caveats above.
-    # +14:00 - -11:00 = +25:00 = always on a different date
-    export TZ='Pacific/Kiritimati' # +14:00
-
-    "$SOF2"/scripts/xtensa-build-all.sh "${PLATFS[@]}"
-    mv build_*_?cc reprobld/b1/
-
-
-    # Restore TZ just in case we want to use dates later.
-    TZ="$oldTZ"
-
-
-    cd reprobld
-    diff -qr b0 b1/ |
-        grep -E -v "${GREP_EXCLUDE_ARGS[@]}" || {
-        printf \
-          "\n\n ---- PASS: no unexpected difference found between %s/b0/ and b1/ --- \n\n" "$(pwd)"
-        exit 0
-    }
-
-    printf "\n\n ---- FAIL: differences found between %s/b0/ and b1/ --- \n\n" "$(pwd)"
-    diff_some_files
-    printf "\n\n ---- FAIL: differences found between %s/b0/ and b1/ --- \n\n" "$(pwd)"
-}
-
-test -x "${SOF_TOP}"/scripts/xtensa-build-all.sh || exit 0
-
-main "$@"
diff --git a/smex/CMakeLists.txt b/smex/CMakeLists.txt
index 01d9bf8778b3..3b0fe567ee54 100644
--- a/smex/CMakeLists.txt
+++ b/smex/CMakeLists.txt
@@ -33,5 +33,5 @@ target_include_directories(smex PRIVATE
 
 # TODO: smex should not need RTOS headers: FIX.
 target_include_directories(smex PRIVATE
-	"${SOF_ROOT_SOURCE_DIRECTORY}/xtos/include"
+	"${SOF_ROOT_SOURCE_DIRECTORY}/posix/include"
 )
diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt
index e1455a75bd7e..cd068b8b5edc 100644
--- a/src/CMakeLists.txt
+++ b/src/CMakeLists.txt
@@ -17,23 +17,3 @@ add_subdirectory(drivers)
 if (CONFIG_TRACE)
 	add_subdirectory(trace)
 endif()
-
-if(CONFIG_LIBRARY)
-	return()
-endif()
-
-add_subdirectory(debug)
-add_subdirectory(init)
-add_subdirectory(schedule)
-
-if (CONFIG_PROBE)
-	add_subdirectory(probe)
-endif()
-
-if (CONFIG_MULTICORE)
-	add_subdirectory(idc)
-endif()
-
-if (CONFIG_LOADABLE_MODULES)
-	add_subdirectory(library_manager)
-endif()
diff --git a/src/arch/host/configs/library_defconfig b/src/arch/host/configs/library_defconfig
index 1279dd26c924..3a72dc85c79a 100644
--- a/src/arch/host/configs/library_defconfig
+++ b/src/arch/host/configs/library_defconfig
@@ -31,7 +31,6 @@ CONFIG_DEBUG_MEMORY_USAGE_SCAN=n
 CONFIG_IPC_MAJOR_3=n
 CONFIG_IPC_MAJOR_4=y
 CONFIG_LIBRARY=y
-CONFIG_LIBRARY_STATIC=y
 CONFIG_MATH_IIR_DF2T=y
 CONFIG_TRACEV=y
 CONFIG_XT_RUN=y
diff --git a/src/arch/host/configs/plugin_ipc4_defconfig b/src/arch/host/configs/plugin_ipc4_defconfig
deleted file mode 100644
index 0398ea947dda..000000000000
--- a/src/arch/host/configs/plugin_ipc4_defconfig
+++ /dev/null
@@ -1,22 +0,0 @@
-CONFIG_IPC_MAJOR_4=y
-CONFIG_LIBRARY=y
-CONFIG_TRACEV=y
-CONFIG_DEBUG_MEMORY_USAGE_SCAN=n
-CONFIG_COMP_CROSSOVER=y
-CONFIG_COMP_DRC=y
-CONFIG_COMP_MULTIBAND_DRC=y
-CONFIG_COMP_SRC=y
-CONFIG_COMP_SRC_IPC4_FULL_MATRIX=y
-CONFIG_COMP_MFCC=y
-CONFIG_COMP_GAIN=y
-CONFIG_COMP_VOLUME_WINDOWS_FADE=y
-CONFIG_COMP_MODULES_SO=y
-CONFIG_COMP_MODULE_ADAPTER=y
-CONFIG_COMP_MIXIN_MIXOUT=y
-CONFIG_IPC4_GATEWAY=n
-CONFIG_COMP_DAI_GROUP=n
-CONFIG_FORMAT_S16LE=y
-CONFIG_FORMAT_S32LE=y
-CONFIG_FORMAT_S24LE=y
-CONFIG_COMP_PEAK_VOL=n
-CONFIG_COMP_MODULE_SHARED_LIBRARY_BUILD=y
diff --git a/src/arch/host/include/arch/debug/gdb/init.h b/src/arch/host/include/arch/debug/gdb/init.h
deleted file mode 100644
index 076d55f25bf5..000000000000
--- a/src/arch/host/include/arch/debug/gdb/init.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- *
- * Copyright(c) 2019 Intel Corporation. All rights reserved.
- *
- * Author: Marcin Rajwa <marcin.rajwa@linux.intel.com>
- */
-
-/*
- * Header file for init.S
- */
-
-#ifdef __SOF_DEBUG_GDB_GDB_H__
-
-#ifndef __ARCH_DEBUG_GDB_INIT_H__
-#define __ARCH_DEBUG_GDB_INIT_H__
-
-extern void gdb_init_debug_exception(void);
-
-#endif /* __ARCH_DEBUG_GDB_INIT_H__ */
-
-#else
-
-#error "This file shouldn't be included from outside of sof/debug/gdb/gdb.h"
-
-#endif /* __SOF_DEBUG_GDB_GDB_H__ */
diff --git a/src/arch/host/include/arch/debug/gdb/utilities.h b/src/arch/host/include/arch/debug/gdb/utilities.h
deleted file mode 100644
index 9d0c53bdc066..000000000000
--- a/src/arch/host/include/arch/debug/gdb/utilities.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- *
- * Copyright(c) 2019 Intel Corporation. All rights reserved.
- *
- * Author: Curtis <cujomalainey@chromium.org>
- */
-
-/*
- * Header file for host-GDB utilities.
- */
-
-#ifndef __ARCH_DEBUG_GDB_UTILITIES_H__
-#define __ARCH_DEBUG_GDB_UTILITIES_H__
-
-void arch_gdb_read_sr(int sr);
-void arch_gdb_write_sr(int sr, int *sregs);
-unsigned char arch_gdb_load_from_memory(void *mem);
-void arch_gdb_memory_load_and_store(void *mem, unsigned char ch);
-void arch_gdb_single_step(int *sregs);
-
-#endif /* __ARCH_DEBUG_GDB_UTILITIES_H__ */
diff --git a/src/arch/xtensa/configs/acp_6_3_defconfig b/src/arch/xtensa/configs/acp_6_3_defconfig
deleted file mode 100644
index 6b391bacc861..000000000000
--- a/src/arch/xtensa/configs/acp_6_3_defconfig
+++ /dev/null
@@ -1,37 +0,0 @@
-CONFIG_ACP_6_3=y
-CONFIG_RIMAGE_SIGNING_SCHEMA="acp_6_3"
-CONFIG_TRACE_CHANNEL=7
-CONFIG_WRAP_ACTUAL_POSITION=y
-CONFIG_AMD_BT=n
-CONFIG_AMD_SP=n
-CONFIG_CORE_COUNT=1
-CONFIG_LP_MEMORY_BANKS=0
-CONFIG_HP_MEMORY_BANKS=10
-CONFIG_FORMAT_CONVERT_HIFI3=n
-CONFIG_LP_SRAM=n
-CONFIG_HAVE_AGENT=n
-CONFIG_COMP_VOLUME=n
-CONFIG_COMP_SRC=n
-CONFIG_COMP_FIR=n
-CONFIG_COMP_IIR=n
-CONFIG_COMP_DCBLOCK=n
-CONFIG_COMP_CROSSOVER=n
-CONFIG_COMP_DRC=n
-CONFIG_COMP_MULTIBAND_DRC=n
-CONFIG_COMP_TONE=n
-CONFIG_COMP_SWITCH=n
-CONFIG_COMP_KPB=n
-CONFIG_MAXIM_DSM=n
-CONFIG_COMP_ASRC=n
-CONFIG_COMP_IGO_NR=n
-CONFIG_COMP_COPIER=n
-CONFIG_COMP_RTNR=n
-CONFIG_COMP_ARIA=n
-CONFIG_COMP_BASEFW_IPC4=n
-CONFIG_COMP_UP_DOWN_MIXER=n
-CONFIG_COMP_DCBLOCK=n
-CONFIG_COMP_TDFB=n
-#CONFIG_COMP_MUX=n
-CONFIG_COMP_SEL=n
-CONFIG_COMP_MIXER=n
-CONFIG_AMD_BINARY_BUILD=y
diff --git a/src/arch/xtensa/configs/mt8186_defconfig b/src/arch/xtensa/configs/mt8186_defconfig
deleted file mode 100644
index e9555a1fb31f..000000000000
--- a/src/arch/xtensa/configs/mt8186_defconfig
+++ /dev/null
@@ -1,16 +0,0 @@
-CONFIG_MT8186=y
-CONFIG_CORE_COUNT=1
-CONFIG_XT_VIRTUAL_OPS=1
-CONFIG_COMP_VOLUME=y
-CONFIG_COMP_SRC=n
-CONFIG_COMP_FIR=n
-CONFIG_COMP_IIR=n
-CONFIG_COMP_DCBLOCK=n
-CONFIG_COMP_TDFB=n
-CONFIG_COMP_TONE=n
-CONFIG_COMP_MIXER=n
-CONFIG_COMP_MUX=n
-CONFIG_COMP_KPB=n
-CONFIG_COMP_SEL=n
-CONFIG_COMP_ASRC=n
-
diff --git a/src/arch/xtensa/configs/mt8195_defconfig b/src/arch/xtensa/configs/mt8195_defconfig
deleted file mode 100644
index cffe02dd842c..000000000000
--- a/src/arch/xtensa/configs/mt8195_defconfig
+++ /dev/null
@@ -1,16 +0,0 @@
-CONFIG_MT8195=y
-CONFIG_CORE_COUNT=1
-CONFIG_XT_VIRTUAL_OPS=1
-CONFIG_COMP_VOLUME=y
-CONFIG_COMP_SRC=n
-CONFIG_COMP_FIR=n
-CONFIG_COMP_IIR=n
-CONFIG_COMP_DCBLOCK=n
-CONFIG_COMP_TDFB=n
-CONFIG_COMP_TONE=n
-CONFIG_COMP_MIXER=n
-CONFIG_COMP_MUX=n
-CONFIG_COMP_KPB=n
-CONFIG_COMP_SEL=n
-CONFIG_COMP_ASRC=n
-
diff --git a/src/arch/xtensa/configs/mt8196_defconfig b/src/arch/xtensa/configs/mt8196_defconfig
deleted file mode 100644
index f030ddc4fe2f..000000000000
--- a/src/arch/xtensa/configs/mt8196_defconfig
+++ /dev/null
@@ -1,16 +0,0 @@
-CONFIG_MT8196=y
-CONFIG_CORE_COUNT=1
-CONFIG_COMP_VOLUME=y
-CONFIG_COMP_SRC=n
-CONFIG_COMP_FIR=n
-CONFIG_COMP_IIR=n
-CONFIG_COMP_DCBLOCK=n
-CONFIG_COMP_TDFB=n
-CONFIG_COMP_TONE=n
-CONFIG_COMP_MIXER=n
-CONFIG_COMP_MUX=n
-CONFIG_COMP_KPB=n
-CONFIG_COMP_SEL=n
-CONFIG_COMP_ASRC=n
-CONFIG_DEBUG=y
-CONFIG_SCHEDULE_LL_NO_RESCHEDULE_TASK=y
diff --git a/src/arch/xtensa/configs/mt8365_defconfig b/src/arch/xtensa/configs/mt8365_defconfig
deleted file mode 100644
index 3631692a10ff..000000000000
--- a/src/arch/xtensa/configs/mt8365_defconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-CONFIG_MT8365=y
-CONFIG_CORE_COUNT=1
-CONFIG_XT_VIRTUAL_OPS=1
-CONFIG_COMP_VOLUME=y
-CONFIG_COMP_SRC=n
-CONFIG_COMP_FIR=n
-CONFIG_COMP_IIR=n
-CONFIG_COMP_DCBLOCK=n
-CONFIG_COMP_TDFB=n
-CONFIG_COMP_TONE=n
-CONFIG_COMP_MIXER=n
-CONFIG_COMP_MUX=n
-CONFIG_COMP_KPB=n
-CONFIG_COMP_SEL=n
-CONFIG_COMP_ASRC=n
diff --git a/src/arch/xtensa/configs/override/mt8186_chrome_dts.config b/src/arch/xtensa/configs/override/mt8186_chrome_dts.config
deleted file mode 100644
index 0160eaea199a..000000000000
--- a/src/arch/xtensa/configs/override/mt8186_chrome_dts.config
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_COMP_IIR=y
-CONFIG_COMP_MODULE_ADAPTER=y
-CONFIG_DTS_CODEC=y
diff --git a/src/arch/xtensa/configs/override/mt8186_chrome_waves.config b/src/arch/xtensa/configs/override/mt8186_chrome_waves.config
deleted file mode 100644
index 6e0143275ba6..000000000000
--- a/src/arch/xtensa/configs/override/mt8186_chrome_waves.config
+++ /dev/null
@@ -1,2 +0,0 @@
-CONFIG_COMP_MODULE_ADAPTER=y
-CONFIG_WAVES_CODEC=y
diff --git a/src/arch/xtensa/configs/override/mt8188_chrome_waves.config b/src/arch/xtensa/configs/override/mt8188_chrome_waves.config
deleted file mode 100644
index 6e0143275ba6..000000000000
--- a/src/arch/xtensa/configs/override/mt8188_chrome_waves.config
+++ /dev/null
@@ -1,2 +0,0 @@
-CONFIG_COMP_MODULE_ADAPTER=y
-CONFIG_WAVES_CODEC=y
diff --git a/src/arch/xtensa/configs/override/mt8195_chrome_dts.config b/src/arch/xtensa/configs/override/mt8195_chrome_dts.config
deleted file mode 100644
index 7d91a2206da3..000000000000
--- a/src/arch/xtensa/configs/override/mt8195_chrome_dts.config
+++ /dev/null
@@ -1,4 +0,0 @@
-
-CONFIG_COMP_IIR=y
-CONFIG_COMP_CODEC_ADAPTER=y
-CONFIG_DTS_CODEC=y
diff --git a/src/arch/xtensa/configs/override/mt8195_chrome_google_rtc_rtnr.config b/src/arch/xtensa/configs/override/mt8195_chrome_google_rtc_rtnr.config
deleted file mode 100644
index 7a0c166abb57..000000000000
--- a/src/arch/xtensa/configs/override/mt8195_chrome_google_rtc_rtnr.config
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_COMP_RTNR=y
-CONFIG_COMP_GOOGLE_RTC_AUDIO_PROCESSING=y
-CONFIG_COMP_MUX=y
diff --git a/src/arch/xtensa/configs/override/mt8195_chrome_rtnr.config b/src/arch/xtensa/configs/override/mt8195_chrome_rtnr.config
deleted file mode 100644
index 96da46bb8baa..000000000000
--- a/src/arch/xtensa/configs/override/mt8195_chrome_rtnr.config
+++ /dev/null
@@ -1 +0,0 @@
-CONFIG_COMP_RTNR=y
diff --git a/src/arch/xtensa/configs/override/mt8196_chrome_dts.config b/src/arch/xtensa/configs/override/mt8196_chrome_dts.config
deleted file mode 100644
index 0160eaea199a..000000000000
--- a/src/arch/xtensa/configs/override/mt8196_chrome_dts.config
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_COMP_IIR=y
-CONFIG_COMP_MODULE_ADAPTER=y
-CONFIG_DTS_CODEC=y
diff --git a/src/arch/xtensa/configs/override/mt8196_chrome_waves.config b/src/arch/xtensa/configs/override/mt8196_chrome_waves.config
deleted file mode 100644
index 6e0143275ba6..000000000000
--- a/src/arch/xtensa/configs/override/mt8196_chrome_waves.config
+++ /dev/null
@@ -1,2 +0,0 @@
-CONFIG_COMP_MODULE_ADAPTER=y
-CONFIG_WAVES_CODEC=y
diff --git a/src/arch/xtensa/configs/override/renoir_chrome_dts.config b/src/arch/xtensa/configs/override/renoir_chrome_dts.config
deleted file mode 100644
index 0160eaea199a..000000000000
--- a/src/arch/xtensa/configs/override/renoir_chrome_dts.config
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_COMP_IIR=y
-CONFIG_COMP_MODULE_ADAPTER=y
-CONFIG_DTS_CODEC=y
diff --git a/src/arch/xtensa/configs/renoir_defconfig b/src/arch/xtensa/configs/renoir_defconfig
deleted file mode 100644
index f86a843bdc5d..000000000000
--- a/src/arch/xtensa/configs/renoir_defconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-CONFIG_RENOIR=y
-CONFIG_TRACE_CHANNEL=7
-CONFIG_WRAP_ACTUAL_POSITION=y
-CONFIG_AMD_BT=n
-CONFIG_CORE_COUNT=1
-CONFIG_LP_MEMORY_BANKS=0
-CONFIG_HP_MEMORY_BANKS=10
-CONFIG_FORMAT_CONVERT_HIFI3=n
-CONFIG_LP_SRAM=n
-CONFIG_HAVE_AGENT=n
-CONFIG_PROBE=y
-CONFIG_PROBE_POINTS_MAX=16
\ No newline at end of file
diff --git a/src/arch/xtensa/configs/vangogh_defconfig b/src/arch/xtensa/configs/vangogh_defconfig
deleted file mode 100644
index f022b070de2e..000000000000
--- a/src/arch/xtensa/configs/vangogh_defconfig
+++ /dev/null
@@ -1,28 +0,0 @@
-CONFIG_VANGOGH=y
-CONFIG_RIMAGE_SIGNING_SCHEMA="vangogh"
-CONFIG_TRACE_CHANNEL=7
-CONFIG_WRAP_ACTUAL_POSITION=y
-CONFIG_AMD_BT=n
-CONFIG_CORE_COUNT=1
-CONFIG_LP_MEMORY_BANKS=0
-CONFIG_HP_MEMORY_BANKS=20
-CONFIG_FORMAT_CONVERT_HIFI3=n
-CONFIG_LP_SRAM=n
-CONFIG_HAVE_AGENT=n
-CONFIG_COMP_SRC=n
-CONFIG_COMP_FIR=n
-CONFIG_COMP_IIR=n
-CONFIG_COMP_DCBLOCK=n
-CONFIG_COMP_TDFB=n
-CONFIG_COMP_TONE=n
-CONFIG_COMP_MIXER=n
-CONFIG_COMP_MUX=n
-CONFIG_COMP_SWITCH=n
-CONFIG_COMP_KPB=n
-CONFIG_COMP_SEL=n
-CONFIG_COMP_ASRC=n
-CONFIG_TRACE=y
-CONFIG_TRACEE=y
-CONFIG_TRACEV=y
-CONFIG_PROBE=y
-CONFIG_PROBE_POINTS_MAX=16
diff --git a/src/audio/CMakeLists.txt b/src/audio/CMakeLists.txt
index 92002c8b7c1c..53b8584467b4 100644
--- a/src/audio/CMakeLists.txt
+++ b/src/audio/CMakeLists.txt
@@ -10,138 +10,136 @@ set(base_files
 	channel_map.c
 )
 
-### Common actions for Zephyr/XTOS ###
-if(NOT CONFIG_COMP_MODULE_SHARED_LIBRARY_BUILD)
-	# directories included unconditionally (alphabetical order)
-	add_subdirectory(buffers)
-	add_subdirectory(pcm_converter)
-	add_subdirectory(pipeline)
-
-	if(CONFIG_COMP_BASEFW_IPC4 AND NOT CONFIG_LIBRARY)
-		add_local_sources(sof base_fw.c)
-	endif()
-	add_local_sources_ifdef(CONFIG_IPC4_BASE_FW_INTEL sof base_fw_intel.c)
+### Common actions for Zephyr and the host library ###
+# directories included unconditionally (alphabetical order)
+add_subdirectory(buffers)
+add_subdirectory(pcm_converter)
+add_subdirectory(pipeline)
+
+if(CONFIG_COMP_BASEFW_IPC4 AND NOT CONFIG_LIBRARY)
+	add_local_sources(sof base_fw.c)
+endif()
+add_local_sources_ifdef(CONFIG_IPC4_BASE_FW_INTEL sof base_fw_intel.c)
 
-	# directories and files included conditionally (alphabetical order)
-	if(CONFIG_COMP_ARIA)
-		add_subdirectory(aria)
-	endif()
-	if(CONFIG_COMP_ASRC)
-		add_subdirectory(asrc)
-	endif()
-	if(CONFIG_COMP_COPIER)
-		add_subdirectory(copier)
-	endif()
-	if(CONFIG_COMP_CROSSOVER)
-		add_subdirectory(crossover)
-	endif()
-	if(CONFIG_COMP_DCBLOCK)
-		add_subdirectory(dcblock)
-	endif()
-	if(CONFIG_COMP_DRC)
-		add_subdirectory(drc)
-	endif()
-	if(CONFIG_COMP_FIR)
-		add_subdirectory(eq_fir)
-	endif()
-	if(CONFIG_COMP_IGO_NR)
-		add_subdirectory(igo_nr)
-	endif()
-	if(CONFIG_COMP_IIR)
-		add_subdirectory(eq_iir)
-	endif()
-	if(CONFIG_COMP_LEVEL_MULTIPLIER)
-		add_subdirectory(level_multiplier)
-	endif()
-	if(CONFIG_COMP_MFCC)
-		add_subdirectory(mfcc)
-	endif()
-	if(CONFIG_COMP_MIXER)
-		add_subdirectory(mixer)
-	endif()
-	if(CONFIG_COMP_MIXIN_MIXOUT)
-		add_subdirectory(mixin_mixout)
-	endif()
-	if(CONFIG_COMP_MODULE_ADAPTER)
-		add_subdirectory(module_adapter)
-	endif()
-	if(CONFIG_COMP_MULTIBAND_DRC)
-		add_subdirectory(multiband_drc)
-	endif()
-	if(CONFIG_COMP_MUX)
-		add_subdirectory(mux)
-	endif()
-	if(CONFIG_COMP_PHASE_VOCODER)
-		add_subdirectory(phase_vocoder)
-	endif()
-	if(CONFIG_COMP_RTNR)
-		add_subdirectory(rtnr)
-	endif()
-	if(CONFIG_COMP_SEL)
-		add_subdirectory(selector)
-	endif()
-	if(CONFIG_COMP_SMART_AMP)
-		add_subdirectory(smart_amp)
-	endif()
-	if(CONFIG_COMP_SOUND_DOSE)
-		add_subdirectory(sound_dose)
-	endif()
-	if(CONFIG_COMP_SRC)
-		add_subdirectory(src)
-	endif()
-	if(CONFIG_COMP_STFT_PROCESS)
-		add_subdirectory(stft_process)
-	endif()
-	if(CONFIG_COMP_TDFB)
-		add_subdirectory(tdfb)
-	endif()
-	if(CONFIG_COMP_TEMPLATE)
-		add_subdirectory(template)
-	endif()
-	if(CONFIG_COMP_TENSORFLOW)
-		add_subdirectory(tensorflow)
-	endif()
-	if(CONFIG_COMP_UP_DOWN_MIXER)
-		add_subdirectory(up_down_mixer)
-	endif()
-	if(CONFIG_COMP_VOLUME)
-		add_subdirectory(volume)
-	endif()
-	if(CONFIG_DTS_CODEC)
-		add_subdirectory(codec)
-	endif()
-	# end of directories and files included conditionally (alphabetical order)
+# directories and files included conditionally (alphabetical order)
+if(CONFIG_COMP_ARIA)
+	add_subdirectory(aria)
+endif()
+if(CONFIG_COMP_ASRC)
+	add_subdirectory(asrc)
+endif()
+if(CONFIG_COMP_COPIER)
+	add_subdirectory(copier)
+endif()
+if(CONFIG_COMP_CROSSOVER)
+	add_subdirectory(crossover)
+endif()
+if(CONFIG_COMP_DCBLOCK)
+	add_subdirectory(dcblock)
+endif()
+if(CONFIG_COMP_DRC)
+	add_subdirectory(drc)
+endif()
+if(CONFIG_COMP_FIR)
+	add_subdirectory(eq_fir)
+endif()
+if(CONFIG_COMP_IGO_NR)
+	add_subdirectory(igo_nr)
+endif()
+if(CONFIG_COMP_IIR)
+	add_subdirectory(eq_iir)
+endif()
+if(CONFIG_COMP_LEVEL_MULTIPLIER)
+	add_subdirectory(level_multiplier)
+endif()
+if(CONFIG_COMP_MFCC)
+	add_subdirectory(mfcc)
+endif()
+if(CONFIG_COMP_MIXER)
+	add_subdirectory(mixer)
+endif()
+if(CONFIG_COMP_MIXIN_MIXOUT)
+	add_subdirectory(mixin_mixout)
+endif()
+if(CONFIG_COMP_MODULE_ADAPTER)
+	add_subdirectory(module_adapter)
+endif()
+if(CONFIG_COMP_MULTIBAND_DRC)
+	add_subdirectory(multiband_drc)
+endif()
+if(CONFIG_COMP_MUX)
+	add_subdirectory(mux)
+endif()
+if(CONFIG_COMP_PHASE_VOCODER)
+	add_subdirectory(phase_vocoder)
+endif()
+if(CONFIG_COMP_RTNR)
+	add_subdirectory(rtnr)
+endif()
+if(CONFIG_COMP_SEL)
+	add_subdirectory(selector)
+endif()
+if(CONFIG_COMP_SMART_AMP)
+	add_subdirectory(smart_amp)
+endif()
+if(CONFIG_COMP_SOUND_DOSE)
+	add_subdirectory(sound_dose)
+endif()
+if(CONFIG_COMP_SRC)
+	add_subdirectory(src)
+endif()
+if(CONFIG_COMP_STFT_PROCESS)
+	add_subdirectory(stft_process)
+endif()
+if(CONFIG_COMP_TDFB)
+	add_subdirectory(tdfb)
+endif()
+if(CONFIG_COMP_TEMPLATE)
+	add_subdirectory(template)
+endif()
+if(CONFIG_COMP_TENSORFLOW)
+	add_subdirectory(tensorflow)
+endif()
+if(CONFIG_COMP_UP_DOWN_MIXER)
+	add_subdirectory(up_down_mixer)
+endif()
+if(CONFIG_COMP_VOLUME)
+	add_subdirectory(volume)
+endif()
+if(CONFIG_DTS_CODEC)
+	add_subdirectory(codec)
+endif()
+# end of directories and files included conditionally (alphabetical order)
 
-	add_subdirectory(google)
-	add_subdirectory(nxp)
+add_subdirectory(google)
+add_subdirectory(nxp)
 
-	if(CONFIG_COMP_CHAIN_DMA)
-		add_local_sources(sof chain_dma.c)
-	endif()
-	if(CONFIG_COMP_KPB AND NOT CONFIG_LIBRARY_STATIC)
-		add_local_sources(sof
-			kpb.c
-		)
-	endif()
-	if(CONFIG_INTEL_ADSP_MIC_PRIVACY)
-		add_subdirectory(mic_privacy_manager)
-	endif()
-	if(CONFIG_COMP_TONE)
-		add_subdirectory(tone)
-	endif()
-	if(CONFIG_UAOL_INTEL_ADSP)
-		add_local_sources(sof intel_uaol.c)
-	endif()
-	if(CONFIG_ZEPHYR_NATIVE_DRIVERS)
-		list(APPEND base_files host-zephyr.c)
-		sof_list_append_ifdef(CONFIG_COMP_DAI base_files dai-zephyr.c)
-	else()
-		list(APPEND base_files host-legacy.c)
-		sof_list_append_ifdef(CONFIG_COMP_DAI base_files dai-legacy.c)
-	endif()
+if(CONFIG_COMP_CHAIN_DMA)
+	add_local_sources(sof chain_dma.c)
+endif()
+if(CONFIG_COMP_KPB AND NOT CONFIG_LIBRARY)
+	add_local_sources(sof
+		kpb.c
+	)
+endif()
+if(CONFIG_INTEL_ADSP_MIC_PRIVACY)
+	add_subdirectory(mic_privacy_manager)
+endif()
+if(CONFIG_COMP_TONE)
+	add_subdirectory(tone)
+endif()
+if(CONFIG_UAOL_INTEL_ADSP)
+	add_local_sources(sof intel_uaol.c)
+endif()
+if(CONFIG_ZEPHYR_NATIVE_DRIVERS)
+	list(APPEND base_files host-zephyr.c)
+	sof_list_append_ifdef(CONFIG_COMP_DAI base_files dai-zephyr.c)
+else()
+	list(APPEND base_files host-legacy.c)
+	sof_list_append_ifdef(CONFIG_COMP_DAI base_files dai-legacy.c)
 endif()
 
-### Common files (also used in shared library build)
+### Common files
 
 sof_list_append_ifdef(CONFIG_COMP_BLOB base_files data_blob.c)
 
@@ -154,9 +152,7 @@ if(zephyr) ###  Zephyr ###
 		${base_files}
 	)
 
-	return()
-elseif(NOT CONFIG_COMP_MODULE_SHARED_LIBRARY_BUILD)
-	### not shared library, e.g. testbench ###
+else() ### library, e.g. testbench ###
 
 	add_local_sources(sof
 		host-legacy.c
@@ -168,112 +164,4 @@ elseif(NOT CONFIG_COMP_MODULE_SHARED_LIBRARY_BUILD)
 			dai-legacy.c
 		)
 	endif()
-
-	return()
 endif()
-
-### Shared library build (CONFIG_COMP_MODULE_SHARED_LIBRARY_BUILD) ###
-
-subdirs(pipeline)
-
-if(CONFIG_COMP_MODULE_ADAPTER)
-		add_subdirectory(module_adapter)
-endif()
-
-add_local_sources(sof
-	data_blob.c
-	buffers/comp_buffer.c
-	buffers/audio_buffer.c
-	${base_files}
-)
-
-# Audio Modules with various optimizaitons
-
-# add rules for module compilation and installation
-function(sof_audio_add_module lib_name compile_flags)
-	add_library(${lib_name} MODULE "")
-	target_link_libraries(${lib_name} PRIVATE sof_options)
-	target_link_libraries(${lib_name} PRIVATE -Wl,--export-dynamic)
-	target_compile_options(${lib_name} PRIVATE ${compile_flags})
-	add_local_sources(${lib_name} ${ARGN})
-	sof_append_relative_path_definitions(${lib_name})
-	install(TARGETS ${lib_name} DESTINATION lib)
-endfunction()
-
-include(CheckCCompilerFlag)
-
-set(available_optimizations)
-
-# checks if flag is supported by compiler and sets needed flags
-# note: to debug vectorisation please add "-fopt-info-vec-note" option after
-# the enable command below.
-macro(check_optimization opt_name flag enable_cmd extra_define)
-	check_c_compiler_flag(${flag} compiles_flag_${opt_name})
-	if(compiles_flag_${opt_name})
-		list(APPEND available_optimizations ${opt_name})
-		set(${opt_name}_flags ${flag} ${extra_define} ${enable_cmd} -ffast-math)
-	endif()
-endmacro()
-
-# modules will be compiled only for flags supported by compiler
-check_optimization(sse42 -msse4.2 -ftree-vectorize -DOPS_SSE42)
-check_optimization(avx -mavx -ftree-vectorize -DOPS_AVX)
-check_optimization(avx2 -mavx2 -ftree-vectorize -DOPS_AVX2)
-check_optimization(fma -mfma -ftree-vectorize -DOPS_FMA)
-check_optimization(hifi2ep -mhifi2ep "" -DOPS_HIFI2EP)
-check_optimization(hifi3 -mhifi3 "" -DOPS_HIFI3)
-
-set(sof_audio_modules mixer volume src asrc eq-fir eq-iir dcblock crossover tdfb drc multiband_drc mfcc mux)
-
-# sources for each module
-if(CONFIG_IPC_MAJOR_3)
-	set(volume_sources volume/volume.c volume/volume_generic.c volume/volume_ipc3.c)
-	set(asrc_sources asrc/asrc_ipc3.c)
-	set(src_sources src/src.c src/src_ipc3.c src/src_generic.c)
-	set(eq-iir_sources eq_iir/eq_iir_ipc3.c eq_iir/eq_iir_generic.c)
-	set(eq-fir_sources eq_fir/eq_fir_ipc3.c)
-	set(tdfb_sources tdfb/tdfb_ipc3.c)
-	set(tdfb_sources multiband_drc/multiband_drc_ipc3.c)
-	set(dcblock_sources dcblock/dcblock_ipc3.c)
-	set(mux_sources mux/mux_ipc3.c)
-	set(crossover_sources crossover/crossover_ipc3.c)
-elseif(CONFIG_IPC_MAJOR_4)
-	set(volume_sources volume/volume.c volume/volume_generic.c volume/volume_ipc4.c)
-	set(asrc_sources asrc/asrc_ipc4.c)
-	set(src_sources src/src.c src/src_ipc4.c src/src_generic.c)
-	set(eq-iir_sources eq_iir/eq_iir_ipc4.c eq_iir/eq_iir_generic.c)
-	set(eq-fir_sources eq_fir/eq_fir_ipc4.c)
-	set(tdfb_sources tdfb/tdfb_ipc4.c)
-	set(tdfb_sources multiband_drc/multiband_drc_ipc4.c)
-	set(dcblock_sources dcblock/dcblock_ipc4.c)
-	set(mux_sources mux/mux_ipc4.c)
-	set(crossover_sources crossover/crossover_ipc4.c)
-endif()
-
-if(CONFIG_IPC_MAJOR_3)
-	set(mixer_src mixer/mixer.c mixer/mixer_generic.c mixer/mixer_hifi3.c)
-elseif(CONFIG_IPC_MAJOR_4)
-	set(mixer_src mixin_mixout/mixin_mixout.c mixin_mixout/mixin_mixout_generic.c mixin_mixout/mixin_mixout_hifi3.c)
-endif()
-
-set(mixer_sources ${mixer_src})
-set(asrc_sources asrc/asrc.c asrc/asrc_farrow.c asrc/asrc_farrow_generic.c)
-set(eq-fir_sources eq_fir/eq_fir.c eq_fir/eq_fir_generic.c)
-set(eq-iir_sources eq_iir/eq_iir.c)
-set(dcblock_sources dcblock/dcblock.c dcblock/dcblock_generic.c dcblock/dcblock_hifi4.c)
-set(crossover_sources crossover/crossover.c crossover/crossover_generic.c)
-set(tdfb_sources tdfb/tdfb.c tdfb/tdfb_generic.c tdfb/tdfb_direction.c)
-set(drc_sources drc/drc.c drc/drc_generic.c drc/drc_math_generic.c)
-set(multiband_drc_sources multiband_drc/multiband_drc_generic.c crossover/crossover.c drc/drc.c drc/drc_generic.c drc/drc_math_generic.c multiband_drc/multiband_drc.c )
-set(mfcc_sources mfcc/mfcc.c mfcc/mfcc_setup.c mfcc/mfcc_common.c mfcc/mfcc_generic.c mfcc/mfcc_hifi4.c mfcc/mfcc_hifi3.c)
-set(mux_sources mux/mux.c mux/mux_generic.c)
-
-foreach(audio_module ${sof_audio_modules})
-	# first compile with no optimizations
-	sof_audio_add_module(sof_${audio_module} "" ${${audio_module}_sources})
-
-	# compile for each optimization
-	foreach(opt ${available_optimizations})
-		sof_audio_add_module(sof_${audio_module}_${opt} "${${opt}_flags}" ${${audio_module}_sources})
-	endforeach()
-endforeach()
diff --git a/src/audio/Kconfig b/src/audio/Kconfig
index 53f5301760f9..06ffc1b57117 100644
--- a/src/audio/Kconfig
+++ b/src/audio/Kconfig
@@ -414,12 +414,6 @@ config WRAP_ACTUAL_POSITION
 	  in some cases based on the period size, the frame may not exactly be at the
 	  end of the buffer and roll over for some bytes from the beginning of the buffer.
 
-config COMP_MODULE_SHARED_LIBRARY_BUILD
-	bool "Build SOF modules as shared libraries"
-	help
-	  Select if you want to build modules as shared objects that can be used to run
-	  pipelines on the host with the testbench or the ALSA plugin.
-
 config DISABLE_DESCRIPTOR_SPLIT
 	bool "Disable descriptor split"
 	help
diff --git a/src/audio/google/CMakeLists.txt b/src/audio/google/CMakeLists.txt
index fa55c9f39a2e..44e6e81ad190 100644
--- a/src/audio/google/CMakeLists.txt
+++ b/src/audio/google/CMakeLists.txt
@@ -66,60 +66,56 @@ if(zephyr) ###  Zephyr ###
 endif()
 
 ### Library build rules ###
-if(CONFIG_LIBRARY_STATIC)
-	if(CONFIG_COMP_GOOGLE_HOTWORD_DETECT)
-		add_local_sources(sof
-			google_hotword_detect.c
-		)
-		target_link_libraries(sof PRIVATE libhifi3_google_hotword_dsp_api.a)
-		target_link_libraries(sof PRIVATE c)
-		target_link_libraries(sof PRIVATE m)
-	endif()
-
-	if(CONFIG_COMP_GOOGLE_RTC_AUDIO_PROCESSING)
-	  target_include_directories(sof PRIVATE ${CMAKE_SOURCE_DIR}/third_party/include)
-	  add_local_sources(sof
-		google_rtc_audio_processing.c
-		)
-	  if(CONFIG_GOOGLE_RTC_AUDIO_PROCESSING_MOCK)
-		add_local_sources(sof
-		  google_rtc_audio_processing_mock.c
-		  )
-	  else()
-		message(INFO "Link with google_rtc_audio_processing")
-		target_link_directories(sof PRIVATE ${CMAKE_SOURCE_DIR}/third_party/lib)
-		target_link_libraries(sof PRIVATE google_rtc_audio_processing)
-		target_link_libraries(sof PRIVATE c++)
-		target_link_libraries(sof PRIVATE c++abi)
-		target_link_libraries(sof PRIVATE m)
-		target_link_libraries(sof PRIVATE c)
-	  endif()
-	endif()
+if(CONFIG_COMP_GOOGLE_HOTWORD_DETECT)
+	add_local_sources(sof
+		google_hotword_detect.c
+	)
+	target_link_libraries(sof PRIVATE libhifi3_google_hotword_dsp_api.a)
+	target_link_libraries(sof PRIVATE c)
+	target_link_libraries(sof PRIVATE m)
+endif()
 
-	if(CONFIG_COMP_GOOGLE_CTC_AUDIO_PROCESSING)
-	  target_include_directories(sof PRIVATE ${CMAKE_SOURCE_DIR}/third_party/include)
-	  add_local_sources(sof
-		google_ctc_audio_processing.c
-		)
-	  if(CONFIG_IPC_MAJOR_3)
-	  	add_local_sources(sof google_ctc_audio_processing_ipc3.c)
-	  elseif(CONFIG_IPC_MAJOR_4)
-	  	add_local_sources(sof google_ctc_audio_processing_ipc4.c)
-	  endif()
-	  if(CONFIG_GOOGLE_CTC_AUDIO_PROCESSING_MOCK)
-		add_local_sources(sof
-		  google_ctc_audio_processing_mock.c
-		  )
-	  else()
-		message(INFO "Link with google_ctc_audio_processing")
-		target_link_directories(sof PRIVATE ${CMAKE_SOURCE_DIR}/third_party/lib)
-		target_link_libraries(sof PRIVATE google_ctc_audio_processing)
-		target_link_libraries(sof PRIVATE c++)
-		target_link_libraries(sof PRIVATE c++abi)
-		target_link_libraries(sof PRIVATE m)
-		target_link_libraries(sof PRIVATE c)
-	  endif()
-	endif()
-	return()
+if(CONFIG_COMP_GOOGLE_RTC_AUDIO_PROCESSING)
+  target_include_directories(sof PRIVATE ${CMAKE_SOURCE_DIR}/third_party/include)
+  add_local_sources(sof
+	google_rtc_audio_processing.c
+	)
+  if(CONFIG_GOOGLE_RTC_AUDIO_PROCESSING_MOCK)
+	add_local_sources(sof
+	  google_rtc_audio_processing_mock.c
+	  )
+  else()
+	message(INFO "Link with google_rtc_audio_processing")
+	target_link_directories(sof PRIVATE ${CMAKE_SOURCE_DIR}/third_party/lib)
+	target_link_libraries(sof PRIVATE google_rtc_audio_processing)
+	target_link_libraries(sof PRIVATE c++)
+	target_link_libraries(sof PRIVATE c++abi)
+	target_link_libraries(sof PRIVATE m)
+	target_link_libraries(sof PRIVATE c)
+  endif()
 endif()
 
+if(CONFIG_COMP_GOOGLE_CTC_AUDIO_PROCESSING)
+  target_include_directories(sof PRIVATE ${CMAKE_SOURCE_DIR}/third_party/include)
+  add_local_sources(sof
+	google_ctc_audio_processing.c
+	)
+  if(CONFIG_IPC_MAJOR_3)
+  	add_local_sources(sof google_ctc_audio_processing_ipc3.c)
+  elseif(CONFIG_IPC_MAJOR_4)
+  	add_local_sources(sof google_ctc_audio_processing_ipc4.c)
+  endif()
+  if(CONFIG_GOOGLE_CTC_AUDIO_PROCESSING_MOCK)
+	add_local_sources(sof
+	  google_ctc_audio_processing_mock.c
+	  )
+  else()
+	message(INFO "Link with google_ctc_audio_processing")
+	target_link_directories(sof PRIVATE ${CMAKE_SOURCE_DIR}/third_party/lib)
+	target_link_libraries(sof PRIVATE google_ctc_audio_processing)
+	target_link_libraries(sof PRIVATE c++)
+	target_link_libraries(sof PRIVATE c++abi)
+	target_link_libraries(sof PRIVATE m)
+	target_link_libraries(sof PRIVATE c)
+  endif()
+endif()
diff --git a/src/audio/module_adapter/CMakeLists.txt b/src/audio/module_adapter/CMakeLists.txt
index ca9ffbd8f787..6c33bc94efb8 100644
--- a/src/audio/module_adapter/CMakeLists.txt
+++ b/src/audio/module_adapter/CMakeLists.txt
@@ -105,83 +105,79 @@ endif()
 	return()
 endif()
 
-if(NOT CONFIG_COMP_MODULE_SHARED_LIBRARY_BUILD)
-	if(CONFIG_CADENCE_CODEC)
-		add_local_sources(sof module/cadence.c)
+if(CONFIG_CADENCE_CODEC)
+	add_local_sources(sof module/cadence.c)
 
-		if(CONFIG_CADENCE_CODEC_WRAPPER)
-			sof_add_static_library(codec_wrapper_lib ${CONFIG_CADENCE_CODEC_WRAPPER_LIB})
-		endif()
-
-		if(CONFIG_CADENCE_CODEC_AAC_DEC)
-			sof_add_static_library(xa_aac_dec ${CONFIG_CADENCE_CODEC_AAC_DEC_LIB})
-		endif()
-
-		if(CONFIG_CADENCE_CODEC_BSAC_DEC)
-			sof_add_static_library(xa_bsac_dec ${CONFIG_CADENCE_CODEC_BSAC_DEC_LIB})
-		endif()
-
-		if(CONFIG_CADENCE_CODEC_DAB_DEC)
-			sof_add_static_library(xa_dab_dec ${CONFIG_CADENCE_CODEC_DAB_DEC_LIB})
-		endif()
-
-		if(CONFIG_CADENCE_CODEC_DRM_DEC)
-			sof_add_static_library(xa_drm_dec ${CONFIG_CADENCE_CODEC_DRM_DEC_LIB})
-		endif()
+	if(CONFIG_CADENCE_CODEC_WRAPPER)
+		sof_add_static_library(codec_wrapper_lib ${CONFIG_CADENCE_CODEC_WRAPPER_LIB})
+	endif()
 
-		if(CONFIG_CADENCE_CODEC_MP3_DEC)
-			sof_add_static_library(xa_mp3_dec ${CONFIG_CADENCE_CODEC_MP3_DEC_LIB})
-		endif()
+	if(CONFIG_CADENCE_CODEC_AAC_DEC)
+		sof_add_static_library(xa_aac_dec ${CONFIG_CADENCE_CODEC_AAC_DEC_LIB})
+	endif()
 
-		if(CONFIG_CADENCE_CODEC_MP3_ENC)
-			sof_add_static_library(xa_mp3_enc ${CONFIG_CADENCE_CODEC_MP3_ENC_LIB})
-		endif()
+	if(CONFIG_CADENCE_CODEC_BSAC_DEC)
+		sof_add_static_library(xa_bsac_dec ${CONFIG_CADENCE_CODEC_BSAC_DEC_LIB})
+	endif()
 
-		if(CONFIG_CADENCE_CODEC_SBC_DEC)
-			sof_add_static_library(xa_sbc_dec ${CONFIG_CADENCE_CODEC_SBC_DEC_LIB})
-		endif()
+	if(CONFIG_CADENCE_CODEC_DAB_DEC)
+		sof_add_static_library(xa_dab_dec ${CONFIG_CADENCE_CODEC_DAB_DEC_LIB})
+	endif()
 
-		if(CONFIG_CADENCE_CODEC_VORBIS_DEC)
-			sof_add_static_library(xa_vorbis_dec ${CONFIG_CADENCE_CODEC_VORBIS_DEC_LIB})
-		endif()
+	if(CONFIG_CADENCE_CODEC_DRM_DEC)
+		sof_add_static_library(xa_drm_dec ${CONFIG_CADENCE_CODEC_DRM_DEC_LIB})
+	endif()
 
-		if(CONFIG_CADENCE_CODEC_SRC_PP)
-			sof_add_static_library(xa_src_pp ${CONFIG_CADENCE_CODEC_SRC_PP_LIB})
-		endif()
+	if(CONFIG_CADENCE_CODEC_MP3_DEC)
+		sof_add_static_library(xa_mp3_dec ${CONFIG_CADENCE_CODEC_MP3_DEC_LIB})
+	endif()
 
+	if(CONFIG_CADENCE_CODEC_MP3_ENC)
+		sof_add_static_library(xa_mp3_enc ${CONFIG_CADENCE_CODEC_MP3_ENC_LIB})
 	endif()
 
-	if(CONFIG_SOF_COMPRESS_CODEC_PCM_DEC)
-		add_subdirectory(module/compress_other)
+	if(CONFIG_CADENCE_CODEC_SBC_DEC)
+		sof_add_static_library(xa_sbc_dec ${CONFIG_CADENCE_CODEC_SBC_DEC_LIB})
 	endif()
 
-	if(CONFIG_COMP_DOLBY_DAX_AUDIO_PROCESSING)
-		target_include_directories(sof PRIVATE ${PROJECT_SOURCE_DIR}/third_party/include)
-		add_local_sources(sof module/dolby/dax.c)
-		add_local_sources(sof module/dolby/dax_instance_manager.c)
-		if (CONFIG_COMP_DOLBY_DAX_AUDIO_PROCESSING_MOCK)
-			add_local_sources(sof module/dolby/dax_mock.c)
-		else()
-			target_link_libraries(sof PRIVATE m)
-			target_link_libraries(sof PRIVATE c)
-			sof_add_static_library(dax_effect
-				${PROJECT_SOURCE_DIR}/third_party/lib/libdax.a)
-		endif()
+	if(CONFIG_CADENCE_CODEC_VORBIS_DEC)
+		sof_add_static_library(xa_vorbis_dec ${CONFIG_CADENCE_CODEC_VORBIS_DEC_LIB})
 	endif()
 
-	if(CONFIG_PASSTHROUGH_CODEC)
-		add_local_sources(sof module/passthrough.c)
+	if(CONFIG_CADENCE_CODEC_SRC_PP)
+		sof_add_static_library(xa_src_pp ${CONFIG_CADENCE_CODEC_SRC_PP_LIB})
 	endif()
 
-	if(CONFIG_WAVES_CODEC)
-		add_local_sources(sof module/waves/waves.c)
-		if (CONFIG_WAVES_CODEC_STUB)
-			add_local_sources(sof module/waves/maxx_stub.c)
-		else()
-			sof_add_static_library(MaxxChrome ${CMAKE_CURRENT_LIST_DIR}/lib/release/libMaxxChrome.a)
-		endif()
-	# folder with Waves API must be among include directories
+endif()
+
+if(CONFIG_SOF_COMPRESS_CODEC_PCM_DEC)
+	add_subdirectory(module/compress_other)
+endif()
+
+if(CONFIG_COMP_DOLBY_DAX_AUDIO_PROCESSING)
+	target_include_directories(sof PRIVATE ${PROJECT_SOURCE_DIR}/third_party/include)
+	add_local_sources(sof module/dolby/dax.c)
+	add_local_sources(sof module/dolby/dax_instance_manager.c)
+	if (CONFIG_COMP_DOLBY_DAX_AUDIO_PROCESSING_MOCK)
+		add_local_sources(sof module/dolby/dax_mock.c)
+	else()
+		target_link_libraries(sof PRIVATE m)
+		target_link_libraries(sof PRIVATE c)
+		sof_add_static_library(dax_effect
+			${PROJECT_SOURCE_DIR}/third_party/lib/libdax.a)
 	endif()
+endif()
 
-	return()
+if(CONFIG_PASSTHROUGH_CODEC)
+	add_local_sources(sof module/passthrough.c)
+endif()
+
+if(CONFIG_WAVES_CODEC)
+	add_local_sources(sof module/waves/waves.c)
+	if (CONFIG_WAVES_CODEC_STUB)
+		add_local_sources(sof module/waves/maxx_stub.c)
+	else()
+		sof_add_static_library(MaxxChrome ${CMAKE_CURRENT_LIST_DIR}/lib/release/libMaxxChrome.a)
+	endif()
+# folder with Waves API must be among include directories
 endif()
diff --git a/src/audio/pipeline/pipeline-stream.c b/src/audio/pipeline/pipeline-stream.c
index 5fd795e818db..4bdd0c93b9c9 100644
--- a/src/audio/pipeline/pipeline-stream.c
+++ b/src/audio/pipeline/pipeline-stream.c
@@ -200,39 +200,6 @@ int pipeline_copy(struct pipeline *p)
 	return ret;
 }
 
-#if CONFIG_LIBRARY && !CONFIG_LIBRARY_STATIC
-/* trigger pipeline immediately in IPC context. TODO: Add support for XRUN */
-int pipeline_trigger(struct pipeline *p, struct comp_dev *host, int cmd)
-{
-	int ret;
-
-	pipe_info(p, "pipe trigger cmd %d", cmd);
-
-	p->trigger.aborted = false;
-
-	ret = pipeline_trigger_run(p, host, cmd);
-	if (ret < 0)
-		return ret;
-
-	switch (cmd) {
-	case COMP_TRIGGER_PRE_START:
-	case COMP_TRIGGER_START:
-	case COMP_TRIGGER_PRE_RELEASE:
-		p->status = COMP_STATE_ACTIVE;
-		break;
-	case COMP_TRIGGER_STOP:
-	case COMP_TRIGGER_PAUSE:
-		p->status = COMP_STATE_PAUSED;
-		break;
-	default:
-		break;
-	}
-
-	return  0;
-}
-
-#else /* CONFIG_LIBRARY */
-
 /* only collect scheduling components */
 static int pipeline_comp_list(struct comp_dev *current,
 			      struct comp_buffer *calling_buf,
@@ -471,7 +438,6 @@ int pipeline_trigger(struct pipeline *p, struct comp_dev *host, int cmd)
 
 	return 0;
 }
-#endif /* CONFIG_LIBRARY */
 
 /* Runs in IPC or in pipeline task context */
 static int pipeline_comp_trigger(struct comp_dev *current,
diff --git a/src/debug/CMakeLists.txt b/src/debug/CMakeLists.txt
index 5cb8e8bd9c6c..d91bd79234e8 100644
--- a/src/debug/CMakeLists.txt
+++ b/src/debug/CMakeLists.txt
@@ -1,9 +1,5 @@
 # SPDX-License-Identifier: BSD-3-Clause
 
-if(CONFIG_GDB_DEBUG)
-	add_subdirectory(gdb)
-endif()
-
 add_subdirectory(tester)
 
 is_zephyr(zephyr)
diff --git a/src/debug/gdb/CMakeLists.txt b/src/debug/gdb/CMakeLists.txt
deleted file mode 100644
index 4ca1af254b05..000000000000
--- a/src/debug/gdb/CMakeLists.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-
-# Common to Zephyr and XTOS
-add_local_sources(sof
-	gdb.c
-	ringbuffer.c
-)
diff --git a/src/debug/gdb/README.md b/src/debug/gdb/README.md
deleted file mode 100644
index 33b6a31915c1..000000000000
--- a/src/debug/gdb/README.md
+++ /dev/null
@@ -1,65 +0,0 @@
-# GDB Remote Debugging Stub
-
-The Sound Open Firmware (SOF) project carries a GNU Debugger (GDB) stub directly integrated with the framework's exception handlers. This translates commands sent by a GDB client (running on the host Linux machine) into architecture-specific logic.
-
-## Feature Overview
-
-Instead of completely relying on complex JTAG setups, developers can use this stub to dynamically introspect panic states, stack traces, and variable states during firmware execution, particularly inside isolated SoC DSP cores.
-
-When the firmware faults or hits a defined breakpoint, the exception vector routes control into this stub. It then waits for GDB Remote Protocol packet streams (ASCII formatted over the SOF mailbox/shared memory window). The Host reads these mailbox slots and pushes/pulls responses to its active GNU Debugger session.
-
-## Architecture
-
-Data moves between the Host GDB environment, the physical mailboxes bounding the DSP domain, the DSP firmware's built-in stub, and the active exception state.
-
-```mermaid
-sequenceDiagram
-    participant GdbSession as Host GDB Client
-    participant IPC as SOF Driver / ALSA
-    participant Stub as Firmware GDB Stub (gdb_parser)
-    participant HW as DSP Context Registers
-
-    HW-->>Stub: Hard Fault / Breakpoint Hit
-    activate Stub
-
-    Note over Stub: Stores fault context (sregs/aregs)
-
-    Stub-->>IPC: Write Mailbox: Breakpoint Notification
-
-    GdbSession->>IPC: Send Packet (e.g., $g#67 to Read Regs)
-    IPC->>Stub: Passes 'g' string
-
-    Stub->>HW: Reads requested register values
-    HW-->>Stub: Values
-
-    Stub->>Stub: mem_to_hex() formatting
-    Stub-->>GdbSession: Returns hex payload via Mailbox
-
-    GdbSession->>IPC: Send Packet ($c#63 to Continue)
-    IPC->>Stub: Process 'c'
-    Stub->>HW: Restores Context, Retains Execution
-    deactivate Stub
-```
-
-## How to Enable
-
-A basic GDB debugging configuration is exposed via Kconfig and must be explicitly bound:
-
-* `CONFIG_GDB_DEBUG`: Needs to be toggled `=y` to compile `src/debug/gdb/gdb.c` into the main application.
-
-Additionally, the overarching architecture requires the corresponding Exception vectors to be rewritten. In Zephyr OS based builds (which currently drive native architectures), fatal exception handling must be configured to pass register dumps recursively to `gdb_handle_exception()`.
-
-## Usage and Protocols
-
-The protocol adheres precisely to the standard GDB remote serial specification. Each string packet expects the format:
-
-`$<packet-data>#<check-sum>`
-
-Supported Command Handlers inside the Stub:
-
-* `g` (Read all registers) / `G` (Write all registers)
-* `m` (Read memory) / `M` (Write memory)
-* `p` (Read specific register) / `P` (Write specific register)
-* `v` (Query architecture/support details like `vCont`)
-* `c` / `s` (Continue execution / Single-step)
-* `z` / `Z` (Insert/Remove breakpoints)
diff --git a/src/debug/gdb/gdb.c b/src/debug/gdb/gdb.c
deleted file mode 100644
index 0345acfced92..000000000000
--- a/src/debug/gdb/gdb.c
+++ /dev/null
@@ -1,480 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-//
-// Copyright(c) 2018 Intel Corporation. All rights reserved.
-//
-// Author: Marcin Rajwa <marcin.rajwa@linux.intel.com>
-
-/*
- * GDB Stub - parse incoming GDB packets, control FW accordingly and provide
- * a reply to the GDB server.
- *
- */
-
-#include <sof/debug/gdb/gdb.h>
-#include <sof/debug/gdb/ringbuffer.h>
-#include <rtos/cache.h>
-#include <string.h>
-
-/* local functions */
-static int get_hex(unsigned char ch);
-static int hex_to_int(unsigned char **ptr, int *int_value);
-static void put_packet(unsigned char *buffer);
-static unsigned char *get_packet(void);
-static void gdb_log_exception(char *message);
-static unsigned char *mem_to_hex(void *mem_,
-				 unsigned char *buf, int count);
-static unsigned char *hex_to_mem(const unsigned char *buf, void *mem_,
-				 int count);
-static inline int gdb_parser(void);
-
-/* main buffers */
-static unsigned char remcom_in_buffer[GDB_BUFMAX];
-static unsigned char remcom_out_buffer[GDB_BUFMAX];
-
-static const char hex_chars[] = "0123456789abcdef";
-
-/* registers backup conatiners */
-int sregs[256];
-int aregs[64];
-
-void gdb_init(void)
-{
-	init_buffers();
-}
-
-/* scan for the GDB packet sequence $<data>#<check_sum> */
-unsigned char *get_packet(void)
-{
-	unsigned char *buffer = &remcom_in_buffer[0];
-	unsigned char check_sum;
-	unsigned char xmitcsum;
-	int count;
-	unsigned char ch;
-
-	/* wait around for the start character, ignore all other characters */
-	while ((ch = get_debug_char()) != '$')
-		;
-retry:
-	check_sum = 0;
-	xmitcsum = -1;
-	count = 0;
-
-	/* now, read until a # or end of buffer is found */
-	while (count < GDB_BUFMAX - 1) {
-		ch = get_debug_char();
-
-		if (ch == '$')
-			goto retry;
-		if (ch == '#')
-			break;
-		check_sum = check_sum + ch;
-		buffer[count] = ch;
-		count++;
-	}
-	/* mark end of the sequence */
-	buffer[count] = 0x00;
-	if (ch == '#') {
-		/* We have request already, now fetch its check_sum */
-		ch = get_debug_char();
-		xmitcsum = get_hex(ch) << 4;
-		ch = get_debug_char();
-		xmitcsum += get_hex(ch);
-
-		if (check_sum != xmitcsum) {
-			/* TODO: handle wrong check_sums */
-			put_debug_char('+');
-		} else {
-			/* successful transfer */
-			put_debug_char('+');
-	/*
-	 * if a sequence char is present
-	 * reply the sequence ID
-	 */
-			if (buffer[2] == ':') {
-				put_debug_char(buffer[0]);
-				put_debug_char(buffer[1]);
-
-				return &buffer[3];
-			}
-		}
-	}
-	return buffer;
-}
-
-/* Convert ch from a request to an int */
-static int get_hex(unsigned char ch)
-{
-	if (ch >= 'a' && ch <= 'f')
-		return ch - 'a' + 10;
-	if (ch >= '0' && ch <= '9')
-		return ch - '0';
-	if (ch >= 'A' && ch <= 'F')
-		return ch - 'A' + 10;
-	return -1;
-}
-
-void gdb_handle_exception(void)
-{
-	gdb_log_exception("Hello from GDB!");
-
-	while (gdb_parser())
-		;/* do nothing */
-}
-
-/**
- * \brief Parse incoming GDB packets.
- *
- * Every incoming packet has the format: $packet-data#check-sum
- * packet-data varies depending on command. Full description
- * of each command packet can be found in GNU GDB reference manual.
- */
-static inline int gdb_parser(void)
-{
-	unsigned char *request;
-	unsigned int i;
-	int addr;
-	int length;
-	unsigned int windowbase = (4 * sregs[DEBUG_WINDOWBASE]);
-
-	request = get_packet();
-	/* Log any exception caused by debug exception */
-	gdb_debug_info(request);
-	/* Pick incoming request handler */
-	unsigned char command = *request++;
-
-	switch (command) {
-	/* Continue normal program execution and leave debug handler */
-	case 'c':
-		/* incoming packet has the form $c,ADDRESS#CH, where:
-		 * c - continue command identifier,
-		 * ADDRESS - address on which to continue
-		 * CH - two bytes checksum.
-		 */
-		if (hex_to_int(&request, &addr))
-			sregs[DEBUG_PC] = addr;
-
-		/* return from exception */
-		return 0;
-	/* insert breakpoint */
-	case 'Z':
-		switch (*request++) {
-		/* HW breakpoint */
-		case '1':
-		/* Incoming packet has the form $ZX,ADDRESS,LEN,#CH, where:
-		 * Z - breakpoint command identifier, X - 0/1, SW/HW breakpoint
-		 * ADDRESS - address on which breakpoint shall be put
-		 * LEN - address length in bytes, CH - two bytes checksum.
-		 */
-			if (*request++ == ',' && hex_to_int(&request, &addr) &&
-			    *request++ == ',' && hex_to_int(&request, &length)
-			    && *request == 0) {
-				for (i = 0; i < DEBUG_NUM_IBREAK; ++i) {
-					if (!(sregs[DEBUG_IBREAKENABLE] &
-					    (1 << i)) ||
-					    sregs[DEBUG_IBREAKA + i] == addr) {
-						sregs[DEBUG_IBREAKA + i] =
-							addr;
-						sregs[DEBUG_IBREAKENABLE] |=
-							(1 << i);
-						arch_gdb_write_sr(
-							(DEBUG_IBREAKA + i),
-							sregs);
-						arch_gdb_write_sr(
-							DEBUG_IBREAKENABLE,
-							sregs);
-						break;
-					}
-				}
-
-				if (i == DEBUG_NUM_IBREAK) {
-					strcpy((char *)remcom_out_buffer,
-					       "E02");
-				} else {
-					strcpy((char *)remcom_out_buffer, "OK");
-					sregs[DEBUG_INTENABLE] &=
-					GDB_DISABLE_LOWER_INTERRUPTS_MASK;
-					arch_gdb_write_sr(DEBUG_INTENABLE,
-							  sregs);
-				}
-			} else {
-				strcpy((char *)remcom_out_buffer, "E01");
-			}
-			break;
-		/* SW breakpoints */
-		default:
-			/* send empty response to indicate thet SW breakpoints
-			 *  are not supported
-			 */
-			strcpy((char *)remcom_out_buffer, "");
-			break;
-		}
-		break;
-	/* remove HW breakpoint */
-	case 'z':
-		switch (*request++) {
-		/* Incoming packet has the form $zX,ADDRESS,LEN,#CH, where:
-		 * Z - breakpoint command identifier, X - 0/1, SW/HW breakpoint
-		 * ADDRESS - address from which breakpoint shall be removed
-		 * LEN - address length in bytes, CH - two bytes checksum.
-		 */
-		case '1':
-			if (*request++ == ',' && hex_to_int(&request, &addr) &&
-			*request++ == ',' && hex_to_int(&request, &length)) {
-				for (i = 0; i < DEBUG_NUM_IBREAK; ++i) {
-					if (sregs[DEBUG_IBREAKENABLE] &
-					    (1 << i) &&
-					    sregs[DEBUG_IBREAKA + i] == addr) {
-						sregs[DEBUG_IBREAKENABLE]
-						&= ~(1 << i);
-						arch_gdb_write_sr(
-							DEBUG_IBREAKENABLE,
-							sregs);
-						break;
-					}
-				}
-				if (i == DEBUG_NUM_IBREAK)
-					strcpy((char *)remcom_out_buffer,
-					"E02");
-				else
-					strcpy((char *)remcom_out_buffer, "OK");
-			} else {
-				/* respond with error message */
-				strcpy((char *)remcom_out_buffer, "E01");
-			}
-			break;
-		/* SW breakpoints */
-		default:
-			/* send empty response to indicate thet SW breakpoints
-			 *  are not supported
-			 */
-			strcpy((char *)remcom_out_buffer, "");
-			break;
-		}
-		break;
-	/* single step in the code */
-	case 's':
-		/* incoming packet has the form $s#CH, where:
-		 * s - step command identifier,
-		 * CH - two bytes checksum.
-		 */
-		if (hex_to_int(&request, &addr))
-			sregs[DEBUG_PC] = addr;
-		arch_gdb_single_step(sregs);
-		return 0;
-	/* read register */
-	case 'p':
-		/* Incoming packet has the form $p,REGISTER#CH, where:
-		 * p - read register command identifier,
-		 * REGISTER - register number to read,
-		 * CH - two bytes checksum.
-		 */
-		if (hex_to_int(&request, &addr)) {
-			/* read address register in the current window */
-			if (addr < GDB_AR_REG_RANGE) {
-				mem_to_hex(aregs + addr, remcom_out_buffer, 4);
-			} else if (addr == GDB_PC_REG_ID) {
-				/* read PC */
-				mem_to_hex(sregs + DEBUG_PC,
-					remcom_out_buffer, 4);
-			} else if (addr >= GDB_AREG_RANGE &&
-				   addr < (GDB_AREG_RANGE + DEBUG_NUM_AREGS)) {
-				mem_to_hex(aregs + ((addr - windowbase) &
-					   GDB_REGISTER_MASK),
-					   remcom_out_buffer, 4);
-			} else if (addr >= GDB_SPEC_REG_RANGE_START &&
-				   addr < GDB_SPEC_REG_RANGE_END) {
-				addr &= GDB_REGISTER_MASK;
-				arch_gdb_read_sr(addr);
-				mem_to_hex(sregs + addr, remcom_out_buffer, 4);
-			} else if (addr >= GDB_SPEC_REG_RANGE_END &&
-				   addr < GDB_REG_RANGE_END) {
-				strcpy((char *)remcom_out_buffer,
-						"deadbabe");
-			} else {
-				/* unexpected register number */
-				strcpy((char *)remcom_out_buffer, "E00");
-			}
-		}
-		break;
-	/* write register */
-	case 'P':
-		/* Incoming packet has the form $P,REGISTER#CH, where:
-		 * P - write register command identifier,
-		 * REGISTER - register number to write,
-		 * CH - two bytes checksum.
-		 */
-		if (hex_to_int(&request, &addr) && *(request++) == '=') {
-			int ok = 1;
-
-			if (addr < GDB_AR_REG_RANGE) {
-				hex_to_mem(request, aregs + addr, 4);
-			} else if (addr == GDB_PC_REG_ID) {
-				hex_to_mem(request, sregs + DEBUG_PC, 4);
-			} else if (addr >= GDB_AREG_RANGE && addr <
-				   GDB_AREG_RANGE + DEBUG_NUM_AREGS) {
-				hex_to_mem(request, aregs +
-				((addr - windowbase) &	GDB_REGISTER_MASK), 4);
-			} else if (addr >= GDB_SPEC_REG_RANGE_START &&
-				   addr < GDB_SPEC_REG_RANGE_END) {
-				addr &= GDB_REGISTER_MASK;
-				hex_to_mem(request, sregs + addr, 4);
-			} else {
-				ok = 0;
-				strcpy((char *)remcom_out_buffer, "E00");
-			}
-			if (ok)
-				strcpy((char *)remcom_out_buffer, "OK");
-		}
-		break;
-	/* read memory */
-	case 'm':
-		/* Incoming packet has the form $m,ADDRESS#CH, where:
-		 * m - read address command identifier,
-		 * ADDRESS - address to read from,
-		 * CH - two bytes checksum.
-		 */
-		i = hex_to_int(&request, &addr);
-		if (i == GDB_VALID_MEM_ADDRESS_LEN &&
-		    ((addr & GDB_VALID_MEM_START_BYTE) >> 28) ==
-		    GDB_VALID_MEM_START_BYTE &&
-		    *request++ == ',' && hex_to_int(&request, &length)) {
-			if (mem_to_hex((void *)addr, remcom_out_buffer, length))
-				break;
-			/* wrong memory address - respond with error message */
-			strcpy((char *)remcom_out_buffer, "E03");
-		} else {
-			/* wrong packet format - respond with error message */
-			strcpy((char *)remcom_out_buffer, "E01");
-		}
-		break;
-	/* write memory */
-	case 'X': /* binary mode */
-	case 'M':
-		/* Incoming packet has the form $M,ADDRESS#CH, where:
-		 * M - write address command identifier,
-		 * ADDRESS - address to write into,
-		 * CH - two bytes checksum.
-		 */
-		if (hex_to_int(&request, &addr) && *request++ == ',' &&
-		    hex_to_int(&request, &length) && *request++ == ':') {
-			if (hex_to_mem(request, (void *)addr, length))
-				strcpy((char *)remcom_out_buffer, "OK");
-			else
-				strcpy((char *)remcom_out_buffer, "E03");
-		} else {
-			strcpy((char *)remcom_out_buffer, "E02");
-		}
-		break;
-	default:
-		gdb_log_exception("Unknown GDB command.");
-		break;
-	}
-	/* reply to the request */
-	put_packet(remcom_out_buffer);
-
-	return 1;
-}
-
-/*
- * While we find nice hex chars, build an int.
- * Return number of chars processed.
- */
-static int hex_to_int(unsigned char **ptr, int *int_value)
-{
-	int num_chars = 0;
-	int hex_value;
-
-	*int_value = 0;
-	if (!ptr)
-		return 0;
-
-	while (**ptr) {
-		hex_value = get_hex(**ptr);
-		if (hex_value < 0)
-			break;
-
-		*int_value = (*int_value << 4) | hex_value;
-		num_chars++;
-		(*ptr)++;
-	}
-	return num_chars;
-}
-
-/* Send the packet to the buffer */
-static void put_packet(unsigned char *buffer)
-{
-	unsigned char check_sum;
-	int count;
-	unsigned char ch;
-
-	/* $<packet_info>#<check_sum> */
-	do {
-		put_debug_char('$');
-		check_sum = 0;
-		count = 0;
-
-		while ((ch = buffer[count])) {
-			put_debug_char(ch);
-			buffer[count] = 0;
-			check_sum += ch;
-			count += 1;
-		}
-
-		put_debug_char('#');
-		put_debug_char(hex_chars[check_sum >> 4]);
-		put_debug_char(hex_chars[check_sum & 0xf]);
-
-	} while (get_debug_char() != '+');
-}
-
-static void gdb_log_exception(char *message)
-{
-	while (*message)
-		put_exception_char(*message++);
-}
-
-/* Convert the memory pointed to by mem into hex, placing result in buf.
- * Return a pointer to the last char put in buf (null), in case of mem fault,
- * return 0.
- */
-static unsigned char *mem_to_hex(void *mem_, unsigned char *buf,
-				 int count)
-{
-	unsigned char *mem = mem_;
-	unsigned char ch;
-
-	if (!mem || !buf)
-		return NULL;
-	while (count-- > 0) {
-		ch = arch_gdb_load_from_memory(mem);
-		mem++;
-		*buf++ = hex_chars[ch >> 4];
-		*buf++ = hex_chars[ch & 0xf];
-	}
-
-	*buf = 0;
-	return buf;
-}
-
-/* convert the hex array pointed to by buf into binary to be placed in mem
- * return a pointer to the character after the last byte written
- */
-static unsigned char *hex_to_mem(const unsigned char *buf, void *mem_,
-				 int count)
-{
-	unsigned char *mem = mem_;
-	int i;
-	unsigned char ch;
-
-	if (!mem || !buf)
-		return NULL;
-	for (i = 0; i < count; i++) {
-		ch = get_hex(*buf++) << 4;
-		ch |= get_hex(*buf++);
-		arch_gdb_memory_load_and_store(mem, ch);
-		mem++;
-	}
-
-	dcache_writeback_region((__sparse_force void __sparse_cache *)mem, count);
-	return mem;
-}
diff --git a/src/debug/gdb/ringbuffer.c b/src/debug/gdb/ringbuffer.c
deleted file mode 100644
index 4afd415fd3af..000000000000
--- a/src/debug/gdb/ringbuffer.c
+++ /dev/null
@@ -1,51 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-//
-// Copyright(c) 2019 Intel Corporation. All rights reserved.
-//
-// Author: Marcin Rajwa <marcin.rajwa@linux.intel.com>
-
-#include <sof/debug/gdb/ringbuffer.h>
-#include <sof/lib/mailbox.h>
-
-#define BUFFER_OFFSET 0x120
-
-volatile struct ring * const rx = (void *)mailbox_get_debug_base();
-volatile struct ring * const tx = (void *)(mailbox_get_debug_base() +
-					   BUFFER_OFFSET);
-volatile struct ring * const debug = (void *)(mailbox_get_debug_base() +
-					      (2 * BUFFER_OFFSET));
-
-void init_buffers(void)
-{
-	rx->head = rx->tail = 0;
-	tx->head = tx->tail = 0;
-	debug->head = debug->tail = 0;
-}
-
-void put_debug_char(unsigned char c)
-{
-	while (!ring_have_space(tx))
-		;
-
-	tx->data[tx->head] = c;
-	tx->head = ring_next_head(tx);
-}
-
-unsigned char get_debug_char(void)
-{
-	unsigned char v;
-
-	while (!ring_have_data(rx))
-		;
-
-	v = rx->data[rx->tail];
-	rx->tail = ring_next_tail(rx);
-
-	return v;
-}
-
-void put_exception_char(char c)
-{
-	debug->data[debug->head] = c;
-	debug->head = ring_next_head(debug);
-}
diff --git a/src/drivers/CMakeLists.txt b/src/drivers/CMakeLists.txt
index dc82ed66a737..97d70f9b4d58 100644
--- a/src/drivers/CMakeLists.txt
+++ b/src/drivers/CMakeLists.txt
@@ -1,26 +1,5 @@
 # SPDX-License-Identifier: BSD-3-Clause
 
-if(CONFIG_IMX)
-	add_subdirectory(imx)
-endif()
-
-if(CONFIG_AMD)
-	add_subdirectory(amd)
-endif()
-
-if(CONFIG_MEDIATEK)
-	add_subdirectory(mediatek)
-endif()
-
 if(CONFIG_LIBRARY)
 	add_subdirectory(host)
-	return()
-endif()
-
-if(CONFIG_DW)
-	add_subdirectory(dw)
 endif()
-
-add_subdirectory(generic)
-
-add_local_sources(sof interrupt.c)
diff --git a/src/drivers/Kconfig b/src/drivers/Kconfig
index 7818bd74796b..3349688d23a5 100644
--- a/src/drivers/Kconfig
+++ b/src/drivers/Kconfig
@@ -2,12 +2,6 @@
 
 menu "Drivers"
 
-rsource "dw/Kconfig"
-
-rsource "imx/Kconfig"
-
-rsource "mediatek/Kconfig"
-
 rsource "amd/Kconfig"
 
 config DUMMY_DMA
diff --git a/src/drivers/amd/CMakeLists.txt b/src/drivers/amd/CMakeLists.txt
deleted file mode 100644
index 8b58af2b3017..000000000000
--- a/src/drivers/amd/CMakeLists.txt
+++ /dev/null
@@ -1,13 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-if(CONFIG_RENOIR OR CONFIG_VANGOGH OR CONFIG_REMBRANDT OR CONFIG_ACP_6_3 OR CONFIG_ACP_7_0)
-	add_subdirectory(common)
-endif()
-if(CONFIG_RENOIR)
-	add_subdirectory(renoir)
-elseif(CONFIG_REMBRANDT OR CONFIG_ACP_6_3 OR CONFIG_ACP_7_0)
-	add_subdirectory(rembrandt)
-elseif(CONFIG_VANGOGH)
-	add_subdirectory(vangogh)
-elseif(CONFIG_ACP_7_X)
-	add_subdirectory(acp_7_x)
-endif()
diff --git a/src/drivers/amd/acp_7_x/CMakeLists.txt b/src/drivers/amd/acp_7_x/CMakeLists.txt
deleted file mode 100644
index 5dd81656d1ea..000000000000
--- a/src/drivers/amd/acp_7_x/CMakeLists.txt
+++ /dev/null
@@ -1,5 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-
-add_local_sources(sof
-	ipc.c
-)
diff --git a/src/drivers/amd/common/CMakeLists.txt b/src/drivers/amd/common/CMakeLists.txt
deleted file mode 100644
index 4e74f474d72f..000000000000
--- a/src/drivers/amd/common/CMakeLists.txt
+++ /dev/null
@@ -1,11 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-
-add_local_sources(sof
-	acp_dma.c
-	acp_bt_dai.c
-	acp_dmic_dai.c
-	ipc.c
-	timer.c
-	acp_sp_dma.c
-	acp_dmic_dma.c
-)
diff --git a/src/drivers/amd/common/timer.c b/src/drivers/amd/common/timer.c
deleted file mode 100644
index e2fa9d3d9e6c..000000000000
--- a/src/drivers/amd/common/timer.c
+++ /dev/null
@@ -1,101 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-//
-//Copyright(c) 2023 AMD. All rights reserved.
-//
-//Author:       Basavaraj Hiregoudar <basavaraj.hiregoudar@amd.com>
-//              SaiSurya, Ch <saisurya.chakkaveeravenkatanaga@amd.com>
-
-#include <xtensa/config/core-isa.h>
-#include <sof/audio/component_ext.h>
-#include <sof/audio/component.h>
-#include <rtos/interrupt.h>
-#include <rtos/timer.h>
-#include <sof/lib/memory.h>
-#include <sof/platform.h>
-#include <ipc/stream.h>
-#include <errno.h>
-#include <stdint.h>
-
-void platform_timer_start(struct timer *timer)
-{
-	/* Nothing to do here */
-}
-
-void platform_timer_stop(struct timer *timer)
-{
-	arch_timer_disable(timer);
-}
-
-int64_t platform_timer_set(struct timer *timer, uint64_t ticks)
-{
-	return arch_timer_set(timer, ticks);
-}
-
-void platform_timer_clear(struct timer *timer)
-{
-	arch_timer_clear(timer);
-}
-
-uint64_t platform_timer_get(struct timer *timer)
-{
-	return arch_timer_get_system(timer);
-}
-
-uint64_t platform_timer_get_atomic(struct timer *timer)
-{
-	return arch_timer_get_system(timer);
-}
-
-void platform_host_timestamp(struct comp_dev *host,
-			     struct sof_ipc_stream_posn *posn)
-{
-	int err;
-
-	err = comp_position(host, posn);
-	if (err == 0)
-		posn->flags |= SOF_TIME_HOST_VALID | SOF_TIME_HOST_64;
-}
-
-void platform_dai_timestamp(struct comp_dev *dai,
-			    struct sof_ipc_stream_posn *posn)
-{
-	int err;
-
-	err = comp_position(dai, posn);
-	if (err == 0)
-		posn->flags |= SOF_TIME_DAI_VALID;
-
-	posn->wallclock = timer_get_system(timer_get()) - posn->wallclock;
-	posn->flags |= SOF_TIME_WALL_VALID | SOF_TIME_WALL_64;
-}
-
-void platform_dai_wallclock(struct comp_dev *dai, uint64_t *wallclock)
-{
-	*wallclock = timer_get_system(timer_get());
-}
-
-int timer_register(struct timer *timer, void(*handler)(void *arg), void *arg)
-{
-	switch (timer->id) {
-	case TIMER0:
-	case TIMER1:
-		return arch_timer_register(timer, handler, arg);
-	default:
-		return -EINVAL;
-	}
-}
-
-void timer_unregister(struct timer *timer, void *arg)
-{
-	interrupt_unregister(timer->irq, arg);
-}
-
-void timer_enable(struct timer *timer, void *arg, int core)
-{
-	interrupt_enable(timer->irq, arg);
-}
-
-void timer_disable(struct timer *timer, void *arg, int core)
-{
-	interrupt_disable(timer->irq, arg);
-}
diff --git a/src/drivers/amd/rembrandt/CMakeLists.txt b/src/drivers/amd/rembrandt/CMakeLists.txt
deleted file mode 100644
index 08b13df744d2..000000000000
--- a/src/drivers/amd/rembrandt/CMakeLists.txt
+++ /dev/null
@@ -1,15 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-
-add_local_sources(sof
-	acp_dma.c
-	acp_sp_dai.c
-	acp_hs_dai.c
-	acp_sw_audio_dai.c
-	interrupt.c
-	ipc.c
-	acp_bt_dma.c
-	acp_sp_dma.c
-	acp_hs_dma.c
-	acp_sw_audio_dma.c
-	acp_dmic_dma.c
-)
diff --git a/src/drivers/amd/rembrandt/acp_hs_dma.c b/src/drivers/amd/rembrandt/acp_hs_dma.c
index 75c562bc0318..f00c408bcff0 100644
--- a/src/drivers/amd/rembrandt/acp_hs_dma.c
+++ b/src/drivers/amd/rembrandt/acp_hs_dma.c
@@ -98,10 +98,6 @@ static int acp_dai_hs_dma_start(struct dma_chan_data *channel)
 		/* Request SMU to set aclk to 600 Mhz */
 		acp_change_clock_notify(600000000);
 		io_reg_write((PU_REGISTER_BASE + ACP_CLKMUX_SEL), ACP_ACLK_CLK_SEL);
-#ifdef CONFIG_ACP_6_3
-		if (!io_reg_read(PU_REGISTER_BASE + ACP_I2S_196MHZ_CLK_SEL))
-			io_reg_write((PU_REGISTER_BASE + ACP_I2S_196MHZ_CLK_SEL), 0x1);
-#endif
 	}
 
 	if (channel->direction == DMA_DIR_MEM_TO_DEV) {
@@ -185,10 +181,6 @@ static int acp_dai_hs_dma_stop(struct dma_chan_data *channel)
 		if (!acp_pdm_en) {
 			io_reg_write((PU_REGISTER_BASE + ACP_CLKMUX_SEL), ACP_INTERNAL_CLK_SEL);
 			acp_change_clock_notify(0);
-#ifdef CONFIG_ACP_6_3
-			if (io_reg_read(PU_REGISTER_BASE + ACP_I2S_196MHZ_CLK_SEL))
-				io_reg_write((PU_REGISTER_BASE + ACP_I2S_196MHZ_CLK_SEL), 0x0);
-#endif
 		}
 	}
 	return 0;
diff --git a/src/drivers/amd/rembrandt/acp_sw_audio_dai.c b/src/drivers/amd/rembrandt/acp_sw_audio_dai.c
deleted file mode 100644
index 65bd9ecd3c45..000000000000
--- a/src/drivers/amd/rembrandt/acp_sw_audio_dai.c
+++ /dev/null
@@ -1,117 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-//
-//Copyright(c) 2023, 2026 AMD. All rights reserved.
-//
-//Author:       Basavaraj Hiregoudar <basavaraj.hiregoudar@amd.com>
-//              Maruthi Machani <maruthi.machani@amd.com>
-//              Sivasubramanian <sravisar@amd.com>
-
-#include <sof/drivers/acp_dai_dma.h>
-#include <sof/lib/uuid.h>
-#include <sof/trace/trace.h>
-
-SOF_DEFINE_REG_UUID(swaudiodai);
-
-/* unused with Zephyr, generates no output */
-DECLARE_TR_CTX(swaudiodai_tr, SOF_UUID(swaudiodai_uuid), LOG_LEVEL_INFO);
-
-static inline int swaudiodai_set_config(struct dai *dai, struct ipc_config_dai *common_config,
-					const void *spec_config)
-{
-	const struct sof_ipc_dai_config *config = spec_config;
-	struct acp_pdata *acpdata = dai_get_drvdata(dai);
-
-	acpdata->config = *config;
-	acpdata->sdw_params = config->acpsdw;
-
-	return 0;
-}
-
-static int swaudiodai_trigger(struct dai *dai, int cmd, int direction)
-{
-	/* nothing to do on rembrandt for SW dai */
-	return 0;
-}
-
-static int swaudiodai_probe(struct dai *dai)
-{
-	struct acp_pdata *acp;
-
-	dai_info(dai, "#$AMD$# SW dai probe");
-	/* allocate private data */
-	acp = rzalloc(SOF_MEM_FLAG_KERNEL | SOF_MEM_FLAG_COHERENT, sizeof(*acp));
-	if (!acp) {
-		dai_err(dai, "SW dai probe alloc failed");
-		return -ENOMEM;
-	}
-	dai_set_drvdata(dai, acp);
-
-	return 0;
-}
-
-static int swaudiodai_remove(struct dai *dai)
-{
-	struct acp_pdata *acp = dai_get_drvdata(dai);
-
-	dai_info(dai, "entry");
-	rfree(acp);
-	dai_set_drvdata(dai, NULL);
-
-	return 0;
-}
-
-static int swaudiodai_get_fifo(struct dai *dai, int direction, int stream_id)
-{
-	switch (direction) {
-	case DAI_DIR_PLAYBACK:
-	case DAI_DIR_CAPTURE:
-		return dai_fifo(dai, direction);
-	default:
-		dai_err(dai, "Invalid direction");
-		return -EINVAL;
-	}
-}
-
-static int swaudiodai_get_handshake(struct dai *dai, int direction, int stream_id)
-{
-	int handshake = dai->plat_data.fifo[direction].handshake;
-
-	interrupt_get_irq(handshake, "irqsteer1");
-
-	return dai->plat_data.fifo[direction].handshake;
-}
-
-static int swaudiodai_get_hw_params(struct dai *dai,
-				    struct sof_ipc_stream_params *params,
-				    int dir)
-{
-	struct acp_pdata *acpdata = dai_get_drvdata(dai);
-
-	/* DAI currently supports only these parameters */
-	params->rate = acpdata->sdw_params.rate;
-	params->channels = acpdata->sdw_params.channels;
-	params->buffer_fmt = SOF_IPC_BUFFER_INTERLEAVED;
-	params->frame_fmt = SOF_IPC_FRAME_S16_LE;
-
-	return 0;
-}
-
-const struct dai_driver acp_swaudiodai_driver = {
-	.type = SOF_DAI_AMD_SDW,
-	.uid = SOF_UUID(swaudiodai_uuid),
-#if !CONFIG_ZEPHYR_LOG
-	.tctx = &swaudiodai_tr,
-#endif
-	.dma_dev = DMA_DEV_SW,
-	.dma_caps = DMA_CAP_SW,
-	.ops = {
-		.trigger		= swaudiodai_trigger,
-		.set_config		= swaudiodai_set_config,
-		.probe			= swaudiodai_probe,
-		.remove			= swaudiodai_remove,
-		.get_fifo		= swaudiodai_get_fifo,
-		.get_handshake		= swaudiodai_get_handshake,
-		.get_hw_params          = swaudiodai_get_hw_params,
-	},
-};
-
diff --git a/src/drivers/amd/rembrandt/acp_sw_audio_dma.c b/src/drivers/amd/rembrandt/acp_sw_audio_dma.c
deleted file mode 100644
index 48e27ff7d455..000000000000
--- a/src/drivers/amd/rembrandt/acp_sw_audio_dma.c
+++ /dev/null
@@ -1,576 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause//
-//Copyright(c) 2023 AMD. All rights reserved.
-//
-//Author:       Basavaraj Hiregoudar <basavaraj.hiregoudar@amd.com>
-//              Maruthi Machani <maruthi.machani@amd.com>
-
-#include <sof/audio/component.h>
-#include <sof/drivers/acp_dai_dma.h>
-#include <sof/lib/notifier.h>
-#include <platform/chip_registers.h>
-#include <rtos/wait.h>
-#include <sof/lib/uuid.h>
-#include <sof/trace/trace.h>
-
-#if defined(CONFIG_ACP_6_3) || defined(CONFIG_ACP_7_0)
-
-SOF_DEFINE_REG_UUID(acp_sw_audio);
-
-/* unused with Zephyr, generates no output */
-DECLARE_TR_CTX(acp_sw_audio_tr, SOF_UUID(acp_sw_audio_uuid), LOG_LEVEL_INFO);
-
-#if defined(CONFIG_ACP_6_3)
-#define DMA_CH_COUNT			8
-#elif defined(CONFIG_ACP_7_0)
-#define DMA_CH_COUNT			12
-#endif
-
-//initialization of soundwire-0 fifos(Audio, BT and HS)
-#define SW0_AUDIO_FIFO_SIZE			128
-#define SW0_AUDIO_TX_FIFO_ADDR		0
-#define SW0_AUDIO_RX_FIFO_ADDR		(SW0_AUDIO_TX_FIFO_ADDR + SW0_AUDIO_FIFO_SIZE)
-
-#define SW0_BT_FIFO_SIZE		128
-#define SW0_BT_TX_FIFO_ADDR		(SW0_AUDIO_RX_FIFO_ADDR + SW0_AUDIO_FIFO_SIZE)
-#define SW0_BT_RX_FIFO_ADDR		(SW0_BT_TX_FIFO_ADDR + SW0_BT_FIFO_SIZE)
-
-#define SW0_HS_FIFO_SIZE		128
-#define SW0_HS_TX_FIFO_ADDR		(SW0_BT_RX_FIFO_ADDR + SW0_BT_FIFO_SIZE)
-#define SW0_HS_RX_FIFO_ADDR		(SW0_HS_TX_FIFO_ADDR + SW0_HS_FIFO_SIZE)
-
-//initialization of soundwire-1 fifos(Audio, BT and HS)
-#define SW1_AUDIO_FIFO_SIZE			128
-#define SW1_AUDIO_TX_FIFO_ADDR		(SW0_HS_RX_FIFO_ADDR + SW0_HS_FIFO_SIZE)
-#define SW1_AUDIO_RX_FIFO_ADDR		(SW1_AUDIO_TX_FIFO_ADDR + SW1_AUDIO_FIFO_SIZE)
-
-#define SW1_BT_FIFO_SIZE		128
-#define SW1_BT_TX_FIFO_ADDR		(SW1_AUDIO_RX_FIFO_ADDR + SW1_AUDIO_FIFO_SIZE)
-#define SW1_BT_RX_FIFO_ADDR		(SW1_BT_TX_FIFO_ADDR + SW1_BT_FIFO_SIZE)
-
-#define SW1_HS_FIFO_SIZE		128
-#define SW1_HS_TX_FIFO_ADDR		(SW1_BT_RX_FIFO_ADDR + SW1_BT_FIFO_SIZE)
-#define SW1_HS_RX_FIFO_ADDR		(SW1_HS_TX_FIFO_ADDR + SW1_HS_FIFO_SIZE)
-
-static uint32_t sw_audio_buff_size_playback;
-static uint32_t sw_audio_buff_size_capture;
-
-struct sw_dev_register {
-	uint32_t	sw_dev_en;
-	uint32_t	sw_dev_en_status;
-	uint32_t	sw_dev_fifo_addr;
-	uint32_t	fifo_addr;
-	uint32_t	sw_dev_fifo_size;
-	uint32_t	fifo_size;
-	uint32_t	sw_dev_ringbuff_addr;
-	uint32_t	sw_dev_ringbuff_size;
-	uint32_t	sw_dev_dma_size;
-	uint32_t	sw_dev_dma_watermark;
-	uint32_t	sw_dev_dma_intr_status;
-	uint32_t	sw_dev_dma_intr_cntl;
-	uint32_t	statusindex;
-};
-
-static struct sw_dev_register sw_dev[DMA_CH_COUNT] = {
-{ACP_SW_HS_RX_EN, ACP_SW_HS_RX_EN_STATUS, ACP_HS_RX_FIFOADDR, SW0_HS_RX_FIFO_ADDR,
-ACP_HS_RX_FIFOSIZE, SW0_HS_FIFO_SIZE, ACP_HS_RX_RINGBUFADDR, ACP_HS_RX_RINGBUFSIZE,
-ACP_HS_RX_DMA_SIZE, ACP_HS_RX_INTR_WATERMARK_SIZE, ACP_DSP0_INTR_STAT, ACP_DSP0_INTR_CNTL, 0},
-
-{ACP_SW_HS_TX_EN, ACP_SW_HS_TX_EN_STATUS, ACP_HS_TX_FIFOADDR, SW0_HS_TX_FIFO_ADDR,
-ACP_HS_TX_FIFOSIZE, SW0_HS_FIFO_SIZE, ACP_HS_TX_RINGBUFADDR, ACP_HS_TX_RINGBUFSIZE,
-ACP_HS_TX_DMA_SIZE, ACP_HS_TX_INTR_WATERMARK_SIZE, ACP_DSP0_INTR_STAT, ACP_DSP0_INTR_CNTL, 1},
-
-{ACP_P1_SW_BT_RX_EN, ACP_P1_SW_BT_RX_EN_STATUS, ACP_P1_BT_RX_FIFOADDR, SW1_BT_RX_FIFO_ADDR,
-ACP_P1_BT_RX_FIFOSIZE, SW1_BT_FIFO_SIZE, ACP_P1_BT_RX_RINGBUFADDR, ACP_P1_BT_RX_RINGBUFSIZE,
-ACP_P1_BT_RX_DMA_SIZE, ACP_P1_BT_RX_INTR_WATERMARK_SIZE, ACP_DSP0_INTR_STAT1, ACP_DSP0_INTR_CNTL1,
-2},
-
-{ACP_P1_SW_BT_TX_EN, ACP_P1_SW_BT_TX_EN_STATUS, ACP_P1_BT_TX_FIFOADDR, SW1_BT_TX_FIFO_ADDR,
-ACP_P1_BT_TX_FIFOSIZE, SW1_BT_FIFO_SIZE, ACP_P1_BT_TX_RINGBUFADDR, ACP_P1_BT_TX_RINGBUFSIZE,
-ACP_P1_BT_TX_DMA_SIZE, ACP_P1_BT_TX_INTR_WATERMARK_SIZE, ACP_DSP0_INTR_STAT1, ACP_DSP0_INTR_CNTL1,
-3},
-
-{ACP_SW_AUDIO_RX_EN, ACP_SW_AUDIO_RX_EN_STATUS, ACP_AUDIO_RX_FIFOADDR, SW0_AUDIO_RX_FIFO_ADDR,
-ACP_AUDIO_RX_FIFOSIZE, SW0_AUDIO_FIFO_SIZE, ACP_AUDIO_RX_RINGBUFADDR, ACP_AUDIO_RX_RINGBUFSIZE,
-ACP_AUDIO_RX_DMA_SIZE, ACP_AUDIO_RX_INTR_WATERMARK_SIZE, ACP_DSP0_INTR_STAT, ACP_DSP0_INTR_CNTL, 4},
-
-{ACP_SW_AUDIO_TX_EN, ACP_SW_AUDIO_TX_EN_STATUS, ACP_AUDIO_TX_FIFOADDR, SW0_AUDIO_TX_FIFO_ADDR,
-ACP_AUDIO_TX_FIFOSIZE, SW0_AUDIO_FIFO_SIZE, ACP_AUDIO_TX_RINGBUFADDR, ACP_AUDIO_TX_RINGBUFSIZE,
-ACP_AUDIO_TX_DMA_SIZE, ACP_AUDIO_TX_INTR_WATERMARK_SIZE, ACP_DSP0_INTR_STAT, ACP_DSP0_INTR_CNTL, 5},
-
-{ACP_SW_BT_RX_EN, ACP_SW_BT_RX_EN_STATUS, ACP_BT_RX_FIFOADDR, SW0_BT_RX_FIFO_ADDR,
-ACP_BT_RX_FIFOSIZE, SW0_BT_FIFO_SIZE, ACP_BT_RX_RINGBUFADDR, ACP_BT_RX_RINGBUFSIZE,
-ACP_BT_RX_DMA_SIZE, ACP_BT_RX_INTR_WATERMARK_SIZE, ACP_DSP0_INTR_STAT, ACP_DSP0_INTR_CNTL, 2},
-
-{ACP_SW_BT_TX_EN, ACP_SW_BT_TX_EN_STATUS, ACP_BT_TX_FIFOADDR, SW0_BT_TX_FIFO_ADDR,
-ACP_BT_TX_FIFOSIZE, SW0_BT_FIFO_SIZE, ACP_BT_TX_RINGBUFADDR, ACP_BT_TX_RINGBUFSIZE,
-ACP_BT_TX_DMA_SIZE, ACP_BT_TX_INTR_WATERMARK_SIZE, ACP_DSP0_INTR_STAT, ACP_DSP0_INTR_CNTL, 3},
-
-#if defined(CONFIG_ACP_7_0)
-{ACP_P1_SW_AUDIO_RX_EN, ACP_P1_SW_AUDIO_RX_EN_STATUS, ACP_P1_AUDIO_RX_FIFOADDR,
-SW1_AUDIO_RX_FIFO_ADDR, ACP_P1_AUDIO_RX_FIFOSIZE, SW1_AUDIO_FIFO_SIZE,
-ACP_P1_AUDIO_RX_RINGBUFADDR, ACP_P1_AUDIO_RX_RINGBUFSIZE, ACP_P1_AUDIO_RX_DMA_SIZE,
-ACP_P1_AUDIO_RX_INTR_WATERMARK_SIZE, ACP_DSP0_INTR_STAT1, ACP_DSP0_INTR_CNTL1, 4},
-
-{ACP_P1_SW_AUDIO_TX_EN, ACP_P1_SW_AUDIO_TX_EN_STATUS, ACP_P1_AUDIO_TX_FIFOADDR,
-SW1_AUDIO_TX_FIFO_ADDR, ACP_P1_AUDIO_TX_FIFOSIZE, SW1_AUDIO_FIFO_SIZE,
-ACP_P1_AUDIO_TX_RINGBUFADDR, ACP_P1_AUDIO_TX_RINGBUFSIZE, ACP_P1_AUDIO_TX_DMA_SIZE,
-ACP_P1_AUDIO_TX_INTR_WATERMARK_SIZE, ACP_DSP0_INTR_STAT1, ACP_DSP0_INTR_CNTL1, 5},
-
-{ACP_P1_SW_HEADSET_RX_EN, ACP_P1_SW_HEADSET_RX_EN_STATUS, ACP_P1_HS_RX_FIFOADDR,
-SW1_HS_RX_FIFO_ADDR, ACP_P1_HS_RX_FIFOSIZE, SW1_HS_FIFO_SIZE,
-ACP_P1_HS_RX_RINGBUFADDR, ACP_P1_HS_RX_RINGBUFSIZE, ACP_P1_HS_RX_DMA_SIZE,
-ACP_P1_HS_RX_INTR_WATERMARK_SIZE, ACP_DSP0_INTR_STAT1, ACP_DSP0_INTR_CNTL1, 0},
-
-{ACP_P1_SW_HEADSET_TX_EN, ACP_P1_SW_HEADSET_TX_EN_STATUS, ACP_P1_HS_TX_FIFOADDR,
-SW1_HS_TX_FIFO_ADDR, ACP_P1_HS_TX_FIFOSIZE, SW1_HS_FIFO_SIZE,
-ACP_P1_HS_TX_RINGBUFADDR, ACP_P1_HS_TX_RINGBUFSIZE, ACP_P1_HS_TX_DMA_SIZE,
-ACP_P1_HS_TX_INTR_WATERMARK_SIZE, ACP_DSP0_INTR_STAT1, ACP_DSP0_INTR_CNTL1, 1},
-#endif
-};
-
-/* allocate next free DMA channel */
-static struct dma_chan_data *acp_dai_sw_audio_dma_channel_get(struct dma *dma,
-							      unsigned int req_chan)
-{
-	k_spinlock_key_t key;
-	struct dma_chan_data *channel;
-
-	key = k_spin_lock(&dma->lock);
-	if (req_chan >= dma->plat_data.channels) {
-		k_spin_unlock(&dma->lock, key);
-		tr_err(&acp_sw_audio_tr, "Channel %d not in range", req_chan);
-		return NULL;
-	}
-	channel = &dma->chan[req_chan];
-	if (channel->status != COMP_STATE_INIT) {
-		k_spin_unlock(&dma->lock, key);
-		tr_err(&acp_sw_audio_tr, "channel already in use %d", req_chan);
-		return NULL;
-	}
-	atomic_add(&dma->num_channels_busy, 1);
-	channel->status = COMP_STATE_READY;
-	k_spin_unlock(&dma->lock, key);
-
-	return channel;
-}
-
-/* channel must not be running when this is called */
-static void acp_dai_sw_audio_dma_channel_put(struct dma_chan_data *channel)
-{
-	k_spinlock_key_t key;
-
-	notifier_unregister_all(NULL, channel);
-	key = k_spin_lock(&channel->dma->lock);
-	channel->status = COMP_STATE_INIT;
-	atomic_sub(&channel->dma->num_channels_busy, 1);
-	k_spin_unlock(&channel->dma->lock, key);
-}
-
-static int acp_dai_sw_audio_dma_start(struct dma_chan_data *channel)
-{
-	uint32_t		sw0_audio_tx_en = 0;
-	uint32_t		sw0_audio_rx_en = 0;
-	uint32_t		acp_pdm_en;
-	int i;
-
-	for (i = 0; i < DMA_CH_COUNT; i += 2) {
-		sw0_audio_tx_en |= io_reg_read(PU_REGISTER_BASE + sw_dev[i].sw_dev_en);
-		sw0_audio_rx_en |= io_reg_read(PU_REGISTER_BASE + sw_dev[i + 1].sw_dev_en);
-	}
-
-	acp_pdm_en = io_reg_read(PU_REGISTER_BASE + ACP_WOV_PDM_ENABLE);
-	if (!sw0_audio_tx_en && !sw0_audio_rx_en && !acp_pdm_en) {
-		/* Request SMU to set aclk to 600 Mhz */
-		acp_change_clock_notify(600000000);
-		io_reg_write(PU_REGISTER_BASE + ACP_CLKMUX_SEL, ACP_ACLK_CLK_SEL);
-	}
-
-	switch (channel->direction) {
-	case DMA_DIR_MEM_TO_DEV:
-	case DMA_DIR_DEV_TO_MEM:
-		channel->status = COMP_STATE_ACTIVE;
-		io_reg_write(PU_REGISTER_BASE + sw_dev[channel->index].sw_dev_en, 1);
-		poll_for_register_delay(PU_REGISTER_BASE + sw_dev[channel->index].sw_dev_en_status,
-					0x1, 0x1, 15);
-		break;
-	default:
-		tr_err(&acp_sw_audio_tr, "Start direction not defined %d",
-		       channel->direction);
-		return -EINVAL;
-	}
-
-	return 0;
-}
-
-static int acp_dai_sw_audio_dma_release(struct dma_chan_data *channel)
-{
-	/* nothing to do on rembrandt */
-	return 0;
-}
-
-static int acp_dai_sw_audio_dma_pause(struct dma_chan_data *channel)
-{
-	/* nothing to do on rembrandt */
-	return 0;
-}
-
-static int acp_dai_sw_audio_dma_stop(struct dma_chan_data *channel)
-{
-	uint32_t		sw0_audio_tx_en = 0;
-	uint32_t		sw0_audio_rx_en = 0;
-	uint32_t		acp_pdm_en;
-	int i;
-
-	switch (channel->status) {
-	case COMP_STATE_READY:
-	case COMP_STATE_PREPARE:
-		return 0;
-	case COMP_STATE_PAUSED:
-	case COMP_STATE_ACTIVE:
-		break;
-	default:
-		return -EINVAL;
-	}
-	channel->status = COMP_STATE_READY;
-	switch (channel->direction) {
-	case DMA_DIR_MEM_TO_DEV:
-	case DMA_DIR_DEV_TO_MEM:
-		io_reg_write(PU_REGISTER_BASE + sw_dev[channel->index].sw_dev_en, 0);
-		poll_for_register_delay(PU_REGISTER_BASE + sw_dev[channel->index].sw_dev_en_status,
-					0x1, 0x0, 15);
-		break;
-	default:
-		tr_err(&acp_sw_audio_tr, "Stop direction not defined %d",
-		       channel->direction);
-		return -EINVAL;
-	}
-
-	for (i = 0; i < DMA_CH_COUNT; i += 2) {
-		sw0_audio_tx_en |= io_reg_read(PU_REGISTER_BASE + sw_dev[i].sw_dev_en);
-		sw0_audio_rx_en |= io_reg_read(PU_REGISTER_BASE + sw_dev[i + 1].sw_dev_en);
-	}
-	acp_pdm_en = io_reg_read(PU_REGISTER_BASE + ACP_WOV_PDM_ENABLE);
-
-	if (!sw0_audio_tx_en && !sw0_audio_rx_en) {
-		/* Request SMU to scale down aclk to minimum clk */
-		if (!acp_pdm_en) {
-			io_reg_write(PU_REGISTER_BASE + ACP_CLKMUX_SEL, ACP_INTERNAL_CLK_SEL);
-			acp_change_clock_notify(0);
-		}
-	}
-
-	return 0;
-}
-
-static int acp_dai_sw_audio_dma_status(struct dma_chan_data *channel,
-				       struct dma_chan_status *status,
-				       uint8_t direction)
-{
-	/* nothing to do on rembrandt */
-	return 0;
-}
-
-/* set the DMA channel configuration, source/target address, buffer sizes */
-static int acp_dai_sw_audio_dma_set_config(struct dma_chan_data *channel,
-					   struct dma_sg_config *config)
-{
-	uint32_t sw0_audio_ringbuff_addr;
-	uint32_t sw0_audio_fifo_addr;
-
-	if (!config->cyclic) {
-		tr_err(&acp_sw_audio_tr, "cyclic configurations only supported!");
-		return -EINVAL;
-	}
-	if (config->scatter) {
-		tr_err(&acp_sw_audio_tr, "scatter enabled, that is not supported for now!");
-		return -EINVAL;
-	}
-
-	channel->is_scheduling_source = true;
-	channel->direction = config->direction;
-
-	switch (channel->direction) {
-	case DMA_DIR_MEM_TO_DEV:
-		sw_audio_buff_size_playback = config->elem_array.elems[0].size *
-					config->elem_array.count;
-		/* SW Transmit FIFO Address and FIFO Size*/
-		sw0_audio_fifo_addr = sw_dev[channel->index].fifo_addr;
-		io_reg_write(PU_REGISTER_BASE + sw_dev[channel->index].sw_dev_fifo_addr,
-			     sw0_audio_fifo_addr);
-		io_reg_write(PU_REGISTER_BASE + sw_dev[channel->index].sw_dev_fifo_size,
-			     sw_dev[channel->index].fifo_size);
-
-		/* Transmit RINGBUFFER Address and size*/
-		config->elem_array.elems[0].src = (config->elem_array.elems[0].src &
-					ACP_DRAM_ADDRESS_MASK);
-		sw0_audio_ringbuff_addr = (config->elem_array.elems[0].src | ACP_SRAM);
-		io_reg_write(PU_REGISTER_BASE + sw_dev[channel->index].sw_dev_ringbuff_addr,
-			     sw0_audio_ringbuff_addr);
-		io_reg_write(PU_REGISTER_BASE + sw_dev[channel->index].sw_dev_ringbuff_size,
-			     sw_audio_buff_size_playback);
-
-		/* Transmit DMA transfer size in bytes */
-		io_reg_write(PU_REGISTER_BASE + sw_dev[channel->index].sw_dev_dma_size,
-			     (uint32_t)(64/*ACP_DMA_TRANS_SIZE_128*/));
-
-		/* Watermark size for SW transmit FIFO - Half of SW buffer size */
-		io_reg_write(PU_REGISTER_BASE + sw_dev[channel->index].sw_dev_dma_watermark,
-			     (sw_audio_buff_size_playback >> 1));
-		break;
-	case DMA_DIR_DEV_TO_MEM:
-		sw_audio_buff_size_capture = config->elem_array.elems[0].size *
-					config->elem_array.count;
-		/* SW Receive FIFO Address and FIFO Size*/
-		sw0_audio_fifo_addr = sw_dev[channel->index].fifo_addr;
-		io_reg_write(PU_REGISTER_BASE + sw_dev[channel->index].sw_dev_fifo_addr,
-			     sw0_audio_fifo_addr);
-		io_reg_write(PU_REGISTER_BASE + sw_dev[channel->index].sw_dev_fifo_size,
-			     sw_dev[channel->index].fifo_size);
-
-		/* Receive RINGBUFFER Address and size*/
-		config->elem_array.elems[0].dest =
-			(config->elem_array.elems[0].dest & ACP_DRAM_ADDRESS_MASK);
-		sw0_audio_ringbuff_addr = (config->elem_array.elems[0].dest | ACP_SRAM);
-		io_reg_write(PU_REGISTER_BASE + sw_dev[channel->index].sw_dev_ringbuff_addr,
-			     sw0_audio_ringbuff_addr);
-		io_reg_write(PU_REGISTER_BASE + sw_dev[channel->index].sw_dev_ringbuff_size,
-			     sw_audio_buff_size_capture);
-
-		/* Receive DMA transfer size in bytes */
-		io_reg_write(PU_REGISTER_BASE + sw_dev[channel->index].sw_dev_dma_size,
-			     (uint32_t)(64/*ACP_DMA_TRANS_SIZE_128*/));
-
-		/* Watermark size for  receive fifo - Half of SW buffer size*/
-		io_reg_write(PU_REGISTER_BASE + sw_dev[channel->index].sw_dev_dma_watermark,
-			     sw_audio_buff_size_capture >> 1);
-		break;
-	default:
-		tr_err(&acp_sw_audio_tr, "Config channel direction undefined %d",
-		       channel->direction);
-		return -EINVAL;
-	}
-
-	return 0;
-}
-
-static int acp_dai_sw_audio_dma_copy(struct dma_chan_data *channel, int bytes,
-				     uint32_t flags)
-{
-	struct dma_cb_data next = {
-		.channel = channel,
-		.elem.size = bytes,
-	};
-	notifier_event(channel, NOTIFIER_ID_DMA_COPY,
-		       NOTIFIER_TARGET_CORE_LOCAL, &next, sizeof(next));
-
-	return 0;
-}
-
-static int acp_dai_sw_audio_dma_probe(struct dma *dma)
-{
-	int channel;
-
-	if (dma->chan) {
-		tr_err(&acp_sw_audio_tr, "Repeated probe");
-		return -EEXIST;
-	}
-	dma->chan = rzalloc(SOF_MEM_FLAG_KERNEL,
-			    dma->plat_data.channels *
-			    sizeof(struct dma_chan_data));
-	if (!dma->chan) {
-		tr_err(&acp_sw_audio_tr, "Probe failure,unable to allocate channel descriptors");
-		return -ENOMEM;
-	}
-	for (channel = 0; channel < dma->plat_data.channels; channel++) {
-		dma->chan[channel].dma = dma;
-		dma->chan[channel].index = channel;
-		dma->chan[channel].status = COMP_STATE_INIT;
-	}
-	atomic_init(&dma->num_channels_busy, 0);
-	return 0;
-}
-
-static int acp_dai_sw_audio_dma_remove(struct dma *dma)
-{
-	if (!dma->chan) {
-		tr_err(&acp_sw_audio_tr, "remove called without probe,it's a no-op");
-		return 0;
-	}
-
-	rfree(dma->chan);
-	dma->chan = NULL;
-
-	return 0;
-}
-
-static int acp_dai_sw_audio_dma_get_data_size(struct dma_chan_data *channel,
-					      uint32_t *avail, uint32_t *free)
-{
-	if (channel->direction == DMA_DIR_MEM_TO_DEV) {
-		*free = sw_audio_buff_size_playback >> 1;
-		*avail = sw_audio_buff_size_playback >> 1;
-
-	} else if (channel->direction == DMA_DIR_DEV_TO_MEM) {
-		*free = sw_audio_buff_size_capture >> 1;
-		*avail = sw_audio_buff_size_capture >> 1;
-
-	} else {
-		tr_err(&acp_sw_audio_tr, "Channel direction not defined %d", channel->direction);
-		return -EINVAL;
-	}
-
-	return 0;
-}
-
-static int acp_dai_sw_audio_dma_get_attribute(struct dma *dma, uint32_t type, uint32_t *value)
-{
-	switch (type) {
-	case DMA_ATTR_BUFFER_ALIGNMENT:
-	case DMA_ATTR_COPY_ALIGNMENT:
-		*value = ACP_DMA_BUFFER_ALIGN_128;
-		break;
-	case DMA_ATTR_BUFFER_ADDRESS_ALIGNMENT:
-		*value = PLATFORM_DCACHE_ALIGN;
-		break;
-	case DMA_ATTR_BUFFER_PERIOD_COUNT:
-		*value = ACP_DAI_DMA_BUFFER_PERIOD_COUNT;
-		break;
-	default:
-		return -ENOENT;
-	}
-
-	return 0;
-}
-
-static int acp_dai_sw_audio_dma_interrupt(struct dma_chan_data *channel, enum dma_irq_cmd cmd)
-{
-	uint32_t status = 0;
-	acp_dsp0_intr_stat_t acp_intr_stat;
-	acp_dsp0_intr_cntl_t acp_intr_cntl;
-	acp_dsp0_intr_stat1_t acp_intr_stat1;
-	acp_dsp0_intr_cntl1_t acp_intr_cntl1;
-
-	if (channel->status == COMP_STATE_INIT)
-		return 0;
-	switch (cmd) {
-	case DMA_IRQ_STATUS_GET:
-		switch (channel->index) {
-		case SDW1_ACP_P1_SW_BT_TX_EN_CH:
-		case SDW1_ACP_P1_SW_BT_RX_EN_CH:
-		case SDW1_ACP_P1_SW_AUDIO_RX_EN_CH:
-		case SDW1_ACP_P1_SW_AUDIO_TX_EN_CH:
-		case SDW1_ACP_P1_SW_HS_RX_EN_CH:
-		case SDW1_ACP_P1_SW_HS_TX_EN_CH:
-			acp_intr_stat1 = (acp_dsp0_intr_stat1_t)dma_reg_read(channel->dma,
-			sw_dev[channel->index].sw_dev_dma_intr_status);
-			status = acp_intr_stat1.bits.audio_buffer_int_stat;
-			break;
-		default:
-			acp_intr_stat = (acp_dsp0_intr_stat_t)dma_reg_read(channel->dma,
-			sw_dev[channel->index].sw_dev_dma_intr_status);
-			status = acp_intr_stat.bits.audio_buffer_int_stat;
-			break;
-		}
-		return (status & (1 << sw_dev[channel->index].statusindex));
-	case DMA_IRQ_CLEAR:
-		switch (channel->index) {
-		case SDW1_ACP_P1_SW_BT_TX_EN_CH:
-		case SDW1_ACP_P1_SW_BT_RX_EN_CH:
-		case SDW1_ACP_P1_SW_AUDIO_RX_EN_CH:
-		case SDW1_ACP_P1_SW_AUDIO_TX_EN_CH:
-		case SDW1_ACP_P1_SW_HS_RX_EN_CH:
-		case SDW1_ACP_P1_SW_HS_TX_EN_CH:
-			acp_intr_stat1.u32all = 0;
-			acp_intr_stat1.bits.audio_buffer_int_stat =
-						(1 << sw_dev[channel->index].statusindex);
-			status = acp_intr_stat1.u32all;
-			dma_reg_write(channel->dma, sw_dev[channel->index].sw_dev_dma_intr_status,
-				      status);
-			break;
-		default:
-			acp_intr_stat.u32all = 0;
-			acp_intr_stat.bits.audio_buffer_int_stat =
-						(1 << sw_dev[channel->index].statusindex);
-			status = acp_intr_stat.u32all;
-			dma_reg_write(channel->dma, sw_dev[channel->index].sw_dev_dma_intr_status,
-				      status);
-			break;
-		}
-		return 0;
-	case DMA_IRQ_MASK:
-		switch (channel->index) {
-		case SDW1_ACP_P1_SW_BT_TX_EN_CH:
-		case SDW1_ACP_P1_SW_BT_RX_EN_CH:
-		case SDW1_ACP_P1_SW_AUDIO_RX_EN_CH:
-		case SDW1_ACP_P1_SW_AUDIO_TX_EN_CH:
-		case SDW1_ACP_P1_SW_HS_RX_EN_CH:
-		case SDW1_ACP_P1_SW_HS_TX_EN_CH:
-			acp_intr_cntl1 = (acp_dsp0_intr_cntl1_t)dma_reg_read(channel->dma,
-			sw_dev[channel->index].sw_dev_dma_intr_cntl);
-			acp_intr_cntl1.bits.audio_buffer_int_mask &=
-			(~(1 << sw_dev[channel->index].statusindex));
-			status = acp_intr_cntl1.u32all;
-			dma_reg_write(channel->dma, sw_dev[channel->index].sw_dev_dma_intr_cntl,
-				      status);
-			break;
-		default:
-			acp_intr_cntl = (acp_dsp0_intr_cntl_t)
-			io_reg_read(PU_REGISTER_BASE + sw_dev[channel->index].sw_dev_dma_intr_cntl);
-			acp_intr_cntl.bits.audio_buffer_int_mask &=
-			(~(1 << sw_dev[channel->index].statusindex));
-			status = acp_intr_cntl.u32all;
-			dma_reg_write(channel->dma, sw_dev[channel->index].sw_dev_dma_intr_cntl,
-				      status);
-			break;
-		}
-		return 0;
-	case DMA_IRQ_UNMASK:
-		switch (channel->index) {
-		case SDW1_ACP_P1_SW_BT_TX_EN_CH:
-		case SDW1_ACP_P1_SW_BT_RX_EN_CH:
-		case SDW1_ACP_P1_SW_AUDIO_RX_EN_CH:
-		case SDW1_ACP_P1_SW_AUDIO_TX_EN_CH:
-		case SDW1_ACP_P1_SW_HS_RX_EN_CH:
-		case SDW1_ACP_P1_SW_HS_TX_EN_CH:
-			acp_intr_cntl1 = (acp_dsp0_intr_cntl1_t)dma_reg_read(channel->dma,
-				sw_dev[channel->index].sw_dev_dma_intr_cntl);
-			acp_intr_cntl1.bits.audio_buffer_int_mask  |=
-			(1 << sw_dev[channel->index].statusindex);
-			status = acp_intr_cntl1.u32all;
-			dma_reg_write(channel->dma, sw_dev[channel->index].sw_dev_dma_intr_cntl,
-				      status);
-			break;
-		default:
-			acp_intr_cntl = (acp_dsp0_intr_cntl_t)dma_reg_read(channel->dma,
-			    sw_dev[channel->index].sw_dev_dma_intr_cntl);
-			acp_intr_cntl.bits.audio_buffer_int_mask |=
-				(1 << sw_dev[channel->index].statusindex);
-			status = acp_intr_cntl.u32all;
-			dma_reg_write(channel->dma, sw_dev[channel->index].sw_dev_dma_intr_cntl,
-				      status);
-			break;
-		}
-		return 0;
-	default:
-		return -EINVAL;
-	}
-}
-
-const struct dma_ops acp_dai_sw_audio_dma_ops = {
-	.channel_get		= acp_dai_sw_audio_dma_channel_get,
-	.channel_put		= acp_dai_sw_audio_dma_channel_put,
-	.start			= acp_dai_sw_audio_dma_start,
-	.stop			= acp_dai_sw_audio_dma_stop,
-	.pause			= acp_dai_sw_audio_dma_pause,
-	.release		= acp_dai_sw_audio_dma_release,
-	.copy			= acp_dai_sw_audio_dma_copy,
-	.status			= acp_dai_sw_audio_dma_status,
-	.set_config		= acp_dai_sw_audio_dma_set_config,
-	.interrupt		= acp_dai_sw_audio_dma_interrupt,
-	.probe			= acp_dai_sw_audio_dma_probe,
-	.remove			= acp_dai_sw_audio_dma_remove,
-	.get_data_size		= acp_dai_sw_audio_dma_get_data_size,
-	.get_attribute		= acp_dai_sw_audio_dma_get_attribute,
-};
-
-#endif
diff --git a/src/drivers/amd/renoir/CMakeLists.txt b/src/drivers/amd/renoir/CMakeLists.txt
deleted file mode 100644
index 3987a52c2446..000000000000
--- a/src/drivers/amd/renoir/CMakeLists.txt
+++ /dev/null
@@ -1,11 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-
-add_local_sources(sof
-	acp_dma.c
-	acp_sp_dai.c
-	interrupt.c
-	ipc.c
-	acp_bt_dma.c
-	acp_sp_dma.c
-	acp_dmic_dma.c
-)
diff --git a/src/drivers/amd/renoir/acp_bt_dma.c b/src/drivers/amd/renoir/acp_bt_dma.c
deleted file mode 100644
index bc7767f4138f..000000000000
--- a/src/drivers/amd/renoir/acp_bt_dma.c
+++ /dev/null
@@ -1,443 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-//
-//Copyright(c) 2021 AMD. All rights reserved.
-//
-//Author:	Basavaraj Hiregoudar <basavaraj.hiregoudar@amd.com>
-//		Anup Kulkarni <anup.kulkarni@amd.com>
-//		Bala Kishore <balakishore.pati@amd.com>
-
-#include <rtos/atomic.h>
-#include <sof/audio/component.h>
-#include <rtos/bit.h>
-#include <sof/drivers/acp_dai_dma.h>
-#include <rtos/interrupt.h>
-#include <rtos/timer.h>
-#include <rtos/alloc.h>
-#include <rtos/clk.h>
-#include <sof/lib/cpu.h>
-#include <sof/lib/dma.h>
-#include <sof/lib/io.h>
-#include <sof/lib/pm_runtime.h>
-#include <sof/lib/notifier.h>
-#include <sof/platform.h>
-#include <sof/schedule/schedule.h>
-#include <rtos/spinlock.h>
-#include <sof/math/numbers.h>
-#include <sof/trace/trace.h>
-#include <ipc/topology.h>
-#include <user/trace.h>
-#include <errno.h>
-#include <stdbool.h>
-#include <stddef.h>
-#include <stdint.h>
-#include <platform/fw_scratch_mem.h>
-#include <platform/chip_registers.h>
-
-SOF_DEFINE_REG_UUID(acp_bt_dma);
-
-/* unused with Zephyr, generates no output */
-DECLARE_TR_CTX(acp_bt_dma_tr, SOF_UUID(acp_bt_dma_uuid), LOG_LEVEL_INFO);
-
-/* DMA number of buffer periods */
-#define BT_FIFO_SIZE		768
-
-/* ACP DMA transfer size */
-#define ACP_BT_DMA_TRANS_SIZE	64
-#define BT_IER_DISABLE		0x0
-
-static uint64_t prev_tx_pos;
-static uint64_t prev_rx_pos;
-static uint32_t bt_buff_size;
-
-/* Allocate requested DMA channel if it is free */
-static struct dma_chan_data *acp_dai_bt_dma_channel_get(struct dma *dma,
-						   unsigned int req_chan)
-{
-	k_spinlock_key_t key;
-	struct dma_chan_data *channel;
-
-	key = k_spin_lock(&dma->lock);
-	if (req_chan >= dma->plat_data.channels) {
-		k_spin_unlock(&dma->lock, key);
-		tr_err(&acp_bt_dma_tr, "Channel %d not in range", req_chan);
-		return NULL;
-	}
-	channel = &dma->chan[req_chan];
-	if (channel->status != COMP_STATE_INIT) {
-		k_spin_unlock(&dma->lock, key);
-		tr_err(&acp_bt_dma_tr, "channel already in use %d", req_chan);
-		return NULL;
-	}
-	atomic_add(&dma->num_channels_busy, 1);
-	channel->status = COMP_STATE_READY;
-	k_spin_unlock(&dma->lock, key);
-
-	return channel;
-}
-
-/* channel must not be running when this is called */
-static void acp_dai_bt_dma_channel_put(struct dma_chan_data *channel)
-{
-	k_spinlock_key_t key;
-
-	notifier_unregister_all(NULL, channel);
-	key = k_spin_lock(&channel->dma->lock);
-	channel->status = COMP_STATE_INIT;
-	atomic_sub(&channel->dma->num_channels_busy, 1);
-	k_spin_unlock(&channel->dma->lock, key);
-}
-
-static int acp_dai_bt_dma_start(struct dma_chan_data *channel)
-{
-	acp_bttdm_ier_t         bt_ier;
-	acp_bttdm_iter_t        bt_tdm_iter;
-	acp_bttdm_irer_t        bt_tdm_irer;
-	uint32_t		acp_pdm_en;
-
-	bt_tdm_iter = (acp_bttdm_iter_t)io_reg_read((PU_REGISTER_BASE + ACP_BTTDM_ITER));
-	bt_tdm_irer = (acp_bttdm_irer_t)io_reg_read((PU_REGISTER_BASE + ACP_BTTDM_IRER));
-	acp_pdm_en = (uint32_t)io_reg_read(PU_REGISTER_BASE + ACP_WOV_PDM_ENABLE);
-
-	if (!bt_tdm_iter.bits.bttdm_txen && !bt_tdm_irer.bits.bttdm_rx_en && !acp_pdm_en) {
-		io_reg_write((PU_REGISTER_BASE + ACP_CLKMUX_SEL), ACP_ACLK_CLK_SEL);
-		/* Request SMU to set aclk to 600 Mhz */
-		acp_change_clock_notify(600000000);
-	}
-
-	if (channel->direction == DMA_DIR_MEM_TO_DEV) {
-		channel->status = COMP_STATE_ACTIVE;
-		prev_tx_pos = 0;
-		bt_ier = (acp_bttdm_ier_t)io_reg_read((PU_REGISTER_BASE + ACP_BTTDM_IER));
-		bt_ier.bits.bttdm_ien = 1;
-		io_reg_write((PU_REGISTER_BASE + ACP_BTTDM_IER), bt_ier.u32all);
-		bt_tdm_iter.u32all = 0;
-		bt_tdm_iter.bits.bttdm_txen = 1;
-		bt_tdm_iter.bits.bttdm_tx_protocol_mode  = 0;
-		bt_tdm_iter.bits.bttdm_tx_data_path_mode = 1;
-		bt_tdm_iter.bits.bttdm_tx_samp_len = 2;
-		io_reg_write((PU_REGISTER_BASE + ACP_BTTDM_ITER), bt_tdm_iter.u32all);
-	} else if (channel->direction == DMA_DIR_DEV_TO_MEM) {
-		channel->status = COMP_STATE_ACTIVE;
-		prev_rx_pos = 0;
-		bt_ier = (acp_bttdm_ier_t)io_reg_read((PU_REGISTER_BASE + ACP_BTTDM_IER));
-		bt_ier.bits.bttdm_ien = 1;
-		io_reg_write((PU_REGISTER_BASE + ACP_BTTDM_IER), bt_ier.u32all);
-		bt_tdm_irer.u32all = 0;
-		bt_tdm_irer.bits.bttdm_rx_en = 1;
-		bt_tdm_irer.bits.bttdm_rx_protocol_mode  = 0;
-		bt_tdm_irer.bits.bttdm_rx_data_path_mode = 1;
-		bt_tdm_irer.bits.bttdm_rx_samplen = 2;
-		io_reg_write((PU_REGISTER_BASE + ACP_BTTDM_IRER), bt_tdm_irer.u32all);
-	} else {
-		tr_err(&acp_bt_dma_tr, " ACP:Start direction not defined %d", channel->direction);
-		return -EINVAL;
-	}
-	return 0;
-}
-
-
-static int acp_dai_bt_dma_release(struct dma_chan_data *channel)
-{
-	/* nothing to do on renoir */
-	return 0;
-}
-
-static int acp_dai_bt_dma_pause(struct dma_chan_data *channel)
-{
-	/* nothing to do on renoir */
-	return 0;
-}
-
-static int acp_dai_bt_dma_stop(struct dma_chan_data *channel)
-{
-	acp_bttdm_iter_t        bt_tdm_iter;
-	acp_bttdm_irer_t        bt_tdm_irer;
-	uint32_t		acp_pdm_en;
-
-	switch (channel->status) {
-	case COMP_STATE_READY:
-	case COMP_STATE_PREPARE:
-		return 0;
-	case COMP_STATE_PAUSED:
-	case COMP_STATE_ACTIVE:
-		break;
-	default:
-		return -EINVAL;
-	}
-	channel->status = COMP_STATE_READY;
-	if (channel->direction == DMA_DIR_MEM_TO_DEV) {
-		bt_tdm_iter = (acp_bttdm_iter_t)io_reg_read(PU_REGISTER_BASE + ACP_BTTDM_ITER);
-		bt_tdm_iter.bits.bttdm_txen = 0;
-		io_reg_write(PU_REGISTER_BASE + ACP_BTTDM_ITER, bt_tdm_iter.u32all);
-	} else if (channel->direction == DMA_DIR_DEV_TO_MEM) {
-		bt_tdm_irer = (acp_bttdm_irer_t)io_reg_read(PU_REGISTER_BASE + ACP_BTTDM_IRER);
-		bt_tdm_irer.bits.bttdm_rx_en = 0;
-		io_reg_write(PU_REGISTER_BASE + ACP_BTTDM_IRER, bt_tdm_irer.u32all);
-	} else {
-		tr_err(&acp_bt_dma_tr, "direction not defined %d", channel->direction);
-		return -EINVAL;
-	}
-
-	bt_tdm_iter = (acp_bttdm_iter_t)io_reg_read(PU_REGISTER_BASE + ACP_BTTDM_ITER);
-	bt_tdm_irer = (acp_bttdm_irer_t)io_reg_read(PU_REGISTER_BASE + ACP_BTTDM_IRER);
-	acp_pdm_en = (uint32_t)io_reg_read(PU_REGISTER_BASE + ACP_WOV_PDM_ENABLE);
-	if (!bt_tdm_iter.bits.bttdm_txen && !bt_tdm_irer.bits.bttdm_rx_en) {
-		io_reg_write((PU_REGISTER_BASE + ACP_BTTDM_IER), BT_IER_DISABLE);
-		/* Request SMU to scale down aclk to minimum clk */
-		if (!acp_pdm_en) {
-			acp_change_clock_notify(0);
-			io_reg_write((PU_REGISTER_BASE + ACP_CLKMUX_SEL), ACP_INTERNAL_CLK_SEL);
-		}
-	}
-
-	return 0;
-}
-
-/* fill in "status" with current DMA channel state and position */
-static int acp_dai_bt_dma_status(struct dma_chan_data *channel,
-		struct dma_chan_status *status,
-		uint8_t direction)
-{
-	/* nothing to do on renoir */
-	return 0;
-}
-
-/* set the DMA channel configuration
- * source/target address
- * DMA transfer sizes
- */
-static int acp_dai_bt_dma_set_config(struct dma_chan_data *channel,
-				struct dma_sg_config *config)
-{
-	uint32_t bt_ringbuff_addr;
-	uint32_t fifo_addr;
-
-	if (!config->cyclic) {
-		tr_err(&acp_bt_dma_tr, "cyclic configurations only supported!");
-		return -EINVAL;
-	}
-	if (config->scatter) {
-		tr_err(&acp_bt_dma_tr, "scatter enabled, that is not supported for now");
-		return -EINVAL;
-	}
-
-	volatile acp_scratch_mem_config_t *pscratch_mem_cfg =
-		(volatile acp_scratch_mem_config_t *) (PU_REGISTER_BASE + SCRATCH_REG_OFFSET);
-	channel->is_scheduling_source = true;
-	channel->direction = config->direction;
-	bt_buff_size = config->elem_array.elems[0].size * config->elem_array.count;
-
-	switch (config->direction) {
-	case DMA_DIR_MEM_TO_DEV:
-
-		/* BT Transmit FIFO Address and FIFO Size */
-		fifo_addr = (uint32_t)(&pscratch_mem_cfg->acp_transmit_fifo_buffer);
-		io_reg_write((PU_REGISTER_BASE + ACP_BT_TX_FIFOADDR), fifo_addr);
-		io_reg_write((PU_REGISTER_BASE + ACP_BT_TX_FIFOSIZE), (uint32_t)(BT_FIFO_SIZE));
-
-		/* Transmit RINGBUFFER Address and size */
-		bt_ringbuff_addr = config->elem_array.elems[0].src & ACP_DRAM_ADDRESS_MASK;
-		io_reg_write((PU_REGISTER_BASE + ACP_BT_TX_RINGBUFADDR), bt_ringbuff_addr);
-		io_reg_write((PU_REGISTER_BASE + ACP_BT_TX_RINGBUFSIZE), bt_buff_size);
-
-		/* Transmit DMA transfer size in bytes */
-		io_reg_write((PU_REGISTER_BASE + ACP_BT_TX_DMA_SIZE),
-			     (uint32_t)(ACP_BT_DMA_TRANS_SIZE));
-
-		/* Watermark size for BT transfer fifo */
-		io_reg_write((PU_REGISTER_BASE + ACP_BT_TX_INTR_WATERMARK_SIZE),
-			     (bt_buff_size >> 1));
-		break;
-	case DMA_DIR_DEV_TO_MEM:
-
-		/* BT Receive FIFO Address and FIFO Size*/
-		fifo_addr = (uint32_t)(&pscratch_mem_cfg->acp_receive_fifo_buffer);
-		io_reg_write((PU_REGISTER_BASE + ACP_BT_RX_FIFOADDR), fifo_addr);
-		io_reg_write((PU_REGISTER_BASE + ACP_BT_RX_FIFOSIZE), (uint32_t)(BT_FIFO_SIZE));
-
-		/* Receive RINGBUFFER Address and size */
-		bt_ringbuff_addr = config->elem_array.elems[0].dest & ACP_DRAM_ADDRESS_MASK;
-		io_reg_write((PU_REGISTER_BASE + ACP_BT_RX_RINGBUFADDR), bt_ringbuff_addr);
-		io_reg_write((PU_REGISTER_BASE + ACP_BT_RX_RINGBUFSIZE), bt_buff_size);
-
-		/* Receive DMA transfer size in bytes */
-		io_reg_write((PU_REGISTER_BASE + ACP_BT_RX_DMA_SIZE),
-			     (uint32_t)(ACP_BT_DMA_TRANS_SIZE));
-		/* Watermark size for BT receive fifo */
-		io_reg_write((PU_REGISTER_BASE + ACP_BT_RX_INTR_WATERMARK_SIZE),
-			     (bt_buff_size >> 1));
-		break;
-	default:
-		tr_err(&acp_bt_dma_tr, "unsupported config direction");
-		return -EINVAL;
-	}
-
-	return 0;
-}
-
-static int acp_dai_bt_dma_copy(struct dma_chan_data *channel, int bytes,
-			  uint32_t flags)
-{
-	struct dma_cb_data next = {
-		.channel = channel,
-		.elem.size = bytes,
-	};
-	notifier_event(channel, NOTIFIER_ID_DMA_COPY,
-			NOTIFIER_TARGET_CORE_LOCAL, &next, sizeof(next));
-	return 0;
-}
-
-static int acp_dai_bt_dma_probe(struct dma *dma)
-{
-	int channel;
-
-	if (dma->chan) {
-		tr_err(&acp_bt_dma_tr, "Repeated probe");
-		return -EEXIST;
-	}
-	dma->chan = rzalloc(SOF_MEM_FLAG_KERNEL,
-			    dma->plat_data.channels *
-			    sizeof(struct dma_chan_data));
-	if (!dma->chan) {
-		tr_err(&acp_bt_dma_tr, "Probe failure, unable to allocate channel descriptors");
-		return -ENOMEM;
-	}
-	for (channel = 0; channel < dma->plat_data.channels; channel++) {
-		dma->chan[channel].dma = dma;
-		dma->chan[channel].index = channel;
-		dma->chan[channel].status = COMP_STATE_INIT;
-	}
-	atomic_init(&dma->num_channels_busy, 0);
-	return 0;
-}
-
-static int acp_dai_bt_dma_remove(struct dma *dma)
-{
-	if (!dma->chan) {
-		tr_err(&acp_bt_dma_tr, "remove call without probe, it's a no-op");
-		return 0;
-	}
-	rfree(dma->chan);
-	dma->chan = NULL;
-	return 0;
-}
-
-static int acp_dai_bt_dma_get_data_size(struct dma_chan_data *channel,
-					uint32_t *avail, uint32_t *free)
-{
-	if (channel->direction == DMA_DIR_MEM_TO_DEV) {
-#if CONFIG_DISABLE_DESCRIPTOR_SPLIT
-		uint64_t tx_low, curr_tx_pos, tx_high;
-		tx_low = (uint32_t)io_reg_read(PU_REGISTER_BASE +
-				ACP_BT_TX_LINEARPOSITIONCNTR_LOW);
-		tx_high = (uint32_t)io_reg_read(PU_REGISTER_BASE +
-				ACP_BT_TX_LINEARPOSITIONCNTR_HIGH);
-		curr_tx_pos = (uint64_t)((tx_high << 32) | tx_low);
-		*free = (curr_tx_pos - prev_tx_pos) > bt_buff_size ?
-			(curr_tx_pos - prev_tx_pos) % bt_buff_size :
-			(curr_tx_pos - prev_tx_pos);
-		*avail = bt_buff_size - *free;
-		prev_tx_pos = curr_tx_pos;
-#else
-		*free = bt_buff_size >> 1;
-		*avail = bt_buff_size >> 1;
-#endif
-	} else if (channel->direction == DMA_DIR_DEV_TO_MEM) {
-#if CONFIG_DISABLE_DESCRIPTOR_SPLIT
-		uint64_t rx_low, curr_rx_pos, rx_high;
-		rx_low = (uint32_t)io_reg_read(PU_REGISTER_BASE +
-				ACP_BT_RX_LINEARPOSITIONCNTR_LOW);
-		rx_high = (uint32_t)io_reg_read(PU_REGISTER_BASE +
-				ACP_BT_RX_LINEARPOSITIONCNTR_HIGH);
-		curr_rx_pos = (uint64_t)((rx_high << 32) | rx_low);
-		*free = (curr_rx_pos - prev_rx_pos) > bt_buff_size ?
-			(curr_rx_pos - prev_rx_pos) % bt_buff_size :
-			(curr_rx_pos - prev_rx_pos);
-		*avail = bt_buff_size - *free;
-		prev_rx_pos = curr_rx_pos;
-#else
-		*free = bt_buff_size >> 1;
-		*avail = bt_buff_size >> 1;
-#endif
-	} else {
-		tr_err(&acp_bt_dma_tr, "Channel direction Not defined %d",
-		       channel->direction);
-		return -EINVAL;
-	}
-	return 0;
-}
-
-static int acp_dai_bt_dma_get_attribute(struct dma *dma, uint32_t type, uint32_t *value)
-{
-	switch (type) {
-	case DMA_ATTR_BUFFER_ALIGNMENT:
-	case DMA_ATTR_COPY_ALIGNMENT:
-		*value = ACP_DMA_BUFFER_ALIGN;
-		break;
-	case DMA_ATTR_BUFFER_ADDRESS_ALIGNMENT:
-		*value = PLATFORM_DCACHE_ALIGN;
-		break;
-	case DMA_ATTR_BUFFER_PERIOD_COUNT:
-		*value = ACP_DAI_DMA_BUFFER_PERIOD_COUNT;
-		break;
-	default:
-		return -ENOENT; /* Attribute not found */
-	}
-	return 0;
-}
-
-static int acp_dai_bt_dma_interrupt(struct dma_chan_data *channel, enum dma_irq_cmd cmd)
-{
-	uint32_t status;
-	acp_dsp0_intr_stat_t acp_intr_stat;
-	acp_dsp0_intr_cntl_t acp_intr_cntl;
-
-	if (channel->status == COMP_STATE_INIT)
-		return 0;
-	switch (cmd) {
-	case DMA_IRQ_STATUS_GET:
-		acp_intr_stat =  (acp_dsp0_intr_stat_t)
-			(dma_reg_read(channel->dma, ACP_DSP0_INTR_STAT));
-		status = acp_intr_stat.bits.audio_buffer_int_stat;
-		return (status & (1<<channel->index));
-	case DMA_IRQ_CLEAR:
-		acp_intr_stat.u32all = 0;
-		acp_intr_stat.bits.audio_buffer_int_stat = (1 << channel->index);
-		status  = acp_intr_stat.u32all;
-		dma_reg_write(channel->dma, ACP_DSP0_INTR_STAT, status);
-		return 0;
-	case DMA_IRQ_MASK:
-		acp_intr_cntl =  (acp_dsp0_intr_cntl_t)
-				dma_reg_read(channel->dma, ACP_DSP0_INTR_CNTL);
-		acp_intr_cntl.bits.audio_buffer_int_mask &= (~(1 << channel->index));
-		status  = acp_intr_cntl.u32all;
-		dma_reg_write(channel->dma, ACP_DSP0_INTR_CNTL, status);
-		return 0;
-	case DMA_IRQ_UNMASK:
-		acp_intr_cntl =  (acp_dsp0_intr_cntl_t)
-				dma_reg_read(channel->dma, ACP_DSP0_INTR_CNTL);
-		acp_intr_cntl.bits.audio_buffer_int_mask  |=  (1 << channel->index);
-		status = acp_intr_cntl.u32all;
-		dma_reg_write(channel->dma, ACP_DSP0_INTR_CNTL, status);
-		return 0;
-	default:
-		return -EINVAL;
-	}
-}
-
-const struct dma_ops acp_dai_bt_dma_ops = {
-	.channel_get		= acp_dai_bt_dma_channel_get,
-	.channel_put		= acp_dai_bt_dma_channel_put,
-	.start			= acp_dai_bt_dma_start,
-	.stop			= acp_dai_bt_dma_stop,
-	.pause			= acp_dai_bt_dma_pause,
-	.release		= acp_dai_bt_dma_release,
-	.copy			= acp_dai_bt_dma_copy,
-	.status			= acp_dai_bt_dma_status,
-	.set_config		= acp_dai_bt_dma_set_config,
-	.interrupt		= acp_dai_bt_dma_interrupt,
-	.probe			= acp_dai_bt_dma_probe,
-	.remove			= acp_dai_bt_dma_remove,
-	.get_data_size		= acp_dai_bt_dma_get_data_size,
-	.get_attribute		= acp_dai_bt_dma_get_attribute,
-};
diff --git a/src/drivers/amd/renoir/acp_dma.c b/src/drivers/amd/renoir/acp_dma.c
deleted file mode 100644
index 84dda2baf2aa..000000000000
--- a/src/drivers/amd/renoir/acp_dma.c
+++ /dev/null
@@ -1,249 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-//
-//Copyright(c) 2021 AMD. All rights reserved.
-//
-//Author:       Basavaraj Hiregoudar <basavaraj.hiregoudar@amd.com>
-//              Anup Kulkarni <anup.kulkarni@amd.com>
-//              Bala Kishore <balakishore.pati@amd.com>
-
-#include <sof/audio/component.h>
-#include <platform/chip_registers.h>
-#include <platform/fw_scratch_mem.h>
-#include <platform/chip_offset_byte.h>
-#include <sof/drivers/acp_dai_dma.h>
-#include <rtos/timer.h>
-#include <rtos/alloc.h>
-#include <sof/lib/dma.h>
-#include <sof/lib/io.h>
-#include <sof/lib/notifier.h>
-#include <sof/lib/uuid.h>
-#include <sof/math/numbers.h>
-#include <sof/platform.h>
-#include <errno.h>
-#include <stddef.h>
-#include <stdint.h>
-#include <platform/acp_dma.h>
-
-void amd_dma_reconfig(struct dma_chan_data *channel, uint32_t bytes)
-{
-	uint32_t strt_idx = 0;
-	uint32_t src;
-	uint32_t dest;
-	uint32_t tail, head;
-
-	acp_cfg_dma_descriptor_t psrc_dscr[ACP_MAX_STREAMS];
-	acp_cfg_dma_descriptor_t *pdest_dscr;
-	acp_dma_cntl_0_t dma_cntl;
-	struct acp_dma_chan_data *acp_dma_chan;
-	struct acp_dma_config *dma_cfg;
-
-	volatile acp_scratch_mem_config_t *pscratch_mem_cfg =
-		(volatile acp_scratch_mem_config_t *)(PU_REGISTER_BASE + SCRATCH_REG_OFFSET);
-	acp_dma_chan = dma_chan_get_data(channel);
-	dma_cfg = &acp_dma_chan->config[channel->index];
-	pdest_dscr = (acp_cfg_dma_descriptor_t *)(pscratch_mem_cfg->acp_cfg_dma_descriptor);
-	if (channel->direction == DMA_DIR_HMEM_TO_LMEM) {
-		head = bytes;
-		/* Update the read and write pointers */
-		dma_cfg->rd_ptr =  ACP_SYST_MEM_WINDOW + dma_cfg->phy_off + dma_cfg->rd_size;
-		dma_cfg->wr_ptr = dma_cfg->base + dma_cfg->wr_size;
-		src = dma_cfg->rd_ptr;
-		dest = dma_cfg->wr_ptr;
-		psrc_dscr[strt_idx].src_addr  = src;
-		psrc_dscr[strt_idx].dest_addr = dest;
-		psrc_dscr[strt_idx].trns_cnt.bits.trns_cnt = bytes;
-		/* Configure a single descrption */
-		dma_config_descriptor(strt_idx, 1, psrc_dscr, pdest_dscr);
-		dma_chan_reg_write(channel, ACP_DMA_DSCR_CNT_0, 1);
-		/* Check for wrap-around case for system  buffer */
-		if (dma_cfg->rd_size + bytes > dma_cfg->sys_buff_size) {
-			/* Configure the descriptor  for head and tail */
-			/* values for the wrap around case */
-			tail = dma_cfg->sys_buff_size - dma_cfg->rd_size;
-			head = bytes - tail;
-			psrc_dscr[strt_idx].trns_cnt.bits.trns_cnt = tail;
-			psrc_dscr[strt_idx+1].src_addr = ACP_SYST_MEM_WINDOW + dma_cfg->phy_off;
-			psrc_dscr[strt_idx+1].dest_addr = dest+tail;
-			psrc_dscr[strt_idx+1].trns_cnt.bits.trns_cnt = head;
-			dma_config_descriptor(strt_idx, 2, psrc_dscr, pdest_dscr);
-			dma_chan_reg_write(channel, ACP_DMA_DSCR_CNT_0, 2);
-			dma_cfg->rd_size = 0;
-		}
-		/* Check for wrap-around case for host buffer */
-		if (dma_cfg->wr_size + bytes > dma_cfg->size) {
-			tail = dma_cfg->size - dma_cfg->wr_size;
-			head = bytes - tail;
-
-			psrc_dscr[strt_idx].trns_cnt.bits.trns_cnt = tail;
-			psrc_dscr[strt_idx + 1].trns_cnt.bits.trns_cnt = head;
-
-			/* start from "0" like starting address of buffer */
-			psrc_dscr[strt_idx + 1].dest_addr = dma_cfg->base;
-
-			psrc_dscr[strt_idx + 1].src_addr  = src + tail;
-
-			dma_config_descriptor(strt_idx, 2, psrc_dscr, pdest_dscr);
-			dma_chan_reg_write(channel, ACP_DMA_DSCR_CNT_0, 2);
-			dma_cfg->wr_size = 0;
-		}
-
-		dma_cfg->rd_size += head;
-		dma_cfg->rd_size %= dma_cfg->sys_buff_size;
-		dma_cfg->wr_size += bytes;
-		dma_cfg->wr_size %= dma_cfg->size;
-	} else if (channel->direction == DMA_DIR_LMEM_TO_HMEM)	{
-		head = bytes;
-		dma_cfg->wr_ptr = ACP_SYST_MEM_WINDOW + dma_cfg->phy_off + dma_cfg->wr_size;
-		dma_cfg->rd_ptr =  dma_cfg->base + dma_cfg->rd_size;
-		src = dma_cfg->rd_ptr;
-		dest = dma_cfg->wr_ptr;
-		psrc_dscr[strt_idx].src_addr  = src;
-		psrc_dscr[strt_idx].dest_addr = dest;
-		psrc_dscr[strt_idx].trns_cnt.bits.trns_cnt = bytes;
-		/* Configure a single descrption */
-		dma_config_descriptor(strt_idx, 1, psrc_dscr, pdest_dscr);
-		dma_chan_reg_write(channel, ACP_DMA_DSCR_CNT_0, 1);
-		/* Check for wrap-around case for system  buffer */
-		if (dma_cfg->wr_size + bytes > dma_cfg->sys_buff_size) {
-			/* Configure the descriptor  for head and
-			 * tail values for the wrap around case
-			 */
-			tail = dma_cfg->sys_buff_size - dma_cfg->wr_size;
-			head = bytes - tail;
-			psrc_dscr[strt_idx].trns_cnt.bits.trns_cnt = tail;
-			psrc_dscr[strt_idx+1].src_addr = src + tail;
-			psrc_dscr[strt_idx+1].dest_addr = ACP_SYST_MEM_WINDOW + dma_cfg->phy_off;
-			psrc_dscr[strt_idx+1].trns_cnt.bits.trns_cnt = head;
-			dma_config_descriptor(strt_idx, 2, psrc_dscr, pdest_dscr);
-			dma_chan_reg_write(channel, ACP_DMA_DSCR_CNT_0, 2);
-			dma_cfg->wr_size  = 0;
-		}
-		dma_cfg->wr_size  += head;
-		dma_cfg->wr_size  %= dma_cfg->sys_buff_size;
-		dma_cfg->rd_size  += bytes;
-		dma_cfg->rd_size  %= dma_cfg->size;
-	}
-	/* clear the dma channel control bits */
-	dma_cntl = (acp_dma_cntl_0_t) dma_chan_reg_read(channel, ACP_DMA_CNTL_0);
-	dma_cntl.bits.dmachrun = 0;
-	dma_chan_reg_write(channel, ACP_DMA_CNTL_0, dma_cntl.u32all);
-	/* Load start index of decriptor and priority */
-	dma_chan_reg_write(channel, ACP_DMA_DSCR_STRT_IDX_0, strt_idx);
-	dma_chan_reg_write(channel, ACP_DMA_PRIO_0, 1);
-	channel->status = COMP_STATE_PREPARE;
-}
-
-/* Some set_config helper functions */
-int dma_setup(struct dma_chan_data *channel,
-	      struct dma_sg_elem_array *sgelems, uint32_t dir)
-{
-	uint32_t dscr_cnt, dscr = 0;
-	uint32_t tc;
-	uint16_t dscr_strt_idx = 0;
-	uint32_t *phy_off;
-	uint32_t *syst_buff_size;
-	acp_dma_cntl_0_t    dma_cntl;
-	struct acp_dma_config *dma_cfg;
-	struct acp_dma_chan_data *acp_dma_chan = dma_chan_get_data(channel);
-
-	volatile acp_scratch_mem_config_t *pscratch_mem_cfg =
-		(volatile acp_scratch_mem_config_t *)(PU_REGISTER_BASE + SCRATCH_REG_OFFSET);
-	dscr_cnt = sgelems->count;
-	/* Trace uses descriptor from index seven */
-	/* and other streams use descriptors from zero */
-	if (channel->index == DMA_TRACE_CHANNEL)
-		dscr_strt_idx = DMA_TRACE_CHANNEL;
-	else
-		dscr_strt_idx = 0;
-	/* ACP DMA Descriptor in scratch memory */
-	acp_cfg_dma_descriptor_t *dma_config_dscr;
-
-	dma_config_dscr  = (acp_cfg_dma_descriptor_t *)(pscratch_mem_cfg->acp_cfg_dma_descriptor);
-	/* physical offset of system memory */
-	phy_off = (uint32_t *)(pscratch_mem_cfg->phy_offset);
-	/* size of system memory buffer */
-	syst_buff_size = (uint32_t *)(pscratch_mem_cfg->syst_buff_size);
-
-	for (dscr = 0; dscr < dscr_cnt; dscr++) {
-		if (dir == DMA_DIR_HMEM_TO_LMEM) {
-			dma_config_dscr[dscr_strt_idx + dscr].src_addr =
-				sgelems->elems[dscr].src + ACP_SYST_MEM_WINDOW;
-			dma_config_dscr[dscr_strt_idx + dscr].dest_addr =
-				sgelems->elems[dscr].dest & ACP_DRAM_ADDRESS_MASK;
-		} else {
-			dma_config_dscr[dscr_strt_idx + dscr].dest_addr =
-				sgelems->elems[dscr].dest + ACP_SYST_MEM_WINDOW;
-			dma_config_dscr[dscr_strt_idx + dscr].src_addr =
-				sgelems->elems[dscr].src & ACP_DRAM_ADDRESS_MASK;
-		}
-		dma_config_dscr[dscr_strt_idx + dscr].trns_cnt.u32all = 0;
-		dma_config_dscr[dscr_strt_idx + dscr].trns_cnt.bits.trns_cnt =
-						sgelems->elems[dscr].size;
-	}
-	dma_config_dscr[dscr_strt_idx + (dscr-1)].trns_cnt.bits.ioc = 0;
-	dma_cfg = &acp_dma_chan->config[channel->index];
-	/* bytes of data to be transferred for the dma */
-	tc = dma_config_dscr[dscr_strt_idx].trns_cnt.bits.trns_cnt;
-	/* DMA configuration for stream */
-	if (channel->index != DMA_TRACE_CHANNEL) {
-		if (!dma_cfg->size) {
-			acp_dma_chan->dir = dir;
-			acp_dma_chan->idx = channel->index;
-			dma_cfg->phy_off =  phy_off[channel->index];
-			dma_cfg->size =  tc * dscr_cnt;
-			dma_cfg->sys_buff_size = syst_buff_size[channel->index];
-
-			if (dir == DMA_DIR_HMEM_TO_LMEM) {
-				/* Playback */
-				dma_cfg->base  = dma_config_dscr[dscr_strt_idx].dest_addr;
-				dma_cfg->wr_size = 0;
-				dma_cfg->rd_size = dma_cfg->size;
-			} else {
-				/* Capture */
-				dma_cfg->base = dma_config_dscr[dscr_strt_idx].src_addr;
-				dma_cfg->rd_size = 0;
-				if (channel->index == dma_cfg->probe_channel)
-					dma_cfg->wr_size = 0;
-				else
-					dma_cfg->wr_size = dma_cfg->size;
-			}
-		}
-	}
-	/* clear the dma channel control bits */
-	dma_cntl = (acp_dma_cntl_0_t) dma_chan_reg_read(channel, ACP_DMA_CNTL_0);
-	dma_cntl.bits.dmachrun = 0;
-	dma_cntl.bits.dmachiocen = 0;
-	dma_chan_reg_write(channel, ACP_DMA_CNTL_0, dma_cntl.u32all);
-
-	/* Program DMAChDscrStrIdx to the index
-	 * number of the first descriptor to be processed.
-	 */
-	dma_chan_reg_write(channel, ACP_DMA_DSCR_STRT_IDX_0, dscr_strt_idx);
-	/* program DMAChDscrdscrcnt to the
-	 * number of descriptors to be processed in the transfer
-	 */
-	dma_chan_reg_write(channel, ACP_DMA_DSCR_CNT_0, dscr_cnt);
-	/* set DMAChPrioLvl according to the priority */
-	dma_chan_reg_write(channel, ACP_DMA_PRIO_0, 1);
-	channel->status = COMP_STATE_PREPARE;
-	return 0;
-}
-
-int acp_dma_get_attribute(struct dma *dma, uint32_t type, uint32_t *value)
-{
-	switch (type) {
-	case DMA_ATTR_BUFFER_ALIGNMENT:
-	case DMA_ATTR_COPY_ALIGNMENT:
-		*value = ACP_DMA_BUFFER_ALIGN;
-		break;
-	case DMA_ATTR_BUFFER_ADDRESS_ALIGNMENT:
-		*value = PLATFORM_DCACHE_ALIGN;
-		break;
-	case DMA_ATTR_BUFFER_PERIOD_COUNT:
-		*value = ACP_DMA_BUFFER_PERIOD_COUNT;
-		break;
-	default:
-		return -ENOENT; /* Attribute not found */
-	}
-	return 0;
-}
diff --git a/src/drivers/amd/renoir/acp_dmic_dma.c b/src/drivers/amd/renoir/acp_dmic_dma.c
deleted file mode 100644
index 86b43aaa1825..000000000000
--- a/src/drivers/amd/renoir/acp_dmic_dma.c
+++ /dev/null
@@ -1,230 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-//
-//Copyright(c) 2021 AMD. All rights reserved.
-//
-//Author:	Basavaraj Hiregoudar <basavaraj.hiregoudar@amd.com>
-//		Anup Kulkarni <anup.kulkarni@amd.com>
-
-#include <rtos/atomic.h>
-#include <sof/audio/component.h>
-#include <rtos/bit.h>
-#include <sof/drivers/acp_dai_dma.h>
-#include <rtos/interrupt.h>
-#include <rtos/timer.h>
-#include <rtos/alloc.h>
-#include <rtos/clk.h>
-#include <sof/lib/cpu.h>
-#include <sof/lib/dma.h>
-#include <sof/lib/io.h>
-#include <sof/lib/pm_runtime.h>
-#include <sof/lib/notifier.h>
-#include <sof/platform.h>
-#include <sof/schedule/schedule.h>
-#include <rtos/spinlock.h>
-#include <sof/math/numbers.h>
-#include <sof/trace/trace.h>
-#include <ipc/topology.h>
-#include <user/trace.h>
-#include <errno.h>
-#include <stdbool.h>
-#include <stddef.h>
-#include <stdint.h>
-#include <platform/fw_scratch_mem.h>
-#include <platform/chip_registers.h>
-#include <platform/acp_dmic_dma.h>
-
-SOF_DEFINE_REG_UUID(acp_dmic_dma);
-/* unused with Zephyr, generates no output */
-DECLARE_TR_CTX(acp_dmic_dma_rn_tr, SOF_UUID(acp_dmic_dma_uuid), LOG_LEVEL_INFO);
-
-uint32_t dmic_rngbuff_size;
-extern struct acp_dmic_silence acp_initsilence;
-
-int acp_dmic_dma_start(struct dma_chan_data *channel)
-{
-	acp_wov_pdm_decimation_factor_t deci_fctr;
-	acp_wov_misc_ctrl_t wov_misc_ctrl;
-	acp_wov_pdm_dma_enable_t  pdm_dma_enable;
-	acp_i2stdm_iter_t	sp_iter;
-	acp_i2stdm_irer_t	sp_irer;
-	uint32_t		acp_pdm_en;
-	struct timer *timer = timer_get();
-	uint64_t deadline = platform_timer_get(timer) +
-				clock_ms_to_ticks(PLATFORM_DEFAULT_CLOCK, 1) * 500 / 1000;
-
-	sp_iter = (acp_i2stdm_iter_t)io_reg_read((PU_REGISTER_BASE + ACP_I2STDM_ITER));
-	sp_irer = (acp_i2stdm_irer_t)io_reg_read((PU_REGISTER_BASE + ACP_I2STDM_IRER));
-	acp_pdm_en = (uint32_t)io_reg_read(PU_REGISTER_BASE + ACP_WOV_PDM_ENABLE);
-	acp_initsilence.silence_incr = 0;
-	acp_initsilence.coeff = 0;
-
-	if (!sp_iter.bits.i2stdm_txen && !sp_irer.bits.i2stdm_rx_en && !acp_pdm_en) {
-		io_reg_write((PU_REGISTER_BASE + ACP_CLKMUX_SEL), ACP_ACLK_CLK_SEL);
-		/* Request SMU to set aclk to 600 Mhz */
-		acp_change_clock_notify(600000000);
-	}
-
-	channel->status = COMP_STATE_ACTIVE;
-	if (channel->direction == DMA_DIR_DEV_TO_MEM) {
-		/* Channel for DMIC */
-		/* Decimation Factor */
-		deci_fctr.u32all = 2;
-		io_reg_write(PU_REGISTER_BASE + ACP_WOV_PDM_DECIMATION_FACTOR,
-							deci_fctr.u32all);
-		/* PDM Control */
-		wov_misc_ctrl = (acp_wov_misc_ctrl_t)
-			io_reg_read(PU_REGISTER_BASE + ACP_WOV_MISC_CTRL);
-		wov_misc_ctrl.u32all |= 0x10;
-		io_reg_write(PU_REGISTER_BASE + ACP_WOV_MISC_CTRL,
-						wov_misc_ctrl.u32all);
-		/* PDM Enable */
-		io_reg_write(PU_REGISTER_BASE + ACP_WOV_PDM_ENABLE, 1);
-		/* PDM DMA Enable */
-		io_reg_write(PU_REGISTER_BASE + ACP_WOV_PDM_DMA_ENABLE, 1);
-		/* Check the PDM DMA Enable status bit */
-		pdm_dma_enable = (acp_wov_pdm_dma_enable_t)
-			io_reg_read(PU_REGISTER_BASE + ACP_WOV_PDM_DMA_ENABLE);
-		while (!(uint32_t)pdm_dma_enable.bits.pdm_dma_en_status) {
-			if (deadline < platform_timer_get(timer)) {
-				/* safe check in case we've got preempted after read */
-				if ((uint32_t)pdm_dma_enable.bits.pdm_dma_en_status)
-					return 0;
-				tr_err(&acp_dmic_dma_rn_tr, "DMICDMA: timed out for dma start");
-				return -ETIME;
-			}
-			pdm_dma_enable = (acp_wov_pdm_dma_enable_t)
-					io_reg_read(PU_REGISTER_BASE + ACP_WOV_PDM_DMA_ENABLE);
-		}
-	}
-	return 0;
-}
-
-int acp_dmic_dma_stop(struct dma_chan_data *channel)
-{
-	acp_wov_pdm_dma_enable_t  pdm_dma_enable;
-	acp_i2stdm_iter_t	sp_iter;
-	acp_i2stdm_irer_t	sp_irer;
-	uint32_t		acp_pdm_en;
-	struct timer *timer = timer_get();
-	uint64_t deadline = platform_timer_get(timer) +
-			clock_ms_to_ticks(PLATFORM_DEFAULT_CLOCK, 1) * 500 / 1000;
-	switch (channel->status) {
-	case COMP_STATE_READY:
-	case COMP_STATE_PREPARE:
-		return 0;
-	case COMP_STATE_PAUSED:
-	case COMP_STATE_ACTIVE:
-		break;
-	default:
-		return -EINVAL;
-	}
-	channel->status = COMP_STATE_READY;
-	/* Disable PDM DMA */
-	io_reg_write(PU_REGISTER_BASE + ACP_WOV_PDM_DMA_ENABLE, 0);
-	/* Disable PDM */
-	pdm_dma_enable = (acp_wov_pdm_dma_enable_t)
-		io_reg_read(PU_REGISTER_BASE + ACP_WOV_PDM_DMA_ENABLE);
-	/* Check PDM DMA Status */
-	while ((uint32_t)pdm_dma_enable.bits.pdm_dma_en_status) {
-		if (deadline < platform_timer_get(timer)) {
-			/* safe check in case we've got preempted after read */
-			if ((uint32_t)pdm_dma_enable.bits.pdm_dma_en_status)
-				return 0;
-			tr_err(&acp_dmic_dma_rn_tr, "DMIC-DMA: timed out for dma stop");
-			return -ETIME;
-		}
-		pdm_dma_enable = (acp_wov_pdm_dma_enable_t)
-			io_reg_read(PU_REGISTER_BASE + ACP_WOV_PDM_DMA_ENABLE);
-	}
-	/* Disable  PDM */
-	io_reg_write(PU_REGISTER_BASE + ACP_WOV_PDM_ENABLE, 0);
-	/* Clear PDM FIFO */
-	io_reg_write(PU_REGISTER_BASE + ACP_WOV_PDM_FIFO_FLUSH, 1);
-	sp_iter = (acp_i2stdm_iter_t)io_reg_read((PU_REGISTER_BASE + ACP_I2STDM_ITER));
-	sp_irer = (acp_i2stdm_irer_t)io_reg_read((PU_REGISTER_BASE + ACP_I2STDM_IRER));
-	acp_pdm_en = (uint32_t)io_reg_read(PU_REGISTER_BASE + ACP_WOV_PDM_ENABLE);
-
-	if (!sp_iter.bits.i2stdm_txen && !sp_irer.bits.i2stdm_rx_en && !acp_pdm_en) {
-		/* Request SMU to set aclk to minimum aclk */
-		acp_change_clock_notify(0);
-		io_reg_write((PU_REGISTER_BASE + ACP_CLKMUX_SEL), ACP_INTERNAL_CLK_SEL);
-	}
-
-	return 0;
-}
-
-/* set the DMA channel configuration, source/target address, buffer sizes */
-int acp_dmic_dma_set_config(struct dma_chan_data *channel,
-			    struct dma_sg_config *config)
-{
-	uint32_t ring_buff_addr;
-	uint32_t timeperiod_ms;
-	acp_wov_rx_ringbufaddr_t dmic_ringbuff_addr;
-	acp_wov_rx_ringbufsize_t dmic_ringbuff_size;
-	acp_wov_rx_intr_watermark_size_t watermark;
-
-	channel->is_scheduling_source = true;
-	channel->direction = config->direction;
-	switch (config->direction) {
-	case DMA_DIR_DEV_TO_MEM:
-	case DMA_DIR_MEM_TO_DEV:
-		acp_initsilence.dmic_rngbuff_addr1 = (char *)config->elem_array.elems[0].dest;
-		ring_buff_addr = config->elem_array.elems[0].dest &
-						ACP_DRAM_ADDRESS_MASK;
-		/* Load Ring buffer address */
-		dmic_ringbuff_addr.bits.rx_ringbufaddr = ring_buff_addr;
-		io_reg_write(PU_REGISTER_BASE +
-			ACP_WOV_RX_RINGBUFADDR, dmic_ringbuff_addr.u32all);
-		/* Load Ring buffer Size */
-		dmic_rngbuff_size = (config->elem_array.elems[0].size*
-					config->elem_array.count);
-
-		dmic_ringbuff_size.bits.rx_ringbufsize = dmic_rngbuff_size;
-		io_reg_write(PU_REGISTER_BASE +
-			ACP_WOV_RX_RINGBUFSIZE, dmic_ringbuff_size.u32all);
-		/* Write the ring buffer size to register */
-		watermark.bits.rx_intr_watermark_size = (dmic_rngbuff_size >> 1);
-		io_reg_write(PU_REGISTER_BASE +
-			ACP_WOV_RX_INTR_WATERMARK_SIZE, watermark.u32all);
-		timeperiod_ms = dmic_rngbuff_size / (acp_initsilence.num_chs *
-			acp_initsilence.samplerate_khz * acp_initsilence.bytes_per_sample *
-			config->elem_array.count);
-		acp_initsilence.silence_cnt = DMIC_SETTLING_TIME_MS / timeperiod_ms;
-		acp_initsilence.numfilterbuffers = DMIC_SMOOTH_TIME_MS / timeperiod_ms;
-		break;
-	default:
-		tr_err(&acp_dmic_dma_rn_tr,
-		       "dmic dma_set_config() unsupported config direction");
-		return -EINVAL;
-	}
-	if (!config->cyclic) {
-		tr_err(&acp_dmic_dma_rn_tr,
-		       "DMIC DMA: cyclic configurations only supported!");
-		return -EINVAL;
-	}
-	if (config->scatter) {
-		tr_err(&acp_dmic_dma_rn_tr,
-		       "DMIC DMA: scatter enabled, not supported for now!");
-		return -EINVAL;
-	}
-	return 0;
-}
-
-int acp_dmic_dma_get_attribute(struct dma *dma, uint32_t type, uint32_t *value)
-{
-	switch (type) {
-	case DMA_ATTR_BUFFER_ALIGNMENT:
-	case DMA_ATTR_COPY_ALIGNMENT:
-		*value = ACP_DMA_BUFFER_ALIGN;
-		break;
-	case DMA_ATTR_BUFFER_ADDRESS_ALIGNMENT:
-		*value = PLATFORM_DCACHE_ALIGN;
-		break;
-	case DMA_ATTR_BUFFER_PERIOD_COUNT:
-		*value = ACP_DAI_DMA_BUFFER_PERIOD_COUNT;
-		break;
-	default:
-		return -ENOENT; /* Attribute not found */
-	}
-	return 0;
-}
diff --git a/src/drivers/amd/renoir/acp_sp_dai.c b/src/drivers/amd/renoir/acp_sp_dai.c
deleted file mode 100644
index 10c1b27f621c..000000000000
--- a/src/drivers/amd/renoir/acp_sp_dai.c
+++ /dev/null
@@ -1,165 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-//
-//Copyright(c) 2021 AMD. All rights reserved.
-//
-//Author:       Basavaraj Hiregoudar <basavaraj.hiregoudar@amd.com>
-//              Anup Kulkarni <anup.kulkarni@amd.com>
-//              Bala Kishore <balakishore.pati@amd.com>
-
-#include <sof/audio/component.h>
-#include <sof/drivers/acp_dai_dma.h>
-#include <rtos/interrupt.h>
-#include <rtos/alloc.h>
-#include <sof/lib/dai.h>
-#include <sof/lib/dma.h>
-#include <sof/lib/uuid.h>
-#include <ipc/dai.h>
-#include <ipc/topology.h>
-#include <platform/fw_scratch_mem.h>
-#include <sof/lib/io.h>
-#include <platform/chip_offset_byte.h>
-
-SOF_DEFINE_REG_UUID(spdai);
-/* unused with Zephyr, generates no output */
-DECLARE_TR_CTX(spdai_tr, SOF_UUID(spdai_uuid), LOG_LEVEL_INFO);
-
-static inline int spdai_set_config(struct dai *dai, struct ipc_config_dai *common_config,
-				   const void *spec_config)
-{
-	const struct sof_ipc_dai_config *config = spec_config;
-	struct acp_pdata *acpdata = dai_get_drvdata(dai);
-
-	acp_i2stdm_iter_t sp_iter;
-	acp_i2stdm_irer_t sp_irer;
-
-	acpdata->config = *config;
-	acpdata->params = config->acpsp;
-
-	sp_iter = (acp_i2stdm_iter_t)io_reg_read(PU_REGISTER_BASE + ACP_I2STDM_ITER);
-	sp_irer = (acp_i2stdm_irer_t)io_reg_read(PU_REGISTER_BASE + ACP_I2STDM_IRER);
-	switch (config->format & SOF_DAI_FMT_FORMAT_MASK) {
-	case SOF_DAI_FMT_DSP_A:
-		{
-		acp_i2stdm_txfrmt_t i2stdm_txfrmt;
-		acp_i2stdm_rxfrmt_t reg_i2stdm_rxfrmt;
-
-		i2stdm_txfrmt.u32all = io_reg_read((PU_REGISTER_BASE + ACP_I2STDM_TXFRMT));
-		i2stdm_txfrmt.bits.i2stdm_num_slots = acpdata->params.tdm_slots;
-		i2stdm_txfrmt.bits.i2stdm_slot_len = 16;
-		io_reg_write((PU_REGISTER_BASE + ACP_I2STDM_TXFRMT), i2stdm_txfrmt.u32all);
-
-		sp_iter.bits.i2stdm_tx_protocol_mode = 1;
-		io_reg_write((PU_REGISTER_BASE + ACP_I2STDM_ITER), sp_iter.u32all);
-
-		reg_i2stdm_rxfrmt.u32all = io_reg_read((PU_REGISTER_BASE + ACP_I2STDM_RXFRMT));
-		reg_i2stdm_rxfrmt.bits.i2stdm_num_slots = 2;
-		reg_i2stdm_rxfrmt.bits.i2stdm_slot_len = 16;
-		io_reg_write((PU_REGISTER_BASE + ACP_I2STDM_RXFRMT), reg_i2stdm_rxfrmt.u32all);
-
-		sp_irer.bits.i2stdm_rx_protocol_mode = 1;
-		io_reg_write((PU_REGISTER_BASE + ACP_I2STDM_IRER), sp_irer.u32all);
-		}
-		break;
-	case SOF_DAI_FMT_I2S:
-		sp_iter.bits.i2stdm_tx_protocol_mode = 0;
-		io_reg_write((PU_REGISTER_BASE + ACP_I2STDM_ITER), sp_iter.u32all);
-
-		sp_irer.bits.i2stdm_rx_protocol_mode = 0;
-		io_reg_write((PU_REGISTER_BASE + ACP_I2STDM_IRER), sp_irer.u32all);
-		break;
-	default:
-		dai_err(dai, "hsdai_set_config invalid format");
-		return -EINVAL;
-		}
-	return 0;
-}
-
-static int spdai_trigger(struct dai *dai, int cmd, int direction)
-{
-	/* nothing to do on renoir for SP dai */
-	return 0;
-}
-
-static int spdai_probe(struct dai *dai)
-{
-	struct acp_pdata *acp;
-
-	dai_info(dai, "SP dai probe");
-	/* allocate private data */
-	acp = rzalloc(SOF_MEM_FLAG_KERNEL | SOF_MEM_FLAG_COHERENT, sizeof(*acp));
-	if (!acp) {
-		dai_err(dai, "SP dai probe alloc failed");
-		return -ENOMEM;
-	}
-	dai_set_drvdata(dai, acp);
-	return 0;
-}
-
-static int spdai_remove(struct dai *dai)
-{
-	struct acp_pdata *acp = dai_get_drvdata(dai);
-
-	rfree(acp);
-	dai_set_drvdata(dai, NULL);
-	return 0;
-}
-
-static int spdai_get_fifo(struct dai *dai, int direction, int stream_id)
-{
-	switch (direction) {
-	case DAI_DIR_PLAYBACK:
-	case DAI_DIR_CAPTURE:
-		return dai_fifo(dai, direction);
-	default:
-		dai_err(dai, "Invalid direction");
-		return -EINVAL;
-	}
-}
-
-static int spdai_get_handshake(struct dai *dai, int direction, int stream_id)
-{
-	return dai->plat_data.fifo[direction].handshake;
-}
-
-static int spdai_get_hw_params(struct dai *dai,
-			      struct sof_ipc_stream_params *params,
-			      int dir)
-{
-	struct acp_pdata *acpdata = dai_get_drvdata(dai);
-
-	if (dir == DAI_DIR_PLAYBACK) {
-		/* SP DAI currently supports only these parameters */
-		params->rate = ACP_DEFAULT_SAMPLE_RATE;
-		params->channels = acpdata->params.tdm_slots;
-		params->buffer_fmt = SOF_IPC_BUFFER_INTERLEAVED;
-		params->frame_fmt = SOF_IPC_FRAME_S16_LE;
-	} else if (dir == DAI_DIR_CAPTURE) {
-		/* SP DAI currently supports only these parameters */
-		params->rate = ACP_DEFAULT_SAMPLE_RATE;
-		params->channels = 2;
-		params->buffer_fmt = SOF_IPC_BUFFER_INTERLEAVED;
-		params->frame_fmt = SOF_IPC_FRAME_S16_LE;
-	}
-	return 0;
-}
-
-const struct dai_driver acp_spdai_driver = {
-	.type = SOF_DAI_AMD_SP,
-	.uid = SOF_UUID(spdai_uuid),
-#if !CONFIG_ZEPHYR_LOG
-	.tctx = &spdai_tr,
-#endif
-	.dma_dev = DMA_DEV_SP,
-	.dma_caps = DMA_CAP_SP,
-	.ops = {
-		.trigger		= spdai_trigger,
-		.set_config		= spdai_set_config,
-		.probe			= spdai_probe,
-		.remove			= spdai_remove,
-		.get_fifo		= spdai_get_fifo,
-		.get_handshake		= spdai_get_handshake,
-		.get_hw_params          = spdai_get_hw_params,
-	},
-};
-
-
diff --git a/src/drivers/amd/renoir/acp_sp_dma.c b/src/drivers/amd/renoir/acp_sp_dma.c
deleted file mode 100644
index ba488600826d..000000000000
--- a/src/drivers/amd/renoir/acp_sp_dma.c
+++ /dev/null
@@ -1,310 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-//
-//Copyright(c) 2021 AMD. All rights reserved.
-//
-//Author:       Basavaraj Hiregoudar <basavaraj.hiregoudar@amd.com>
-//              Anup Kulkarni <anup.kulkarni@amd.com>
-//              Bala Kishore <balakishore.pati@amd.com>
-
-#include <rtos/atomic.h>
-#include <sof/audio/component.h>
-#include <rtos/bit.h>
-#include <sof/drivers/acp_dai_dma.h>
-#include <rtos/interrupt.h>
-#include <rtos/timer.h>
-#include <rtos/alloc.h>
-#include <rtos/clk.h>
-#include <sof/lib/cpu.h>
-#include <sof/lib/dma.h>
-#include <sof/lib/io.h>
-#include <sof/lib/pm_runtime.h>
-#include <sof/lib/notifier.h>
-#include <sof/platform.h>
-#include <sof/schedule/schedule.h>
-#include <rtos/spinlock.h>
-#include <sof/math/numbers.h>
-#include <sof/trace/trace.h>
-#include <ipc/topology.h>
-#include <user/trace.h>
-#include <errno.h>
-#include <stdbool.h>
-#include <stddef.h>
-#include <stdint.h>
-#include <platform/fw_scratch_mem.h>
-#include <platform/chip_registers.h>
-#include <platform/acp_sp_dma.h>
-
-SOF_DEFINE_REG_UUID(acp_sp);
-/* unused with Zephyr, generates no output */
-DECLARE_TR_CTX(acp_sp_rn_tr, SOF_UUID(acp_sp_uuid), LOG_LEVEL_INFO);
-
-static uint64_t prev_tx_pos;
-static uint64_t prev_rx_pos;
-static uint32_t sp_buff_size_playback;
-static uint32_t sp_buff_size_capture;
-/* allocate next free DMA channel */
-int acp_dai_sp_dma_start(struct dma_chan_data *channel)
-{
-	acp_i2stdm_ier_t sp_ier;
-	acp_i2stdm_iter_t sp_iter;
-	acp_i2stdm_irer_t sp_irer;
-	uint32_t acp_pdm_en;
-
-	sp_iter = (acp_i2stdm_iter_t)io_reg_read((PU_REGISTER_BASE + ACP_I2STDM_ITER));
-	sp_irer = (acp_i2stdm_irer_t)io_reg_read((PU_REGISTER_BASE + ACP_I2STDM_IRER));
-	acp_pdm_en = (uint32_t)io_reg_read(PU_REGISTER_BASE + ACP_WOV_PDM_ENABLE);
-
-	if (!sp_iter.bits.i2stdm_txen && !sp_irer.bits.i2stdm_rx_en && !acp_pdm_en) {
-		io_reg_write((PU_REGISTER_BASE + ACP_CLKMUX_SEL), ACP_ACLK_CLK_SEL);
-		/* Request SMU to set aclk to 600 Mhz */
-		acp_change_clock_notify(600000000);
-	}
-	if (channel->direction == DMA_DIR_MEM_TO_DEV) {
-		channel->status = COMP_STATE_ACTIVE;
-		prev_tx_pos = 0;
-		sp_ier = (acp_i2stdm_ier_t)io_reg_read((PU_REGISTER_BASE + ACP_I2STDM_IER));
-		sp_ier.bits.i2stdm_ien = 1;
-		io_reg_write((PU_REGISTER_BASE + ACP_I2STDM_IER), sp_ier.u32all);
-		sp_iter.bits.i2stdm_txen = 1;
-		sp_iter.bits.i2stdm_tx_data_path_mode = 1;
-		sp_iter.bits.i2stdm_tx_samp_len = 2;
-		io_reg_write((PU_REGISTER_BASE + ACP_I2STDM_ITER), sp_iter.u32all);
-	} else if (channel->direction == DMA_DIR_DEV_TO_MEM) {
-		channel->status = COMP_STATE_ACTIVE;
-		prev_rx_pos = 0;
-		sp_ier = (acp_i2stdm_ier_t)io_reg_read((PU_REGISTER_BASE + ACP_I2STDM_IER));
-		sp_ier.bits.i2stdm_ien = 1;
-		io_reg_write((PU_REGISTER_BASE + ACP_I2STDM_IER), sp_ier.u32all);
-		sp_irer.bits.i2stdm_rx_en = 1;
-		sp_irer.bits.i2stdm_rx_data_path_mode = 1;
-		sp_irer.bits.i2stdm_rx_samplen = 2;
-		io_reg_write((PU_REGISTER_BASE + ACP_I2STDM_IRER), sp_irer.u32all);
-	} else {
-		tr_err(&acp_sp_rn_tr, "Start direction not defined %d", channel->direction);
-		return -EINVAL;
-	}
-
-	return 0;
-}
-
-int acp_dai_sp_dma_stop(struct dma_chan_data *channel)
-{
-	acp_i2stdm_irer_t sp_irer;
-	acp_i2stdm_iter_t sp_iter;
-	uint32_t acp_pdm_en;
-
-	switch (channel->status) {
-	case COMP_STATE_READY:
-	case COMP_STATE_PREPARE:
-		return 0;
-	case COMP_STATE_PAUSED:
-	case COMP_STATE_ACTIVE:
-		break;
-	default:
-		return -EINVAL;
-	}
-	channel->status = COMP_STATE_READY;
-	if (channel->direction == DMA_DIR_MEM_TO_DEV) {
-		sp_iter = (acp_i2stdm_iter_t)io_reg_read((PU_REGISTER_BASE + ACP_I2STDM_ITER));
-		sp_iter.bits.i2stdm_txen = 0;
-		io_reg_write((PU_REGISTER_BASE + ACP_I2STDM_ITER), sp_iter.u32all);
-	} else if (channel->direction == DMA_DIR_DEV_TO_MEM) {
-		sp_irer = (acp_i2stdm_irer_t)io_reg_read((PU_REGISTER_BASE + ACP_I2STDM_IRER));
-		sp_irer.bits.i2stdm_rx_en = 0;
-		io_reg_write((PU_REGISTER_BASE + ACP_I2STDM_IRER), sp_irer.u32all);
-	} else {
-		tr_err(&acp_sp_rn_tr, "Stop direction not defined %d", channel->direction);
-		return -EINVAL;
-	}
-	sp_iter = (acp_i2stdm_iter_t)io_reg_read((PU_REGISTER_BASE + ACP_I2STDM_ITER));
-	sp_irer = (acp_i2stdm_irer_t)io_reg_read((PU_REGISTER_BASE + ACP_I2STDM_IRER));
-	acp_pdm_en = (uint32_t)io_reg_read(PU_REGISTER_BASE + ACP_WOV_PDM_ENABLE);
-
-	if (!sp_iter.bits.i2stdm_txen && !sp_irer.bits.i2stdm_rx_en) {
-		io_reg_write((PU_REGISTER_BASE + ACP_I2STDM_IER), SP_IER_DISABLE);
-		/* Request SMU to scale down aclk to minimum clk */
-		if (!acp_pdm_en) {
-			acp_change_clock_notify(0);
-			io_reg_write((PU_REGISTER_BASE + ACP_CLKMUX_SEL), ACP_INTERNAL_CLK_SEL);
-		}
-	}
-
-	return 0;
-}
-
-/* set the DMA channel configuration, source/target address, buffer sizes */
-int acp_dai_sp_dma_set_config(struct dma_chan_data *channel,
-			      struct dma_sg_config *config)
-{
-	uint32_t sp_buff_addr;
-	uint32_t sp_fifo_addr;
-
-	if (!config->cyclic) {
-		tr_err(&acp_sp_rn_tr, "cyclic configurations only supported!");
-		return -EINVAL;
-	}
-	if (config->scatter) {
-		tr_err(&acp_sp_rn_tr, "scatter enabled, that is not supported for now!");
-		return -EINVAL;
-	}
-
-	volatile acp_scratch_mem_config_t *pscratch_mem_cfg =
-		(volatile acp_scratch_mem_config_t *)(PU_REGISTER_BASE + SCRATCH_REG_OFFSET);
-	channel->is_scheduling_source = true;
-	channel->direction = config->direction;
-
-	if (config->direction ==  DMA_DIR_MEM_TO_DEV) {
-
-		sp_buff_size_playback = config->elem_array.elems[0].size * config->elem_array.count;
-		/* SP Transmit FIFO Address and FIFO Size*/
-		sp_fifo_addr = (uint32_t)(&pscratch_mem_cfg->acp_transmit_fifo_buffer);
-		memset((void *)sp_fifo_addr, 0, SP_FIFO_SIZE);
-		io_reg_write((PU_REGISTER_BASE + ACP_I2S_TX_FIFOADDR), sp_fifo_addr);
-		io_reg_write((PU_REGISTER_BASE + ACP_I2S_TX_FIFOSIZE), (uint32_t)(SP_FIFO_SIZE));
-
-		/* Transmit RINGBUFFER Address and size*/
-		sp_buff_addr = config->elem_array.elems[0].src & ACP_DRAM_ADDRESS_MASK;
-		io_reg_write((PU_REGISTER_BASE + ACP_I2S_TX_RINGBUFADDR), sp_buff_addr);
-		io_reg_write((PU_REGISTER_BASE + ACP_I2S_TX_RINGBUFSIZE), sp_buff_size_playback);
-
-		/* Transmit DMA transfer size in bytes */
-		io_reg_write((PU_REGISTER_BASE + ACP_I2S_TX_DMA_SIZE),
-			     (uint32_t)(ACP_DMA_TRANS_SIZE));
-
-		/* Watermark size for SP transmit FIFO - Half of SP buffer size */
-		io_reg_write((PU_REGISTER_BASE + ACP_I2S_TX_INTR_WATERMARK_SIZE),
-			     (sp_buff_size_playback >> 1));
-
-	} else if (config->direction == DMA_DIR_DEV_TO_MEM) {
-
-		sp_buff_size_capture = config->elem_array.elems[0].size * config->elem_array.count;
-		/* SP Receive FIFO Address and FIFO Size*/
-		sp_fifo_addr = (uint32_t)(&pscratch_mem_cfg->acp_receive_fifo_buffer);
-		memset((void *)sp_fifo_addr, 0, SP_FIFO_SIZE);
-		io_reg_write((PU_REGISTER_BASE + ACP_I2S_RX_FIFOADDR), sp_fifo_addr);
-		io_reg_write((PU_REGISTER_BASE + ACP_I2S_RX_FIFOSIZE),
-			     (uint32_t)(SP_FIFO_SIZE));
-
-		/* Receive RINGBUFFER Address and size*/
-		sp_buff_addr = config->elem_array.elems[0].dest & ACP_DRAM_ADDRESS_MASK;
-		io_reg_write((PU_REGISTER_BASE + ACP_I2S_RX_RINGBUFADDR), sp_buff_addr);
-		io_reg_write((PU_REGISTER_BASE + ACP_I2S_RX_RINGBUFSIZE), sp_buff_size_capture);
-
-		/* Receive DMA transfer size in bytes */
-		io_reg_write((PU_REGISTER_BASE + ACP_I2S_RX_DMA_SIZE),
-			     (uint32_t)(ACP_DMA_TRANS_SIZE));
-
-		/* Watermark size for SP receive fifo - Half of SP buffer size*/
-		io_reg_write((PU_REGISTER_BASE + ACP_I2S_RX_INTR_WATERMARK_SIZE),
-			     (sp_buff_size_capture >> 1));
-
-	} else {
-		tr_err(&acp_sp_rn_tr, "config channel direction undefined %d", channel->direction);
-		return -EINVAL;
-	}
-
-	return 0;
-}
-
-int acp_dai_sp_dma_get_data_size(struct dma_chan_data *channel,
-				 uint32_t *avail, uint32_t *free)
-{
-	if (channel->direction == DMA_DIR_MEM_TO_DEV) {
-#if CONFIG_DISABLE_DESCRIPTOR_SPLIT
-		uint64_t tx_low, curr_tx_pos, tx_high;
-		tx_low = (uint32_t)io_reg_read(PU_REGISTER_BASE +
-				ACP_I2S_TX_LINEARPOSITIONCNTR_LOW);
-		tx_high = (uint32_t)io_reg_read(PU_REGISTER_BASE +
-				ACP_I2S_TX_LINEARPOSITIONCNTR_HIGH);
-		curr_tx_pos = (uint64_t)((tx_high<<32) | tx_low);
-		*free = (curr_tx_pos - prev_tx_pos) > sp_buff_size_playback ?
-			(curr_tx_pos - prev_tx_pos) % sp_buff_size_playback :
-			(curr_tx_pos - prev_tx_pos);
-		*avail = sp_buff_size_playback - *free;
-		prev_tx_pos = curr_tx_pos;
-#else
-		*free = (sp_buff_size_playback >> 1);
-		*avail = (sp_buff_size_playback >> 1);
-#endif
-	} else if (channel->direction == DMA_DIR_DEV_TO_MEM) {
-#if CONFIG_DISABLE_DESCRIPTOR_SPLIT
-		uint64_t rx_low, curr_rx_pos, rx_high;
-		rx_low = (uint32_t)io_reg_read(PU_REGISTER_BASE +
-				ACP_I2S_RX_LINEARPOSITIONCNTR_LOW);
-		rx_high = (uint32_t)io_reg_read(PU_REGISTER_BASE +
-				ACP_I2S_RX_LINEARPOSITIONCNTR_HIGH);
-		curr_rx_pos = (uint64_t)((rx_high<<32) | rx_low);
-		*free = (curr_rx_pos - prev_rx_pos) > sp_buff_size_capture ?
-			(curr_rx_pos - prev_rx_pos) % sp_buff_size_capture :
-			(curr_rx_pos - prev_rx_pos);
-		*avail = sp_buff_size_capture - *free;
-		prev_rx_pos = curr_rx_pos;
-#else
-		*avail = (sp_buff_size_capture >> 1);
-		*free  = (sp_buff_size_capture >> 1);
-#endif
-	} else {
-		tr_err(&acp_sp_rn_tr, "Channel direction not defined %d", channel->direction);
-		return -EINVAL;
-	}
-	return 0;
-}
-
-int acp_dai_sp_dma_get_attribute(struct dma *dma, uint32_t type, uint32_t *value)
-{
-	switch (type) {
-	case DMA_ATTR_BUFFER_ALIGNMENT:
-	case DMA_ATTR_COPY_ALIGNMENT:
-		*value = ACP_DMA_BUFFER_ALIGN;
-		break;
-	case DMA_ATTR_BUFFER_ADDRESS_ALIGNMENT:
-		*value = PLATFORM_DCACHE_ALIGN;
-		break;
-	case DMA_ATTR_BUFFER_PERIOD_COUNT:
-		*value = ACP_DAI_DMA_BUFFER_PERIOD_COUNT;
-		break;
-	default:
-		return -ENOENT;
-	}
-	return 0;
-}
-
-int acp_dai_sp_dma_interrupt(struct dma_chan_data *channel, enum dma_irq_cmd cmd)
-{
-	uint32_t status;
-	acp_dsp0_intr_stat_t acp_intr_stat;
-	acp_dsp0_intr_cntl_t acp_intr_cntl;
-
-	if (channel->status == COMP_STATE_INIT)
-		return 0;
-	switch (cmd) {
-	case DMA_IRQ_STATUS_GET:
-		acp_intr_stat =  (acp_dsp0_intr_stat_t)
-			(dma_reg_read(channel->dma, ACP_DSP0_INTR_STAT));
-		status = acp_intr_stat.bits.audio_buffer_int_stat;
-		return (status & (1<<channel->index));
-	case DMA_IRQ_CLEAR:
-		acp_intr_stat.u32all = 0;
-		acp_intr_stat.bits.audio_buffer_int_stat =
-					(1 << channel->index);
-		status  = acp_intr_stat.u32all;
-		dma_reg_write(channel->dma, ACP_DSP0_INTR_STAT, status);
-		return 0;
-	case DMA_IRQ_MASK:
-		acp_intr_cntl =  (acp_dsp0_intr_cntl_t)
-				dma_reg_read(channel->dma, ACP_DSP0_INTR_CNTL);
-		acp_intr_cntl.bits.audio_buffer_int_mask &= (~(1 << channel->index));
-		status  = acp_intr_cntl.u32all;
-		dma_reg_write(channel->dma, ACP_DSP0_INTR_CNTL, status);
-		return 0;
-	case DMA_IRQ_UNMASK:
-		acp_intr_cntl =  (acp_dsp0_intr_cntl_t)
-				dma_reg_read(channel->dma, ACP_DSP0_INTR_CNTL);
-		acp_intr_cntl.bits.audio_buffer_int_mask  |=  (1 << channel->index);
-		status = acp_intr_cntl.u32all;
-		dma_reg_write(channel->dma, ACP_DSP0_INTR_CNTL, status);
-		return 0;
-	default:
-		return -EINVAL;
-	}
-}
diff --git a/src/drivers/amd/renoir/interrupt.c b/src/drivers/amd/renoir/interrupt.c
deleted file mode 100644
index 38407dfe5fc8..000000000000
--- a/src/drivers/amd/renoir/interrupt.c
+++ /dev/null
@@ -1,381 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-//
-//Copyright(c) 2021 AMD. All rights reserved.
-//
-//Author:       Basavaraj Hiregoudar <basavaraj.hiregoudar@amd.com>
-//              Anup Kulkarni <anup.kulkarni@amd.com>
-//              Bala Kishore <balakishore.pati@amd.com>
-#include <sof/common.h>
-#include <platform/chip_offset_byte.h>
-#include <platform/chip_registers.h>
-#include <rtos/interrupt.h>
-#include <sof/lib/cpu.h>
-#include <sof/lib/io.h>
-#include <sof/lib/memory.h>
-#include <sof/lib/uuid.h>
-#include <sof/list.h>
-#include <rtos/spinlock.h>
-#include <xtensa/hal.h>
-#include <xtensa/config/core.h>
-#include <xtensa/config/specreg.h>
-#include <xtensa/core-macros.h>
-#include "xtos-internal.h"
-#include <errno.h>
-#include <inttypes.h>
-#include <stdbool.h>
-#include <stddef.h>
-#include <stdint.h>
-
-SOF_DEFINE_REG_UUID(irq_acp);
-
-/* unused with Zephyr, generates no output */
-DECLARE_TR_CTX(acp_irq_tr, SOF_UUID(irq_acp_uuid), LOG_LEVEL_INFO);
-
-#define IRQ_INT_MASK(irq)	(1 << (irq))
-#define RESERVED_IRQS_NUM	0
-#define IRQS_NUM		8
-#define IRQS_PER_LINE		1
-
-static inline uint32_t acp_irq_status_read(uint32_t reg)
-{
-	return io_reg_read(PU_REGISTER_BASE + reg);
-}
-
-static inline void acp_irq_update_bits(uint32_t reg, uint32_t mask,
-				      uint32_t value)
-{
-	io_reg_update_bits(PU_REGISTER_BASE + reg, mask, value);
-}
-
-static uint32_t acp_irq_get_status(uint32_t index)
-{
-	/* 0-7 interrupts are used */
-	if (index > 7)
-		return 0;
-	return acp_irq_status_read(ACP_DSP0_INTR_STAT);
-}
-
-static void acp_irq_mask_int(uint32_t irq)
-{
-	uint32_t mask;
-
-	if (irq < RESERVED_IRQS_NUM || irq >= IRQS_NUM) {
-		tr_err(&acp_irq_tr, "Invalid interrupt");
-		return;
-	}
-	mask = IRQ_INT_MASK(irq);
-	acp_irq_update_bits(ACP_DSP0_INTR_CNTL, mask, 0);
-}
-
-static void acp_irq_unmask_int(uint32_t irq)
-{
-	uint32_t mask;
-
-	if (irq < RESERVED_IRQS_NUM || irq >= IRQS_NUM) {
-		tr_err(&acp_irq_tr, "Invalid interrupt");
-		return;
-	}
-	mask = IRQ_INT_MASK(irq);
-	acp_irq_update_bits(ACP_DSP0_INTR_CNTL, mask, mask);
-}
-
-static uint64_t acp_get_irq_interrupts(uint32_t index)
-{
-	return acp_irq_get_status(index);
-}
-
-static int get_first_irq(uint64_t ints)
-{
-	return ffs(ints) - 1;
-}
-
-static inline void acp_handle_irq(struct irq_cascade_desc *cascade,
-				    uint32_t line_index, uint64_t status)
-{
-	int core = cpu_get_id();
-	struct list_item *clist;
-	struct irq_desc *child = NULL;
-	int bit;
-	bool handled;
-	k_spinlock_key_t key;
-
-	while (status) {
-		bit = get_first_irq(status);
-		handled = false;
-		status &= ~(1ull << bit);
-
-		key = k_spin_lock(&cascade->lock);
-
-		list_for_item(clist, &cascade->child[bit].list) {
-			child = container_of(clist, struct irq_desc, irq_list);
-
-			if (child->handler && (child->cpu_mask & 1 << core)) {
-				child->handler(child->handler_arg);
-				handled = true;
-			}
-		}
-
-		k_spin_unlock(&cascade->lock, key);
-
-		if (!handled) {
-			tr_err(&acp_irq_tr, "irq_handler(): not handled, bit %d",
-					bit);
-			acp_irq_mask_int(line_index * IRQS_PER_LINE + bit);
-		}
-	}
-}
-
-static inline void irq_handler(void *data, uint32_t line_index)
-{
-	struct irq_desc *parent = data;
-	struct irq_cascade_desc *cascade =
-		container_of(parent, struct irq_cascade_desc, desc);
-	uint64_t status;
-
-	status = acp_get_irq_interrupts(line_index);
-
-	if (status)
-		/* Handle current interrupts */
-		acp_handle_irq(cascade, line_index, status);
-	else
-		tr_err(&acp_irq_tr, "invalid interrupt status");
-}
-
-#define DEFINE_IRQ_HANDLER(n) \
-	static void irqhandler_##n(void *arg) \
-	{ \
-		irq_handler(arg, n); \
-	}
-
-DEFINE_IRQ_HANDLER(0)
-DEFINE_IRQ_HANDLER(1)
-DEFINE_IRQ_HANDLER(3)
-DEFINE_IRQ_HANDLER(4)
-DEFINE_IRQ_HANDLER(5)
-
-static void acp_irq_mask(struct irq_desc *desc, uint32_t irq, unsigned int core)
-{
-	acp_irq_mask_int(irq);
-}
-
-static void acp_irq_unmask(struct irq_desc *desc, uint32_t irq, unsigned int core)
-{
-	acp_irq_unmask_int(irq);
-}
-
-static const struct irq_cascade_ops irq_ops = {
-	.mask = acp_irq_mask,
-	.unmask = acp_irq_unmask,
-};
-
-static const struct irq_cascade_tmpl dsp_irq[] = {
-	{
-		.irq = IRQ_NUM_TIMER0,
-		.handler = irqhandler_0,
-		.ops = &irq_ops,
-		.global_mask = false,
-	}, {
-		.irq = IRQ_NUM_SOFTWARE0,
-		.handler = irqhandler_1,
-		.ops = &irq_ops,
-		.global_mask = false,
-	},
-	{
-		.irq = IRQ_NUM_EXT_LEVEL3,
-		.handler = irqhandler_3,
-		.ops = &irq_ops,
-		.global_mask = false,
-	},
-	{
-		.irq = IRQ_NUM_EXT_LEVEL4,
-		.handler = irqhandler_4,
-		.ops = &irq_ops,
-		.global_mask = false,
-	},
-	{
-		.irq = IRQ_NUM_EXT_LEVEL5,
-		.handler = irqhandler_5,
-		.ops = &irq_ops,
-		.global_mask = false,
-	},
-};
-
-void platform_interrupt_init(void)
-{
-	int i;
-
-	acp_intr_route();
-	/* disable all interrupts and their service routines */
-	acp_intr_disable();
-	for (i = 0; i < ARRAY_SIZE(dsp_irq); i++)
-		interrupt_cascade_register(dsp_irq + i);
-	acp_intr_enable();
-	acp_dsp_sw_intr_enable();
-}
-
-void platform_interrupt_set(uint32_t irq)
-{
-	if (interrupt_is_dsp_direct(irq))
-		arch_interrupt_set(irq);
-}
-
-void platform_interrupt_clear(uint32_t irq, uint32_t mask)
-{
-	switch (irq) {
-	case IRQ_NUM_TIMER0:
-	case IRQ_NUM_SOFTWARE0:
-	case IRQ_NUM_EXT_LEVEL3:
-	case IRQ_NUM_EXT_LEVEL4:
-	case IRQ_NUM_EXT_LEVEL5:
-		if (interrupt_is_dsp_direct(irq))
-			arch_interrupt_clear(irq);
-		break;
-	default:
-		break;
-	}
-}
-
-uint32_t platform_interrupt_get_enabled(void)
-{
-	/* TODO */
-	return 0;
-}
-
-void interrupt_mask(uint32_t irq, unsigned int cpu)
-{
-	if (interrupt_is_dsp_direct(irq))
-		arch_interrupt_clear(irq);
-}
-
-void interrupt_unmask(uint32_t irq, unsigned int cpu)
-{
-	if (interrupt_is_dsp_direct(irq))
-		arch_interrupt_set(irq);
-}
-
-
-void acp_intr_route(void)
-{
-	dsp_interrupt_routing_ctrl_t interrupt_rout_cntl;
-	/* Routing the particular interrupts to the particular level */
-	interrupt_rout_cntl = (dsp_interrupt_routing_ctrl_t) io_reg_read(
-			(PU_REGISTER_BASE + DSP_INTERRUPT_ROUTING_CTRL));
-	interrupt_rout_cntl.bits.dma_intr_level	= acp_interrupt_level_5;
-	interrupt_rout_cntl.bits.az_sw_i2s_intr_level	 = acp_interrupt_level_5;
-	interrupt_rout_cntl.bits.host_to_dsp_intr1_level = acp_interrupt_level_3;
-	interrupt_rout_cntl.bits.wov_intr_level		 = acp_interrupt_level_4;
-	io_reg_write((PU_REGISTER_BASE + DSP_INTERRUPT_ROUTING_CTRL),
-						interrupt_rout_cntl.u32all);
-}
-
-void acp_dsp_sw_intr_enable(void)
-{
-	acp_dsp_sw_intr_cntl_t  sw_intr_ctrl_reg;
-
-	xthal_set_intclear(IRQ_NUM_EXT_LEVEL5);
-	sw_intr_ctrl_reg = (acp_dsp_sw_intr_cntl_t) io_reg_read((PU_REGISTER_BASE +
-							ACP_DSP_SW_INTR_CNTL));
-	sw_intr_ctrl_reg.bits.dsp0_to_host_intr_mask   = INTERRUPT_ENABLE;
-	/* Write the Software Interrupt controller register */
-	io_reg_write((PU_REGISTER_BASE + ACP_DSP_SW_INTR_CNTL), sw_intr_ctrl_reg.u32all);
-	/* Enabling software interuppts */
-	platform_interrupt_set(IRQ_NUM_EXT_LEVEL3);
-}
-
-void acp_intr_enable(void)
-{
-	acp_dsp0_intr_cntl_t interrupt_cntl;
-	acp_dsp0_intr_stat_t interrupt_sts;
-	acp_external_intr_enb_t ext_interrupt_enb;
-
-	platform_interrupt_clear(IRQ_NUM_EXT_LEVEL5, 0);
-	platform_interrupt_clear(IRQ_NUM_TIMER0, 0);
-	interrupt_sts.u32all = 0;
-	/* Clear status of all interrupts in ACP_DSP0_INTR_STAT register */
-	interrupt_sts.bits.dmaiocstat		 = 0xFF;
-	interrupt_sts.bits.audio_buffer_int_stat = 0x3F;
-	interrupt_sts.bits.wov_dma_stat		 = INTERRUPT_ENABLE;
-	io_reg_write((PU_REGISTER_BASE + ACP_DSP0_INTR_STAT),
-					interrupt_sts.u32all);
-	/* Disable the ACP to Host interrupts */
-	ext_interrupt_enb.bits.acpextintrenb = INTERRUPT_ENABLE;
-	io_reg_write((PU_REGISTER_BASE + ACP_EXTERNAL_INTR_ENB),
-					ext_interrupt_enb.u32all);
-	interrupt_cntl = (acp_dsp0_intr_cntl_t) io_reg_read((PU_REGISTER_BASE +
-							ACP_DSP0_INTR_CNTL));
-	interrupt_cntl.u32all = 0;
-	io_reg_write((PU_REGISTER_BASE + ACP_DSP0_INTR_CNTL), interrupt_cntl.u32all);
-	interrupt_cntl.bits.dmaiocmask			= 0xFF;
-	interrupt_cntl.bits.audio_buffer_int_mask	= INTERRUPT_DISABLE;
-	interrupt_cntl.bits.wov_dma_intr_mask		= INTERRUPT_DISABLE;
-	io_reg_write((PU_REGISTER_BASE + ACP_DSP0_INTR_CNTL), interrupt_cntl.u32all);
-	platform_interrupt_set(IRQ_NUM_EXT_LEVEL5);
-	platform_interrupt_set(IRQ_NUM_EXT_LEVEL4);
-}
-
-void acp_intr_disable(void)
-{
-	acp_dsp0_intr_stat_t interrupt_status;
-	acp_external_intr_enb_t ext_interrupt_enb;
-	acp_dsp0_intr_cntl_t interrupt_cntl;
-
-	interrupt_status = (acp_dsp0_intr_stat_t) io_reg_read((PU_REGISTER_BASE +
-							ACP_DSP0_INTR_STAT));
-	/* Check and Clear all the Interrupt status bits */
-	interrupt_status.bits.dmaiocstat		= 0xFF;
-	interrupt_status.bits.audio_buffer_int_stat	= 0x3F;
-	interrupt_status.bits.wov_dma_stat		= INTERRUPT_ENABLE;
-	io_reg_write((PU_REGISTER_BASE + ACP_DSP0_INTR_STAT), interrupt_status.u32all);
-	/* Disable the ACP to Host interrupts */
-	ext_interrupt_enb.bits.acpextintrenb = INTERRUPT_CLEAR;
-	io_reg_write((PU_REGISTER_BASE + ACP_EXTERNAL_INTR_ENB),  ext_interrupt_enb.u32all);
-	/* Disable all the required ACP interrupts
-	 * in acp_dsp0_intr_cntl_t register
-	 */
-	interrupt_cntl = (acp_dsp0_intr_cntl_t) io_reg_read((PU_REGISTER_BASE +
-							ACP_DSP0_INTR_CNTL));
-	interrupt_cntl.bits.dmaiocmask			= INTERRUPT_DISABLE;
-	interrupt_cntl.bits.audio_buffer_int_mask	= INTERRUPT_DISABLE;
-	interrupt_cntl.bits.wov_dma_intr_mask		= INTERRUPT_DISABLE;
-	io_reg_write((PU_REGISTER_BASE + ACP_DSP0_INTR_CNTL),  interrupt_cntl.u32all);
-	platform_interrupt_clear(IRQ_NUM_EXT_LEVEL5, 0);
-	platform_interrupt_clear(IRQ_NUM_EXT_LEVEL3, 0);
-	platform_interrupt_clear(IRQ_NUM_EXT_LEVEL4, 0);
-	platform_interrupt_clear(IRQ_NUM_TIMER1, 0);
-	platform_interrupt_clear(IRQ_NUM_TIMER0, 0);
-}
-
-void acp_dsp_sw_intr_disable(void)
-{
-	acp_dsp_sw_intr_cntl_t  sw_intr_ctrl_reg;
-	/* Read the register */
-	sw_intr_ctrl_reg = (acp_dsp_sw_intr_cntl_t) io_reg_read((PU_REGISTER_BASE +
-							ACP_DSP_SW_INTR_CNTL));
-	sw_intr_ctrl_reg.bits.dsp0_to_host_intr_mask = INTERRUPT_DISABLE;
-	/* Write the Software Interrupt controller register */
-	io_reg_write((PU_REGISTER_BASE + ACP_DSP_SW_INTR_CNTL), sw_intr_ctrl_reg.u32all);
-	platform_interrupt_clear(IRQ_NUM_EXT_LEVEL3, 0);
-}
-
-/* This function triggers a host interrupt from ACP DSP */
-void acp_dsp_to_host_intr_trig(void)
-{
-	acp_sw_intr_trig_t  sw_intr_trig;
-	/* Read the Software Interrupt controller register and update */
-	sw_intr_trig = (acp_sw_intr_trig_t) io_reg_read(PU_REGISTER_BASE + ACP_SW_INTR_TRIG);
-	/* Configures the trigger bit in ACP_DSP_SW_INTR_TRIG register */
-	sw_intr_trig.bits.trig_dsp0_to_host_intr = INTERRUPT_ENABLE;
-	/* Write the Software Interrupt controller register */
-	io_reg_write((PU_REGISTER_BASE + ACP_SW_INTR_TRIG), sw_intr_trig.u32all);
-}
-
-/* Clear the Acknowledge ( status) for the host to DSP interrupt */
-void acp_ack_intr_from_host(void)
-{
-	/* acknowledge the host interrupt */
-	acp_dsp_sw_intr_stat_t sw_intr_stat;
-
-	sw_intr_stat.u32all = 0;
-	sw_intr_stat.bits.host_to_dsp0_intr1_stat = INTERRUPT_ENABLE;
-	io_reg_write((PU_REGISTER_BASE + ACP_DSP_SW_INTR_STAT), sw_intr_stat.u32all);
-}
diff --git a/src/drivers/amd/renoir/ipc.c b/src/drivers/amd/renoir/ipc.c
deleted file mode 100644
index b718f57540ba..000000000000
--- a/src/drivers/amd/renoir/ipc.c
+++ /dev/null
@@ -1,163 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-//
-//Copyright(c) 2021 AMD. All rights reserved.
-//
-//Author:       Basavaraj Hiregoudar <basavaraj.hiregoudar@amd.com>
-//              Anup Kulkarni <anup.kulkarni@amd.com>
-//              Bala Kishore <balakishore.pati@amd.com>
-
-#include <rtos/panic.h>
-#include <xtensa/core-macros.h>
-#include <platform/chip_offset_byte.h>
-#include <platform/chip_registers.h>
-#include <rtos/interrupt.h>
-#include <sof/ipc/driver.h>
-#include <sof/ipc/msg.h>
-#include <sof/ipc/schedule.h>
-#include <rtos/alloc.h>
-#include <sof/lib/dma.h>
-#include <sof/lib/mailbox.h>
-#include <sof/lib/memory.h>
-#include <sof/lib/uuid.h>
-#include <rtos/wait.h>
-#include <sof/list.h>
-#include <sof/platform.h>
-#include <sof/schedule/edf_schedule.h>
-#include <sof/schedule/schedule.h>
-#include <rtos/task.h>
-#include <rtos/spinlock.h>
-#include <ipc/header.h>
-#include <ipc/topology.h>
-#include <errno.h>
-#include <stddef.h>
-#include <stdint.h>
-#include <platform/platform.h>
-#include <platform/ipc.h>
-
-volatile acp_scratch_mem_config_t *pscratch_mem_cfg = (volatile acp_scratch_mem_config_t *)
-						      (PU_REGISTER_BASE + SCRATCH_REG_OFFSET);
-
-void amd_irq_handler(void *arg)
-{
-	struct ipc *ipc = arg;
-	uint32_t status;
-	uint32_t lock;
-	uint32_t delay_cnt = 10000;
-	bool lock_fail = false;
-	acp_dsp_sw_intr_stat_t swintrstat;
-	acp_sw_intr_trig_t  swintrtrig;
-
-	swintrstat = (acp_dsp_sw_intr_stat_t)io_reg_read(PU_REGISTER_BASE + ACP_DSP_SW_INTR_STAT);
-	status = swintrstat.u32all &  HOST_TO_DSP_INTR;
-	if (status) {
-		/* Interrupt source */
-		if (sof_ipc_host_status()) {
-			lock = io_reg_read(PU_REGISTER_BASE + ACP_AXI2DAGB_SEM_0);
-			while (lock) {
-				lock = io_reg_read(PU_REGISTER_BASE + ACP_AXI2DAGB_SEM_0);
-				if (!delay_cnt) {
-					lock_fail = true;
-					break;
-				}
-				delay_cnt--;
-			}
-			if (lock_fail) {
-				tr_err(&ipc_tr, "ACP fail to acquire the lock");
-				return;
-			}
-			/* Check if it is response from host */
-			if (sof_ipc_host_ack_flag()) {
-				/* Clear the ACK from host  */
-				sof_ipc_host_ack_clear();
-				/* Clear the Host to DSP Status Register */
-				acp_ack_intr_from_host();
-				/* Configures the trigger bit in ACP_DSP_SW_INTR_TRIG register */
-				swintrtrig = (acp_sw_intr_trig_t)
-					     io_reg_read(PU_REGISTER_BASE + ACP_SW_INTR_TRIG);
-				swintrtrig.bits.trig_host_to_dsp0_intr1	= INTERRUPT_DISABLE;
-				swintrtrig.bits.trig_dsp0_to_host_intr	= INTERRUPT_DISABLE;
-				io_reg_write((PU_REGISTER_BASE + ACP_SW_INTR_TRIG),
-					     swintrtrig.u32all);
-			}
-			/* Check if new message from host */
-			if (sof_ipc_host_msg_flag()) {
-				/* Clear the msg bit from host */
-				sof_ipc_host_msg_clear();
-				/* Clear the Host to DSP Status Register */
-				acp_ack_intr_from_host();
-				ipc_schedule_process(ipc);
-			}
-			io_reg_write((PU_REGISTER_BASE + ACP_AXI2DAGB_SEM_0), lock);
-		} else {
-			tr_err(&ipc_tr, "IPC:interrupt without setting flags host status 0x%x",
-			       sof_ipc_host_status());
-		}
-	}
-}
-
-void ipc_platform_complete_cmd(struct ipc *ipc)
-{
-	acp_sw_intr_trig_t  sw_intr_trig;
-
-	/* Set Dsp Ack for msg from host */
-	sof_ipc_dsp_ack_set();
-	/* Configures the trigger bit in ACP_DSP_SW_INTR_TRIG register */
-	sw_intr_trig = (acp_sw_intr_trig_t)
-		io_reg_read(PU_REGISTER_BASE + ACP_SW_INTR_TRIG);
-	sw_intr_trig.bits.trig_host_to_dsp0_intr1  = INTERRUPT_DISABLE;
-	sw_intr_trig.bits.trig_dsp0_to_host_intr = INTERRUPT_DISABLE;
-	io_reg_write((PU_REGISTER_BASE + ACP_SW_INTR_TRIG), sw_intr_trig.u32all);
-	/* now interrupt host to tell it we have sent a message */
-	acp_dsp_to_host_intr_trig();
-	if (ipc->pm_prepare_D3) {
-		while (1)
-			wait_for_interrupt(0);
-	}
-}
-
-int ipc_platform_send_msg(const struct ipc_msg *msg)
-{
-	acp_sw_intr_trig_t  sw_intr_trig;
-	acp_dsp_sw_intr_stat_t sw_intr_stat;
-	uint32_t status;
-	uint32_t lock;
-	uint32_t delay_cnt = 10000;
-	/* Check if host cleared the status for previous messages */
-	sw_intr_stat = (acp_dsp_sw_intr_stat_t)
-		io_reg_read(PU_REGISTER_BASE + ACP_DSP_SW_INTR_STAT);
-	status =  sw_intr_stat.bits.dsp0_to_host_intr_stat;
-	if (sof_ipc_dsp_status() || status) {
-		sw_intr_stat = (acp_dsp_sw_intr_stat_t)
-				io_reg_read(PU_REGISTER_BASE + ACP_DSP_SW_INTR_STAT);
-		status =  sw_intr_stat.bits.dsp0_to_host_intr_stat;
-		return -EBUSY;
-	}
-	lock = io_reg_read(PU_REGISTER_BASE + ACP_AXI2DAGB_SEM_0);
-	while (lock) {
-		lock = io_reg_read(PU_REGISTER_BASE + ACP_AXI2DAGB_SEM_0);
-		if (!delay_cnt)
-			return -EBUSY;
-
-		delay_cnt--;
-	}
-
-	/* Write new message in the mailbox */
-	mailbox_dspbox_write(0, msg->tx_data, msg->tx_size);
-
-	/* Need to set DSP message flag */
-	sof_ipc_dsp_msg_set();
-	/* now interrupt host to tell it we have sent a message */
-	acp_dsp_to_host_intr_trig();
-	/* Disable the trigger bit in ACP_DSP_SW_INTR_TRIG register */
-	sw_intr_trig = (acp_sw_intr_trig_t)io_reg_read(PU_REGISTER_BASE + ACP_SW_INTR_TRIG);
-	sw_intr_trig.bits.trig_dsp0_to_host_intr = INTERRUPT_DISABLE;
-	io_reg_write((PU_REGISTER_BASE + ACP_SW_INTR_TRIG), sw_intr_trig.u32all);
-	io_reg_write((PU_REGISTER_BASE + ACP_AXI2DAGB_SEM_0), lock);
-	return 0;
-}
-
-void ipc_platform_send_msg_direct(const struct ipc_msg *msg)
-{
-	/* TODO: add support */
-}
-
diff --git a/src/drivers/amd/vangogh/CMakeLists.txt b/src/drivers/amd/vangogh/CMakeLists.txt
deleted file mode 100644
index 24e80e3e76d7..000000000000
--- a/src/drivers/amd/vangogh/CMakeLists.txt
+++ /dev/null
@@ -1,13 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-
-add_local_sources(sof
-	acp_dma.c
-	acp_sp_dai.c
-	acp_hs_dai.c
-	interrupt.c
-	ipc.c
-	acp_bt_dma.c
-	acp_sp_dma.c
-	acp_hs_dma.c
-	acp_dmic_dma.c
-)
diff --git a/src/drivers/amd/vangogh/acp_bt_dma.c b/src/drivers/amd/vangogh/acp_bt_dma.c
deleted file mode 100644
index 9b0f496fc4da..000000000000
--- a/src/drivers/amd/vangogh/acp_bt_dma.c
+++ /dev/null
@@ -1,443 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-//
-//Copyright(c) 2023 AMD. All rights reserved.
-//
-//Author:	Basavaraj Hiregoudar <basavaraj.hiregoudar@amd.com>
-//		SaiSurya, Ch <saisurya.chakkaveeravenkatanaga@amd.com>
-
-#include <rtos/atomic.h>
-#include <sof/audio/component.h>
-#include <rtos/bit.h>
-#include <sof/drivers/acp_dai_dma.h>
-#include <rtos/interrupt.h>
-#include <rtos/timer.h>
-#include <rtos/alloc.h>
-#include <rtos/clk.h>
-#include <sof/lib/cpu.h>
-#include <sof/lib/dma.h>
-#include <sof/lib/io.h>
-#include <sof/lib/pm_runtime.h>
-#include <sof/lib/notifier.h>
-#include <sof/platform.h>
-#include <sof/schedule/schedule.h>
-#include <rtos/spinlock.h>
-#include <sof/math/numbers.h>
-#include <sof/trace/trace.h>
-#include <ipc/topology.h>
-#include <user/trace.h>
-#include <errno.h>
-#include <stdbool.h>
-#include <stddef.h>
-#include <stdint.h>
-#include <platform/fw_scratch_mem.h>
-#include <platform/chip_registers.h>
-
-SOF_DEFINE_REG_UUID(acp_bt_dma);
-
-/* unused with Zephyr, generates no output */
-DECLARE_TR_CTX(acp_bt_dma_tr, SOF_UUID(acp_bt_dma_uuid), LOG_LEVEL_INFO);
-
-/* DMA number of buffer periods */
-#define BT_FIFO_SIZE		768
-
-/* ACP DMA transfer size */
-#define ACP_BT_DMA_TRANS_SIZE	128
-#define BT_IER_DISABLE		0x0
-/* Vangogh hw specific addr map */
-#define ACP_DRAM_PHY_TRNS       0x0DEB0000
-
-static uint64_t prev_tx_pos;
-static uint64_t prev_rx_pos;
-static uint32_t bt_buff_size;
-
-/* Allocate requested DMA channel if it is free */
-static struct dma_chan_data *acp_dai_bt_dma_channel_get(struct dma *dma,
-							unsigned int req_chan)
-{
-	k_spinlock_key_t key;
-	struct dma_chan_data *channel;
-
-	key = k_spin_lock(&dma->lock);
-	if (req_chan >= dma->plat_data.channels) {
-		k_spin_unlock(&dma->lock, key);
-		tr_err(&acp_bt_dma_tr, "Channel %d not in range", req_chan);
-		return NULL;
-	}
-	channel = &dma->chan[req_chan];
-	if (channel->status != COMP_STATE_INIT) {
-		k_spin_unlock(&dma->lock, key);
-		tr_err(&acp_bt_dma_tr, "channel already in use %d", req_chan);
-		return NULL;
-	}
-	atomic_add(&dma->num_channels_busy, 1);
-	channel->status = COMP_STATE_READY;
-	k_spin_unlock(&dma->lock, key);
-
-	return channel;
-}
-
-/* channel must not be running when this is called */
-static void acp_dai_bt_dma_channel_put(struct dma_chan_data *channel)
-{
-	k_spinlock_key_t key;
-
-	notifier_unregister_all(NULL, channel);
-	key = k_spin_lock(&channel->dma->lock);
-	channel->status = COMP_STATE_INIT;
-	atomic_sub(&channel->dma->num_channels_busy, 1);
-	k_spin_unlock(&channel->dma->lock, key);
-}
-
-static int acp_dai_bt_dma_start(struct dma_chan_data *channel)
-{
-	acp_bttdm_ier_t         bt_ier;
-	acp_bttdm_iter_t        bt_tdm_iter;
-	acp_bttdm_irer_t        bt_tdm_irer;
-
-	bt_tdm_iter = (acp_bttdm_iter_t)io_reg_read((PU_REGISTER_BASE + ACP_BTTDM_ITER));
-	bt_tdm_irer = (acp_bttdm_irer_t)io_reg_read((PU_REGISTER_BASE + ACP_BTTDM_IRER));
-
-	if (!bt_tdm_iter.bits.bttdm_txen && !bt_tdm_irer.bits.bttdm_rx_en)
-		/* Request SMU to set aclk to 600 Mhz */
-		acp_change_clock_notify(600000000);
-
-	if (channel->direction == DMA_DIR_MEM_TO_DEV) {
-		channel->status = COMP_STATE_ACTIVE;
-		prev_tx_pos = 0;
-		bt_ier = (acp_bttdm_ier_t)io_reg_read(PU_REGISTER_BASE + ACP_BTTDM_IER);
-		bt_ier.bits.bttdm_ien = 1;
-		io_reg_write((PU_REGISTER_BASE + ACP_BTTDM_IER), bt_ier.u32all);
-		bt_tdm_iter.u32all = 0;
-		bt_tdm_iter.bits.bttdm_txen = 1;
-		bt_tdm_iter.bits.bttdm_tx_protocol_mode  = 0;
-		bt_tdm_iter.bits.bttdm_tx_data_path_mode = 1;
-		bt_tdm_iter.bits.bttdm_tx_samp_len = 2;
-		io_reg_write((PU_REGISTER_BASE + ACP_BTTDM_ITER), bt_tdm_iter.u32all);
-	} else if (channel->direction == DMA_DIR_DEV_TO_MEM) {
-		channel->status = COMP_STATE_ACTIVE;
-		prev_rx_pos = 0;
-		bt_ier = (acp_bttdm_ier_t)io_reg_read(PU_REGISTER_BASE + ACP_BTTDM_IER);
-		bt_ier.bits.bttdm_ien = 1;
-		io_reg_write((PU_REGISTER_BASE + ACP_BTTDM_IER), bt_ier.u32all);
-		bt_tdm_irer.u32all = 0;
-		bt_tdm_irer.bits.bttdm_rx_en = 1;
-		bt_tdm_irer.bits.bttdm_rx_protocol_mode  = 0;
-		bt_tdm_irer.bits.bttdm_rx_data_path_mode = 1;
-		bt_tdm_irer.bits.bttdm_rx_samplen = 2;
-		io_reg_write((PU_REGISTER_BASE + ACP_BTTDM_IRER), bt_tdm_irer.u32all);
-	} else {
-		tr_err(&acp_bt_dma_tr, "Start direction not defined %d", channel->direction);
-		return -EINVAL;
-	}
-	return 0;
-}
-
-static int acp_dai_bt_dma_release(struct dma_chan_data *channel)
-{
-	/* nothing to do on vangogh */
-	return 0;
-}
-
-static int acp_dai_bt_dma_pause(struct dma_chan_data *channel)
-{
-	/* nothing to do on vangogh */
-	return 0;
-}
-
-static int acp_dai_bt_dma_stop(struct dma_chan_data *channel)
-{
-	acp_bttdm_iter_t        bt_tdm_iter;
-	acp_bttdm_irer_t        bt_tdm_irer;
-
-	switch (channel->status) {
-	case COMP_STATE_READY:
-	case COMP_STATE_PREPARE:
-		return 0;
-	case COMP_STATE_PAUSED:
-	case COMP_STATE_ACTIVE:
-		break;
-	default:
-		return -EINVAL;
-	}
-	channel->status = COMP_STATE_READY;
-	if (channel->direction == DMA_DIR_MEM_TO_DEV) {
-		bt_tdm_iter = (acp_bttdm_iter_t)io_reg_read(PU_REGISTER_BASE + ACP_BTTDM_ITER);
-		bt_tdm_iter.bits.bttdm_txen = 0;
-		io_reg_write(PU_REGISTER_BASE + ACP_BTTDM_ITER, bt_tdm_iter.u32all);
-	} else if (channel->direction == DMA_DIR_DEV_TO_MEM) {
-		bt_tdm_irer = (acp_bttdm_irer_t)io_reg_read(PU_REGISTER_BASE + ACP_BTTDM_IRER);
-		bt_tdm_irer.bits.bttdm_rx_en = 0;
-		io_reg_write(PU_REGISTER_BASE + ACP_BTTDM_IRER, bt_tdm_irer.u32all);
-	} else {
-		tr_err(&acp_bt_dma_tr, "direction not defined %d", channel->direction);
-		return -EINVAL;
-	}
-
-	bt_tdm_iter = (acp_bttdm_iter_t)io_reg_read(PU_REGISTER_BASE + ACP_BTTDM_ITER);
-	bt_tdm_irer = (acp_bttdm_irer_t)io_reg_read(PU_REGISTER_BASE + ACP_BTTDM_IRER);
-	if (!bt_tdm_iter.bits.bttdm_txen && !bt_tdm_irer.bits.bttdm_rx_en) {
-		io_reg_write((PU_REGISTER_BASE + ACP_BTTDM_IER), BT_IER_DISABLE);
-		/* Request SMU to scale down aclk to minimum clk */
-		acp_change_clock_notify(0);
-	}
-
-	return 0;
-}
-
-/* fill in "status" with current DMA channel state and position */
-static int acp_dai_bt_dma_status(struct dma_chan_data *channel,
-				 struct dma_chan_status *status,
-				 uint8_t direction)
-{
-	/* nothing to do on vangogh */
-	return 0;
-}
-
-/* set the DMA channel configuration
- * source/target address
- * DMA transfer sizes
- */
-static int acp_dai_bt_dma_set_config(struct dma_chan_data *channel,
-				     struct dma_sg_config *config)
-{
-	uint32_t bt_ringbuff_addr;
-	uint32_t bt_fifo_addr;
-
-	if (!config->cyclic) {
-		tr_err(&acp_bt_dma_tr, "cyclic configurations only supported");
-		return -EINVAL;
-	}
-	if (config->scatter) {
-		tr_err(&acp_bt_dma_tr, "scatter enabled, that is not supported for now");
-		return -EINVAL;
-	}
-
-	volatile acp_scratch_mem_config_t *pscratch_mem_cfg =
-		(volatile acp_scratch_mem_config_t *)(PU_REGISTER_BASE + SCRATCH_REG_OFFSET);
-	channel->is_scheduling_source = true;
-	channel->direction = config->direction;
-	bt_buff_size = config->elem_array.elems[0].size * config->elem_array.count;
-
-	switch (config->direction) {
-	case DMA_DIR_MEM_TO_DEV:
-
-		/* BT Transmit FIFO Address and FIFO Size */
-		bt_fifo_addr = (uint32_t)(&pscratch_mem_cfg->acp_transmit_fifo_buffer);
-		bt_fifo_addr = (bt_fifo_addr & ACP_DRAM_ADDRESS_MASK);
-		bt_fifo_addr = (bt_fifo_addr - ACP_DRAM_PHY_TRNS);
-		io_reg_write((PU_REGISTER_BASE + ACP_BT_TX_FIFOADDR), bt_fifo_addr);
-		io_reg_write((PU_REGISTER_BASE + ACP_BT_TX_FIFOSIZE), (uint32_t)(BT_FIFO_SIZE));
-
-		/* Transmit RINGBUFFER Address and size */
-		config->elem_array.elems[0].src =
-			(config->elem_array.elems[0].src & ACP_DRAM_ADDRESS_MASK);
-		bt_ringbuff_addr = (config->elem_array.elems[0].src | 0x01000000);
-		io_reg_write((PU_REGISTER_BASE + ACP_BT_TX_RINGBUFADDR), bt_ringbuff_addr);
-		io_reg_write((PU_REGISTER_BASE + ACP_BT_TX_RINGBUFSIZE), bt_buff_size);
-
-		/* Transmit DMA transfer size in bytes */
-		io_reg_write((PU_REGISTER_BASE + ACP_BT_TX_DMA_SIZE),
-			     (uint32_t)(ACP_DMA_TRANS_SIZE_128));
-		/* Watermark size for BT transfer fifo */
-		io_reg_write((PU_REGISTER_BASE + ACP_BT_TX_INTR_WATERMARK_SIZE),
-			     (bt_buff_size >> 1));
-		break;
-	case DMA_DIR_DEV_TO_MEM:
-
-		/* BT Receive FIFO Address and FIFO Size*/
-		bt_fifo_addr = (uint32_t)(&pscratch_mem_cfg->acp_receive_fifo_buffer);
-		bt_fifo_addr = (bt_fifo_addr & ACP_DRAM_ADDRESS_MASK);
-		bt_fifo_addr = (bt_fifo_addr - ACP_DRAM_PHY_TRNS);
-		io_reg_write((PU_REGISTER_BASE + ACP_BT_RX_FIFOADDR), bt_fifo_addr);
-		io_reg_write((PU_REGISTER_BASE + ACP_BT_RX_FIFOSIZE), (uint32_t)(BT_FIFO_SIZE));
-
-		/* Receive RINGBUFFER Address and size */
-		config->elem_array.elems[0].dest =
-			(config->elem_array.elems[0].dest & ACP_DRAM_ADDRESS_MASK);
-		bt_ringbuff_addr = (config->elem_array.elems[0].dest | 0x01000000);
-		io_reg_write((PU_REGISTER_BASE + ACP_BT_RX_RINGBUFADDR), bt_ringbuff_addr);
-		io_reg_write((PU_REGISTER_BASE + ACP_BT_RX_RINGBUFSIZE), bt_buff_size);
-
-		/* Receive DMA transfer size in bytes */
-		io_reg_write((PU_REGISTER_BASE + ACP_BT_RX_DMA_SIZE),
-			     (uint32_t)(ACP_DMA_TRANS_SIZE_128));
-		/* Watermark size for BT receive fifo */
-		io_reg_write((PU_REGISTER_BASE + ACP_BT_RX_INTR_WATERMARK_SIZE),
-			     (bt_buff_size >> 1));
-		break;
-	default:
-		tr_err(&acp_bt_dma_tr, "unsupported config direction");
-		return -EINVAL;
-	}
-
-	return 0;
-}
-
-static int acp_dai_bt_dma_copy(struct dma_chan_data *channel, int bytes,
-			       uint32_t flags)
-{
-	struct dma_cb_data next = {
-		.channel = channel,
-		.elem.size = bytes,
-	};
-	notifier_event(channel, NOTIFIER_ID_DMA_COPY,
-		       NOTIFIER_TARGET_CORE_LOCAL, &next, sizeof(next));
-	return 0;
-}
-
-static int acp_dai_bt_dma_probe(struct dma *dma)
-{
-	int channel;
-
-	if (dma->chan) {
-		tr_err(&acp_bt_dma_tr, "Repeated probe");
-		return -EEXIST;
-	}
-	dma->chan = rzalloc(SOF_MEM_FLAG_KERNEL,
-			    dma->plat_data.channels *
-			    sizeof(struct dma_chan_data));
-	if (!dma->chan) {
-		tr_err(&acp_bt_dma_tr, "Probe failure, unable to allocate channel descriptors");
-		return -ENOMEM;
-	}
-	for (channel = 0; channel < dma->plat_data.channels; channel++) {
-		dma->chan[channel].dma = dma;
-		dma->chan[channel].index = channel;
-		dma->chan[channel].status = COMP_STATE_INIT;
-	}
-	atomic_init(&dma->num_channels_busy, 0);
-	return 0;
-}
-
-static int acp_dai_bt_dma_remove(struct dma *dma)
-{
-	if (!dma->chan) {
-		tr_err(&acp_bt_dma_tr, "remove called without probe, it's a no-op");
-		return 0;
-	}
-
-	rfree(dma->chan);
-	dma->chan = NULL;
-	return 0;
-}
-
-static int acp_dai_bt_dma_get_data_size(struct dma_chan_data *channel,
-					uint32_t *avail, uint32_t *free)
-{
-	if (channel->direction == DMA_DIR_MEM_TO_DEV) {
-#if CONFIG_DISABLE_DESCRIPTOR_SPLIT
-		uint64_t tx_low, curr_tx_pos, tx_high;
-		tx_low = (uint32_t)io_reg_read(PU_REGISTER_BASE +
-				ACP_BT_TX_LINEARPOSITIONCNTR_LOW);
-		tx_high = (uint32_t)io_reg_read(PU_REGISTER_BASE +
-				ACP_BT_TX_LINEARPOSITIONCNTR_HIGH);
-		curr_tx_pos = (uint64_t)((tx_high << 32) | tx_low);
-		*free = (curr_tx_pos - prev_tx_pos) > bt_buff_size ?
-			(curr_tx_pos - prev_tx_pos) % bt_buff_size :
-			(curr_tx_pos - prev_tx_pos);
-		*avail = bt_buff_size - *free;
-		prev_tx_pos = curr_tx_pos;
-#else
-		*free = bt_buff_size >> 1;
-		*avail = bt_buff_size >> 1;
-#endif
-	} else if (channel->direction == DMA_DIR_DEV_TO_MEM) {
-#if CONFIG_DISABLE_DESCRIPTOR_SPLIT
-		uint64_t rx_low, curr_rx_pos, rx_high;
-		rx_low = (uint32_t)io_reg_read(PU_REGISTER_BASE +
-				ACP_BT_RX_LINEARPOSITIONCNTR_LOW);
-		rx_high = (uint32_t)io_reg_read(PU_REGISTER_BASE +
-				ACP_BT_RX_LINEARPOSITIONCNTR_HIGH);
-		curr_rx_pos = (uint64_t)((rx_high << 32) | rx_low);
-		*free = (curr_rx_pos - prev_rx_pos) > bt_buff_size ?
-			(curr_rx_pos - prev_rx_pos) % bt_buff_size :
-			(curr_rx_pos - prev_rx_pos);
-		*avail = bt_buff_size - *free;
-		prev_rx_pos = curr_rx_pos;
-#else
-		*free = bt_buff_size >> 1;
-		*avail = bt_buff_size >> 1;
-#endif
-	} else {
-		tr_err(&acp_bt_dma_tr, "Channel direction Not defined %d",
-		       channel->direction);
-		return -EINVAL;
-	}
-	return 0;
-}
-
-static int acp_dai_bt_dma_get_attribute(struct dma *dma, uint32_t type, uint32_t *value)
-{
-	switch (type) {
-	case DMA_ATTR_BUFFER_ALIGNMENT:
-	case DMA_ATTR_COPY_ALIGNMENT:
-		*value = ACP_DMA_BUFFER_ALIGN_128;
-		break;
-	case DMA_ATTR_BUFFER_ADDRESS_ALIGNMENT:
-		*value = PLATFORM_DCACHE_ALIGN;
-		break;
-	case DMA_ATTR_BUFFER_PERIOD_COUNT:
-		*value = ACP_DAI_DMA_BUFFER_PERIOD_COUNT;
-		break;
-	default:
-		return -ENOENT; /* Attribute not found */
-	}
-	return 0;
-}
-
-static int acp_dai_bt_dma_interrupt(struct dma_chan_data *channel, enum dma_irq_cmd cmd)
-{
-	uint32_t status;
-	acp_dsp0_intr_stat_t acp_intr_stat;
-	acp_dsp0_intr_cntl_t acp_intr_cntl;
-
-	if (channel->status == COMP_STATE_INIT)
-		return 0;
-
-	switch (cmd) {
-	case DMA_IRQ_STATUS_GET:
-		acp_intr_stat =  (acp_dsp0_intr_stat_t)
-			(dma_reg_read(channel->dma, ACP_DSP0_INTR_STAT));
-		status = acp_intr_stat.bits.audio_buffer_int_stat;
-		return (status & (1 << channel->index));
-	case DMA_IRQ_CLEAR:
-		acp_intr_stat.u32all = 0;
-		acp_intr_stat.bits.audio_buffer_int_stat = (1 << channel->index);
-		status  = acp_intr_stat.u32all;
-		dma_reg_write(channel->dma, ACP_DSP0_INTR_STAT, status);
-		return 0;
-	case DMA_IRQ_MASK:
-		acp_intr_cntl =  (acp_dsp0_intr_cntl_t)
-				dma_reg_read(channel->dma, ACP_DSP0_INTR_CNTL);
-		acp_intr_cntl.bits.audio_buffer_int_mask &= (~(1 << channel->index));
-		status  = acp_intr_cntl.u32all;
-		dma_reg_write(channel->dma, ACP_DSP0_INTR_CNTL, status);
-		return 0;
-	case DMA_IRQ_UNMASK:
-		acp_intr_cntl =  (acp_dsp0_intr_cntl_t)
-				dma_reg_read(channel->dma, ACP_DSP0_INTR_CNTL);
-		acp_intr_cntl.bits.audio_buffer_int_mask  |=  (1 << channel->index);
-		status = acp_intr_cntl.u32all;
-		dma_reg_write(channel->dma, ACP_DSP0_INTR_CNTL, status);
-		return 0;
-	default:
-		return -EINVAL;
-	}
-}
-
-const struct dma_ops acp_dai_bt_dma_ops = {
-	.channel_get		= acp_dai_bt_dma_channel_get,
-	.channel_put		= acp_dai_bt_dma_channel_put,
-	.start			= acp_dai_bt_dma_start,
-	.stop			= acp_dai_bt_dma_stop,
-	.pause			= acp_dai_bt_dma_pause,
-	.release		= acp_dai_bt_dma_release,
-	.copy			= acp_dai_bt_dma_copy,
-	.status			= acp_dai_bt_dma_status,
-	.set_config		= acp_dai_bt_dma_set_config,
-	.interrupt		= acp_dai_bt_dma_interrupt,
-	.probe			= acp_dai_bt_dma_probe,
-	.remove			= acp_dai_bt_dma_remove,
-	.get_data_size		= acp_dai_bt_dma_get_data_size,
-	.get_attribute		= acp_dai_bt_dma_get_attribute,
-};
diff --git a/src/drivers/amd/vangogh/acp_dma.c b/src/drivers/amd/vangogh/acp_dma.c
deleted file mode 100644
index 853460d289c8..000000000000
--- a/src/drivers/amd/vangogh/acp_dma.c
+++ /dev/null
@@ -1,290 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-//
-//Copyright(c) 2023 AMD. All rights reserved.
-//
-//Author:       Basavaraj Hiregoudar <basavaraj.hiregoudar@amd.com>
-//              SaiSurya, Ch <saisurya.chakkaveeravenkatanaga@amd.com>
-
-#include <sof/audio/component.h>
-#include <platform/chip_registers.h>
-#include <platform/fw_scratch_mem.h>
-#include <platform/chip_offset_byte.h>
-#include <sof/drivers/acp_dai_dma.h>
-#include <rtos/timer.h>
-#include <rtos/alloc.h>
-#include <sof/lib/dma.h>
-#include <sof/lib/io.h>
-#include <sof/lib/notifier.h>
-#include <sof/lib/uuid.h>
-#include <sof/math/numbers.h>
-#include <sof/platform.h>
-#include <errno.h>
-#include <stddef.h>
-#include <stdint.h>
-#include <platform/acp_dma.h>
-
-void amd_dma_reconfig(struct dma_chan_data *channel, uint32_t bytes)
-{
-	uint32_t strt_idx = 0;
-	uint32_t src;
-	uint32_t dest;
-	uint32_t tail, head;
-	uint32_t src1;
-	uint32_t dest1;
-
-	acp_cfg_dma_descriptor_t psrc_dscr[ACP_MAX_STREAMS];
-	acp_cfg_dma_descriptor_t *pdest_dscr;
-	acp_dma_cntl_0_t dma_cntl;
-	struct acp_dma_chan_data *acp_dma_chan;
-	struct acp_dma_config *dma_cfg;
-
-	volatile acp_scratch_mem_config_t *pscratch_mem_cfg =
-		(volatile acp_scratch_mem_config_t *)(PU_SCRATCH_REG_BASE + SCRATCH_REG_OFFSET);
-	acp_dma_chan = dma_chan_get_data(channel);
-	dma_cfg = &acp_dma_chan->config[channel->index];
-	pdest_dscr = (acp_cfg_dma_descriptor_t *)(pscratch_mem_cfg->acp_cfg_dma_descriptor);
-	if (channel->direction == DMA_DIR_HMEM_TO_LMEM) {
-		head = bytes;
-		/* Update the read and write pointers */
-		dma_cfg->rd_ptr =  ACP_SYST_MEM_WINDOW + dma_cfg->phy_off + dma_cfg->rd_size;
-		dma_cfg->wr_ptr = dma_cfg->base + dma_cfg->wr_size;
-		src = dma_cfg->rd_ptr;
-		dest = dma_cfg->wr_ptr;
-		psrc_dscr[strt_idx].src_addr  = src;
-		dest = (dest & ACP_DRAM_ADDRESS_MASK);
-		psrc_dscr[strt_idx].dest_addr = (dest | ACP_DRAM_ADDR_TRNS);
-		psrc_dscr[strt_idx].trns_cnt.bits.trns_cnt = bytes;
-		/* Configure a single descrption */
-		dma_config_descriptor(strt_idx, 1, psrc_dscr, pdest_dscr);
-		dma_chan_reg_write(channel, ACP_DMA_DSCR_CNT_0, 1);
-		/* Check for wrap-around case for system  buffer */
-		if (dma_cfg->rd_size + bytes > dma_cfg->sys_buff_size) {
-			/* Configure the descriptor  for head and tail */
-			/* values for the wrap around case */
-			tail = dma_cfg->sys_buff_size - dma_cfg->rd_size;
-			head = bytes - tail;
-			psrc_dscr[strt_idx].trns_cnt.bits.trns_cnt = tail;
-			psrc_dscr[strt_idx + 1].src_addr = ACP_SYST_MEM_WINDOW + dma_cfg->phy_off;
-			dest1 = dest + tail;
-			dest1 = (dest1 & ACP_DRAM_ADDRESS_MASK);
-			psrc_dscr[strt_idx + 1].dest_addr = (dest1 | ACP_DRAM_ADDR_TRNS);
-			psrc_dscr[strt_idx + 1].trns_cnt.bits.trns_cnt = head;
-			dma_config_descriptor(strt_idx, 2, psrc_dscr, pdest_dscr);
-			dma_chan_reg_write(channel, ACP_DMA_DSCR_CNT_0, 2);
-			dma_cfg->rd_size = 0;
-		}
-		/* Check for wrap-around case for host buffer */
-		if (dma_cfg->wr_size + bytes > dma_cfg->size) {
-			tail = dma_cfg->size - dma_cfg->wr_size;
-			head = bytes - tail;
-
-			psrc_dscr[strt_idx].trns_cnt.bits.trns_cnt = tail;
-			psrc_dscr[strt_idx + 1].trns_cnt.bits.trns_cnt = head;
-
-			/* start from "0" like starting address of buffer */
-			psrc_dscr[strt_idx + 1].dest_addr =
-				((dma_cfg->base & ACP_DRAM_ADDRESS_MASK) | ACP_DRAM_ADDR_TRNS);
-
-			src1 = src + tail;
-			psrc_dscr[strt_idx + 1].src_addr  = src1;
-
-			dma_config_descriptor(strt_idx, 2, psrc_dscr, pdest_dscr);
-			dma_chan_reg_write(channel, ACP_DMA_DSCR_CNT_0, 2);
-			dma_cfg->wr_size = 0;
-		}
-
-		dma_cfg->rd_size += head;
-		dma_cfg->rd_size %= dma_cfg->sys_buff_size;
-		dma_cfg->wr_size += bytes;
-		dma_cfg->wr_size %= dma_cfg->size;
-	} else if (channel->direction == DMA_DIR_LMEM_TO_HMEM)	{
-		head = bytes;
-		dma_cfg->wr_ptr = ACP_SYST_MEM_WINDOW + dma_cfg->phy_off + dma_cfg->wr_size;
-		dma_cfg->rd_ptr =  dma_cfg->base + dma_cfg->rd_size;
-		src = dma_cfg->rd_ptr;
-		dest = dma_cfg->wr_ptr;
-		src = (src & ACP_DRAM_ADDRESS_MASK);
-		psrc_dscr[strt_idx].src_addr = (src | ACP_DRAM_ADDR_TRNS);
-		psrc_dscr[strt_idx].dest_addr = dest;
-		psrc_dscr[strt_idx].trns_cnt.bits.trns_cnt = bytes;
-		/* Configure a single descrption */
-		dma_config_descriptor(strt_idx, 1, psrc_dscr, pdest_dscr);
-		dma_chan_reg_write(channel, ACP_DMA_DSCR_CNT_0, 1);
-		/* Check for wrap-around case for system  buffer */
-		if (dma_cfg->wr_size + bytes > dma_cfg->sys_buff_size) {
-			/* Configure the descriptor  for head and
-			 * tail values for the wrap around case
-			 */
-			tail = dma_cfg->sys_buff_size - dma_cfg->wr_size;
-			head = bytes - tail;
-			psrc_dscr[strt_idx].trns_cnt.bits.trns_cnt = tail;
-			src1 = src + tail;
-			psrc_dscr[strt_idx + 1].dest_addr = ACP_SYST_MEM_WINDOW + dma_cfg->phy_off;
-			psrc_dscr[strt_idx + 1].trns_cnt.bits.trns_cnt = head;
-			src1 = (src1 & ACP_DRAM_ADDRESS_MASK);
-			psrc_dscr[strt_idx + 1].src_addr = (src1 | ACP_DRAM_ADDR_TRNS);
-			dma_config_descriptor(strt_idx, 2, psrc_dscr, pdest_dscr);
-			dma_chan_reg_write(channel, ACP_DMA_DSCR_CNT_0, 2);
-			dma_cfg->wr_size  = 0;
-		}
-		dma_cfg->wr_size  += head;
-		dma_cfg->wr_size  %= dma_cfg->sys_buff_size;
-		dma_cfg->rd_size  += bytes;
-		dma_cfg->rd_size  %= dma_cfg->size;
-	}
-	/* clear the dma channel control bits */
-	dma_cntl = (acp_dma_cntl_0_t)dma_chan_reg_read(channel, ACP_DMA_CNTL_0);
-	dma_cntl.bits.dmachrun = 0;
-	dma_chan_reg_write(channel, ACP_DMA_CNTL_0, dma_cntl.u32all);
-	/* Load start index of decriptor and priority */
-	dma_chan_reg_write(channel, ACP_DMA_DSCR_STRT_IDX_0, strt_idx);
-	dma_chan_reg_write(channel, ACP_DMA_PRIO_0, 1);
-	channel->status = COMP_STATE_PREPARE;
-}
-
-/* Some set_config helper functions */
-int dma_setup(struct dma_chan_data *channel,
-	      struct dma_sg_elem_array *sgelems, uint32_t dir)
-{
-	uint32_t dscr_cnt, dscr;
-	uint32_t tc;
-	uint16_t dscr_strt_idx;
-	uint32_t *phy_off;
-	uint32_t *syst_buff_size;
-	uint32_t src;
-	uint32_t dest;
-	uint32_t buff_size = 0;
-	acp_dma_cntl_0_t    dma_cntl;
-	struct acp_dma_config *dma_cfg;
-	struct acp_dma_chan_data *acp_dma_chan = dma_chan_get_data(channel);
-
-	volatile acp_scratch_mem_config_t *pscratch_mem_cfg =
-		(volatile acp_scratch_mem_config_t *)(PU_SCRATCH_REG_BASE + SCRATCH_REG_OFFSET);
-	dscr_cnt = sgelems->count;
-	/* Trace uses descriptor from index seven */
-	/* and other streams use descriptors from zero */
-	if (channel->index == DMA_TRACE_CHANNEL)
-		dscr_strt_idx = DMA_TRACE_CHANNEL;
-	else
-		dscr_strt_idx = 0;
-
-	/* ACP DMA Descriptor in scratch memory */
-	acp_cfg_dma_descriptor_t *dma_config_dscr;
-
-	dma_config_dscr  = (acp_cfg_dma_descriptor_t *)(pscratch_mem_cfg->acp_cfg_dma_descriptor);
-	/* physical offset of system memory */
-	phy_off = (uint32_t *)(pscratch_mem_cfg->phy_offset);
-	/* size of system memory buffer */
-	syst_buff_size = (uint32_t *)(pscratch_mem_cfg->syst_buff_size);
-	for (dscr = 0; dscr < dscr_cnt; dscr++) {
-		if (dir == DMA_DIR_HMEM_TO_LMEM) {
-			if (channel->index != DMA_TRACE_CHANNEL) {
-				dma_config_dscr[dscr_strt_idx + dscr].src_addr =
-					(phy_off[channel->index] + ACP_SYST_MEM_WINDOW + buff_size);
-			} else {
-				dma_config_dscr[dscr_strt_idx + dscr].src_addr =
-					sgelems->elems[dscr].src + ACP_SYST_MEM_WINDOW;
-			}
-			dest = sgelems->elems[dscr].dest;
-			dest = (dest & ACP_DRAM_ADDRESS_MASK);
-			dma_config_dscr[dscr_strt_idx + dscr].dest_addr =
-				(dest | ACP_DRAM_ADDR_TRNS);
-			dma_config_dscr[dscr_strt_idx + dscr].trns_cnt.u32all = 0;
-			dma_config_dscr[dscr_strt_idx + dscr].trns_cnt.bits.trns_cnt =
-					sgelems->elems[dscr].size;
-		} else {
-			if (channel->index != DMA_TRACE_CHANNEL)
-				dma_config_dscr[dscr_strt_idx + dscr].dest_addr =
-					(phy_off[channel->index] + ACP_SYST_MEM_WINDOW + buff_size);
-			else
-				dma_config_dscr[dscr_strt_idx + dscr].dest_addr =
-					(sgelems->elems[dscr].dest + ACP_SYST_MEM_WINDOW);
-			src = sgelems->elems[dscr].src;
-			src = (src & ACP_DRAM_ADDRESS_MASK);
-			dma_config_dscr[dscr_strt_idx + dscr].src_addr = (src | ACP_DRAM_ADDR_TRNS);
-			dma_config_dscr[dscr_strt_idx + dscr].trns_cnt.u32all = 0;
-			dma_config_dscr[dscr_strt_idx + dscr].trns_cnt.bits.trns_cnt =
-					sgelems->elems[dscr].size;
-		}
-		dma_config_dscr[dscr_strt_idx + dscr].trns_cnt.u32all = 0;
-		dma_config_dscr[dscr_strt_idx + dscr].trns_cnt.bits.trns_cnt =
-					sgelems->elems[dscr].size;
-		buff_size = sgelems->elems[dscr].size;
-	}
-	dma_config_dscr[dscr_strt_idx + (dscr - 1)].trns_cnt.bits.ioc = 0;
-	dma_cfg = &acp_dma_chan->config[channel->index];
-	/* bytes of data to be transferred for the dma */
-	tc = dma_config_dscr[dscr_strt_idx].trns_cnt.bits.trns_cnt;
-	/* DMA configuration for stream */
-	if (channel->index != DMA_TRACE_CHANNEL) {
-		if (!dma_cfg->size) {
-			acp_dma_chan->dir = dir;
-			acp_dma_chan->idx = channel->index;
-			dma_cfg->phy_off =  phy_off[channel->index];
-			dma_cfg->size =  tc * dscr_cnt;
-			dma_cfg->sys_buff_size = syst_buff_size[channel->index];
-
-			if (dir == DMA_DIR_HMEM_TO_LMEM) {
-				/* Playback */
-				dma_config_dscr[dscr_strt_idx].dest_addr =
-					(dma_config_dscr[dscr_strt_idx].dest_addr &
-					 ACP_DRAM_ADDRESS_MASK);
-				dma_cfg->base  =
-					dma_config_dscr[dscr_strt_idx].dest_addr |
-					ACP_DRAM_ADDR_TRNS;
-				dma_cfg->wr_size = 0;
-				dma_cfg->rd_size = dma_cfg->size;
-			} else {
-				/* Capture */
-				dma_config_dscr[dscr_strt_idx].src_addr =
-					(dma_config_dscr[dscr_strt_idx].src_addr &
-					 ACP_DRAM_ADDRESS_MASK);
-				dma_cfg->base =
-					dma_config_dscr[dscr_strt_idx].src_addr |
-					ACP_DRAM_ADDR_TRNS;
-				dma_cfg->rd_size = 0;
-				if (channel->index == dma_cfg->probe_channel)
-					dma_cfg->wr_size = 0;
-				else
-					dma_cfg->wr_size = dma_cfg->size;
-			}
-		}
-	}
-	/* clear the dma channel control bits */
-	dma_cntl = (acp_dma_cntl_0_t)dma_chan_reg_read(channel, ACP_DMA_CNTL_0);
-	dma_cntl.bits.dmachrun = 0;
-	dma_cntl.bits.dmachiocen = 0;
-	dma_chan_reg_write(channel, ACP_DMA_CNTL_0, dma_cntl.u32all);
-
-	/* Program DMAChDscrStrIdx to the index
-	 * number of the first descriptor to be processed.
-	 */
-	dma_chan_reg_write(channel, ACP_DMA_DSCR_STRT_IDX_0, dscr_strt_idx);
-	/* program DMAChDscrdscrcnt to the
-	 * number of descriptors to be processed in the transfer
-	 */
-	dma_chan_reg_write(channel, ACP_DMA_DSCR_CNT_0, dscr_cnt);
-	/* set DMAChPrioLvl according to the priority */
-	dma_chan_reg_write(channel, ACP_DMA_PRIO_0, 1);
-	channel->status = COMP_STATE_PREPARE;
-	return 0;
-}
-
-int acp_dma_get_attribute(struct dma *dma, uint32_t type, uint32_t *value)
-{
-	switch (type) {
-	case DMA_ATTR_BUFFER_ALIGNMENT:
-	case DMA_ATTR_COPY_ALIGNMENT:
-		*value = ACP_DMA_BUFFER_ALIGN;
-		break;
-	case DMA_ATTR_BUFFER_ADDRESS_ALIGNMENT:
-		*value = PLATFORM_DCACHE_ALIGN;
-		break;
-	case DMA_ATTR_BUFFER_PERIOD_COUNT:
-		*value = ACP_DMA_BUFFER_PERIOD_COUNT;
-		break;
-	default:
-		return -ENOENT; /* Attribute not found */
-	}
-	return 0;
-}
diff --git a/src/drivers/amd/vangogh/acp_dmic_dma.c b/src/drivers/amd/vangogh/acp_dmic_dma.c
deleted file mode 100644
index bff340d88946..000000000000
--- a/src/drivers/amd/vangogh/acp_dmic_dma.c
+++ /dev/null
@@ -1,219 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-//
-//Copyright(c) 2023 AMD. All rights reserved.
-//
-//Author:	Basavaraj Hiregoudar <basavaraj.hiregoudar@amd.com>
-//		SaiSurya, Ch <saisurya.chakkaveeravenkatanaga@amd.com>
-
-#include <rtos/atomic.h>
-#include <sof/audio/component.h>
-#include <rtos/bit.h>
-#include <sof/drivers/acp_dai_dma.h>
-#include <rtos/interrupt.h>
-#include <rtos/timer.h>
-#include <rtos/alloc.h>
-#include <rtos/clk.h>
-#include <sof/lib/cpu.h>
-#include <sof/lib/dma.h>
-#include <sof/lib/io.h>
-#include <sof/lib/pm_runtime.h>
-#include <sof/lib/notifier.h>
-#include <sof/platform.h>
-#include <sof/schedule/schedule.h>
-#include <rtos/spinlock.h>
-#include <sof/math/numbers.h>
-#include <sof/trace/trace.h>
-#include <ipc/topology.h>
-#include <user/trace.h>
-#include <errno.h>
-#include <stdbool.h>
-#include <stddef.h>
-#include <stdint.h>
-#include <platform/fw_scratch_mem.h>
-#include <platform/chip_registers.h>
-#include <platform/acp_dmic_dma.h>
-
-SOF_DEFINE_REG_UUID(acp_dmic_dma);
-/* unused with Zephyr, generates no output */
-DECLARE_TR_CTX(acp_dmic_dma_vgh_tr, SOF_UUID(acp_dmic_dma_uuid), LOG_LEVEL_INFO);
-
-uint32_t dmic_rngbuff_size;
-
-int acp_dmic_dma_start(struct dma_chan_data *channel)
-{
-	acp_wov_pdm_no_of_channels_t pdm_channels;
-	acp_wov_pdm_decimation_factor_t deci_fctr;
-	acp_wov_misc_ctrl_t wov_misc_ctrl;
-	acp_wov_pdm_dma_enable_t  pdm_dma_enable;
-	acp_hstdm_iter_t        hs_iter;
-	acp_hstdm_irer_t        hs_irer;
-	uint32_t                acp_pdm_en;
-
-	struct timer *timer = timer_get();
-	uint64_t deadline = platform_timer_get(timer) +
-			    clock_ms_to_ticks(PLATFORM_DEFAULT_CLOCK, 1) * 500 / 1000;
-	 hs_iter = (acp_hstdm_iter_t)io_reg_read((PU_REGISTER_BASE + ACP_HSTDM_ITER));
-	hs_irer = (acp_hstdm_irer_t)io_reg_read((PU_REGISTER_BASE + ACP_HSTDM_IRER));
-	acp_pdm_en = (uint32_t)io_reg_read(PU_REGISTER_BASE + ACP_WOV_PDM_ENABLE);
-
-	if (!hs_iter.bits.hstdm_txen && !hs_irer.bits.hstdm_rx_en && !acp_pdm_en) {
-		io_reg_write((PU_REGISTER_BASE + ACP_CLKMUX_SEL), ACP_ACLK_CLK_SEL);
-		/* Request SMU to set aclk to 600 Mhz */
-		acp_change_clock_notify(600000000);
-	}
-	channel->status = COMP_STATE_ACTIVE;
-	if (channel->direction == DMA_DIR_DEV_TO_MEM) {
-		/* Channel for DMIC */
-		pdm_channels.bits.pdm_no_of_channels = 0;
-		io_reg_write(PU_REGISTER_BASE + ACP_WOV_PDM_NO_OF_CHANNELS,
-			     pdm_channels.u32all);
-		/* Decimation Factor */
-		deci_fctr.u32all = 2;
-		io_reg_write(PU_REGISTER_BASE + ACP_WOV_PDM_DECIMATION_FACTOR,
-			     deci_fctr.u32all);
-		/* PDM Control */
-		wov_misc_ctrl = (acp_wov_misc_ctrl_t)
-				io_reg_read(PU_REGISTER_BASE + ACP_WOV_MISC_CTRL);
-		wov_misc_ctrl.u32all |= 0x10;
-		io_reg_write(PU_REGISTER_BASE + ACP_WOV_MISC_CTRL,
-			     wov_misc_ctrl.u32all);
-		/* PDM Enable */
-		io_reg_write(PU_REGISTER_BASE + ACP_WOV_PDM_ENABLE, 1);
-		/* PDM DMA Enable */
-		io_reg_write(PU_REGISTER_BASE + ACP_WOV_PDM_DMA_ENABLE, 1);
-		/* Check the PDM DMA Enable status bit */
-		pdm_dma_enable = (acp_wov_pdm_dma_enable_t)
-				 io_reg_read(PU_REGISTER_BASE + ACP_WOV_PDM_DMA_ENABLE);
-		while (!(uint32_t)pdm_dma_enable.bits.pdm_dma_en_status) {
-			if (deadline < platform_timer_get(timer)) {
-				/* safe check in case we've got preempted after read */
-				if ((uint32_t)pdm_dma_enable.bits.pdm_dma_en_status)
-					return 0;
-				tr_err(&acp_dmic_dma_vgh_tr, "timed out for dma start");
-				return -ETIME;
-			}
-			pdm_dma_enable = (acp_wov_pdm_dma_enable_t)
-					io_reg_read(PU_REGISTER_BASE + ACP_WOV_PDM_DMA_ENABLE);
-		}
-	}
-	return 0;
-}
-
-int acp_dmic_dma_stop(struct dma_chan_data *channel)
-{
-	acp_wov_pdm_dma_enable_t  pdm_dma_enable;
-	acp_hstdm_iter_t        hs_iter;
-	acp_hstdm_irer_t        hs_irer;
-	uint32_t acp_pdm_en;
-	struct timer *timer = timer_get();
-	uint64_t deadline = platform_timer_get(timer) +
-			clock_ms_to_ticks(PLATFORM_DEFAULT_CLOCK, 1) * 500 / 1000;
-
-	switch (channel->status) {
-	case COMP_STATE_READY:
-	case COMP_STATE_PREPARE:
-		return 0;
-	case COMP_STATE_PAUSED:
-	case COMP_STATE_ACTIVE:
-		break;
-	default:
-		return -EINVAL;
-	}
-	channel->status = COMP_STATE_READY;
-	/* Disable PDM DMA */
-	io_reg_write(PU_REGISTER_BASE + ACP_WOV_PDM_DMA_ENABLE, 0);
-	/* Disable PDM */
-	pdm_dma_enable = (acp_wov_pdm_dma_enable_t)
-		io_reg_read(PU_REGISTER_BASE + ACP_WOV_PDM_DMA_ENABLE);
-	/* Check PDM DMA Status */
-	while ((uint32_t)pdm_dma_enable.bits.pdm_dma_en_status) {
-		if (deadline < platform_timer_get(timer)) {
-			/* safe check in case we've got preempted after read */
-			if ((uint32_t)pdm_dma_enable.bits.pdm_dma_en_status)
-				return 0;
-			tr_err(&acp_dmic_dma_vgh_tr, "timed out for dma stop");
-			return -ETIME;
-		}
-		pdm_dma_enable = (acp_wov_pdm_dma_enable_t)
-			io_reg_read(PU_REGISTER_BASE + ACP_WOV_PDM_DMA_ENABLE);
-	}
-	/* Disable  PDM */
-	io_reg_write(PU_REGISTER_BASE + ACP_WOV_PDM_ENABLE, 0);
-	/* Clear PDM FIFO */
-	io_reg_write(PU_REGISTER_BASE + ACP_WOV_PDM_FIFO_FLUSH, 1);
-	hs_iter = (acp_hstdm_iter_t)io_reg_read((PU_REGISTER_BASE + ACP_HSTDM_ITER));
-	hs_irer = (acp_hstdm_irer_t)io_reg_read((PU_REGISTER_BASE + ACP_HSTDM_IRER));
-	acp_pdm_en = (uint32_t)io_reg_read(PU_REGISTER_BASE + ACP_WOV_PDM_ENABLE);
-
-	if (!hs_iter.bits.hstdm_txen && !hs_irer.bits.hstdm_rx_en && !acp_pdm_en) {
-		/* Request SMU to set aclk to minimum aclk */
-		acp_change_clock_notify(0);
-		io_reg_write((PU_REGISTER_BASE + ACP_CLKMUX_SEL), ACP_INTERNAL_CLK_SEL);
-	}
-
-	return 0;
-}
-
-/* set the DMA channel configuration, source/target address, buffer sizes */
-int acp_dmic_dma_set_config(struct dma_chan_data *channel,
-			    struct dma_sg_config *config)
-{
-	uint32_t ring_buff_addr;
-	acp_wov_rx_ringbufsize_t dmic_ringbuff_size;
-	acp_wov_rx_intr_watermark_size_t watermark;
-
-	channel->is_scheduling_source = true;
-	channel->direction = config->direction;
-	switch (config->direction) {
-	case DMA_DIR_DEV_TO_MEM:
-	case DMA_DIR_MEM_TO_DEV:
-		config->elem_array.elems[0].dest =
-			(config->elem_array.elems[0].dest & ACP_DRAM_ADDRESS_MASK);
-		ring_buff_addr = (config->elem_array.elems[0].dest | 0x01000000);
-		/* Load Ring buffer address */
-		io_reg_write(PU_REGISTER_BASE +
-			ACP_WOV_RX_RINGBUFADDR, ring_buff_addr);
-		/* Load Ring buffer Size */
-		dmic_rngbuff_size = (config->elem_array.elems[0].size *
-				config->elem_array.count);
-		dmic_ringbuff_size.bits.rx_ringbufsize = dmic_rngbuff_size;
-		io_reg_write(PU_REGISTER_BASE +
-			ACP_WOV_RX_RINGBUFSIZE, dmic_ringbuff_size.u32all);
-		/* Write the ring buffer size to register */
-		watermark.bits.rx_intr_watermark_size = (dmic_rngbuff_size >> 1);
-		io_reg_write(PU_REGISTER_BASE +
-			ACP_WOV_RX_INTR_WATERMARK_SIZE, watermark.u32all);
-		break;
-	default:
-		tr_err(&acp_dmic_dma_vgh_tr, "unsupported config direction");
-		return -EINVAL;
-	}
-	if (!config->cyclic) {
-		tr_err(&acp_dmic_dma_vgh_tr, "cyclic configurations only supported!");
-		return -EINVAL;
-	}
-	if (config->scatter) {
-		tr_err(&acp_dmic_dma_vgh_tr, "scatter enabled, not supported for now!");
-		return -EINVAL;
-	}
-	return 0;
-}
-
-int acp_dmic_dma_get_attribute(struct dma *dma, uint32_t type, uint32_t *value)
-{
-	switch (type) {
-	case DMA_ATTR_BUFFER_ALIGNMENT:
-	case DMA_ATTR_COPY_ALIGNMENT:
-		*value = ACP_DMA_BUFFER_ALIGN;
-		break;
-	case DMA_ATTR_BUFFER_ADDRESS_ALIGNMENT:
-		*value = PLATFORM_DCACHE_ALIGN;
-		break;
-	case DMA_ATTR_BUFFER_PERIOD_COUNT:
-		*value = ACP_DAI_DMA_BUFFER_PERIOD_COUNT;
-		break;
-	default:
-		return -ENOENT; /* Attribute not found */
-	}
-	return 0;
-}
diff --git a/src/drivers/amd/vangogh/acp_hs_dai.c b/src/drivers/amd/vangogh/acp_hs_dai.c
deleted file mode 100644
index c333e1a04d87..000000000000
--- a/src/drivers/amd/vangogh/acp_hs_dai.c
+++ /dev/null
@@ -1,100 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-//
-//Copyright(c) 2023 AMD. All rights reserved.
-//
-//Author:       Basavaraj Hiregoudar <basavaraj.hiregoudar@amd.com>
-//              SaiSurya, Ch <saisurya.chakkaveeravenkatanaga@amd.com>
-
-#include <sof/audio/component.h>
-#include <sof/drivers/acp_dai_dma.h>
-#include <rtos/interrupt.h>
-#include <rtos/alloc.h>
-#include <sof/lib/dai.h>
-#include <sof/lib/dma.h>
-#include <sof/lib/uuid.h>
-#include <ipc/dai.h>
-#include <ipc/topology.h>
-#include <platform/fw_scratch_mem.h>
-#include <sof/lib/io.h>
-#include <platform/chip_offset_byte.h>
-
-SOF_DEFINE_REG_UUID(hsdai);
-/* unused with Zephyr, generates no output */
-DECLARE_TR_CTX(hsdai_tr, SOF_UUID(hsdai_uuid), LOG_LEVEL_INFO);
-
-static inline int hsdai_set_config(struct dai *dai, struct ipc_config_dai *common_config,
-				   const void *spec_config)
-{
-	/* set master clk for hs dai */
-	io_reg_write(PU_REGISTER_BASE + ACP_I2STDM2_MSTRCLKGEN, 0x40081);
-	return 0;
-}
-
-static int hsdai_trigger(struct dai *dai, int cmd, int direction)
-{
-	/* nothing to do on vangogh for HS dai */
-	return 0;
-}
-
-static int hsdai_probe(struct dai *dai)
-{
-	/* TODO */
-	return 0;
-}
-
-static int hsdai_remove(struct dai *dai)
-{
-	/* TODO */
-	return 0;
-}
-
-static int hsdai_get_fifo(struct dai *dai, int direction, int stream_id)
-{
-	switch (direction) {
-	case DAI_DIR_PLAYBACK:
-	case DAI_DIR_CAPTURE:
-		return dai_fifo(dai, direction);
-	default:
-		dai_err(dai, "Invalid direction");
-		return -EINVAL;
-	}
-}
-
-static int hsdai_get_handshake(struct dai *dai, int direction, int stream_id)
-{
-	int handshake = dai->plat_data.fifo[direction].handshake;
-
-	interrupt_get_irq(handshake, "irqsteer1");
-	return dai->plat_data.fifo[direction].handshake;
-}
-
-static int hsdai_get_hw_params(struct dai *dai,
-			       struct sof_ipc_stream_params *params,
-			       int dir)
-{
-	/* HS DAI currently supports only these parameters */
-	params->rate = ACP_DEFAULT_SAMPLE_RATE;
-	params->channels = ACP_DEFAULT_NUM_CHANNELS;
-	params->buffer_fmt = SOF_IPC_BUFFER_INTERLEAVED;
-	params->frame_fmt = SOF_IPC_FRAME_S16_LE;
-	return 0;
-}
-
-const struct dai_driver acp_hsdai_driver = {
-	.type = SOF_DAI_AMD_HS,
-	.uid = SOF_UUID(hsdai_uuid),
-#if !CONFIG_ZEPHYR_LOG
-	.tctx = &hsdai_tr,
-#endif
-	.dma_dev = DMA_DEV_HS,
-	.dma_caps = DMA_CAP_HS,
-	.ops = {
-		.trigger		= hsdai_trigger,
-		.set_config		= hsdai_set_config,
-		.probe			= hsdai_probe,
-		.remove			= hsdai_remove,
-		.get_fifo		= hsdai_get_fifo,
-		.get_handshake		= hsdai_get_handshake,
-		.get_hw_params          = hsdai_get_hw_params,
-	},
-};
diff --git a/src/drivers/amd/vangogh/acp_hs_dma.c b/src/drivers/amd/vangogh/acp_hs_dma.c
deleted file mode 100644
index b37d58548690..000000000000
--- a/src/drivers/amd/vangogh/acp_hs_dma.c
+++ /dev/null
@@ -1,443 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-//
-//Copyright(c) 2023 AMD. All rights reserved.
-//
-//Author:       Basavaraj Hiregoudar <basavaraj.hiregoudar@amd.com>
-//              SaiSurya, Ch <saisurya.chakkaveeravenkatanaga@amd.com>
-
-#include <rtos/atomic.h>
-#include <sof/audio/component.h>
-#include <rtos/bit.h>
-#include <sof/drivers/acp_dai_dma.h>
-#include <rtos/interrupt.h>
-#include <rtos/timer.h>
-#include <rtos/alloc.h>
-#include <rtos/clk.h>
-#include <sof/lib/cpu.h>
-#include <sof/lib/dma.h>
-#include <sof/lib/io.h>
-#include <sof/lib/pm_runtime.h>
-#include <sof/lib/notifier.h>
-#include <sof/platform.h>
-#include <sof/schedule/schedule.h>
-#include <rtos/spinlock.h>
-#include <sof/math/numbers.h>
-#include <sof/trace/trace.h>
-#include <ipc/topology.h>
-#include <user/trace.h>
-#include <errno.h>
-#include <stdbool.h>
-#include <stddef.h>
-#include <stdint.h>
-#include <platform/fw_scratch_mem.h>
-#include <platform/chip_registers.h>
-
-SOF_DEFINE_REG_UUID(acp_hs);
-/* unused with Zephyr, generates no output */
-DECLARE_TR_CTX(acp_hs_tr, SOF_UUID(acp_hs_uuid), LOG_LEVEL_INFO);
-
-#define HS_FIFO_SIZE		512
-#define HS_IER_DISABLE		0x0
-/* Vangogh hw specific addr map */
-#define ACP_DRAM_PHY_TRNS	0x0DEB0000
-
-static uint64_t prev_tx_pos;
-static uint64_t prev_rx_pos;
-static uint32_t hs_buff_size;
-/* allocate next free DMA channel */
-static struct dma_chan_data *acp_dai_hs_dma_channel_get(struct dma *dma,
-							unsigned int req_chan)
-{
-	k_spinlock_key_t key;
-	struct dma_chan_data *channel;
-
-	key = k_spin_lock(&dma->lock);
-	if (req_chan >= dma->plat_data.channels) {
-		k_spin_unlock(&dma->lock, key);
-		tr_err(&acp_hs_tr, "Channel %d not in range", req_chan);
-		return NULL;
-	}
-	channel = &dma->chan[req_chan];
-	if (channel->status != COMP_STATE_INIT) {
-		k_spin_unlock(&dma->lock, key);
-		tr_err(&acp_hs_tr, "channel already in use %d", req_chan);
-		return NULL;
-	}
-	atomic_add(&dma->num_channels_busy, 1);
-	channel->status = COMP_STATE_READY;
-	k_spin_unlock(&dma->lock, key);
-	return channel;
-}
-
-/* channel must not be running when this is called */
-static void acp_dai_hs_dma_channel_put(struct dma_chan_data *channel)
-{
-	k_spinlock_key_t key;
-
-	notifier_unregister_all(NULL, channel);
-	key = k_spin_lock(&channel->dma->lock);
-	channel->status = COMP_STATE_INIT;
-	atomic_sub(&channel->dma->num_channels_busy, 1);
-	k_spin_unlock(&channel->dma->lock, key);
-}
-
-static int acp_dai_hs_dma_start(struct dma_chan_data *channel)
-{
-	acp_hstdm_ier_t hs_ier;
-	acp_hstdm_iter_t hs_iter;
-	acp_hstdm_irer_t hs_irer;
-	uint32_t	acp_pdm_en;
-
-	hs_iter = (acp_hstdm_iter_t)io_reg_read((PU_REGISTER_BASE + ACP_HSTDM_ITER));
-	hs_irer = (acp_hstdm_irer_t)io_reg_read((PU_REGISTER_BASE + ACP_HSTDM_IRER));
-	acp_pdm_en = (uint32_t)io_reg_read(PU_REGISTER_BASE + ACP_WOV_PDM_ENABLE);
-
-	if (!hs_iter.bits.hstdm_txen && !hs_irer.bits.hstdm_rx_en && !acp_pdm_en) {
-		io_reg_write((PU_REGISTER_BASE + ACP_CLKMUX_SEL), ACP_ACLK_CLK_SEL);
-		/* Request SMU to set aclk to 600 Mhz */
-		acp_change_clock_notify(600000000);
-	}
-
-	if (channel->direction == DMA_DIR_MEM_TO_DEV) {
-		channel->status = COMP_STATE_ACTIVE;
-		prev_tx_pos = 0;
-		hs_ier = (acp_hstdm_ier_t)io_reg_read(PU_REGISTER_BASE + ACP_HSTDM_IER);
-		hs_ier.bits.hstdm_ien = 1;
-		io_reg_write((PU_REGISTER_BASE + ACP_HSTDM_IER), hs_ier.u32all);
-		hs_iter.bits.hstdm_txen = 1;
-		hs_iter.bits.hstdm_tx_protocol_mode = 0;
-		hs_iter.bits.hstdm_tx_data_path_mode = 1;
-		hs_iter.bits.hstdm_tx_samp_len = 2;
-		io_reg_write((PU_REGISTER_BASE + ACP_HSTDM_ITER), hs_iter.u32all);
-	} else if (channel->direction == DMA_DIR_DEV_TO_MEM) {
-		channel->status = COMP_STATE_ACTIVE;
-		prev_rx_pos = 0;
-		hs_ier = (acp_hstdm_ier_t)io_reg_read(PU_REGISTER_BASE + ACP_HSTDM_IER);
-		hs_ier.bits.hstdm_ien = 1;
-		io_reg_write((PU_REGISTER_BASE + ACP_HSTDM_IER), hs_ier.u32all);
-		hs_irer.bits.hstdm_rx_en = 1;
-		hs_irer.bits.hstdm_rx_protocol_mode = 0;
-		hs_irer.bits.hstdm_rx_data_path_mode = 1;
-		hs_irer.bits.hstdm_rx_samplen = 2;
-		io_reg_write((PU_REGISTER_BASE + ACP_HSTDM_IRER), hs_irer.u32all);
-	} else {
-		tr_err(&acp_hs_tr, "Start direction not defined %d", channel->direction);
-		return -EINVAL;
-	}
-
-	return 0;
-}
-
-static int acp_dai_hs_dma_release(struct dma_chan_data *channel)
-{
-	/* nothing to do on vangogh */
-	return 0;
-}
-
-static int acp_dai_hs_dma_pause(struct dma_chan_data *channel)
-{
-	/* nothing to do on vangogh */
-	return 0;
-}
-
-static int acp_dai_hs_dma_stop(struct dma_chan_data *channel)
-{
-	acp_hstdm_irer_t hs_irer;
-	acp_hstdm_iter_t hs_iter;
-	acp_i2stdm_irer_t sp_irer;
-	acp_i2stdm_iter_t sp_iter;
-	uint32_t                acp_pdm_en;
-
-	switch (channel->status) {
-	case COMP_STATE_READY:
-	case COMP_STATE_PREPARE:
-		return 0;
-	case COMP_STATE_PAUSED:
-	case COMP_STATE_ACTIVE:
-		break;
-	default:
-		return -EINVAL;
-	}
-	channel->status = COMP_STATE_READY;
-	if (channel->direction == DMA_DIR_MEM_TO_DEV) {
-		hs_iter = (acp_hstdm_iter_t)io_reg_read(PU_REGISTER_BASE + ACP_HSTDM_ITER);
-		hs_iter.bits.hstdm_txen = 0;
-		io_reg_write((PU_REGISTER_BASE + ACP_HSTDM_ITER), hs_iter.u32all);
-	} else if (channel->direction == DMA_DIR_DEV_TO_MEM) {
-		channel->status = COMP_STATE_READY;
-		hs_irer = (acp_hstdm_irer_t)io_reg_read(PU_REGISTER_BASE + ACP_HSTDM_IRER);
-		hs_irer.bits.hstdm_rx_en = 0;
-		io_reg_write((PU_REGISTER_BASE + ACP_HSTDM_IRER), hs_irer.u32all);
-	} else {
-		tr_err(&acp_hs_tr, "Stop direction not defined %d", channel->direction);
-		return -EINVAL;
-	}
-	hs_iter = (acp_hstdm_iter_t)io_reg_read((PU_REGISTER_BASE + ACP_HSTDM_ITER));
-	hs_irer = (acp_hstdm_irer_t)io_reg_read((PU_REGISTER_BASE + ACP_HSTDM_IRER));
-	sp_iter = (acp_i2stdm_iter_t)io_reg_read((PU_REGISTER_BASE + ACP_I2STDM_ITER));
-	sp_irer = (acp_i2stdm_irer_t)io_reg_read((PU_REGISTER_BASE + ACP_I2STDM_IRER));
-	acp_pdm_en = (uint32_t)io_reg_read(PU_REGISTER_BASE + ACP_WOV_PDM_ENABLE);
-	if (!hs_iter.bits.hstdm_txen && !hs_irer.bits.hstdm_rx_en && !sp_iter.bits.i2stdm_txen &&
-	    !sp_irer.bits.i2stdm_rx_en) {
-		io_reg_write((PU_REGISTER_BASE + ACP_HSTDM_IER), HS_IER_DISABLE);
-		/* Request SMU to scale down aclk to minimum clk */
-		if (!acp_pdm_en) {
-			acp_change_clock_notify(0);
-			io_reg_write((PU_REGISTER_BASE + ACP_CLKMUX_SEL), ACP_INTERNAL_CLK_SEL);
-		}
-	}
-	return 0;
-}
-
-static int acp_dai_hs_dma_status(struct dma_chan_data *channel,
-				 struct dma_chan_status *status,
-				 uint8_t direction)
-{
-	/* nothing to do on vangogh */
-	return 0;
-}
-
-/* set the DMA channel configuration, source/target address, buffer sizes */
-static int acp_dai_hs_dma_set_config(struct dma_chan_data *channel,
-				     struct dma_sg_config *config)
-{
-	uint32_t hs_buff_addr;
-	uint32_t hs_fifo_addr;
-
-	if (!config->cyclic) {
-		tr_err(&acp_hs_tr, "cyclic configurations only supported!");
-		return -EINVAL;
-	}
-	if (config->scatter) {
-		tr_err(&acp_hs_tr, "scatter enabled, that is not supported for now!");
-		return -EINVAL;
-	}
-
-	volatile acp_scratch_mem_config_t *pscratch_mem_cfg =
-		(volatile acp_scratch_mem_config_t *)(PU_SCRATCH_REG_BASE + SCRATCH_REG_OFFSET);
-	channel->is_scheduling_source = true;
-	channel->direction = config->direction;
-	hs_buff_size = config->elem_array.elems[0].size * config->elem_array.count;
-	if (config->direction ==  DMA_DIR_MEM_TO_DEV) {
-		/* HS Transmit FIFO Address and FIFO Size*/
-		hs_fifo_addr = (uint32_t)(&pscratch_mem_cfg->acp_transmit_hs_fifo_buffer);
-		hs_fifo_addr = (hs_fifo_addr & ACP_DRAM_ADDRESS_MASK);
-		hs_fifo_addr = (hs_fifo_addr - ACP_DRAM_PHY_TRNS);
-		io_reg_write((PU_REGISTER_BASE + ACP_HS_TX_FIFOADDR), hs_fifo_addr);
-		io_reg_write((PU_REGISTER_BASE + ACP_HS_TX_FIFOSIZE), (uint32_t)(HS_FIFO_SIZE));
-
-		/* Transmit RINGBUFFER Address and size*/
-		config->elem_array.elems[0].src =
-			(config->elem_array.elems[0].src & ACP_DRAM_ADDRESS_MASK);
-		hs_buff_addr = (config->elem_array.elems[0].src | ACP_DRAM_ADDR_TRNS);
-		io_reg_write((PU_REGISTER_BASE + ACP_HS_TX_RINGBUFADDR), hs_buff_addr);
-		io_reg_write((PU_REGISTER_BASE + ACP_HS_TX_RINGBUFSIZE), hs_buff_size);
-
-		/* Transmit DMA transfer size in bytes */
-		io_reg_write((PU_REGISTER_BASE + ACP_HS_TX_DMA_SIZE),
-			     (uint32_t)(ACP_DMA_TRANS_SIZE));
-
-		/* Watermark size for HS transmit FIFO - Half of HS buffer size */
-		io_reg_write((PU_REGISTER_BASE + ACP_HS_TX_INTR_WATERMARK_SIZE),
-			     (hs_buff_size >> 1));
-
-	} else if (config->direction == DMA_DIR_DEV_TO_MEM) {
-		/* HS Receive FIFO Address and FIFO Size*/
-		hs_fifo_addr = (uint32_t)(&pscratch_mem_cfg->acp_receive_fifo_buffer);
-		hs_fifo_addr = (hs_fifo_addr & ACP_DRAM_ADDRESS_MASK);
-		hs_fifo_addr = (hs_fifo_addr - ACP_DRAM_PHY_TRNS);
-		io_reg_write((PU_REGISTER_BASE + ACP_HS_RX_FIFOADDR), hs_fifo_addr);
-		io_reg_write((PU_REGISTER_BASE + ACP_HS_RX_FIFOSIZE),
-			     (uint32_t)(HS_FIFO_SIZE));
-
-		/* Receive RINGBUFFER Address and size*/
-		config->elem_array.elems[0].dest =
-			(config->elem_array.elems[0].dest & ACP_DRAM_ADDRESS_MASK);
-		hs_buff_addr = (config->elem_array.elems[0].dest | ACP_DRAM_ADDR_TRNS);
-		io_reg_write((PU_REGISTER_BASE + ACP_HS_RX_RINGBUFADDR), hs_buff_addr);
-		io_reg_write((PU_REGISTER_BASE + ACP_HS_RX_RINGBUFSIZE), hs_buff_size);
-
-		/* Receive DMA transfer size in bytes */
-		io_reg_write((PU_REGISTER_BASE + ACP_HS_RX_DMA_SIZE),
-			     (uint32_t)(ACP_DMA_TRANS_SIZE));
-
-		/* Watermark size for  receive fifo - Half of HS buffer size*/
-		io_reg_write((PU_REGISTER_BASE + ACP_HS_RX_INTR_WATERMARK_SIZE),
-			     (hs_buff_size >> 1));
-
-	} else {
-		tr_err(&acp_hs_tr, "Config channel direction undefined %d", channel->direction);
-		return -EINVAL;
-	}
-
-	return 0;
-}
-
-static int acp_dai_hs_dma_copy(struct dma_chan_data *channel, int bytes,
-			       uint32_t flags)
-{
-	struct dma_cb_data next = {
-		.channel = channel,
-		.elem.size = bytes,
-	};
-	tr_info(&acp_hs_tr, "entry");
-	notifier_event(channel, NOTIFIER_ID_DMA_COPY,
-		       NOTIFIER_TARGET_CORE_LOCAL, &next, sizeof(next));
-	return 0;
-}
-
-static int acp_dai_hs_dma_probe(struct dma *dma)
-{
-	int channel;
-
-	if (dma->chan) {
-		tr_err(&acp_hs_tr, "Repeated probe");
-		return -EEXIST;
-	}
-	dma->chan = rzalloc(SOF_MEM_FLAG_KERNEL,
-			    dma->plat_data.channels *
-			    sizeof(struct dma_chan_data));
-	if (!dma->chan) {
-		tr_err(&acp_hs_tr, "Probe failure,unable to allocate channel descriptors");
-		return -ENOMEM;
-	}
-	for (channel = 0; channel < dma->plat_data.channels; channel++) {
-		dma->chan[channel].dma = dma;
-		dma->chan[channel].index = channel;
-		dma->chan[channel].status = COMP_STATE_INIT;
-	}
-	atomic_init(&dma->num_channels_busy, 0);
-	return 0;
-}
-
-static int acp_dai_hs_dma_remove(struct dma *dma)
-{
-	if (!dma->chan) {
-		tr_err(&acp_hs_tr, "remove called without probe,it's a no-op");
-		return 0;
-	}
-
-	rfree(dma->chan);
-	dma->chan = NULL;
-	return 0;
-}
-
-static int acp_dai_hs_dma_get_data_size(struct dma_chan_data *channel,
-					uint32_t *avail, uint32_t *free)
-{
-	if (channel->direction == DMA_DIR_MEM_TO_DEV) {
-#if CONFIG_DISABLE_DESCRIPTOR_SPLIT
-		uint64_t tx_low, curr_tx_pos, tx_high;
-		tx_low = (uint32_t)io_reg_read(PU_REGISTER_BASE +
-				ACP_HS_TX_LINEARPOSITIONCNTR_LOW);
-		tx_high = (uint32_t)io_reg_read(PU_REGISTER_BASE +
-				ACP_HS_TX_LINEARPOSITIONCNTR_HIGH);
-		curr_tx_pos = (uint64_t)((tx_high << 32) | tx_low);
-		*free = (curr_tx_pos - prev_tx_pos) > hs_buff_size ?
-			(curr_tx_pos - prev_tx_pos) % hs_buff_size :
-			(curr_tx_pos - prev_tx_pos);
-		*avail = hs_buff_size - *free;
-		prev_tx_pos = curr_tx_pos;
-#else
-		*free = (hs_buff_size >> 1);
-		*avail = (hs_buff_size >> 1);
-#endif
-	} else if (channel->direction == DMA_DIR_DEV_TO_MEM) {
-#if CONFIG_DISABLE_DESCRIPTOR_SPLIT
-		uint64_t rx_low, curr_rx_pos, rx_high;
-		rx_low = (uint32_t)io_reg_read(PU_REGISTER_BASE +
-				ACP_HS_RX_LINEARPOSITIONCNTR_LOW);
-		rx_high = (uint32_t)io_reg_read(PU_REGISTER_BASE +
-				ACP_HS_RX_LINEARPOSITIONCNTR_HIGH);
-		curr_rx_pos = (uint64_t)((rx_high << 32) | rx_low);
-		*free = (curr_rx_pos - prev_rx_pos) > hs_buff_size ?
-			(curr_rx_pos - prev_rx_pos) % hs_buff_size :
-			(curr_rx_pos - prev_rx_pos);
-		*avail = hs_buff_size - *free;
-		prev_rx_pos = curr_rx_pos;
-#else
-		*free = (hs_buff_size >> 1);
-		*avail = (hs_buff_size >> 1);
-#endif
-	} else {
-		tr_err(&acp_hs_tr, "Channel direction not defined %d", channel->direction);
-		return -EINVAL;
-	}
-	return 0;
-}
-
-static int acp_dai_hs_dma_get_attribute(struct dma *dma, uint32_t type, uint32_t *value)
-{
-	switch (type) {
-	case DMA_ATTR_BUFFER_ALIGNMENT:
-	case DMA_ATTR_COPY_ALIGNMENT:
-		*value = ACP_DMA_BUFFER_ALIGN;
-		break;
-	case DMA_ATTR_BUFFER_ADDRESS_ALIGNMENT:
-		*value = PLATFORM_DCACHE_ALIGN;
-		break;
-	case DMA_ATTR_BUFFER_PERIOD_COUNT:
-		*value = ACP_DAI_DMA_BUFFER_PERIOD_COUNT;
-		break;
-	default:
-		return -ENOENT;
-	}
-	return 0;
-}
-
-static int acp_dai_hs_dma_interrupt(struct dma_chan_data *channel, enum dma_irq_cmd cmd)
-{
-	uint32_t status;
-	acp_dsp0_intr_stat_t acp_intr_stat;
-	acp_dsp0_intr_cntl_t acp_intr_cntl;
-
-	if (channel->status == COMP_STATE_INIT)
-		return 0;
-	switch (cmd) {
-	case DMA_IRQ_STATUS_GET:
-		acp_intr_stat =  (acp_dsp0_intr_stat_t)
-			dma_reg_read(channel->dma, ACP_DSP0_INTR_STAT);
-		status = acp_intr_stat.bits.audio_buffer_int_stat;
-		return (status & (1 << channel->index));
-	case DMA_IRQ_CLEAR:
-		acp_intr_stat.u32all = 0;
-		acp_intr_stat.bits.audio_buffer_int_stat =
-					(1 << channel->index);
-		status  = acp_intr_stat.u32all;
-		dma_reg_write(channel->dma, ACP_DSP0_INTR_STAT, status);
-		return 0;
-	case DMA_IRQ_MASK:
-		acp_intr_cntl =  (acp_dsp0_intr_cntl_t)
-				dma_reg_read(channel->dma, ACP_DSP0_INTR_CNTL);
-		acp_intr_cntl.bits.audio_buffer_int_mask &= (~(1 << channel->index));
-		status  = acp_intr_cntl.u32all;
-		dma_reg_write(channel->dma, ACP_DSP0_INTR_CNTL, status);
-		return 0;
-	case DMA_IRQ_UNMASK:
-		acp_intr_cntl =  (acp_dsp0_intr_cntl_t)
-				dma_reg_read(channel->dma, ACP_DSP0_INTR_CNTL);
-		acp_intr_cntl.bits.audio_buffer_int_mask  |=  (1 << channel->index);
-		status = acp_intr_cntl.u32all;
-		dma_reg_write(channel->dma, ACP_DSP0_INTR_CNTL, status);
-		return 0;
-	default:
-		return -EINVAL;
-	}
-}
-
-const struct dma_ops acp_dai_hs_dma_ops = {
-	.channel_get		= acp_dai_hs_dma_channel_get,
-	.channel_put		= acp_dai_hs_dma_channel_put,
-	.start			= acp_dai_hs_dma_start,
-	.stop			= acp_dai_hs_dma_stop,
-	.pause			= acp_dai_hs_dma_pause,
-	.release		= acp_dai_hs_dma_release,
-	.copy			= acp_dai_hs_dma_copy,
-	.status			= acp_dai_hs_dma_status,
-	.set_config		= acp_dai_hs_dma_set_config,
-	.interrupt		= acp_dai_hs_dma_interrupt,
-	.probe			= acp_dai_hs_dma_probe,
-	.remove			= acp_dai_hs_dma_remove,
-	.get_data_size		= acp_dai_hs_dma_get_data_size,
-	.get_attribute		= acp_dai_hs_dma_get_attribute,
-};
diff --git a/src/drivers/amd/vangogh/acp_sp_dai.c b/src/drivers/amd/vangogh/acp_sp_dai.c
deleted file mode 100644
index 2de52b2ae5f3..000000000000
--- a/src/drivers/amd/vangogh/acp_sp_dai.c
+++ /dev/null
@@ -1,97 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-//
-//Copyright(c) 2023 AMD. All rights reserved.
-//
-//Author:       Basavaraj Hiregoudar <basavaraj.hiregoudar@amd.com>
-//              SaiSurya, Ch <saisurya.chakkaveeravenkatanaga@amd.com>
-
-#include <sof/audio/component.h>
-#include <sof/drivers/acp_dai_dma.h>
-#include <rtos/interrupt.h>
-#include <rtos/alloc.h>
-#include <sof/lib/dai.h>
-#include <sof/lib/dma.h>
-#include <sof/lib/uuid.h>
-#include <ipc/dai.h>
-#include <ipc/topology.h>
-#include <platform/fw_scratch_mem.h>
-#include <sof/lib/io.h>
-#include <platform/chip_offset_byte.h>
-
-SOF_DEFINE_REG_UUID(spdai);
-/* unused with Zephyr, generates no output */
-DECLARE_TR_CTX(spdai_tr, SOF_UUID(spdai_uuid), LOG_LEVEL_INFO);
-
-static inline int spdai_set_config(struct dai *dai, struct ipc_config_dai *common_config,
-				   const void *spec_config)
-{
-	/* nothing to do on vangogh for SP dai */
-	io_reg_write(PU_REGISTER_BASE + ACP_I2STDM0_MSTRCLKGEN, 0x40081);
-	return 0;
-}
-
-static int spdai_trigger(struct dai *dai, int cmd, int direction)
-{
-	/* nothing to do on vangogh for SP dai */
-	return 0;
-}
-
-static int spdai_probe(struct dai *dai)
-{
-	/* TODO */
-	return 0;
-}
-
-static int spdai_remove(struct dai *dai)
-{
-	/* TODO */
-	return 0;
-}
-
-static int spdai_get_fifo(struct dai *dai, int direction, int stream_id)
-{
-	switch (direction) {
-	case DAI_DIR_PLAYBACK:
-	case DAI_DIR_CAPTURE:
-		return dai_fifo(dai, direction);
-	default:
-		dai_err(dai, "Invalid direction");
-		return -EINVAL;
-	}
-}
-
-static int spdai_get_handshake(struct dai *dai, int direction, int stream_id)
-{
-	return dai->plat_data.fifo[direction].handshake;
-}
-
-static int spdai_get_hw_params(struct dai *dai,
-			       struct sof_ipc_stream_params *params,
-			       int dir)
-{
-	/* SP DAI currently supports only these parameters */
-	params->rate = ACP_DEFAULT_SAMPLE_RATE;
-	params->channels = ACP_DEFAULT_NUM_CHANNELS;
-	params->buffer_fmt = SOF_IPC_BUFFER_INTERLEAVED;
-	params->frame_fmt = SOF_IPC_FRAME_S16_LE;
-	return 0;
-}
-
-const struct dai_driver acp_spdai_driver = {
-	.type = SOF_DAI_AMD_SP,
-	.uid = SOF_UUID(spdai_uuid),
-#if !CONFIG_ZEPHYR_LOG
-	.tctx = &spdai_tr,
-#endif
-	.dma_dev = DMA_DEV_SP,
-	.dma_caps = DMA_CAP_SP,
-	.ops = {
-		.trigger		= spdai_trigger,
-		.set_config		= spdai_set_config,
-		.probe			= spdai_probe,
-		.remove			= spdai_remove,
-		.get_fifo		= spdai_get_fifo,
-		.get_handshake		= spdai_get_handshake,
-		.get_hw_params          = spdai_get_hw_params,
-	},
-};
diff --git a/src/drivers/amd/vangogh/acp_sp_dma.c b/src/drivers/amd/vangogh/acp_sp_dma.c
deleted file mode 100644
index 7949db6a7495..000000000000
--- a/src/drivers/amd/vangogh/acp_sp_dma.c
+++ /dev/null
@@ -1,315 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-//
-//Copyright(c) 2023 AMD. All rights reserved.
-//
-//Author:       Basavaraj Hiregoudar <basavaraj.hiregoudar@amd.com>
-//              SaiSurya, Ch <saisurya.chakkaveeravenkatanaga@amd.com>
-
-#include <rtos/atomic.h>
-#include <sof/audio/component.h>
-#include <rtos/bit.h>
-#include <sof/drivers/acp_dai_dma.h>
-#include <rtos/interrupt.h>
-#include <rtos/timer.h>
-#include <rtos/alloc.h>
-#include <rtos/clk.h>
-#include <sof/lib/cpu.h>
-#include <sof/lib/dma.h>
-#include <sof/lib/io.h>
-#include <sof/lib/pm_runtime.h>
-#include <sof/lib/notifier.h>
-#include <sof/platform.h>
-#include <sof/schedule/schedule.h>
-#include <rtos/spinlock.h>
-#include <sof/math/numbers.h>
-#include <sof/trace/trace.h>
-#include <ipc/topology.h>
-#include <user/trace.h>
-#include <errno.h>
-#include <stdbool.h>
-#include <stddef.h>
-#include <stdint.h>
-#include <platform/fw_scratch_mem.h>
-#include <platform/chip_registers.h>
-#include <platform/acp_sp_dma.h>
-
-SOF_DEFINE_REG_UUID(acp_sp);
-/* unused with Zephyr, generates no output */
-DECLARE_TR_CTX(acp_sp_vgh_tr, SOF_UUID(acp_sp_uuid), LOG_LEVEL_INFO);
-
-/* Vangogh hw specific addr map */
-#define ACP_DRAM_PHY_TRNS       0x0DEB0000
-
-static uint64_t prev_tx_pos;
-static uint64_t prev_rx_pos;
-static uint32_t sp_buff_size;
-
-int acp_dai_sp_dma_start(struct dma_chan_data *channel)
-{
-	acp_i2stdm_ier_t sp_ier;
-	acp_i2stdm_iter_t sp_iter;
-	acp_i2stdm_irer_t sp_irer;
-
-	sp_iter = (acp_i2stdm_iter_t)io_reg_read((PU_REGISTER_BASE + ACP_I2STDM_ITER));
-	sp_irer = (acp_i2stdm_irer_t)io_reg_read((PU_REGISTER_BASE + ACP_I2STDM_IRER));
-
-	if (!sp_iter.bits.i2stdm_txen && !sp_irer.bits.i2stdm_rx_en)
-		/* Request SMU to set aclk to 600 Mhz */
-		acp_change_clock_notify(600000000);
-
-	if (channel->direction == DMA_DIR_MEM_TO_DEV) {
-		channel->status = COMP_STATE_ACTIVE;
-		prev_tx_pos = 0;
-		sp_ier = (acp_i2stdm_ier_t)io_reg_read(PU_REGISTER_BASE + ACP_I2STDM_IER);
-		sp_ier.bits.i2stdm_ien = 1;
-		io_reg_write((PU_REGISTER_BASE + ACP_I2STDM_IER), sp_ier.u32all);
-		sp_iter.bits.i2stdm_txen = 1;
-		sp_iter.bits.i2stdm_tx_protocol_mode = 0;
-		sp_iter.bits.i2stdm_tx_data_path_mode = 1;
-		sp_iter.bits.i2stdm_tx_samp_len = 2;
-		io_reg_write((PU_REGISTER_BASE + ACP_I2STDM_ITER), sp_iter.u32all);
-	} else if (channel->direction == DMA_DIR_DEV_TO_MEM) {
-		channel->status = COMP_STATE_ACTIVE;
-		prev_rx_pos = 0;
-		sp_ier = (acp_i2stdm_ier_t)io_reg_read(PU_REGISTER_BASE + ACP_I2STDM_IER);
-		sp_ier.bits.i2stdm_ien = 1;
-		io_reg_write((PU_REGISTER_BASE + ACP_I2STDM_IER), sp_ier.u32all);
-		sp_irer.bits.i2stdm_rx_en = 1;
-		sp_irer.bits.i2stdm_rx_protocol_mode = 0;
-		sp_irer.bits.i2stdm_rx_data_path_mode = 1;
-		sp_irer.bits.i2stdm_rx_samplen = 2;
-		io_reg_write((PU_REGISTER_BASE + ACP_I2STDM_IRER), sp_irer.u32all);
-	} else {
-		tr_err(&acp_sp_vgh_tr, "Start direction not defined %d", channel->direction);
-		return -EINVAL;
-	}
-
-	return 0;
-}
-
-int acp_dai_sp_dma_stop(struct dma_chan_data *channel)
-{
-	acp_i2stdm_irer_t sp_irer;
-	acp_i2stdm_iter_t sp_iter;
-	acp_hstdm_iter_t hs_iter;
-	acp_hstdm_irer_t hs_irer;
-
-	switch (channel->status) {
-	case COMP_STATE_READY:
-	case COMP_STATE_PREPARE:
-		return 0;
-	case COMP_STATE_PAUSED:
-	case COMP_STATE_ACTIVE:
-		break;
-	default:
-		return -EINVAL;
-	}
-	channel->status = COMP_STATE_READY;
-	if (channel->direction == DMA_DIR_MEM_TO_DEV) {
-		sp_iter = (acp_i2stdm_iter_t)io_reg_read(PU_REGISTER_BASE + ACP_I2STDM_ITER);
-		sp_iter.bits.i2stdm_txen = 0;
-		io_reg_write((PU_REGISTER_BASE + ACP_I2STDM_ITER), sp_iter.u32all);
-	} else if (channel->direction == DMA_DIR_DEV_TO_MEM) {
-		sp_irer = (acp_i2stdm_irer_t)io_reg_read(PU_REGISTER_BASE + ACP_I2STDM_IRER);
-		sp_irer.bits.i2stdm_rx_en = 0;
-		io_reg_write((PU_REGISTER_BASE + ACP_I2STDM_IRER), sp_irer.u32all);
-	} else {
-		tr_err(&acp_sp_vgh_tr, "Stop direction not defined %d", channel->direction);
-		return -EINVAL;
-	}
-	sp_iter = (acp_i2stdm_iter_t)io_reg_read((PU_REGISTER_BASE + ACP_I2STDM_ITER));
-	sp_irer = (acp_i2stdm_irer_t)io_reg_read((PU_REGISTER_BASE + ACP_I2STDM_IRER));
-	hs_iter = (acp_hstdm_iter_t)io_reg_read((PU_REGISTER_BASE + ACP_HSTDM_ITER));
-	hs_irer = (acp_hstdm_irer_t)io_reg_read((PU_REGISTER_BASE + ACP_HSTDM_IRER));
-	if (!sp_iter.bits.i2stdm_txen && !sp_irer.bits.i2stdm_rx_en && !hs_iter.bits.hstdm_txen &&
-	    !hs_irer.bits.hstdm_rx_en) {
-		io_reg_write((PU_REGISTER_BASE + ACP_I2STDM_IER), SP_IER_DISABLE);
-		/* Request SMU to scale down aclk to minimum clk */
-		acp_change_clock_notify(0);
-		io_reg_write((PU_REGISTER_BASE + ACP_CLKMUX_SEL), ACP_INTERNAL_CLK_SEL);
-	}
-	return 0;
-}
-
-/* set the DMA channel configuration, source/target address, buffer sizes */
-int acp_dai_sp_dma_set_config(struct dma_chan_data *channel,
-			      struct dma_sg_config *config)
-{
-	uint32_t sp_buff_addr;
-	uint32_t sp_fifo_addr;
-
-	if (!config->cyclic) {
-		tr_err(&acp_sp_vgh_tr, "cyclic configurations only supported!");
-		return -EINVAL;
-	}
-	if (config->scatter) {
-		tr_err(&acp_sp_vgh_tr, "scatter enabled, that is not supported for now!");
-		return -EINVAL;
-	}
-
-	volatile acp_scratch_mem_config_t *pscratch_mem_cfg =
-		(volatile acp_scratch_mem_config_t *)(PU_SCRATCH_REG_BASE + SCRATCH_REG_OFFSET);
-	channel->is_scheduling_source = true;
-	channel->direction = config->direction;
-	sp_buff_size = config->elem_array.elems[0].size * config->elem_array.count;
-
-	if (config->direction ==  DMA_DIR_MEM_TO_DEV) {
-		/* SP Transmit FIFO Address and FIFO Size*/
-		sp_fifo_addr = (uint32_t)(&pscratch_mem_cfg->acp_transmit_fifo_buffer);
-		sp_fifo_addr = (sp_fifo_addr & ACP_DRAM_ADDRESS_MASK);
-		sp_fifo_addr = (sp_fifo_addr - ACP_DRAM_PHY_TRNS);
-		io_reg_write((PU_REGISTER_BASE + ACP_I2S_TX_FIFOADDR), sp_fifo_addr);
-		io_reg_write((PU_REGISTER_BASE + ACP_I2S_TX_FIFOSIZE), (uint32_t)(SP_FIFO_SIZE));
-
-		/* Transmit RINGBUFFER Address and size*/
-		config->elem_array.elems[0].src =
-			(config->elem_array.elems[0].src & ACP_DRAM_ADDRESS_MASK);
-		sp_buff_addr = (config->elem_array.elems[0].src | ACP_DRAM_ADDR_TRNS);
-		io_reg_write((PU_REGISTER_BASE + ACP_I2S_TX_RINGBUFADDR), sp_buff_addr);
-		io_reg_write((PU_REGISTER_BASE + ACP_I2S_TX_RINGBUFSIZE), sp_buff_size);
-
-		/* Transmit DMA transfer size in bytes */
-		io_reg_write((PU_REGISTER_BASE + ACP_I2S_TX_DMA_SIZE),
-			     (uint32_t)(ACP_DMA_TRANS_SIZE_128));
-
-		/* Watermark size for SP transmit FIFO - Half of SP buffer size */
-		io_reg_write((PU_REGISTER_BASE + ACP_I2S_TX_INTR_WATERMARK_SIZE),
-			     (sp_buff_size >> 1));
-
-	} else if (config->direction == DMA_DIR_DEV_TO_MEM) {
-		/* SP Receive FIFO Address and FIFO Size*/
-		sp_fifo_addr = (uint32_t)(&pscratch_mem_cfg->acp_receive_fifo_buffer);
-		sp_fifo_addr = (sp_fifo_addr & ACP_DRAM_ADDRESS_MASK);
-		sp_fifo_addr = (sp_fifo_addr - ACP_DRAM_PHY_TRNS);
-		io_reg_write((PU_REGISTER_BASE + ACP_I2S_RX_FIFOADDR), sp_fifo_addr);
-		io_reg_write((PU_REGISTER_BASE + ACP_I2S_RX_FIFOSIZE),
-			     (uint32_t)(SP_FIFO_SIZE));
-
-		/* Receive RINGBUFFER Address and size*/
-		config->elem_array.elems[0].dest =
-			(config->elem_array.elems[0].dest & ACP_DRAM_ADDRESS_MASK);
-		sp_buff_addr = (config->elem_array.elems[0].dest | ACP_DRAM_ADDR_TRNS);
-		io_reg_write((PU_REGISTER_BASE + ACP_I2S_RX_RINGBUFADDR), sp_buff_addr);
-		io_reg_write((PU_REGISTER_BASE + ACP_I2S_RX_RINGBUFSIZE), sp_buff_size);
-
-		/* Receive DMA transfer size in bytes */
-		io_reg_write((PU_REGISTER_BASE + ACP_I2S_RX_DMA_SIZE),
-			     (uint32_t)(ACP_DMA_TRANS_SIZE_128));
-
-		/* Watermark size for SP receive fifo - Half of SP buffer size*/
-		io_reg_write((PU_REGISTER_BASE + ACP_I2S_RX_INTR_WATERMARK_SIZE),
-			     (sp_buff_size >> 1));
-
-	} else {
-		tr_err(&acp_sp_vgh_tr, "DMA Config channel direction undefined %d",
-		       channel->direction);
-		return -EINVAL;
-	}
-
-	return 0;
-}
-
-int acp_dai_sp_dma_get_data_size(struct dma_chan_data *channel,
-				 uint32_t *avail, uint32_t *free)
-{
-	if (channel->direction == DMA_DIR_MEM_TO_DEV) {
-#if CONFIG_DISABLE_DESCRIPTOR_SPLIT
-		uint64_t tx_low, curr_tx_pos, tx_high;
-		tx_low = (uint32_t)io_reg_read(PU_REGISTER_BASE +
-				ACP_I2S_TX_LINEARPOSITIONCNTR_LOW);
-		tx_high = (uint32_t)io_reg_read(PU_REGISTER_BASE +
-				ACP_I2S_TX_LINEARPOSITIONCNTR_HIGH);
-		curr_tx_pos = (uint64_t)((tx_high << 32) | tx_low);
-		*free = (curr_tx_pos - prev_tx_pos) > sp_buff_size ?
-			(curr_tx_pos - prev_tx_pos) % sp_buff_size :
-			(curr_tx_pos - prev_tx_pos);
-		*avail = sp_buff_size - *free;
-		prev_tx_pos = curr_tx_pos;
-#else
-		//TODO  timer-based scheduling
-		*free = (sp_buff_size >> 1);
-		*avail = (sp_buff_size >> 1);
-#endif
-	} else if (channel->direction == DMA_DIR_DEV_TO_MEM) {
-#if CONFIG_DISABLE_DESCRIPTOR_SPLIT
-		uint64_t rx_low, curr_rx_pos, rx_high;
-		rx_low = (uint32_t)io_reg_read(PU_REGISTER_BASE +
-				ACP_I2S_RX_LINEARPOSITIONCNTR_LOW);
-		rx_high = (uint32_t)io_reg_read(PU_REGISTER_BASE +
-				ACP_I2S_RX_LINEARPOSITIONCNTR_HIGH);
-		curr_rx_pos = (uint64_t)((rx_high << 32) | rx_low);
-		*free = (curr_rx_pos - prev_rx_pos) > sp_buff_size ?
-			(curr_rx_pos - prev_rx_pos) % sp_buff_size :
-			(curr_rx_pos - prev_rx_pos);
-		*avail = sp_buff_size - *free;
-		prev_rx_pos = curr_rx_pos;
-#else
-		//TODO  timer-based scheduling
-		*free = (sp_buff_size >> 1);
-		*avail = (sp_buff_size >> 1);
-#endif
-	} else {
-		tr_err(&acp_sp_vgh_tr, "Channel direction not defined %d", channel->direction);
-		return -EINVAL;
-	}
-	return 0;
-}
-
-int acp_dai_sp_dma_get_attribute(struct dma *dma, uint32_t type, uint32_t *value)
-{
-	switch (type) {
-	case DMA_ATTR_BUFFER_ALIGNMENT:
-	case DMA_ATTR_COPY_ALIGNMENT:
-		*value = ACP_DMA_BUFFER_ALIGN_128;
-		break;
-	case DMA_ATTR_BUFFER_ADDRESS_ALIGNMENT:
-		*value = PLATFORM_DCACHE_ALIGN;
-		break;
-	case DMA_ATTR_BUFFER_PERIOD_COUNT:
-		*value = ACP_DAI_DMA_BUFFER_PERIOD_COUNT;
-		break;
-	default:
-		return -ENOENT;
-	}
-	return 0;
-}
-
-int acp_dai_sp_dma_interrupt(struct dma_chan_data *channel, enum dma_irq_cmd cmd)
-{
-	uint32_t status;
-	acp_dsp0_intr_stat_t acp_intr_stat;
-	acp_dsp0_intr_cntl_t acp_intr_cntl;
-
-	if (channel->status == COMP_STATE_INIT)
-		return 0;
-	switch (cmd) {
-	case DMA_IRQ_STATUS_GET:
-		acp_intr_stat =  (acp_dsp0_intr_stat_t)
-			dma_reg_read(channel->dma, ACP_DSP0_INTR_STAT);
-		status = acp_intr_stat.bits.audio_buffer_int_stat;
-		return (status & (1 << channel->index));
-	case DMA_IRQ_CLEAR:
-		acp_intr_stat.u32all = 0;
-		acp_intr_stat.bits.audio_buffer_int_stat =
-					(1 << channel->index);
-		status  = acp_intr_stat.u32all;
-		dma_reg_write(channel->dma, ACP_DSP0_INTR_STAT, status);
-		return 0;
-	case DMA_IRQ_MASK:
-		acp_intr_cntl =  (acp_dsp0_intr_cntl_t)
-				dma_reg_read(channel->dma, ACP_DSP0_INTR_CNTL);
-		acp_intr_cntl.bits.audio_buffer_int_mask &= (~(1 << channel->index));
-		status  = acp_intr_cntl.u32all;
-		dma_reg_write(channel->dma, ACP_DSP0_INTR_CNTL, status);
-		return 0;
-	case DMA_IRQ_UNMASK:
-		acp_intr_cntl =  (acp_dsp0_intr_cntl_t)
-				dma_reg_read(channel->dma, ACP_DSP0_INTR_CNTL);
-		acp_intr_cntl.bits.audio_buffer_int_mask  |=  (1 << channel->index);
-		status = acp_intr_cntl.u32all;
-		dma_reg_write(channel->dma, ACP_DSP0_INTR_CNTL, status);
-		return 0;
-	default:
-		return -EINVAL;
-	}
-}
diff --git a/src/drivers/amd/vangogh/interrupt.c b/src/drivers/amd/vangogh/interrupt.c
deleted file mode 100644
index 5bdb1f281618..000000000000
--- a/src/drivers/amd/vangogh/interrupt.c
+++ /dev/null
@@ -1,439 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-//
-//Copyright(c) 2023 AMD. All rights reserved.
-//
-//Author:       Basavaraj Hiregoudar <basavaraj.hiregoudar@amd.com>
-//              SaiSurya, Ch <saisurya.chakkaveeravenkatanaga@amd.com>
-#include <sof/common.h>
-#include <platform/chip_offset_byte.h>
-#include <platform/chip_registers.h>
-#include <rtos/interrupt.h>
-#include <sof/lib/cpu.h>
-#include <sof/lib/io.h>
-#include <sof/lib/memory.h>
-#include <sof/lib/uuid.h>
-#include <sof/list.h>
-#include <rtos/spinlock.h>
-#include <xtensa/hal.h>
-#include <xtensa/config/core.h>
-#include <xtensa/config/specreg.h>
-#include <xtensa/core-macros.h>
-#include "xtos-internal.h"
-#include <errno.h>
-#include <inttypes.h>
-#include <stdbool.h>
-#include <stddef.h>
-#include <stdint.h>
-
-SOF_DEFINE_REG_UUID(irq_acp);
-
-/* unused with Zephyr, generates no output */
-DECLARE_TR_CTX(acp_irq_tr, SOF_UUID(irq_acp_uuid), LOG_LEVEL_INFO);
-
-#define IRQ_INT_MASK(irq)	(1 << (irq))
-#define RESERVED_IRQS_NUM	0
-#define IRQS_NUM		9
-#define IRQS_PER_LINE		1
-
-static inline uint32_t acp_irq_status_read(uint32_t reg)
-{
-	return io_reg_read(PU_REGISTER_BASE + reg);
-}
-
-static inline void acp_irq_update_bits(uint32_t reg, uint32_t mask,
-				       uint32_t value)
-{
-	io_reg_update_bits(PU_REGISTER_BASE + reg, mask, value);
-}
-
-static uint32_t acp_irq_get_status(uint32_t index)
-{
-	/* 0-7 interrupts are used */
-	if (index > 7)
-		return 0;
-	return acp_irq_status_read(ACP_DSP0_INTR_STAT);
-}
-
-static void acp_irq_mask_int(uint32_t irq)
-{
-	uint32_t mask;
-
-	if (irq < RESERVED_IRQS_NUM || irq >= IRQS_NUM) {
-		tr_err(&acp_irq_tr, "Invalid interrupt");
-		return;
-	}
-	mask = IRQ_INT_MASK(irq);
-	acp_irq_update_bits(ACP_DSP0_INTR_CNTL, mask, 0);
-}
-
-static void acp_irq_unmask_int(uint32_t irq)
-{
-	uint32_t mask;
-
-	if (irq < RESERVED_IRQS_NUM || irq >= IRQS_NUM) {
-		tr_err(&acp_irq_tr, "Invalid interrupt");
-		return;
-	}
-	mask = IRQ_INT_MASK(irq);
-	acp_irq_update_bits(ACP_DSP0_INTR_CNTL, mask, mask);
-}
-
-static uint64_t acp_get_irq_interrupts(uint32_t index)
-{
-	return acp_irq_get_status(index);
-}
-
-static int get_first_irq(uint64_t ints)
-{
-	return ffs(ints) - 1;
-}
-
-static inline void acp_handle_irq_5(struct irq_cascade_desc *cascade,
-				    uint32_t line_index, uint64_t status)
-{
-	int core = cpu_get_id();
-	struct list_item *clist;
-	struct irq_desc *child = NULL;
-	int bit;
-	bool handled;
-	k_spinlock_key_t key;
-
-	while (status) {
-		bit = get_first_irq(status);
-		handled = false;
-		status &= ~(1ull << bit);
-		bit = 5;//bit-23;//HARDCODING
-
-		key = k_spin_lock(&cascade->lock);
-
-		list_for_item(clist, &cascade->child[bit].list) {
-			child = container_of(clist, struct irq_desc, irq_list);
-
-			if (child->handler && (child->cpu_mask & 1 << core)) {
-				k_spin_unlock(&cascade->lock, key);
-				child->handler(child->handler_arg);
-				k_spin_lock(&cascade->lock);
-				handled = true;
-			}
-		}
-
-		k_spin_unlock(&cascade->lock, key);
-
-		if (!handled) {
-			tr_err(&acp_irq_tr, "irq_handler(): not handled, bit %d",
-			       bit);
-			acp_irq_mask_int(line_index * IRQS_PER_LINE + bit);
-		}
-	}
-}
-
-static inline void acp_handle_irq(struct irq_cascade_desc *cascade,
-				  uint32_t line_index, uint64_t status)
-{
-	int core = cpu_get_id();
-	struct list_item *clist;
-	struct irq_desc *child = NULL;
-	int bit;
-	bool handled;
-	k_spinlock_key_t key;
-
-	while (status) {
-		bit = get_first_irq(status);
-		handled = false;
-		status &= ~(1ull << bit);
-
-		key = k_spin_lock(&cascade->lock);
-
-		list_for_item(clist, &cascade->child[bit].list) {
-			child = container_of(clist, struct irq_desc, irq_list);
-
-			if (child->handler && (child->cpu_mask & 1 << core)) {
-				child->handler(child->handler_arg);
-				handled = true;
-			}
-		}
-
-		k_spin_unlock(&cascade->lock, key);
-
-		if (!handled) {
-			tr_err(&acp_irq_tr, "irq_handler(): not handled, bit %d", bit);
-			acp_irq_mask_int(line_index * IRQS_PER_LINE + bit);
-		}
-	}
-}
-
-static void irqhandler_5(void *data)
-{
-	uint32_t line_index = 5;
-	struct irq_desc *parent = data;
-	struct irq_cascade_desc *cascade =
-		container_of(parent, struct irq_cascade_desc, desc);
-	uint64_t status;
-
-	line_index = 5;
-	status = acp_get_irq_interrupts(line_index);
-
-	if (status)
-		/* Handle current interrupts */
-		acp_handle_irq_5(cascade, line_index, status);
-	else
-		tr_err(&acp_irq_tr, "invalid interrupt status");
-}
-
-static inline void irq_handler(void *data, uint32_t line_index)
-{
-	struct irq_desc *parent = data;
-	struct irq_cascade_desc *cascade =
-		container_of(parent, struct irq_cascade_desc, desc);
-	uint64_t status;
-
-	status = acp_get_irq_interrupts(line_index);
-	if (status)
-		/* Handle current interrupts */
-		acp_handle_irq(cascade, line_index, status);
-	else
-		tr_err(&acp_irq_tr, "invalid interrupt status");
-}
-
-#define DEFINE_IRQ_HANDLER(n) \
-	static void irqhandler_##n(void *arg) \
-	{ \
-		irq_handler(arg, n); \
-	}
-
-DEFINE_IRQ_HANDLER(0)
-DEFINE_IRQ_HANDLER(1)
-DEFINE_IRQ_HANDLER(3)
-DEFINE_IRQ_HANDLER(4)
-
-static void acp_irq_mask(struct irq_desc *desc, uint32_t irq, unsigned int core)
-{
-	acp_irq_mask_int(irq);
-}
-
-static void acp_irq_unmask(struct irq_desc *desc, uint32_t irq, unsigned int core)
-{
-	acp_irq_unmask_int(irq);
-}
-
-static const struct irq_cascade_ops irq_ops = {
-	.mask = acp_irq_mask,
-	.unmask = acp_irq_unmask,
-};
-
-static const struct irq_cascade_tmpl dsp_irq[] = {
-	{
-		.irq = IRQ_NUM_TIMER0,
-		.handler = irqhandler_0,
-		.ops = &irq_ops,
-		.global_mask = false,
-	}, {
-		.irq = IRQ_NUM_SOFTWARE0,
-		.handler = irqhandler_1,
-		.ops = &irq_ops,
-		.global_mask = false,
-	},
-	{
-		.irq = IRQ_NUM_EXT_LEVEL3,
-		.handler = irqhandler_3,
-		.ops = &irq_ops,
-		.global_mask = false,
-	},
-	{
-		.irq = IRQ_NUM_EXT_LEVEL4,
-		.handler = irqhandler_4,
-		.ops = &irq_ops,
-		.global_mask = false,
-	},
-	{
-		.name = "irqsteer1",
-		.irq = IRQ_NUM_EXT_LEVEL5,
-		.handler = irqhandler_5,
-		.ops = &irq_ops,
-		.global_mask = false,
-	},
-};
-
-void platform_interrupt_init(void)
-{
-	int i;
-
-	acp_intr_route();
-	/* disable all interrupts and their service routines */
-	acp_intr_disable();
-	for (i = 0; i < ARRAY_SIZE(dsp_irq); i++)
-		interrupt_cascade_register(dsp_irq + i);
-	acp_intr_enable();
-	acp_dsp_sw_intr_enable();
-}
-
-void platform_interrupt_set(uint32_t irq)
-{
-	arch_interrupt_set(irq);
-}
-
-void platform_interrupt_clear(uint32_t irq, uint32_t mask)
-{
-	switch (irq) {
-	case IRQ_NUM_TIMER0:
-	case IRQ_NUM_SOFTWARE0:
-	case IRQ_NUM_EXT_LEVEL3:
-	case IRQ_NUM_EXT_LEVEL4:
-	case IRQ_NUM_EXT_LEVEL5:
-		arch_interrupt_clear(irq);
-		break;
-	default:
-		break;
-	}
-}
-
-uint32_t platform_interrupt_get_enabled(void)
-{
-	/* TODO */
-	return 0;
-}
-
-void interrupt_mask(uint32_t irq, unsigned int cpu)
-{
-	arch_interrupt_clear(irq);
-}
-
-void interrupt_unmask(uint32_t irq, unsigned int cpu)
-{
-	arch_interrupt_set(irq);
-}
-
-void acp_intr_route(void)
-{
-	dsp_interrupt_routing_ctrl_0_t interrupt_rout_cntl_0;
-	dsp_interrupt_routing_ctrl_1_t interrupt_rout_cntl_1;
-
-	/* Routing the particular interrupts to the particular level */
-	interrupt_rout_cntl_0 = (dsp_interrupt_routing_ctrl_0_t)io_reg_read
-				((PU_REGISTER_BASE + DSP_INTERRUPT_ROUTING_CTRL_0));
-	interrupt_rout_cntl_0.bits.dma_intr_level	= acp_interrupt_level_5;
-	interrupt_rout_cntl_0.bits.az_sw_i2s_intr_level	 = acp_interrupt_level_5;
-	io_reg_write((PU_REGISTER_BASE + DSP_INTERRUPT_ROUTING_CTRL_0),
-		     interrupt_rout_cntl_0.u32all);
-
-	interrupt_rout_cntl_1 = (dsp_interrupt_routing_ctrl_1_t)io_reg_read
-				((PU_REGISTER_BASE + DSP_INTERRUPT_ROUTING_CTRL_1));
-	interrupt_rout_cntl_1.bits.host_to_dsp_intr1_level = acp_interrupt_level_3;
-	interrupt_rout_cntl_1.bits.wov_intr_level	 = acp_interrupt_level_4;
-	io_reg_write((PU_REGISTER_BASE + DSP_INTERRUPT_ROUTING_CTRL_1),
-		     interrupt_rout_cntl_1.u32all);
-}
-
-void acp_dsp_sw_intr_enable(void)
-{
-	acp_dsp_sw_intr_cntl_t  sw_intr_ctrl_reg;
-
-	xthal_set_intclear(IRQ_NUM_EXT_LEVEL5);
-	sw_intr_ctrl_reg = (acp_dsp_sw_intr_cntl_t)io_reg_read((PU_REGISTER_BASE +
-							ACP_DSP_SW_INTR_CNTL));
-	sw_intr_ctrl_reg.bits.dsp0_to_host_intr_mask   = INTERRUPT_ENABLE;
-	/* Write the Software Interrupt controller register */
-	io_reg_write((PU_REGISTER_BASE + ACP_DSP_SW_INTR_CNTL), sw_intr_ctrl_reg.u32all);
-	/* Enabling software interuppts */
-	platform_interrupt_set(IRQ_NUM_EXT_LEVEL3);
-}
-
-void acp_intr_enable(void)
-{
-	acp_dsp0_intr_cntl_t interrupt_cntl;
-	acp_dsp0_intr_stat_t interrupt_sts;
-	acp_external_intr_enb_t ext_interrupt_enb;
-
-	platform_interrupt_clear(IRQ_NUM_EXT_LEVEL5, 0);
-	platform_interrupt_clear(IRQ_NUM_TIMER0, 0);
-	interrupt_sts.u32all = 0;
-	/* Clear status of all interrupts in ACP_DSP0_INTR_STAT register */
-	interrupt_sts.bits.dmaiocstat		 = 0xFF;
-	interrupt_sts.bits.audio_buffer_int_stat = 0x3F;
-	interrupt_sts.bits.wov_dma_stat		 = INTERRUPT_ENABLE;
-	io_reg_write((PU_REGISTER_BASE + ACP_DSP0_INTR_STAT),
-		     interrupt_sts.u32all);
-	/* Disable the ACP to Host interrupts */
-	ext_interrupt_enb.bits.acpextintrenb = INTERRUPT_ENABLE;
-	io_reg_write((PU_REGISTER_BASE + ACP_EXTERNAL_INTR_ENB),
-		     ext_interrupt_enb.u32all);
-	interrupt_cntl = (acp_dsp0_intr_cntl_t)io_reg_read((PU_REGISTER_BASE +
-							ACP_DSP0_INTR_CNTL));
-	interrupt_cntl.u32all = 0;
-	io_reg_write((PU_REGISTER_BASE + ACP_DSP0_INTR_CNTL), interrupt_cntl.u32all);
-	interrupt_cntl.bits.dmaiocmask			= 0xFF;
-	interrupt_cntl.bits.audio_buffer_int_mask	= INTERRUPT_DISABLE;
-	interrupt_cntl.bits.wov_dma_intr_mask		= INTERRUPT_DISABLE;
-	io_reg_write((PU_REGISTER_BASE + ACP_DSP0_INTR_CNTL), interrupt_cntl.u32all);
-	platform_interrupt_set(IRQ_NUM_EXT_LEVEL5);
-	platform_interrupt_set(IRQ_NUM_EXT_LEVEL4);
-}
-
-void acp_intr_disable(void)
-{
-	acp_dsp0_intr_stat_t interrupt_status;
-	acp_external_intr_enb_t ext_interrupt_enb;
-	acp_dsp0_intr_cntl_t interrupt_cntl;
-
-	interrupt_status = (acp_dsp0_intr_stat_t)io_reg_read((PU_REGISTER_BASE +
-							ACP_DSP0_INTR_STAT));
-	/* Check and Clear all the Interrupt status bits */
-	interrupt_status.bits.dmaiocstat		= 0xFF;
-	interrupt_status.bits.audio_buffer_int_stat	= 0x3F;
-	interrupt_status.bits.wov_dma_stat		= INTERRUPT_ENABLE;
-	io_reg_write((PU_REGISTER_BASE + ACP_DSP0_INTR_STAT), interrupt_status.u32all);
-
-	/* Disable the ACP to Host interrupts */
-	ext_interrupt_enb.bits.acpextintrenb = INTERRUPT_CLEAR;
-	io_reg_write((PU_REGISTER_BASE + ACP_EXTERNAL_INTR_ENB),  ext_interrupt_enb.u32all);
-	/* Disable all the required ACP interrupts
-	 * in acp_dsp0_intr_cntl_t register
-	 */
-	interrupt_cntl = (acp_dsp0_intr_cntl_t)io_reg_read((PU_REGISTER_BASE +
-							ACP_DSP0_INTR_CNTL));
-	interrupt_cntl.bits.dmaiocmask			= INTERRUPT_DISABLE;
-	interrupt_cntl.bits.audio_buffer_int_mask	= INTERRUPT_DISABLE;
-	interrupt_cntl.bits.wov_dma_intr_mask		= INTERRUPT_DISABLE;
-	io_reg_write((PU_REGISTER_BASE + ACP_DSP0_INTR_CNTL),  interrupt_cntl.u32all);
-	platform_interrupt_clear(IRQ_NUM_EXT_LEVEL5, 0);
-	platform_interrupt_clear(IRQ_NUM_EXT_LEVEL3, 0);
-	platform_interrupt_clear(IRQ_NUM_EXT_LEVEL4, 0);
-	platform_interrupt_clear(IRQ_NUM_TIMER1, 0);
-	platform_interrupt_clear(IRQ_NUM_TIMER0, 0);
-}
-
-void acp_dsp_sw_intr_disable(void)
-{
-	acp_dsp_sw_intr_cntl_t  sw_intr_ctrl_reg;
-	/* Read the register */
-	sw_intr_ctrl_reg = (acp_dsp_sw_intr_cntl_t)io_reg_read((PU_REGISTER_BASE +
-							ACP_DSP_SW_INTR_CNTL));
-	sw_intr_ctrl_reg.bits.dsp0_to_host_intr_mask = INTERRUPT_DISABLE;
-	/* Write the Software Interrupt controller register */
-	io_reg_write((PU_REGISTER_BASE + ACP_DSP_SW_INTR_CNTL), sw_intr_ctrl_reg.u32all);
-	platform_interrupt_clear(IRQ_NUM_EXT_LEVEL3, 0);
-}
-
-/* This function triggers a host interrupt from ACP DSP */
-void acp_dsp_to_host_intr_trig(void)
-{
-	acp_sw_intr_trig_t  sw_intr_trig;
-	/* Read the Software Interrupt controller register and update */
-	sw_intr_trig = (acp_sw_intr_trig_t)io_reg_read(PU_REGISTER_BASE + ACP_SW_INTR_TRIG);
-	/* Configures the trigger bit in ACP_DSP_SW_INTR_TRIG register */
-	sw_intr_trig.bits.trig_dsp0_to_host_intr = INTERRUPT_ENABLE;
-	/* Write the Software Interrupt controller register */
-	io_reg_write((PU_REGISTER_BASE + ACP_SW_INTR_TRIG), sw_intr_trig.u32all);
-}
-
-/* Clear the Acknowledge ( status) for the host to DSP interrupt */
-void acp_ack_intr_from_host(void)
-{
-	/* acknowledge the host interrupt */
-	acp_dsp_sw_intr_stat_t sw_intr_stat;
-
-	sw_intr_stat = (acp_dsp_sw_intr_stat_t)io_reg_read(PU_REGISTER_BASE +
-							ACP_DSP_SW_INTR_STAT);
-	sw_intr_stat.bits.host_to_dsp0_intr1_stat = INTERRUPT_ENABLE;
-	io_reg_write((PU_REGISTER_BASE + ACP_DSP_SW_INTR_STAT), sw_intr_stat.u32all);
-}
diff --git a/src/drivers/amd/vangogh/ipc.c b/src/drivers/amd/vangogh/ipc.c
deleted file mode 100644
index 05f3de709310..000000000000
--- a/src/drivers/amd/vangogh/ipc.c
+++ /dev/null
@@ -1,147 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-//
-//Copyright(c) 2023 AMD. All rights reserved.
-//
-//Author:       Basavaraj Hiregoudar <basavaraj.hiregoudar@amd.com>
-//              SaiSurya, Ch <saisurya.chakkaveeravenkatanaga@amd.com>
-
-#include <rtos/panic.h>
-#include <xtensa/core-macros.h>
-#include <platform/chip_offset_byte.h>
-#include <platform/chip_registers.h>
-#include <rtos/interrupt.h>
-#include <sof/ipc/driver.h>
-#include <sof/ipc/msg.h>
-#include <sof/ipc/schedule.h>
-#include <rtos/alloc.h>
-#include <sof/lib/dma.h>
-#include <sof/lib/mailbox.h>
-#include <sof/lib/memory.h>
-#include <sof/lib/uuid.h>
-#include <rtos/wait.h>
-#include <sof/list.h>
-#include <sof/platform.h>
-#include <sof/schedule/edf_schedule.h>
-#include <sof/schedule/schedule.h>
-#include <rtos/task.h>
-#include <rtos/spinlock.h>
-#include <ipc/header.h>
-#include <ipc/topology.h>
-#include <errno.h>
-#include <stddef.h>
-#include <stdint.h>
-#include <platform/platform.h>
-#include <platform/ipc.h>
-
-volatile acp_scratch_mem_config_t *pscratch_mem_cfg = (volatile acp_scratch_mem_config_t *)
-						      (PU_SCRATCH_REG_BASE + SCRATCH_REG_OFFSET);
-
-void amd_irq_handler(void *arg)
-{
-	struct ipc *ipc = arg;
-	uint32_t status;
-	uint32_t lock;
-	acp_dsp_sw_intr_stat_t swintrstat;
-	acp_sw_intr_trig_t  swintrtrig;
-
-	swintrstat = (acp_dsp_sw_intr_stat_t)io_reg_read(PU_REGISTER_BASE + ACP_DSP_SW_INTR_STAT);
-	status = swintrstat.u32all &  HOST_TO_DSP_INTR;
-	if (status) {
-		/* Interrupt source */
-		if (sof_ipc_host_status()) {
-			lock = io_reg_read(PU_REGISTER_BASE + ACP_AXI2DAGB_SEM_0);
-			while (lock)
-				lock = io_reg_read(PU_REGISTER_BASE + ACP_AXI2DAGB_SEM_0);
-			/* Check if it is response from host */
-			if (sof_ipc_host_ack_flag()) {
-				/* Clear the ACK from host  */
-				sof_ipc_host_ack_clear();
-				/* Clear the Host to DSP Status Register */
-				acp_ack_intr_from_host();
-				/* Configures the trigger bit in ACP_DSP_SW_INTR_TRIG register */
-				swintrtrig = (acp_sw_intr_trig_t)
-					     io_reg_read(PU_REGISTER_BASE + ACP_SW_INTR_TRIG);
-				swintrtrig.bits.trig_host_to_dsp0_intr1	= INTERRUPT_DISABLE;
-				swintrtrig.bits.trig_dsp0_to_host_intr	= INTERRUPT_DISABLE;
-				io_reg_write((PU_REGISTER_BASE + ACP_SW_INTR_TRIG),
-					     swintrtrig.u32all);
-			}
-			/* Check if new message from host */
-			if (sof_ipc_host_msg_flag()) {
-				/* Clear the msg bit from host */
-				sof_ipc_host_msg_clear();
-				/* Clear the Host to DSP Status Register */
-				acp_ack_intr_from_host();
-				ipc_schedule_process(ipc);
-			}
-			io_reg_write((PU_REGISTER_BASE + ACP_AXI2DAGB_SEM_0), lock);
-		} else {
-			tr_err(&ipc_tr, "IPC:interrupt without setting flags host status 0x%x",
-			       sof_ipc_host_status());
-		}
-	}
-}
-
-void ipc_platform_complete_cmd(struct ipc *ipc)
-{
-	acp_sw_intr_trig_t  sw_intr_trig;
-
-	/* Set Dsp Ack for msg from host */
-	sof_ipc_dsp_ack_set();
-	/* Configures the trigger bit in ACP_DSP_SW_INTR_TRIG register */
-	sw_intr_trig = (acp_sw_intr_trig_t)
-		io_reg_read(PU_REGISTER_BASE + ACP_SW_INTR_TRIG);
-	sw_intr_trig.bits.trig_host_to_dsp0_intr1  = INTERRUPT_DISABLE;
-	sw_intr_trig.bits.trig_dsp0_to_host_intr = INTERRUPT_DISABLE;
-	io_reg_write((PU_REGISTER_BASE + ACP_SW_INTR_TRIG), sw_intr_trig.u32all);
-	/* now interrupt host to tell it we have sent a message */
-	acp_dsp_to_host_intr_trig();
-	/* Disable the trigger bit in ACP_DSP_SW_INTR_TRIG register */
-	sw_intr_trig = (acp_sw_intr_trig_t)io_reg_read(PU_REGISTER_BASE + ACP_SW_INTR_TRIG);
-	sw_intr_trig.bits.trig_dsp0_to_host_intr = INTERRUPT_DISABLE;
-	io_reg_write((PU_REGISTER_BASE + ACP_SW_INTR_TRIG), sw_intr_trig.u32all);
-	if (ipc->pm_prepare_D3) {
-		while (1)
-			wait_for_interrupt(0);
-	}
-}
-
-int ipc_platform_send_msg(const struct ipc_msg *msg)
-{
-	int ret = 0;
-	acp_sw_intr_trig_t  sw_intr_trig;
-	acp_dsp_sw_intr_stat_t sw_intr_stat;
-	uint32_t status;
-	uint32_t lock;
-	/* Check if host cleared the status for previous messages */
-	sw_intr_stat = (acp_dsp_sw_intr_stat_t)
-		io_reg_read(PU_REGISTER_BASE + ACP_DSP_SW_INTR_STAT);
-	status =  sw_intr_stat.bits.dsp0_to_host_intr_stat;
-	if (sof_ipc_dsp_status() || status) {
-		sw_intr_stat = (acp_dsp_sw_intr_stat_t)
-				io_reg_read(PU_REGISTER_BASE + ACP_DSP_SW_INTR_STAT);
-		status =  sw_intr_stat.bits.dsp0_to_host_intr_stat;
-		return ret;
-	}
-	lock = io_reg_read(PU_REGISTER_BASE + ACP_AXI2DAGB_SEM_0);
-	while (lock)
-		lock = io_reg_read(PU_REGISTER_BASE + ACP_AXI2DAGB_SEM_0);
-	/* Write new message in the mailbox */
-	mailbox_dspbox_write(0, msg->tx_data, msg->tx_size);
-	/* Need to set DSP message flag */
-	sof_ipc_dsp_msg_set();
-	/* now interrupt host to tell it we have sent a message */
-	acp_dsp_to_host_intr_trig();
-	/* Disable the trigger bit in ACP_DSP_SW_INTR_TRIG register */
-	sw_intr_trig = (acp_sw_intr_trig_t)io_reg_read(PU_REGISTER_BASE + ACP_SW_INTR_TRIG);
-	sw_intr_trig.bits.trig_dsp0_to_host_intr = INTERRUPT_DISABLE;
-	io_reg_write((PU_REGISTER_BASE + ACP_SW_INTR_TRIG), sw_intr_trig.u32all);
-	io_reg_write((PU_REGISTER_BASE + ACP_AXI2DAGB_SEM_0), lock);
-	return ret;
-}
-
-void ipc_platform_send_msg_direct(const struct ipc_msg *msg)
-{
-	/* TODO: add support */
-}
-
diff --git a/src/drivers/dw/CMakeLists.txt b/src/drivers/dw/CMakeLists.txt
deleted file mode 100644
index ef1465b2d4ae..000000000000
--- a/src/drivers/dw/CMakeLists.txt
+++ /dev/null
@@ -1,13 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-
-if(CONFIG_DW_DMA)
-	add_local_sources(sof dma.c)
-endif()
-
-if(CONFIG_DW_GPIO)
-	add_local_sources(sof gpio.c)
-endif()
-
-if(CONFIG_DW_SPI)
-	add_local_sources(sof ssi-spi.c)
-endif()
diff --git a/src/drivers/dw/Kconfig b/src/drivers/dw/Kconfig
deleted file mode 100644
index 552139abc50b..000000000000
--- a/src/drivers/dw/Kconfig
+++ /dev/null
@@ -1,37 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-
-config DW
-	bool
-	default n
-	help
-	  This has to be selected if platform supports Designware features.
-
-if DW
-
-config DW_DMA
-	bool "Designware DMA driver"
-	default n
-	help
-	  Select this to enable support for the Designware DMA controller.
-
-config DW_DMA_AGGREGATED_IRQ
-	bool
-	default n
-	help
-	  Some platforms cannot register interrupt per DW-DMA channel
-	  and have the possibility only to register interrupts per
-	  DMA controller, which require manual handling of aggregated
-	  irq.
-
-	  Any platforms with DW-DMA aggregated interrupts support
-	  should set this.
-
-config DW_SPI
-	bool
-	default n
-
-config DW_GPIO
-	bool
-	default n
-
-endif # DW
diff --git a/src/drivers/dw/dma.c b/src/drivers/dw/dma.c
deleted file mode 100644
index d0c8158f0518..000000000000
--- a/src/drivers/dw/dma.c
+++ /dev/null
@@ -1,1173 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-//
-// Copyright(c) 2016 Intel Corporation. All rights reserved.
-//
-// Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
-//         Keyon Jie <yang.jie@linux.intel.com>
-
-/*
- * This driver API will only be called by 3 clients in sof :-
- *
- * 1. Host audio component. This component represents the ALSA PCM device
- *    and involves copying data to/from the host ALSA audio buffer to/from the
- *    the DSP buffer.
- *
- * 2. DAI audio component. This component represents physical DAIs and involves
- *    copying data to/from the DSP buffers to/from the DAI FIFOs.
- *
- * 3. IPC Layer. Some IPC needs DMA to copy audio buffer page table information
- *    from the host DRAM into DSP DRAM. This page table information is then
- *    used to construct the DMA configuration for the host client 1 above.
- */
-
-#include <rtos/atomic.h>
-#include <sof/audio/component.h>
-#include <rtos/bit.h>
-#include <sof/common.h>
-#include <sof/drivers/dw-dma.h>
-#include <rtos/interrupt.h>
-#include <rtos/timer.h>
-#include <rtos/alloc.h>
-#include <rtos/cache.h>
-#include <sof/lib/cpu.h>
-#include <sof/lib/dma.h>
-#include <sof/lib/memory.h>
-#include <sof/lib/pm_runtime.h>
-#include <rtos/wait.h>
-#include <sof/lib/notifier.h>
-#include <sof/platform.h>
-#include <rtos/spinlock.h>
-#include <ipc/topology.h>
-
-#include <errno.h>
-#include <stdbool.h>
-#include <stddef.h>
-#include <stdint.h>
-
-LOG_MODULE_REGISTER(dw_dma, CONFIG_SOF_LOG_LEVEL);
-
-SOF_DEFINE_REG_UUID(dw_dma);
-
-/* unused with Zephyr, generates no output */
-DECLARE_TR_CTX(dwdma_tr, SOF_UUID(dw_dma_uuid), LOG_LEVEL_INFO);
-
-/* pointer data for DW DMA buffer */
-struct dw_dma_ptr_data {
-	uint32_t current_ptr;
-	uint32_t start_ptr;
-	uint32_t end_ptr;
-	uint32_t hw_ptr;
-	uint32_t buffer_bytes;
-};
-
-/* data for each DW DMA channel */
-struct dw_dma_chan_data {
-	struct dw_lli *lli;
-	struct dw_lli *lli_current;
-	uint32_t cfg_lo;
-	uint32_t cfg_hi;
-	struct dw_dma_ptr_data ptr_data;	/* pointer data */
-};
-
-/* use array to get burst_elems for specific slot number setting.
- * the relation between msize and burst_elems should be
- * 2 ^ msize = burst_elems
- */
-static const uint32_t burst_elems[] = {1, 2, 4, 8};
-
-#if CONFIG_DMA_HW_LLI
-#define DW_DMA_BUFFER_PERIOD_COUNT	4
-#else
-#define DW_DMA_BUFFER_PERIOD_COUNT	2
-#endif
-
-static int dw_dma_stop(struct dma_chan_data *channel);
-
-static void dw_dma_interrupt_mask(struct dma_chan_data *channel)
-{
-	/* mask block, transfer and error interrupts for channel */
-	dma_reg_write(channel->dma, DW_MASK_TFR, DW_CHAN_MASK(channel->index));
-	dma_reg_write(channel->dma, DW_MASK_BLOCK,
-		      DW_CHAN_MASK(channel->index));
-	dma_reg_write(channel->dma, DW_MASK_ERR, DW_CHAN_MASK(channel->index));
-}
-
-static void dw_dma_interrupt_unmask(struct dma_chan_data *channel)
-{
-	/* unmask block, transfer and error interrupts for channel */
-#if CONFIG_DMA_HW_LLI
-	dma_reg_write(channel->dma, DW_MASK_BLOCK,
-		      DW_CHAN_UNMASK(channel->index));
-#else
-	dma_reg_write(channel->dma, DW_MASK_TFR,
-		      DW_CHAN_UNMASK(channel->index));
-#endif
-	dma_reg_write(channel->dma, DW_MASK_ERR,
-		      DW_CHAN_UNMASK(channel->index));
-}
-
-static void dw_dma_interrupt_clear(struct dma_chan_data *channel)
-{
-	/* clear transfer, block, src, dst and error interrupts for channel */
-	dma_reg_write(channel->dma, DW_CLEAR_TFR, DW_CHAN(channel->index));
-	dma_reg_write(channel->dma, DW_CLEAR_BLOCK, DW_CHAN(channel->index));
-	dma_reg_write(channel->dma, DW_CLEAR_SRC_TRAN, DW_CHAN(channel->index));
-	dma_reg_write(channel->dma, DW_CLEAR_DST_TRAN, DW_CHAN(channel->index));
-	dma_reg_write(channel->dma, DW_CLEAR_ERR, DW_CHAN(channel->index));
-}
-
-static uint32_t dw_dma_interrupt_status(struct dma_chan_data *channel)
-{
-	uint32_t status;
-
-#if CONFIG_DMA_HW_LLI
-	status = dma_reg_read(channel->dma, DW_STATUS_BLOCK);
-#else
-	status = dma_reg_read(channel->dma, DW_STATUS_TFR);
-#endif
-
-	return status & DW_CHAN(channel->index);
-}
-
-static void dw_dma_increment_pointer(struct dw_dma_chan_data *chan, int bytes)
-{
-	chan->ptr_data.current_ptr += bytes;
-	if (chan->ptr_data.current_ptr >= chan->ptr_data.end_ptr)
-		chan->ptr_data.current_ptr = chan->ptr_data.start_ptr +
-			(chan->ptr_data.current_ptr - chan->ptr_data.end_ptr);
-}
-
-#if !CONFIG_DMA_HW_LLI
-/* reload using LLI data from DMA IRQ cb */
-static inline void dw_dma_chan_reload_lli_cb(void *arg, enum notify_id type,
-					     void *data)
-{
-	struct dma_chan_data *channel = data;
-	struct dma *dma = channel->dma;
-	struct dw_dma_chan_data *dw_chan = dma_chan_get_data(channel);
-	struct dw_lli *lli = dw_chan->lli_current;
-
-	/* only need to reload if this is a block transfer */
-	if (!lli || !lli->llp) {
-		channel->status = COMP_STATE_PREPARE;
-		return;
-	}
-
-	/* channel not active */
-	if (channel->status != COMP_STATE_ACTIVE)
-		return;
-
-	/* channel still transferring previous lli */
-	if (dma_reg_read(dma, DW_DMA_CHAN_EN) & DW_CHAN(channel->index))
-		return;
-
-	/* get current and next block pointers */
-	lli = (struct dw_lli *)lli->llp;
-	dw_chan->lli_current = lli;
-
-	/* channel needs to start from scratch, so write SAR and DAR */
-	dma_reg_write(dma, DW_SAR(channel->index), lli->sar);
-	dma_reg_write(dma, DW_DAR(channel->index), lli->dar);
-
-	/* program CTL_LO and CTL_HI */
-	dma_reg_write(dma, DW_CTRL_LOW(channel->index), lli->ctrl_lo);
-	dma_reg_write(dma, DW_CTRL_HIGH(channel->index), lli->ctrl_hi);
-
-	/* program CFG_LO and CFG_HI */
-	dma_reg_write(dma, DW_CFG_LOW(channel->index), dw_chan->cfg_lo);
-	dma_reg_write(dma, DW_CFG_HIGH(channel->index), dw_chan->cfg_hi);
-
-	/* enable the channel */
-	dma_reg_write(dma, DW_DMA_CHAN_EN, DW_CHAN_UNMASK(channel->index));
-}
-#endif
-
-/* allocate next free DMA channel */
-static struct dma_chan_data *dw_dma_channel_get(struct dma *dma,
-						unsigned int req_chan)
-{
-	k_spinlock_key_t key;
-	int i;
-
-	tr_info(&dwdma_tr, "dw_dma_channel_get(): dma %d request channel %d",
-		dma->plat_data.id, req_chan);
-
-	key = k_spin_lock(&dma->lock);
-
-	/* find first free non draining channel */
-	for (i = 0; i < dma->plat_data.channels; i++) {
-
-		/* use channel if it's free */
-		if (dma->chan[i].status != COMP_STATE_INIT)
-			continue;
-
-		dma->chan[i].status = COMP_STATE_READY;
-
-		atomic_add(&dma->num_channels_busy, 1);
-#if !CONFIG_DMA_HW_LLI
-		notifier_register(&dma->chan[i], &dma->chan[i],
-				  NOTIFIER_ID_DMA_IRQ, dw_dma_chan_reload_lli_cb);
-#endif
-
-		/* return channel */
-		k_spin_unlock(&dma->lock, key);
-		return &dma->chan[i];
-	}
-
-	/* DMA controller has no free channels */
-	k_spin_unlock(&dma->lock, key);
-	tr_err(&dwdma_tr, "dw_dma_channel_get(): dma %d no free channels",
-	       dma->plat_data.id);
-
-	return NULL;
-}
-
-/* channel must not be running when this is called */
-static void dw_dma_channel_put_unlocked(struct dma_chan_data *channel)
-{
-	struct dw_dma_chan_data *dw_chan = dma_chan_get_data(channel);
-
-	dw_dma_interrupt_mask(channel);
-
-	/* disable linear link position */
-	platform_dw_dma_llp_disable(channel->dma, channel);
-
-	/* free the lli allocated by set_config*/
-	if (dw_chan->lli) {
-		rfree(dw_chan->lli);
-		dw_chan->lli = NULL;
-	}
-
-	notifier_unregister_all(NULL, channel);
-
-	/* set new state */
-	channel->status = COMP_STATE_INIT;
-	channel->desc_count = 0;
-	dw_chan->ptr_data.current_ptr = 0;
-	dw_chan->ptr_data.start_ptr = 0;
-	dw_chan->ptr_data.end_ptr = 0;
-	dw_chan->ptr_data.buffer_bytes = 0;
-	atomic_sub(&channel->dma->num_channels_busy, 1);
-}
-
-/* channel must not be running when this is called */
-static void dw_dma_channel_put(struct dma_chan_data *channel)
-{
-	k_spinlock_key_t key;
-
-	tr_info(&dwdma_tr, "dma %d channel %d put",
-		channel->dma->plat_data.id, channel->index);
-
-	key = k_spin_lock(&channel->dma->lock);
-	dw_dma_channel_put_unlocked(channel);
-	k_spin_unlock(&channel->dma->lock, key);
-}
-
-static int dw_dma_start(struct dma_chan_data *channel)
-{
-	struct dma *dma = channel->dma;
-	struct dw_dma_chan_data *dw_chan = dma_chan_get_data(channel);
-	struct dw_lli *lli = dw_chan->lli_current;
-	uint32_t flags;
-	int ret = 0;
-#if CONFIG_DMA_HW_LLI
-	uint32_t words_per_tfr = 0;
-#endif
-
-	tr_dbg(&dwdma_tr, "dma %d channel %d start",
-	       channel->dma->plat_data.id, channel->index);
-
-	irq_local_disable(flags);
-
-	/* check if channel idle, disabled and ready */
-	if ((channel->status != COMP_STATE_PREPARE &&
-	     channel->status != COMP_STATE_PAUSED) ||
-	    (dma_reg_read(dma, DW_DMA_CHAN_EN) & DW_CHAN(channel->index))) {
-		tr_err(&dwdma_tr, "dma %d channel %d not ready ena 0x%x status 0x%x",
-		       dma->plat_data.id, channel->index,
-		       dma_reg_read(dma, DW_DMA_CHAN_EN),
-		       channel->status);
-		ret = -EBUSY;
-		goto out;
-	}
-
-	/* is valid stream */
-	if (!dw_chan->lli) {
-		tr_err(&dwdma_tr, "dma %d channel %d invalid stream",
-		       dma->plat_data.id, channel->index);
-		ret = -EINVAL;
-		goto out;
-	}
-
-#if CONFIG_DMA_HW_LLI
-	/* LLP mode - write LLP pointer unless in scatter mode */
-	dma_reg_write(dma, DW_LLP(channel->index),
-		      (lli->ctrl_lo & (DW_CTLL_LLP_D_EN | DW_CTLL_LLP_S_EN)) ?
-		      (uint32_t)lli : 0);
-#endif
-	/* channel needs to start from scratch, so write SAR and DAR */
-	dma_reg_write(dma, DW_SAR(channel->index), lli->sar);
-	dma_reg_write(dma, DW_DAR(channel->index), lli->dar);
-
-	/* program CTL_LO and CTL_HI */
-	dma_reg_write(dma, DW_CTRL_LOW(channel->index), lli->ctrl_lo);
-	dma_reg_write(dma, DW_CTRL_HIGH(channel->index), lli->ctrl_hi);
-
-	/* program CFG_LO and CFG_HI */
-	dma_reg_write(dma, DW_CFG_LOW(channel->index), dw_chan->cfg_lo);
-	dma_reg_write(dma, DW_CFG_HIGH(channel->index), dw_chan->cfg_hi);
-
-#if CONFIG_DMA_HW_LLI
-	if (lli->ctrl_lo & DW_CTLL_D_SCAT_EN) {
-		words_per_tfr = (lli->ctrl_hi & DW_CTLH_BLOCK_TS_MASK) >>
-			((lli->ctrl_lo & DW_CTLL_DST_WIDTH_MASK) >>
-			DW_CTLL_DST_WIDTH_SHIFT);
-		dma_reg_write(dma, DW_DSR(channel->index),
-			      DW_DSR_DSC(words_per_tfr) |
-			      DW_DSR_DSI(words_per_tfr));
-	}
-#endif
-
-	/* assign core */
-	channel->core = cpu_get_id();
-
-	/* enable linear link position */
-	platform_dw_dma_llp_enable(dma, channel);
-
-	/* enable the channel */
-	channel->status = COMP_STATE_ACTIVE;
-	dma_reg_write(dma, DW_DMA_CHAN_EN, DW_CHAN_UNMASK(channel->index));
-
-out:
-	irq_local_enable(flags);
-
-	return ret;
-}
-
-static int dw_dma_release(struct dma_chan_data *channel)
-{
-	struct dw_dma_chan_data *dw_chan = dma_chan_get_data(channel);
-	uint32_t flags;
-
-	tr_info(&dwdma_tr, "dma %d channel %d release",
-		channel->dma->plat_data.id, channel->index);
-
-	irq_local_disable(flags);
-
-	/* get next lli for proper release */
-	dw_chan->lli_current = (struct dw_lli *)dw_chan->lli_current->llp;
-
-	/* prepare to start */
-	dw_dma_stop(channel);
-
-	irq_local_enable(flags);
-
-	return 0;
-}
-
-static int dw_dma_pause(struct dma_chan_data *channel)
-{
-	struct dw_dma_chan_data *dw_chan = dma_chan_get_data(channel);
-	struct dma *dma = channel->dma;
-	uint32_t flags;
-
-	tr_info(&dwdma_tr, "dma %d channel %d pause",
-		channel->dma->plat_data.id, channel->index);
-
-	irq_local_disable(flags);
-
-	if (channel->status != COMP_STATE_ACTIVE)
-		goto out;
-
-	dma_reg_write(dma, DW_CFG_LOW(channel->index),
-		      dw_chan->cfg_lo | DW_CFGL_SUSPEND);
-
-	/* pause the channel */
-	channel->status = COMP_STATE_PAUSED;
-
-out:
-	irq_local_enable(flags);
-
-	return 0;
-}
-
-static int dw_dma_stop(struct dma_chan_data *channel)
-{
-	struct dma *dma = channel->dma;
-	uint32_t flags;
-	int ret;
-
-#if CONFIG_DMA_HW_LLI || CONFIG_DMA_SUSPEND_DRAIN
-	struct dw_dma_chan_data *dw_chan = dma_chan_get_data(channel);
-#endif
-
-#if CONFIG_DMA_HW_LLI
-	struct dw_lli *lli = dw_chan->lli;
-	int i;
-#endif
-
-	tr_info(&dwdma_tr, "dma %d channel %d stop",
-		dma->plat_data.id, channel->index);
-
-	irq_local_disable(flags);
-
-	if (channel->status != COMP_STATE_ACTIVE &&
-	    channel->status != COMP_STATE_PAUSED)
-		goto out;
-
-#if CONFIG_DMA_SUSPEND_DRAIN
-	/* channel cannot be disabled right away, so first we need to
-	 * suspend it and drain the FIFO
-	 */
-	dma_reg_write(dma, DW_CFG_LOW(channel->index),
-		      dw_chan->cfg_lo | DW_CFGL_SUSPEND | DW_CFGL_DRAIN);
-
-	/* now we wait for FIFO to be empty */
-	ret = poll_for_register_delay(dma_base(dma) +
-				      DW_CFG_LOW(channel->index),
-				      DW_CFGL_FIFO_EMPTY,
-				      DW_CFGL_FIFO_EMPTY,
-				      DW_DMA_TIMEOUT);
-	if (ret < 0)
-		tr_err(&dwdma_tr, "dma %d channel %d timeout",
-		       dma->plat_data.id, channel->index);
-#endif
-
-	dma_reg_write(dma, DW_DMA_CHAN_EN, DW_CHAN_MASK(channel->index));
-
-	/* wait for channel to be disabled */
-	ret = poll_for_register_delay(dma_base(dma) + DW_DMA_CHAN_EN,
-				      DW_CHAN(channel->index), 0, DW_DMA_TIMEOUT);
-	if (ret < 0) {
-		tr_err(&dwdma_tr, "dma %d channel %d disable timeout",
-		       dma->plat_data.id, channel->index);
-		return -ETIMEDOUT;
-	}
-
-#if CONFIG_DMA_HW_LLI
-	for (i = 0; i < channel->desc_count; i++) {
-		lli->ctrl_hi &= ~DW_CTLH_DONE(1);
-		lli++;
-	}
-
-#ifndef __ZEPHYR__
-	dcache_writeback_region((__sparse_force void __sparse_cache *)dw_chan->lli,
-				sizeof(struct dw_lli) * channel->desc_count);
-#endif
-#endif
-
-	channel->status = COMP_STATE_PREPARE;
-
-out:
-	irq_local_enable(flags);
-
-	return 0;
-}
-
-/* fill in "status" with current DMA channel state and position */
-static int dw_dma_status(struct dma_chan_data *channel,
-			 struct dma_chan_status *status,
-			 uint8_t direction)
-{
-	status->state = channel->status;
-	status->r_pos = dma_reg_read(channel->dma, DW_SAR(channel->index));
-	status->w_pos = dma_reg_read(channel->dma, DW_DAR(channel->index));
-	status->timestamp = sof_cycle_get_64();
-
-	if (status->ipc_posn_data) {
-		uint32_t *llp = (uint32_t *)status->ipc_posn_data;
-
-		platform_dw_dma_llp_read(channel->dma, channel, llp, llp + 1);
-	}
-
-	return 0;
-}
-
-/* set the DMA channel configuration, source/target address, buffer sizes */
-static int dw_dma_set_config(struct dma_chan_data *channel,
-			     struct dma_sg_config *config)
-{
-	const struct dw_drv_plat_data *dp =
-		channel->dma->plat_data.drv_plat_data;
-	struct dw_dma_chan_data *dw_chan = dma_chan_get_data(channel);
-	struct dma_sg_elem *sg_elem;
-	struct dw_lli *lli_desc;
-	struct dw_lli *lli_desc_head;
-	struct dw_lli *lli_desc_tail;
-	uint16_t chan_class;
-	uint32_t msize = 3;/* default msize */
-	uint32_t flags;
-	int ret = 0;
-	int i;
-
-	tr_dbg(&dwdma_tr, "dma %d channel %d config",
-	       channel->dma->plat_data.id, channel->index);
-
-	irq_local_disable(flags);
-
-	chan_class = dp->chan[channel->index].class;
-
-	/* default channel config */
-	channel->direction = config->direction;
-	channel->is_scheduling_source = config->is_scheduling_source;
-	channel->period = config->period;
-	dw_chan->cfg_lo = DW_CFG_LOW_DEF;
-	dw_chan->cfg_hi = DW_CFG_HIGH_DEF;
-
-	if (!config->elem_array.count) {
-		tr_err(&dwdma_tr, "dma %d channel %d no elems",
-		       channel->dma->plat_data.id, channel->index);
-		ret = -EINVAL;
-		goto out;
-	}
-
-	if (config->irq_disabled &&
-	    config->elem_array.count < DW_DMA_CFG_NO_IRQ_MIN_ELEMS) {
-		tr_err(&dwdma_tr, "dma %d channel %d not enough elems for config with irq disabled %d",
-		       channel->dma->plat_data.id,
-		       channel->index, config->elem_array.count);
-		ret = -EINVAL;
-		goto out;
-	}
-
-	/* do we need to realloc descriptors */
-	if (config->elem_array.count != channel->desc_count) {
-
-		/*
-		 * Allocate descriptors for channel. They must be cache-line
-		 * size aligned to avoid corrupting adjacent memory when
-		 * synchronizing caches. Such corruption has been observed with
-		 * Zephyr. A generic fix will be implemented for all SOF DMA
-		 * allocations on Zephyr to always force cache-line size
-		 * alignment.
-		 */
-		rfree(dw_chan->lli);
-
-		dw_chan->lli = rmalloc(SOF_MEM_FLAG_KERNEL | SOF_MEM_FLAG_COHERENT | SOF_MEM_FLAG_DMA,
-				       sizeof(struct dw_lli) * config->elem_array.count);
-		if (!dw_chan->lli) {
-			tr_err(&dwdma_tr, "dma %d channel %d lli alloc failed",
-			       channel->dma->plat_data.id,
-			       channel->index);
-			/* allocation failed, so dw_chan->lli is now NULL; reset
-			 * the count to match it so a later config does not
-			 * bzero() a NULL pointer using a stale count
-			 */
-			channel->desc_count = 0;
-			ret = -ENOMEM;
-			goto out;
-		}
-
-		/* only commit the new count once the buffer is allocated */
-		channel->desc_count = config->elem_array.count;
-	}
-
-	/* initialise descriptors */
-	bzero(dw_chan->lli, sizeof(struct dw_lli) * channel->desc_count);
-	lli_desc = dw_chan->lli;
-	lli_desc_head = dw_chan->lli;
-	lli_desc_tail = dw_chan->lli + channel->desc_count - 1;
-
-	/* configure msize if burst_elems is set */
-	if (config->burst_elems) {
-		for (i = 0; i < ARRAY_SIZE(burst_elems); i++) {
-			if (burst_elems[i] == config->burst_elems) {
-				msize = i;
-				break;
-			}
-		}
-	}
-
-	dw_chan->ptr_data.buffer_bytes = 0;
-
-	/* fill in lli for the elems in the list */
-	for (i = 0; i < config->elem_array.count; i++) {
-		sg_elem = config->elem_array.elems + i;
-
-		/* write CTL_LO for each lli */
-		switch (config->src_width) {
-		case 2:
-			/* non peripheral copies are optimal using words */
-			switch (config->direction) {
-			case DMA_DIR_LMEM_TO_HMEM:
-			case DMA_DIR_HMEM_TO_LMEM:
-			case DMA_DIR_MEM_TO_MEM:
-				/* config the src tr width for 32 bit words */
-				lli_desc->ctrl_lo |= DW_CTLL_SRC_WIDTH(2);
-				break;
-			default:
-				/* config the src width for 16 bit samples */
-				lli_desc->ctrl_lo |= DW_CTLL_SRC_WIDTH(1);
-				break;
-			}
-			break;
-		case 4:
-			/* config the src tr width for 24, 32 bit samples */
-			lli_desc->ctrl_lo |= DW_CTLL_SRC_WIDTH(2);
-			break;
-		default:
-			tr_err(&dwdma_tr, "dma %d channel %d invalid src width %d",
-			       channel->dma->plat_data.id,
-			       channel->index, config->src_width);
-			ret = -EINVAL;
-			goto out;
-		}
-
-		switch (config->dest_width) {
-		case 2:
-			/* non peripheral copies are optimal using words */
-			switch (config->direction) {
-			case DMA_DIR_LMEM_TO_HMEM:
-			case DMA_DIR_HMEM_TO_LMEM:
-			case DMA_DIR_MEM_TO_MEM:
-				/* config the dest tr width for 32 bit words */
-				lli_desc->ctrl_lo |= DW_CTLL_DST_WIDTH(2);
-				break;
-			default:
-				/* config the dest width for 16 bit samples */
-				lli_desc->ctrl_lo |= DW_CTLL_DST_WIDTH(1);
-				break;
-			}
-			break;
-		case 4:
-			/* config the dest tr width for 24, 32 bit samples */
-			lli_desc->ctrl_lo |= DW_CTLL_DST_WIDTH(2);
-			break;
-		default:
-			tr_err(&dwdma_tr, "dma %d channel %d invalid dest width %d",
-			       channel->dma->plat_data.id,
-			       channel->index, config->dest_width);
-			ret = -EINVAL;
-			goto out;
-		}
-
-		lli_desc->ctrl_lo |= DW_CTLL_SRC_MSIZE(msize) |
-			DW_CTLL_DST_MSIZE(msize) |
-			DW_CTLL_INT_EN; /* enable interrupt */
-
-		/* config the SINC and DINC fields of CTL_LO,
-		 * SRC/DST_PER fields of CFG_HI
-		 */
-		switch (config->direction) {
-		case DMA_DIR_LMEM_TO_HMEM:
-			lli_desc->ctrl_lo |= DW_CTLL_FC_M2M | DW_CTLL_SRC_INC |
-				DW_CTLL_DST_INC;
-#if CONFIG_DMA_HW_LLI
-			lli_desc->ctrl_lo |=
-				DW_CTLL_LLP_S_EN | DW_CTLL_LLP_D_EN;
-#endif
-			break;
-		case DMA_DIR_HMEM_TO_LMEM:
-			lli_desc->ctrl_lo |= DW_CTLL_FC_M2M | DW_CTLL_SRC_INC |
-				DW_CTLL_DST_INC;
-#if CONFIG_DMA_HW_LLI
-			lli_desc->ctrl_lo |=
-				DW_CTLL_LLP_S_EN | DW_CTLL_LLP_D_EN;
-#endif
-			break;
-		case DMA_DIR_MEM_TO_MEM:
-			lli_desc->ctrl_lo |= DW_CTLL_FC_M2M | DW_CTLL_SRC_INC |
-				DW_CTLL_DST_INC;
-#if CONFIG_DMA_HW_LLI
-			lli_desc->ctrl_lo |=
-				DW_CTLL_LLP_S_EN | DW_CTLL_LLP_D_EN;
-#endif
-			break;
-		case DMA_DIR_MEM_TO_DEV:
-			lli_desc->ctrl_lo |= DW_CTLL_FC_M2P | DW_CTLL_SRC_INC |
-				DW_CTLL_DST_FIX;
-#if CONFIG_DMA_HW_LLI
-			lli_desc->ctrl_lo |= DW_CTLL_LLP_S_EN;
-			dw_chan->cfg_lo |= DW_CFG_RELOAD_DST;
-#endif
-			dw_chan->cfg_hi |= DW_CFGH_DST(config->dest_dev);
-			platform_dw_dma_llp_config(channel->dma, channel,
-						   config->dest_dev);
-			break;
-		case DMA_DIR_DEV_TO_MEM:
-			lli_desc->ctrl_lo |= DW_CTLL_FC_P2M | DW_CTLL_SRC_FIX |
-				DW_CTLL_DST_INC;
-#if CONFIG_DMA_HW_LLI
-			if (!config->scatter)
-				lli_desc->ctrl_lo |= DW_CTLL_LLP_D_EN;
-			else
-				/* Use contiguous auto-reload. Line 3 in
-				 * table 3-3
-				 */
-				lli_desc->ctrl_lo |= DW_CTLL_D_SCAT_EN;
-			dw_chan->cfg_lo |= DW_CFG_RELOAD_SRC;
-#endif
-			dw_chan->cfg_hi |= DW_CFGH_SRC(config->src_dev);
-			platform_dw_dma_llp_config(channel->dma, channel,
-						   config->src_dev);
-			break;
-		case DMA_DIR_DEV_TO_DEV:
-			lli_desc->ctrl_lo |= DW_CTLL_FC_P2P | DW_CTLL_SRC_FIX |
-				DW_CTLL_DST_FIX;
-#if CONFIG_DMA_HW_LLI
-			lli_desc->ctrl_lo |=
-				DW_CTLL_LLP_S_EN | DW_CTLL_LLP_D_EN;
-#endif
-			dw_chan->cfg_hi |= DW_CFGH_SRC(config->src_dev) |
-				DW_CFGH_DST(config->dest_dev);
-			break;
-		default:
-			tr_err(&dwdma_tr, "dma %d channel %d invalid direction %d",
-			       channel->dma->plat_data.id,
-			       channel->index, config->direction);
-			ret = -EINVAL;
-			goto out;
-		}
-
-		lli_desc->sar = sg_elem->src;
-		lli_desc->dar = sg_elem->dest;
-
-		if (sg_elem->size > DW_CTLH_BLOCK_TS_MASK) {
-			tr_err(&dwdma_tr, "dma %d channel %d block size too big %d",
-			       channel->dma->plat_data.id,
-			       channel->index, sg_elem->size);
-			ret = -EINVAL;
-			goto out;
-		}
-
-		/* set channel class */
-		platform_dw_dma_set_class(dw_chan, lli_desc, chan_class);
-
-		/* set transfer size of element */
-		platform_dw_dma_set_transfer_size(dw_chan, lli_desc,
-						  sg_elem->size);
-
-		dw_chan->ptr_data.buffer_bytes += sg_elem->size;
-
-		/* set next descriptor in list */
-		lli_desc->llp = (uint32_t)(lli_desc + 1);
-
-		/* next descriptor */
-		lli_desc++;
-	}
-
-#if CONFIG_DMA_HW_LLI
-	dw_chan->cfg_lo |= DW_CFG_CTL_HI_UPD_EN;
-#endif
-
-	/* end of list or cyclic buffer */
-	if (config->cyclic) {
-		lli_desc_tail->llp = (uint32_t)lli_desc_head;
-	} else {
-		lli_desc_tail->llp = 0;
-#if CONFIG_DMA_HW_LLI
-		lli_desc_tail->ctrl_lo &=
-			~(DW_CTLL_LLP_S_EN | DW_CTLL_LLP_D_EN);
-#endif
-	}
-
-	/* write back descriptors so DMA engine can read them directly */
-#ifndef __ZEPHYR__
-	dcache_writeback_region((__sparse_force void __sparse_cache *)dw_chan->lli,
-				sizeof(struct dw_lli) * channel->desc_count);
-#endif
-
-	channel->status = COMP_STATE_PREPARE;
-	dw_chan->lli_current = dw_chan->lli;
-
-	/* initialize pointers */
-	dw_chan->ptr_data.start_ptr = DW_DMA_LLI_ADDRESS(dw_chan->lli,
-							 channel->direction);
-	dw_chan->ptr_data.end_ptr = dw_chan->ptr_data.start_ptr +
-				    dw_chan->ptr_data.buffer_bytes;
-	dw_chan->ptr_data.current_ptr = dw_chan->ptr_data.start_ptr;
-	dw_chan->ptr_data.hw_ptr = dw_chan->ptr_data.start_ptr;
-
-out:
-	irq_local_enable(flags);
-
-	return ret;
-}
-
-static void dw_dma_verify_transfer(struct dma_chan_data *channel,
-				   struct dma_cb_data *next)
-{
-	struct dw_dma_chan_data *dw_chan = dma_chan_get_data(channel);
-#if CONFIG_DMA_HW_LLI
-#if defined __ZEPHYR__
-	int i;
-#else
-	struct dw_lli *lli = platform_dw_dma_lli_get(dw_chan->lli_current);
-#endif
-	switch (next->status) {
-	case DMA_CB_STATUS_END:
-		channel->status = COMP_STATE_PREPARE;
-		dma_reg_write(channel->dma, DW_DMA_CHAN_EN,
-			      DW_CHAN_MASK(channel->index));
-		/* fallthrough */
-	default:
-	/* default action is to clear the DONE bit for all LLI making
-	 * sure the cache is coherent between DSP and DMAC.
-	 */
-#if defined __ZEPHYR__
-		for (i = 0; i < channel->desc_count; i++)
-			dw_chan->lli[i].ctrl_hi &= ~DW_CTLH_DONE(1);
-#else
-		while (lli->ctrl_hi & DW_CTLH_DONE(1)) {
-			lli->ctrl_hi &= ~DW_CTLH_DONE(1);
-			dw_chan->lli_current =
-				(struct dw_lli *)dw_chan->lli_current->llp;
-			lli = platform_dw_dma_lli_get(dw_chan->lli_current);
-		}
-#endif
-		break;
-	}
-#else
-	/* check for reload channel:
-	 * next->status is DMA_CB_STATUS_END, stop this dma copy.
-	 */
-	switch (next->status) {
-	case DMA_CB_STATUS_END:
-		channel->status = COMP_STATE_PREPARE;
-		dw_chan->lli_current =
-			(struct dw_lli *)dw_chan->lli_current->llp;
-		break;
-	default:
-		break;
-	}
-#endif
-}
-
-static int dw_dma_copy(struct dma_chan_data *channel, int bytes,
-		       uint32_t flags)
-{
-	struct dw_dma_chan_data *dw_chan = dma_chan_get_data(channel);
-	int ret = 0;
-	struct dma_cb_data next = {
-		.channel = channel,
-		.elem = { .size = bytes },
-		.status = DMA_CB_STATUS_END,
-	};
-	k_spinlock_key_t key;
-
-	tr_dbg(&dwdma_tr, "dma %d channel %d copy",
-	       channel->dma->plat_data.id, channel->index);
-
-	notifier_event(channel, NOTIFIER_ID_DMA_COPY,
-		       NOTIFIER_TARGET_CORE_LOCAL, &next, sizeof(next));
-
-	if (flags & DMA_COPY_ONE_SHOT) {
-		/* for one shot copy start the DMA */
-		ret = dw_dma_start(channel);
-		if (ret < 0)
-			return ret;
-	}
-
-	if (flags & DMA_COPY_BLOCKING) {
-		/* wait for transfer finish */
-		ret = poll_for_register_delay(dma_base(channel->dma) +
-					      DW_DMA_CHAN_EN,
-					      DW_CHAN(channel->index), 0,
-					      DW_DMA_TIMEOUT);
-		if (ret < 0) {
-			tr_dbg(&dwdma_tr, "poll_for_register_delay timeout");
-			return ret;
-		}
-	}
-
-	dw_dma_verify_transfer(channel, &next);
-
-	/* increment current pointer */
-	key = k_spin_lock(&channel->dma->lock);
-	dw_dma_increment_pointer(dw_chan, bytes);
-	k_spin_unlock(&channel->dma->lock, key);
-
-	return ret;
-}
-
-static int dw_dma_setup(struct dma *dma)
-{
-	int i;
-
-	/* we cannot config DMAC if DMAC has been already enabled by host */
-	if (dma_reg_read(dma, DW_DMA_CFG))
-		dma_reg_write(dma, DW_DMA_CFG, 0);
-
-	/* now check that it's 0 */
-	for (i = DW_DMA_CFG_TRIES; i > 0; i--)
-		if (!dma_reg_read(dma, DW_DMA_CFG))
-			break;
-
-	if (!i) {
-		tr_err(&dwdma_tr, "dma %d setup failed",
-		       dma->plat_data.id);
-		return -EIO;
-	}
-
-	for (i = 0; i < dma->plat_data.channels; i++)
-		dma_reg_read(dma, DW_DMA_CHAN_EN);
-
-	/* enable the DMA controller */
-	dma_reg_write(dma, DW_DMA_CFG, 1);
-
-	/* mask all interrupts for all channels */
-	dma_reg_write(dma, DW_MASK_TFR, DW_CHAN_MASK_ALL);
-	dma_reg_write(dma, DW_MASK_BLOCK, DW_CHAN_MASK_ALL);
-	dma_reg_write(dma, DW_MASK_SRC_TRAN, DW_CHAN_MASK_ALL);
-	dma_reg_write(dma, DW_MASK_DST_TRAN, DW_CHAN_MASK_ALL);
-	dma_reg_write(dma, DW_MASK_ERR, DW_CHAN_MASK_ALL);
-
-#if CONFIG_DMA_FIFO_PARTITION
-	/* allocate FIFO partitions for each channel */
-	dma_reg_write(dma, DW_FIFO_PART1_HI,
-		      DW_FIFO_CHx(DW_FIFO_SIZE) | DW_FIFO_CHy(DW_FIFO_SIZE));
-	dma_reg_write(dma, DW_FIFO_PART1_LO,
-		      DW_FIFO_CHx(DW_FIFO_SIZE) | DW_FIFO_CHy(DW_FIFO_SIZE));
-	dma_reg_write(dma, DW_FIFO_PART0_HI,
-		      DW_FIFO_CHx(DW_FIFO_SIZE) | DW_FIFO_CHy(DW_FIFO_SIZE));
-	dma_reg_write(dma, DW_FIFO_PART0_LO,
-		      DW_FIFO_CHx(DW_FIFO_SIZE) | DW_FIFO_CHy(DW_FIFO_SIZE) |
-		      DW_FIFO_UPD);
-#endif
-
-	return 0;
-}
-
-static int dw_dma_probe(struct dma *dma)
-{
-	struct dma_chan_data *chan;
-	struct dw_dma_chan_data *dw_chan;
-	int ret;
-	int i;
-
-	if (dma->chan)
-		return -EEXIST; /* already created */
-
-	/* disable dynamic clock gating */
-	pm_runtime_get_sync(DW_DMAC_CLK, dma->plat_data.id);
-
-	/* allocate dma channels */
-	dma->chan = rzalloc(SOF_MEM_FLAG_KERNEL | SOF_MEM_FLAG_COHERENT,
-			    sizeof(struct dma_chan_data) * dma->plat_data.channels);
-
-	if (!dma->chan) {
-		tr_err(&dwdma_tr, "dma %d allocation of channels failed",
-		       dma->plat_data.id);
-		goto out;
-	}
-
-	ret = dw_dma_setup(dma);
-	if (ret < 0)
-		return ret;
-
-	/* init work */
-	for (i = 0, chan = dma->chan; i < dma->plat_data.channels;
-	     i++, chan++) {
-		chan->status = COMP_STATE_INIT;
-		chan->dma = dma;
-		chan->index = i;
-		chan->core = DMA_CORE_INVALID;
-
-		dw_chan = rzalloc(SOF_MEM_FLAG_KERNEL | SOF_MEM_FLAG_COHERENT,
-				  sizeof(*dw_chan));
-
-		if (!dw_chan) {
-			tr_err(&dwdma_tr, "dma %d allocation of channel %d private data failed",
-			       dma->plat_data.id, i);
-			goto out;
-		}
-
-		dma_chan_set_data(chan, dw_chan);
-	}
-
-	/* init number of channels draining */
-	atomic_init(&dma->num_channels_busy, 0);
-
-	return 0;
-
-out:
-	if (dma->chan) {
-		for (i = 0; i < dma->plat_data.channels; i++)
-			rfree(dma_chan_get_data(&dma->chan[i]));
-		rfree(dma->chan);
-		dma->chan = NULL;
-	}
-
-	return -ENOMEM;
-}
-
-static int dw_dma_remove(struct dma *dma)
-{
-	int i;
-
-	tr_dbg(&dwdma_tr, "dma %d remove", dma->plat_data.id);
-
-	pm_runtime_put_sync(DW_DMAC_CLK, dma->plat_data.id);
-
-	for (i = 0; i < dma->plat_data.channels; i++)
-		rfree(dma_chan_get_data(&dma->chan[i]));
-
-	rfree(dma->chan);
-	dma->chan = NULL;
-
-	return 0;
-}
-
-/* capture */
-static int dw_dma_avail_data_size(struct dma_chan_data *channel)
-{
-	struct dw_dma_chan_data *dw_chan = dma_chan_get_data(channel);
-	int32_t read_ptr = dw_chan->ptr_data.current_ptr;
-	int32_t write_ptr = dma_reg_read(channel->dma, DW_DAR(channel->index));
-	int32_t delta = write_ptr - dw_chan->ptr_data.hw_ptr;
-	int size;
-
-	dw_chan->ptr_data.hw_ptr = write_ptr;
-
-	size = write_ptr - read_ptr;
-	if (size < 0) {
-		size += dw_chan->ptr_data.buffer_bytes;
-	} else if (!size) {
-		/*
-		 * Buffer is either full or empty. If the DMA pointer has
-		 * changed, then the DMA has filled the buffer.
-		 */
-		if (delta)
-			size = dw_chan->ptr_data.buffer_bytes;
-		else
-			tr_info(&dwdma_tr, "size is 0!");
-	}
-
-	tr_dbg(&dwdma_tr, "DAR %x reader 0x%x free 0x%x avail 0x%x", write_ptr,
-	       read_ptr, dw_chan->ptr_data.buffer_bytes - size, size);
-
-	return size;
-}
-
-/* playback */
-static int dw_dma_free_data_size(struct dma_chan_data *channel)
-{
-	struct dw_dma_chan_data *dw_chan = dma_chan_get_data(channel);
-	int32_t read_ptr = dma_reg_read(channel->dma, DW_SAR(channel->index));
-	int32_t write_ptr = dw_chan->ptr_data.current_ptr;
-	int32_t delta = read_ptr - dw_chan->ptr_data.hw_ptr;
-	int size;
-
-	dw_chan->ptr_data.hw_ptr = read_ptr;
-
-	size = read_ptr - write_ptr;
-	if (size < 0) {
-		size += dw_chan->ptr_data.buffer_bytes;
-	} else if (!size) {
-		/*
-		 * Buffer is either full or empty. If the DMA pointer has
-		 * changed, then the DMA has emptied the buffer.
-		 */
-		if (delta)
-			size = dw_chan->ptr_data.buffer_bytes;
-		else
-			tr_info(&dwdma_tr, "size is 0!");
-	}
-
-	tr_dbg(&dwdma_tr, "SAR %x writer 0x%x free 0x%x avail 0x%x", read_ptr,
-	       write_ptr, size, dw_chan->ptr_data.buffer_bytes - size);
-
-	return size;
-}
-
-static int dw_dma_get_data_size(struct dma_chan_data *channel,
-				uint32_t *avail, uint32_t *free)
-{
-	struct dw_dma_chan_data *dw_chan = dma_chan_get_data(channel);
-	k_spinlock_key_t key;
-	int ret = 0;
-
-	tr_dbg(&dwdma_tr, "dma %d channel %d get data size",
-	       channel->dma->plat_data.id, channel->index);
-
-	key = k_spin_lock(&channel->dma->lock);
-
-	if (channel->direction == DMA_DIR_HMEM_TO_LMEM ||
-	    channel->direction == DMA_DIR_DEV_TO_MEM) {
-		*avail = dw_dma_avail_data_size(channel);
-		*free = dw_chan->ptr_data.buffer_bytes - *avail;
-	} else {
-		*free = dw_dma_free_data_size(channel);
-		*avail = dw_chan->ptr_data.buffer_bytes - *free;
-	}
-
-	k_spin_unlock(&channel->dma->lock, key);
-
-#if CONFIG_DMA_HW_LLI
-	if (!(dma_reg_read(channel->dma, DW_DMA_CHAN_EN) &
-	      DW_CHAN(channel->index))) {
-		tr_err(&dwdma_tr, "xrun detected");
-		return -ENODATA;
-	}
-#endif
-
-	return ret;
-}
-
-static int dw_dma_get_attribute(struct dma *dma, uint32_t type,
-				uint32_t *value)
-{
-	int ret = 0;
-
-	switch (type) {
-	case DMA_ATTR_BUFFER_ALIGNMENT:
-		*value = DW_DMA_BUFFER_ALIGNMENT;
-		break;
-	case DMA_ATTR_COPY_ALIGNMENT:
-		*value = DW_DMA_COPY_ALIGNMENT;
-		break;
-	case DMA_ATTR_BUFFER_ADDRESS_ALIGNMENT:
-		*value = PLATFORM_DCACHE_ALIGN;
-		break;
-	case DMA_ATTR_BUFFER_PERIOD_COUNT:
-		*value = DW_DMA_BUFFER_PERIOD_COUNT;
-		break;
-	default:
-		ret = -EINVAL;
-		break;
-	}
-
-	return ret;
-}
-
-static int dw_dma_interrupt(struct dma_chan_data *channel, enum dma_irq_cmd cmd)
-{
-	int ret = 0;
-
-	switch (cmd) {
-	case DMA_IRQ_STATUS_GET:
-		ret = dw_dma_interrupt_status(channel);
-		break;
-	case DMA_IRQ_CLEAR:
-		dw_dma_interrupt_clear(channel);
-		break;
-	case DMA_IRQ_MASK:
-		dw_dma_interrupt_mask(channel);
-		break;
-	case DMA_IRQ_UNMASK:
-		dw_dma_interrupt_unmask(channel);
-		break;
-	default:
-		ret = -EINVAL;
-		break;
-	}
-
-	return ret;
-}
-
-const struct dma_ops dw_dma_ops = {
-	.channel_get		= dw_dma_channel_get,
-	.channel_put		= dw_dma_channel_put,
-	.start			= dw_dma_start,
-	.stop			= dw_dma_stop,
-	.pause			= dw_dma_pause,
-	.release		= dw_dma_release,
-	.copy			= dw_dma_copy,
-	.status			= dw_dma_status,
-	.set_config		= dw_dma_set_config,
-	.probe			= dw_dma_probe,
-	.remove			= dw_dma_remove,
-	.get_data_size		= dw_dma_get_data_size,
-	.get_attribute		= dw_dma_get_attribute,
-	.interrupt		= dw_dma_interrupt,
-};
diff --git a/src/drivers/dw/gpio.c b/src/drivers/dw/gpio.c
deleted file mode 100644
index f8340ea23bca..000000000000
--- a/src/drivers/dw/gpio.c
+++ /dev/null
@@ -1,72 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-//
-// Copyright(c) 2019 Intel Corporation. All rights reserved.
-//
-// Author: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
-
-#include <sof/drivers/gpio.h>
-#include <sof/drivers/iomux.h>
-#include <sof/lib/io.h>
-#include <sof/lib/memory.h>
-#include <errno.h>
-#include <stddef.h>
-#include <stdint.h>
-
-#define PORTA_DAT_REG	0x00
-#define PORTA_DIR_REG	0x04
-#define PORTA_CTL_REG	0x08
-
-struct gpio {
-	uint32_t base;
-};
-
-static struct gpio dw_gpio = {
-	.base = DW_GPIO_BASE,
-};
-
-int gpio_write(const struct gpio *gpio, unsigned int port,
-	       enum gpio_level level)
-{
-	io_reg_update_bits(gpio->base + PORTA_DAT_REG, 1 << port,
-			   (level == GPIO_LEVEL_HIGH) << port);
-
-	return 0;
-}
-
-int gpio_read(const struct gpio *gpio, unsigned int port)
-{
-	return ((io_reg_read(gpio->base + PORTA_DAT_REG) >> port) & 1) ?
-		GPIO_LEVEL_HIGH : GPIO_LEVEL_LOW;
-}
-
-int gpio_configure(const struct gpio *gpio, unsigned int port,
-		   const struct gpio_config *config)
-{
-	const struct gpio_pin_config *gpio_cfg = gpio_data + port;
-	const struct iomux_pin_config *pin_cfg = &gpio_cfg->mux_config;
-	struct iomux *mux = iomux_get(gpio_cfg->mux_id);
-	int ret;
-
-	if (!mux)
-		return -ENODEV;
-
-	ret = iomux_configure(mux, pin_cfg);
-	if (ret < 0)
-		return ret;
-
-	/* set the direction of GPIO */
-	io_reg_update_bits(gpio->base + PORTA_DIR_REG, 1 << port,
-			(config->direction == GPIO_DIRECTION_OUTPUT) << port);
-
-	return 0;
-}
-
-const struct gpio *gpio_get(unsigned int id)
-{
-	return id ? NULL : &dw_gpio;
-}
-
-int gpio_probe(const struct gpio *gpio)
-{
-	return gpio == &dw_gpio ? 0 : -ENODEV;
-}
diff --git a/src/drivers/dw/ssi-spi.c b/src/drivers/dw/ssi-spi.c
deleted file mode 100644
index 364ea9d19b9c..000000000000
--- a/src/drivers/dw/ssi-spi.c
+++ /dev/null
@@ -1,535 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-//
-// Copyright(c) 2017 Intel Corporation. All rights reserved.
-//
-// Author: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
-
-#include <sof/common.h>
-#include <rtos/panic.h>
-#include <sof/drivers/gpio.h>
-#include <sof/ipc/driver.h>
-#include <sof/ipc/schedule.h>
-#include <sof/drivers/spi.h>
-#include <rtos/alloc.h>
-#include <rtos/cache.h>
-#include <rtos/clk.h>
-#include <sof/lib/dma.h>
-#include <sof/lib/io.h>
-#include <sof/lib/mailbox.h>
-#include <sof/lib/memory.h>
-#include <sof/lib/uuid.h>
-#include <rtos/wait.h>
-#include <sof/platform.h>
-#include <sof/schedule/ll_schedule.h>
-#include <sof/schedule/schedule.h>
-#include <rtos/task.h>
-#include <rtos/spinlock.h>
-#include <rtos/string.h>
-#include <ipc/header.h>
-#include <ipc/topology.h>
-#include <stddef.h>
-#include <stdint.h>
-
-SOF_DEFINE_REG_UUID(spi_completion);
-
-#define	SPI_REG_CTRLR0		0x00
-#define	SPI_REG_CTRLR1		0x04
-#define	SPI_REG_SSIENR		0x08
-#define	SPI_REG_MWCR		0x0C
-#define	SPI_REG_SER		0x10
-#define	SPI_REG_BAUDR		0x14
-#define	SPI_REG_TXFTLR		0x18
-#define	SPI_REG_RXFTLR		0x1C
-#define	SPI_REG_TXFLR		0x20
-#define	SPI_REG_RXFLR		0x24
-#define	SPI_REG_SR		0x28
-#define	SPI_REG_IMR		0x2C
-#define	SPI_REG_ISR		0x30
-#define	SPI_REG_RISR		0x34
-#define	SPI_REG_TXOICR		0x38
-#define	SPI_REG_RXOICR		0x3C
-#define	SPI_REG_RXUICR		0x40
-#define	SPI_REG_ICR		0x48
-#define	SPI_REG_DMACR		0x4C
-#define	SPI_REG_DMATDLR		0x50
-#define	SPI_REG_DMARDLR		0x54
-#define	SPI_REG_DR		0x60
-#define	SPI_REG_SPICTRLR0	0xF4
-
-#define SPI_BUFFER_SIZE		256
-
-#define SSI_SLAVE_CLOCK_CTL	(EXT_CTRL_BASE + 0x60)
-
-/* CTRLR0 */
-/* 00-standard spi; 01-dual spi; 10-quad spi */
-#define SPI_FRAME_FORMAT(x)		(x << 21)
-#define SPI_DATA_FRAME_SIZE(x)		(x << 16)
-/* 0-slave tx enabled; 1-slave tx disabled */
-#define SPI_SLV_OE(x)			(x << 10)
-/* 00-both; 01-transmit only;
- * 10-receive only; 11-eeprom read
- */
-#define SPI_TRANSFER_MODE(x)		(x << 8)
-/* 0-inactive low; 1-inactive high */
-#define SPI_SCPOL(x)			(x << 7)
-/* 0-first edge capture; 1-one cycle after cs line */
-#define SPI_SCPH(x)			(x << 6)
-/* 00-moto spi; 01-ti ssp; 10-ns microwire */
-#define SPI_FRAME_TYPE(x)		(x << 4)
-
-/* SSIENR */
-#define SPI_SSIEN			1
-
-/* DMACR */
-/* 0-transmit DMA disable; 1-transmit DMA enable */
-#define	SPI_DMACR_TDMAE(x)		(x << 1)
-/* 0-receive DMA disable; 1-receive DMA enable */
-#define SPI_DMACR_RDMAE(x)		(x << 0)
-/* DMATDLR/DMARDLR */
-/* transmit data level: 0~255 */
-#define SPI_DMATDLR(x)			(x << 0)
-/* receive data level: 0~255 */
-#define SPI_DMARDLR(x)			(x << 0)
-
-enum {
-	SPI_TRIGGER_START,
-	SPI_TRIGGER_STOP,
-};
-
-/* SPI-Slave ISR's state machine: from the PoV of the DSP */
-enum IPC_STATUS {
-	IPC_READ,
-	IPC_WRITE,
-};
-
-struct spi_dma_config {
-	enum spi_xfer_direction dir;
-	void *src_buf;
-	void *dest_buf;
-	uint32_t buffer_size;
-	uint32_t transfer_len;
-};
-
-struct spi_reg_list {
-	uint32_t ctrlr0;
-	uint32_t dmacr;		/* dma control register */
-};
-
-struct spi {
-	const struct gpio *gpio;
-	uint32_t index;
-	struct dma_chan_data *chan[2];	/* spi-slave rx/tx dma */
-	uint32_t buffer_size;
-	uint8_t *rx_buffer;
-	uint8_t *tx_buffer;
-	struct dma *dma[2];
-	struct spi_reg_list reg;
-	const struct spi_platform_data *plat_data;
-	struct spi_dma_config config[2];
-	uint32_t ipc_status;
-	struct task completion;
-	struct sof_ipc_hdr hdr;
-};
-
-#define spi_fifo_handshake(spi, direction) \
-			spi->plat_data->fifo[direction].handshake
-#define spi_reg_write(spi, reg, val) \
-			io_reg_write(spi->plat_data->base + reg, val)
-
-static void spi_start(struct spi *spi, int direction)
-{
-	/* disable SPI first before config */
-	spi_reg_write(spi, SPI_REG_SSIENR, 0);
-
-	spi_reg_write(spi, SPI_REG_CTRLR0, spi->reg.ctrlr0);
-	spi_reg_write(spi, SPI_REG_IMR, 0);
-
-	/* Trigger interrupt at or above 1 entry in the RX FIFO */
-	spi_reg_write(spi, SPI_REG_RXFTLR, 1);
-	/* Trigger DMA at or above 1 entry in the RX FIFO */
-	spi_reg_write(spi, SPI_REG_DMARDLR, SPI_DMARDLR(1));
-
-	/* Trigger interrupt at or below 1 entry in the TX FIFO */
-	spi_reg_write(spi, SPI_REG_TXFTLR, 1);
-	/* Trigger DMA at or below 1 entry in the TX FIFO */
-	spi_reg_write(spi, SPI_REG_DMATDLR, SPI_DMATDLR(1));
-
-	spi_reg_write(spi, SPI_REG_DMACR, spi->reg.dmacr);
-	spi_reg_write(spi, SPI_REG_SSIENR, SPI_SSIEN);
-}
-
-static void spi_stop(struct spi *spi)
-{
-	spi_reg_write(spi, SPI_REG_DMACR,
-		     SPI_DMACR_TDMAE(0) | SPI_DMACR_RDMAE(0));
-	spi_reg_write(spi, SPI_REG_SSIENR, 0);
-}
-
-static void delay(unsigned int ms)
-{
-	wait_delay_ms(ms);
-}
-
-static int spi_trigger(struct spi *spi, int cmd, int direction)
-{
-	int ret;
-
-	switch (cmd) {
-	case SPI_TRIGGER_START:
-		/* trigger the SPI-Slave + DMA + INT + Receiving */
-		ret = dma_start_legacy(spi->chan[direction]);
-		if (ret < 0)
-			return ret;
-
-		/*
-		 * DMA seems to need some time before it can service a data
-		 * request from the SPI FIFO
-		 */
-		wait_delay(1);
-
-		spi_start(spi, direction);
-
-		break;
-	case SPI_TRIGGER_STOP:
-		/* Stop the SPI-Slave */
-		spi_stop(spi);
-		dma_stop_legacy(spi->chan[direction]);
-
-		break;
-	default:
-		return -EINVAL;
-	}
-
-	return 0;
-}
-
-/* Only enable one direction at a time: Rx or Tx */
-static inline void spi_config(struct spi *spi,
-			      const struct spi_dma_config *spi_cfg)
-{
-	switch (spi_cfg->dir) {
-	case SPI_DIR_RX:
-		spi->reg.ctrlr0 = SPI_FRAME_FORMAT(0)
-						| SPI_DATA_FRAME_SIZE(0x1f)
-						| SPI_TRANSFER_MODE(0x2)
-						| SPI_SCPOL(1)
-						| SPI_SLV_OE(1)
-						| SPI_SCPH(1)
-						| SPI_FRAME_TYPE(0);
-		spi->reg.dmacr	 = SPI_DMACR_RDMAE(1);
-		break;
-	case SPI_DIR_TX:
-		spi->reg.ctrlr0 = SPI_FRAME_FORMAT(0)
-						| SPI_DATA_FRAME_SIZE(0x1f)
-						| SPI_TRANSFER_MODE(0x1)
-						| SPI_SCPOL(1)
-						| SPI_SLV_OE(0)
-						| SPI_SCPH(1)
-						| SPI_FRAME_TYPE(0);
-		spi->reg.dmacr	 = SPI_DMACR_TDMAE(1);
-		break;
-	default:
-		break;
-	}
-}
-
-static int spi_slave_dma_set_config(struct spi *spi,
-				    const struct spi_dma_config *spi_cfg)
-{
-	struct dma_sg_config config = {
-		.src_width  = 4,
-		.dest_width = 4,
-	};
-	struct dma_sg_elem local_sg_elem;
-	struct dma_chan_data *chan = spi->chan[spi_cfg->dir];
-
-	/* dma config */
-
-	local_sg_elem.size = spi_cfg->transfer_len;
-
-	/*
-	 * Source and destination width is 32 bits, contrary to dw_apb_ssi note
-	 * on page 87
-	 */
-	switch (spi_cfg->dir) {
-	case SPI_DIR_RX:	/* HOST -> DSP */
-		config.direction	= DMA_DIR_DEV_TO_MEM;
-		config.scatter		= true;
-		config.src_dev		= spi_fifo_handshake(spi,
-							spi_cfg->dir);
-
-		local_sg_elem.dest	= (uint32_t)spi_cfg->dest_buf;
-		local_sg_elem.src	= spi->plat_data->base + SPI_REG_DR;
-		break;
-	case SPI_DIR_TX:	/* DSP -> HOST */
-		config.direction	= DMA_DIR_MEM_TO_DEV;
-		config.dest_dev		= spi_fifo_handshake(spi,
-							spi_cfg->dir);
-
-		local_sg_elem.dest	= spi->plat_data->base + SPI_REG_DR;
-		local_sg_elem.src	= (uint32_t)spi_cfg->src_buf;
-		break;
-	default:
-		return -EINVAL;
-	}
-
-	/* configure local DMA elem */
-	config.elem_array.count = 1;
-	config.elem_array.elems = &local_sg_elem;
-
-	return dma_set_config_legacy(chan, &config);
-}
-
-static int spi_set_config(struct spi *spi,
-			   const struct spi_dma_config *spi_cfg)
-{
-	/* spi slave config */
-	spi_config(spi, spi_cfg);
-
-	/* dma config */
-	return spi_slave_dma_set_config(spi, spi_cfg);
-}
-
-static enum task_state spi_completion_work(void *data)
-{
-	struct spi *spi = data;
-	struct sof_ipc_hdr *hdr;
-	struct spi_dma_config *config;
-
-	switch (spi->ipc_status) {
-	case IPC_READ:
-		hdr = (struct sof_ipc_hdr *)spi->rx_buffer;
-
-		dcache_invalidate_region((__sparse_force void __sparse_cache *)spi->rx_buffer,
-					 SPI_BUFFER_SIZE);
-		mailbox_hostbox_write(0, spi->rx_buffer, hdr->size);
-
-		ipc_schedule_process(ipc_get());
-
-		break;
-	case IPC_WRITE:	/* DSP -> HOST */
-		/*
-		 * Data has been transferred to the SPI FIFO, but we don't know
-		 * whether the master has read it all out yet. We might have to
-		 * wait here before reconfiguring the SPI controller
-		 */
-		spi_trigger(spi, SPI_TRIGGER_STOP, SPI_DIR_TX);
-
-		/* configure to receive next header */
-		spi->ipc_status = IPC_READ;
-		config = spi->config + SPI_DIR_RX;
-		config->transfer_len = ALIGN_UP_COMPILE(sizeof(*hdr), 16);
-		spi_set_config(spi, config);
-		spi_trigger(spi, SPI_TRIGGER_START, SPI_DIR_RX);
-
-		break;
-	}
-
-	return SOF_TASK_STATE_RESCHEDULE;
-}
-
-int spi_push(struct spi *spi, const void *data, size_t size)
-{
-	struct spi_dma_config *config = spi->config + SPI_DIR_TX;
-	int ret;
-
-	if (size > SPI_BUFFER_SIZE) {
-		tr_err(&ipc_tr, "ePs");
-		return -ENOBUFS;
-	}
-
-	ret = spi_trigger(spi, SPI_TRIGGER_STOP, SPI_DIR_RX);
-	if (ret < 0)
-		return ret;
-
-	/* configure transmit path of SPI-slave */
-	config->transfer_len = ALIGN_UP_COMPILE(size, 16);
-	ret = spi_set_config(spi, config);
-	if (ret < 0)
-		return ret;
-
-	spi->ipc_status = IPC_WRITE;
-
-	/* Actually we have to send IPC messages in one go */
-	ret = memcpy_s(config->src_buf, config->buffer_size, data, size);
-	assert(!ret);
-
-	dcache_writeback_region((__sparse_force void __sparse_cache *)config->src_buf, size);
-
-	ret = spi_trigger(spi, SPI_TRIGGER_START, SPI_DIR_TX);
-	if (ret < 0)
-		return ret;
-
-	/*
-	 * Tell the master to pull out the data, we aren't getting DMA
-	 * completion until all the prepared data has been transferred
-	 * to the SPI controller FIFO
-	 */
-	gpio_write(spi->gpio, PLATFORM_SPI_GPIO_IRQ, GPIO_LEVEL_HIGH);
-	delay(1);
-	gpio_write(spi->gpio, PLATFORM_SPI_GPIO_IRQ, GPIO_LEVEL_LOW);
-
-	return 0;
-}
-
-static int spi_slave_init(struct spi *spi)
-{
-	struct spi_dma_config *config = spi->config + SPI_DIR_RX;
-	struct gpio_config gpio_cfg = {.direction = GPIO_DIRECTION_OUTPUT};
-	int ret;
-
-	/* A GPIO to signal host IPC IRQ */
-	gpio_configure(spi->gpio, PLATFORM_SPI_GPIO_IRQ, &gpio_cfg);
-
-	bzero(spi->config, sizeof(spi->config));
-
-	/* configure receive path of SPI-slave */
-	config->dir = SPI_DIR_RX;
-	config->dest_buf = spi->rx_buffer;
-	config->transfer_len = ALIGN_UP_COMPILE(sizeof(struct sof_ipc_hdr), 16);
-
-	ret = spi_set_config(spi, config);
-	if (ret < 0)
-		return ret;
-
-	dcache_invalidate_region((__sparse_force void __sparse_cache *)spi->rx_buffer, SPI_BUFFER_SIZE);
-	ret = spi_trigger(spi, SPI_TRIGGER_START, SPI_DIR_RX);
-	if (ret < 0)
-		return ret;
-
-	/* prepare transmit path of SPI-slave */
-	config = spi->config + SPI_DIR_TX;
-	config->dir = SPI_DIR_TX;
-	config->src_buf = spi->tx_buffer;
-	config->buffer_size = spi->buffer_size;
-
-	spi->completion.priv_data = NULL;
-
-	ret = schedule_task_init_ll(&spi->completion,
-				    SOF_UUID(spi_compl_task_uuid),
-				    SOF_SCHEDULE_LL_DMA,
-				    SOF_TASK_PRI_MED, spi_completion_work,
-				    spi, 0, 0);
-	if (ret < 0)
-		return ret;
-
-	schedule_task(&spi->completion, 0, 100);
-
-	return 0;
-}
-
-int spi_probe(struct spi *spi)
-{
-	int ret;
-
-	spi->dma[SPI_DIR_RX] = dma_get(DMA_DIR_DEV_TO_MEM, DMA_CAP_GP_LP,
-				       DMA_DEV_SSI, DMA_ACCESS_SHARED);
-	if (!spi->dma[SPI_DIR_RX])
-		return -ENODEV;
-
-	spi->dma[SPI_DIR_TX] = dma_get(DMA_DIR_MEM_TO_DEV, DMA_CAP_GP_LP,
-				       DMA_DEV_SSI, DMA_ACCESS_SHARED);
-	if (!spi->dma[SPI_DIR_TX])
-		return -ENODEV;
-
-	spi->chan[SPI_DIR_RX] = dma_channel_get_legacy(spi->dma[SPI_DIR_RX], 0);
-	if (!spi->chan[SPI_DIR_RX])
-		return -ENODEV;
-
-	spi->chan[SPI_DIR_TX] = dma_channel_get_legacy(spi->dma[SPI_DIR_TX], 0);
-	if (!spi->chan[SPI_DIR_TX])
-		return -ENODEV;
-
-	spi->gpio = gpio_get(PLATFORM_SPI_GPIO_ID);
-	if (!spi->gpio)
-		return -ENODEV;
-
-	ret = gpio_probe(spi->gpio);
-	if (ret < 0)
-		return ret;
-
-	/* configure the spi clock */
-	io_reg_write(SSI_SLAVE_CLOCK_CTL, 0x00000001);
-
-	spi->rx_buffer = rzalloc(SOF_MEM_FLAG_KERNEL | SOF_MEM_FLAG_DMA,
-				 SPI_BUFFER_SIZE);
-	if (!spi->rx_buffer) {
-		tr_err(&ipc_tr, "eSp");
-		return -ENOMEM;
-	}
-
-	spi->tx_buffer = rzalloc(SOF_MEM_FLAG_KERNEL | SOF_MEM_FLAG_DMA,
-				 SPI_BUFFER_SIZE);
-	spi->buffer_size = SPI_BUFFER_SIZE;
-	if (!spi->tx_buffer) {
-		rfree(spi->rx_buffer);
-		tr_err(&ipc_tr, "eSp");
-		return -ENOMEM;
-	}
-
-	spi->ipc_status = IPC_READ;
-
-	return spi_slave_init(spi);
-}
-
-/* lock */
-struct k_spinlock spi_lock;
-static struct spi *spi_devices;
-static unsigned int n_spi_devices;
-
-struct spi *spi_get(enum spi_type type)
-{
-	struct spi *spi;
-	unsigned int i;
-	k_spinlock_key_t key;
-
-	key = k_spin_lock(&spi_lock);
-
-	for (i = 0, spi = spi_devices; i < n_spi_devices; i++, spi++)
-		if (spi->plat_data->type == type)
-			break;
-
-	k_spin_unlock(&spi_lock, key);
-
-	return i < n_spi_devices ? spi : NULL;
-}
-
-int spi_install(const struct spi_platform_data *plat, size_t n)
-{
-	struct spi *spi;
-	unsigned int i;
-	k_spinlock_key_t key;
-	int ret;
-
-	key = k_spin_lock(&spi_lock);
-
-	if (spi_devices) {
-		ret = -EBUSY;
-		goto unlock;
-	}
-
-	spi_devices = rmalloc(SOF_MEM_FLAG_KERNEL,
-			      sizeof(*spi) * n);
-	if (!spi_devices) {
-		ret = -ENOMEM;
-		goto unlock;
-	}
-
-	n_spi_devices = n;
-	ret = 0;
-
-	for (i = 0, spi = spi_devices; i < n; i++, spi++) {
-		spi->index = i;
-		spi->plat_data = plat + i;
-	}
-
-unlock:
-	k_spin_unlock(&spi_lock, key);
-
-	return ret;
-}
-
-void spi_init(void)
-{
-	k_spinlock_init(&spi_lock);
-}
diff --git a/src/drivers/generic/CMakeLists.txt b/src/drivers/generic/CMakeLists.txt
deleted file mode 100644
index 6a64feb8ef38..000000000000
--- a/src/drivers/generic/CMakeLists.txt
+++ /dev/null
@@ -1,5 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-
-if (CONFIG_DUMMY_DMA)
-	add_local_sources(sof dummy-dma.c)
-endif()
diff --git a/src/drivers/imx/CMakeLists.txt b/src/drivers/imx/CMakeLists.txt
deleted file mode 100644
index b5dc724256c7..000000000000
--- a/src/drivers/imx/CMakeLists.txt
+++ /dev/null
@@ -1,29 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-
-add_local_sources(sof
-	sai.c
-	ipc.c
-	timer.c
-)
-
-if(CONFIG_IMX_EDMA)
-	add_local_sources(sof edma.c)
-endif()
-
-if(CONFIG_IMX_ESAI)
-	add_local_sources(sof esai.c)
-endif()
-
-if(CONFIG_IMX_SDMA)
-	add_local_sources(sof sdma.c)
-endif()
-
-if(CONFIG_IMX_MICFIL)
-	add_local_sources(sof micfil.c)
-endif()
-
-if(CONFIG_IMX_INTERRUPT_IRQSTEER)
-	add_local_sources(sof interrupt-irqsteer.c)
-elseif(CONFIG_IMX_INTERRUPT_GENERIC)
-	add_local_sources(sof interrupt-generic.c)
-endif()
diff --git a/src/drivers/imx/Kconfig b/src/drivers/imx/Kconfig
deleted file mode 100644
index 85f2a50a1162..000000000000
--- a/src/drivers/imx/Kconfig
+++ /dev/null
@@ -1,53 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-
-config IMX_EDMA
-	bool "i.MX EDMA driver"
-	default n
-	depends on IMX
-	help
-	  Select this to enable support for i.MX EDMA DMA controller.
-
-config IMX_SDMA
-	bool "i.MX SDMA driver"
-	default n
-	depends on IMX
-	help
-	  Select this to enable support for i.MX SDMA DMA controller.
-
-config IMX_ESAI
-	bool "i.MX ESAI driver"
-	default n
-	depends on IMX
-	help
-	  Select this to enable support for i.MX ESAI IP.
-
-config IMX_MICFIL
-	bool "i.MX MICFIL PDM driver"
-	default n
-	depends on IMX
-	select HAVE_SDMA_FIRMWARE
-	help
-	  Select this to enable support for i.MX MICFIL PDM IP. This block implements
-	  the required digital interface to provide a 24-bits audio signal from a PDM
-	  microphone bitstream in a configurable output sampling rate
-
-config IMX_INTERRUPT_IRQSTEER
-	bool
-	default n
-	help
-	  This has to be selected for i.MX NXP platform that have irqsteer.
-	  It enables NXP platforms-specific features.
-
-config IMX_INTERRUPT_GENERIC
-	bool
-	default n
-	help
-	  This has to be selected for i.MX NXP platform that do not have irqsteer.
-	  It enables NXP platforms-specific features.
-
-config HAVE_SDMA_FIRMWARE
-	bool "Enable SDMA firmware load"
-	default n
-	help
-	  Select this to load SDMA firmware to enable additional functionality
-          for SDMA controller.
diff --git a/src/drivers/imx/edma.c b/src/drivers/imx/edma.c
deleted file mode 100644
index 13d609dc06be..000000000000
--- a/src/drivers/imx/edma.c
+++ /dev/null
@@ -1,567 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-//
-// Copyright 2019 NXP
-//
-// Author: Daniel Baluta <daniel.baluta@nxp.com>
-// Author: Paul Olaru <paul.olaru@nxp.com>
-
-#include <sof/audio/component.h>
-#include <sof/drivers/edma.h>
-#include <rtos/timer.h>
-#include <rtos/alloc.h>
-#include <sof/lib/dma.h>
-#include <sof/lib/io.h>
-#include <sof/lib/notifier.h>
-#include <sof/lib/uuid.h>
-#include <sof/math/numbers.h>
-#include <sof/platform.h>
-#include <errno.h>
-#include <stddef.h>
-#include <stdint.h>
-
-LOG_MODULE_REGISTER(edma, CONFIG_SOF_LOG_LEVEL);
-
-SOF_DEFINE_REG_UUID(edma);
-
-/* unused with Zephyr, generates no output */
-DECLARE_TR_CTX(edma_tr, SOF_UUID(edma_uuid), LOG_LEVEL_INFO);
-
-static void chan_addr_convert(struct dma_chan_data *channel, uint32_t *sbase, uint32_t *dbase)
-{
-	if (channel->direction == DMA_DIR_MEM_TO_DEV)
-		*sbase = local_to_host(*sbase);
-	else
-		*dbase = local_to_host(*dbase);
-}
-
-static int edma_encode_tcd_attr(int src_width, int dest_width)
-{
-	int result = 0;
-
-	switch (src_width) {
-	case 1:
-		result = EDMA_TCD_ATTR_SSIZE_8BIT;
-		break;
-	case 2:
-		result = EDMA_TCD_ATTR_SSIZE_16BIT;
-		break;
-	case 4:
-		result = EDMA_TCD_ATTR_SSIZE_32BIT;
-		break;
-	case 8:
-		result = EDMA_TCD_ATTR_SSIZE_64BIT;
-		break;
-	case 16:
-		result = EDMA_TCD_ATTR_SSIZE_16BYTE;
-		break;
-	case 32:
-		result = EDMA_TCD_ATTR_SSIZE_32BYTE;
-		break;
-	case 64:
-		result = EDMA_TCD_ATTR_SSIZE_64BYTE;
-		break;
-	default:
-		return -EINVAL;
-	}
-
-	switch (dest_width) {
-	case 1:
-		result |= EDMA_TCD_ATTR_DSIZE_8BIT;
-		break;
-	case 2:
-		result |= EDMA_TCD_ATTR_DSIZE_16BIT;
-		break;
-	case 4:
-		result |= EDMA_TCD_ATTR_DSIZE_32BIT;
-		break;
-	case 8:
-		result |= EDMA_TCD_ATTR_DSIZE_64BIT;
-		break;
-	case 16:
-		result |= EDMA_TCD_ATTR_DSIZE_16BYTE;
-		break;
-	case 32:
-		result |= EDMA_TCD_ATTR_DSIZE_32BYTE;
-		break;
-	case 64:
-		result |= EDMA_TCD_ATTR_DSIZE_64BYTE;
-		break;
-	default:
-		return -EINVAL;
-	}
-
-	return result;
-}
-
-/* acquire the specific DMA channel */
-static struct dma_chan_data *edma_channel_get(struct dma *dma,
-					      unsigned int req_chan)
-{
-	k_spinlock_key_t key;
-	struct dma_chan_data *channel;
-
-	tr_dbg(&edma_tr, "EDMA: channel_get(%d)", req_chan);
-
-	key = k_spin_lock(&dma->lock);
-	if (req_chan >= dma->plat_data.channels) {
-		k_spin_unlock(&dma->lock, key);
-		tr_err(&edma_tr, "EDMA: Channel %d out of range", req_chan);
-		return NULL;
-	}
-
-	channel = &dma->chan[req_chan];
-	if (channel->status != COMP_STATE_INIT) {
-		k_spin_unlock(&dma->lock, key);
-		tr_err(&edma_tr, "EDMA: Cannot reuse channel %d", req_chan);
-		return NULL;
-	}
-
-	atomic_add(&dma->num_channels_busy, 1);
-	channel->status = COMP_STATE_READY;
-	k_spin_unlock(&dma->lock, key);
-
-	return channel;
-}
-
-/* channel must not be running when this is called */
-static void edma_channel_put(struct dma_chan_data *channel)
-{
-	k_spinlock_key_t key;
-
-	/* Assuming channel is stopped, we thus don't need hardware to
-	 * do anything right now
-	 */
-	tr_info(&edma_tr, "EDMA: channel_put(%d)", channel->index);
-
-	notifier_unregister_all(NULL, channel);
-
-	key = k_spin_lock(&channel->dma->lock);
-	channel->status = COMP_STATE_INIT;
-	atomic_sub(&channel->dma->num_channels_busy, 1);
-	k_spin_unlock(&channel->dma->lock, key);
-}
-
-static int edma_start(struct dma_chan_data *channel)
-{
-	tr_info(&edma_tr, "EDMA: start(%d)", channel->index);
-
-	if (channel->status != COMP_STATE_PREPARE &&
-	    channel->status != COMP_STATE_PAUSED)
-		return -EINVAL;
-
-	channel->status = COMP_STATE_ACTIVE;
-	/* Allow the HW to automatically trigger further transfers */
-	dma_chan_reg_update_bits(channel, EDMA_CH_CSR,
-				 EDMA_CH_CSR_ERQ_EARQ, EDMA_CH_CSR_ERQ_EARQ);
-	return 0;
-}
-
-static int edma_release(struct dma_chan_data *channel)
-{
-	/* TODO actually handle pause/release properly? */
-	tr_info(&edma_tr, "EDMA: release(%d)", channel->index);
-
-	if (channel->status != COMP_STATE_PAUSED)
-		return -EINVAL;
-
-	channel->status = COMP_STATE_PREPARE;
-	return 0;
-}
-
-static int edma_pause(struct dma_chan_data *channel)
-{
-	/* TODO actually handle pause/release properly? */
-	tr_info(&edma_tr, "EDMA: pause(%d)", channel->index);
-
-	if (channel->status != COMP_STATE_ACTIVE)
-		return -EINVAL;
-
-	channel->status = COMP_STATE_PAUSED;
-
-	/* Disable HW requests */
-	dma_chan_reg_update_bits(channel, EDMA_CH_CSR,
-				 EDMA_CH_CSR_ERQ_EARQ, 0);
-	return 0;
-}
-
-static int edma_stop(struct dma_chan_data *channel)
-{
-	tr_info(&edma_tr, "EDMA: stop(%d)", channel->index);
-	/* Validate state */
-	// TODO: Should we?
-	switch (channel->status) {
-	case COMP_STATE_READY:
-	case COMP_STATE_PREPARE:
-		return 0; /* do not try to stop multiple times */
-	case COMP_STATE_PAUSED:
-	case COMP_STATE_ACTIVE:
-		break;
-	default:
-		return -EINVAL;
-	}
-	channel->status = COMP_STATE_READY;
-	/* Disable channel */
-	dma_chan_reg_write(channel, EDMA_CH_CSR, 0);
-	dma_chan_reg_write(channel, EDMA_TCD_CSR, 0);
-	/* The remaining TCD values will still be valid but I don't care
-	 * about them anyway
-	 */
-	return 0;
-}
-
-static int edma_copy(struct dma_chan_data *channel, int bytes, uint32_t flags)
-{
-	struct dma_cb_data next = {
-		.channel = channel,
-		.elem.size = bytes,
-	};
-
-	notifier_event(channel, NOTIFIER_ID_DMA_COPY,
-		       NOTIFIER_TARGET_CORE_LOCAL, &next, sizeof(next));
-
-	return 0;
-}
-
-static int edma_status(struct dma_chan_data *channel,
-		       struct dma_chan_status *status, uint8_t direction)
-{
-	status->state = channel->status;
-	status->flags = 0;
-	/* Note: these might be slightly inaccurate as they are only
-	 * updated at the end of each minor (block) transfer
-	 */
-	status->r_pos = dma_chan_reg_read(channel, EDMA_TCD_SADDR);
-	status->w_pos = dma_chan_reg_read(channel, EDMA_TCD_DADDR);
-	status->timestamp = sof_cycle_get_64();
-	return 0;
-}
-
-static int edma_validate_nonsg_config(struct dma_sg_elem_array *sgelems,
-				      uint32_t soff, uint32_t doff)
-{
-	uint32_t sbase, dbase, size;
-
-	if (!sgelems)
-		return -EINVAL;
-	if (sgelems->count != 2)
-		return -EINVAL; /* Only ping-pong configs supported */
-
-	sbase = sgelems->elems[0].src;
-	dbase = sgelems->elems[0].dest;
-	size = sgelems->elems[0].size;
-
-	if (sbase + size * SGN(soff) != sgelems->elems[1].src)
-		return -EINVAL; /**< Not contiguous */
-	if (dbase + size * SGN(doff) != sgelems->elems[1].dest)
-		return -EINVAL; /**< Not contiguous */
-	if (size != sgelems->elems[1].size)
-		return -EINVAL; /**< Mismatched sizes */
-
-	return 0; /* Ok, we good */
-}
-
-/* Some set_config helper functions */
-/**
- * \brief Compute and set the TCDs for this channel
- * \param[in] channel DMA channel
- * \param[in] soff Computed SOFF register value
- * \param[in] doff Computed DOFF register value
- * \param[in] cyclic Whether the transfer should be cyclic
- * \param[in] sg Whether we should do scatter-gather
- * \param[in] irqoff Whether the IRQ is disabled
- * \param[in] sgelems The scatter-gather elems, from the config
- * \param[in] src_width Width of transfer on source end
- * \param[in] dest_width Width of transfer on destination end
- * \return 0 on success, negative on error
- *
- * Computes the TCD to be uploaded to the hardware registers. In the
- * scatter-gather situation, it also allocates and computes the
- * additional TCDs, one for each of the input elems.
- */
-static int edma_setup_tcd(struct dma_chan_data *channel, int16_t soff,
-			  int16_t doff, bool cyclic, bool sg, bool irqoff,
-			  struct dma_sg_elem_array *sgelems, int src_width,
-			  int dest_width, uint32_t burst_elems)
-{
-	int rc;
-#if defined(CONFIG_IMX8ULP) || defined(CONFIG_IMX93_A55)
-	struct dai_data *dd = channel->dev_data;
-	int direction, handshake, dmamux_cfg;
-#endif
-	uint32_t sbase, dbase, total_size, elem_count, elem_size, size;
-
-	assert(!sg);
-	assert(cyclic);
-	/* Not scatter-gather, just create a regular TCD. Don't
-	 * allocate anything
-	 */
-
-	/* The only supported non-SG configurations are:
-	 * -> 2 buffers
-	 * -> The buffers must be of equal size
-	 * -> The buffers must be contiguous
-	 * -> The first buffer should be of the lower address
-	 */
-
-	/* TODO Support more advanced non-SG configurations */
-
-	rc = edma_validate_nonsg_config(sgelems, soff, doff);
-	if (rc < 0)
-		return rc;
-
-	sbase = sgelems->elems[0].src;
-	dbase = sgelems->elems[0].dest;
-	total_size = 2 * sgelems->elems[0].size;
-	/* TODO more flexible elem_count and elem_size
-	 * calculations
-	 */
-	elem_count = 2;
-	elem_size = total_size / elem_count;
-
-	/* burst_elems is in words translate it in bytes and divide by two
-	 * to fill the FIFO to half its size
-	 */
-	burst_elems = burst_elems * src_width / 2U;
-
-	size = MIN(elem_size, burst_elems);
-	while (size >= 4U) {
-		if ((elem_size % size) == 0UL)
-			break;
-		size -= 1U;
-	}
-	assert(size >= 4U);
-	rc = edma_encode_tcd_attr(src_width, dest_width);
-	if (rc < 0)
-		return rc;
-
-#if defined(CONFIG_IMX8ULP) || defined(CONFIG_IMX93_A55)
-	/* Do not write EDMA_CH_MUX register when it has value,
-	 * otherwise the register will be cleared.
-	 */
-	if (channel->direction == DMA_DIR_MEM_TO_DEV)
-		direction = DAI_DIR_PLAYBACK;
-	else
-		direction = DAI_DIR_CAPTURE;
-
-	handshake = dai_get_handshake(dd->dai, direction, 0);
-	dmamux_cfg = EDMA_HS_GET_DMAMUX_CFG(handshake);
-
-	if (!dma_chan_reg_read(channel, EDMA_CH_MUX))
-		dma_chan_reg_write(channel, EDMA_CH_MUX, dmamux_cfg);
-#endif
-
-	chan_addr_convert(channel, &sbase, &dbase);
-
-	/* Configure the in-hardware TCD */
-	dma_chan_reg_write(channel, EDMA_TCD_SADDR, sbase);
-	dma_chan_reg_write16(channel, EDMA_TCD_SOFF, soff);
-	dma_chan_reg_write16(channel, EDMA_TCD_ATTR, rc);
-	dma_chan_reg_write(channel, EDMA_TCD_NBYTES, size);
-	dma_chan_reg_write(channel, EDMA_TCD_SLAST, -total_size * SGN(soff));
-	dma_chan_reg_write(channel, EDMA_TCD_DADDR, dbase);
-	dma_chan_reg_write16(channel, EDMA_TCD_DOFF, doff);
-	dma_chan_reg_write16(channel, EDMA_TCD_CITER, total_size / size);
-	dma_chan_reg_write(channel, EDMA_TCD_DLAST_SGA,
-			   -total_size * SGN(doff));
-	dma_chan_reg_write16(channel, EDMA_TCD_BITER, total_size / size);
-	dma_chan_reg_write16(channel, EDMA_TCD_CSR, 0);
-
-	channel->status = COMP_STATE_PREPARE;
-	return 0;
-}
-
-/* set the DMA channel configuration, source/target address, buffer sizes */
-static int edma_set_config(struct dma_chan_data *channel,
-			   struct dma_sg_config *config)
-{
-	int16_t soff = 0;
-	int16_t doff = 0;
-
-	tr_info(&edma_tr, "EDMA: set config");
-
-	channel->is_scheduling_source = config->is_scheduling_source;
-	channel->direction = config->direction;
-
-	switch (config->direction) {
-	case DMA_DIR_MEM_TO_DEV:
-		soff = config->src_width;
-		doff = 0;
-		break;
-	case DMA_DIR_DEV_TO_MEM:
-		soff = 0;
-		doff = config->dest_width;
-		break;
-	default:
-		tr_err(&edma_tr, "unsupported config direction");
-		return -EINVAL;
-	}
-
-	if (!config->cyclic) {
-		tr_err(&edma_tr, "EDMA: Only cyclic configurations are supported!");
-		return -EINVAL;
-	}
-	if (config->scatter) {
-		tr_err(&edma_tr, "EDMA: scatter enabled, that is not supported for now!");
-		return -EINVAL;
-	}
-
-	return edma_setup_tcd(channel, soff, doff, config->cyclic,
-			      config->scatter, config->irq_disabled,
-			      &config->elem_array, config->src_width,
-			      config->dest_width, config->burst_elems);
-}
-
-static int edma_probe(struct dma *dma)
-{
-	int channel;
-
-	if (dma->chan) {
-		tr_err(&edma_tr, "EDMA: Repeated probe");
-		return -EEXIST;
-	}
-	tr_info(&edma_tr, "EDMA: probe");
-
-	dma->chan = rzalloc(SOF_MEM_FLAG_KERNEL,
-			    dma->plat_data.channels *
-			    sizeof(struct dma_chan_data));
-	if (!dma->chan) {
-		tr_err(&edma_tr, "EDMA: Probe failure, unable to allocate channel descriptors");
-		return -ENOMEM;
-	}
-	for (channel = 0; channel < dma->plat_data.channels; channel++) {
-		dma->chan[channel].dma = dma;
-		dma->chan[channel].index = channel;
-	}
-	return 0;
-}
-
-static int edma_remove(struct dma *dma)
-{
-	int channel;
-
-	if (!dma->chan) {
-		tr_err(&edma_tr, "EDMA: remove called without probe, it's a no-op");
-		return 0;
-	}
-	for (channel = 0; channel < dma->plat_data.channels; channel++) {
-		/* Disable HW requests for this channel */
-		dma_chan_reg_write(&dma->chan[channel], EDMA_CH_CSR, 0);
-		/* Remove TCD from channel */
-		dma_chan_reg_write16(&dma->chan[channel], EDMA_TCD_CSR, 0);
-	}
-	rfree(dma->chan);
-	dma->chan = NULL;
-
-	return 0;
-}
-
-static int edma_interrupt(struct dma_chan_data *channel, enum dma_irq_cmd cmd)
-{
-	if (channel->status == COMP_STATE_INIT)
-		return 0;
-
-	switch (cmd) {
-	case DMA_IRQ_STATUS_GET:
-		return dma_chan_reg_read(channel, EDMA_CH_INT);
-	case DMA_IRQ_CLEAR:
-		dma_chan_reg_write(channel, EDMA_CH_INT, 1);
-		return 0;
-	case DMA_IRQ_MASK:
-		dma_chan_reg_update_bits16(channel, EDMA_TCD_CSR,
-					   EDMA_TCD_CSR_INTHALF_INTMAJOR,
-					   0);
-		return 0;
-	case DMA_IRQ_UNMASK:
-		dma_chan_reg_update_bits16(channel, EDMA_TCD_CSR,
-					   EDMA_TCD_CSR_INTHALF_INTMAJOR,
-					   EDMA_TCD_CSR_INTHALF_INTMAJOR);
-		return 0;
-	default:
-		return -EINVAL;
-	}
-}
-
-static int edma_get_attribute(struct dma *dma, uint32_t type, uint32_t *value)
-{
-	switch (type) {
-	case DMA_ATTR_BUFFER_ALIGNMENT:
-	case DMA_ATTR_COPY_ALIGNMENT:
-		/* With 4-byte transfers we need to align the buffers to
-		 * 4 bytes. Even if it can be programmed in 2-byte or
-		 * 1-byte for the transfers, this function cannot
-		 * determine that. So return a conservative value.
-		 *
-		 * The EDMA could theoretically transfer larger bursts
-		 * per elementary copy (up to 64 bytes). However since
-		 * we won't use that in SOF I won't unnecessarily
-		 * restrict alignment (the alignment requirement is the
-		 * size of the elementary copy).
-		 */
-		*value = 4;
-		break;
-	case DMA_ATTR_BUFFER_ADDRESS_ALIGNMENT:
-		*value = PLATFORM_DCACHE_ALIGN;
-		break;
-	case DMA_ATTR_BUFFER_PERIOD_COUNT:
-		*value = EDMA_BUFFER_PERIOD_COUNT;
-		break;
-	default:
-		return -ENOENT; /* Attribute not found */
-	}
-	return 0;
-}
-
-static int edma_get_data_size(struct dma_chan_data *channel,
-			      uint32_t *avail, uint32_t *free)
-{
-	/* We assume the channel is configured, otherwise this will
-	 * return undefined data.
-	 *
-	 * get_data_size() and copy() are run exactly once per
-	 * interrupt, and currently we have the elem size stored
-	 * directly in the hardware register EDMA_TCD_SLAST
-	 * as negative offset divided by 2 for playback and, similarly,
-	 * in EDMA_TCD_DLAST_SGA for capture.
-	 *
-	 * TODO If we support multiple DMA transfers per SOF elem, we
-	 * need to adjust for that and copy the whole required data per
-	 * interrupt.
-	 */
-	int32_t playback_data_size, capture_data_size;
-
-	playback_data_size = (int32_t)dma_chan_reg_read(channel,
-		EDMA_TCD_SLAST);
-	capture_data_size = (int32_t)dma_chan_reg_read(channel,
-		EDMA_TCD_DLAST_SGA);
-
-	switch (channel->direction) {
-	case DMA_DIR_MEM_TO_DEV:
-		*free = ABS(playback_data_size) / 2;
-		break;
-	case DMA_DIR_DEV_TO_MEM:
-		*avail = ABS(capture_data_size) / 2;
-		break;
-	default:
-		tr_err(&edma_tr, "unsupported direction %d",
-		       channel->direction);
-		return -EINVAL;
-	}
-	return 0;
-}
-
-const struct dma_ops edma_ops = {
-	.channel_get	= edma_channel_get,
-	.channel_put	= edma_channel_put,
-	.start		= edma_start,
-	.stop		= edma_stop,
-	.pause		= edma_pause,
-	.release	= edma_release,
-	.copy		= edma_copy,
-	.status		= edma_status,
-	.set_config	= edma_set_config,
-	.probe		= edma_probe,
-	.remove		= edma_remove,
-	.interrupt	= edma_interrupt,
-	.get_attribute	= edma_get_attribute,
-	.get_data_size	= edma_get_data_size,
-};
diff --git a/src/drivers/imx/esai.c b/src/drivers/imx/esai.c
deleted file mode 100644
index a7853ea32932..000000000000
--- a/src/drivers/imx/esai.c
+++ /dev/null
@@ -1,447 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-//
-// Copyright 2019 NXP
-//
-// Author: Daniel Baluta <daniel.baluta@nxp.com>
-// Author: Paul Olaru <paul.olaru@nxp.com>
-
-#include <sof/audio/component.h>
-#include <sof/drivers/edma.h>
-#include <sof/drivers/esai.h>
-#include <rtos/interrupt.h>
-#include <rtos/alloc.h>
-#include <sof/lib/dai.h>
-#include <sof/lib/dma.h>
-#include <sof/lib/uuid.h>
-#include <ipc/dai.h>
-#include <ipc/topology.h>
-#include <errno.h>
-#include <stdint.h>
-
-LOG_MODULE_REGISTER(esai, CONFIG_SOF_LOG_LEVEL);
-
-SOF_DEFINE_REG_UUID(esai);
-
-/* unused with Zephyr, generates no output */
-DECLARE_TR_CTX(esai_tr, SOF_UUID(esai_uuid), LOG_LEVEL_INFO);
-
-struct esai_pdata {
-	struct {
-		uint32_t ecr;
-		uint32_t tfcr;
-		uint32_t rfcr;
-		uint32_t saicr;
-		uint32_t tcr;
-		uint32_t tccr;
-		uint32_t rcr;
-		uint32_t rccr;
-		uint32_t tsma;
-		uint32_t tsmb;
-		uint32_t rsma;
-		uint32_t rsmb;
-		uint32_t prrc;
-		uint32_t pcrc;
-	} regs;
-	struct sof_ipc_dai_esai_params params;
-};
-
-static inline int esai_set_config(struct dai *dai, struct ipc_config_dai *common_config,
-				  const void *spec_config)
-{
-	const struct sof_ipc_dai_config *config = spec_config;
-	uint32_t xcr = 0, xccr = 0, mask;
-	struct esai_pdata *esai = dai_get_drvdata(dai);
-
-	dai_dbg(dai, "ESAI: set_config format 0x%04x",
-		config->format);
-
-	esai->params = config->esai;
-
-	switch (config->format & SOF_DAI_FMT_FORMAT_MASK) {
-	case SOF_DAI_FMT_I2S:
-		/* Data on rising edge of bclk, frame low, 1clk before
-		 * data
-		 */
-		xcr |= ESAI_xCR_xFSR;
-		xccr |= ESAI_xCCR_xFSP | ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
-		break;
-	case SOF_DAI_FMT_RIGHT_J:
-		/* Data on rising edge of bclk, frame high, right
-		 * aligned
-		 */
-		xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
-		xcr  |= ESAI_xCR_xWA;
-		break;
-	case SOF_DAI_FMT_LEFT_J:
-		/* Data on rising edge of bclk, frame high */
-		xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
-		break;
-	case SOF_DAI_FMT_DSP_A:
-		/* Data on rising edge of bclk, frame high, 1clk before
-		 * data
-		 */
-		xcr |= ESAI_xCR_xFSL | ESAI_xCR_xFSR;
-		xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
-		break;
-	case SOF_DAI_FMT_DSP_B:
-		/* Data on rising edge of bclk, frame high */
-		xcr |= ESAI_xCR_xFSL;
-		xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
-		break;
-	case SOF_DAI_FMT_PDM:
-		dai_err(dai, "ESAI: Unsupported format (PDM)");
-		return -EINVAL;
-	default:
-		dai_err(dai, "ESAI: invalid format");
-		return -EINVAL;
-	}
-
-	switch (config->format & SOF_DAI_FMT_INV_MASK) {
-	case SOF_DAI_FMT_NB_NF:
-		 /* Nothing to do for both normal cases */
-		break;
-	case SOF_DAI_FMT_NB_IF:
-		/* Invert frame clock */
-		xccr ^= ESAI_xCCR_xFSP;
-		break;
-	case SOF_DAI_FMT_IB_NF:
-		/* Invert bit clock */
-		xccr ^= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
-		break;
-	case SOF_DAI_FMT_IB_IF:
-		/* Invert both clocks */
-		xccr ^= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP | ESAI_xCCR_xFSP;
-		break;
-	default:
-		dai_err(dai, "ESAI: Invalid bit inversion format");
-		return -EINVAL;
-	}
-
-	switch (config->format & SOF_DAI_FMT_CLOCK_PROVIDER_MASK) {
-	case SOF_DAI_FMT_CBP_CFP:
-		/* Nothing to do in the registers */
-		break;
-	case SOF_DAI_FMT_CBP_CFC:
-		xccr |= ESAI_xCCR_xFSD;
-		break;
-	case SOF_DAI_FMT_CBC_CFP:
-		xccr |= ESAI_xCCR_xCKD;
-		break;
-	case SOF_DAI_FMT_CBC_CFC:
-		xccr |= ESAI_xCCR_xFSD | ESAI_xCCR_xCKD;
-		break;
-	default:
-		dai_err(dai, "ESAI: Invalid clock provider-consumer configuration");
-		return -EINVAL;
-	}
-
-	/* Set networked mode; we only support 2 channels now, not 1 */
-	xcr |= ESAI_xCR_xMOD_NETWORK;
-	xccr |= ESAI_xCCR_xDC(2);
-
-	/* Codec desires 32-bit samples, while the pipeline works with 24-bit
-	 * samples. Pad the least significant bits with zeros.
-	 * TODO replace 24 with the sample width requested from the topology.
-	 */
-	xcr |= ESAI_xCR_xSWS(32, 24) | ESAI_xCR_PADC;
-
-	/* Remove "RESET" flag so we can configure the ESAI */
-	dai_update_bits(dai, REG_ESAI_ECR, ESAI_ECR_ERST, 0);
-
-	/* EXTAL transmitter in, we should use external EXTAL pin as MCLK */
-	dai_update_bits(dai, REG_ESAI_ECR, ESAI_ECR_ETI, ESAI_ECR_ETI);
-
-	mask = ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP | ESAI_xCCR_xFSP |
-		ESAI_xCCR_xFSD | ESAI_xCCR_xCKD | ESAI_xCCR_xHCKD |
-		ESAI_xCCR_xDC_MASK;
-
-	xccr |= ESAI_xCCR_xHCKD; /* Set the HCKT pin as an output */
-
-	dai_update_bits(dai, REG_ESAI_TCCR, mask, xccr);
-	/* There is a hardware limitation which prevents tx and rx to be
-	 * simultaneously provider or simultaneously consumer. As a workaround,
-	 * we will leave tx as provider and set rx as consumer.
-	 */
-	xccr &= ~(ESAI_xCCR_xCKD | ESAI_xCCR_xFSD);
-	dai_update_bits(dai, REG_ESAI_RCCR, mask, xccr);
-
-	mask = ESAI_xCR_xFSL | ESAI_xCR_xFSR | ESAI_xCR_xWA |
-		ESAI_xCR_xMOD_MASK | ESAI_xCR_xSWS_MASK | ESAI_xCR_PADC |
-		ESAI_xCR_xPR;
-	/* Personal reset, suspend the actual TX/RX for now */
-	xcr |= ESAI_xCR_xPR;
-
-	dai_update_bits(dai, REG_ESAI_TCR, mask, xcr);
-	/* rx doesn't have any PADC bit, remove it from the mask */
-	mask &= ~ESAI_xCR_PADC;
-	dai_update_bits(dai, REG_ESAI_RCR, mask, xcr);
-
-	/* Disable transmission by disabling all slots */
-	dai_write(dai, REG_ESAI_TSMA, 0);
-	dai_write(dai, REG_ESAI_TSMB, 0);
-	dai_write(dai, REG_ESAI_RSMA, 0);
-	dai_write(dai, REG_ESAI_RSMB, 0);
-
-	/* Program FIFOs */
-	dai_update_bits(dai, REG_ESAI_RFCR, ESAI_xFCR_xFR, 0);
-
-	/* Reset transmit FIFO */
-	dai_update_bits(dai, REG_ESAI_TFCR,
-			ESAI_xFCR_xFR_MASK,
-			ESAI_xFCR_xFR);
-	/* Reset receive FIFO */
-	dai_update_bits(dai, REG_ESAI_RFCR,
-			ESAI_xFCR_xFR_MASK,
-			ESAI_xFCR_xFR);
-
-	/* Set transmit fifo configuration register
-	 * xWA(24): 24-bit samples as input/output. Must agree with xSWS above.
-	 *	    TODO get sample width from topology.
-	 * xFWM(96): Trigger next DMA transfer when at least 96 (of the 128)
-	 *	     slots are empty (or full for capture).
-	 * TE(1): Enable 1 transmitter.
-	 * RE(1): Enable 1 receiver.
-	 * TIEN: Transmitter initialization enable. This will pull the initial
-	 *       samples from the FIFO in the transmit registers. The
-	 *       alternative would have been to manually initialize the
-	 *       transmit registers manually, which would have been more
-	 *       complex to implement.
-	 */
-	dai_update_bits(dai, REG_ESAI_TFCR,
-			ESAI_xFCR_xFR_MASK | ESAI_xFCR_xWA_MASK |
-			ESAI_xFCR_xFWM_MASK | ESAI_xFCR_TE_MASK |
-			ESAI_xFCR_TIEN,
-			ESAI_xFCR_xWA(24) | ESAI_xFCR_xFWM(96) |
-			ESAI_xFCR_TE(1) | ESAI_xFCR_TIEN);
-
-	dai_update_bits(dai, REG_ESAI_RFCR,
-			ESAI_xFCR_xFR_MASK | ESAI_xFCR_xWA_MASK |
-			ESAI_xFCR_xFWM_MASK | ESAI_xFCR_RE_MASK,
-			ESAI_xFCR_xWA(24) | ESAI_xFCR_xFWM(96) |
-			ESAI_xFCR_RE(1));
-
-	/* Set the clock divider to divide EXTAL by 16 (DIV8 from PSR,
-	 * plus a divide by 2 which is mandatory overall)
-	 * This configuration supports hardcoded MCLK at 49152000 Hz and
-	 * obtains frame clock of 96000 Hz (2 48000Hz channels) and bit clock
-	 * of 3072000 Hz (32-bit samples).
-	 * xFP(1): No division from this divider (can do 1-16)
-	 * xPSR_DIV8: Divide by 8
-	 * There is also an additional divide by 2 which is forced by the
-	 * hardware design of the ESAI.
-	 *
-	 * TODO use ESAI params instead of hardcode to compute the clock divider
-	 * settings.
-	 */
-	dai_update_bits(dai, REG_ESAI_TCCR, ESAI_xCCR_xFP_MASK,
-			ESAI_xCCR_xFP(1));
-	dai_update_bits(dai, REG_ESAI_RCCR, ESAI_xCCR_xFP_MASK,
-			ESAI_xCCR_xFP(1));
-	dai_update_bits(dai, REG_ESAI_TCCR, ESAI_xCCR_xPSR_MASK,
-			ESAI_xCCR_xPSR_DIV8);
-	dai_update_bits(dai, REG_ESAI_RCCR, ESAI_xCCR_xPSR_MASK,
-			ESAI_xCCR_xPSR_DIV8);
-
-	/* Remove ESAI personal reset */
-	dai_update_bits(dai, REG_ESAI_xCR(0), ESAI_xCR_xPR, 0);
-	dai_update_bits(dai, REG_ESAI_xCR(1), ESAI_xCR_xPR, 0);
-
-	/* Configure ESAI pins, enable them all */
-	dai_update_bits(dai, REG_ESAI_PRRC, ESAI_PRRC_PDC_MASK,
-			ESAI_PRRC_PDC(ESAI_GPIO));
-	dai_update_bits(dai, REG_ESAI_PCRC, ESAI_PCRC_PC_MASK,
-			ESAI_PCRC_PC(ESAI_GPIO));
-	return 0;
-}
-
-static void esai_start(struct dai *dai, int direction)
-{
-	/* FIFO enable */
-	dai_update_bits(dai, REG_ESAI_xFCR(direction), ESAI_xFCR_xFEN_MASK,
-			ESAI_xFCR_xFEN);
-
-	/* To prevent channel swap issues, write a sample per channel. The ESAI
-	 * can begin transmitting these samples while it is requesting for a
-	 * DMA transfer, before said DMA transfer actually puts more samples
-	 * into the ESAI FIFO. Only needed on playback/transmit.
-	 */
-	if (!direction) {
-		/* TODO adjust this when we have more than 2 channels;
-		 * we need to write a word per active channel.
-		 */
-		dai_write(dai, REG_ESAI_ETDR, 0);
-		dai_write(dai, REG_ESAI_ETDR, 0);
-	}
-
-	/* Enable one transmitter or receiver */
-	dai_update_bits(dai, REG_ESAI_xCR(direction),
-			ESAI_xCR_xE_MASK(direction), ESAI_xCR_xE(direction, 1));
-
-	/* Configure time slot registers, enable two time slots for two
-	 * channels.
-	 *
-	 * This actually begins playback/capture.
-	 *
-	 * The order of setting xSMB first and xSMA second is required to
-	 * correctly start playback/capture; setting them in reverse order may
-	 * cause significant channel swap issues when using more than 16
-	 * channels.
-	 */
-	dai_update_bits(dai, REG_ESAI_xSMB(direction), ESAI_xSMB_xS_MASK,
-			ESAI_xSMB_xS_CHANS(2));
-
-	dai_update_bits(dai, REG_ESAI_xSMA(direction), ESAI_xSMA_xS_MASK,
-			ESAI_xSMA_xS_CHANS(2));
-}
-
-static void esai_stop(struct dai *dai, int direction)
-{
-	/* Disable transmitters/receivers */
-	dai_update_bits(dai, REG_ESAI_xCR(direction),
-			direction ? ESAI_xCR_TE_MASK : ESAI_xCR_RE_MASK, 0);
-
-	/* Turn off pins */
-	dai_update_bits(dai, REG_ESAI_xSMA(direction), ESAI_xSMA_xS_MASK, 0);
-	dai_update_bits(dai, REG_ESAI_xSMB(direction), ESAI_xSMB_xS_MASK, 0);
-
-	/* disable and reset FIFO */
-	dai_update_bits(dai, REG_ESAI_xFCR(direction),
-			ESAI_xFCR_xFR | ESAI_xFCR_xFEN, ESAI_xFCR_xFR);
-	dai_update_bits(dai, REG_ESAI_xFCR(direction), ESAI_xFCR_xFR, 0);
-}
-
-static int esai_trigger(struct dai *dai, int cmd, int direction)
-{
-	dai_dbg(dai, "ESAI: trigger");
-
-	switch (cmd) {
-	case COMP_TRIGGER_START:
-	case COMP_TRIGGER_RELEASE:
-		esai_start(dai, direction);
-		break;
-	case COMP_TRIGGER_STOP:
-	case COMP_TRIGGER_PAUSE:
-		esai_stop(dai, direction);
-		break;
-	default:
-		dai_err(dai, "ESAI: invalid trigger cmd %d", cmd);
-		return -EINVAL;
-	}
-	return 0;
-}
-
-static int esai_probe(struct dai *dai)
-{
-	struct esai_pdata *pdata;
-
-	dai_dbg(dai, "ESAI: probe");
-	if (dai_get_drvdata(dai)) {
-		dai_err(dai, "ESAI: Repeated probe, skipping");
-		return -EEXIST;
-	}
-	pdata = rzalloc(SOF_MEM_FLAG_KERNEL | SOF_MEM_FLAG_COHERENT, sizeof(*pdata));
-	if (!pdata) {
-		dai_err(dai, "ESAI probe failure, out of memory");
-		return -ENOMEM;
-	}
-	dai_set_drvdata(dai, pdata);
-
-	/* ESAI core reset */
-	dai_write(dai, REG_ESAI_ECR, ESAI_ECR_ERST | ESAI_ECR_ESAIEN);
-	dai_write(dai, REG_ESAI_ECR, ESAI_ECR_ESAIEN);
-	/* ESAI personal reset (should be by default but just to be sure) */
-	dai_write(dai, REG_ESAI_PRRC, 0);
-	dai_write(dai, REG_ESAI_PCRC, 0);
-	/* ESAI FIFO reset */
-	dai_write(dai, REG_ESAI_TFCR, ESAI_xFCR_xFR);
-	dai_write(dai, REG_ESAI_RFCR, ESAI_xFCR_xFR);
-	/* Clear TSMA, TSMB (disable all transmitters and receivers) */
-	dai_write(dai, REG_ESAI_TSMA, 0);
-	dai_write(dai, REG_ESAI_TSMB, 0);
-	dai_write(dai, REG_ESAI_RSMA, 0);
-	dai_write(dai, REG_ESAI_RSMB, 0);
-
-	return 0;
-}
-
-static int esai_remove(struct dai *dai)
-{
-	struct esai_pdata *pdata = dai_get_drvdata(dai);
-
-	dai_info(dai, "entry");
-
-	rfree(pdata);
-	dai_set_drvdata(dai, NULL);
-
-	return 0;
-}
-
-static int esai_get_handshake(struct dai *dai, int direction, int stream_id)
-{
-	int handshake = dai->plat_data.fifo[direction].handshake;
-	int channel = EDMA_HS_GET_CHAN(handshake);
-	int irq = irqstr_get_sof_int(EDMA_HS_GET_IRQ(handshake));
-
-	return EDMA_HANDSHAKE(irq, channel, 0);
-}
-
-static int esai_get_fifo(struct dai *dai, int direction, int stream_id)
-{
-	switch (direction) {
-	case DAI_DIR_PLAYBACK:
-	case DAI_DIR_CAPTURE:
-		return dai_fifo(dai, direction); /* stream_id is unused */
-	default:
-		dai_err(dai, "Invalid direction");
-		return -EINVAL;
-	}
-}
-
-static int esai_get_fifo_depth(struct dai *dai, int direction)
-{
-	switch (direction) {
-	case DAI_DIR_PLAYBACK:
-	case DAI_DIR_CAPTURE:
-		return dai->plat_data.fifo[direction].depth;
-	default:
-		dai_err(dai, "Invalid direction");
-		return -EINVAL;
-	}
-}
-
-static int esai_get_hw_params(struct dai *dai,
-			      struct sof_ipc_stream_params *params,
-			      int dir)
-{
-	struct esai_pdata *esai = dai_get_drvdata(dai);
-
-	/* ESAI only currently supports these parameters */
-	params->rate = esai->params.fsync_rate;
-	params->channels = 2;
-	params->buffer_fmt = 0;
-	params->frame_fmt = SOF_IPC_FRAME_S24_4LE;
-
-	dai_info(dai, "params->rate = %d, fsync_rate = %d",
-		 params->rate, esai->params.fsync_rate);
-
-	return 0;
-}
-
-const struct dai_driver esai_driver = {
-	.type = SOF_DAI_IMX_ESAI,
-	.uid = SOF_UUID(esai_uuid),
-#if !CONFIG_ZEPHYR_LOG
-	.tctx = &esai_tr,
-#endif
-	.dma_dev = DMA_DEV_ESAI,
-	.ops = {
-		.trigger		= esai_trigger,
-		.set_config		= esai_set_config,
-		.probe			= esai_probe,
-		.remove			= esai_remove,
-		.get_handshake		= esai_get_handshake,
-		.get_fifo		= esai_get_fifo,
-		.get_fifo_depth		= esai_get_fifo_depth,
-		.get_hw_params		= esai_get_hw_params,
-	},
-};
diff --git a/src/drivers/imx/interrupt-generic.c b/src/drivers/imx/interrupt-generic.c
deleted file mode 100644
index 506a079eed46..000000000000
--- a/src/drivers/imx/interrupt-generic.c
+++ /dev/null
@@ -1,57 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-//
-// Copyright 2021 NXP
-//
-// Author: Peng Zhang <peng.zhang_8@nxp.com>
-
-#include <sof/common.h>
-#include <rtos/interrupt.h>
-#include <sof/lib/cpu.h>
-#include <sof/lib/io.h>
-#include <sof/lib/memory.h>
-#include <sof/lib/uuid.h>
-#include <sof/list.h>
-#include <rtos/spinlock.h>
-#include <errno.h>
-#include <inttypes.h>
-#include <stdbool.h>
-#include <stddef.h>
-#include <stdint.h>
-
-LOG_MODULE_REGISTER(generic_irq_imx, CONFIG_SOF_LOG_LEVEL);
-
-SOF_DEFINE_REG_UUID(interrupt);
-
-/* unused with Zephyr, generates no output */
-DECLARE_TR_CTX(noirq_i_tr, SOF_UUID(interrupt_uuid), LOG_LEVEL_INFO);
-
-/* this is needed because i.MX8 implementation assumes all boards have an irqsteer.
- * Needs to be fixed.
- */
-int irqstr_get_sof_int(int irqstr_int)
-{
-	return irqstr_int;
-}
-
-void platform_interrupt_init(void) {}
-
-#ifndef __ZEPHYR__
-void platform_interrupt_set(uint32_t irq)
-{
-	arch_interrupt_set(irq);
-}
-
-void platform_interrupt_clear(uint32_t irq, uint32_t mask)
-{
-	arch_interrupt_clear(irq);
-}
-#endif /* __ZEPHYR__ */
-
-uint32_t platform_interrupt_get_enabled(void)
-{
-	return 0;
-}
-
-void interrupt_mask(uint32_t irq, unsigned int cpu) {}
-
-void interrupt_unmask(uint32_t irq, unsigned int cpu) {}
diff --git a/src/drivers/imx/interrupt-irqsteer.c b/src/drivers/imx/interrupt-irqsteer.c
deleted file mode 100644
index 76313f1d25dc..000000000000
--- a/src/drivers/imx/interrupt-irqsteer.c
+++ /dev/null
@@ -1,488 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-//
-// Copyright 2019 NXP
-//
-// Author: Daniel Baluta <daniel.baluta@nxp.com>
-// Author: Paul Olaru <paul.olaru@nxp.com>
-
-#include <sof/common.h>
-#include <rtos/interrupt.h>
-#include <sof/lib/cpu.h>
-#include <sof/lib/io.h>
-#include <sof/lib/memory.h>
-#include <sof/lib/uuid.h>
-#include <sof/list.h>
-#include <rtos/spinlock.h>
-#include <errno.h>
-#include <inttypes.h>
-#include <stdbool.h>
-#include <stddef.h>
-#include <stdint.h>
-
-LOG_MODULE_REGISTER(irq_imx, CONFIG_SOF_LOG_LEVEL);
-
-SOF_DEFINE_REG_UUID(interrupt);
-
-/* unused with Zephyr, generates no output */
-DECLARE_TR_CTX(irq_i_tr, SOF_UUID(interrupt_uuid), LOG_LEVEL_INFO);
-
-/*
- * The IRQ_STEER module takes 512 shared interrupts and delivers them
- * via 8 interrupt lines to any other component. It supports 5 channels,
- * one of them being for the DSP itself (channel 0).
- *
- *                        +-----------+
- * IRQ 0-63 ------/64---> |           | ---/8----> Channel 0 (DSP)
- * IRQ 64-127 ----/64---> |           |
- * IRQ 128-191 ---/64---> |           | ---/8----> Channel 1 (M4)
- * IRQ 192-255 ---/64---> | IRQ_STEER |
- * IRQ 256-319 ---/64---> |           | ---/8----> Channel 2 (SCU2)
- * IRQ 320-383 ---/64---> |           | ---/8----> Channel 3 (SCU1)
- * IRQ 384-447 ---/64---> |           |
- * IRQ 448-511 ---/64---> |           | ---/1----> Channel 4 (CTI)
- *                        +-----------+
- *
- * IRQ steer channel block diagram (all 5 channels are identical)
- *
- * +---------------------------------------------------------+
- * |                  +---+          +----+           +---+  |
- * ---> IRQ 0-63 ---> |   |          |    |           |   |  |
- * |  [MASK 0-63] --> | & | --/64--> | OR | ---/1---> | & | ----> OUT[0]
- * |                  |   | [STATUS] |    | [MD0] --> |   |  |
- * |                  +---+          +----+           +---+  |
- * |                                                         |
- * | ... (same for the other IRQ lines and outputs to OUT[7] |
- * |                                                         |
- * +---------------------------------------------------------+
- *
- * In the schematic above:
- *    IRQ 0-511: Input IRQ lines (shared IRQs). IRQs 0-31 are reserved.
- *    MASK 0-511: Configurable mask for interrupts.
- *    MD0-MD7: Master disable register, block an entire output interrupt
- *    line.
- *    STATUS: Read only register which shows what interrupts are active.
- *    OUT: The 8 interrupt lines that lead to the DSP, leading to arch
- *    IRQs IRQ_NUM_IRQSTR_DSP0 through 7.
- *
- * Usage of the hardware: We turn on the hardware itself, then we
- * configure the mask (all mask bits default to 0), enable our arch
- * interrupts and wait for an interrupt on an output line.
- *
- * Upon receiving an arch interrupt, the driver must check the STATUS
- * registers corresponding to the arch interrupt in order to figure out
- * what the actual, input shared interrupt was, and then call any
- * registered callback to handle the condition leading to the interrupt.
- *
- * The hardware also supports forcing an interrupt from the software; I
- * have omitted this from the schematic since it is not relevant to the
- * usage in this driver.
- */
-
-/* The MASK, SET (unused) and STATUS registers are 512-bit registers
- * split into 16 32-bit registers that we can directly access.
- *
- * To get the proper register for the shared interrupt irq, we do
- * IRQSTR_CH_MASK(IRQSTR_INT_REG(irq)) (MASK can be replaced by SET or
- * STATUS).
- *
- * The interrupt mapping to registers is defined in
- * platform/drivers/interrupt.h for each platform.
- *
- * The IRQSTR_CH_* macros perform the second part of this calculation
- * (offset) automatically.
- */
-
-#define IRQSTR_INT_REG(irq)		((irq) / 32)
-#define IRQSTR_INT_BIT(irq)		((irq) % 32)
-#define IRQSTR_INT_MASK(irq)		(1 << IRQSTR_INT_BIT(irq))
-
-#if defined(__ZEPHYR__)
-#define interrupt_get_irq mux_interrupt_get_irq
-#endif
-
-/* HW register access helper methods */
-
-static inline void irqstr_write(uint32_t reg, uint32_t value)
-{
-	io_reg_write(IRQSTR_BASE_ADDR + reg, value);
-}
-
-static inline uint32_t irqstr_read(uint32_t reg)
-{
-	return io_reg_read(IRQSTR_BASE_ADDR + reg);
-}
-
-static inline void irqstr_update_bits(uint32_t reg, uint32_t mask,
-				      uint32_t value)
-{
-	io_reg_update_bits(IRQSTR_BASE_ADDR + reg, mask, value);
-}
-
-/* IRQ_STEER helper methods
- * These methods are usable in any IRQ_STEER driver, not specific to SOF
- */
-
-static void irqstr_enable_hw(void)
-{
-	irqstr_write(IRQSTR_CHANCTL, 1);
-}
-
-static void irqstr_disable_hw(void)
-{
-	irqstr_write(IRQSTR_CHANCTL, 0);
-}
-
-/* irqstr_get_status_word() - Get an interrupt status word
- * @index The index of the status word
- *
- * Get the status of interrupts 32*index .. 32*(index+1)-1 in a word.
- * This status is in one hardware register.
- * Return: Status register word for the corresponding interrupts
- */
-static uint32_t irqstr_get_status_word(uint32_t index)
-{
-	if (index < IRQSTR_RESERVED_IRQS_NUM / 32)
-		return 0;
-	/* On out of range for our platform, be silent */
-	if (index >= IRQSTR_IRQS_REGISTERS_NUM)
-		return 0;
-	return irqstr_read(IRQSTR_CH_STATUS(index));
-}
-
-static uint32_t irqstr_fixup_irq(uint32_t irq)
-{
-#ifdef CONFIG_IMX8M
-	return irq - 32;
-#else
-	return irq;
-#endif
-}
-
-/* Mask, that is, disable interrupts */
-static void irqstr_mask_int(uint32_t irq)
-{
-	uint32_t mask;
-
-	if (irq < IRQSTR_RESERVED_IRQS_NUM || irq >= IRQSTR_IRQS_NUM)
-		return; // Unusable interrupts
-
-	irq = irqstr_fixup_irq(irq);
-
-	mask = IRQSTR_INT_MASK(irq);
-	irqstr_update_bits(IRQSTR_CH_MASK(IRQSTR_INT_REG(irq)), mask, 0);
-}
-
-/* Unmask, that is, enable interrupts */
-static void irqstr_unmask_int(uint32_t irq)
-{
-	uint32_t mask;
-
-	if (irq < IRQSTR_RESERVED_IRQS_NUM || irq >= IRQSTR_IRQS_NUM)
-		return; // Unusable interrupts
-
-	irq = irqstr_fixup_irq(irq);
-
-	mask = IRQSTR_INT_MASK(irq);
-	irqstr_update_bits(IRQSTR_CH_MASK(IRQSTR_INT_REG(irq)), mask, mask);
-}
-
-#ifdef CONFIG_IMX8M
-
-/* Quirk of the driver in SOF (Quirk is specific to 8MP):
- * -> IRQSTR has 5 input channels each with 32 interrupts
- * -> IRQSTR has 3 output channels each with 64 interrupts
- * -> IRQ in[31:0]    => IRQ out[63:32]   (output channel #0)
- * -> IRQ in[63:32]   => IRQ out[95:64]   (output channel #1, low half)
- * -> IRQ in[95:64]   => IRQ out[127:96]  (output channel #1, high half)
- * -> IRQ in[127:96]  => IRQ out[159:128] (output channel #2, low half)
- * -> IRQ in[159:128] => IRQ out[191:160] (output channel #2, high half)
- * Thus in SOF irqsteer we shift everything with 32 and we get:
- * -> Interrupts 0-31 are not usable
- * -> Interrupts 32-63 map to hw irqs 0-31 (irqsteer0)
- * -> Interrupts 64-127 map to hw irqs 32-95 (irqsteer1)
- * -> Interrupts 128-191 map to hw irqs 96-159 (irqsteer2)
- */
-
-const char * const irq_name_irqsteer[] = {
-	"irqsteer0",
-	"irqsteer1",
-	"irqsteer2"
-};
-#else
-/* SOF specific part of the driver */
-
-/* Quirk of the driver in SOF (Quirk is specific to 8QXP/8QM):
- * -> Interrupts 0-31 are hardware
- * -> Interrupts 32-63 are unusable, as they are reserved in irqstr. We
- *  will never get an event on these shared interrupt lines.
- * -> Interrupts 64-543 are usable, mapping to 32-512 in IRQSTR itself
- * The above functions expect the 32-512 interrupts valid, not the
- * shifted SOF ones.
- */
-
-const char * const irq_name_irqsteer[] = {
-	"irqsteer0",
-	"irqsteer1",
-	"irqsteer2",
-	"irqsteer3",
-	"irqsteer4",
-	"irqsteer5",
-	"irqsteer6",
-	"irqsteer7"
-};
-#endif
-
-#define IRQ_MAX_TRIES	1000
-
-/* Extract the 64 status bits corresponding to output interrupt line
- * index (64 input interrupts)
- */
-#ifdef CONFIG_IMX8M
-static uint64_t get_irqsteer_interrupts(uint32_t index)
-{
-	uint64_t result = 0;
-
-	result = irqstr_get_status_word(2 * index);
-	result <<= 32;
-
-	/* line 0 is special only maps interrupts [63..32],
-	 * interval [31..0] is not used
-	 */
-	if (index == 0)
-		return result;
-
-	result |= irqstr_get_status_word(2 * index - 1);
-	return result;
-}
-#else
-static uint64_t get_irqsteer_interrupts(uint32_t index)
-{
-	uint64_t result = irqstr_get_status_word(2 * index + 1);
-
-	result <<= 32;
-	result |= irqstr_get_status_word(2 * index);
-	return result;
-}
-#endif
-
-/**
- * get_first_irq() Get the first IRQ bit set in this group.
- *
- * Get the first pending IRQ in the group. For example, get_first_irq(0x40)
- * will return 6 (as 1 << 6 is 0x40), while get_first_irq(0) will return -1.
- *
- * @param ints The 64 input interrupts
- * @return -1 if all interrupts are clear, or a shift value if at least
- * one interrupt is set.
- */
-static int get_first_irq(uint64_t ints)
-{
-	return ffsll(ints) - 1;
-}
-
-static inline void handle_irq_batch(struct irq_cascade_desc *cascade,
-				    uint32_t line_index, uint64_t status)
-{
-	int core = cpu_get_id();
-	struct list_item *clist;
-	struct irq_desc *child = NULL;
-	int bit;
-	bool handled;
-	k_spinlock_key_t key;
-
-	while (status) {
-		bit = get_first_irq(status);
-		handled = false;
-		status &= ~(1ull << bit); /* Release interrupt */
-
-		key = k_spin_lock(&cascade->lock);
-
-		/* Get child if any and run handler */
-		list_for_item(clist, &cascade->child[bit].list) {
-			child = container_of(clist, struct irq_desc, irq_list);
-
-			if (child->handler && (child->cpu_mask & 1 << core)) {
-				/* run handler in non atomic context */
-				k_spin_unlock(&cascade->lock, key);
-				child->handler(child->handler_arg);
-				k_spin_lock(&cascade->lock);
-
-				handled = true;
-			}
-		}
-
-		k_spin_unlock(&cascade->lock, key);
-
-		if (!handled) {
-			tr_err(&irq_i_tr, "irq_handler(): nobody cared, bit %d",
-			       bit);
-			/* Mask this interrupt so it won't happen again */
-			irqstr_mask_int(line_index * IRQSTR_IRQS_PER_LINE + bit);
-		}
-	}
-}
-
-static inline void irq_handler(void *data, uint32_t line_index)
-{
-	struct irq_desc *parent = data;
-	struct irq_cascade_desc *cascade =
-		container_of(parent, struct irq_cascade_desc, desc);
-	uint64_t status;
-	uint32_t tries = IRQ_MAX_TRIES;
-
-	status = get_irqsteer_interrupts(line_index);
-
-	while (status) {
-		/* Handle current interrupts */
-		handle_irq_batch(cascade, line_index, status);
-
-		/* Any interrupts happened while we were handling the
-		 * current ones?
-		 */
-		status = get_irqsteer_interrupts(line_index);
-		if (!status)
-			break;
-
-		/* Any device keeping interrupting while we're handling
-		 * or can't clear?
-		 */
-
-		if (!--tries) {
-			tries = IRQ_MAX_TRIES;
-			tr_err(&irq_i_tr, "IRQ storm, status 0x%08x%08x",
-			       (uint32_t)(status >> 32), (uint32_t)status);
-		}
-	}
-}
-
-#define DEFINE_IRQ_HANDLER(n) \
-	static inline void irqstr_irqhandler_##n(void *arg) \
-	{ \
-		irq_handler(arg, n); \
-	}
-
-DEFINE_IRQ_HANDLER(0)
-DEFINE_IRQ_HANDLER(1)
-DEFINE_IRQ_HANDLER(2)
-DEFINE_IRQ_HANDLER(3)
-DEFINE_IRQ_HANDLER(4)
-DEFINE_IRQ_HANDLER(5)
-DEFINE_IRQ_HANDLER(6)
-DEFINE_IRQ_HANDLER(7)
-
-static void irq_mask(struct irq_desc *desc, uint32_t irq, unsigned int core)
-{
-	uint32_t irq_base = desc->irq - IRQ_NUM_IRQSTR_DSP0;
-
-	/* Compute the actual IRQ_STEER IRQ number */
-	irq_base *= IRQSTR_IRQS_PER_LINE;
-	irq += irq_base;
-
-	irqstr_mask_int(irq);
-}
-
-static void irq_unmask(struct irq_desc *desc, uint32_t irq, unsigned int core)
-{
-	uint32_t irq_base = desc->irq - IRQ_NUM_IRQSTR_DSP0;
-
-	/* Compute the actual IRQ_STEER IRQ number */
-	irq_base *= IRQSTR_IRQS_PER_LINE;
-	irq += irq_base;
-
-	irqstr_unmask_int(irq);
-}
-
-static const struct irq_cascade_ops irq_ops = {
-	.mask = irq_mask,
-	.unmask = irq_unmask,
-};
-
-/* IRQ_STEER interrupts */
-#define IRQSTR_CASCADE_TMPL_DECL(n) \
-	{ \
-		.name = "irqsteer" #n, \
-		.irq = IRQ_NUM_IRQSTR_DSP##n, \
-		.handler = irqstr_irqhandler_##n, \
-		.ops = &irq_ops, \
-		.global_mask = false, \
-	},
-
-static const struct irq_cascade_tmpl dsp_irq[] = {
-	IRQSTR_CASCADE_TMPL_DECL(0)
-	IRQSTR_CASCADE_TMPL_DECL(1)
-	IRQSTR_CASCADE_TMPL_DECL(2)
-	IRQSTR_CASCADE_TMPL_DECL(3)
-	IRQSTR_CASCADE_TMPL_DECL(4)
-	IRQSTR_CASCADE_TMPL_DECL(5)
-	IRQSTR_CASCADE_TMPL_DECL(6)
-	IRQSTR_CASCADE_TMPL_DECL(7)
-};
-
-int irqstr_get_sof_int(int irqstr_int)
-{
-	int line, irq;
-
-	/* Is it a valid interrupt? */
-	if (irqstr_int < 0 || irqstr_int >= IRQSTR_IRQS_NUM)
-		return -EINVAL;
-
-	line = irqstr_int / IRQSTR_IRQS_PER_LINE;
-	irq = irqstr_int % IRQSTR_IRQS_PER_LINE;
-
-	return interrupt_get_irq(irq, irq_name_irqsteer[line]);
-}
-
-void platform_interrupt_init(void)
-{
-	int i;
-
-	/* Turn off the hardware so we don't have stray interrupts while
-	 * initializing
-	 */
-	irqstr_disable_hw();
-	/* Mask every external IRQ first */
-	for (i = 0; i < IRQSTR_IRQS_REGISTERS_NUM; i++)
-		irqstr_write(IRQSTR_CH_MASK(i), 0);
-	/* Turn on the IRQ_STEER hardware */
-	irqstr_enable_hw();
-
-	for (i = 0; i < ARRAY_SIZE(dsp_irq); i++)
-		interrupt_cascade_register(dsp_irq + i);
-}
-
-#ifndef __ZEPHYR__
-void platform_interrupt_set(uint32_t irq)
-{
-	if (interrupt_is_dsp_direct(irq))
-		arch_interrupt_set(irq);
-}
-
-void platform_interrupt_clear(uint32_t irq, uint32_t mask)
-{
-	if (interrupt_is_dsp_direct(irq))
-		arch_interrupt_clear(irq);
-}
-#endif /* __ZEPHYR */
-
-uint32_t platform_interrupt_get_enabled(void)
-{
-	return 0;
-}
-
-void interrupt_mask(uint32_t irq, unsigned int cpu)
-{
-	struct irq_cascade_desc *cascade = interrupt_get_parent(irq);
-
-	if (cascade && cascade->ops->mask)
-		cascade->ops->mask(&cascade->desc, irq - cascade->irq_base,
-				   cpu);
-}
-
-void interrupt_unmask(uint32_t irq, unsigned int cpu)
-{
-	struct irq_cascade_desc *cascade = interrupt_get_parent(irq);
-
-	if (cascade && cascade->ops->unmask)
-		cascade->ops->unmask(&cascade->desc, irq - cascade->irq_base,
-				     cpu);
-}
diff --git a/src/drivers/imx/micfil.c b/src/drivers/imx/micfil.c
deleted file mode 100644
index e0209fa9c815..000000000000
--- a/src/drivers/imx/micfil.c
+++ /dev/null
@@ -1,336 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-//
-// Copyright 2023 NXP
-//
-// Author: Daniel Baluta <daniel.baluta@nxp.com>
-
-#include <sof/audio/component.h>
-#include <sof/audio/format.h>
-#include <rtos/alloc.h>
-#include <sof/drivers/micfil.h>
-#include <sof/lib/dai.h>
-#include <sof/lib/dma.h>
-#include <sof/lib/memory.h>
-#include <sof/lib/pm_runtime.h>
-#include <sof/lib/uuid.h>
-#include <ipc/dai.h>
-#include <errno.h>
-#include <stddef.h>
-#include <stdint.h>
-
-LOG_MODULE_REGISTER(micfil_dai, CONFIG_SOF_LOG_LEVEL);
-
-SOF_DEFINE_REG_UUID(micfil);
-
-/* unused with Zephyr, generates no output */
-DECLARE_TR_CTX(micfil_tr, SOF_UUID(micfil_uuid), LOG_LEVEL_INFO);
-
-#define MICFIL_OSR_DEFAULT		16
-/* set default gain to 2 */
-#define MICFIL_DEFAULT_ADJ_RANGE	0x22222222
-#define MICFIL_CLK_ROOT			24576000
-
-enum micfil_quality {
-	QUALITY_HIGH,
-	QUALITY_MEDIUM,
-	QUALITY_LOW,
-	QUALITY_VLOW0,
-	QUALITY_VLOW1,
-	QUALITY_VLOW2,
-};
-
-static void micfil_reset(struct dai *dai)
-{
-	dai_update_bits(dai, REG_MICFIL_CTRL1, MICFIL_CTRL1_MDIS, 0);
-	dai_update_bits(dai, REG_MICFIL_CTRL1, MICFIL_CTRL1_SRES, MICFIL_CTRL1_SRES);
-	dai_update_bits(dai, REG_MICFIL_STAT, 0xff, 0xff);
-}
-
-static int micfil_get_hw_params(struct dai *dai,
-				struct sof_ipc_stream_params *params, int dir)
-{
-	struct micfil_pdata *micfil = dai_get_drvdata(dai);
-
-	dai_info(dai, "entry");
-
-	params->rate = micfil->params.pdm_rate;
-	params->channels = micfil->params.pdm_ch;
-	params->buffer_fmt = SOF_IPC_BUFFER_INTERLEAVED;
-	params->frame_fmt = SOF_IPC_FRAME_S32_LE;
-
-	return 0;
-}
-
-static int micfil_set_quality(struct dai *dai)
-{
-	struct micfil_pdata *micfil = dai_get_drvdata(dai);
-	int qsel;
-
-	switch (micfil->quality) {
-	case QUALITY_HIGH:
-		qsel = MICFIL_QSEL_HIGH_QUALITY;
-		break;
-	case QUALITY_MEDIUM:
-		qsel = MICFIL_QSEL_MEDIUM_QUALITY;
-		break;
-	case QUALITY_LOW:
-		qsel = MICFIL_QSEL_LOW_QUALITY;
-		break;
-	case QUALITY_VLOW0:
-		qsel = MICFIL_QSEL_VLOW0_QUALITY;
-		break;
-	case QUALITY_VLOW1:
-		qsel = MICFIL_QSEL_VLOW1_QUALITY;
-		break;
-	case QUALITY_VLOW2:
-		qsel = MICFIL_QSEL_VLOW2_QUALITY;
-		break;
-	default:
-		dai_err(dai, "MICFIL: invalid quality mode %d", micfil->quality);
-		return -EINVAL;
-	}
-
-	dai_update_bits(dai, REG_MICFIL_CTRL2, MICFIL_CTRL2_QSEL,
-			MICFIL_CTRL2_QSEL_BITS(qsel));
-
-	return 0;
-}
-
-/* get_pdm_clk - computes the product between k-factor and PDM_CLK rate
- * @param dai, SOF DAI struct
- * @param rate, output sampling rate
- *
- * PDM_CLK depends on Quality Mode, output sampling rate and quality
- * mode
- */
-static unsigned int micfil_get_pdm_clk(struct dai *dai, int rate)
-{
-	unsigned int osr;
-	unsigned int qsel;
-	unsigned int ctrl2_reg;
-	unsigned int pdm_clk = 0;
-
-	ctrl2_reg = dai_read(dai, REG_MICFIL_CTRL2);
-	osr = 16 - ((ctrl2_reg & MICFIL_CTRL2_CICOSR) >> MICFIL_CTRL2_CICOSR_SHIFT);
-	qsel = (ctrl2_reg & MICFIL_CTRL2_QSEL) >> MICFIL_CTRL2_QSEL_SHIFT;
-
-	/* See Quality modes chapter in MICFIL documentation */
-	switch (qsel) {
-	case MICFIL_QSEL_HIGH_QUALITY:
-		pdm_clk = rate * 8 * osr / 2; /* kfactor = 0.5 */
-		break;
-	case MICFIL_QSEL_MEDIUM_QUALITY:
-	case MICFIL_QSEL_VLOW0_QUALITY:
-		pdm_clk = rate * 4 * osr; /* kfactor = 1 */
-		break;
-	case MICFIL_QSEL_LOW_QUALITY:
-	case MICFIL_QSEL_VLOW1_QUALITY:
-		pdm_clk = rate * 2 * osr * 2; /* kfactor = 2 */
-		break;
-	case MICFIL_QSEL_VLOW2_QUALITY:
-		pdm_clk = rate * osr; /* kfactor = 4 */
-		break;
-	default:
-		break;
-	}
-
-	return pdm_clk;
-}
-
-static int micfil_get_clk_div(struct dai *dai, int rate)
-{
-	unsigned int pdm_clk;
-
-	pdm_clk = micfil_get_pdm_clk(dai, rate);
-	if (!pdm_clk)
-		return -EINVAL;
-
-	/*
-	 *
-	 * See: Clock divider chapter from micfil documentation
-	 * PDM_CLK rate = MICFIL_CLK_ROOT rate / (2 * K * CLKDIV)
-	 *
-	 * this means that if we want to compute CLKDIV then:
-	 * CLKDIV = MICFIL_CLK_ROOT rate / (PDM_CLK rate * K * 2)
-	 *
-	 * micfil_get_pdm_clk function returns K * PDM_CLK rate
-	 */
-	return MICFIL_CLK_ROOT / (pdm_clk * 2);
-}
-
-static int micfil_set_clock_params(struct dai *dai, int rate)
-{
-	int clk_div;
-
-	dai_update_bits(dai, REG_MICFIL_CTRL2, MICFIL_CTRL2_CICOSR,
-			MICFIL_CTRL2_CICOSR_BITS(MICFIL_OSR_DEFAULT));
-
-	clk_div = micfil_get_clk_div(dai, rate);
-	if (clk_div < 0)
-		return clk_div;
-
-	dai_update_bits(dai, REG_MICFIL_CTRL2, MICFIL_CTRL2_CLKDIV,
-			MICFIL_CTRL2_CLKDIV_BITS(clk_div));
-
-	return 0;
-}
-
-static int micfil_set_config(struct dai *dai, struct ipc_config_dai *common_config,
-			     const void *spec_config)
-{
-	int i, ret;
-	unsigned int val = 0;
-	struct micfil_pdata *micfil = dai_get_drvdata(dai);
-	const struct sof_ipc_dai_config *config = spec_config;
-
-	micfil->params = config->micfil;
-
-	dai_info(dai, "dai_idx %d channels %d sampling_freq %d",
-		 common_config->dai_index, micfil->params.pdm_ch, micfil->params.pdm_rate);
-
-	/* disable the module */
-	dai_update_bits(dai, REG_MICFIL_CTRL1, MICFIL_CTRL1_PDMIEN, 0);
-
-	micfil_set_quality(dai);
-
-	/* set default gain to 2 */
-	dai_write(dai, REG_MICFIL_OUT_CTRL, MICFIL_DEFAULT_ADJ_RANGE);
-
-	/* set DC Remover in bypass mode */
-	for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++)
-		val |= MICFIL_DC_BYPASS << MICFIL_DC_CHX_SHIFT(i);
-	dai_update_bits(dai, REG_MICFIL_DC_CTRL, MICFIL_DC_CTRL_CONFIG, val);
-
-	/* FIFO WMK */
-	dai_update_bits(dai, REG_MICFIL_FIFO_CTRL, MICFIL_FIFO_CTRL_FIFOWMK,
-			MICFIL_FIFO_CTRL_FIFOWMK_BITS(31));
-
-	/* enable channels */
-	dai_update_bits(dai, REG_MICFIL_CTRL1, MICFIL_CTRL1_CHNEN,
-			((1 << micfil->params.pdm_ch) - 1));
-
-	ret = micfil_set_clock_params(dai, micfil->params.pdm_rate);
-	if (ret < 0)
-		return ret;
-
-	return 0;
-}
-
-static int micfil_get_handshake(struct dai *dai, int direction, int stream_id)
-{
-	return dai->plat_data.fifo[SOF_IPC_STREAM_CAPTURE].handshake;
-}
-
-static int micfil_get_fifo(struct dai *dai, int direction, int stream_id)
-{
-	return dai->plat_data.fifo[SOF_IPC_STREAM_CAPTURE].offset;
-}
-
-static int micfil_get_fifo_depth(struct dai *dai, int direction)
-{
-	return dai->plat_data.fifo[SOF_IPC_STREAM_CAPTURE].depth;
-}
-
-static void micfil_start(struct dai *dai)
-{
-	dai_info(dai, "entry");
-
-	micfil_reset(dai);
-
-	/* DMA Interrupt Selection - DISEL bits
-	 * 00 - DMA and IRQ disabled
-	 * 01 - DMA req enabled
-	 * 10 - IRQ enabled
-	 * 11 - reserved
-	 */
-	dai_update_bits(dai, REG_MICFIL_CTRL1,
-			MICFIL_CTRL1_DISEL,
-			MICFIL_CTRL1_DISEL_BITS(MICFIL_CTRL1_DISEL_DMA));
-
-	/* Enable the module */
-	dai_update_bits(dai, REG_MICFIL_CTRL1, MICFIL_CTRL1_PDMIEN, MICFIL_CTRL1_PDMIEN);
-}
-
-static void micfil_stop(struct dai *dai)
-{
-	dai_info(dai, "entry");
-
-	/* Disable the module */
-	dai_update_bits(dai, REG_MICFIL_CTRL1, MICFIL_CTRL1_PDMIEN, 0);
-
-	dai_update_bits(dai, REG_MICFIL_CTRL1, MICFIL_CTRL1_DISEL,
-			MICFIL_CTRL1_DISEL_BITS(MICFIL_CTRL1_DISEL_DISABLE));
-}
-
-static int micfil_trigger(struct dai *dai, int cmd, int direction)
-{
-	dai_info(dai, "cmd %d dir %d", cmd, direction);
-
-	switch (cmd) {
-	case COMP_TRIGGER_START:
-	case COMP_TRIGGER_RELEASE:
-		micfil_start(dai);
-		break;
-	case COMP_TRIGGER_STOP:
-	case COMP_TRIGGER_PAUSE:
-		micfil_stop(dai);
-	case COMP_TRIGGER_PRE_START:
-	case COMP_TRIGGER_PRE_RELEASE:
-		break;
-	default:
-		dai_err(dai, "MICFIL: invalid trigger cmd %d", cmd);
-		return -EINVAL;
-	}
-
-	return 0;
-}
-
-static int micfil_probe(struct dai *dai)
-{
-	struct micfil_pdata *micfil;
-
-	dai_info(dai, "entry");
-
-	micfil = rzalloc(SOF_MEM_FLAG_KERNEL | SOF_MEM_FLAG_COHERENT, sizeof(*micfil));
-	if (!micfil) {
-		dai_err(dai, "micfil probe failed");
-		return -ENOMEM;
-	}
-
-	micfil->quality = QUALITY_VLOW0;
-
-	dai_set_drvdata(dai, micfil);
-
-	return 0;
-}
-
-static int micfil_remove(struct dai *dai)
-{
-	struct micfil_pdata *micfil = dai_get_drvdata(dai);
-
-	dai_info(dai, "entry");
-
-	rfree(micfil);
-	dai_set_drvdata(dai, NULL);
-
-	return 0;
-}
-
-const struct dai_driver micfil_driver = {
-	.type = SOF_DAI_IMX_MICFIL,
-	.uid = SOF_UUID(micfil_uuid),
-#if !CONFIG_ZEPHYR_LOG
-	.tctx = &micfil_tr,
-#endif
-	.dma_dev = SOF_DMA_DEV_MICFIL,
-	.ops = {
-		.trigger		= micfil_trigger,
-		.set_config		= micfil_set_config,
-		.get_hw_params		= micfil_get_hw_params,
-		.get_handshake		= micfil_get_handshake,
-		.get_fifo		= micfil_get_fifo,
-		.get_fifo_depth		= micfil_get_fifo_depth,
-		.probe			= micfil_probe,
-		.remove			= micfil_remove,
-	},
-};
diff --git a/src/drivers/imx/sai.c b/src/drivers/imx/sai.c
deleted file mode 100644
index 9adffd8e4521..000000000000
--- a/src/drivers/imx/sai.c
+++ /dev/null
@@ -1,577 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-//
-// Copyright 2019 NXP
-//
-// Author: Daniel Baluta <daniel.baluta@nxp.com>
-// Author: Jerome Laclavere <jerome.laclavere@nxp.com>
-// Author: Guido Roncarolo <guido.roncarolo@nxp.com>
-
-#include <sof/audio/component.h>
-#include <rtos/bit.h>
-#include <sof/drivers/edma.h>
-#include <sof/drivers/sai.h>
-#include <sof/lib/dai.h>
-#include <sof/lib/dma.h>
-#include <rtos/wait.h>
-#include <sof/lib/uuid.h>
-#include <ipc/dai.h>
-#include <errno.h>
-#include <stdint.h>
-
-LOG_MODULE_REGISTER(sai, CONFIG_SOF_LOG_LEVEL);
-
-SOF_DEFINE_REG_UUID(sai);
-
-/* unused with Zephyr, generates no output */
-DECLARE_TR_CTX(sai_tr, SOF_UUID(sai_uuid), LOG_LEVEL_INFO);
-
-#define REG_TX_DIR 0
-#define REG_RX_DIR 1
-
-static void sai_start(struct dai *dai, int direction)
-{
-	dai_info(dai, "SAI: entry");
-
-	struct sai_pdata *sai = dai_get_drvdata(dai);
-	int chan_idx = 0;
-	uint32_t xcsr = 0U;
-	int i;
-	int n;
-#ifdef CONFIG_IMX8ULP
-	int fifo_offset = 0;
-#endif
-
-	if (direction == DAI_DIR_CAPTURE) {
-		/* Software Reset */
-		dai_update_bits(dai, REG_SAI_XCSR(DAI_DIR_CAPTURE),
-				REG_SAI_CSR_SR, REG_SAI_CSR_SR);
-		/* Clear SR bit to finish the reset */
-		dai_update_bits(dai, REG_SAI_XCSR(DAI_DIR_CAPTURE),
-				REG_SAI_CSR_SR, 0U);
-		/* Check if the opposite direction is also disabled */
-		xcsr = dai_read(dai, REG_SAI_XCSR(DAI_DIR_PLAYBACK));
-		if (!(xcsr & REG_SAI_CSR_FRDE)) {
-			/* Software Reset */
-			dai_update_bits(dai, REG_SAI_XCSR(DAI_DIR_PLAYBACK),
-					REG_SAI_CSR_SR, REG_SAI_CSR_SR);
-			/* Clear SR bit to finish the reset */
-			dai_update_bits(dai, REG_SAI_XCSR(DAI_DIR_PLAYBACK),
-					REG_SAI_CSR_SR, 0U);
-			/* Transmitter enable */
-			dai_update_bits(dai, REG_SAI_XCSR(DAI_DIR_PLAYBACK),
-					REG_SAI_CSR_TERE, REG_SAI_CSR_TERE);
-		}
-	} else {
-		/* Check if the opposite direction is also disabled */
-		xcsr = dai_read(dai, REG_SAI_XCSR(DAI_DIR_CAPTURE));
-		if (!(xcsr & REG_SAI_CSR_FRDE)) {
-			/* Software Reset */
-			dai_update_bits(dai, REG_SAI_XCSR(DAI_DIR_PLAYBACK),
-					REG_SAI_CSR_SR, REG_SAI_CSR_SR);
-			/* Clear SR bit to finish the reset */
-			dai_update_bits(dai, REG_SAI_XCSR(DAI_DIR_PLAYBACK),
-					REG_SAI_CSR_SR, 0U);
-		}
-	}
-
-	/* W1C */
-	dai_update_bits(dai, REG_SAI_XCSR(direction),
-			REG_SAI_CSR_FEF, 1);
-	dai_update_bits(dai, REG_SAI_XCSR(direction),
-			REG_SAI_CSR_SEF, 1);
-	dai_update_bits(dai, REG_SAI_XCSR(direction),
-			REG_SAI_CSR_WSF, 1);
-
-	/*
-	 * Add one frame of data to FIFO before TRCE is enabled.
-	 * In FIFO words this equates to tdm_slots/(slots_per_32b_fifo_word). Minimum: one word.
-	 * Not performing this 'priming' can lead to negative effects like shifted
-	 * and / or missing slots.
-	 * TODO: check if that works in all situations
-	 */
-
-	switch (sai->params.tdm_slot_width) {
-	case 8:
-		n = sai->params.tdm_slots / 4;
-		break;
-	case 16:
-		n = sai->params.tdm_slots / 2;
-		break;
-	default:
-		n = sai->params.tdm_slots;
-		break;
-	}
-
-	if (!n)
-		n = 1;
-
-	if (direction == DAI_DIR_PLAYBACK) {
-		for (i = 0; i < n; i++)
-			dai_write(dai, REG_SAI_TDR0, 0x0);
-	} else {
-		for (i = 0; i < n; i++)
-			dai_write(dai, REG_SAI_RDR0, 0x0);
-	}
-
-	/* enable DMA requests */
-	dai_update_bits(dai, REG_SAI_XCSR(direction),
-			REG_SAI_CSR_FRDE, REG_SAI_CSR_FRDE);
-
-	chan_idx = BIT(0);
-	/* RX3 supports capture on imx8ulp */
-#ifdef CONFIG_IMX8ULP
-	if (direction == DAI_DIR_CAPTURE) {
-		fifo_offset = (dai_fifo(dai, DAI_DIR_CAPTURE) - dai_base(dai) - REG_SAI_RDR0) >> 2;
-		chan_idx = BIT(fifo_offset);
-	} else {
-		fifo_offset = (dai_fifo(dai, DAI_DIR_PLAYBACK) - dai_base(dai) - REG_SAI_TDR0) >> 2;
-		chan_idx = BIT(fifo_offset);
-	}
-#endif
-
-	/* transmit/receive data channel enable */
-	dai_update_bits(dai, REG_SAI_XCR3(direction),
-			REG_SAI_CR3_TRCE_MASK, REG_SAI_CR3_TRCE(chan_idx));
-
-	/* transmitter/receiver enable */
-	dai_update_bits(dai, REG_SAI_XCSR(direction),
-			REG_SAI_CSR_TERE, REG_SAI_CSR_TERE);
-}
-
-static void sai_release(struct dai *dai, int direction)
-{
-	dai_info(dai, "SAI: entry");
-
-	int chan_idx = 0;
-#ifdef CONFIG_IMX8ULP
-	int fifo_offset = 0;
-#endif
-	/* enable DMA requests */
-	dai_update_bits(dai, REG_SAI_XCSR(direction),
-			REG_SAI_CSR_FRDE, REG_SAI_CSR_FRDE);
-
-	chan_idx = BIT(0);
-#ifdef CONFIG_IMX8ULP
-	if (direction == DAI_DIR_CAPTURE) {
-		fifo_offset = (dai_fifo(dai, DAI_DIR_CAPTURE) - dai_base(dai) - REG_SAI_RDR0) >> 2;
-		chan_idx = BIT(fifo_offset);
-	} else {
-		fifo_offset = (dai_fifo(dai, DAI_DIR_PLAYBACK) - dai_base(dai) - REG_SAI_TDR0) >> 2;
-		chan_idx = BIT(fifo_offset);
-	}
-#endif
-
-	/* transmit/receive data channel enable */
-	dai_update_bits(dai, REG_SAI_XCR3(direction),
-			REG_SAI_CR3_TRCE_MASK, REG_SAI_CR3_TRCE(chan_idx));
-
-	/* transmitter/receiver enable */
-	dai_update_bits(dai, REG_SAI_XCSR(direction),
-			REG_SAI_CSR_TERE, REG_SAI_CSR_TERE);
-}
-
-static void sai_stop(struct dai *dai, int direction)
-{
-	dai_info(dai, "SAI: entry");
-
-	uint32_t xcsr = 0U;
-	int ret = 0;
-
-	/* Disable DMA request */
-	dai_update_bits(dai, REG_SAI_XCSR(direction),
-			REG_SAI_CSR_FRDE, 0);
-
-	/* Transmit/Receive data channel disable */
-	dai_update_bits(dai, REG_SAI_XCR3(direction),
-			REG_SAI_CR3_TRCE_MASK,
-			REG_SAI_CR3_TRCE(0));
-
-	/* Disable interrupts */
-	dai_update_bits(dai, REG_SAI_XCSR(direction),
-			REG_SAI_CSR_XIE_MASK, 0);
-
-	/* Disable transmitter/receiver */
-	if (direction == DAI_DIR_CAPTURE) {
-		dai_update_bits(dai, REG_SAI_XCSR(DAI_DIR_CAPTURE), REG_SAI_CSR_TERE, 0);
-		ret = poll_for_register_delay(dai_base(dai) +
-					      REG_SAI_XCSR(DAI_DIR_CAPTURE),
-					      REG_SAI_CSR_TERE, 0, 100);
-
-		/* Check if the opposite direction is also disabled */
-		xcsr = dai_read(dai, REG_SAI_XCSR(DAI_DIR_PLAYBACK));
-		if (!(xcsr & REG_SAI_CSR_FRDE)) {
-			dai_update_bits(dai, REG_SAI_XCSR(DAI_DIR_PLAYBACK), REG_SAI_CSR_TERE, 0);
-			ret = poll_for_register_delay(dai_base(dai) +
-						      REG_SAI_XCSR(DAI_DIR_PLAYBACK),
-						      REG_SAI_CSR_TERE, 0, 100);
-		}
-	} else {
-		/* Check if the opposite direction is also disabled */
-		xcsr = dai_read(dai, REG_SAI_XCSR(DAI_DIR_CAPTURE));
-		if (!(xcsr & REG_SAI_CSR_FRDE)) {
-			dai_update_bits(dai, REG_SAI_XCSR(DAI_DIR_PLAYBACK), REG_SAI_CSR_TERE, 0);
-			ret = poll_for_register_delay(dai_base(dai) +
-						      REG_SAI_XCSR(DAI_DIR_PLAYBACK),
-						      REG_SAI_CSR_TERE, 0, 100);
-		}
-	}
-
-	if (ret < 0)
-		dai_warn(dai, "sai: poll for register delay failed");
-}
-
-static inline int sai_set_config(struct dai *dai, struct ipc_config_dai *common_config,
-				 const void *spec_config)
-{
-	dai_info(dai, "SAI: entry");
-	const struct sof_ipc_dai_config *config = spec_config;
-	uint32_t val_cr2 = 0, val_cr4 = 0, val_cr5 = 0;
-	uint32_t mask_cr2 = 0, mask_cr4 = 0, mask_cr5 = 0;
-	uint32_t clk_div;
-	bool tdm_enable;
-	struct sai_pdata *sai = dai_get_drvdata(dai);
-
-	sai->config = *config;
-	sai->params = config->sai;
-
-	/* bit width of a single slot; FIFO word always 32b */
-	uint32_t sywd = sai->params.tdm_slot_width;
-
-	/*
-	 * Divide the audio main clock to generate the bit clock when
-	 * configured for an internal bit clock.
-	 * The division value is (DIV + 1) * 2.
-	 * If mclk == bclk set the divider bypass bit, REG_SAI_CR2_BYP.
-	 */
-
-	if (config->sai.mclk_rate == config->sai.bclk_rate) {
-		val_cr2 |= REG_SAI_CR2_BYP;
-		clk_div = 0;
-	} else {
-		clk_div = (config->sai.mclk_rate / config->sai.bclk_rate / 2) - 1;
-	}
-
-	/* TDM mode is enabled only when fmt is dsp_a or dsp_b and
-	 * we can have from 1 to 32 channels.
-	 * for any other formats we assume I2S like interface where
-	 * audio frames have 2 channels, even for mono scenario. The
-	 * second channel will be masked out.
-	 */
-	tdm_enable = false;
-
-	switch (config->format & SOF_DAI_FMT_FORMAT_MASK) {
-	case SOF_DAI_FMT_I2S:
-		/*
-		 * Frame low, 1clk before data, one word length for frame sync,
-		 * frame sync starts one serial clock cycle earlier,
-		 * that is, together with the last bit of the previous
-		 * data word.
-		 */
-#ifdef CONFIG_IMX8ULP
-		val_cr4 |= REG_SAI_CR4_FSE;
-#else
-		val_cr2 |= REG_SAI_CR2_BCP;
-		val_cr4 |= REG_SAI_CR4_FSE | REG_SAI_CR4_FSP;
-		val_cr4 |= REG_SAI_CR4_SYWD(sywd);
-#endif
-		break;
-	case SOF_DAI_FMT_LEFT_J:
-		/*
-		 * Frame high, one word length for frame sync,
-		 * frame sync asserts with the first bit of the frame.
-		 */
-		val_cr2 |= REG_SAI_CR2_BCP;
-		val_cr4 |= REG_SAI_CR4_SYWD(sywd);
-		break;
-	case SOF_DAI_FMT_DSP_A:
-		/*
-		 * Frame high, 1clk before data, one bit for frame sync,
-		 * frame sync starts one serial clock cycle earlier,
-		 * that is, together with the last bit of the previous
-		 * data word.
-		 */
-		val_cr2 |= REG_SAI_CR2_BCP;
-		val_cr4 |= REG_SAI_CR4_FSE;
-		val_cr4 |= REG_SAI_CR4_SYWD(1U);
-		tdm_enable = true;
-		break;
-	case SOF_DAI_FMT_DSP_B:
-		/*
-		 * Frame high, one bit for frame sync,
-		 * frame sync asserts with the first bit of the frame.
-		 */
-		val_cr2 |= REG_SAI_CR2_BCP;
-		val_cr4 |= REG_SAI_CR4_SYWD(1U);
-		tdm_enable = true;
-		break;
-	case SOF_DAI_FMT_PDM:
-		val_cr2 |= REG_SAI_CR2_BCP;
-		val_cr4 &= ~REG_SAI_CR4_MF;
-		break;
-	case SOF_DAI_FMT_RIGHT_J:
-		val_cr4 |= REG_SAI_CR4_SYWD(sywd);
-		break;
-	default:
-		return -EINVAL;
-	}
-
-	/* DAI clock inversion */
-	switch (config->format & SOF_DAI_FMT_INV_MASK) {
-	case SOF_DAI_FMT_IB_IF:
-		/* Invert both clocks */
-		val_cr2 ^= REG_SAI_CR2_BCP;
-		val_cr4 ^= REG_SAI_CR4_FSP;
-		break;
-	case SOF_DAI_FMT_IB_NF:
-		/* Invert bit clock */
-		val_cr2 ^= REG_SAI_CR2_BCP;
-		break;
-	case SOF_DAI_FMT_NB_IF:
-		/* Invert frame clock */
-		val_cr4 ^= REG_SAI_CR4_FSP;
-		break;
-	case SOF_DAI_FMT_NB_NF:
-		/* Nothing to do for both normal cases */
-		break;
-	default:
-		return -EINVAL;
-	}
-
-	/* DAI clock provider masks */
-	switch (config->format & SOF_DAI_FMT_CLOCK_PROVIDER_MASK) {
-	case SOF_DAI_FMT_CBC_CFC:
-		dai_info(dai, "SAI: codec is consumer");
-		val_cr2 |= REG_SAI_CR2_MSEL_MCLK1;
-		val_cr2 |= REG_SAI_CR2_BCD_MSTR;
-		val_cr2 |= clk_div;
-		val_cr4 |= REG_SAI_CR4_FSD_MSTR;
-		break;
-	case SOF_DAI_FMT_CBP_CFP:
-		dai_info(dai, "SAI: codec is provider");
-		/*
-		 * fields CR2_DIV and CR2_MSEL not relevant in consumer mode.
-		 * fields CR2_BCD and CR4_MFSD already at 0
-		 */
-		break;
-	case SOF_DAI_FMT_CBC_CFP:
-		val_cr2 |= REG_SAI_CR2_BCD_MSTR;
-		val_cr2 |= clk_div;
-		break;
-	case SOF_DAI_FMT_CBP_CFC:
-		val_cr4 |= REG_SAI_CR4_FSD_MSTR;
-		val_cr2 |= clk_div;
-		break;
-	default:
-		return -EINVAL;
-	}
-
-#ifndef CONFIG_IMX8ULP
-	switch (sai->params.tdm_slot_width) {
-	case 8:
-		val_cr4 |= REG_SAI_CR4_FPACK_8;
-		break;
-	case 16:
-		val_cr4 |= REG_SAI_CR4_FPACK_16;
-		break;
-	default:
-		break;
-	}
-#endif
-
-	if (tdm_enable)
-		val_cr4 |= REG_SAI_CR4_FRSZ(sai->params.tdm_slots);
-	else
-		val_cr4 |= REG_SAI_CR4_FRSZ(
-		    (sai->params.tdm_slots == 1) ? 2 : sai->params.tdm_slots);
-
-	val_cr4 |= REG_SAI_CR4_CHMOD;
-	val_cr4 |= REG_SAI_CR4_MF;
-
-	val_cr5 |= REG_SAI_CR5_WNW(sywd) | REG_SAI_CR5_W0W(sywd) |
-			REG_SAI_CR5_FBT(sywd);
-
-	mask_cr2  = REG_SAI_CR2_BCP | REG_SAI_CR2_BCD_MSTR |
-			REG_SAI_CR2_BYP_MASK |
-			REG_SAI_CR2_MSEL_MASK | REG_SAI_CR2_DIV_MASK;
-
-	mask_cr4  = REG_SAI_CR4_MF | REG_SAI_CR4_FSE |
-			REG_SAI_CR4_FSP | REG_SAI_CR4_FSD_MSTR |
-			REG_SAI_CR4_FRSZ_MASK | REG_SAI_CR4_SYWD_MASK |
-			REG_SAI_CR4_CHMOD_MASK | REG_SAI_CR4_FPACK_MASK;
-
-	mask_cr5  = REG_SAI_CR5_WNW_MASK | REG_SAI_CR5_W0W_MASK |
-			REG_SAI_CR5_FBT_MASK;
-
-	dai_update_bits(dai, REG_SAI_XCR1(REG_TX_DIR), REG_SAI_CR1_RFW_MASK,
-			dai->plat_data.fifo[REG_TX_DIR].watermark);
-	dai_update_bits(dai, REG_SAI_XCR2(REG_TX_DIR), mask_cr2, val_cr2);
-	dai_update_bits(dai, REG_SAI_XCR4(REG_TX_DIR), mask_cr4, val_cr4);
-	dai_update_bits(dai, REG_SAI_XCR5(REG_TX_DIR), mask_cr5, val_cr5);
-	/* turn on (set to zero) slots */
-	dai_update_bits(dai, REG_SAI_XMR(REG_TX_DIR), REG_SAI_XMR_MASK,
-			~(sai->params.tx_slots));
-
-	val_cr2 |= REG_SAI_CR2_SYNC;
-	mask_cr2 |= REG_SAI_CR2_SYNC_MASK;
-
-	dai_update_bits(dai, REG_SAI_XCR1(REG_RX_DIR), REG_SAI_CR1_RFW_MASK,
-			dai->plat_data.fifo[REG_RX_DIR].watermark);
-	dai_update_bits(dai, REG_SAI_XCR2(REG_RX_DIR), mask_cr2, val_cr2);
-	dai_update_bits(dai, REG_SAI_XCR4(REG_RX_DIR), mask_cr4, val_cr4);
-	dai_update_bits(dai, REG_SAI_XCR5(REG_RX_DIR), mask_cr5, val_cr5);
-	/* turn on (set to zero) slots */
-	dai_update_bits(dai, REG_SAI_XMR(REG_RX_DIR), REG_SAI_XMR_MASK,
-			~(sai->params.rx_slots));
-
-#if defined(CONFIG_IMX8M) || defined(CONFIG_IMX93_A55)
-	/*
-	 * For i.MX8MP, MCLK is bound with TX enable bit.
-	 * Therefore, enable transmitter to output MCLK
-	 */
-	dai_update_bits(dai, REG_SAI_XCSR(DAI_DIR_PLAYBACK),
-			REG_SAI_CSR_TERE, REG_SAI_CSR_TERE);
-	dai_update_bits(dai, REG_SAI_MCTL, REG_SAI_MCTL_MCLK_EN,
-			REG_SAI_MCTL_MCLK_EN);
-#endif
-
-	return 0;
-}
-
-static int sai_trigger(struct dai *dai, int cmd, int direction)
-{
-	dai_info(dai, "SAI: entry");
-
-	switch (cmd) {
-	case COMP_TRIGGER_START:
-		sai_start(dai, direction);
-		break;
-	case COMP_TRIGGER_RELEASE:
-		sai_release(dai, direction);
-		break;
-	case COMP_TRIGGER_STOP:
-	case COMP_TRIGGER_PAUSE:
-		sai_stop(dai, direction);
-		break;
-	case COMP_TRIGGER_PRE_START:
-	case COMP_TRIGGER_PRE_RELEASE:
-		break;
-	default:
-		dai_err(dai, "SAI: invalid trigger cmd %d", cmd);
-		break;
-	}
-	return 0;
-}
-
-static int sai_probe(struct dai *dai)
-{
-	struct sai_pdata *sai;
-
-	dai_info(dai, "SAI: entry");
-
-	/* allocate private data */
-	sai = rzalloc(SOF_MEM_FLAG_KERNEL | SOF_MEM_FLAG_COHERENT, sizeof(*sai));
-	if (!sai) {
-		dai_err(dai, "alloc failed");
-		return -ENOMEM;
-	}
-	dai_set_drvdata(dai, sai);
-
-	/* Software Reset for both Tx and Rx */
-	dai_update_bits(dai, REG_SAI_TCSR, REG_SAI_CSR_SR, REG_SAI_CSR_SR);
-	dai_update_bits(dai, REG_SAI_RCSR, REG_SAI_CSR_SR, REG_SAI_CSR_SR);
-
-	/* Clear SR bit to finish the reset */
-	dai_update_bits(dai, REG_SAI_TCSR, REG_SAI_CSR_SR, 0U);
-	dai_update_bits(dai, REG_SAI_RCSR, REG_SAI_CSR_SR, 0U);
-
-	/* Reset all Tx register values */
-	dai_write(dai, REG_SAI_TCR2, 0U);
-	dai_write(dai, REG_SAI_TCR3, 0U);
-	dai_write(dai, REG_SAI_TCR4, 0U);
-	dai_write(dai, REG_SAI_TCR5, 0U);
-	dai_write(dai, REG_SAI_TMR,  0U);
-
-	/* Reset all Rx register values */
-	dai_write(dai, REG_SAI_RCR2, 0U);
-	dai_write(dai, REG_SAI_RCR3, 0U);
-	dai_write(dai, REG_SAI_RCR4, 0U);
-	dai_write(dai, REG_SAI_RCR5, 0U);
-	dai_write(dai, REG_SAI_RMR,  0U);
-
-	return 0;
-}
-
-static int sai_remove(struct dai *dai)
-{
-	struct sai_pdata *sai = dai_get_drvdata(dai);
-
-	dai_info(dai, "entry");
-
-	rfree(sai);
-	dai_set_drvdata(dai, NULL);
-
-	return 0;
-}
-
-static int sai_get_handshake(struct dai *dai, int direction, int stream_id)
-{
-	return dai->plat_data.fifo[direction].handshake;
-}
-
-static int sai_get_fifo(struct dai *dai, int direction, int stream_id)
-{
-	switch (direction) {
-	case DAI_DIR_PLAYBACK:
-	case DAI_DIR_CAPTURE:
-		return dai_fifo(dai, direction); /* stream_id is unused */
-	default:
-		dai_err(dai, "Invalid direction");
-		return -EINVAL;
-	}
-}
-
-static int sai_get_fifo_depth(struct dai *dai, int direction)
-{
-	switch (direction) {
-	case DAI_DIR_PLAYBACK:
-	case DAI_DIR_CAPTURE:
-		return dai->plat_data.fifo[direction].depth;
-	default:
-		dai_err(dai, "Invalid direction");
-		return -EINVAL;
-	}
-}
-
-static int sai_get_hw_params(struct dai *dai,
-			     struct sof_ipc_stream_params *params,
-			     int dir)
-{
-	struct sai_pdata *sai = dai_get_drvdata(dai);
-
-	params->rate = sai->params.fsync_rate;
-	params->channels = sai->params.tdm_slots;
-	params->buffer_fmt = SOF_IPC_BUFFER_INTERLEAVED;
-	/* frame_fmt always S32_LE because that is the native width of the fifo registers */
-	params->frame_fmt = SOF_IPC_FRAME_S32_LE;
-
-	return 0;
-}
-
-const struct dai_driver sai_driver = {
-	.type = SOF_DAI_IMX_SAI,
-	.uid = SOF_UUID(sai_uuid),
-#if !CONFIG_ZEPHYR_LOG
-	.tctx = &sai_tr,
-#endif
-	.dma_dev = SOF_DMA_DEV_SAI,
-	.ops = {
-		.trigger		= sai_trigger,
-		.set_config		= sai_set_config,
-		.probe			= sai_probe,
-		.remove			= sai_remove,
-		.get_handshake		= sai_get_handshake,
-		.get_fifo		= sai_get_fifo,
-		.get_fifo_depth		= sai_get_fifo_depth,
-		.get_hw_params		= sai_get_hw_params,
-	},
-};
diff --git a/src/drivers/imx/sdma.c b/src/drivers/imx/sdma.c
deleted file mode 100644
index 5a0af339974a..000000000000
--- a/src/drivers/imx/sdma.c
+++ /dev/null
@@ -1,1016 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-//
-// Copyright 2020 NXP
-//
-// Author: Paul Olaru <paul.olaru@nxp.com>
-
-#include <sof/audio/component.h>
-#include <sof/drivers/sdma.h>
-#include <rtos/timer.h>
-#include <rtos/alloc.h>
-#include <sof/lib/dma.h>
-#include <sof/lib/io.h>
-#include <sof/lib/notifier.h>
-#include <sof/lib/uuid.h>
-#include <rtos/wait.h>
-#include <sof/platform.h>
-#include <errno.h>
-#include <stddef.h>
-#include <stdint.h>
-
-LOG_MODULE_REGISTER(sdma, CONFIG_SOF_LOG_LEVEL);
-
-SOF_DEFINE_REG_UUID(sdma);
-
-/* unused with Zephyr, generates no output */
-DECLARE_TR_CTX(sdma_tr, SOF_UUID(sdma_uuid), LOG_LEVEL_INFO);
-
-#define SDMA_BUFFER_PERIOD_COUNT 2
-
-struct sdma_bd {
-	/* SDMA BD (buffer descriptor) configuration */
-	uint32_t config;
-
-	/* Buffer addresses, typically source and destination in some
-	 * order, dependent on script
-	 */
-	uint32_t buf_addr;
-	uint32_t buf_xaddr;
-} __packed;
-
-/* SDMA core context */
-struct sdma_context {
-	uint32_t pc;
-	uint32_t spc;
-	uint32_t g_reg[8];
-	uint32_t dma_xfer_regs[14];
-	uint32_t scratch[8];
-} __packed;
-
-/* SDMA channel control block */
-struct sdma_ccb {
-	uint32_t current_bd_paddr;
-	uint32_t base_bd_paddr;
-	uint32_t status;
-	uint32_t reserved; /* No channel descriptor implemented */
-};
-
-/* This structure includes all SDMA related channel data */
-struct sdma_chan {
-	/* Statically allocate BDs; we can change if we ever need dynamic
-	 * allocation
-	 */
-	struct sdma_bd desc[SDMA_MAX_BDS];
-	int desc_count;
-	struct sdma_context *ctx;
-	struct sdma_ccb *ccb;
-	int hw_event;
-	int next_bd;
-	int sdma_chan_type;
-	int fifo_paddr;
-
-	unsigned int watermark_level;
-	unsigned int sw_done_sel; /* software done selector */
-};
-
-/* Private data for the whole controller */
-struct sdma_pdata {
-	/* Statically allocate channel private data and contexts array.
-	 * CCBs must be allocated as array anyway.
-	 */
-	struct sdma_chan *chan_pdata;
-	struct sdma_context *contexts;
-	struct sdma_ccb *ccb_array;
-};
-
-static void sdma_set_overrides(struct dma_chan_data *channel,
-			       bool event_override, bool host_override)
-{
-	tr_dbg(&sdma_tr, "event %d, host %d", event_override, host_override);
-	dma_reg_update_bits(channel->dma, SDMA_EVTOVR, BIT(channel->index),
-			    event_override ? BIT(channel->index) : 0);
-	dma_reg_update_bits(channel->dma, SDMA_HOSTOVR, BIT(channel->index),
-			    host_override ? BIT(channel->index) : 0);
-}
-
-static void sdma_enable_channel(struct dma *dma, int channel)
-{
-	dma_reg_write(dma, SDMA_HSTART, BIT(channel));
-}
-
-static void sdma_disable_channel(struct dma *dma, int channel)
-{
-	dma_reg_write(dma, SDMA_STOP_STAT, BIT(channel));
-}
-
-static int sdma_run_c0(struct dma *dma, uint8_t cmd, uint32_t buf_addr,
-		       uint16_t sdma_addr, uint16_t count)
-{
-	struct dma_chan_data *c0 = dma->chan;
-	struct sdma_chan *c0data = dma_chan_get_data(c0);
-	int ret;
-
-	tr_dbg(&sdma_tr, "cmd %d buf_addr 0x%08x sdma_addr 0x%04x count %d",
-	       cmd, buf_addr, sdma_addr, count);
-
-	c0data->desc[0].config = SDMA_BD_CMD(cmd) | SDMA_BD_COUNT(count)
-		| SDMA_BD_WRAP | SDMA_BD_DONE;
-	c0data->desc[0].buf_addr = buf_addr;
-	c0data->desc[0].buf_xaddr = sdma_addr;
-	if (sdma_addr)
-		c0data->desc[0].config |= SDMA_BD_EXTD;
-
-	c0data->ccb->current_bd_paddr = (uint32_t)&c0data->desc[0];
-	c0data->ccb->base_bd_paddr = (uint32_t)&c0data->desc[0];
-
-	/* Writeback descriptors and CCB */
-	dcache_writeback_region(c0data->desc,
-				sizeof(c0data->desc[0]));
-	dcache_writeback_region(c0data->ccb, sizeof(*c0data->ccb));
-
-	/* Set event override to true so we can manually start channel */
-	sdma_set_overrides(c0, true, false);
-
-	sdma_enable_channel(dma, 0);
-
-	/* 1 is BIT(0) for channel 0, the bit will be cleared as the
-	 * channel finishes execution. 1ms is sufficient if everything is fine.
-	 */
-	ret = poll_for_register_delay(dma_base(dma) + SDMA_STOP_STAT,
-				      1, 0, 1000);
-	if (ret >= 0)
-		ret = 0;
-
-	if (ret < 0)
-		tr_err(&sdma_tr, "SDMA channel 0 timed out");
-
-	/* Switch to dynamic context switch mode if needed. This saves power. */
-	if ((dma_reg_read(dma, SDMA_CONFIG) & SDMA_CONFIG_CSM_MSK) ==
-	    SDMA_CONFIG_CSM_STATIC)
-		dma_reg_update_bits(dma, SDMA_CONFIG, SDMA_CONFIG_CSM_MSK,
-				    SDMA_CONFIG_CSM_DYN);
-
-	tr_dbg(&sdma_tr, "done, ret = %d", ret);
-
-	return ret;
-}
-
-static int sdma_register_init(struct dma *dma)
-{
-	int ret;
-	struct sdma_pdata *pdata = dma_get_drvdata(dma);
-	int i;
-
-	tr_dbg(&sdma_tr, "entry");
-	dma_reg_write(dma, SDMA_RESET, 1);
-	/* Wait for 10us */
-	ret = poll_for_register_delay(dma_base(dma) + SDMA_RESET, 1, 0, 1000);
-	if (ret < 0) {
-		tr_err(&sdma_tr, "SDMA reset error, base address %p",
-		       (void *)dma_base(dma));
-		return ret;
-	}
-
-	dma_reg_write(dma, SDMA_MC0PTR, 0);
-
-	/* Ack all interrupts, they're leftover */
-	dma_reg_write(dma, SDMA_INTR, MASK(31, 0));
-
-	/* SDMA requires static context switch for first execution of channel 0
-	 * in the future. Set it to static here, then have it change to dynamic
-	 * after this first execution of channel 0 completes.
-	 *
-	 * Also set ACR bit according to hardware configuration. Each platform
-	 * may have a different configuration.
-	 */
-#if SDMA_CORE_RATIO
-	dma_reg_update_bits(dma, SDMA_CONFIG,
-			    SDMA_CONFIG_CSM_MSK | SDMA_CONFIG_ACR,
-			    SDMA_CONFIG_ACR);
-#else
-	dma_reg_update_bits(dma, SDMA_CONFIG,
-			    SDMA_CONFIG_CSM_MSK | SDMA_CONFIG_ACR, 0);
-#endif
-	/* Set 32-word scratch memory size */
-	dma_reg_update_bits(dma, SDMA_CHN0ADDR, BIT(14), BIT(14));
-
-	/* Reset channel enable map (it doesn't reset with the controller).
-	 * It shall be updated whenever channels need to be activated by
-	 * hardware events.
-	 */
-	for (i = 0; i < SDMA_HWEVENTS_COUNT; i++)
-		dma_reg_write(dma, SDMA_CHNENBL(i), 0);
-
-	for (i = 0; i < dma->plat_data.channels; i++)
-		dma_reg_write(dma, SDMA_CHNPRI(i), 0);
-
-	/* Write ccb_array pointer to SDMA controller */
-	dma_reg_write(dma, SDMA_MC0PTR, (uint32_t)pdata->ccb_array);
-
-	return 0;
-}
-
-static void sdma_init_c0(struct dma *dma)
-{
-	struct dma_chan_data *c0 = &dma->chan[0];
-	struct sdma_pdata *sdma_pdata = dma_get_drvdata(dma);
-	struct sdma_chan *pdata = &sdma_pdata->chan_pdata[0];
-
-	tr_dbg(&sdma_tr, "entry");
-	c0->status = COMP_STATE_READY;
-
-	/* Reset channel 0 private data */
-	memset(pdata, 0, sizeof(*pdata));
-	pdata->ctx = sdma_pdata->contexts;
-	pdata->ccb = sdma_pdata->ccb_array;
-	pdata->hw_event = -1;
-	dma_chan_set_data(c0, pdata);
-
-	dma_reg_write(dma, SDMA_CHNPRI(0), SDMA_MAXPRI);
-}
-
-static int sdma_boot(struct dma *dma)
-{
-	int ret;
-
-	tr_dbg(&sdma_tr, "entry");
-	ret = sdma_register_init(dma);
-	if (ret < 0)
-		return ret;
-
-	sdma_init_c0(dma);
-
-	tr_dbg(&sdma_tr, "done");
-	return 0;
-}
-
-static int sdma_upload_context(struct dma_chan_data *chan)
-{
-	struct sdma_chan *pdata = dma_chan_get_data(chan);
-
-	/* Ensure context is ready for upload */
-	dcache_writeback_region(pdata->ctx, sizeof(*pdata->ctx));
-
-	tr_dbg(&sdma_tr, "for channel %d", chan->index);
-
-	/* Last parameters are unneeded for this command and are ignored;
-	 * set to 0.
-	 */
-	return sdma_run_c0(chan->dma, SDMA_CMD_C0_SET_DM, (uint32_t)pdata->ctx,
-			   SDMA_SRAM_CONTEXTS_BASE +
-				 /* https://trac.cppcheck.net/ticket/10179 */
-				 /* cppcheck-suppress divideSizeof */
-			   chan->index * sizeof(*pdata->ctx) / 4,
-				 /* https://trac.cppcheck.net/ticket/10179 */
-				 /* cppcheck-suppress divideSizeof */
-			   sizeof(*pdata->ctx) / 4);
-}
-
-#if CONFIG_HAVE_SDMA_FIRMWARE
-static int sdma_load_firmware(struct dma *dma, void *buf, int addr, int size)
-{
-	return sdma_run_c0(dma->chan->dma, SDMA_CMD_C0_SET_PM,
-			   (uint32_t)buf, addr, size / 2);
-}
-#endif
-
-/* Below SOF related functions will be placed */
-
-static int sdma_probe(struct dma *dma)
-{
-	int channel;
-	int ret;
-	struct sdma_pdata *pdata;
-
-	if (dma->chan) {
-		tr_err(&sdma_tr, "SDMA: Repeated probe");
-		return -EEXIST;
-	}
-
-	tr_info(&sdma_tr, "SDMA: probe");
-
-	dma->chan = rzalloc(SOF_MEM_FLAG_KERNEL,
-			    dma->plat_data.channels *
-			    sizeof(struct dma_chan_data));
-	if (!dma->chan) {
-		tr_err(&sdma_tr, "SDMA: Probe failure, unable to allocate channel descriptors");
-		return -ENOMEM;
-	}
-
-	pdata = rzalloc(SOF_MEM_FLAG_KERNEL,
-			sizeof(*pdata));
-	if (!pdata) {
-		rfree(dma->chan);
-		dma->chan = NULL;
-		tr_err(&sdma_tr, "SDMA: Probe failure, unable to allocate private data");
-		return -ENOMEM;
-	}
-	dma_set_drvdata(dma, pdata);
-
-	for (channel = 0; channel < dma->plat_data.channels; channel++) {
-		dma->chan[channel].status = COMP_STATE_INIT;
-		dma->chan[channel].index = channel;
-		dma->chan[channel].dma = dma;
-	}
-
-	pdata->chan_pdata = rzalloc(SOF_MEM_FLAG_KERNEL,
-				    dma->plat_data.channels *
-				    sizeof(struct sdma_chan));
-	if (!pdata->chan_pdata) {
-		ret = -ENOMEM;
-		tr_err(&sdma_tr, "SDMA: probe: out of memory");
-		goto err;
-	}
-
-	pdata->contexts = rzalloc(SOF_MEM_FLAG_KERNEL,
-				  dma->plat_data.channels *
-				  sizeof(struct sdma_context));
-	if (!pdata->contexts) {
-		ret = -ENOMEM;
-		tr_err(&sdma_tr, "SDMA: probe: unable to allocate contexts");
-		goto err;
-	}
-
-	pdata->ccb_array = rzalloc(SOF_MEM_FLAG_KERNEL,
-				   dma->plat_data.channels *
-				   sizeof(struct sdma_ccb));
-	if (!pdata->ccb_array) {
-		ret = -ENOMEM;
-		tr_err(&sdma_tr, "SDMA: probe: unable to allocate CCBs");
-		goto err;
-	}
-
-	ret = sdma_boot(dma);
-	if (ret < 0) {
-		tr_err(&sdma_tr, "SDMA: Unable to boot");
-		goto err;
-	}
-
-#if CONFIG_HAVE_SDMA_FIRMWARE
-	ret = sdma_load_firmware(dma, (void *)sdma_code,
-				 RAM_CODE_START_ADDR,
-				 RAM_CODE_SIZE * sizeof(short));
-	if (ret < 0) {
-		tr_err(&sdma_tr, "SDMA: Failed to load firmware");
-		goto err;
-	}
-#endif
-
-	goto out;
-err:
-	if (pdata->chan_pdata)
-		rfree(pdata->chan_pdata);
-	if (pdata->contexts)
-		rfree(pdata->contexts);
-	if (pdata->ccb_array)
-		rfree(pdata->ccb_array);
-	/* Failures of allocation were treated already */
-	rfree(dma_get_drvdata(dma));
-	rfree(dma->chan);
-	dma_set_drvdata(dma, NULL);
-	dma->chan = NULL;
-out:
-	return ret;
-}
-
-static int sdma_remove(struct dma *dma)
-{
-	struct sdma_pdata *pdata = dma_get_drvdata(dma);
-
-	if (!dma->chan) {
-		tr_err(&sdma_tr, "SDMA: Remove called without probe, that's a noop");
-		return 0;
-	}
-
-	tr_dbg(&sdma_tr, "entry");
-
-	/* Prevent all channels except channel 0 from running */
-	dma_reg_write(dma, SDMA_HOSTOVR, 1);
-	dma_reg_write(dma, SDMA_EVTOVR, 0);
-
-	/* Stop all channels except channel 0 */
-	dma_reg_write(dma, SDMA_STOP_STAT, ~1);
-
-	/* Reset SDMAC */
-	dma_reg_write(dma, SDMA_RESET, 1);
-
-	/* Free all memory related to SDMA */
-	rfree(pdata->chan_pdata);
-	rfree(pdata->contexts);
-	rfree(pdata->ccb_array);
-	rfree(dma->chan);
-	dma->chan = NULL;
-
-	return 0;
-}
-
-static struct dma_chan_data *sdma_channel_get(struct dma *dma,
-					      unsigned int chan)
-{
-	struct sdma_pdata *pdata = dma_get_drvdata(dma);
-	struct dma_chan_data *channel;
-	struct sdma_chan *cdata;
-	int i;
-	/* Ignoring channel 0; let's just allocate a free channel */
-
-	tr_dbg(&sdma_tr, "sdma_channel_get");
-	for (i = 1; i < dma->plat_data.channels; i++) {
-		channel = &dma->chan[i];
-		if (channel->status != COMP_STATE_INIT)
-			continue;
-
-		/* Reset channel private data */
-		cdata = &pdata->chan_pdata[i];
-		memset(cdata, 0, sizeof(*cdata));
-		cdata->ctx = pdata->contexts + i;
-		cdata->ccb = pdata->ccb_array + i;
-		cdata->hw_event = -1;
-
-		channel->status = COMP_STATE_READY;
-		channel->index = i;
-		dma_chan_set_data(channel, cdata);
-
-		/* Allow events, allow manual */
-		sdma_set_overrides(channel, false, false);
-		return channel;
-	}
-	tr_err(&sdma_tr, "sdma no channel free");
-	return NULL;
-}
-
-static void sdma_enable_event(struct dma_chan_data *channel, int eventnum)
-{
-	struct sdma_chan *pdata = dma_chan_get_data(channel);
-
-	tr_dbg(&sdma_tr, "channel %d, event %d", channel->index, eventnum);
-
-	if (eventnum < 0 || eventnum >= SDMA_HWEVENTS_COUNT)
-		return; /* No change if request is invalid */
-
-	dma_reg_update_bits(channel->dma, SDMA_CHNENBL(eventnum),
-			    BIT(channel->index), BIT(channel->index));
-
-	if (pdata->sw_done_sel & BIT(31)) {
-		unsigned int done0;
-
-		done0 = SDMA_DONE0_CONFIG_DONE_SEL | ~SDMA_DONE0_CONFIG_DONE_DIS;
-		dma_reg_update_bits(channel->dma, SDMA_DONE0_CONFIG, 0xFF, done0);
-	}
-}
-
-static void sdma_disable_event(struct dma_chan_data *channel, int eventnum)
-{
-	tr_dbg(&sdma_tr, "channel %d, event %d", channel->index, eventnum);
-
-	if (eventnum < 0 || eventnum >= SDMA_HWEVENTS_COUNT)
-		return; /* No change if request is invalid */
-
-	dma_reg_update_bits(channel->dma, SDMA_CHNENBL(eventnum),
-			    BIT(channel->index), 0);
-}
-
-static void sdma_channel_put(struct dma_chan_data *channel)
-{
-	struct sdma_chan *pdata = dma_chan_get_data(channel);
-
-	if (channel->status == COMP_STATE_INIT)
-		return; /* Channel was already free */
-	tr_dbg(&sdma_tr, "channel %d", channel->index);
-
-	dma_interrupt_legacy(channel, DMA_IRQ_CLEAR);
-	sdma_disable_event(channel, pdata->hw_event);
-	sdma_set_overrides(channel, false, false);
-	channel->status = COMP_STATE_INIT;
-}
-
-static int sdma_start(struct dma_chan_data *channel)
-{
-	tr_dbg(&sdma_tr, "channel %d", channel->index);
-
-	if (channel->status != COMP_STATE_PREPARE &&
-	    channel->status != COMP_STATE_PAUSED)
-		return -EINVAL;
-
-	channel->status = COMP_STATE_ACTIVE;
-
-	sdma_enable_channel(channel->dma, channel->index);
-
-	return 0;
-}
-
-static int sdma_stop(struct dma_chan_data *channel)
-{
-	/* do not try to stop multiple times */
-	if (channel->status != COMP_STATE_ACTIVE &&
-	    channel->status != COMP_STATE_PAUSED)
-		return 0;
-
-	channel->status = COMP_STATE_READY;
-
-	tr_dbg(&sdma_tr, "channel %d", channel->index);
-
-	sdma_disable_channel(channel->dma, channel->index);
-
-	return 0;
-}
-
-static int sdma_pause(struct dma_chan_data *channel)
-{
-	struct sdma_chan *pdata = dma_chan_get_data(channel);
-
-	if (channel->status != COMP_STATE_ACTIVE)
-		return -EINVAL;
-
-	channel->status = COMP_STATE_PAUSED;
-
-	/* Manually controlled channels need not be paused. */
-	if (pdata->hw_event != -1)
-		dma_reg_update_bits(channel->dma, SDMA_HOSTOVR,
-				    BIT(channel->index), 0);
-
-	return 0;
-}
-
-static int sdma_release(struct dma_chan_data *channel)
-{
-	if (channel->status != COMP_STATE_PAUSED)
-		return -EINVAL;
-
-	channel->status = COMP_STATE_PREPARE;
-
-	/* No pointer realignment is necessary for release, context points
-	 * correctly to beginning of the following BD.
-	 */
-	return 0;
-}
-
-static int sdma_copy(struct dma_chan_data *channel, int bytes, uint32_t flags)
-{
-	struct sdma_chan *pdata = dma_chan_get_data(channel);
-	struct dma_cb_data next = {
-		.channel = channel,
-		.elem.size = bytes,
-	};
-	int idx;
-
-	tr_dbg(&sdma_tr, "entry");
-
-	idx = (pdata->next_bd + 1) % 2;
-	pdata->next_bd = idx;
-
-	/* Work around the fact that we cannot allocate uncached memory
-	 * on all platforms supporting SDMA.
-	 */
-	dcache_invalidate_region(&pdata->desc[idx].config,
-				 sizeof(pdata->desc[idx].config));
-	pdata->desc[idx].config |= SDMA_BD_DONE;
-	dcache_writeback_region(&pdata->desc[idx].config,
-				sizeof(pdata->desc[idx].config));
-
-	notifier_event(channel, NOTIFIER_ID_DMA_COPY,
-		       NOTIFIER_TARGET_CORE_LOCAL, &next, sizeof(next));
-
-	sdma_enable_channel(channel->dma, channel->index);
-
-	return 0;
-}
-
-static int sdma_status(struct dma_chan_data *channel,
-		       struct dma_chan_status *status, uint8_t direction)
-{
-	struct sdma_chan *pdata = dma_chan_get_data(channel);
-	struct sdma_bd *bd;
-
-	tr_dbg(&sdma_tr, "entry");
-	if (channel->status == COMP_STATE_INIT)
-		return -EINVAL;
-	status->state = channel->status;
-	status->flags = 0;
-	status->w_pos = 0;
-	status->r_pos = 0;
-	status->timestamp = sof_cycle_get_64();
-
-	bd = (struct sdma_bd *)pdata->ccb->current_bd_paddr;
-
-	switch (pdata->sdma_chan_type) {
-	case SDMA_CHAN_TYPE_AP2AP:
-		/* We won't ever enable MMU will we? */
-		status->r_pos = bd->buf_addr;
-		status->w_pos = bd->buf_xaddr;
-		break;
-	case SDMA_CHAN_TYPE_AP2MCU:
-	case SDMA_CHAN_TYPE_MCU2SHP:
-	case SDMA_CHAN_TYPE_SAI2MCU:
-		status->r_pos = bd->buf_addr;
-		status->w_pos = pdata->fifo_paddr;
-		/* We cannot see the target address */
-		break;
-	case SDMA_CHAN_TYPE_MCU2AP:
-	case SDMA_CHAN_TYPE_SHP2MCU:
-		status->w_pos = bd->buf_addr;
-		status->r_pos = pdata->fifo_paddr;
-		break;
-	}
-	return 0;
-}
-
-static void sdma_set_watermarklevel(struct dma_chan_data *chan)
-{
-	struct sdma_chan *pdata = dma_chan_get_data(chan);
-
-	/* TODO: retrieve this information from DAI */
-	unsigned int n_fifos = 4; /* number of HW fifos used */
-	unsigned int words_per_fifo = 1; /* number of audio channels per frame */
-
-	/* sw_done_sel mimics software done configuration from Linux
-	 * see Documentation/devicetree/bindings/fsl-imx-sdma.txt
-	 */
-	unsigned int sw_done_sel = 0;
-
-	/* sw_done_sel configuration
-	 * - bit31:  sw_done
-	 * - bit15:8 selector
-	 * - bit7-0  priority
-	 */
-	sw_done_sel |= BIT(31);
-
-	/* watermark level:
-	 * bit0~11: wartermark level(wml*fifo_number)
-	 * bit15~12: to do-fifo number
-	 * bit16~19: fifo offset
-	 * bit27~24: sw done selector
-	 * bit28~31: numbers of audio channels in one frame, 0: 1 channel,1: 2 channels
-	 * bit23: sw done enable
-	 */
-
-	pdata->watermark_level |= SDMA_WATERMARK_LEVEL_SW_DONE |
-		 (sw_done_sel & 0xff) << SDMA_WATERMARK_LEVEL_SW_DONE_SEL_OFF;
-
-	pdata->watermark_level |=
-		SDMA_WATERMARK_LEVEL_N_FIFOS(n_fifos);
-
-	pdata->watermark_level |=
-		SDMA_WATERMARK_LEVEL_WORDS_PER_FIFO(words_per_fifo - 1);
-
-	pdata->sw_done_sel = sw_done_sel;
-}
-
-static int sdma_read_config(struct dma_chan_data *channel,
-			    struct dma_sg_config *config)
-{
-	int i;
-	struct sdma_chan *pdata = dma_chan_get_data(channel);
-	struct dai_data *dd = channel->dev_data;
-	uint32_t dma_dev = dd->dai->drv->dma_dev;
-
-	switch (config->direction) {
-	case SOF_DMA_DIR_MEM_TO_DEV:
-		pdata->hw_event = config->dest_dev;
-		pdata->sdma_chan_type = SDMA_CHAN_TYPE_MCU2SHP;
-		pdata->fifo_paddr = config->elem_array.elems[0].dest;
-		break;
-	case SOF_DMA_DIR_DEV_TO_MEM:
-		pdata->hw_event = config->src_dev;
-		if (dma_dev == SOF_DMA_DEV_MICFIL)
-			pdata->sdma_chan_type = SDMA_CHAN_TYPE_SAI2MCU;
-		else
-			pdata->sdma_chan_type = SDMA_CHAN_TYPE_SHP2MCU;
-		pdata->fifo_paddr = config->elem_array.elems[0].src;
-		break;
-	case SOF_DMA_DIR_MEM_TO_MEM:
-		pdata->sdma_chan_type = SDMA_CHAN_TYPE_AP2AP;
-		/* Fallthrough, TODO: implement to support m2m */
-	default:
-		tr_err(&sdma_tr, "sdma_set_config: Unsupported direction %d",
-		       config->direction);
-		return -EINVAL;
-	}
-
-	for (i = 0; i < config->elem_array.count; i++) {
-		if (config->direction == SOF_DMA_DIR_MEM_TO_DEV &&
-		    pdata->fifo_paddr != config->elem_array.elems[i].dest) {
-			tr_err(&sdma_tr, "FIFO changes address!");
-			return -EINVAL;
-		}
-
-		if (config->direction == SOF_DMA_DIR_DEV_TO_MEM &&
-		    pdata->fifo_paddr != config->elem_array.elems[i].src) {
-			tr_err(&sdma_tr, "FIFO changes address!");
-			return -EINVAL;
-		}
-
-		if (config->elem_array.elems[i].size > SDMA_BD_MAX_COUNT) {
-			/* Future improvement: Create multiple BDs so as to
-			 * support this situation
-			 */
-			tr_err(&sdma_tr, "sdma_set_config: elem transfers too much: %d bytes",
-			       config->elem_array.elems[i].size);
-			return -EINVAL;
-		}
-	}
-
-	return 0;
-}
-
-/* Data to store in the descriptors:
- * 1) Each descriptor corresponds to each of the
- *    config->elem_array elems; if we have more than
- *    MAX_DESCRIPTORS we bail outright. For the future, we could
- *    allocate the per-channel descriptors dynamically.
- * 2) For each of them, store the host side (SDRAM side) as
- *    buf_addr and keep the FIFO address as a separate variable.
- *    Complain if this address changes between descriptors as we
- *    do not support this for now.
- * 3) Enable interrupts, set up transfer width, length of elem,
- *    wrap bit on the last descriptor, host side address, and
- *    finally the DONE bit so the SDMA can use the descriptors.
- * 4) The FIFO address will be stored in the context.
- * 5) Actually upload context now as we are inside DAI prepare.
- *    We have no other opportunity in the future.
- */
-static int sdma_prep_desc(struct dma_chan_data *channel,
-			  struct dma_sg_config *config)
-{
-	int i;
-	int width;
-	int watermark;
-	uint32_t sdma_script_addr;
-	struct sdma_chan *pdata = dma_chan_get_data(channel);
-	struct sdma_bd *bd;
-
-	/* Validate requested configuration */
-	if (config->elem_array.count > SDMA_MAX_BDS) {
-		tr_err(&sdma_tr, "sdma_set_config: Unable to handle %d descriptors",
-		       config->elem_array.count);
-		return -EINVAL;
-	}
-	if (config->elem_array.count <= 0) {
-		tr_err(&sdma_tr, "sdma_set_config: Invalid descriptor count: %d",
-		       config->elem_array.count);
-		return -EINVAL;
-	}
-
-	pdata->next_bd = 0;
-
-	/* Silence "may be used uninitialized" warnings with gcc10 -O1
-	 * and maybe other compilers/levels that don't know that
-	 * config->elem_array.count > 0
-	 */
-	bd = &pdata->desc[0];
-	width = 0;
-
-	for (i = 0; i < config->elem_array.count; i++) {
-		bd = &pdata->desc[i];
-		/* For MEM2DEV and DEV2MEM, buf_addr holds the RAM address and
-		 * the FIFO address is stored in one of the general registers of
-		 * the SDMA core.
-		 * For MEM2MEM the source is stored in buf_addr and destination
-		 * is in buf_xaddr.
-		 */
-		switch (config->direction) {
-		case SOF_DMA_DIR_MEM_TO_DEV:
-			bd->buf_addr = config->elem_array.elems[i].src;
-			width = config->src_width;
-			break;
-		case SOF_DMA_DIR_DEV_TO_MEM:
-			bd->buf_addr = config->elem_array.elems[i].dest;
-			width = config->dest_width;
-			break;
-		case SOF_DMA_DIR_MEM_TO_MEM:
-			bd->buf_addr = config->elem_array.elems[i].src;
-			bd->buf_xaddr = config->elem_array.elems[i].dest;
-			width = config->dest_width;
-			break;
-		default:
-			return -EINVAL;
-		}
-
-		bd->config = SDMA_BD_COUNT(config->elem_array.elems[i].size) |
-			SDMA_BD_CMD(SDMA_CMD_XFER_SIZE(width));
-		if (!config->irq_disabled)
-			bd->config |= SDMA_BD_INT;
-
-		bd->config |= SDMA_BD_CONT;
-		if (pdata->next_bd == i)
-			bd->config |= SDMA_BD_DONE;
-	}
-
-	/* Configure last BD to account for cyclic transfers */
-	if (config->cyclic)
-		bd->config |= SDMA_BD_WRAP;
-	bd->config &= ~SDMA_BD_CONT;
-
-	/* CCB must point to buffer descriptors array */
-	memset(pdata->ccb, 0, sizeof(*pdata->ccb));
-	pdata->ccb->base_bd_paddr = (uint32_t)pdata->desc;
-	pdata->ccb->current_bd_paddr = (uint32_t)pdata->desc;
-	pdata->desc_count = config->elem_array.count;
-
-	/* Context must be configured, dependent on transfer direction */
-
-	switch (pdata->sdma_chan_type) {
-	case SDMA_CHAN_TYPE_AP2AP:
-		sdma_script_addr = SDMA_SCRIPT_AP2AP_OFF;
-		break;
-	case SDMA_CHAN_TYPE_MCU2SHP:
-		sdma_script_addr = SDMA_SCRIPT_MCU2SHP_OFF;
-		break;
-	case SDMA_CHAN_TYPE_SHP2MCU:
-		sdma_script_addr = SDMA_SCRIPT_SHP2MCU_OFF;
-		break;
-	case SDMA_CHAN_TYPE_SAI2MCU:
-		sdma_script_addr = SDMA_SCRIPT_SAI2MCU_OFF;
-		break;
-	default:
-		/* This case doesn't happen; we need to assign the other cases
-		 * for AP2MCU and MCU2AP
-		 */
-		tr_err(&sdma_tr, "Unexpected SDMA error");
-		return -EINVAL;
-	}
-
-	watermark = (config->burst_elems * width) / 8;
-
-	if (pdata->sdma_chan_type == SDMA_CHAN_TYPE_SAI2MCU) {
-		sdma_set_watermarklevel(channel);
-		watermark |= pdata->watermark_level;
-	} else {
-		watermark = (config->burst_elems * width) / 8;
-	}
-
-	memset(pdata->ctx, 0, sizeof(*pdata->ctx));
-	pdata->ctx->pc = sdma_script_addr;
-
-	if (pdata->sdma_chan_type == SDMA_CHAN_TYPE_AP2AP) {
-		/* Base of RAM, TODO must be moved to a define */
-		pdata->ctx->g_reg[7] = 0x40000000;
-	} else {
-		if (pdata->hw_event != -1) {
-			if (pdata->hw_event >= 32)
-				pdata->ctx->g_reg[0] |= BIT(pdata->hw_event - 32);
-			else
-				pdata->ctx->g_reg[1] |= BIT(pdata->hw_event);
-		}
-		pdata->ctx->g_reg[6] = pdata->fifo_paddr;
-		pdata->ctx->g_reg[7] = watermark;
-	}
-
-	dcache_writeback_region(pdata->desc, sizeof(pdata->desc));
-	dcache_writeback_region(pdata->ccb, sizeof(*pdata->ccb));
-	dcache_writeback_region(pdata->ctx,  sizeof(*pdata->ctx));
-
-	return 0;
-}
-
-static int sdma_set_config(struct dma_chan_data *channel,
-			   struct dma_sg_config *config)
-{
-	struct sdma_chan *pdata = dma_chan_get_data(channel);
-	int ret;
-
-	tr_dbg(&sdma_tr, "channel %d", channel->index);
-
-	ret = sdma_read_config(channel, config);
-	if (ret < 0)
-		return ret;
-
-	channel->is_scheduling_source = config->is_scheduling_source;
-	channel->direction = config->direction;
-
-	ret = sdma_prep_desc(channel, config);
-	if (ret < 0)
-		return ret;
-
-	/* allow events + allow manual start */
-	sdma_set_overrides(channel, false, false);
-
-	/* Upload context */
-	ret = sdma_upload_context(channel);
-	if (ret < 0) {
-		tr_err(&sdma_tr, "Unable to upload context, bailing");
-		return ret;
-	}
-
-	tr_dbg(&sdma_tr, "SDMA context uploaded");
-	/* Context uploaded, we can set up events now */
-	sdma_enable_event(channel, pdata->hw_event);
-
-	/* Finally set channel priority */
-	dma_reg_write(channel->dma, SDMA_CHNPRI(channel->index), SDMA_DEFPRI);
-
-	channel->status = COMP_STATE_PREPARE;
-
-	return 0;
-}
-
-static int sdma_interrupt(struct dma_chan_data *channel, enum dma_irq_cmd cmd)
-{
-	if (!channel->index)
-		return 0;
-
-	switch (cmd) {
-	case DMA_IRQ_STATUS_GET:
-		/* Any nonzero value means interrupt is active */
-		return dma_reg_read(channel->dma, SDMA_INTR) &
-			BIT(channel->index);
-	case DMA_IRQ_CLEAR:
-		dma_reg_write(channel->dma, SDMA_INTR, BIT(channel->index));
-		return 0;
-	case DMA_IRQ_MASK:
-	case DMA_IRQ_UNMASK:
-		/* We cannot control interrupts except by resetting channel to
-		 * have it reread the buffer descriptors. That cannot be done
-		 * in the context where this function is called. Silently ignore
-		 * requests to mask/unmask per-channel interrupts.
-		 */
-		return 0;
-	default:
-		tr_err(&sdma_tr, "unknown cmd %d", cmd);
-		return -EINVAL;
-	}
-}
-
-static int sdma_get_attribute(struct dma *dma, uint32_t type, uint32_t *value)
-{
-	switch (type) {
-	case DMA_ATTR_BUFFER_ALIGNMENT:
-	case DMA_ATTR_COPY_ALIGNMENT:
-		/* Use a conservative value, because some scripts
-		 * require an alignment of 4 while others can read
-		 * unaligned data. Account for those which require
-		 * aligned data.
-		 */
-		*value = 4;
-		break;
-	case DMA_ATTR_BUFFER_ADDRESS_ALIGNMENT:
-		*value = PLATFORM_DCACHE_ALIGN;
-		break;
-	case DMA_ATTR_BUFFER_PERIOD_COUNT:
-		*value = SDMA_BUFFER_PERIOD_COUNT;
-		break;
-	default:
-		return -ENOENT; /* Attribute not found */
-	}
-
-	return 0;
-}
-
-static int sdma_get_data_size(struct dma_chan_data *channel, uint32_t *avail,
-			      uint32_t *free)
-{
-	/* Check buffer descriptors, those with "DONE" = 0 are for the
-	 * host, "DONE" = 1 are for SDMA. The host side are either
-	 * available or free.
-	 */
-	struct sdma_chan *pdata = dma_chan_get_data(channel);
-	uint32_t result_data = 0;
-	int i;
-
-	tr_dbg(&sdma_tr, "channel %d", channel->index);
-	if (channel->index == 0) {
-		/* Channel 0 shouldn't have this called anyway */
-		tr_err(&sdma_tr, "Please do not call get_data_size on SDMA channel 0!");
-		*avail = *free = 0;
-		return -EINVAL;
-	}
-
-	dcache_invalidate_region(pdata->desc, sizeof(pdata->desc[0]) * SDMA_MAX_BDS);
-
-	for (i = 0; i < pdata->desc_count && i < SDMA_MAX_BDS; i++) {
-		if (pdata->desc[i].config & SDMA_BD_DONE)
-			continue; /* These belong to SDMA controller */
-		result_data += pdata->desc[i].config &
-			SDMA_BD_COUNT_MASK;
-	}
-
-	*avail = *free = 0;
-	switch (channel->direction) {
-	case SOF_DMA_DIR_MEM_TO_DEV:
-		*free = result_data;
-		break;
-	case SOF_DMA_DIR_DEV_TO_MEM:
-		*avail = result_data;
-		break;
-	default:
-		tr_err(&sdma_tr, "channel invalid direction");
-		return -EINVAL;
-	}
-	return 0;
-}
-
-const struct dma_ops sdma_ops = {
-	.channel_get	= sdma_channel_get,
-	.channel_put	= sdma_channel_put,
-	.start		= sdma_start,
-	.stop		= sdma_stop,
-	.pause		= sdma_pause,
-	.release	= sdma_release,
-	.copy		= sdma_copy,
-	.status		= sdma_status,
-	.set_config	= sdma_set_config,
-	.probe		= sdma_probe,
-	.remove		= sdma_remove,
-	.interrupt	= sdma_interrupt,
-	.get_attribute	= sdma_get_attribute,
-	.get_data_size	= sdma_get_data_size,
-};
diff --git a/src/drivers/imx/timer.c b/src/drivers/imx/timer.c
deleted file mode 100644
index fd396af493ea..000000000000
--- a/src/drivers/imx/timer.c
+++ /dev/null
@@ -1,112 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-//
-// Copyright 2019 NXP
-//
-// Author: Daniel Baluta <daniel.baluta@nxp.com>
-
-#include <sof/audio/component_ext.h>
-#include <rtos/interrupt.h>
-#include <rtos/timer.h>
-#include <sof/lib/memory.h>
-#include <sof/platform.h>
-#include <ipc/stream.h>
-#include <errno.h>
-#include <stdint.h>
-
-void platform_timer_start(struct timer *timer)
-{
-	//nothing to do on IMX for cpu timer
-}
-
-void platform_timer_stop(struct timer *timer)
-{
-	arch_timer_disable(timer);
-}
-
-int64_t platform_timer_set(struct timer *timer, uint64_t ticks)
-{
-	return arch_timer_set(timer, ticks);
-}
-
-void platform_timer_clear(struct timer *timer)
-{
-	arch_timer_clear(timer);
-}
-
-uint64_t platform_timer_get(struct timer *timer)
-{
-	return arch_timer_get_system(timer);
-}
-
-/* IRQs off in arch_timer_get_system() */
-uint64_t platform_timer_get_atomic(struct timer *timer)
-{
-	return arch_timer_get_system(timer);
-}
-
-/* get timestamp for host stream DMA position */
-void platform_host_timestamp(struct comp_dev *host,
-			     struct sof_ipc_stream_posn *posn)
-{
-	int err;
-
-	/* get host position */
-	err = comp_position(host, posn);
-	if (err == 0)
-		posn->flags |= SOF_TIME_HOST_VALID | SOF_TIME_HOST_64;
-}
-
-/* get timestamp for DAI stream DMA position */
-void platform_dai_timestamp(struct comp_dev *dai,
-			    struct sof_ipc_stream_posn *posn)
-{
-	int err;
-
-	/* get DAI position */
-	err = comp_position(dai, posn);
-	if (err == 0)
-		posn->flags |= SOF_TIME_DAI_VALID;
-
-	/* get SSP wallclock - DAI sets this to stream start value */
-	posn->wallclock = timer_get_system(timer_get()) - posn->wallclock;
-	posn->flags |= SOF_TIME_WALL_VALID | SOF_TIME_WALL_64;
-}
-
-/* get current wallclock for componnent */
-void platform_dai_wallclock(struct comp_dev *dai, uint64_t *wallclock)
-{
-	/* only 1 wallclock on imx8 */
-	*wallclock = timer_get_system(timer_get());
-}
-
-int timer_register(struct timer *timer, void(*handler)(void *arg), void *arg)
-{
-	int ret;
-
-	switch (timer->id) {
-	case TIMER0:
-	case TIMER1:
-		ret = arch_timer_register(timer, handler, arg);
-		break;
-	default:
-		ret = -EINVAL;
-		break;
-	}
-
-	return ret;
-}
-
-void timer_unregister(struct timer *timer, void *arg)
-{
-	interrupt_unregister(timer->irq, arg);
-}
-
-void timer_enable(struct timer *timer, void *arg, int core)
-{
-	interrupt_enable(timer->irq, arg);
-}
-
-void timer_disable(struct timer *timer, void *arg, int core)
-{
-	interrupt_disable(timer->irq, arg);
-}
diff --git a/src/drivers/mediatek/CMakeLists.txt b/src/drivers/mediatek/CMakeLists.txt
deleted file mode 100644
index 4362b62ec7cb..000000000000
--- a/src/drivers/mediatek/CMakeLists.txt
+++ /dev/null
@@ -1,15 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-
-add_subdirectory(afe)
-if(CONFIG_MT8195)
-	add_subdirectory(mt8195)
-endif()
-if(CONFIG_MT8186 OR CONFIG_MT8188)
-        add_subdirectory(mt818x)
-endif()
-if(CONFIG_MT8196)
-	add_subdirectory(mt8196)
-endif()
-if(CONFIG_MT8365)
-	add_subdirectory(mt8365)
-endif()
diff --git a/src/drivers/mediatek/Kconfig b/src/drivers/mediatek/Kconfig
deleted file mode 100644
index 22d27a4bbbb6..000000000000
--- a/src/drivers/mediatek/Kconfig
+++ /dev/null
@@ -1,19 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-
-config TEST_SGEN
-	bool
-	default n
-	help
-	  Note: TEST_SGEN for test only
-	  Define this TEST_SGEN to enable sine tone generator,
-	  then output data to audio memory interface(memif)
-
-config MEDIATEK_DRAM_IMAGE
-	bool "Change image location to DRAM"
-	default n
-	help
-	  Select this to generate the SOF image on DRAM for MediaTek platform.
-	  If the image size cannot fit in the DSP SRAM, enable this option will
-	  move all sections except vector from SRAM to DRAM.
-
-	  If unsure, select "n".
diff --git a/src/drivers/mediatek/afe/CMakeLists.txt b/src/drivers/mediatek/afe/CMakeLists.txt
deleted file mode 100644
index 228a6555d2c8..000000000000
--- a/src/drivers/mediatek/afe/CMakeLists.txt
+++ /dev/null
@@ -1,18 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-
-add_local_sources(sof afe-memif.c afe-dai.c afe-drv.c)
-if(CONFIG_MT8186)
-        add_subdirectory(mt8186)
-endif()
-if(CONFIG_MT8188)
-        add_subdirectory(mt8188)
-endif()
-if(CONFIG_MT8195)
-        add_subdirectory(mt8195)
-endif()
-if(CONFIG_MT8196)
-        add_subdirectory(mt8196)
-endif()
-if(CONFIG_MT8365)
-        add_subdirectory(mt8365)
-endif()
diff --git a/src/drivers/mediatek/afe/afe-memif.c b/src/drivers/mediatek/afe/afe-memif.c
index 8726f5d00d3c..48e55c733920 100644
--- a/src/drivers/mediatek/afe/afe-memif.c
+++ b/src/drivers/mediatek/afe/afe-memif.c
@@ -13,7 +13,6 @@
 #include <sof/drivers/afe-drv.h>
 #include <sof/drivers/afe-dai.h>
 #include <sof/drivers/afe-memif.h>
-#include <sof/drivers/afe-sgen.h>
 #include <rtos/timer.h>
 #include <rtos/alloc.h>
 #include <sof/lib/dma.h>
@@ -110,9 +109,6 @@ static int memif_start(struct dma_chan_data *channel)
 		return -EINVAL;
 
 	channel->status = COMP_STATE_ACTIVE;
-#if CONFIG_TEST_SGEN
-	afe_sinegen_enable();
-#endif
 	/* Do the HW start of the DMA */
 	return afe_memif_set_enable(memif->afe, memif->memif_id, 1);
 }
@@ -132,9 +128,6 @@ static int memif_release(struct dma_chan_data *channel)
 	ret = afe_memif_set_enable(memif->afe, memif->memif_id, 0);
 	if (ret < 0)
 		return ret;
-#if CONFIG_TEST_SGEN
-	afe_sinegen_disable();
-#endif
 
 	return 0;
 }
diff --git a/src/drivers/mediatek/afe/mt8186/CMakeLists.txt b/src/drivers/mediatek/afe/mt8186/CMakeLists.txt
deleted file mode 100644
index 3f0653684edf..000000000000
--- a/src/drivers/mediatek/afe/mt8186/CMakeLists.txt
+++ /dev/null
@@ -1,5 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-
-if(CONFIG_TEST_SGEN)
-add_local_sources(sof afe-sgen.c)
-endif()
diff --git a/src/drivers/mediatek/afe/mt8186/afe-sgen.c b/src/drivers/mediatek/afe/mt8186/afe-sgen.c
deleted file mode 100644
index de87bccc2fff..000000000000
--- a/src/drivers/mediatek/afe/mt8186/afe-sgen.c
+++ /dev/null
@@ -1,250 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-/*
- * Copyright(c) 2023 MediaTek. All rights reserved.
- *
- * Author: Trevor Wu <trevor.wu@mediatek.com>
- */
-#include <stdint.h>
-
-#include <sof/drivers/afe-sgen.h>
-#include <sof/lib/io.h>
-#include <sof/lib/uuid.h>
-#include <sof/trace/trace.h>
-
-#include <mt8186-afe-regs.h>
-#include <mt8186-afe-common.h>
-
-SOF_DEFINE_REG_UUID(sgen_mt8186);
-
-/* unused with Zephyr, generates no output */
-DECLARE_TR_CTX(sgen_tr, SOF_UUID(sgen_mt8186_uuid), LOG_LEVEL_INFO);
-
-/*
- * Note: TEST_SGEN for test only
- * Define this TEST_SGEN to enable sine tone generator
- * then output data to audio memory interface(memif),
- * you can set TEST_SGEN_ID to choose output to which memif.
- * e.g. set TEST_SGEN as '1' and TEST_SGEN_ID as "MT8186_MEMIF_DL2",
- * the data source of DL2 will from sine generator.
- */
-#define TEST_SGEN_ID MT8186_MEMIF_UL1
-#define AUDIO_TML_PD_MASK 1
-#define AUDIO_TML_PD_SHIFT 27
-
-#define AFE_SGEN_FREQ_DIV_CH1_MASK 0x1f
-#define AFE_SGEN_FREQ_DIV_CH1_SHIFT 0
-#define AFE_SGEN_FREQ_DIV_CH2_MASK 0x1f
-#define AFE_SGEN_FREQ_DIV_CH2_SHIFT 12
-#define AFE_SGEN_AMP_DIV_CH1_MASK 0x7
-#define AFE_SGEN_AMP_DIV_CH1_SHIFT 5
-#define AFE_SGEN_AMP_DIV_CH2_MASK 0x7
-#define AFE_SGEN_AMP_DIV_CH2_SHIFT 17
-#define AFE_SGEN_MUTE_CH1_MASK 0x1
-#define AFE_SGEN_MUTE_CH1_SHIFT 24
-#define AFE_SGEN_MUTE_CH2_MASK 0x1
-#define AFE_SGEN_MUTE_CH2_SHIFT 25
-#define AFE_SGEN_ENABLE_MASK 0x1
-#define AFE_SGEN_ENABLE_SHIFT 26
-
-#define AFE_SINEGEN_CON1_TIMING_CH1_MASK 0xf
-#define AFE_SINEGEN_CON1_TIMING_CH1_SHIFT 8
-#define AFE_SINEGEN_CON1_TIMING_CH2_MASK 0xf
-#define AFE_SINEGEN_CON1_TIMING_CH2_SHIFT 20
-
-#define AFE_SINEGEN_LB_MODE_MSK 0xff
-#define AFE_SINEGEN_LB_MODE_SHIFT 0
-
-enum {
-	MT8186_SGEN_UL1 = 0x96,
-	MT8186_SGEN_UL2 = 0x86,
-	MT8186_SGEN_DL1 = 0x6,
-	MT8186_SGEN_DL2 = 0x8,
-};
-
-/*sgen freq div*/
-enum {
-	SGEN_FREQ_64D1 = 1,
-	SGEN_FREQ_64D2 = 2,
-	SGEN_FREQ_64D3 = 3,
-	SGEN_FREQ_64D4 = 4,
-	SGEN_FREQ_64D5 = 5,
-	SGEN_FREQ_64D6 = 6,
-	SGEN_FREQ_64D7 = 7,
-	SGEN_FREQ_64D8 = 8,
-};
-
-/*sgen amp div*/
-enum {
-	SGEN_AMP_D128 = 0,
-	SGEN_AMP_D64 = 1,
-	SGEN_AMP_D32 = 2,
-	SGEN_AMP_D16 = 3,
-	SGEN_AMP_D8 = 4,
-	SGEN_AMP_D4 = 5,
-	SGEN_AMP_D2 = 6,
-	SGEN_AMP_D1 = 7,
-};
-
-enum {
-	SGEN_CH_TIMING_8K = 0,
-	SGEN_CH_TIMING_11P025K = 1,
-	SGEN_CH_TIMING_12K = 2,
-	SGEN_CH_TIMING_384K = 3,
-	SGEN_CH_TIMING_16K = 4,
-	SGEN_CH_TIMING_22P05K = 5,
-	SGEN_CH_TIMING_24K = 6,
-	SGEN_CH_TIMING_352P8K = 7,
-	SGEN_CH_TIMING_32K = 8,
-	SGEN_CH_TIMING_44P1K = 9,
-	SGEN_CH_TIMING_48K = 10,
-	SGEN_CH_TIMING_88P2K = 11,
-	SGEN_CH_TIMING_96K = 12,
-	SGEN_CH_TIMING_176P4K = 13,
-	SGEN_CH_TIMING_192K = 14,
-};
-
-static uint32_t mt8186_sinegen_timing(uint32_t rate)
-{
-	uint32_t sinegen_timing;
-
-	switch (rate) {
-	case 8000:
-		sinegen_timing = SGEN_CH_TIMING_8K;
-		break;
-	case 12000:
-		sinegen_timing = SGEN_CH_TIMING_12K;
-		break;
-	case 16000:
-		sinegen_timing = SGEN_CH_TIMING_16K;
-		break;
-	case 24000:
-		sinegen_timing = SGEN_CH_TIMING_24K;
-		break;
-	case 32000:
-		sinegen_timing = SGEN_CH_TIMING_32K;
-		break;
-	case 48000:
-		sinegen_timing = SGEN_CH_TIMING_48K;
-		break;
-	case 96000:
-		sinegen_timing = SGEN_CH_TIMING_96K;
-		break;
-	case 192000:
-		sinegen_timing = SGEN_CH_TIMING_192K;
-		break;
-	case 384000:
-		sinegen_timing = SGEN_CH_TIMING_384K;
-		break;
-	case 11025:
-		sinegen_timing = SGEN_CH_TIMING_11P025K;
-		break;
-	case 22050:
-		sinegen_timing = SGEN_CH_TIMING_22P05K;
-		break;
-	case 44100:
-		sinegen_timing = SGEN_CH_TIMING_44P1K;
-		break;
-	case 88200:
-		sinegen_timing = SGEN_CH_TIMING_88P2K;
-		break;
-	case 176400:
-		sinegen_timing = SGEN_CH_TIMING_176P4K;
-		break;
-	case 352800:
-		sinegen_timing = SGEN_CH_TIMING_352P8K;
-		break;
-	default:
-		sinegen_timing = SGEN_CH_TIMING_48K;
-		tr_err(&sgen_tr, "invalid rate %d, set default 48k ", rate);
-	}
-	tr_dbg(&sgen_tr, "rate %d, sinegen_timing %d ", rate, sinegen_timing);
-	return sinegen_timing;
-}
-
-static void mtk_afe_reg_update_bits(uint32_t addr_offset, uint32_t mask, uint32_t val, int shift)
-{
-	io_reg_update_bits(AFE_BASE_ADDR + addr_offset, mask << shift, val << shift);
-}
-
-static uint32_t mtk_afe_reg_read(uint32_t addr_offset)
-{
-	return io_reg_read(AFE_BASE_ADDR + addr_offset);
-}
-
-static void mt8186_afe_sinegen_enable(uint32_t sgen_id, uint32_t rate, int enable)
-{
-	uint32_t loopback_mode, reg_1, reg_2, sinegen_timing;
-
-	tr_dbg(&sgen_tr, "sgen_id %d, enable %d", sgen_id, enable);
-
-	sinegen_timing = mt8186_sinegen_timing(rate);
-
-	if (enable == 1) {
-		/* set loopback mode */
-		switch (sgen_id) {
-		case MT8186_MEMIF_UL1:
-			loopback_mode = MT8186_SGEN_UL1;
-			break;
-		case MT8186_MEMIF_UL2:
-			loopback_mode = MT8186_SGEN_UL2;
-			break;
-		case MT8186_MEMIF_DL1:
-			loopback_mode = MT8186_SGEN_DL1;
-			break;
-		case MT8186_MEMIF_DL2:
-			loopback_mode = MT8186_SGEN_DL2;
-			break;
-		default:
-			tr_err(&sgen_tr, "invalid sgen_id %d", sgen_id);
-			return;
-		}
-		/* enable sinegen clock*/
-		mtk_afe_reg_update_bits(AUDIO_TOP_CON0, AUDIO_TML_PD_MASK, 0, AUDIO_TML_PD_SHIFT);
-
-		/*loopback source*/
-		mtk_afe_reg_update_bits(AFE_SINEGEN_CON2, AFE_SINEGEN_LB_MODE_MSK, loopback_mode,
-					AFE_SINEGEN_LB_MODE_SHIFT);
-
-		/* sine gen timing*/
-		mtk_afe_reg_update_bits(AFE_SINEGEN_CON0, AFE_SINEGEN_CON1_TIMING_CH1_MASK,
-					sinegen_timing, AFE_SINEGEN_CON1_TIMING_CH1_SHIFT);
-		mtk_afe_reg_update_bits(AFE_SINEGEN_CON0, AFE_SINEGEN_CON1_TIMING_CH2_MASK,
-					sinegen_timing, AFE_SINEGEN_CON1_TIMING_CH2_SHIFT);
-
-		/*freq div*/
-		mtk_afe_reg_update_bits(AFE_SINEGEN_CON0, AFE_SGEN_FREQ_DIV_CH1_MASK,
-					SGEN_FREQ_64D1, AFE_SGEN_FREQ_DIV_CH1_SHIFT);
-		mtk_afe_reg_update_bits(AFE_SINEGEN_CON0, AFE_SGEN_FREQ_DIV_CH2_MASK,
-					SGEN_FREQ_64D2, AFE_SGEN_FREQ_DIV_CH2_SHIFT);
-
-		/*amp div*/
-		mtk_afe_reg_update_bits(AFE_SINEGEN_CON0, AFE_SGEN_AMP_DIV_CH1_MASK, SGEN_AMP_D2,
-					AFE_SGEN_AMP_DIV_CH1_SHIFT);
-		mtk_afe_reg_update_bits(AFE_SINEGEN_CON0, AFE_SGEN_AMP_DIV_CH2_MASK, SGEN_AMP_D2,
-					AFE_SGEN_AMP_DIV_CH2_SHIFT);
-		/* enable sgen*/
-		mtk_afe_reg_update_bits(AFE_SINEGEN_CON0, AFE_SGEN_ENABLE_MASK, 1,
-					AFE_SGEN_ENABLE_SHIFT);
-	} else {
-		/* disable sgen*/
-		mtk_afe_reg_update_bits(AFE_SINEGEN_CON0, AFE_SGEN_ENABLE_MASK, 0,
-					AFE_SGEN_ENABLE_SHIFT);
-
-		/* disable sgen clock */
-		mtk_afe_reg_update_bits(AUDIO_TOP_CON0, AUDIO_TML_PD_MASK, 1, AUDIO_TML_PD_SHIFT);
-	}
-
-	reg_1 = mtk_afe_reg_read(AFE_SINEGEN_CON0);
-	reg_2 = mtk_afe_reg_read(AFE_SINEGEN_CON2);
-	tr_dbg(&sgen_tr, "AFE_SINEGEN_CON0 0x%x, AFE_SINEGEN_CON2 0x%x", reg_1, reg_2);
-}
-
-void afe_sinegen_enable(void)
-{
-	mt8186_afe_sinegen_enable(TEST_SGEN_ID, 48000, 1);
-}
-
-void afe_sinegen_disable(void)
-{
-	mt8186_afe_sinegen_enable(TEST_SGEN_ID, 48000, 0);
-}
diff --git a/src/drivers/mediatek/afe/mt8188/CMakeLists.txt b/src/drivers/mediatek/afe/mt8188/CMakeLists.txt
deleted file mode 100644
index 3f0653684edf..000000000000
--- a/src/drivers/mediatek/afe/mt8188/CMakeLists.txt
+++ /dev/null
@@ -1,5 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-
-if(CONFIG_TEST_SGEN)
-add_local_sources(sof afe-sgen.c)
-endif()
diff --git a/src/drivers/mediatek/afe/mt8188/afe-sgen.c b/src/drivers/mediatek/afe/mt8188/afe-sgen.c
deleted file mode 100644
index ab4b1a18f727..000000000000
--- a/src/drivers/mediatek/afe/mt8188/afe-sgen.c
+++ /dev/null
@@ -1,257 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-/*
- * Copyright(c) 2023 MediaTek. All rights reserved.
- *
- * Author: Trevor Wu <trevor.wu@mediatek.com>
- */
-
-#include <stdint.h>
-
-#include <sof/drivers/afe-sgen.h>
-#include <sof/lib/io.h>
-#include <sof/lib/uuid.h>
-#include <sof/trace/trace.h>
-
-#include <mt8188-afe-reg.h>
-#include <mt8188-afe-common.h>
-
-SOF_DEFINE_REG_UUID(sgen_mt8188);
-
-/* unused with Zephyr, generates no output */
-DECLARE_TR_CTX(sgen_tr, SOF_UUID(sgen_mt8188_uuid), LOG_LEVEL_INFO);
-
-/*
- * Note: TEST_SGEN for test only
- * Define this TEST_SGEN to enable sine tone generator
- * then output data to audio memory interface(memif),
- * you can set TEST_SGEN_ID to choose output to which memif.
- * e.g. set TEST_SGEN as '1' and TEST_SGEN_ID as "MT8186_MEMIF_DL2",
- * the data source of DL2 will from sine generator.
- */
-#define TEST_SGEN_ID MT8188_MEMIF_DL2
-#define AUDIO_TML_PD_MASK 1
-#define AUDIO_TML_PD_SHIFT 27
-
-#define AFE_SGEN_FREQ_DIV_CH1_MASK 0x1f
-#define AFE_SGEN_FREQ_DIV_CH1_SHIFT 0
-#define AFE_SGEN_FREQ_DIV_CH2_MASK 0x1f
-#define AFE_SGEN_FREQ_DIV_CH2_SHIFT 12
-#define AFE_SGEN_AMP_DIV_CH1_MASK 0x7
-#define AFE_SGEN_AMP_DIV_CH1_SHIFT 5
-#define AFE_SGEN_AMP_DIV_CH2_MASK 0x7
-#define AFE_SGEN_AMP_DIV_CH2_SHIFT 17
-#define AFE_SGEN_MUTE_CH1_MASK 0x1
-#define AFE_SGEN_MUTE_CH1_SHIFT 24
-#define AFE_SGEN_MUTE_CH2_MASK 0x1
-#define AFE_SGEN_MUTE_CH2_SHIFT 25
-#define AFE_SGEN_ENABLE_MASK 0x1
-#define AFE_SGEN_ENABLE_SHIFT 26
-
-#define AFE_SINEGEN_CON1_TIMING_CH1_MASK 0x1f
-#define AFE_SINEGEN_CON1_TIMING_CH1_SHIFT 16
-#define AFE_SINEGEN_CON1_TIMING_CH2_MASK 0x1f
-#define AFE_SINEGEN_CON1_TIMING_CH2_SHIFT 21
-
-#define AFE_SINEGEN_LB_MODE_MSK 0xff
-#define AFE_SINEGEN_LB_MODE_SHIFT 24
-
-enum {
-	MT8188_SGEN_UL5 = 0x18,
-	MT8188_SGEN_UL4 = 0x1f,
-	MT8188_SGEN_DL3 = 0x47,
-	MT8188_SGEN_DL2 = 0x60,
-};
-
-/*sgen freq div*/
-enum {
-	SGEN_FREQ_64D1 = 1,
-	SGEN_FREQ_64D2 = 2,
-	SGEN_FREQ_64D3 = 3,
-	SGEN_FREQ_64D4 = 4,
-	SGEN_FREQ_64D5 = 5,
-	SGEN_FREQ_64D6 = 6,
-	SGEN_FREQ_64D7 = 7,
-	SGEN_FREQ_64D8 = 8,
-};
-
-/*sgen amp div*/
-enum {
-	SGEN_AMP_D1 = 0,
-	SGEN_AMP_D2 = 1,
-	SGEN_AMP_D4 = 2,
-	SGEN_AMP_D8 = 3,
-	SGEN_AMP_D16 = 4,
-	SGEN_AMP_D32 = 5,
-	SGEN_AMP_D64 = 6,
-	SGEN_AMP_D128 = 7,
-};
-
-enum {
-	SGEN_CH_TIMING_8K = 0,
-	SGEN_CH_TIMING_12K = 1,
-	SGEN_CH_TIMING_16K = 2,
-	SGEN_CH_TIMING_24K = 3,
-	SGEN_CH_TIMING_32K = 4,
-	SGEN_CH_TIMING_48K = 5,
-	SGEN_CH_TIMING_96K = 6,
-	SGEN_CH_TIMING_192K = 7,
-	SGEN_CH_TIMING_384K = 8,
-	SGEN_CH_TIMING_7P35K = 16,
-	SGEN_CH_TIMING_11P025K = 17,
-	SGEN_CH_TIMING_14P7K = 18,
-	SGEN_CH_TIMING_22P05K = 19,
-	SGEN_CH_TIMING_29P4K = 20,
-	SGEN_CH_TIMING_44P1K = 21,
-	SGEN_CH_TIMING_88P2K = 22,
-	SGEN_CH_TIMING_176P4K = 23,
-	SGEN_CH_TIMING_352P8K = 24,
-};
-
-static uint32_t mt8188_sinegen_timing(uint32_t rate)
-{
-	uint32_t sinegen_timing;
-
-	switch (rate) {
-	case 8000:
-		sinegen_timing = SGEN_CH_TIMING_8K;
-		break;
-	case 12000:
-		sinegen_timing = SGEN_CH_TIMING_12K;
-		break;
-	case 16000:
-		sinegen_timing = SGEN_CH_TIMING_16K;
-		break;
-	case 24000:
-		sinegen_timing = SGEN_CH_TIMING_24K;
-		break;
-	case 32000:
-		sinegen_timing = SGEN_CH_TIMING_32K;
-		break;
-	case 48000:
-		sinegen_timing = SGEN_CH_TIMING_48K;
-		break;
-	case 96000:
-		sinegen_timing = SGEN_CH_TIMING_96K;
-		break;
-	case 192000:
-		sinegen_timing = SGEN_CH_TIMING_192K;
-		break;
-	case 384000:
-		sinegen_timing = SGEN_CH_TIMING_384K;
-		break;
-	case 7350:
-		sinegen_timing = SGEN_CH_TIMING_7P35K;
-		break;
-	case 11025:
-		sinegen_timing = SGEN_CH_TIMING_11P025K;
-		break;
-	case 22050:
-		sinegen_timing = SGEN_CH_TIMING_22P05K;
-		break;
-	case 44100:
-		sinegen_timing = SGEN_CH_TIMING_44P1K;
-		break;
-	case 88200:
-		sinegen_timing = SGEN_CH_TIMING_88P2K;
-		break;
-	case 176400:
-		sinegen_timing = SGEN_CH_TIMING_176P4K;
-		break;
-	case 352800:
-		sinegen_timing = SGEN_CH_TIMING_352P8K;
-		break;
-	default:
-		sinegen_timing = SGEN_CH_TIMING_48K;
-		tr_err(&sgen_tr, "invalid rate %d, set default 48k ", rate);
-	}
-	tr_dbg(&sgen_tr, "rate %d, sinegen_timing %d ", rate, sinegen_timing);
-	return sinegen_timing;
-}
-
-static void mtk_afe_reg_update_bits(uint32_t addr_offset, uint32_t mask, uint32_t val, int shift)
-{
-	io_reg_update_bits(AFE_BASE_ADDR + addr_offset, mask << shift, val << shift);
-}
-
-static uint32_t mtk_afe_reg_read(uint32_t addr_offset)
-{
-	return io_reg_read(AFE_BASE_ADDR + addr_offset);
-}
-
-static void mt8188_afe_sinegen_enable(uint32_t sgen_id, uint32_t rate, int enable)
-{
-	uint32_t loopback_mode, reg_1, reg_2, sinegen_timing;
-
-	tr_dbg(&sgen_tr, "sgen_id %d, enable %d", sgen_id, enable);
-
-	sinegen_timing = mt8188_sinegen_timing(rate);
-
-	if (enable == 1) {
-		/* set loopback mode */
-		switch (sgen_id) {
-		case MT8188_MEMIF_UL4:
-			loopback_mode = MT8188_SGEN_UL4;
-			break;
-		case MT8188_MEMIF_UL5:
-			loopback_mode = MT8188_SGEN_UL5;
-			break;
-		case MT8188_MEMIF_DL2:
-			loopback_mode = MT8188_SGEN_DL2;
-			break;
-		case MT8188_MEMIF_DL3:
-			loopback_mode = MT8188_SGEN_DL3;
-			break;
-		default:
-			tr_err(&sgen_tr, "invalid sgen_id %d", sgen_id);
-			return;
-		}
-		/* enable sinegen clock*/
-		mtk_afe_reg_update_bits(AUDIO_TOP_CON0, AUDIO_TML_PD_MASK, 0, AUDIO_TML_PD_SHIFT);
-
-		/*loopback source*/
-		mtk_afe_reg_update_bits(AFE_SINEGEN_CON2, AFE_SINEGEN_LB_MODE_MSK, loopback_mode,
-					AFE_SINEGEN_LB_MODE_SHIFT);
-
-		/* sine gen timing*/
-		mtk_afe_reg_update_bits(AFE_SINEGEN_CON1, AFE_SINEGEN_CON1_TIMING_CH1_MASK,
-					sinegen_timing, AFE_SINEGEN_CON1_TIMING_CH1_SHIFT);
-		mtk_afe_reg_update_bits(AFE_SINEGEN_CON1, AFE_SINEGEN_CON1_TIMING_CH2_MASK,
-					sinegen_timing, AFE_SINEGEN_CON1_TIMING_CH2_SHIFT);
-
-		/*freq div*/
-		mtk_afe_reg_update_bits(AFE_SINEGEN_CON0, AFE_SGEN_FREQ_DIV_CH1_MASK,
-					SGEN_FREQ_64D1, AFE_SGEN_FREQ_DIV_CH1_SHIFT);
-		mtk_afe_reg_update_bits(AFE_SINEGEN_CON0, AFE_SGEN_FREQ_DIV_CH2_MASK,
-					SGEN_FREQ_64D2, AFE_SGEN_FREQ_DIV_CH2_SHIFT);
-
-		/*amp div*/
-		mtk_afe_reg_update_bits(AFE_SINEGEN_CON0, AFE_SGEN_AMP_DIV_CH1_MASK, SGEN_AMP_D2,
-					AFE_SGEN_AMP_DIV_CH1_SHIFT);
-		mtk_afe_reg_update_bits(AFE_SINEGEN_CON0, AFE_SGEN_AMP_DIV_CH2_MASK, SGEN_AMP_D2,
-					AFE_SGEN_AMP_DIV_CH2_SHIFT);
-		/* enable sgen*/
-		mtk_afe_reg_update_bits(AFE_SINEGEN_CON0, AFE_SGEN_ENABLE_MASK, 1,
-					AFE_SGEN_ENABLE_SHIFT);
-	} else {
-		/* disable sgen*/
-		mtk_afe_reg_update_bits(AFE_SINEGEN_CON0, AFE_SGEN_ENABLE_MASK, 0,
-					AFE_SGEN_ENABLE_SHIFT);
-
-		/* disable sgen clock */
-		mtk_afe_reg_update_bits(AUDIO_TOP_CON0, AUDIO_TML_PD_MASK, 1, AUDIO_TML_PD_SHIFT);
-	}
-
-	reg_1 = mtk_afe_reg_read(AFE_SINEGEN_CON0);
-	reg_2 = mtk_afe_reg_read(AFE_SINEGEN_CON2);
-	tr_dbg(&sgen_tr, "AFE_SINEGEN_CON0 0x%x, AFE_SINEGEN_CON2 0x%x", reg_1, reg_2);
-}
-
-void afe_sinegen_enable(void)
-{
-	mt8188_afe_sinegen_enable(TEST_SGEN_ID, 48000, 1);
-}
-
-void afe_sinegen_disable(void)
-{
-	mt8188_afe_sinegen_enable(TEST_SGEN_ID, 48000, 0);
-}
diff --git a/src/drivers/mediatek/afe/mt8195/CMakeLists.txt b/src/drivers/mediatek/afe/mt8195/CMakeLists.txt
deleted file mode 100644
index 3f0653684edf..000000000000
--- a/src/drivers/mediatek/afe/mt8195/CMakeLists.txt
+++ /dev/null
@@ -1,5 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-
-if(CONFIG_TEST_SGEN)
-add_local_sources(sof afe-sgen.c)
-endif()
diff --git a/src/drivers/mediatek/afe/mt8195/afe-sgen.c b/src/drivers/mediatek/afe/mt8195/afe-sgen.c
deleted file mode 100644
index 64f96a0208d0..000000000000
--- a/src/drivers/mediatek/afe/mt8195/afe-sgen.c
+++ /dev/null
@@ -1,265 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-/*
- * Copyright(c) 2023 MediaTek. All rights reserved.
- *
- * Author: Trevor Wu <trevor.wu@mediatek.com>
- */
-
-#include <stdint.h>
-
-#include <sof/drivers/afe-sgen.h>
-#include <sof/lib/io.h>
-#include <sof/lib/uuid.h>
-#include <sof/trace/trace.h>
-
-#include <mt8195-afe-regs.h>
-#include <mt8195-afe-common.h>
-
-SOF_DEFINE_REG_UUID(sgen_mt8195);
-
-/* unused with Zephyr, generates no output */
-DECLARE_TR_CTX(sgen_tr, SOF_UUID(sgen_mt8195_uuid), LOG_LEVEL_INFO);
-
-/*
- * Note: TEST_SGEN for test only
- * Define this TEST_SGEN to enable sine tone generator
- * then output data to audio memory interface(memif),
- * you can set TEST_SGEN_ID to choose output to which memif.
- * e.g. set TEST_SGEN as '1' and TEST_SGEN_ID as "MT8186_MEMIF_DL2",
- * the data source of DL2 will from sine generator.
- */
-#include <mt8195-afe-regs.h>
-#include <mt8195-afe-common.h>
-#define TEST_SGEN_ID MT8195_MEMIF_DL2
-#define AUDIO_TML_PD_MASK 1
-#define AUDIO_TML_PD_SHIFT 27
-
-#define AFE_SGEN_FREQ_DIV_CH1_MASK 0x1f
-#define AFE_SGEN_FREQ_DIV_CH1_SHIFT 0
-#define AFE_SGEN_FREQ_DIV_CH2_MASK 0x1f
-#define AFE_SGEN_FREQ_DIV_CH2_SHIFT 12
-#define AFE_SGEN_AMP_DIV_CH1_MASK 0x7
-#define AFE_SGEN_AMP_DIV_CH1_SHIFT 5
-#define AFE_SGEN_AMP_DIV_CH2_MASK 0x7
-#define AFE_SGEN_AMP_DIV_CH2_SHIFT 17
-#define AFE_SGEN_MUTE_CH1_MASK 0x1
-#define AFE_SGEN_MUTE_CH1_SHIFT 24
-#define AFE_SGEN_MUTE_CH2_MASK 0x1
-#define AFE_SGEN_MUTE_CH2_SHIFT 25
-#define AFE_SGEN_ENABLE_MASK 0x1
-#define AFE_SGEN_ENABLE_SHIFT 26
-
-#define AFE_SINEGEN_CON1_TIMING_CH1_MASK 0x1f
-#define AFE_SINEGEN_CON1_TIMING_CH1_SHIFT 16
-#define AFE_SINEGEN_CON1_TIMING_CH2_MASK 0x1f
-#define AFE_SINEGEN_CON1_TIMING_CH2_SHIFT 21
-
-#define AFE_SINEGEN_LB_MODE_MSK 0xff
-#define AFE_SINEGEN_LB_MODE_SHIFT 24
-
-enum {
-	MT8195_SGEN_UL5 = 0x18,
-	MT8195_SGEN_UL4 = 0x1f,
-	MT8195_SGEN_DL3 = 0x47,
-	MT8195_SGEN_DL2 = 0x60,
-};
-
-/*sgen freq div*/
-enum {
-	SGEN_FREQ_64D1 = 1,
-	SGEN_FREQ_64D2 = 2,
-	SGEN_FREQ_64D3 = 3,
-	SGEN_FREQ_64D4 = 4,
-	SGEN_FREQ_64D5 = 5,
-	SGEN_FREQ_64D6 = 6,
-	SGEN_FREQ_64D7 = 7,
-	SGEN_FREQ_64D8 = 8,
-};
-
-/*sgen amp div*/
-enum {
-	SGEN_AMP_D1 = 0,
-	SGEN_AMP_D2 = 1,
-	SGEN_AMP_D4 = 2,
-	SGEN_AMP_D8 = 3,
-	SGEN_AMP_D16 = 4,
-	SGEN_AMP_D32 = 5,
-	SGEN_AMP_D64 = 6,
-	SGEN_AMP_D128 = 7,
-};
-
-enum {
-	SGEN_CH_TIMING_8K = 0,
-	SGEN_CH_TIMING_12K = 1,
-	SGEN_CH_TIMING_16K = 2,
-	SGEN_CH_TIMING_24K = 3,
-	SGEN_CH_TIMING_32K = 4,
-	SGEN_CH_TIMING_48K = 5,
-	SGEN_CH_TIMING_96K = 6,
-	SGEN_CH_TIMING_192K = 7,
-	SGEN_CH_TIMING_384K = 8,
-	SGEN_CH_TIMING_7P35K = 16,
-	SGEN_CH_TIMING_11P025K = 17,
-	SGEN_CH_TIMING_14P7K = 18,
-	SGEN_CH_TIMING_22P05K = 19,
-	SGEN_CH_TIMING_29P4K = 20,
-	SGEN_CH_TIMING_44P1K = 21,
-	SGEN_CH_TIMING_88P2K = 22,
-	SGEN_CH_TIMING_176P4K = 23,
-	SGEN_CH_TIMING_352P8K = 24,
-};
-
-static uint32_t mt8195_sinegen_timing(uint32_t rate)
-{
-	uint32_t sinegen_timing;
-
-	switch (rate) {
-	case 8000:
-		sinegen_timing = SGEN_CH_TIMING_8K;
-		break;
-	case 12000:
-		sinegen_timing = SGEN_CH_TIMING_12K;
-		break;
-	case 16000:
-		sinegen_timing = SGEN_CH_TIMING_16K;
-		break;
-	case 24000:
-		sinegen_timing = SGEN_CH_TIMING_24K;
-		break;
-	case 32000:
-		sinegen_timing = SGEN_CH_TIMING_32K;
-		break;
-	case 48000:
-		sinegen_timing = SGEN_CH_TIMING_48K;
-		break;
-	case 96000:
-		sinegen_timing = SGEN_CH_TIMING_96K;
-		break;
-	case 192000:
-		sinegen_timing = SGEN_CH_TIMING_192K;
-		break;
-	case 384000:
-		sinegen_timing = SGEN_CH_TIMING_384K;
-		break;
-	case 7350:
-		sinegen_timing = SGEN_CH_TIMING_7P35K;
-		break;
-	case 11025:
-		sinegen_timing = SGEN_CH_TIMING_11P025K;
-		break;
-	case 14700:
-		sinegen_timing = SGEN_CH_TIMING_14P7K;
-		break;
-	case 22050:
-		sinegen_timing = SGEN_CH_TIMING_22P05K;
-		break;
-	case 29400:
-		sinegen_timing = SGEN_CH_TIMING_29P4K;
-		break;
-	case 44100:
-		sinegen_timing = SGEN_CH_TIMING_44P1K;
-		break;
-	case 88200:
-		sinegen_timing = SGEN_CH_TIMING_88P2K;
-		break;
-	case 176400:
-		sinegen_timing = SGEN_CH_TIMING_176P4K;
-		break;
-	case 352800:
-		sinegen_timing = SGEN_CH_TIMING_352P8K;
-		break;
-	default:
-		sinegen_timing = SGEN_CH_TIMING_48K;
-		tr_err(&sgen_tr, "invalid rate %d, set default 48k ", rate);
-	}
-	tr_dbg(&sgen_tr, "rate %d, sinegen_timing %d ", rate, sinegen_timing);
-	return sinegen_timing;
-}
-
-static void mtk_afe_reg_update_bits(uint32_t addr_offset, uint32_t mask, uint32_t val, int shift)
-{
-	io_reg_update_bits(AFE_BASE_ADDR + addr_offset, mask << shift, val << shift);
-}
-
-static uint32_t mtk_afe_reg_read(uint32_t addr_offset)
-{
-	return io_reg_read(AFE_BASE_ADDR + addr_offset);
-}
-
-static void mt8195_afe_sinegen_enable(uint32_t sgen_id, uint32_t rate, int enable)
-{
-	uint32_t loopback_mode, reg_1, reg_2, sinegen_timing;
-
-	tr_dbg(&sgen_tr, "sgen_id %d, enable %d", sgen_id, enable);
-
-	sinegen_timing = mt8195_sinegen_timing(rate);
-
-	if (enable == 1) {
-		/* set loopback mode */
-		switch (sgen_id) {
-		case MT8195_MEMIF_UL4:
-			loopback_mode = MT8195_SGEN_UL4;
-			break;
-		case MT8195_MEMIF_UL5:
-			loopback_mode = MT8195_SGEN_UL5;
-			break;
-		case MT8195_MEMIF_DL2:
-			loopback_mode = MT8195_SGEN_DL2;
-			break;
-		case MT8195_MEMIF_DL3:
-			loopback_mode = MT8195_SGEN_DL3;
-			break;
-		default:
-			tr_err(&sgen_tr, "invalid sgen_id %d", sgen_id);
-			return;
-		}
-		/* enable sinegen clock*/
-		mtk_afe_reg_update_bits(AUDIO_TOP_CON0, AUDIO_TML_PD_MASK, 0, AUDIO_TML_PD_SHIFT);
-
-		/*loopback source*/
-		mtk_afe_reg_update_bits(AFE_SINEGEN_CON2, AFE_SINEGEN_LB_MODE_MSK, loopback_mode,
-					AFE_SINEGEN_LB_MODE_SHIFT);
-
-		/* sine gen timing*/
-		mtk_afe_reg_update_bits(AFE_SINEGEN_CON1, AFE_SINEGEN_CON1_TIMING_CH1_MASK,
-					sinegen_timing, AFE_SINEGEN_CON1_TIMING_CH1_SHIFT);
-		mtk_afe_reg_update_bits(AFE_SINEGEN_CON1, AFE_SINEGEN_CON1_TIMING_CH2_MASK,
-					sinegen_timing, AFE_SINEGEN_CON1_TIMING_CH2_SHIFT);
-
-		/*freq div*/
-		mtk_afe_reg_update_bits(AFE_SINEGEN_CON0, AFE_SGEN_FREQ_DIV_CH1_MASK,
-					SGEN_FREQ_64D1, AFE_SGEN_FREQ_DIV_CH1_SHIFT);
-		mtk_afe_reg_update_bits(AFE_SINEGEN_CON0, AFE_SGEN_FREQ_DIV_CH2_MASK,
-					SGEN_FREQ_64D2, AFE_SGEN_FREQ_DIV_CH2_SHIFT);
-
-		/*amp div*/
-		mtk_afe_reg_update_bits(AFE_SINEGEN_CON0, AFE_SGEN_AMP_DIV_CH1_MASK, SGEN_AMP_D2,
-					AFE_SGEN_AMP_DIV_CH1_SHIFT);
-		mtk_afe_reg_update_bits(AFE_SINEGEN_CON0, AFE_SGEN_AMP_DIV_CH2_MASK, SGEN_AMP_D2,
-					AFE_SGEN_AMP_DIV_CH2_SHIFT);
-		/* enable sgen*/
-		mtk_afe_reg_update_bits(AFE_SINEGEN_CON0, AFE_SGEN_ENABLE_MASK, 1,
-					AFE_SGEN_ENABLE_SHIFT);
-	} else {
-		/* disable sgen*/
-		mtk_afe_reg_update_bits(AFE_SINEGEN_CON0, AFE_SGEN_ENABLE_MASK, 0,
-					AFE_SGEN_ENABLE_SHIFT);
-
-		/* disable sgen clock */
-		mtk_afe_reg_update_bits(AUDIO_TOP_CON0, AUDIO_TML_PD_MASK, 1, AUDIO_TML_PD_SHIFT);
-	}
-
-	reg_1 = mtk_afe_reg_read(AFE_SINEGEN_CON0);
-	reg_2 = mtk_afe_reg_read(AFE_SINEGEN_CON2);
-	tr_dbg(&sgen_tr, "AFE_SINEGEN_CON0 0x%x, AFE_SINEGEN_CON2 0x%x", reg_1, reg_2);
-}
-
-void afe_sinegen_enable(void)
-{
-	mt8195_afe_sinegen_enable(TEST_SGEN_ID, 48000, 1);
-}
-
-void afe_sinegen_disable(void)
-{
-	mt8195_afe_sinegen_enable(TEST_SGEN_ID, 48000, 0);
-}
diff --git a/src/drivers/mediatek/afe/mt8196/CMakeLists.txt b/src/drivers/mediatek/afe/mt8196/CMakeLists.txt
deleted file mode 100755
index 3f0653684edf..000000000000
--- a/src/drivers/mediatek/afe/mt8196/CMakeLists.txt
+++ /dev/null
@@ -1,5 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-
-if(CONFIG_TEST_SGEN)
-add_local_sources(sof afe-sgen.c)
-endif()
diff --git a/src/drivers/mediatek/afe/mt8196/afe-sgen.c b/src/drivers/mediatek/afe/mt8196/afe-sgen.c
deleted file mode 100755
index f78b8e4a5d8d..000000000000
--- a/src/drivers/mediatek/afe/mt8196/afe-sgen.c
+++ /dev/null
@@ -1,23 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-/*
- * Copyright(c) 2024 MediaTek. All rights reserved.
- *
- * Author: Darren Ye <darren.ye@mediatek.com>
- */
-
-#include <stdint.h>
-
-#include <sof/drivers/afe-sgen.h>
-#include <sof/lib/io.h>
-#include <sof/lib/uuid.h>
-#include <sof/trace/trace.h>
-#include <mt8196-afe-reg.h>
-#include <mt8196-afe-common.h>
-
-void afe_sinegen_enable(void)
-{
-}
-
-void afe_sinegen_disable(void)
-{
-}
diff --git a/src/drivers/mediatek/afe/mt8365/CMakeLists.txt b/src/drivers/mediatek/afe/mt8365/CMakeLists.txt
deleted file mode 100644
index 3f0653684edf..000000000000
--- a/src/drivers/mediatek/afe/mt8365/CMakeLists.txt
+++ /dev/null
@@ -1,5 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-
-if(CONFIG_TEST_SGEN)
-add_local_sources(sof afe-sgen.c)
-endif()
diff --git a/src/drivers/mediatek/afe/mt8365/afe-sgen.c b/src/drivers/mediatek/afe/mt8365/afe-sgen.c
deleted file mode 100644
index 90e746af12d6..000000000000
--- a/src/drivers/mediatek/afe/mt8365/afe-sgen.c
+++ /dev/null
@@ -1,242 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-/*
- * Copyright(c) 2024 MediaTek. All rights reserved.
- *
- * Author: Andrew Perepech <andrew.perepech@mediatek.com>
- */
-
-#include <stdint.h>
-
-#include <sof/drivers/afe-sgen.h>
-#include <sof/lib/io.h>
-#include <sof/lib/uuid.h>
-#include <sof/trace/trace.h>
-
-#include <mt8365-afe-regs.h>
-#include <mt8365-afe-common.h>
-
-SOF_DEFINE_REG_UUID(sgen_mt8365);
-
-/* unused with Zephyr, generates no output */
-DECLARE_TR_CTX(sgen_tr, SOF_UUID(sgen_mt8365_uuid), LOG_LEVEL_INFO);
-
-/*
- * Note: TEST_SGEN for test only
- * Define this TEST_SGEN to enable sine tone generator
- * then output data to audio memory interface(memif),
- * you can set TEST_SGEN_ID to choose output to which memif.
- * e.g. set TEST_SGEN as '1' and TEST_SGEN_ID as "MT8365_MEMIF_DL1",
- * the data source of DL2 will from sine generator.
- */
-#define TEST_SGEN_ID MT8365_MEMIF_DL1
-#define AUDIO_TML_PD_MASK 1
-#define AUDIO_TML_PD_SHIFT 27
-
-#define AFE_SGEN_FREQ_DIV_CH1_MASK 0x1f
-#define AFE_SGEN_FREQ_DIV_CH1_SHIFT 0
-#define AFE_SGEN_FREQ_DIV_CH2_MASK 0x1f
-#define AFE_SGEN_FREQ_DIV_CH2_SHIFT 12
-#define AFE_SGEN_AMP_DIV_CH1_MASK 0x7
-#define AFE_SGEN_AMP_DIV_CH1_SHIFT 5
-#define AFE_SGEN_AMP_DIV_CH2_MASK 0x7
-#define AFE_SGEN_AMP_DIV_CH2_SHIFT 17
-#define AFE_SGEN_MUTE_CH1_MASK 0x1
-#define AFE_SGEN_MUTE_CH1_SHIFT 24
-#define AFE_SGEN_MUTE_CH2_MASK 0x1
-#define AFE_SGEN_MUTE_CH2_SHIFT 25
-#define AFE_SGEN_ENABLE_MASK 0x1
-#define AFE_SGEN_ENABLE_SHIFT 26
-
-#define AFE_SGEN_TIMING_CH1_MASK 0x0f
-#define AFE_SGEN_TIMING_CH1_SHIFT 8
-#define AFE_SGEN_TIMING_CH2_MASK 0x0f
-#define AFE_SGEN_TIMING_CH2_SHIFT 20
-
-#define AFE_SINEGEN_LB_MODE_MSK 0x1f
-#define AFE_SINEGEN_LB_MODE_SHIFT 27
-
-enum {
-	MT8365_SGEN_AWB = (0x3 << 1) | 1,		// o5 + o6 + SGEN to out
-	MT8365_SGEN_VUL = (0x5 << 1) | 1,		// o9 + o10 + SGEN to out
-	MT8365_SGEN_DL1 = (0x3 << 1) | 0,		// i5 + i6 + SGEN to in
-	MT8365_SGEN_DL2 = (0x4 << 1) | 0		// i7 + i8 + SGEN to in
-};
-
-/*sgen freq div*/
-enum {
-	SGEN_FREQ_64D1 = 1,
-	SGEN_FREQ_64D2 = 2,
-	SGEN_FREQ_64D3 = 3,
-	SGEN_FREQ_64D4 = 4,
-	SGEN_FREQ_64D5 = 5,
-	SGEN_FREQ_64D6 = 6,
-	SGEN_FREQ_64D7 = 7,
-	SGEN_FREQ_64D8 = 8,
-};
-
-/*sgen amp div*/
-enum {
-	SGEN_AMP_D1 = 0,
-	SGEN_AMP_D2 = 1,
-	SGEN_AMP_D4 = 2,
-	SGEN_AMP_D8 = 3,
-	SGEN_AMP_D16 = 4,
-	SGEN_AMP_D32 = 5,
-	SGEN_AMP_D64 = 6,
-	SGEN_AMP_D128 = 7,
-};
-
-enum {
-	SGEN_CH_TIMING_8K = 0,
-	SGEN_CH_TIMING_11P025K = 1,
-	SGEN_CH_TIMING_12K = 2,
-	SGEN_CH_TIMING_16K = 4,
-	SGEN_CH_TIMING_22P05K = 5,
-	SGEN_CH_TIMING_24K = 6,
-	SGEN_CH_TIMING_32K = 8,
-	SGEN_CH_TIMING_44P1K = 9,
-	SGEN_CH_TIMING_48K = 10,
-	SGEN_CH_TIMING_88P2K = 11,
-	SGEN_CH_TIMING_96K = 12,
-	SGEN_CH_TIMING_176P4K = 13,
-	SGEN_CH_TIMING_192K = 14,
-};
-
-static uint32_t mt8365_sinegen_timing(uint32_t rate)
-{
-	uint32_t sinegen_timing;
-
-	switch (rate) {
-	case 8000:
-		sinegen_timing = SGEN_CH_TIMING_8K;
-		break;
-	case 11025:
-		sinegen_timing = SGEN_CH_TIMING_11P025K;
-		break;
-	case 12000:
-		sinegen_timing = SGEN_CH_TIMING_12K;
-		break;
-	case 16000:
-		sinegen_timing = SGEN_CH_TIMING_16K;
-		break;
-	case 22050:
-		sinegen_timing = SGEN_CH_TIMING_22P05K;
-		break;
-	case 24000:
-		sinegen_timing = SGEN_CH_TIMING_24K;
-		break;
-	case 32000:
-		sinegen_timing = SGEN_CH_TIMING_32K;
-		break;
-	case 44100:
-		sinegen_timing = SGEN_CH_TIMING_44P1K;
-		break;
-	case 48000:
-		sinegen_timing = SGEN_CH_TIMING_48K;
-		break;
-	case 88200:
-		sinegen_timing = SGEN_CH_TIMING_88P2K;
-		break;
-	case 96000:
-		sinegen_timing = SGEN_CH_TIMING_96K;
-		break;
-	case 176400:
-		sinegen_timing = SGEN_CH_TIMING_176P4K;
-		break;
-	case 192000:
-		sinegen_timing = SGEN_CH_TIMING_192K;
-		break;
-	default:
-		sinegen_timing = SGEN_CH_TIMING_48K;
-		tr_err(&sgen_tr, "invalid rate %d, set default 48k ", rate);
-	}
-	tr_dbg(&sgen_tr, "rate %d, sinegen_timing %d ", rate, sinegen_timing);
-	return sinegen_timing;
-}
-
-static void mtk_afe_reg_update_bits(uint32_t addr_offset, uint32_t mask, uint32_t val, int shift)
-{
-	io_reg_update_bits(AFE_REG_BASE + addr_offset, mask << shift, val << shift);
-}
-
-static uint32_t mtk_afe_reg_read(uint32_t addr_offset)
-{
-	return io_reg_read(AFE_REG_BASE + addr_offset);
-}
-
-static void mt8365_afe_sinegen_enable(uint32_t sgen_id, uint32_t rate, int enable)
-{
-	uint32_t loopback_mode, reg_1, sinegen_timing;
-
-	tr_dbg(&sgen_tr, "sgen_id %d, enable %d", sgen_id, enable);
-
-	sinegen_timing = mt8365_sinegen_timing(rate);
-
-	if (enable == 1) {
-		/* set loopback mode */
-		switch (sgen_id) {
-		case MT8365_MEMIF_AWB:
-			loopback_mode = MT8365_SGEN_AWB;
-			break;
-		case MT8365_MEMIF_VUL:
-			loopback_mode = MT8365_SGEN_VUL;
-			break;
-		case MT8365_MEMIF_DL1:
-			loopback_mode = MT8365_SGEN_DL1;
-			break;
-		case MT8365_MEMIF_DL2:
-			loopback_mode = MT8365_SGEN_DL2;
-			break;
-		default:
-			tr_err(&sgen_tr, "invalid sgen_id %d", sgen_id);
-			return;
-		}
-		/* enable sinegen clock*/
-		mtk_afe_reg_update_bits(AUDIO_TOP_CON0, AUDIO_TML_PD_MASK, 0, AUDIO_TML_PD_SHIFT);
-
-		/*loopback source*/
-		mtk_afe_reg_update_bits(AFE_SGEN_CON0, AFE_SINEGEN_LB_MODE_MSK, loopback_mode,
-					AFE_SINEGEN_LB_MODE_SHIFT);
-
-		/* sine gen timing*/
-		mtk_afe_reg_update_bits(AFE_SGEN_CON0, AFE_SGEN_TIMING_CH1_MASK,
-					sinegen_timing, AFE_SGEN_TIMING_CH1_SHIFT);
-		mtk_afe_reg_update_bits(AFE_SGEN_CON0, AFE_SGEN_TIMING_CH2_MASK,
-					sinegen_timing, AFE_SGEN_TIMING_CH2_SHIFT);
-
-		/*freq div*/
-		mtk_afe_reg_update_bits(AFE_SGEN_CON0, AFE_SGEN_FREQ_DIV_CH1_MASK,
-					SGEN_FREQ_64D1, AFE_SGEN_FREQ_DIV_CH1_SHIFT);
-		mtk_afe_reg_update_bits(AFE_SGEN_CON0, AFE_SGEN_FREQ_DIV_CH2_MASK,
-					SGEN_FREQ_64D2, AFE_SGEN_FREQ_DIV_CH2_SHIFT);
-
-		/*amp div*/
-		mtk_afe_reg_update_bits(AFE_SGEN_CON0, AFE_SGEN_AMP_DIV_CH1_MASK, SGEN_AMP_D2,
-					AFE_SGEN_AMP_DIV_CH1_SHIFT);
-		mtk_afe_reg_update_bits(AFE_SGEN_CON0, AFE_SGEN_AMP_DIV_CH2_MASK, SGEN_AMP_D2,
-					AFE_SGEN_AMP_DIV_CH2_SHIFT);
-		/* enable sgen*/
-		mtk_afe_reg_update_bits(AFE_SGEN_CON0, AFE_SGEN_ENABLE_MASK, 1,
-					AFE_SGEN_ENABLE_SHIFT);
-	} else {
-		/* disable sgen*/
-		mtk_afe_reg_update_bits(AFE_SGEN_CON0, AFE_SGEN_ENABLE_MASK, 0,
-					AFE_SGEN_ENABLE_SHIFT);
-
-		/* disable sgen clock */
-		mtk_afe_reg_update_bits(AUDIO_TOP_CON0, AUDIO_TML_PD_MASK, 1, AUDIO_TML_PD_SHIFT);
-	}
-
-	reg_1 = mtk_afe_reg_read(AFE_SGEN_CON0);
-	tr_dbg(&sgen_tr, "AFE_SGEN_CON0 0x%x", reg_1);
-}
-
-void afe_sinegen_enable(void)
-{
-	mt8365_afe_sinegen_enable(TEST_SGEN_ID, 48000, 1);
-}
-
-void afe_sinegen_disable(void)
-{
-	mt8365_afe_sinegen_enable(TEST_SGEN_ID, 48000, 0);
-}
diff --git a/src/drivers/mediatek/mt818x/CMakeLists.txt b/src/drivers/mediatek/mt818x/CMakeLists.txt
deleted file mode 100644
index 179e42329834..000000000000
--- a/src/drivers/mediatek/mt818x/CMakeLists.txt
+++ /dev/null
@@ -1,4 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-
-add_local_sources(sof interrupt.c ipc.c timer.c)
-
diff --git a/src/drivers/mediatek/mt818x/interrupt.c b/src/drivers/mediatek/mt818x/interrupt.c
deleted file mode 100644
index dd4a46944337..000000000000
--- a/src/drivers/mediatek/mt818x/interrupt.c
+++ /dev/null
@@ -1,228 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-/*
- * Copyright(c) 2022 MediaTek. All rights reserved.
- *
- * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
- *         Tinghan Shen <tinghan.shen@mediatek.com>
- */
-
-#include <errno.h>
-#include <inttypes.h>
-#include <rtos/bit.h>
-#include <sof/common.h>
-#include <rtos/interrupt.h>
-#include <sof/lib/cpu.h>
-#include <sof/lib/io.h>
-#include <sof/lib/memory.h>
-#include <sof/lib/uuid.h>
-#include <sof/list.h>
-#include <rtos/spinlock.h>
-#include <stdbool.h>
-#include <stddef.h>
-#include <stdint.h>
-
-#define PENDING_IRQ_INDEX_MAX 32
-
-SOF_DEFINE_REG_UUID(irq_mt818x);
-
-/* unused with Zephyr, generates no output */
-DECLARE_TR_CTX(int_tr, SOF_UUID(irq_mt818x_uuid), LOG_LEVEL_INFO);
-
-static void mtk_irq_init(void)
-{
-	/* disable all ADSP IRQ */
-	io_reg_write(MTK_ADSP_IRQ_EN, 0);
-
-	 /* mask all IRQs between ADSP and other subsys */
-	io_reg_write(MTK_ADSP_IRQ_MASK, MTK_DSP_OUT_IRQ_MASK);
-}
-
-static void mtk_irq_mask(struct irq_desc *desc, uint32_t irq, unsigned int core)
-{
-	if (!desc) {
-		io_reg_update_bits(MTK_ADSP_IRQ_EN, BIT(irq), 0);
-	} else {
-		switch (desc->irq) {
-		case MTK_DSP_IRQ_MAILBOX:
-			io_reg_update_bits(MTK_ADSP_IRQ_EN, BIT(desc->irq), 0);
-			break;
-		default:
-			tr_err(&int_tr, "Invalid interrupt %d", desc->irq);
-			return;
-		}
-	}
-}
-
-static void mtk_irq_unmask(struct irq_desc *desc, uint32_t irq, unsigned int core)
-{
-	if (!desc) {
-		io_reg_update_bits(MTK_ADSP_IRQ_EN, BIT(irq), BIT(irq));
-	} else {
-		switch (desc->irq) {
-		case MTK_DSP_IRQ_MAILBOX:
-			io_reg_update_bits(MTK_ADSP_IRQ_EN, BIT(desc->irq), BIT(desc->irq));
-			break;
-		default:
-			tr_err(&int_tr, "Invalid interrupt %d", desc->irq);
-			return;
-		}
-	}
-}
-
-static uint32_t mtk_irq_group_pending_status(uint32_t irq)
-{
-	uint32_t irq_status = 0;
-
-	if (irq == MTK_DSP_IRQ_MAILBOX &&
-	    (io_reg_read(MTK_ADSP_IRQ_STATUS) & BIT(MTK_DSP_IRQ_MAILBOX))) {
-		irq_status = io_reg_read(MTK_MBOX_IRQ_IN) & MTK_DSP_MBOX_MASK;
-	}
-
-	return irq_status;
-}
-
-static uint32_t mtk_get_pending_index(uint32_t current, uint32_t *next)
-{
-	uint32_t index;
-
-	if (current == 0)
-		return PENDING_IRQ_INDEX_MAX;
-
-	/* ffs returns one plus the index of the least significant 1-bit of input int */
-	index = ffs(current) - 1;
-
-	/* remove the handling index from current pending status */
-	*next = current & ~(1ull << index);
-
-	return index;
-}
-
-static inline void mtk_handle_group_pending_irq(struct irq_cascade_desc *cascade,
-						uint32_t line_index, uint32_t status)
-{
-	int core = cpu_get_id();
-	struct list_item *clist;
-	struct irq_desc *child = NULL;
-	uint32_t idx;
-	uint32_t next_status;
-	bool handled;
-	k_spinlock_key_t key;
-
-	idx = mtk_get_pending_index(status, &next_status);
-	while (idx < PENDING_IRQ_INDEX_MAX) {
-		handled = false;
-
-		key = k_spin_lock(&cascade->lock);
-		list_for_item(clist, &cascade->child[idx].list) {
-			child = container_of(clist, struct irq_desc, irq_list);
-
-			if (child->handler && (child->cpu_mask & 1 << core)) {
-				child->handler(child->handler_arg);
-				handled = true;
-			}
-		}
-		k_spin_unlock(&cascade->lock, key);
-
-		if (!handled) {
-			tr_err(&int_tr, "Not handle irq %u in group %u",
-			       idx, line_index);
-		}
-
-		idx = mtk_get_pending_index(next_status, &next_status);
-	}
-}
-
-static inline void mtk_irq_group_handler(void *data, uint32_t line_index)
-{
-	struct irq_desc *parent = data;
-	struct irq_cascade_desc *cascade =
-		container_of(parent, struct irq_cascade_desc, desc);
-	uint32_t status;
-
-	status = mtk_irq_group_pending_status(line_index);
-	if (status)
-		mtk_handle_group_pending_irq(cascade, line_index, status);
-	else
-		tr_err(&int_tr, "No pending irq in group %d", line_index);
-}
-
-#define DEFINE_IRQ_HANDLER(n) \
-	static void irqhandler_##n(void *arg) \
-	{ \
-		mtk_irq_group_handler(arg, n); \
-	}
-
-DEFINE_IRQ_HANDLER(2)
-
-static const char mtk_irq_mailbox[] = "mtk_irq_mailbox";
-
-static const struct irq_cascade_ops irq_ops = {
-	.mask = mtk_irq_mask,
-	.unmask = mtk_irq_unmask,
-};
-
-static const struct irq_cascade_tmpl dsp_irq[] = {
-	{
-		.name = mtk_irq_mailbox,
-		.irq = MTK_DSP_IRQ_MAILBOX,
-		.handler = irqhandler_2,
-		.ops = &irq_ops,
-		.global_mask = false,
-	},
-};
-
-int mtk_irq_group_id(uint32_t in_irq)
-{
-	if (in_irq >= MTK_MAX_IRQ_NUM)
-		in_irq -= MTK_MAX_IRQ_NUM;
-
-	return interrupt_get_irq(in_irq, dsp_irq[0].name);
-}
-
-void platform_interrupt_init(void)
-{
-	int i;
-
-	mtk_irq_init();
-	for (i = 0; i < ARRAY_SIZE(dsp_irq); i++)
-		interrupt_cascade_register(dsp_irq + i);
-}
-
-void platform_interrupt_set(uint32_t irq)
-{
-	if (interrupt_is_dsp_direct(irq))
-		arch_interrupt_set(irq);
-}
-
-void platform_interrupt_clear(uint32_t irq, uint32_t mask)
-{
-	if (interrupt_is_dsp_direct(irq))
-		arch_interrupt_clear(irq);
-}
-
-uint32_t platform_interrupt_get_enabled(void)
-{
-	return 0;
-}
-
-void interrupt_mask(uint32_t irq, unsigned int cpu)
-{
-	struct irq_cascade_desc *cascade = interrupt_get_parent(irq);
-
-	if (cascade && cascade->ops->mask)
-		cascade->ops->mask(&cascade->desc, irq - cascade->irq_base,
-				   cpu);
-	else
-		mtk_irq_mask(NULL, irq, 0);
-}
-
-void interrupt_unmask(uint32_t irq, unsigned int cpu)
-{
-	struct irq_cascade_desc *cascade = interrupt_get_parent(irq);
-
-	if (cascade && cascade->ops->unmask)
-		cascade->ops->unmask(&cascade->desc, irq - cascade->irq_base,
-				     cpu);
-	else
-		mtk_irq_unmask(NULL, irq, 0);
-}
diff --git a/src/drivers/mediatek/mt818x/ipc.c b/src/drivers/mediatek/mt818x/ipc.c
deleted file mode 100644
index e8a7ab3c22e5..000000000000
--- a/src/drivers/mediatek/mt818x/ipc.c
+++ /dev/null
@@ -1,196 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-/*
- * Copyright(c) 2022 MediaTek. All rights reserved.
- *
- * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
- *         Tinghan Shen <tinghan.shen@mediatek.com>
- */
-
-#include <rtos/panic.h>
-#include <rtos/interrupt.h>
-#include <sof/ipc/driver.h>
-#include <sof/ipc/msg.h>
-#include <sof/ipc/schedule.h>
-#include <rtos/alloc.h>
-#include <sof/lib/dma.h>
-#include <sof/lib/mailbox.h>
-#include <sof/lib/memory.h>
-#include <sof/lib/uuid.h>
-#include <rtos/wait.h>
-#include <sof/list.h>
-#include <sof/platform.h>
-#include <sof/schedule/edf_schedule.h>
-#include <sof/schedule/schedule.h>
-#include <rtos/task.h>
-#include <rtos/spinlock.h>
-#include <ipc/header.h>
-#include <ipc/topology.h>
-#include <ipc/trace.h>
-#include <platform/drivers/mt_reg_base.h>
-#include <errno.h>
-#include <stdbool.h>
-#include <stddef.h>
-#include <stdint.h>
-
-#define IPC_DSPMBOX_DSP_RSP 0
-#define IPC_DSPMBOX_DSP_REQ 1
-
-SOF_DEFINE_REG_UUID(ipc_task_mt818x);
-
-static struct ipc *local_ipc;
-
-struct ipc_data {
-	struct ipc_data_host_buffer dh_buffer;
-};
-
-static void mbox0_handler(void *args)
-{
-	uint32_t op = io_reg_read(MTK_ADSP_MBOX_IN_CMD(0));
-
-	/* clear interrupt */
-	io_reg_write(MTK_ADSP_MBOX_IN_CMD_CLR(0), op);
-	ipc_schedule_process(local_ipc);
-}
-
-static void mbox1_handler(void *args)
-{
-	uint32_t op = io_reg_read(MTK_ADSP_MBOX_IN_CMD(1));
-
-	/* clear interrupt */
-	io_reg_write(MTK_ADSP_MBOX_IN_CMD_CLR(1), op);
-	local_ipc->is_notification_pending = false;
-}
-
-void trigger_irq_to_host_rsp(void)
-{
-	io_reg_write(MTK_ADSP_MBOX_OUT_CMD(0), ADSP_IPI_OP_RSP);
-}
-
-void trigger_irq_to_host_req(void)
-{
-	io_reg_write(MTK_ADSP_MBOX_OUT_CMD(1), ADSP_IPI_OP_REQ);
-}
-
-enum task_state ipc_platform_do_cmd(struct ipc *ipc)
-{
-	struct ipc_cmd_hdr *hdr;
-
-	hdr = mailbox_validate();
-	ipc_cmd(hdr);
-
-	return SOF_TASK_STATE_COMPLETED;
-}
-
-void ipc_platform_complete_cmd(struct ipc *ipc)
-{
-	trigger_irq_to_host_rsp();
-	while (ipc->pm_prepare_D3)
-		wait_for_interrupt(0);
-}
-
-int ipc_platform_send_msg(const struct ipc_msg *msg)
-{
-	struct ipc *ipc = ipc_get();
-
-	if (ipc->is_notification_pending)
-		return -EBUSY;
-
-	/* now send the message */
-	mailbox_dspbox_write(0, msg->tx_data, msg->tx_size);
-
-	ipc->is_notification_pending = true;
-
-	/* now interrupt host to tell it we have sent a message */
-	trigger_irq_to_host_req();
-	return 0;
-}
-
-void ipc_platform_send_msg_direct(const struct ipc_msg *msg)
-{
-	/* TODO: add support */
-}
-
-#if CONFIG_HOST_PTABLE
-struct ipc_data_host_buffer *ipc_platform_get_host_buffer(struct ipc *ipc)
-{
-	struct ipc_data *iipc = ipc_get_drvdata(ipc);
-
-	return &iipc->dh_buffer;
-}
-#endif
-
-int platform_ipc_init(struct ipc *ipc)
-{
-	int mbox_irq0, mbox_irq1;
-	int ret;
-
-#if CONFIG_HOST_PTABLE
-	struct ipc_data *iipc;
-
-	iipc = rzalloc(SOF_MEM_FLAG_KERNEL, sizeof(*iipc));
-	if (!iipc) {
-		tr_err(&ipc_tr, "Unable to allocate memory for IPC data");
-		sof_panic(SOF_IPC_PANIC_IPC);
-	}
-	ipc_set_drvdata(ipc, iipc);
-#else
-	ipc_set_drvdata(ipc, NULL);
-#endif
-
-	local_ipc = ipc;
-
-	/* schedule */
-	schedule_task_init_edf(&ipc->ipc_task, SOF_UUID(ipc_task_mt818x_uuid),
-			       &ipc_task_ops, ipc, 0, 0);
-
-#if CONFIG_HOST_PTABLE
-	/* allocate page table buffer */
-	iipc->dh_buffer.page_table =
-		rzalloc(SOF_MEM_FLAG_KERNEL, PLATFORM_PAGE_TABLE_SIZE);
-	if (!iipc->dh_buffer.page_table) {
-		tr_err(&ipc_tr, "Unable to allocate host page table buffer");
-		sof_panic(SOF_IPC_PANIC_IPC);
-	}
-
-	iipc->dh_buffer.dmac = dma_get(DMA_DIR_HMEM_TO_LMEM, 0, DMA_DEV_HOST, DMA_ACCESS_SHARED);
-	if (!iipc->dh_buffer.dmac) {
-		tr_err(&ipc_tr, "Unable to find DMA for host page table");
-		sof_panic(SOF_IPC_PANIC_IPC);
-	}
-#endif
-
-	/*
-	 * AP req -- mbox0 --> DSP
-	 *    AP <-- mbox0 --  DSP rsp
-	 *    AP <-- mbox1 --  DSP req
-	 * AP rsp -- mbox1 --> DSP
-	 */
-	mbox_irq0 = mtk_irq_group_id(MTK_DSP_IRQ_MBOX0);
-	if (mbox_irq0 < 0) {
-		tr_err(&ipc_tr, "Invalid ipc mbox 0 IRQ:%d", mbox_irq0);
-		sof_panic(SOF_IPC_PANIC_IPC);
-	}
-
-	mbox_irq1 = mtk_irq_group_id(MTK_DSP_IRQ_MBOX1);
-	if (mbox_irq1 < 0) {
-		tr_err(&ipc_tr, "Invalid ipc mbox 1 IRQ:%d", mbox_irq1);
-		sof_panic(SOF_IPC_PANIC_IPC);
-	}
-
-	ret = interrupt_register(mbox_irq0, mbox0_handler, ipc);
-	if (ret < 0) {
-		tr_err(&ipc_tr, "Unable to register ipc mbox 0 IRQ");
-		sof_panic(SOF_IPC_PANIC_IPC);
-	}
-
-	ret = interrupt_register(mbox_irq1, mbox1_handler, ipc);
-	if (ret < 0) {
-		tr_err(&ipc_tr, "Unable to register ipc mbox 1 IRQ");
-		sof_panic(SOF_IPC_PANIC_IPC);
-	}
-
-	interrupt_enable(mbox_irq0, ipc);
-	interrupt_enable(mbox_irq1, ipc);
-
-	return 0;
-}
diff --git a/src/drivers/mediatek/mt818x/timer.c b/src/drivers/mediatek/mt818x/timer.c
deleted file mode 100644
index 564708d2cdc3..000000000000
--- a/src/drivers/mediatek/mt818x/timer.c
+++ /dev/null
@@ -1,213 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-/*
- * Copyright(c) 2022 MediaTek. All rights reserved.
- *
- * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
- *         Tinghan Shen <tinghan.shen@mediatek.com>
- */
-
-#include <sof/audio/component_ext.h>
-#include <rtos/interrupt.h>
-#include <sof/lib/memory.h>
-#include <sof/platform.h>
-#include <platform/drivers/timer.h>
-#include <ipc/stream.h>
-#include <errno.h>
-#include <stdint.h>
-
-void platform_timer_start(struct timer *timer)
-{
-	/* set 26m clksrc */
-	io_reg_update_bits(MTK_TIMER_CON(timer->id), MTK_TIMER_ENABLE_BIT, 0);
-	io_reg_update_bits(MTK_TIMER_CON(timer->id), MTK_TIMER_CLKSRC_BIT,
-			   MTK_TIMER_CLK_SRC_CLK_26M);
-
-	/* enable timer */
-	io_reg_update_bits(MTK_TIMER_CON(timer->id), MTK_TIMER_ENABLE_BIT,
-			   MTK_TIMER_ENABLE_BIT);
-
-	/* enable system boot time timer */
-	io_reg_update_bits(MTK_OSTIMER_CON, MTK_OSTIMER_EN_BIT,
-			   MTK_OSTIMER_EN_BIT);
-}
-
-void platform_timer_stop(struct timer *timer)
-{
-	if (timer->id > NR_TMRS)
-		return;
-
-	io_reg_update_bits(MTK_TIMER_CON(timer->id), MTK_TIMER_ENABLE_BIT, 0);
-	io_reg_update_bits(MTK_TIMER_IRQ_ACK(timer->id), MTK_TIMER_IRQ_ENABLE, 0);
-}
-
-/* IRQs off in arch_timer_get_system() */
-uint64_t platform_timer_get_atomic(struct timer *timer)
-{
-	return platform_timer_get(timer);
-}
-
-int64_t platform_timer_set(struct timer *timer, uint64_t ticks)
-{
-	uint64_t time;
-	uint32_t flags;
-	uint32_t low, high;
-	uint32_t ticks_set;
-
-	if (timer->id > NR_TMRS)
-		return -EINVAL;
-
-	flags = arch_interrupt_global_disable();
-
-	low = io_reg_read(MTK_OSTIMER_CUR_L);
-	high = io_reg_read(MTK_OSTIMER_CUR_H);
-
-	/* ostimer 13M counter to 26M interrupt */
-	time = (((uint64_t)high << 32) | low) << 1;
-
-	ticks_set = (ticks > time) ? ticks - time : UINT64_MAX - time +  ticks;
-
-	timer->hitimeout = ticks >> 32;
-	timer->lowtimeout = ticks_set;
-
-	/* disable timer before config it */
-	io_reg_update_bits(MTK_TIMER_CON(timer->id), MTK_TIMER_ENABLE_BIT, 0);
-
-	/* timer reset value */
-	io_reg_write(MTK_TIMER_RST_VAL(timer->id), ticks_set);
-
-	/* clear and enable irq */
-	io_reg_update_bits(MTK_TIMER_IRQ_ACK(timer->id), MTK_TIMER_IRQ_CLEAR,
-			   MTK_TIMER_IRQ_CLEAR);
-	io_reg_update_bits(MTK_TIMER_IRQ_ACK(timer->id), MTK_TIMER_IRQ_ENABLE,
-			   MTK_TIMER_IRQ_ENABLE);
-
-	/* enable timer */
-	io_reg_update_bits(MTK_TIMER_CON(timer->id), MTK_TIMER_ENABLE_BIT,
-			   MTK_TIMER_ENABLE_BIT);
-
-	arch_interrupt_global_enable(flags);
-
-	return ticks;
-}
-
-void platform_timer_clear(struct timer *timer)
-{
-	if (timer->id > NR_TMRS)
-		return;
-
-	io_reg_update_bits(MTK_TIMER_IRQ_ACK(timer->id), MTK_TIMER_IRQ_CLEAR,
-			   MTK_TIMER_IRQ_CLEAR);
-}
-
-uint64_t platform_timer_get(struct timer *timer)
-{
-	uint64_t time;
-	uint32_t low;
-	uint32_t high0;
-	uint32_t high1;
-
-	if (timer->id > NR_TMRS)
-		return -EINVAL;
-
-	/* 64bit reads are non atomic on xtensa so we must
-	 * read a stable value where there is no bit 32 flipping.
-	 */
-	do {
-		high0 = io_reg_read(MTK_OSTIMER_CUR_H);
-		low = io_reg_read(MTK_OSTIMER_CUR_L);
-		high1 = io_reg_read(MTK_OSTIMER_CUR_H);
-
-		/* worst case is we perform this twice so 6 * 32b clock reads */
-	} while (high0 != high1);
-
-	/* convert 13M ostimer counter value to 26M */
-	time = (((uint64_t)high0 << 32) | low) << 1;
-
-	return time;
-}
-
-/* get timestamp for host stream DMA position */
-void platform_host_timestamp(struct comp_dev *host, struct sof_ipc_stream_posn *posn)
-{
-	int err;
-
-	/* get host position */
-	err = comp_position(host, posn);
-	if (err == 0)
-		posn->flags |= SOF_TIME_HOST_VALID | SOF_TIME_HOST_64;
-}
-
-/* get timestamp for DAI stream DMA position */
-void platform_dai_timestamp(struct comp_dev *dai,
-			    struct sof_ipc_stream_posn *posn)
-{
-	int err;
-
-	/* get DAI position */
-	err = comp_position(dai, posn);
-	if (err == 0)
-		posn->flags |= SOF_TIME_DAI_VALID;
-
-	posn->wallclock = timer_get_system(timer_get()) - posn->wallclock;
-	posn->flags |= SOF_TIME_WALL_VALID | SOF_TIME_WALL_64;
-}
-
-/* get current wallclock for componnent */
-void platform_dai_wallclock(struct comp_dev *dai, uint64_t *wallclock)
-{
-	*wallclock = platform_timer_get(timer_get());
-}
-
-static void platform_timer_handler(void *arg)
-{
-	struct timer *timer = arg;
-
-	io_reg_update_bits(MTK_TIMER_IRQ_ACK(timer->id), MTK_TIMER_IRQ_CLEAR,
-			   MTK_TIMER_IRQ_CLEAR);
-
-	io_reg_update_bits(MTK_TIMER_CON(timer->id), MTK_TIMER_ENABLE_BIT, 0);
-
-	io_reg_update_bits(MTK_TIMER_IRQ_ACK(timer->id), MTK_TIMER_IRQ_ENABLE, 0);
-
-	timer->handler(timer->data);
-}
-
-static int platform_timer_register(struct timer *timer, void (*handler)(void *arg), void *arg)
-{
-	timer->handler = handler;
-	timer->data = arg;
-	timer->hitime = 0;
-	timer->hitimeout = 0;
-
-	return interrupt_register(timer->irq, platform_timer_handler, timer);
-}
-
-int timer_register(struct timer *timer, void(*handler)(void *arg), void *arg)
-{
-	switch (timer->id) {
-	case OSTIMER0:
-	case OSTIMER1:
-	case OSTIMER2:
-	case OSTIMER3:
-		return platform_timer_register(timer, handler, arg);
-	default:
-		return -EINVAL;
-	}
-}
-
-void timer_unregister(struct timer *timer, void *arg)
-{
-	interrupt_unregister(timer->irq, arg);
-}
-
-void timer_enable(struct timer *timer, void *arg, int core)
-{
-	interrupt_unmask(timer->irq, cpu_get_id());
-	interrupt_enable(timer->irq, arg);
-}
-
-void timer_disable(struct timer *timer, void *arg, int core)
-{
-	interrupt_disable(timer->irq, arg);
-	interrupt_mask(timer->irq, cpu_get_id());
-}
diff --git a/src/drivers/mediatek/mt8195/CMakeLists.txt b/src/drivers/mediatek/mt8195/CMakeLists.txt
deleted file mode 100644
index 0c8e351f06b5..000000000000
--- a/src/drivers/mediatek/mt8195/CMakeLists.txt
+++ /dev/null
@@ -1,4 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-
-add_local_sources(sof ipc.c timer.c interrupt.c)
-
diff --git a/src/drivers/mediatek/mt8195/interrupt.c b/src/drivers/mediatek/mt8195/interrupt.c
deleted file mode 100644
index f05ebe4492c9..000000000000
--- a/src/drivers/mediatek/mt8195/interrupt.c
+++ /dev/null
@@ -1,267 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-/*
- * Copyright(c) 2021 MediaTek. All rights reserved.
- *
- * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
- */
-
-#include <sof/common.h>
-#include <rtos/bit.h>
-#include <rtos/interrupt.h>
-#include <sof/lib/cpu.h>
-#include <sof/lib/io.h>
-#include <sof/lib/memory.h>
-#include <sof/lib/uuid.h>
-#include <sof/list.h>
-#include <rtos/spinlock.h>
-#include <errno.h>
-#include <inttypes.h>
-#include <stdbool.h>
-#include <stddef.h>
-#include <stdint.h>
-
-SOF_DEFINE_REG_UUID(interrupt);
-
-/* unused with Zephyr, generates no output */
-DECLARE_TR_CTX(int_tr, SOF_UUID(interrupt_uuid), LOG_LEVEL_INFO);
-
-/* os timer reg value * 77ns 13M os timer
- * 1  ms: 12987* 1.5ms: 19436
- * 2  ms: 25974* 3  ms: 38961
- */
-
-static void irq_mask_all(void)
-{
-	io_reg_update_bits(RG_DSP_IRQ_EN, 0xffffffff, 0x0);
-	io_reg_update_bits(DSP_IRQ_EN, 0xffffffff, 0x0);
-}
-
-static void mtk_irq_mask(struct irq_desc *desc, uint32_t irq, unsigned int core)
-{
-	int32_t in_irq, level;
-
-	if (!desc) {
-		level = GET_INTLEVEL(irq);
-		in_irq = GET_INTERRUPT_ID(irq);
-		if (level > MAX_IRQ_NUM) {
-			tr_err(&int_tr, "Invalid interrupt %d", irq);
-			return;
-		}
-
-		io_reg_update_bits(RG_DSP_IRQ_EN, BIT(in_irq), 0x0);
-	} else {
-		switch (desc->irq) {
-		case IRQ_EXT_DOMAIN0:
-			io_reg_update_bits(RG_DSP_IRQ_EN, BIT(irq + IRQ_EXT_DOMAIN0_OFFSET), 0x0);
-			break;
-		case IRQ_EXT_DOMAIN1:
-			io_reg_update_bits(DSP_IRQ_EN, BIT(irq), 0x0);
-			break;
-		default:
-			tr_err(&int_tr, "Invalid interrupt %d", desc->irq);
-			return;
-		}
-	}
-}
-
-static void mtk_irq_unmask(struct irq_desc *desc, uint32_t irq, unsigned int core)
-{
-	int32_t in_irq, level;
-
-	if (!desc) {
-		level = GET_INTLEVEL(irq);
-		in_irq = GET_INTERRUPT_ID(irq);
-		if (level > MAX_IRQ_NUM) {
-			tr_err(&int_tr, "Invalid interrupt %d", irq);
-			return;
-		}
-
-		io_reg_update_bits(RG_DSP_IRQ_EN, BIT(in_irq), BIT(in_irq));
-	} else {
-		switch (desc->irq) {
-		case IRQ_EXT_DOMAIN0:
-			io_reg_update_bits(RG_DSP_IRQ_EN, BIT(irq + IRQ_EXT_DOMAIN0_OFFSET),
-					   BIT(irq + IRQ_EXT_DOMAIN0_OFFSET));
-			break;
-		case IRQ_EXT_DOMAIN1:
-			io_reg_update_bits(DSP_IRQ_EN, BIT(irq), BIT(irq));
-			break;
-		default:
-			tr_err(&int_tr, "Invalid interrupt %d", desc->irq);
-			return;
-		}
-	}
-}
-
-static uint64_t mtk_get_irq_interrupts(uint32_t irq)
-{
-	uint32_t irq_status;
-
-	switch (irq) {
-	case IRQ_NUM_EXT_LEVEL23:
-		irq_status = io_reg_read(DSP_IRQ_STATUS);
-		irq_status &= IRQ_EXT_DOMAIN2_MASK;
-		break;
-	default:
-		irq_status = io_reg_read(RG_DSP_IRQ_STATUS);
-		irq_status &= IRQ_EXT_DOMAIN1_MASK;
-		break;
-	}
-	return irq_status;
-}
-
-static int get_first_irq(uint64_t ints)
-{
-	return ffs(ints) - 1;
-}
-
-static inline void mtk_handle_irq(struct irq_cascade_desc *cascade,
-				  uint32_t line_index, uint64_t status)
-{
-	int core = cpu_get_id();
-	struct list_item *clist;
-	struct irq_desc *child = NULL;
-	k_spinlock_key_t key;
-	int bit;
-	bool handled;
-
-	while (status) {
-		bit = get_first_irq(status);
-		handled = false;
-		status &= ~(1ull << bit);
-
-		key = k_spin_lock(&cascade->lock);
-
-		list_for_item(clist, &cascade->child[bit].list) {
-			child = container_of(clist, struct irq_desc, irq_list);
-
-			if (child->handler && (child->cpu_mask & 1 << core)) {
-				child->handler(child->handler_arg);
-				handled = true;
-			}
-		}
-
-		k_spin_unlock(&cascade->lock, key);
-
-		if (!handled) {
-			tr_err(&int_tr, "irq_handler(): not handled, bit %d", bit);
-			if (line_index == IRQ_NUM_EXT_LEVEL23)
-				io_reg_update_bits(DSP_IRQ_EN, BIT(bit), 0x0);
-			else
-				io_reg_update_bits(RG_DSP_IRQ_EN, BIT(bit), 0x0);
-		}
-	}
-}
-
-static inline void irq_handler(void *data, uint32_t line_index)
-{
-	struct irq_desc *parent = data;
-	struct irq_cascade_desc *cascade =
-		container_of(parent, struct irq_cascade_desc, desc);
-	uint64_t status;
-
-	status = mtk_get_irq_interrupts(line_index);
-
-	if (status)
-		/* Handle current interrupts */
-		mtk_handle_irq(cascade, line_index, status);
-	else
-		tr_err(&int_tr, "invalid interrupt status");
-}
-
-#define DEFINE_IRQ_HANDLER(n) \
-	static void irqhandler_##n(void *arg) \
-	{ \
-		irq_handler(arg, n); \
-	}
-
-DEFINE_IRQ_HANDLER(1)
-DEFINE_IRQ_HANDLER(23)
-
-static const char mtk_irq_ext_domain0[] = "mtk_irq_ext_domain0";
-static const char mtk_irq_ext_domain1[] = "mtk_irq_ext_domain1";
-
-static const struct irq_cascade_ops irq_ops = {
-	.mask = mtk_irq_mask,
-	.unmask = mtk_irq_unmask,
-};
-
-static const struct irq_cascade_tmpl dsp_irq[] = {
-	{
-		.name = mtk_irq_ext_domain0,
-		.irq = IRQ_NUM_EXT_LEVEL01,
-		.handler = irqhandler_1,
-		.ops = &irq_ops,
-		.global_mask = false,
-	},
-	{
-		.name = mtk_irq_ext_domain1,
-		.irq = IRQ_NUM_EXT_LEVEL23,
-		.handler = irqhandler_23,
-		.ops = &irq_ops,
-		.global_mask = false,
-	},
-};
-
-uint32_t mtk_get_irq_domain_id(int32_t irq)
-{
-	uint32_t in_irq = GET_INTERRUPT_ID(irq);
-	int32_t level = GET_INTLEVEL(irq);
-
-	if (in_irq >= DOMAIN1_MAX_IRQ_NUM)
-		in_irq -= DOMAIN1_MAX_IRQ_NUM;
-
-	if (level == IRQ_EXT_DOMAIN0)
-		return interrupt_get_irq(in_irq, dsp_irq[0].name);
-	else
-		return interrupt_get_irq(in_irq, dsp_irq[1].name);
-}
-
-void platform_interrupt_init(void)
-{
-	int i;
-
-	irq_mask_all();
-
-	for (i = 0; i < ARRAY_SIZE(dsp_irq); i++)
-		interrupt_cascade_register(dsp_irq + i);
-}
-
-void platform_interrupt_set(uint32_t irq)
-{
-	if (interrupt_is_dsp_direct(irq))
-		arch_interrupt_set(irq);
-}
-
-void platform_interrupt_clear(uint32_t irq, uint32_t mask)
-{
-	if (interrupt_is_dsp_direct(irq))
-		arch_interrupt_clear(irq);
-}
-
-uint32_t platform_interrupt_get_enabled(void)
-{
-	return 0;
-}
-
-void interrupt_mask(uint32_t irq, unsigned int cpu)
-{
-	struct irq_cascade_desc *cascade = interrupt_get_parent(irq);
-
-	if (cascade && cascade->ops->mask)
-		cascade->ops->mask(&cascade->desc, irq - cascade->irq_base,
-				   cpu);
-	else
-		mtk_irq_mask(NULL, irq, 0);
-}
-
-void interrupt_unmask(uint32_t irq, unsigned int cpu)
-{
-	struct irq_cascade_desc *cascade = interrupt_get_parent(irq);
-
-	if (cascade && cascade->ops->unmask)
-		cascade->ops->unmask(&cascade->desc, irq - cascade->irq_base,
-				     cpu);
-	else
-		mtk_irq_unmask(NULL, irq, 0);
-}
diff --git a/src/drivers/mediatek/mt8195/ipc.c b/src/drivers/mediatek/mt8195/ipc.c
deleted file mode 100644
index cb3734d0fbc3..000000000000
--- a/src/drivers/mediatek/mt8195/ipc.c
+++ /dev/null
@@ -1,168 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-/*
- * Copyright(c) 2021 MediaTek. All rights reserved.
- *
- * Author: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
- */
-
-#include <rtos/panic.h>
-#include <rtos/interrupt.h>
-#include <sof/ipc/driver.h>
-#include <sof/ipc/msg.h>
-#include <sof/ipc/schedule.h>
-#include <rtos/alloc.h>
-#include <sof/lib/dma.h>
-#include <sof/lib/mailbox.h>
-#include <sof/lib/memory.h>
-#include <sof/lib/uuid.h>
-#include <rtos/wait.h>
-#include <sof/list.h>
-#include <sof/platform.h>
-#include <sof/schedule/edf_schedule.h>
-#include <sof/schedule/schedule.h>
-#include <rtos/task.h>
-#include <rtos/spinlock.h>
-#include <ipc/header.h>
-#include <ipc/topology.h>
-#include <ipc/trace.h>
-#include <platform/drivers/mt_reg_base.h>
-#include <errno.h>
-#include <stdbool.h>
-#include <stddef.h>
-#include <stdint.h>
-
-#define IPC_DSPMBOX_DSP_RSP 0
-#define IPC_DSPMBOX_DSP_REQ 1
-
-SOF_DEFINE_REG_UUID(ipc_task);
-
-static struct ipc *local_ipc;
-
-struct ipc_data {
-	struct ipc_data_host_buffer dh_buffer;
-};
-
-static void mbox0_handler(void *args)
-{
-	uint32_t op = io_reg_read(MTK_DSP_MBOX_IN_CMD(0));
-
-	/* clear interrupt */
-	io_reg_write(MTK_DSP_MBOX_IN_CMD_CLR(0), op);
-	ipc_schedule_process(local_ipc);
-}
-
-static void mbox1_handler(void *args)
-{
-	uint32_t op = io_reg_read(MTK_DSP_MBOX_IN_CMD(1));
-
-	/* clear interrupt */
-	io_reg_write(MTK_DSP_MBOX_IN_CMD_CLR(1), op);
-	local_ipc->is_notification_pending = false;
-}
-
-void trigger_irq_to_host_rsp(void)
-{
-	io_reg_write(MTK_DSP_MBOX_OUT_CMD(0), ADSP_IPI_OP_RSP);
-}
-
-void trigger_irq_to_host_req(void)
-{
-	io_reg_write(MTK_DSP_MBOX_OUT_CMD(1), ADSP_IPI_OP_REQ);
-}
-
-enum task_state ipc_platform_do_cmd(struct ipc *ipc)
-{
-	struct ipc_cmd_hdr *hdr;
-
-	hdr = mailbox_validate();
-	ipc_cmd(hdr);
-
-	return SOF_TASK_STATE_COMPLETED;
-}
-
-void ipc_platform_complete_cmd(struct ipc *ipc)
-{
-	trigger_irq_to_host_rsp();
-	while (ipc->pm_prepare_D3) {
-		clock_set_freq(CLK_CPU(cpu_get_id()), CLK_SUSPEND_CPU_HZ);
-		asm volatile("waiti 15");
-	}
-}
-
-int ipc_platform_send_msg(const struct ipc_msg *msg)
-{
-	struct ipc *ipc = ipc_get();
-
-	if (ipc->is_notification_pending)
-		return -EBUSY;
-
-	/* now send the message */
-	mailbox_dspbox_write(0, msg->tx_data, msg->tx_size);
-
-	ipc->is_notification_pending = true;
-
-	/* now interrupt host to tell it we have sent a message */
-	trigger_irq_to_host_req();
-	return 0;
-}
-
-void ipc_platform_send_msg_direct(const struct ipc_msg *msg)
-{
-	/* TODO: add support */
-}
-
-#if CONFIG_HOST_PTABLE
-struct ipc_data_host_buffer *ipc_platform_get_host_buffer(struct ipc *ipc)
-{
-	struct ipc_data *iipc = ipc_get_drvdata(ipc);
-
-	return &iipc->dh_buffer;
-}
-#endif
-
-int platform_ipc_init(struct ipc *ipc)
-{
-	uint32_t mbox_irq0, mbox_irq1;
-#if CONFIG_HOST_PTABLE
-	struct ipc_data *iipc;
-
-	iipc = rzalloc(SOF_MEM_FLAG_KERNEL, sizeof(*iipc));
-	if (!iipc) {
-		tr_err(&ipc_tr, "Unable to allocate memory for IPC data");
-		sof_panic(SOF_IPC_PANIC_IPC);
-	}
-	ipc_set_drvdata(ipc, iipc);
-#else
-	ipc_set_drvdata(ipc, NULL);
-#endif
-
-	local_ipc = ipc;
-
-	/* schedule */
-	schedule_task_init_edf(&ipc->ipc_task, SOF_UUID(ipc_task_uuid), &ipc_task_ops, ipc, 0, 0);
-
-#if CONFIG_HOST_PTABLE
-	/* allocate page table buffer */
-	iipc->dh_buffer.page_table =
-		rzalloc(SOF_MEM_FLAG_KERNEL, PLATFORM_PAGE_TABLE_SIZE);
-	if (!iipc->dh_buffer.page_table) {
-		tr_err(&ipc_tr, "Unable to allocate host page table buffer");
-		sof_panic(SOF_IPC_PANIC_IPC);
-	}
-
-	iipc->dh_buffer.dmac = dma_get(DMA_DIR_HMEM_TO_LMEM, 0, DMA_DEV_HOST, DMA_ACCESS_SHARED);
-	if (!iipc->dh_buffer.dmac) {
-		tr_err(&ipc_tr, "Unable to find DMA for host page table");
-		sof_panic(SOF_IPC_PANIC_IPC);
-	}
-#endif
-
-	mbox_irq0 = mtk_get_irq_domain_id(LX_MBOX_IRQ0_B);
-	mbox_irq1 = mtk_get_irq_domain_id(LX_MBOX_IRQ1_B);
-	interrupt_register(mbox_irq0, mbox0_handler, ipc);
-	interrupt_register(mbox_irq1, mbox1_handler, ipc);
-	interrupt_enable(mbox_irq0, ipc);
-	interrupt_enable(mbox_irq1, ipc);
-
-	return 0;
-}
diff --git a/src/drivers/mediatek/mt8195/timer.c b/src/drivers/mediatek/mt8195/timer.c
deleted file mode 100644
index 06ceafe7bb80..000000000000
--- a/src/drivers/mediatek/mt8195/timer.c
+++ /dev/null
@@ -1,205 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-/*
- * Copyright(c) 2021 MediaTek. All rights reserved.
- *
- * Author:Fengquan Chen <fengquan.chen@mediatek.com>
- *        Allen-KH Cheng <allen-kh.cheng@mediatek.com>
- */
-
-#include <sof/audio/component_ext.h>
-#include <rtos/interrupt.h>
-#include <sof/lib/memory.h>
-#include <sof/platform.h>
-#include <platform/drivers/timer.h>
-#include <ipc/stream.h>
-#include <errno.h>
-#include <stdint.h>
-
-void platform_timer_start(struct timer *timer)
-{
-	/*set 13M clksrc*/
-	io_reg_update_bits(CNTCR, CLKSRC_BIT, 0x0);
-	io_reg_update_bits(CNTCR, CLKSRC_13M_BIT, CLKSRC_13M_BIT);
-
-	/*enable timer*/
-	io_reg_update_bits(CNTCR, CNT_EN_BIT, CNT_EN_BIT);
-}
-
-void platform_timer_stop(struct timer *timer)
-{
-	if (timer->id > NR_TMRS)
-		return;
-
-	io_reg_update_bits(TIMER_CON(timer->id), TIMER_ENABLE_BIT, 0x0);
-	io_reg_update_bits(TIMER_IRQ_ACK(timer->id), TIMER_IRQ_ENABLE, 0x0);
-}
-
-/* IRQs off in arch_timer_get_system() */
-uint64_t platform_timer_get_atomic(struct timer *timer)
-{
-	return platform_timer_get(timer);
-}
-
-int64_t platform_timer_set(struct timer *timer, uint64_t ticks)
-{
-	uint64_t time;
-	uint32_t flags;
-	uint32_t low, high;
-	uint32_t ticks_set;
-
-	if (timer->id > NR_TMRS)
-		return -EINVAL;
-
-	flags = arch_interrupt_global_disable();
-
-	low = io_reg_read(OSTIMER_CUR_L);
-	high = io_reg_read(OSTIMER_CUR_H);
-
-	/*ostimer 13M counter to 26M interrupt */
-	time = (((uint64_t)high << 32) | low) << 1;
-	ticks_set = (ticks > time) ? ticks - time : UINT64_MAX - time +  ticks;
-	timer->hitimeout = ticks >> 32;
-	timer->lowtimeout = ticks_set;
-
-	/*selsect 26M clksrc*/
-	io_reg_update_bits(TIMER_CON(timer->id), TIMER_CLKSRC_BIT, 0x0);
-	io_reg_update_bits(TIMER_CON(timer->id),
-			   TIMER_CLK_SRC_CLK_26M << TIMER_CLK_SRC_SHIFT,
-			   TIMER_CLK_SRC_CLK_26M << TIMER_CLK_SRC_SHIFT);
-
-	io_reg_write(TIMER_RST_VAL(timer->id), ticks_set);
-	io_reg_update_bits(TIMER_IRQ_ACK(timer->id), TIMER_IRQ_CLEAR, TIMER_IRQ_CLEAR);
-	io_reg_update_bits(TIMER_IRQ_ACK(timer->id), TIMER_IRQ_ENABLE, TIMER_IRQ_ENABLE);
-	io_reg_update_bits(TIMER_CON(timer->id), TIMER_ENABLE_BIT, TIMER_ENABLE_BIT);
-
-	arch_interrupt_global_enable(flags);
-
-	return ticks;
-}
-
-void platform_timer_clear(struct timer *timer)
-{
-	if (timer->id > NR_TMRS)
-		return;
-
-	io_reg_update_bits(TIMER_IRQ_ACK(timer->id), TIMER_IRQ_CLEAR, TIMER_IRQ_CLEAR);
-}
-
-uint64_t platform_timer_get(struct timer *timer)
-{
-	uint64_t time;
-	uint32_t low;
-	uint32_t high0;
-	uint32_t high1;
-
-	if (timer->id > NR_TMRS)
-		return -EINVAL;
-
-	/* 64bit reads are non atomic on xtensa so we must
-	 * read a stable value where there is no bit 32 flipping.
-	 */
-	do {
-		high0 = io_reg_read(OSTIMER_CUR_H);
-		low = io_reg_read(OSTIMER_CUR_L);
-		high1 = io_reg_read(OSTIMER_CUR_H);
-
-		/* worst case is we perform this twice so 6 * 32b clock reads */
-	} while (high0 != high1);
-
-	/*ostimer 13M counter to 26M interrupt */
-	time = (((uint64_t)high0 << 32) | low) << 1;
-
-	return time;
-}
-
-/* get timestamp for host stream DMA position */
-void platform_host_timestamp(struct comp_dev *host,
-			     struct sof_ipc_stream_posn *posn)
-{
-	int err;
-
-	/* get host position */
-	err = comp_position(host, posn);
-	if (err == 0)
-		posn->flags |= SOF_TIME_HOST_VALID | SOF_TIME_HOST_64;
-}
-
-/* get timestamp for DAI stream DMA position */
-void platform_dai_timestamp(struct comp_dev *dai,
-			    struct sof_ipc_stream_posn *posn)
-{
-	int err;
-
-	/* get DAI position */
-	err = comp_position(dai, posn);
-	if (err == 0)
-		posn->flags |= SOF_TIME_DAI_VALID;
-
-	posn->wallclock = timer_get_system(timer_get()) - posn->wallclock;
-	posn->flags |= SOF_TIME_WALL_VALID | SOF_TIME_WALL_64;
-}
-
-/* get current wallclock for componnent */
-void platform_dai_wallclock(struct comp_dev *dai, uint64_t *wallclock)
-{
-	*wallclock = platform_timer_get(timer_get());
-}
-
-static void platform_timer_handler(void *arg)
-{
-	struct timer *timer = arg;
-
-	io_reg_update_bits(TIMER_IRQ_ACK(timer->id), TIMER_IRQ_CLEAR, TIMER_IRQ_CLEAR);
-	io_reg_update_bits(TIMER_CON(timer->id), TIMER_ENABLE_BIT, 0x0);
-	io_reg_update_bits(TIMER_IRQ_ACK(timer->id), TIMER_IRQ_ENABLE, 0x0);
-	timer->handler(timer->data);
-}
-
-static int platform_timer_register(struct timer *timer, void (*handler)(void *arg), void *arg)
-{
-	uint32_t timer_irq0;
-	int err;
-
-	timer->handler = handler;
-	timer->data = arg;
-	timer->hitime = 0;
-	timer->hitimeout = 0;
-
-	timer_irq0 = mtk_get_irq_domain_id(timer->irq);
-	err = interrupt_register(timer_irq0, platform_timer_handler, timer);
-	if (err < 0)
-		return err;
-
-	/* enable timer interrupt */
-	interrupt_enable(timer_irq0, timer);
-
-	return err;
-}
-
-int timer_register(struct timer *timer, void(*handler)(void *arg), void *arg)
-{
-	switch (timer->id) {
-	case OSTIMER0:
-	case OSTIMER1:
-	case OSTIMER2:
-	case OSTIMER3:
-		return platform_timer_register(timer, handler, arg);
-	default:
-		return -EINVAL;
-	}
-}
-
-void timer_unregister(struct timer *timer, void *arg)
-{
-	interrupt_unregister(timer->irq, arg);
-}
-
-void timer_enable(struct timer *timer, void *arg, int core)
-{
-	interrupt_enable(timer->irq, arg);
-}
-
-void timer_disable(struct timer *timer, void *arg, int core)
-{
-	interrupt_disable(timer->irq, arg);
-}
diff --git a/src/drivers/mediatek/mt8196/CMakeLists.txt b/src/drivers/mediatek/mt8196/CMakeLists.txt
deleted file mode 100644
index 0d5d85f72215..000000000000
--- a/src/drivers/mediatek/mt8196/CMakeLists.txt
+++ /dev/null
@@ -1,4 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-
-add_local_sources(sof interrupt.c intc.c intc_map.c ipc.c timer.c)
-
diff --git a/src/drivers/mediatek/mt8196/intc.c b/src/drivers/mediatek/mt8196/intc.c
deleted file mode 100644
index 32b34bdcc9ea..000000000000
--- a/src/drivers/mediatek/mt8196/intc.c
+++ /dev/null
@@ -1,133 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-/*
- * Copyright(c) 2024 MediaTek. All rights reserved.
- *
- * Author: Hailong Fan <hailong.fan@mediatek.com>
- */
-
-#include <rtos/interrupt.h>
-#include <sof/lib/memory.h>
-#include <sof/platform.h>
-#include <sof/lib/uuid.h>
-#include <platform/drivers/interrupt.h>
-#include <platform/drivers/intc.h>
-#include <errno.h>
-#include <stdint.h>
-
-SOF_DEFINE_REG_UUID(intc_mt8196);
-/* unused with Zephyr, generates no output */
-DECLARE_TR_CTX(intc_tr, SOF_UUID(intc_mt8196_uuid), LOG_LEVEL_INFO);
-
-static struct intc_desc_t intc_desc;
-
-void intc_init(void)
-{
-	uint32_t word, group, irq;
-
-	for (group = 0; group < INTC_GRP_NUM; group++) {
-		for (word = 0; word < INTC_GRP_LEN; word++)
-			intc_desc.grp_irqs[group][word] = 0x0;
-	}
-
-	for (word = 0; word < INTC_GRP_LEN; word++)
-		intc_desc.int_en[word] = 0x0;
-
-	for (irq = 0; irq < IRQ_MAX_CHANNEL; irq++) {
-		intc_desc.irqs[irq].id = irq;
-		intc_desc.irqs[irq].group = irq2grp_map[irq];
-		intc_desc.irqs[irq].pol = INTC_POL_LOW;
-	}
-
-	for (word = 0; word < INTC_GRP_LEN; word++) {
-		io_reg_write(INTC_IRQ_EN(word), 0x0);
-		io_reg_write(INTC_IRQ_WAKE_EN(word), 0x0);
-		io_reg_write(INTC_IRQ_STAGE1_EN(word), 0x0);
-		io_reg_write(INTC_IRQ_POL(word), 0xFFFFFFFF);
-	}
-
-	for (group = 0; group < INTC_GRP_NUM; group++) {
-		for (word = 0; word < INTC_GRP_LEN; word++)
-			io_reg_write(INTC_IRQ_GRP(group, word), 0x0);
-	}
-}
-
-void intc_irq_unmask(enum IRQn_Type irq)
-{
-	uint32_t word;
-
-	if (irq < IRQ_MAX_CHANNEL && intc_desc.irqs[irq].group < INTC_GRP_NUM) {
-		word = INTC_WORD(irq);
-		io_reg_update_bits(INTC_IRQ_EN(word), INTC_BIT(irq), INTC_BIT(irq));
-	} else {
-		tr_err(&intc_tr, "Invalid INTC interrupt %d", irq);
-	}
-}
-
-void intc_irq_mask(enum IRQn_Type irq)
-{
-	uint32_t word;
-
-	if (irq < IRQ_MAX_CHANNEL) {
-		word = INTC_WORD(irq);
-		io_reg_update_bits(INTC_IRQ_EN(word), INTC_BIT(irq), 0);
-	} else {
-		tr_err(&intc_tr, "Invalid INTC interrupt %d", irq);
-	}
-}
-
-int intc_irq_enable(enum IRQn_Type irq)
-{
-	uint32_t word, irq_b, group, pol;
-	int ret;
-
-	if (irq < IRQ_MAX_CHANNEL && intc_desc.irqs[irq].group < INTC_GRP_NUM &&
-	    intc_desc.irqs[irq].pol < INTC_POL_NUM) {
-		word = INTC_WORD(irq);
-		irq_b = INTC_BIT(irq);
-		group = intc_desc.irqs[irq].group;
-		pol = intc_desc.irqs[irq].pol;
-
-		intc_desc.int_en[word] |= irq_b;
-		intc_desc.grp_irqs[group][word] |= irq_b;
-		io_reg_update_bits(INTC_IRQ_EN(word), irq_b, 0);
-		if (pol == INTC_POL_HIGH)
-			io_reg_update_bits(INTC_IRQ_POL(word), irq_b, 0);
-		else
-			io_reg_update_bits(INTC_IRQ_POL(word), irq_b, irq_b);
-
-		io_reg_update_bits(INTC_IRQ_GRP(group, word), irq_b, irq_b);
-		io_reg_update_bits(INTC_IRQ_EN(word), irq_b, irq_b);
-
-		ret = 1;
-	} else {
-		tr_err(&intc_tr, "Invalid INTC interrupt %d", irq);
-		ret = 0;
-	}
-
-	return ret;
-}
-
-int intc_irq_disable(enum IRQn_Type irq)
-{
-	uint32_t word, irq_b, group;
-	int ret;
-
-	if (irq < IRQ_MAX_CHANNEL && intc_desc.irqs[irq].group < INTC_GRP_NUM) {
-		word = INTC_WORD(irq);
-		irq_b = INTC_BIT(irq);
-		group = intc_desc.irqs[irq].group;
-
-		intc_desc.int_en[word] &= ~irq_b;
-		intc_desc.grp_irqs[group][word] &= ~irq_b;
-		io_reg_update_bits(INTC_IRQ_EN(word), irq_b, 0);
-		io_reg_update_bits(INTC_IRQ_GRP(group, word), irq_b, 0);
-
-		ret = 1;
-	} else {
-		tr_err(&intc_tr, "INTC fail to disable irq %u\n", irq);
-		ret = 0;
-	}
-
-	return ret;
-}
-
diff --git a/src/drivers/mediatek/mt8196/intc_map.c b/src/drivers/mediatek/mt8196/intc_map.c
deleted file mode 100644
index 2c3fcbba965d..000000000000
--- a/src/drivers/mediatek/mt8196/intc_map.c
+++ /dev/null
@@ -1,104 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-/*
- * Copyright(c) 2024 MediaTek. All rights reserved.
- *
- * Author: Hailong Fan <hailong.fan@mediatek.com>
- */
-
-#include <sof/audio/component_ext.h>
-#include <rtos/interrupt.h>
-#include <sof/lib/memory.h>
-#include <sof/platform.h>
-#include <platform/drivers/timer.h>
-#include <platform/drivers/interrupt.h>
-#include <ipc/stream.h>
-#include <errno.h>
-#include <stdint.h>
-
-const unsigned char grp_pri[INTC_GRP_NUM] = {
-	INTC_GRP0_LEVEL, INTC_GRP1_LEVEL, INTC_GRP2_LEVEL, INTC_GRP3_LEVEL,
-	INTC_GRP4_LEVEL, INTC_GRP5_LEVEL, INTC_GRP6_LEVEL, INTC_GRP7_LEVEL,
-	INTC_GRP8_LEVEL, INTC_GRP9_LEVEL, INTC_GRP10_LEVEL, INTC_GRP11_LEVEL,
-	INTC_GRP12_LEVEL, INTC_GRP13_LEVEL, INTC_GRP14_LEVEL, INTC_GRP15_LEVEL,
-};
-
-const uint8_t irq2grp_map[IRQ_MAX_CHANNEL] = {
-	[CCU_IRQn]           = INTC_GRP1,
-	[SCP_IRQn]           = INTC_GRP1,
-	[SPM_IRQn]           = INTC_GRP1,
-	[PCIE_IRQn]          = INTC_GRP1,
-	[INFRA_HANG_IRQn]    = INTC_GRP1,
-	[PERI_TIMEOUT_IRQn]  = INTC_GRP1,
-	[MBOX_C0_IRQn]       = INTC_GRP2,
-	[MBOX_C1_IRQn]       = INTC_GRP2,
-	[TIMER0_IRQn]        = INTC_GRP1,
-	[TIMER1_IRQn]        = INTC_GRP1,
-	[IPC_C0_IRQn]        = INTC_GRP1,
-	[IPC_C1_IRQn]        = INTC_GRP1,
-	[IPC1_RSV_IRQn]      = INTC_GRP1,
-	[C2C_SW_C0_IRQn]     = INTC_GRP1,
-	[C2C_SW_C1_IRQn]     = INTC_GRP1,
-	[UART_IRQn]          = INTC_GRP12,
-	[UART_BT_IRQn]       = INTC_GRP12,
-	[LATENCY_MON_IRQn]   = INTC_GRP11,
-	[BUS_TRACKER_IRQn]   = INTC_GRP13,
-	[USB0_IRQn]          = INTC_GRP8,
-	[USB1_IRQn]          = INTC_GRP8,
-	[SCPVOW_IRQn]        = NO_GRP,
-	[CCIF3_C0_IRQn]      = INTC_GRP8,
-	[CCIF3_C1_IRQn]      = INTC_GRP8,
-	[PWR_CTRL_IRQn]      = NO_GRP,
-	[DMA_C0_IRQn]        = INTC_GRP10,
-	[DMA_C1_IRQn]        = NO_GRP,
-	[AXI_DMA0_IRQn]      = INTC_GRP9,
-	[AXI_DMA1_IRQn]      = NO_GRP,
-	[AUDIO_C0_IRQn]      = INTC_GRP10,
-	[AUDIO_C1_IRQn]      = INTC_GRP10,
-	[HIFI5_WDT_C0_IRQn]  = INTC_GRP13,
-	[HIFI5_WDT_C1_IRQn]  = INTC_GRP13,
-	[APU_MBOX_C0_IRQn]   = INTC_GRP0,
-	[APU_MBOX_C1_IRQn]   = INTC_GRP0,
-	[TIMER2_IRQn]        = INTC_GRP13,
-	[PWR_ON_C0_IRQ]      = INTC_GRP13,
-	[PWR_ON_C1_IRQ]      = INTC_GRP13,
-	[WAKEUP_SRC_C0_IRQn] = INTC_GRP13,
-	[WAKEUP_SRC_C1_IRQn] = INTC_GRP13,
-	[WDT_IRQn]           = NO_GRP,
-	[CONNSYS1_IRQn]      = INTC_GRP3,
-	[CONNSYS3_IRQn]      = INTC_GRP3,
-	[CONNSYS4_IRQn]      = INTC_GRP3,
-	[CONNSYS2_IRQn]      = INTC_GRP3,
-	[IPIC_IRQn]          = INTC_GRP1,
-	[AXI_DMA2_IRQn]      = INTC_GRP9,
-	[AXI_DMA3_IRQn]      = NO_GRP,
-	[APSRC_DDREN_IRQn]   = INTC_GRP4,
-	[LAT_MON_EMI_IRQn]   = INTC_GRP11,
-	[LAT_MON_INFRA_IRQn] = INTC_GRP11,
-	[DEVAPC_VIO_IRQn]    = INTC_GRP11,
-	[AO_INFRA_HANG_IRQn] = NO_GRP,
-	[BUS_TRA_EMI_IRQn]   = INTC_GRP13,
-	[BUS_TRA_INFRA_IRQn] = INTC_GRP13,
-	[L2SRAM_VIO_IRQn]    = INTC_GRP11,
-	[L2SRAM_SETERR_IRQn] = INTC_GRP11,
-	[PCIERC_GRP2_IRQn]   = INTC_GRP8,
-	[PCIERC_GRP3_IRQn]   = INTC_GRP8,
-};
-
-const uint8_t grp2hifi_irq_map[INTC_GRP_NUM] = {
-	[INTC_GRP0]  = 0,
-	[INTC_GRP1]  = 1,
-	[INTC_GRP2]  = 2,
-	[INTC_GRP3]  = 3,
-	[INTC_GRP4]  = 4,
-	[INTC_GRP5]  = 5,
-	[INTC_GRP6]  = 7,
-	[INTC_GRP7]  = 8,
-	[INTC_GRP8]  = 9,
-	[INTC_GRP9]  = 10,
-	[INTC_GRP10] = 11,
-	[INTC_GRP11] = 16,
-	[INTC_GRP12] = 17,
-	[INTC_GRP13] = 18,
-	[INTC_GRP14] = 20,
-	[INTC_GRP15] = 21,
-};
diff --git a/src/drivers/mediatek/mt8196/interrupt.c b/src/drivers/mediatek/mt8196/interrupt.c
deleted file mode 100644
index 08dafb5efad2..000000000000
--- a/src/drivers/mediatek/mt8196/interrupt.c
+++ /dev/null
@@ -1,229 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-/*
- * Copyright(c) 2024 MediaTek. All rights reserved.
- *
- * Author: Hailong Fan <hailong.fan@mediatek.com>
- */
-
-#include <errno.h>
-#include <inttypes.h>
-#include <rtos/bit.h>
-#include <sof/common.h>
-#include <rtos/interrupt.h>
-#include <sof/lib/cpu.h>
-#include <sof/lib/io.h>
-#include <sof/lib/memory.h>
-#include <sof/lib/uuid.h>
-#include <sof/list.h>
-#include <rtos/spinlock.h>
-#include <stdbool.h>
-#include <stddef.h>
-#include <stdint.h>
-
-#define PENDING_IRQ_INDEX_MAX 32
-
-SOF_DEFINE_REG_UUID(irq_mt8196);
-
-/* unused with Zephyr, generates no output */
-DECLARE_TR_CTX(int_tr, SOF_UUID(irq_mt8196_uuid), LOG_LEVEL_INFO);
-
-static void mtk_irq_init(void)
-{
-	intc_init();
-}
-
-static void mtk_irq_mask(struct irq_desc *desc, uint32_t irq, unsigned int core)
-{
-	if (!desc) {
-		if (irq >= 0 && irq < IRQ_MAX_CHANNEL)
-			intc_irq_disable(irq);
-		else
-			tr_err(&int_tr, "Invalid interrupt num%d", irq);
-	} else {
-		switch (desc->irq) {
-		case MTK_DSP_IRQ_MBOX_C0:
-			intc_irq_disable(6);
-			break;
-		default:
-			tr_err(&int_tr, "Invalid interrupt %d", desc->irq);
-			return;
-		}
-	}
-}
-
-static void mtk_irq_unmask(struct irq_desc *desc, uint32_t irq, unsigned int core)
-{
-	if (!desc) {
-		if (irq >= 0 && irq < IRQ_MAX_CHANNEL)
-			intc_irq_enable(irq);
-		else
-			tr_err(&int_tr, "Invalid interrupt num%d", irq);
-	} else {
-		switch (desc->irq) {
-		case MTK_DSP_IRQ_MBOX_C0:
-			intc_irq_enable(6);
-			break;
-		default:
-			tr_err(&int_tr, "Invalid interrupt %d", desc->irq);
-			return;
-		}
-	}
-}
-
-static uint32_t mtk_irq_group_pending_status(uint32_t irq)
-{
-	uint32_t irq_status = 0;
-
-	if (irq == MTK_DSP_IRQ_MBOX_C0 &&
-	    (io_reg_read(INTC_IRQ_STA0) & BIT(6))) {
-		irq_status = io_reg_read(MTK_MBOX_IRQ_IN) & MTK_DSP_MBOX_MASK;
-	}
-
-	return irq_status;
-}
-
-static uint32_t mtk_get_pending_index(uint32_t current, uint32_t *next)
-{
-	uint32_t index;
-
-	if (current == 0)
-		return PENDING_IRQ_INDEX_MAX;
-
-	/* ffs returns one plus the index of the least significant 1-bit of input int */
-	index = ffs(current) - 1;
-
-	/* remove the handling index from current pending status */
-	*next = current & ~(1ull << index);
-
-	return index;
-}
-
-static inline void mtk_handle_group_pending_irq(struct irq_cascade_desc *cascade,
-						uint32_t line_index, uint32_t status)
-{
-	int core = cpu_get_id();
-	struct list_item *clist;
-	struct irq_desc *child = NULL;
-	uint32_t idx;
-	uint32_t next_status;
-	bool handled;
-	k_spinlock_key_t key;
-
-	idx = mtk_get_pending_index(status, &next_status);
-	while (idx < PENDING_IRQ_INDEX_MAX) {
-		handled = false;
-
-		key = k_spin_lock(&cascade->lock);
-		list_for_item(clist, &cascade->child[idx].list) {
-			child = container_of(clist, struct irq_desc, irq_list);
-
-			if (child->handler && (child->cpu_mask & 1 << core)) {
-				child->handler(child->handler_arg);
-				handled = true;
-			}
-		}
-		k_spin_unlock(&cascade->lock, key);
-
-		if (!handled) {
-			tr_err(&int_tr, "Not handle irq %u in group %u",
-			       idx, line_index);
-		}
-
-		idx = mtk_get_pending_index(next_status, &next_status);
-	}
-}
-
-static inline void mtk_irq_group_handler(void *data, uint32_t line_index)
-{
-	struct irq_desc *parent = data;
-	struct irq_cascade_desc *cascade =
-		container_of(parent, struct irq_cascade_desc, desc);
-	uint32_t status;
-
-	status = mtk_irq_group_pending_status(line_index);
-	if (status)
-		mtk_handle_group_pending_irq(cascade, line_index, status);
-	else
-		tr_err(&int_tr, "No pending irq in group %d", line_index);
-}
-
-#define DEFINE_IRQ_HANDLER(n) \
-	static void irqhandler_##n(void *arg) \
-	{ \
-		mtk_irq_group_handler(arg, n); \
-	}
-
-DEFINE_IRQ_HANDLER(2)
-
-static const char mtk_irq_mailbox[] = "mtk_irq_mailbox";
-
-static const struct irq_cascade_ops irq_ops = {
-	.mask = mtk_irq_mask,
-	.unmask = mtk_irq_unmask,
-};
-
-static const struct irq_cascade_tmpl dsp_irq[] = {
-	{
-		.name = mtk_irq_mailbox,
-		.irq = MTK_DSP_IRQ_MBOX_C0,
-		.handler = irqhandler_2,
-		.ops = &irq_ops,
-		.global_mask = false,
-	},
-};
-
-int mtk_irq_group_id(uint32_t in_irq)
-{
-	if (in_irq >= MTK_MAX_IRQ_NUM)
-		in_irq -= MTK_MAX_IRQ_NUM;
-
-	return interrupt_get_irq(in_irq, dsp_irq[0].name);
-}
-
-void platform_interrupt_init(void)
-{
-	int i;
-
-	mtk_irq_init();
-	for (i = 0; i < ARRAY_SIZE(dsp_irq); i++)
-		interrupt_cascade_register(dsp_irq + i);
-}
-
-void platform_interrupt_set(uint32_t irq)
-{
-	if (interrupt_is_dsp_direct(irq))
-		arch_interrupt_set(irq);
-}
-
-void platform_interrupt_clear(uint32_t irq, uint32_t mask)
-{
-	if (interrupt_is_dsp_direct(irq))
-		arch_interrupt_clear(irq);
-}
-
-uint32_t platform_interrupt_get_enabled(void)
-{
-	return 0;
-}
-
-void interrupt_mask(uint32_t irq, unsigned int cpu)
-{
-	struct irq_cascade_desc *cascade = interrupt_get_parent(irq);
-
-	if (cascade && cascade->ops->mask)
-		cascade->ops->mask(&cascade->desc, irq - cascade->irq_base,
-				   cpu);
-	else
-		mtk_irq_mask(NULL, irq, 0);
-}
-
-void interrupt_unmask(uint32_t irq, unsigned int cpu)
-{
-	struct irq_cascade_desc *cascade = interrupt_get_parent(irq);
-
-	if (cascade && cascade->ops->unmask)
-		cascade->ops->unmask(&cascade->desc, irq - cascade->irq_base,
-				     cpu);
-	else
-		mtk_irq_unmask(NULL, irq, 0);
-}
diff --git a/src/drivers/mediatek/mt8196/ipc.c b/src/drivers/mediatek/mt8196/ipc.c
deleted file mode 100644
index dda51b495ab8..000000000000
--- a/src/drivers/mediatek/mt8196/ipc.c
+++ /dev/null
@@ -1,195 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-/*
- * Copyright(c) 2024 MediaTek. All rights reserved.
- *
- * Author: Hailong Fan <hailong.fan@mediatek.com>
- */
-
-#include <rtos/panic.h>
-#include <rtos/interrupt.h>
-#include <sof/ipc/driver.h>
-#include <sof/ipc/msg.h>
-#include <sof/ipc/schedule.h>
-#include <rtos/alloc.h>
-#include <sof/lib/dma.h>
-#include <sof/lib/mailbox.h>
-#include <sof/lib/memory.h>
-#include <sof/lib/uuid.h>
-#include <rtos/wait.h>
-#include <sof/list.h>
-#include <sof/platform.h>
-#include <sof/schedule/edf_schedule.h>
-#include <sof/schedule/schedule.h>
-#include <rtos/task.h>
-#include <rtos/spinlock.h>
-#include <ipc/header.h>
-#include <ipc/topology.h>
-#include <ipc/trace.h>
-#include <platform/drivers/mt_reg_base.h>
-#include <errno.h>
-#include <stdbool.h>
-#include <stddef.h>
-#include <stdint.h>
-
-#define IPC_DSPMBOX_DSP_RSP 0
-#define IPC_DSPMBOX_DSP_REQ 1
-
-SOF_DEFINE_REG_UUID(ipc_task_mt8196);
-
-static struct ipc *local_ipc;
-
-struct ipc_data {
-	struct ipc_data_host_buffer dh_buffer;
-};
-
-static void mbox0_handler(void *args)
-{
-	uint32_t op = io_reg_read(MTK_ADSP_MBOX_IN_CMD(0));
-
-	/* clear interrupt */
-	io_reg_write(MTK_ADSP_MBOX_IN_CMD_CLR(0), op);
-	ipc_schedule_process(local_ipc);
-}
-
-static void mbox1_handler(void *args)
-{
-	uint32_t op = io_reg_read(MTK_ADSP_MBOX_IN_CMD(1));
-
-	/* clear interrupt */
-	io_reg_write(MTK_ADSP_MBOX_IN_CMD_CLR(1), op);
-	local_ipc->is_notification_pending = false;
-}
-
-void trigger_irq_to_host_rsp(void)
-{
-	io_reg_write(MTK_ADSP_MBOX_OUT_CMD(0), ADSP_IPI_OP_RSP);
-}
-
-void trigger_irq_to_host_req(void)
-{
-	io_reg_write(MTK_ADSP_MBOX_OUT_CMD(1), ADSP_IPI_OP_REQ);
-}
-
-enum task_state ipc_platform_do_cmd(struct ipc *ipc)
-{
-	struct ipc_cmd_hdr *hdr;
-
-	hdr = mailbox_validate();
-	ipc_cmd(hdr);
-
-	return SOF_TASK_STATE_COMPLETED;
-}
-
-void ipc_platform_complete_cmd(struct ipc *ipc)
-{
-	trigger_irq_to_host_rsp();
-	while (ipc->pm_prepare_D3)
-		wait_for_interrupt(0);
-}
-
-int ipc_platform_send_msg(const struct ipc_msg *msg)
-{
-	struct ipc *ipc = ipc_get();
-
-	if (ipc->is_notification_pending)
-		return -EBUSY;
-
-	/* now send the message */
-	mailbox_dspbox_write(0, msg->tx_data, msg->tx_size);
-
-	ipc->is_notification_pending = true;
-
-	/* now interrupt host to tell it we have sent a message */
-	trigger_irq_to_host_req();
-	return 0;
-}
-
-void ipc_platform_send_msg_direct(const struct ipc_msg *msg)
-{
-	/* TODO: add support */
-}
-
-#if CONFIG_HOST_PTABLE
-struct ipc_data_host_buffer *ipc_platform_get_host_buffer(struct ipc *ipc)
-{
-	struct ipc_data *iipc = ipc_get_drvdata(ipc);
-
-	return &iipc->dh_buffer;
-}
-#endif
-
-int platform_ipc_init(struct ipc *ipc)
-{
-	int mbox_irq0, mbox_irq1;
-	int ret;
-
-#if CONFIG_HOST_PTABLE
-	struct ipc_data *iipc;
-
-	iipc = rzalloc(SOF_MEM_FLAG_KERNEL, sizeof(*iipc));
-	if (!iipc) {
-		tr_err(&ipc_tr, "Unable to allocate memory for IPC data");
-		sof_panic(SOF_IPC_PANIC_IPC);
-	}
-	ipc_set_drvdata(ipc, iipc);
-#else
-	ipc_set_drvdata(ipc, NULL);
-#endif
-
-	local_ipc = ipc;
-
-	/* schedule */
-	schedule_task_init_edf(&ipc->ipc_task, SOF_UUID(ipc_task_mt8196_uuid),
-			       &ipc_task_ops, ipc, 0, 0);
-
-#if CONFIG_HOST_PTABLE
-	/* allocate page table buffer */
-	iipc->dh_buffer.page_table =
-		rzalloc(SOF_MEM_FLAG_KERNEL, PLATFORM_PAGE_TABLE_SIZE);
-	if (!iipc->dh_buffer.page_table) {
-		tr_err(&ipc_tr, "Unable to allocate host page table buffer");
-		sof_panic(SOF_IPC_PANIC_IPC);
-	}
-
-	iipc->dh_buffer.dmac = dma_get(DMA_DIR_HMEM_TO_LMEM, 0, DMA_DEV_HOST, DMA_ACCESS_SHARED);
-	if (!iipc->dh_buffer.dmac) {
-		tr_err(&ipc_tr, "Unable to find DMA for host page table");
-		sof_panic(SOF_IPC_PANIC_IPC);
-	}
-#endif
-
-	/*
-	 * AP req -- mbox0 --> DSP
-	 *    AP <-- mbox0 --  DSP rsp
-	 *    AP <-- mbox1 --  DSP req
-	 * AP rsp -- mbox1 --> DSP
-	 */
-	mbox_irq0 = mtk_irq_group_id(MTK_DSP_IRQ_MBOX0);
-	if (mbox_irq0 < 0) {
-		tr_err(&ipc_tr, "Invalid ipc mbox 0 IRQ:%d", mbox_irq0);
-		sof_panic(SOF_IPC_PANIC_IPC);
-	}
-
-	mbox_irq1 = mtk_irq_group_id(MTK_DSP_IRQ_MBOX1);
-	if (mbox_irq1 < 0) {
-		tr_err(&ipc_tr, "Invalid ipc mbox 1 IRQ:%d", mbox_irq1);
-		sof_panic(SOF_IPC_PANIC_IPC);
-	}
-
-	ret = interrupt_register(mbox_irq0, mbox0_handler, ipc);
-	if (ret < 0) {
-		tr_err(&ipc_tr, "Unable to register ipc mbox 0 IRQ");
-		sof_panic(SOF_IPC_PANIC_IPC);
-	}
-
-	ret = interrupt_register(mbox_irq1, mbox1_handler, ipc);
-	if (ret < 0) {
-		tr_err(&ipc_tr, "Unable to register ipc mbox 1 IRQ");
-		sof_panic(SOF_IPC_PANIC_IPC);
-	}
-
-	interrupt_enable(mbox_irq0, ipc);
-	interrupt_enable(mbox_irq1, ipc);
-
-	return 0;
-}
diff --git a/src/drivers/mediatek/mt8196/timer.c b/src/drivers/mediatek/mt8196/timer.c
deleted file mode 100644
index 211cd45fe19d..000000000000
--- a/src/drivers/mediatek/mt8196/timer.c
+++ /dev/null
@@ -1,220 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-/*
- * Copyright(c) 2024 MediaTek. All rights reserved.
- *
- * Author: Hailong Fan <hailong.fan@mediatek.com>
- */
-
-#include <sof/audio/component_ext.h>
-#include <rtos/interrupt.h>
-#include <sof/lib/memory.h>
-#include <sof/platform.h>
-#include <platform/drivers/timer.h>
-#include <platform/drivers/interrupt.h>
-#include <platform/drivers/intc.h>
-#include <ipc/stream.h>
-#include <errno.h>
-#include <stdint.h>
-
-void platform_timer_start(struct timer *timer)
-{
-	/* set 26m clksrc */
-	io_reg_update_bits(MTK_TIMER_CON(timer->id), MTK_TIMER_ENABLE_BIT, 0);
-	io_reg_update_bits(MTK_TIMER_CON(timer->id), MTK_TIMER_CLKSRC_BIT,
-			   MTK_TIMER_CLK_SRC_CLK_26M);
-
-	/* enable timer */
-	io_reg_update_bits(MTK_TIMER_CON(timer->id), MTK_TIMER_ENABLE_BIT,
-			   MTK_TIMER_ENABLE_BIT);
-
-	/* enable system boot time timer */
-	io_reg_update_bits(MTK_OSTIMER_CON, MTK_OSTIMER_EN_BIT,
-			   MTK_OSTIMER_EN_BIT);
-}
-
-void platform_timer_stop(struct timer *timer)
-{
-	if (timer->id > NR_TMRS)
-		return;
-
-	io_reg_update_bits(MTK_TIMER_CON(timer->id), MTK_TIMER_ENABLE_BIT, 0);
-	io_reg_update_bits(MTK_TIMER_IRQ_ACK(timer->id), MTK_TIMER_IRQ_ENABLE, 0);
-}
-
-/* IRQs off in arch_timer_get_system() */
-uint64_t platform_timer_get_atomic(struct timer *timer)
-{
-	return platform_timer_get(timer);
-}
-
-int64_t platform_timer_set(struct timer *timer, uint64_t ticks)
-{
-	uint64_t time;
-	uint32_t flags;
-	uint32_t low, high;
-	uint32_t ticks_set;
-
-	if (timer->id > NR_TMRS)
-		return -EINVAL;
-
-	flags = arch_interrupt_global_disable();
-
-	low = io_reg_read(MTK_OSTIMER_CUR_L);
-	high = io_reg_read(MTK_OSTIMER_CUR_H);
-
-	/* ostimer 13M counter to 26M interrupt */
-	time = (((uint64_t)high << 32) | low) << 1;
-
-	ticks_set = (ticks > time) ? ticks - time : UINT64_MAX - time +  ticks;
-
-	timer->hitimeout = ticks >> 32;
-	timer->lowtimeout = ticks_set;
-
-	/* disable timer before config it */
-	io_reg_update_bits(MTK_TIMER_CON(timer->id), MTK_TIMER_ENABLE_BIT, 0);
-
-	/* set 26m clksrc */
-	io_reg_update_bits(MTK_TIMER_CON(timer->id), MTK_TIMER_CLKSRC_BIT,
-			   MTK_TIMER_CLK_SRC_CLK_26M);
-	/* timer reset value */
-	io_reg_write(MTK_TIMER_RST_VAL(timer->id), ticks_set);
-
-	/* clear and enable irq */
-	io_reg_update_bits(MTK_TIMER_IRQ_ACK(timer->id), MTK_TIMER_IRQ_CLEAR,
-			   MTK_TIMER_IRQ_CLEAR);
-	io_reg_update_bits(MTK_TIMER_IRQ_ACK(timer->id), MTK_TIMER_IRQ_ENABLE,
-			   MTK_TIMER_IRQ_ENABLE);
-
-	/* enable timer */
-	io_reg_update_bits(MTK_TIMER_CON(timer->id), MTK_TIMER_ENABLE_BIT,
-			   MTK_TIMER_ENABLE_BIT);
-
-	arch_interrupt_global_enable(flags);
-
-	return ticks;
-}
-
-void platform_timer_clear(struct timer *timer)
-{
-	if (timer->id > NR_TMRS)
-		return;
-
-	io_reg_update_bits(MTK_TIMER_IRQ_ACK(timer->id), MTK_TIMER_IRQ_CLEAR,
-			   MTK_TIMER_IRQ_CLEAR);
-}
-
-uint64_t platform_timer_get(struct timer *timer)
-{
-	uint64_t time;
-	uint32_t low;
-	uint32_t high0;
-	uint32_t high1;
-
-	if (timer->id > NR_TMRS)
-		return -EINVAL;
-
-	/* 64bit reads are non atomic on xtensa so we must
-	 * read a stable value where there is no bit 32 flipping.
-	 */
-	do {
-		high0 = io_reg_read(MTK_OSTIMER_CUR_H);
-		low = io_reg_read(MTK_OSTIMER_CUR_L);
-		high1 = io_reg_read(MTK_OSTIMER_CUR_H);
-
-		/* worst case is we perform this twice so 6 * 32b clock reads */
-	} while (high0 != high1);
-
-	/* convert 13M ostimer counter value to 26M */
-	time = (((uint64_t)high0 << 32) | low) << 1;
-
-	return time;
-}
-
-/* get timestamp for host stream DMA position */
-void platform_host_timestamp(struct comp_dev *host, struct sof_ipc_stream_posn *posn)
-{
-	int err;
-
-	/* get host position */
-	err = comp_position(host, posn);
-	if (err == 0)
-		posn->flags |= SOF_TIME_HOST_VALID | SOF_TIME_HOST_64;
-}
-
-/* get timestamp for DAI stream DMA position */
-void platform_dai_timestamp(struct comp_dev *dai,
-			    struct sof_ipc_stream_posn *posn)
-{
-	int err;
-
-	/* get DAI position */
-	err = comp_position(dai, posn);
-	if (err == 0)
-		posn->flags |= SOF_TIME_DAI_VALID;
-
-	posn->wallclock = timer_get_system(timer_get()) - posn->wallclock;
-	posn->flags |= SOF_TIME_WALL_VALID | SOF_TIME_WALL_64;
-}
-
-/* get current wallclock for componnent */
-void platform_dai_wallclock(struct comp_dev *dai, uint64_t *wallclock)
-{
-	*wallclock = platform_timer_get(timer_get());
-}
-
-static void platform_timer_handler(void *arg)
-{
-	struct timer *timer = arg;
-
-	io_reg_update_bits(MTK_TIMER_IRQ_ACK(timer->id), MTK_TIMER_IRQ_CLEAR,
-			   MTK_TIMER_IRQ_CLEAR);
-
-	io_reg_update_bits(MTK_TIMER_CON(timer->id), MTK_TIMER_ENABLE_BIT, 0);
-
-	io_reg_update_bits(MTK_TIMER_IRQ_ACK(timer->id), MTK_TIMER_IRQ_ENABLE, 0);
-
-	timer->handler(timer->data);
-}
-
-static int platform_timer_register(struct timer *timer, void (*handler)(void *arg), void *arg)
-{
-	timer->handler = handler;
-	timer->data = arg;
-	timer->hitime = 0;
-	timer->hitimeout = 0;
-
-	return interrupt_register(timer->irq, platform_timer_handler, timer);
-}
-
-int timer_register(struct timer *timer, void(*handler)(void *arg), void *arg)
-{
-	switch (timer->id) {
-	case OSTIMER0:
-	case OSTIMER1:
-	case OSTIMER2:
-	case OSTIMER3:
-		return platform_timer_register(timer, handler, arg);
-	default:
-		return -EINVAL;
-	}
-}
-
-void timer_unregister(struct timer *timer, void *arg)
-{
-	interrupt_unregister(timer->irq, arg);
-}
-
-void timer_enable(struct timer *timer, void *arg, int core)
-{
-	/* enable timer interrupt */
-	interrupt_enable(timer->irq, arg);
-
-	interrupt_unmask(8, cpu_get_id());
-}
-
-void timer_disable(struct timer *timer, void *arg, int core)
-{
-	/* enable timer interrupt */
-	interrupt_disable(timer->irq, arg);
-	interrupt_mask(8, cpu_get_id());
-}
diff --git a/src/drivers/mediatek/mt8365/CMakeLists.txt b/src/drivers/mediatek/mt8365/CMakeLists.txt
deleted file mode 100644
index 0c8e351f06b5..000000000000
--- a/src/drivers/mediatek/mt8365/CMakeLists.txt
+++ /dev/null
@@ -1,4 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-
-add_local_sources(sof ipc.c timer.c interrupt.c)
-
diff --git a/src/drivers/mediatek/mt8365/interrupt.c b/src/drivers/mediatek/mt8365/interrupt.c
deleted file mode 100644
index 84dc13a2e397..000000000000
--- a/src/drivers/mediatek/mt8365/interrupt.c
+++ /dev/null
@@ -1,226 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-/*
- * Copyright(c) 2024 MediaTek. All rights reserved.
- *
- * Author: Andrew Perepech <andrew.perepech@mediatek.com>
- */
-
-#include <errno.h>
-#include <inttypes.h>
-#include <rtos/bit.h>
-#include <sof/common.h>
-#include <rtos/interrupt.h>
-#include <sof/lib/cpu.h>
-#include <sof/lib/io.h>
-#include <sof/lib/memory.h>
-#include <sof/lib/uuid.h>
-#include <sof/list.h>
-#include <rtos/spinlock.h>
-#include <stdbool.h>
-#include <stddef.h>
-#include <stdint.h>
-
-#define PENDING_IRQ_INDEX_MAX 10
-
-SOF_DEFINE_REG_UUID(interrupt);
-
-/* unused with Zephyr, generates no output */
-DECLARE_TR_CTX(int_tr, SOF_UUID(interrupt_uuid), LOG_LEVEL_INFO);
-
-static void mtk_irq_init(void)
-{
-	/* disable all ADSP IRQ */
-	io_reg_write(RG_DSP_IRQ_EN, 0x0);
-}
-
-static void mtk_irq_mask(struct irq_desc *desc, uint32_t irq, unsigned int core)
-{
-	if (!desc) {
-		io_reg_update_bits(RG_DSP_IRQ_EN, BIT(irq + IRQ_EXT_BIT_OFFSET), 0);
-	} else {
-		switch (desc->irq) {
-		case IRQ_EXT_GROUP1_BASE:
-			io_reg_update_bits(RG_DSP_IRQ_EN, BIT(irq + IRQ_EXT_GROUP1_BIT_OFFSET), 0);
-			break;
-		default:
-			tr_err(&int_tr, "Invalid interrupt %d", irq);
-			return;
-		}
-	}
-}
-
-static void mtk_irq_unmask(struct irq_desc *desc, uint32_t irq, unsigned int core)
-{
-	if (!desc) {
-		io_reg_update_bits(RG_DSP_IRQ_EN, BIT(irq + IRQ_EXT_BIT_OFFSET),
-							BIT(irq + IRQ_EXT_BIT_OFFSET));
-	} else {
-		switch (desc->irq) {
-		case IRQ_EXT_GROUP1_BASE:
-			io_reg_update_bits(RG_DSP_IRQ_EN, BIT(irq + IRQ_EXT_GROUP1_BIT_OFFSET),
-							BIT(irq + IRQ_EXT_GROUP1_BIT_OFFSET));
-			break;
-		default:
-			tr_err(&int_tr, "Invalid interrupt %d", irq);
-			return;
-		}
-	}
-}
-
-static uint32_t mtk_irq_group_pending_status(uint32_t irq)
-{
-	uint32_t irq_status = 0;
-
-	if (irq == IRQ_EXT_GROUP1_BASE) {
-		irq_status = io_reg_read(RG_DSP_IRQ_STATUS);
-		irq_status &= IRQ_EXT_MASK;
-	}
-
-	return irq_status;
-}
-
-static uint32_t mtk_get_pending_index(uint32_t current, uint32_t *next)
-{
-	uint32_t index;
-
-	if (current == 0)
-		return PENDING_IRQ_INDEX_MAX;
-
-	/* ffs returns one plus the index of the least significant 1-bit of input int */
-	index = ffs(current) - 1;
-
-	/* remove the handling index from current pending status */
-	*next = current & ~(1ull << index);
-
-	return index;
-}
-
-static inline void mtk_handle_group_pending_irq(struct irq_cascade_desc *cascade,
-						uint32_t line_index, uint32_t status)
-{
-	int core = cpu_get_id();
-	struct list_item *clist;
-	struct irq_desc *child = NULL;
-	uint32_t idx;
-	uint32_t next_status;
-	bool handled;
-	k_spinlock_key_t key;
-
-	idx = mtk_get_pending_index(status, &next_status);
-	while (idx < PENDING_IRQ_INDEX_MAX) {
-		handled = false;
-
-		key = k_spin_lock(&cascade->lock);
-		list_for_item(clist, &cascade->child[idx - IRQ_EXT_GROUP1_BIT_OFFSET].list) {
-			child = container_of(clist, struct irq_desc, irq_list);
-
-			if (child->handler && (child->cpu_mask & 1 << core)) {
-				child->handler(child->handler_arg);
-				handled = true;
-			}
-		}
-		k_spin_unlock(&cascade->lock, key);
-
-		if (!handled) {
-			tr_err(&int_tr, "Not handle irq %u in group %u",
-			       idx, line_index);
-		}
-
-		idx = mtk_get_pending_index(next_status, &next_status);
-	}
-}
-
-static inline void mtk_irq_group_handler(void *data, uint32_t line_index)
-{
-	struct irq_desc *parent = data;
-	struct irq_cascade_desc *cascade =
-		container_of(parent, struct irq_cascade_desc, desc);
-	uint32_t status;
-
-	status = mtk_irq_group_pending_status(line_index);
-	if (status)
-		mtk_handle_group_pending_irq(cascade, line_index, status);
-	else
-		tr_err(&int_tr, "No pending irq in group %d", line_index);
-}
-
-#define DEFINE_IRQ_HANDLER(n) \
-	static void irqhandler_##n(void *arg) \
-	{ \
-		mtk_irq_group_handler(arg, n); \
-	}
-
-DEFINE_IRQ_HANDLER(1)
-
-static const char mtk_ext_irq[] = "mtk_ext_irq";
-
-static const struct irq_cascade_ops irq_ops = {
-	.mask = mtk_irq_mask,
-	.unmask = mtk_irq_unmask,
-};
-
-static const struct irq_cascade_tmpl dsp_irq[] = {
-	{
-		.name = mtk_ext_irq,
-		.irq = IRQ_EXT_GROUP1_BASE,
-		.handler = irqhandler_1,
-		.ops = &irq_ops,
-		.global_mask = false,
-	},
-};
-
-int mtk_irq_group_id(uint32_t in_irq)
-{
-	if (in_irq >= PLATFORM_IRQ_HW_NUM)
-		in_irq -= PLATFORM_IRQ_HW_NUM;
-
-	return interrupt_get_irq(in_irq, dsp_irq[0].name);
-}
-
-void platform_interrupt_init(void)
-{
-	int i;
-
-	mtk_irq_init();
-	for (i = 0; i < ARRAY_SIZE(dsp_irq); i++)
-		interrupt_cascade_register(dsp_irq + i);
-}
-
-void platform_interrupt_set(uint32_t irq)
-{
-	if (interrupt_is_dsp_direct(irq))
-		arch_interrupt_set(irq);
-}
-
-void platform_interrupt_clear(uint32_t irq, uint32_t mask)
-{
-	if (interrupt_is_dsp_direct(irq))
-		arch_interrupt_clear(irq);
-}
-
-uint32_t platform_interrupt_get_enabled(void)
-{
-	return 0;
-}
-
-void interrupt_mask(uint32_t irq, unsigned int cpu)
-{
-	struct irq_cascade_desc *cascade = interrupt_get_parent(irq);
-
-	if (cascade && cascade->ops->mask)
-		cascade->ops->mask(&cascade->desc, irq - cascade->irq_base,
-				   cpu);
-	else
-		mtk_irq_mask(NULL, irq, 0);
-}
-
-void interrupt_unmask(uint32_t irq, unsigned int cpu)
-{
-	struct irq_cascade_desc *cascade = interrupt_get_parent(irq);
-
-	if (cascade && cascade->ops->unmask)
-		cascade->ops->unmask(&cascade->desc, irq - cascade->irq_base,
-				     cpu);
-	else
-		mtk_irq_unmask(NULL, irq, 0);
-}
diff --git a/src/drivers/mediatek/mt8365/ipc.c b/src/drivers/mediatek/mt8365/ipc.c
deleted file mode 100644
index 348cd6a51f45..000000000000
--- a/src/drivers/mediatek/mt8365/ipc.c
+++ /dev/null
@@ -1,179 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-/*
- * Copyright(c) 2024 MediaTek. All rights reserved.
- *
- * Author: Andrew Perepech <andrew.perepech@mediatek.com>
- */
-
-#include <rtos/panic.h>
-#include <rtos/interrupt.h>
-#include <sof/ipc/driver.h>
-#include <sof/ipc/msg.h>
-#include <sof/ipc/schedule.h>
-#include <rtos/alloc.h>
-#include <sof/lib/dma.h>
-#include <sof/lib/mailbox.h>
-#include <sof/lib/memory.h>
-#include <sof/lib/uuid.h>
-#include <rtos/wait.h>
-#include <sof/list.h>
-#include <sof/platform.h>
-#include <sof/schedule/edf_schedule.h>
-#include <sof/schedule/schedule.h>
-#include <rtos/task.h>
-#include <rtos/spinlock.h>
-#include <ipc/header.h>
-#include <ipc/topology.h>
-#include <ipc/trace.h>
-#include <platform/drivers/mt_reg_base.h>
-#include <errno.h>
-#include <stdbool.h>
-#include <stddef.h>
-#include <stdint.h>
-
-SOF_DEFINE_REG_UUID(ipc_task);
-
-static struct ipc *local_ipc;
-
-struct ipc_data {
-	struct ipc_data_host_buffer dh_buffer;
-};
-
-static void irq_handler(void *args)
-{
-	uint32_t status;
-
-	/* Interrupt arrived, check src */
-	status = mailbox_sw_reg_read(SRAM_REG_OP_CPU2DSP);
-
-	tr_dbg(&ipc_tr, "ipc: irq isr 0x%x", status);
-
-	/* reply message(done) from host */
-	if (status == ADSP_IPI_OP_RSP) {
-		/* clear interrupt */
-		io_reg_update_bits(DSP_RG_INT2CIRQ, CPU2DSP_IRQ, 0);
-		local_ipc->is_notification_pending = false;
-	}
-
-	/* new message from host */
-	if (status == ADSP_IPI_OP_REQ) {
-		/* clear interrupt */
-		io_reg_update_bits(DSP_RG_INT2CIRQ, CPU2DSP_IRQ, 0);
-		ipc_schedule_process(local_ipc);
-	}
-}
-
-/* DSP -> HOST RSP */
-void trigger_irq_to_host_rsp(void)
-{
-	mailbox_sw_reg_write(SRAM_REG_OP_DSP2CPU, ADSP_IPI_OP_RSP);
-	/* trigger host irq */
-	io_reg_update_bits(DSP_RG_INT2CIRQ, DSP2SPM_IRQ_B, 0);
-	io_reg_update_bits(DSP_RG_INT2CIRQ, DSP2CPU_IRQ, DSP2CPU_IRQ);
-}
-
-/* DSP -> HOST REQ */
-void trigger_irq_to_host_req(void)
-{
-	mailbox_sw_reg_write(SRAM_REG_OP_DSP2CPU, ADSP_IPI_OP_REQ);
-	/* trigger host irq */
-	io_reg_update_bits(DSP_RG_INT2CIRQ, DSP2SPM_IRQ_B, 0);
-	io_reg_update_bits(DSP_RG_INT2CIRQ, DSP2CPU_IRQ, DSP2CPU_IRQ);
-}
-
-enum task_state ipc_platform_do_cmd(struct ipc *ipc)
-{
-	struct ipc_cmd_hdr *hdr;
-
-	hdr = mailbox_validate();
-	ipc_cmd(hdr);
-
-	return SOF_TASK_STATE_COMPLETED;
-}
-
-void ipc_platform_complete_cmd(struct ipc *ipc)
-{
-	trigger_irq_to_host_rsp();
-	while (ipc->pm_prepare_D3) {
-		clock_set_freq(CLK_CPU(cpu_get_id()), CLK_SUSPEND_CPU_HZ);
-		asm volatile("waiti 15");
-	}
-}
-
-int ipc_platform_send_msg(const struct ipc_msg *msg)
-{
-	struct ipc *ipc = ipc_get();
-
-	if (ipc->is_notification_pending)
-		return -EBUSY;
-
-	/* now send the message */
-	mailbox_dspbox_write(0, msg->tx_data, msg->tx_size);
-
-	tr_dbg(&ipc_tr, "ipc: msg tx -> 0x%x", msg->header);
-
-	ipc->is_notification_pending = true;
-
-	/* now interrupt host to tell it we have sent a message */
-	trigger_irq_to_host_req();
-	return 0;
-}
-
-void ipc_platform_send_msg_direct(const struct ipc_msg *msg)
-{
-	/* TODO: add support */
-}
-
-#if CONFIG_HOST_PTABLE
-struct ipc_data_host_buffer *ipc_platform_get_host_buffer(struct ipc *ipc)
-{
-	struct ipc_data *iipc = ipc_get_drvdata(ipc);
-
-	return &iipc->dh_buffer;
-}
-#endif
-
-int platform_ipc_init(struct ipc *ipc)
-{
-	uint32_t ipi_irq;
-
-#if CONFIG_HOST_PTABLE
-	struct ipc_data *iipc;
-
-	iipc = rzalloc(SOF_MEM_FLAG_KERNEL, sizeof(*iipc));
-	if (!iipc) {
-		tr_err(&ipc_tr, "Unable to allocate IPC private data");
-		sof_panic(SOF_IPC_PANIC_IPC);
-	}
-	ipc_set_drvdata(ipc, iipc);
-#else
-	ipc_set_drvdata(ipc, NULL);
-#endif
-
-	local_ipc = ipc;
-
-	/* schedule */
-	schedule_task_init_edf(&ipc->ipc_task, SOF_UUID(ipc_task_uuid), &ipc_task_ops, ipc, 0, 0);
-
-#if CONFIG_HOST_PTABLE
-	/* allocate page table buffer */
-	iipc->dh_buffer.page_table =
-		rzalloc(SOF_MEM_FLAG_KERNEL, PLATFORM_PAGE_TABLE_SIZE);
-	if (!iipc->dh_buffer.page_table) {
-		tr_err(&ipc_tr, "Unable to allocate host page table buffer");
-		sof_panic(SOF_IPC_PANIC_IPC);
-	}
-
-	iipc->dh_buffer.dmac = dma_get(DMA_DIR_HMEM_TO_LMEM, 0, DMA_DEV_HOST, DMA_ACCESS_SHARED);
-	if (!iipc->dh_buffer.dmac) {
-		tr_err(&ipc_tr, "Unable to find DMA for host page table");
-		sof_panic(SOF_IPC_PANIC_IPC);
-	}
-#endif
-
-	ipi_irq = mtk_irq_group_id(LX_MCU_IRQ_B);
-	interrupt_register(ipi_irq, irq_handler, ipc);
-	interrupt_enable(ipi_irq, ipc);
-
-	return 0;
-}
diff --git a/src/drivers/mediatek/mt8365/timer.c b/src/drivers/mediatek/mt8365/timer.c
deleted file mode 100644
index 40d33a6d1b50..000000000000
--- a/src/drivers/mediatek/mt8365/timer.c
+++ /dev/null
@@ -1,168 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-/*
- * Copyright(c) 2024 MediaTek. All rights reserved.
- *
- * Author: Andrew Perepech <andrew.perepech@mediatek.com>
- */
-
-#include <sof/audio/component_ext.h>
-#include <rtos/interrupt.h>
-#include <sof/lib/memory.h>
-#include <sof/platform.h>
-#include <platform/drivers/timer.h>
-#include <ipc/stream.h>
-#include <errno.h>
-#include <stdint.h>
-
-void platform_timer_start(struct timer *timer)
-{
-	if (timer->id >= NR_TMRS)
-		return;
-
-	/*timer use 13M clksrc*/
-	/*clear irq, if pending and enable timer*/
-	io_reg_write(TIMER_CON(timer->id), TIMER_IRQ_CLEAR | TIMER_ENABLE_BIT);
-}
-
-void platform_timer_stop(struct timer *timer)
-{
-	if (timer->id >= NR_TMRS)
-		return;
-
-	io_reg_write(TIMER_CON(timer->id), TIMER_IRQ_CLEAR | TIMER_ENABLE_BIT);
-	io_reg_write(TIMER_CON(timer->id), 0);
-
-}
-
-/* IRQs off in arch_timer_get_system() */
-uint64_t platform_timer_get_atomic(struct timer *timer)
-{
-	return platform_timer_get(timer);
-}
-
-int64_t platform_timer_set(struct timer *timer, uint64_t ticks)
-{
-	uint64_t time;
-	uint32_t flags;
-	uint32_t ticks_set;
-
-	if (timer->id >= NR_TMRS)
-		return -EINVAL;
-
-	flags = arch_interrupt_global_disable();
-
-	time = platform_timer_get(timer);
-	ticks_set = (ticks > time) ? ticks - time : UINT64_MAX - time +  ticks;
-	timer->hitimeout = ticks >> 32;
-	timer->lowtimeout = ticks_set;
-
-	io_reg_write(TIMER_CNT_VAL(timer->id), ticks_set);
-	io_reg_write(TIMER_CON(timer->id), TIMER_IRQ_ENABLE | TIMER_ENABLE_BIT);
-
-	arch_interrupt_global_enable(flags);
-
-	return ticks;
-}
-
-void platform_timer_clear(struct timer *timer)
-{
-	if (timer->id >= NR_TMRS)
-		return;
-
-	io_reg_write(TIMER_CON(timer->id), TIMER_IRQ_CLEAR | TIMER_ENABLE_BIT);
-}
-
-uint64_t platform_timer_get(struct timer *timer)
-{
-	uint64_t time;
-	uint32_t low, high;
-
-	if (timer->id >= NR_TMRS)
-		return -EINVAL;
-
-	/* CNTCV_H is only updated when the CNTCV_L is read.
-	 * Always read CNTCV_L before CNTCV_H to get a valid 64-bit timestamp.
-	 */
-	low = io_reg_read(CNTCV_L);
-	high = io_reg_read(CNTCV_H);
-	time = ((uint64_t)high << 32) | low;
-
-	return time;
-}
-
-/* get timestamp for host stream DMA position */
-void platform_host_timestamp(struct comp_dev *host,
-			     struct sof_ipc_stream_posn *posn)
-{
-	int err;
-
-	/* get host position */
-	err = comp_position(host, posn);
-	if (err == 0)
-		posn->flags |= SOF_TIME_HOST_VALID | SOF_TIME_HOST_64;
-}
-
-/* get timestamp for DAI stream DMA position */
-void platform_dai_timestamp(struct comp_dev *dai,
-			    struct sof_ipc_stream_posn *posn)
-{
-	int err;
-
-	/* get DAI position */
-	err = comp_position(dai, posn);
-	if (err == 0)
-		posn->flags |= SOF_TIME_DAI_VALID;
-
-	posn->wallclock = timer_get_system(timer_get()) - posn->wallclock;
-	posn->flags |= SOF_TIME_WALL_VALID | SOF_TIME_WALL_64;
-}
-
-/* get current wallclock for componnent */
-void platform_dai_wallclock(struct comp_dev *dai, uint64_t *wallclock)
-{
-	*wallclock = platform_timer_get(timer_get());
-}
-
-static void platform_timer_handler(void *arg)
-{
-	struct timer *timer = arg;
-
-	timer->handler(timer->data);
-}
-
-static int platform_timer_register(struct timer *timer, void (*handler)(void *arg), void *arg)
-{
-	timer->handler = handler;
-	timer->data = arg;
-	timer->hitime = 0;
-	timer->hitimeout = 0;
-
-	return interrupt_register(timer->irq, platform_timer_handler, timer);
-}
-
-int timer_register(struct timer *timer, void(*handler)(void *arg), void *arg)
-{
-	switch (timer->id) {
-	case OSTIMER0:
-		return platform_timer_register(timer, handler, arg);
-	default:
-		return -EINVAL;
-	}
-}
-
-void timer_unregister(struct timer *timer, void *arg)
-{
-	interrupt_unregister(timer->irq, arg);
-}
-
-void timer_enable(struct timer *timer, void *arg, int core)
-{
-	interrupt_unmask(timer->irq, cpu_get_id());
-	interrupt_enable(timer->irq, arg);
-}
-
-void timer_disable(struct timer *timer, void *arg, int core)
-{
-	interrupt_disable(timer->irq, arg);
-	interrupt_mask(timer->irq, cpu_get_id());
-}
diff --git a/src/include/README.md b/src/include/README.md
index ca04815738e5..4332b684d619 100644
--- a/src/include/README.md
+++ b/src/include/README.md
@@ -26,7 +26,7 @@ Previously SOF had the following **mandatory** include PATHS
  logic and headers i.e.
 
 ```
-xtos/include
+posix/include
 zephyr/include
 ```
 
diff --git a/src/include/ipc/header.h b/src/include/ipc/header.h
index 98352b643502..aeb2a69cafec 100644
--- a/src/include/ipc/header.h
+++ b/src/include/ipc/header.h
@@ -331,7 +331,7 @@ struct ipc_cmd_hdr;
 /** Maximum message size for mailbox Tx/Rx */
 #if CONFIG_IPC_MAJOR_4
 #define SOF_IPC_MSG_MAX_SIZE			0x1000
-#elif CONFIG_LIBRARY_STATIC || UNIT_TEST
+#elif CONFIG_LIBRARY || UNIT_TEST
 #define SOF_IPC_MSG_MAX_SIZE			0x2000
 #else
 #define SOF_IPC_MSG_MAX_SIZE			384
diff --git a/src/include/sof/audio/component.h b/src/include/sof/audio/component.h
index e26a9c1368f4..f414811cc3c9 100644
--- a/src/include/sof/audio/component.h
+++ b/src/include/sof/audio/component.h
@@ -877,7 +877,7 @@ static inline struct processing_module *comp_mod(const struct comp_dev *dev)
 #define comp_get_drvdata(c) \
 	(c->priv_data)
 
-#if defined UNIT_TEST || defined __ZEPHYR__  || CONFIG_LIBRARY_STATIC
+#if defined UNIT_TEST || defined __ZEPHYR__  || CONFIG_LIBRARY
 #define DECLARE_MODULE(init)
 
 /* declared modules */
diff --git a/src/include/sof/debug/debug.h b/src/include/sof/debug/debug.h
index 3cc14416acca..fa3fa990b2b4 100644
--- a/src/include/sof/debug/debug.h
+++ b/src/include/sof/debug/debug.h
@@ -36,12 +36,8 @@
 
 #include <sof/lib/mailbox.h>
 
-/** Firmware ready flags describing debug capabilities (GDB, build flags) */
-#define DEBUG_SET_FW_READY_FLAGS					\
-(									\
-	SOF_IPC_INFO_BUILD |						\
-	(IS_ENABLED(CONFIG_GDB_DEBUG) ? SOF_IPC_INFO_GDB : 0)	\
-)
+/** Firmware ready flags describing debug capabilities (build flags) */
+#define DEBUG_SET_FW_READY_FLAGS	SOF_IPC_INFO_BUILD
 
 /** \brief Dump current file name, function name, and line number to base of debug mailbox */
 #define dbg() \
@@ -128,10 +124,7 @@
 
 #else
 
-#define DEBUG_SET_FW_READY_FLAGS					\
-(									\
-	(IS_ENABLED(CONFIG_GDB_DEBUG) ? SOF_IPC_INFO_GDB : 0)	\
-)
+#define DEBUG_SET_FW_READY_FLAGS	0
 
 #define dbg() do {} while (0)
 #define dbg_at(__x) do {} while (0)
diff --git a/src/include/sof/debug/gdb/gdb.h b/src/include/sof/debug/gdb/gdb.h
index 5cf3d78fde50..4db4e9307b92 100644
--- a/src/include/sof/debug/gdb/gdb.h
+++ b/src/include/sof/debug/gdb/gdb.h
@@ -7,63 +7,15 @@
 
 /**
  * \file include/sof/debug/gdb/gdb.h
- * \brief GDB target debug stub, exception traps, and register accessors.
+ * \brief Entry point of the Zephyr GDB stub (CONFIG_GDBSTUB).
  * \ingroup debug_stream_api
  */
 
 #ifndef __SOF_DEBUG_GDB_GDB_H__
 #define __SOF_DEBUG_GDB_GDB_H__
 
-/* unconditionally including this header will cause
- * problems on architectures such as ARM64 with Zephyr
- * since they don't have an entry in arch/.
- *
- * since GDB debug is only to be used when CONFIG_GDB_DEBUG=y
- * we can safely avoid this problem with the below conditional
- * definition of the symbols.
- */
-#ifdef CONFIG_GDB_DEBUG
-
-#include <arch/debug/gdb/init.h>
-#include <arch/debug/gdb/utilities.h>
-
-#define GDB_BUFMAX 256
-#define GDB_NUMBER_OF_REGISTERS 64
-#define GDB_DISABLE_LOWER_INTERRUPTS_MASK ~0x1F
-#define GDB_REGISTER_MASK 0xFF
-#define GDB_FIRST_BYTE_MASK 0xF0000000
-#define GDB_VALID_MEM_START_BYTE 0xB
-#define GDB_VALID_MEM_ADDRESS_LEN 0x8
-#define GDB_AR_REG_RANGE 0x10 /**< identifies registers in current window */
-#define GDB_PC_REG_ID 0x20 /**< identifies PC register */
-#define GDB_AREG_RANGE 0x100 /**< identifies address registers range */
-#define GDB_SPEC_REG_RANGE_START 0x200 /**< identifies spec registers range */
-#define GDB_SPEC_REG_RANGE_END 0x300 /**< identifies spec registers range */
-#define GDB_REG_RANGE_END 0x400 /**< identifies spec registers range */
-
-/**
- * \brief Exception handler hook triggered on GDB breakpoint or watchpoint trap.
- * \ingroup debug_stream_api
- */
-void gdb_handle_exception(void);
-
-/**
- * \brief Output diagnostic debug string to connected GDB client.
- * \ingroup debug_stream_api
- * @param[in] str Null-terminated string to transmit.
- */
-void gdb_debug_info(unsigned char *str);
-
-/**
- * \brief Initialize debug exception vectors and trap handlers.
- * \ingroup debug_stream_api
- */
-void gdb_init_debug_exception(void);
-
-#endif /* CONFIG_GDB_DEBUG */
-
 /**
- * \brief Initialize the GDB target debugging stub and register listeners.
+ * \brief Initialize the GDB target debugging stub, see ipc_enter_gdb.
  * \ingroup debug_stream_api
  */
 void gdb_init(void);
diff --git a/src/include/sof/debug/gdb/ringbuffer.h b/src/include/sof/debug/gdb/ringbuffer.h
deleted file mode 100644
index 51580215a64d..000000000000
--- a/src/include/sof/debug/gdb/ringbuffer.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- *
- * Copyright(c) 2019 Intel Corporation. All rights reserved.
- *
- * Author: Marcin Rajwa <marcin.rajwa@linux.intel.com>
- */
-
-#ifndef __SOF_DEBUG_GDB_RINGBUFFER_H__
-#define __SOF_DEBUG_GDB_RINGBUFFER_H__
-
-#include <sof/lib/mailbox.h>
-
-#define RING_SIZE 128
-#define DEBUG_RX_BASE (mailbox_get_debug_base())
-#define DEBUG_TX_BASE (mailbox_get_debug_base() + 0x100)
-
-unsigned char get_debug_char(void);
-void put_debug_char(unsigned char c);
-void put_exception_char(char c);
-void init_buffers(void);
-struct ring {
-	unsigned char head;
-	unsigned char fill1[63];
-	unsigned char tail;
-	unsigned char fill2[63];
-	unsigned char data[RING_SIZE];
-};
-
-static inline unsigned int ring_next_head(const volatile struct ring *ring)
-{
-	return (ring->head + 1) & (RING_SIZE - 1);
-}
-
-static inline unsigned int ring_next_tail(const volatile struct ring *ring)
-{
-	return (ring->tail + 1) & (RING_SIZE - 1);
-}
-
-static inline int ring_have_space(const volatile struct ring *ring)
-{
-	return ring_next_head(ring) != ring->tail;
-}
-
-static inline int ring_have_data(const volatile struct ring *ring)
-{
-	return ring->head != ring->tail;
-}
-
-#endif /* __SOF_DEBUG_GDB_RINGBUFFER_H__ */
diff --git a/src/include/sof/drivers/afe-sgen.h b/src/include/sof/drivers/afe-sgen.h
deleted file mode 100644
index 9d9919901daf..000000000000
--- a/src/include/sof/drivers/afe-sgen.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2023 MediaTek. All rights reserved.
- *
- * Author: Trevor Wu <trevor.wu@mediatek.com>
- */
-
-#ifndef __SOF_DRIVERS_AFE_SGEN_H__
-#define __SOF_DRIVERS_AFE_SGEN_H__
-
-void afe_sinegen_enable(void);
-void afe_sinegen_disable(void);
-
-#endif /* __SOF_DRIVERS_AFE_SGEN_H__ */
-
diff --git a/src/include/sof/drivers/dw-dma.h b/src/include/sof/drivers/dw-dma.h
deleted file mode 100644
index fb4d9e5b0ba4..000000000000
--- a/src/include/sof/drivers/dw-dma.h
+++ /dev/null
@@ -1,161 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- *
- * Copyright(c) 2016 Intel Corporation. All rights reserved.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- *         Keyon Jie <yang.jie@linux.intel.com>
- */
-
-#ifndef __SOF_DRIVERS_DW_DMA_H__
-#define __SOF_DRIVERS_DW_DMA_H__
-
-#include <platform/drivers/dw-dma.h>
-#include <rtos/bit.h>
-#include <sof/common.h>
-#include <sof/lib/dma.h>
-#include <sof/trace/trace.h>
-#include <user/trace.h>
-#include <stdint.h>
-
-/* channel registers */
-#define DW_MAX_CHAN		8
-#define DW_FIFO_SIZE		0x80
-#define DW_CHAN_SIZE		0x58
-#define DW_CHAN_OFFSET(chan)	(DW_CHAN_SIZE * (chan))
-
-#define DW_SAR(chan)		(0x00 + DW_CHAN_OFFSET(chan))
-#define DW_DAR(chan)		(0x08 + DW_CHAN_OFFSET(chan))
-#define DW_LLP(chan)		(0x10 + DW_CHAN_OFFSET(chan))
-#define DW_CTRL_LOW(chan)	(0x18 + DW_CHAN_OFFSET(chan))
-#define DW_CTRL_HIGH(chan)	(0x1C + DW_CHAN_OFFSET(chan))
-#define DW_CFG_LOW(chan)	(0x40 + DW_CHAN_OFFSET(chan))
-#define DW_CFG_HIGH(chan)	(0x44 + DW_CHAN_OFFSET(chan))
-#define DW_DSR(chan)		(0x50 + DW_CHAN_OFFSET(chan))
-
-/* common registers */
-#define DW_RAW_TFR		0x2C0
-#define DW_RAW_BLOCK		0x2C8
-#define DW_RAW_SRC_TRAN		0x2D0
-#define DW_RAW_DST_TRAN		0x2D8
-#define DW_RAW_ERR		0x2E0
-#define DW_STATUS_TFR		0x2E8
-#define DW_STATUS_BLOCK		0x2F0
-#define DW_STATUS_SRC_TRAN	0x2F8
-#define DW_STATUS_DST_TRAN	0x300
-#define DW_STATUS_ERR		0x308
-#define DW_MASK_TFR		0x310
-#define DW_MASK_BLOCK		0x318
-#define DW_MASK_SRC_TRAN	0x320
-#define DW_MASK_DST_TRAN	0x328
-#define DW_MASK_ERR		0x330
-#define DW_CLEAR_TFR		0x338
-#define DW_CLEAR_BLOCK		0x340
-#define DW_CLEAR_SRC_TRAN	0x348
-#define DW_CLEAR_DST_TRAN	0x350
-#define DW_CLEAR_ERR		0x358
-#define DW_INTR_STATUS		0x360
-#define DW_DMA_CFG		0x398
-#define DW_DMA_CHAN_EN		0x3A0
-#define DW_FIFO_PART0_LO	0x400
-#define DW_FIFO_PART0_HI	0x404
-#define DW_FIFO_PART1_LO	0x408
-#define DW_FIFO_PART1_HI	0x40C
-
-/* channel bits */
-#define DW_CHAN_WRITE_EN_ALL	MASK(2 * DW_MAX_CHAN - 1, DW_MAX_CHAN)
-#define DW_CHAN_WRITE_EN(chan)	BIT((chan) + DW_MAX_CHAN)
-#define DW_CHAN_ALL		MASK(DW_MAX_CHAN - 1, 0)
-#define DW_CHAN(chan)		BIT(chan)
-#define DW_CHAN_MASK_ALL	DW_CHAN_WRITE_EN_ALL
-#define DW_CHAN_MASK(chan)	DW_CHAN_WRITE_EN(chan)
-#define DW_CHAN_UNMASK_ALL	(DW_CHAN_WRITE_EN_ALL | DW_CHAN_ALL)
-#define DW_CHAN_UNMASK(chan)	(DW_CHAN_WRITE_EN(chan) | DW_CHAN(chan))
-
-/* CFG_LO */
-#define DW_CFGL_DRAIN		BIT(10)
-#define DW_CFGL_FIFO_EMPTY	BIT(9)
-#define DW_CFGL_SUSPEND		BIT(8)
-
-/* CTL_LO */
-#define DW_CTLL_RELOAD_DST	BIT(31)
-#define DW_CTLL_RELOAD_SRC	BIT(30)
-#define DW_CTLL_LLP_S_EN	BIT(28)
-#define DW_CTLL_LLP_D_EN	BIT(27)
-#define DW_CTLL_SMS(x)		SET_BIT(25, x)
-#define DW_CTLL_DMS(x)		SET_BIT(23, x)
-#define DW_CTLL_FC_P2P		SET_BITS(21, 20, 3)
-#define DW_CTLL_FC_P2M		SET_BITS(21, 20, 2)
-#define DW_CTLL_FC_M2P		SET_BITS(21, 20, 1)
-#define DW_CTLL_FC_M2M		SET_BITS(21, 20, 0)
-#define DW_CTLL_D_SCAT_EN	BIT(18)
-#define DW_CTLL_S_GATH_EN	BIT(17)
-#define DW_CTLL_SRC_MSIZE(x)	SET_BITS(16, 14, x)
-#define DW_CTLL_DST_MSIZE(x)	SET_BITS(13, 11, x)
-#define DW_CTLL_SRC_FIX		SET_BITS(10, 9, 2)
-#define DW_CTLL_SRC_DEC		SET_BITS(10, 9, 1)
-#define DW_CTLL_SRC_INC		SET_BITS(10, 9, 0)
-#define DW_CTLL_DST_FIX		SET_BITS(8, 7, 2)
-#define DW_CTLL_DST_DEC		SET_BITS(8, 7, 1)
-#define DW_CTLL_DST_INC		SET_BITS(8, 7, 0)
-#define DW_CTLL_SRC_WIDTH(x)	SET_BITS(6, 4, x)
-#define DW_CTLL_DST_WIDTH(x)	SET_BITS(3, 1, x)
-#define DW_CTLL_INT_EN		BIT(0)
-#define DW_CTLL_SRC_WIDTH_MASK	MASK(6, 4)
-#define DW_CTLL_SRC_WIDTH_SHIFT	4
-#define DW_CTLL_DST_WIDTH_MASK	MASK(3, 1)
-#define DW_CTLL_DST_WIDTH_SHIFT	1
-
-/* DSR */
-#define DW_DSR_DSC(x)		SET_BITS(31, 20, x)
-#define DW_DSR_DSI(x)		SET_BITS(19, 0, x)
-
-/* FIFO_PART */
-#define DW_FIFO_UPD		BIT(26)
-#define DW_FIFO_CHx(x)		SET_BITS(25, 13, x)
-#define DW_FIFO_CHy(x)		SET_BITS(12, 0, x)
-
-/* number of tries to wait for reset */
-#define DW_DMA_CFG_TRIES	10000
-
-/* channel drain timeout in microseconds */
-#define DW_DMA_TIMEOUT	1333
-
-/* min number of elems for config with irq disabled */
-#define DW_DMA_CFG_NO_IRQ_MIN_ELEMS	3
-
-/* linked list item address */
-#define DW_DMA_LLI_ADDRESS(lli, dir) \
-	(((dir) == DMA_DIR_MEM_TO_DEV) ? ((lli)->sar) : ((lli)->dar))
-
-#define DW_DMA_BUFFER_ALIGNMENT 0x4
-#define DW_DMA_COPY_ALIGNMENT	0x4
-
-/* TODO: add FIFO sizes */
-struct dw_chan_data {
-	uint16_t class;
-	uint16_t weight;
-};
-
-struct dw_drv_plat_data {
-	struct dw_chan_data chan[DW_MAX_CHAN];
-};
-
-/* DMA descriptor used by HW */
-struct dw_lli {
-	uint32_t sar;
-	uint32_t dar;
-	uint32_t llp;
-	uint32_t ctrl_lo;
-	uint32_t ctrl_hi;
-	uint32_t sstat;
-	uint32_t dstat;
-
-	/* align to 32 bytes to not cross cache line
-	 * in case of more than two items
-	 */
-	uint32_t reserved;
-} __packed;
-
-extern const struct dma_ops dw_dma_ops;
-
-#endif /* __SOF_DRIVERS_DW_DMA_H__ */
diff --git a/src/include/sof/drivers/esai.h b/src/include/sof/drivers/esai.h
deleted file mode 100644
index c71a2a566867..000000000000
--- a/src/include/sof/drivers/esai.h
+++ /dev/null
@@ -1,195 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- *
- * Copyright 2019 NXP
- *
- * Author: Daniel Baluta <daniel.baluta@nxp.com>
- */
-
-#ifndef __SOF_DRIVERS_ESAI_H__
-#define __SOF_DRIVERS_ESAI_H__
-
-#include <rtos/bit.h>
-#include <sof/lib/dai.h>
-#include <sof/trace/trace.h>
-#include <user/trace.h>
-
-/* ESAI Register Map */
-#define REG_ESAI_ETDR           0x00
-#define REG_ESAI_ERDR           0x04
-#define REG_ESAI_ECR            0x08
-#define REG_ESAI_ESR            0x0C
-#define REG_ESAI_TFCR           0x10
-#define REG_ESAI_TFSR           0x14
-#define REG_ESAI_RFCR           0x18
-#define REG_ESAI_RFSR           0x1C
-#define REG_ESAI_xFCR(rx)       (rx ? REG_ESAI_RFCR : REG_ESAI_TFCR)
-#define REG_ESAI_xFSR(rx)       (rx ? REG_ESAI_RFSR : REG_ESAI_TFSR)
-#define REG_ESAI_TX0            0x80
-#define REG_ESAI_TX1            0x84
-#define REG_ESAI_TX2            0x88
-#define REG_ESAI_TX3            0x8C
-#define REG_ESAI_TX4            0x90
-#define REG_ESAI_TX5            0x94
-#define REG_ESAI_TSR            0x98
-#define REG_ESAI_RX0            0xA0
-#define REG_ESAI_RX1            0xA4
-#define REG_ESAI_RX2            0xA8
-#define REG_ESAI_RX3            0xAC
-#define REG_ESAI_SAISR          0xCC
-#define REG_ESAI_SAICR          0xD0
-#define REG_ESAI_TCR            0xD4
-#define REG_ESAI_TCCR           0xD8
-#define REG_ESAI_RCR            0xDC
-#define REG_ESAI_RCCR           0xE0
-#define REG_ESAI_xCR(rx)        (rx ? REG_ESAI_RCR : REG_ESAI_TCR)
-#define REG_ESAI_xCCR(rx)       (rx ? REG_ESAI_RCCR : REG_ESAI_TCCR)
-#define REG_ESAI_TSMA           0xE4
-#define REG_ESAI_TSMB           0xE8
-#define REG_ESAI_RSMA           0xEC
-#define REG_ESAI_RSMB           0xF0
-#define REG_ESAI_xSMA(rx)       (rx ? REG_ESAI_RSMA : REG_ESAI_TSMA)
-#define REG_ESAI_xSMB(rx)       (rx ? REG_ESAI_RSMB : REG_ESAI_TSMB)
-#define REG_ESAI_PRRC           0xF8
-#define REG_ESAI_PCRC           0xFC
-
-#define ESAI_ECR_ETI		BIT(19)
-#define ESAI_ECR_ETO		BIT(18)
-#define ESAI_ECR_ERI		BIT(17)
-#define ESAI_ECR_ERO		BIT(16)
-#define ESAI_ECR_ERST		BIT(1)
-#define ESAI_ECR_ESAIEN		BIT(0)
-
-#define ESAI_ESR_TINIT		BIT(10)
-#define ESAI_ESR_RFF		BIT(9)
-#define ESAI_ESR_TFE		BIT(8)
-#define ESAI_ESR_TLS		BIT(7)
-#define ESAI_ESR_TDE		BIT(6)
-#define ESAI_ESR_TED		BIT(5)
-#define ESAI_ESR_TD		BIT(4)
-#define ESAI_ESR_RLS		BIT(3)
-#define ESAI_ESR_RDE		BIT(2)
-#define ESAI_ESR_RED		BIT(1)
-#define ESAI_ESR_RD		BIT(0)
-
-#define ESAI_xFCR_TIEN		BIT(19)
-#define ESAI_xFCR_xWA_SHIFT	16
-#define ESAI_xFCR_xWA_WIDTH	3
-#define ESAI_xFCR_xWA_MASK	MASK(18, 16)
-#define ESAI_xFCR_xWA(v)	SET_BITS(18, 16, 8 - ((v) >> 2))
-#define ESAI_xFCR_xFWM_SHIFT	8
-#define ESAI_xFCR_xFWM_WIDTH	8
-#define ESAI_xFCR_xFWM_MASK	MASK(15, 8)
-#define ESAI_xFCR_xFWM(v)	SET_BITS(15, 8, (v) - 1)
-#define ESAI_xFCR_xE_SHIFT	2
-#define ESAI_xFCR_TE_WIDTH	6
-#define ESAI_xFCR_RE_WIDTH	4
-#define ESAI_xFCR_TE_MASK	MASK(7, 2)
-#define ESAI_xFCR_RE_MASK	MASK(5, 2)
-#define ESAI_xFCR_xE_MASK(rx)	(rx ? ESAI_xFCR_RE_MASK : ESAI_xFCR_TE_MASK)
-#define ESAI_xFCR_TE(x)		SET_BITS(7, 2, MASK((x) - 1, 0))
-#define ESAI_xFCR_RE(x)		SET_BITS(5, 2, MASK((x) - 1, 0))
-#define ESAI_xFCR_xE(rx, x)	(rx ? ESAI_xFCR_RE(x) : ESAI_xFCR_TE(x))
-#define ESAI_xFCR_xFR_SHIFT	1
-#define ESAI_xFCR_xFR_MASK	BIT(1)
-#define ESAI_xFCR_xFR		BIT(1)
-#define ESAI_xFCR_xFEN_SHIFT	0
-#define ESAI_xFCR_xFEN		BIT(0)
-#define ESAI_xFCR_xFEN_MASK	BIT(0)
-
-#define ESAI_xFSR_NTFO_MASK	MASK(14, 12)
-#define ESAI_xFSR_NTFI_MASK	MASK(10, 8)
-#define ESAI_xFSR_NRFO_MASK	MASK(9, 8)
-#define ESAI_xFSR_NRFI_MASK	MASK(13, 12)
-#define ESAI_xFSR_xFCNT_MASK	MASK(7, 0)
-
-#define ESAI_SAISR_TODFE	BIT(17)
-#define ESAI_SAISR_TEDE		BIT(16)
-#define ESAI_SAISR_TDE		BIT(15)
-#define ESAI_SAISR_TUE		BIT(14)
-#define ESAI_SAISR_TFS		BIT(13)
-#define ESAI_SAISR_RODF		BIT(10)
-#define ESAI_SAISR_REDF		BIT(9)
-#define ESAI_SAISR_RDF		BIT(8)
-#define ESAI_SAISR_ROE		BIT(7)
-#define ESAI_SAISR_RFS		BIT(6)
-#define ESAI_SAISR_IF2		BIT(2)
-#define ESAI_SAISR_IF1		BIT(1)
-#define ESAI_SAISR_IF0		BIT(0)
-
-#define ESAI_SAICR_ALC		BIT(8)
-#define ESAI_SAICR_TEBE		BIT(7)
-#define ESAI_SAICR_SYN		BIT(6)
-#define ESAI_SAICR_OF2		BIT(2)
-#define ESAI_SAICR_OF1		BIT(1)
-#define ESAI_SAICR_OF0		BIT(0)
-
-#define ESAI_xCR_xLIE		BIT(23)
-#define ESAI_xCR_xIE		BIT(22)
-#define ESAI_xCR_xEDIE		BIT(21)
-#define ESAI_xCR_xEIE		BIT(20)
-#define ESAI_xCR_xPR		BIT(19)
-#define ESAI_xCR_PADC		BIT(17) /* only valid on tx */
-#define ESAI_xCR_xFSR		BIT(16)
-#define ESAI_xCR_xFSL		BIT(15)
-#define ESAI_xCR_xSWS_MASK	MASK(14, 10)
-
-/* The following macro is actually made to fit the table 16-44 in the i.MX8QXP
- * manual, ESAI chapter.
- */
-#define ESAI_xCR_xSWS_VAL(s, w)	((w) < 24 ? ((s) - (w) + (((w) - 8) >> 2)) \
-					  : ((s) < 32 ? 0x1e : 0x1f))
-#define ESAI_xCR_xSWS(s, w)	SET_BITS(14, 10, ESAI_xCR_xSWS_VAL(s, w))
-#define ESAI_xCR_xMOD_MASK	MASK(9, 8)
-#define ESAI_xCR_xMOD_NORMAL	SET_BITS(9, 8, 0)
-#define ESAI_xCR_xMOD_NETWORK	SET_BITS(9, 8, 1)
-#define ESAI_xCR_xMOD_AC97	SET_BITS(9, 8, 3)
-#define ESAI_xCR_xWA		BIT(7)
-#define ESAI_xCR_xSHFD		BIT(6)
-#define ESAI_xCR_TE_MASK	MASK(5, 0)
-#define ESAI_xCR_TE_SET(v)	SET_BITS(5, 0, v)
-#define ESAI_xCR_TE(v)		ESAI_xCR_TE_SET(MASK((v) - 1, 0))
-#define ESAI_xCR_RE_MASK	MASK(3, 0)
-#define ESAI_xCR_RE_SET(v)	SET_BITS(3, 0, v)
-#define ESAI_xCR_RE(v)		ESAI_xCR_RE_SET(MASK((v) - 1, 0))
-#define ESAI_xCR_xE_MASK(rx)	(rx ? ESAI_xCR_RE_MASK : ESAI_xCR_TE_MASK)
-#define ESAI_xCR_xE(rx, v)	(rx ? ESAI_xCR_RE(v) : ESAI_xCR_TE(v))
-
-#define ESAI_xCCR_xHCKD		BIT(23)
-#define ESAI_xCCR_xFSD		BIT(22)
-#define ESAI_xCCR_xCKD		BIT(21)
-#define ESAI_xCCR_xHCKP		BIT(20)
-#define ESAI_xCCR_xFSP		BIT(19)
-#define ESAI_xCCR_xCKP		BIT(18)
-#define ESAI_xCCR_xFP_MASK	MASK(17, 14)
-#define ESAI_xCCR_xFP(div)	SET_BITS(17, 14, (div) - 1)
-#define ESAI_xCCR_xDC_MASK	MASK(13, 9)
-#define ESAI_xCCR_xDC(v)	SET_BITS(13, 9, (v) - 1)
-#define ESAI_xCCR_xDC_AC97	SET_BITS(13, 9, 0x0C)
-#define ESAI_xCCR_xPSR_MASK	MASK(8, 8)
-#define ESAI_xCCR_xPSR_BYPASS	SET_BITS(8, 8, 1)
-#define ESAI_xCCR_xPSR_DIV8	SET_BITS(8, 8, 0)
-#define ESAI_xCCR_xPM_MASK	MASK(7, 0)
-#define ESAI_xCCR_xPM(v)	SET_BITS(7, 0, (v) - 1)
-
-#define ESAI_xSMA_xS_MASK	MASK(15, 0)
-#define ESAI_xSMA_xS(v)		SET_BITS(15, 0, v)
-#define ESAI_xSMB_xS_MASK	MASK(15, 0)
-#define ESAI_xSMB_xS(v)		SET_BITS(15, 0, (v) >> 16)
-#define ESAI_xSMA_xS_CHANS(ch)	ESAI_xSMA_xS(MASK((ch) - 1, 0))
-#define ESAI_xSMB_xS_CHANS(ch)	ESAI_xSMB_xS(MASK((ch) - 1, 0))
-
-#define ESAI_PRRC_PDC_MASK	MASK(11, 0)
-#define ESAI_PRRC_PDC(v)	SET_BITS(11, 0, v)
-
-#define ESAI_PCRC_PC_MASK	MASK(11, 0)
-#define ESAI_PCRC_PC(v)		SET_BITS(11, 0, v)
-
-#define ESAI_GPIO		MASK(11, 0)
-
-#define EDMA_ESAI_IRQ		442
-
-#define EDMA_ESAI_TX_CHAN	7
-#define EDMA_ESAI_RX_CHAN	6
-
-extern const struct dai_driver esai_driver;
-#endif /* __SOF_DRIVERS_ESAI_H__ */
diff --git a/src/include/sof/drivers/gpio.h b/src/include/sof/drivers/gpio.h
deleted file mode 100644
index e7311017426e..000000000000
--- a/src/include/sof/drivers/gpio.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- *
- * Copyright(c) 2019 Intel Corporation. All rights reserved.
- *
- * Author: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
- */
-
-#ifndef __SOF_DRIVERS_GPIO_H__
-#define __SOF_DRIVERS_GPIO_H__
-
-#include <sof/drivers/iomux.h>
-
-struct gpio;
-
-enum gpio_direction {
-	GPIO_DIRECTION_INPUT,
-	GPIO_DIRECTION_OUTPUT,
-};
-
-enum gpio_level {
-	GPIO_LEVEL_LOW,
-	GPIO_LEVEL_HIGH,
-};
-
-struct gpio_config {
-	enum gpio_direction direction;
-};
-
-struct gpio_pin_config {
-	unsigned int mux_id;
-	struct iomux_pin_config mux_config;
-};
-
-extern const struct gpio_pin_config gpio_data[];
-extern const int n_gpios;
-
-int gpio_write(const struct gpio *gpio, unsigned int port,
-	       enum gpio_level level);
-int gpio_read(const struct gpio *gpio, unsigned int port);
-int gpio_configure(const struct gpio *gpio, unsigned int port,
-		   const struct gpio_config *config);
-const struct gpio *gpio_get(unsigned int id);
-int gpio_probe(const struct gpio *gpio);
-
-#endif /* __SOF_DRIVERS_GPIO_H__ */
diff --git a/src/include/sof/drivers/hda-dma.h b/src/include/sof/drivers/hda-dma.h
deleted file mode 100644
index b0bf69a1f44e..000000000000
--- a/src/include/sof/drivers/hda-dma.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- *
- * Copyright(c) 2017 Intel Corporation. All rights reserved.
- *
- * Author: Keyon Jie <yang.jie@linux.intel.com>
- *         Rander Wang <rander.wang@intel.com>
- */
-
-#ifndef __SOF_DRIVERS_HDA_DMA_H__
-#define __SOF_DRIVERS_HDA_DMA_H__
-
-#include <sof/lib/dma.h>
-
-extern const struct dma_ops hda_host_dma_ops;
-extern const struct dma_ops hda_link_dma_ops;
-
-#endif /* __SOF_DRIVERS_HDA_DMA_H__ */
diff --git a/src/include/sof/drivers/hda.h b/src/include/sof/drivers/hda.h
deleted file mode 100644
index a78bac3b624d..000000000000
--- a/src/include/sof/drivers/hda.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- *
- * Copyright(c) 2018 Intel Corporation. All rights reserved.
- *
- * Author: Marcin Maka <marcin.maka@linux.intel.com>
- */
-
-#ifndef __SOF_DRIVERS_HDA_H__
-#define __SOF_DRIVERS_HDA_H__
-
-#include <ipc/dai-intel.h>
-#include <sof/lib/dai.h>
-
-struct hda_pdata {
-	struct sof_ipc_dai_hda_params params;
-};
-
-extern const struct dai_driver hda_driver;
-
-#endif /* __SOF_DRIVERS_HDA_H__ */
diff --git a/src/include/sof/drivers/iomux.h b/src/include/sof/drivers/iomux.h
deleted file mode 100644
index b1c2090fef35..000000000000
--- a/src/include/sof/drivers/iomux.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- *
- * Copyright(c) 2019 Intel Corporation. All rights reserved.
- *
- * Author: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
- */
-
-#ifndef __SOF_DRIVERS_IOMUX_H__
-#define __SOF_DRIVERS_IOMUX_H__
-
-#include <stdint.h>
-
-#define IOMUX_PIN_NUM 32
-
-struct iomux {
-	uint32_t base;
-	/* 0 -- unconfigured; > 0 -- configured for function (state - 1) */
-	uint8_t pin_state[IOMUX_PIN_NUM];
-};
-
-struct iomux_pin_config {
-	unsigned int bit;
-	uint32_t mask;
-	uint32_t fn;
-};
-
-extern struct iomux iomux_data[];
-extern const int n_iomux;
-
-int iomux_configure(struct iomux *iomux, const struct iomux_pin_config *cfg);
-struct iomux *iomux_get(unsigned int id);
-int iomux_probe(struct iomux *iomux);
-
-#endif /* __SOF_DRIVERS_IOMUX_H__ */
diff --git a/src/include/sof/drivers/micfil.h b/src/include/sof/drivers/micfil.h
deleted file mode 100644
index 5d6828102c97..000000000000
--- a/src/include/sof/drivers/micfil.h
+++ /dev/null
@@ -1,174 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- *
- * Copyright 2023 NXP
- *
- * Author: Daniel Baluta <daniel.baluta@nxp.com>
- */
-
-#ifndef __SOF_DRIVERS_MICFIL_H__
-#define __SOF_DRIVERS_MICFIL_H__
-
-#include <rtos/bit.h>
-#include <ipc/dai.h>
-#include <ipc/dai-imx.h>
-#include <sof/lib/dai.h>
-#include <sof/trace/trace.h>
-#include <user/trace.h>
-
-extern const struct dai_driver micfil_driver;
-
-/* MICFIL private data */
-struct micfil_pdata {
-	int quality;
-	struct sof_ipc_dai_config config;
-	struct sof_ipc_dai_micfil_params params;
-};
-
-/* MICFIL Register Map */
-#define REG_MICFIL_CTRL1		0x00
-#define REG_MICFIL_CTRL2		0x04
-#define REG_MICFIL_STAT			0x08
-#define REG_MICFIL_FIFO_CTRL		0x10
-#define REG_MICFIL_FIFO_STAT		0x14
-#define REG_MICFIL_DATACH0		0x24
-#define REG_MICFIL_DATACH1		0x28
-#define REG_MICFIL_DATACH2		0x2C
-#define REG_MICFIL_DATACH3		0x30
-#define REG_MICFIL_DATACH4		0x34
-#define REG_MICFIL_DATACH5		0x38
-#define REG_MICFIL_DATACH6		0x3C
-#define REG_MICFIL_DATACH7		0x40
-#define REG_MICFIL_DC_CTRL		0x64
-#define REG_MICFIL_OUT_CTRL		0x74
-#define REG_MICFIL_OUT_STAT		0x7C
-#define REG_MICFIL_VAD0_CTRL1		0x90
-#define REG_MICFIL_VAD0_CTRL2		0x94
-
-#define REG_MICFIL_VAD0_STAT		0x98
-#define REG_MICFIL_VAD0_SCONFIG		0x9C
-#define REG_MICFIL_VAD0_NCONFIG		0xA0
-#define REG_MICFIL_VAD0_NDATA		0xA4
-#define REG_MICFIL_VAD0_ZCD		0xA8
-
-/* MICFIL Control Register 1 -- REG_MICFILL_CTRL1 0x00 */
-#define MICFIL_CTRL1_MDIS		BIT(31)
-#define MICFIL_CTRL1_DOZEN		BIT(30)
-#define MICFIL_CTRL1_PDMIEN		BIT(29)
-#define MICFIL_CTRL1_DBG		BIT(28)
-#define MICFIL_CTRL1_SRES		BIT(27)
-#define MICFIL_CTRL1_DBGE		BIT(26)
-#define MICFIL_CTRL1_CHNEN		MASK(7, 0)
-
-#define MICFIL_CTRL1_DISEL_DISABLE	0
-#define MICFIL_CTRL1_DISEL_DMA		1
-#define MICFIL_CTRL1_DISEL_IRQ		2
-#define MICFIL_CTRL1_DISEL_BITS(x)	SET_BITS(25, 24, x)
-#define MICFIL_CTRL1_DISEL		MASK(25, 24)
-#define MICFIL_CTRL1_ERREN		BIT(23)
-#define MICFIL_CTRL1_CHEN(ch)		BIT(ch)
-
-/* MICFIL Control Register 2 -- REG_MICFILL_CTRL2 0x04 */
-#define MICFIL_CTRL2_QSEL_SHIFT		25
-#define MICFIL_CTRL2_QSEL		MASK(27, 25)
-#define MICFIL_CTRL2_QSEL_BITS(x)	SET_BITS(27, 25, x)
-#define MICFIL_QSEL_MEDIUM_QUALITY	0
-#define MICFIL_QSEL_HIGH_QUALITY	1
-#define MICFIL_QSEL_LOW_QUALITY		7
-#define MICFIL_QSEL_VLOW0_QUALITY	6
-#define MICFIL_QSEL_VLOW1_QUALITY	5
-#define MICFIL_QSEL_VLOW2_QUALITY	4
-
-#define MICFIL_CTRL2_CICOSR		MASK(19, 16)
-#define MICFIL_CTRL2_CICOSR_SHIFT	16
-#define MICFIL_CTRL2_CICOSR_BITS(x)	SET_BITS(19, 16, x)
-#define MICFIL_CTRL2_CLKDIV		MASK(7, 0)
-#define MICFIL_CTRL2_CLKDIV_BITS(x)	SET_BITS(7, 0, x)
-
-/* MICFIL Status Register -- REG_MICFIL_STAT 0x08 */
-#define MICFIL_STAT_BSY_FIL		BIT(31)
-#define MICFIL_STAT_FIR_RDY		BIT(30)
-#define MICFIL_STAT_LOWFREQF		BIT(29)
-#define MICFIL_STAT_CHXF(ch)		BIT(ch)
-
-/* MICFIL FIFO Control Register -- REG_MICFIL_FIFO_CTRL 0x10 */
-#define MICFIL_FIFO_CTRL_FIFOWMK	MASK(2, 0)
-#define MICFIL_FIFO_CTRL_FIFOWMK_BITS(x)	SET_BITS(2, 0, x)
-
-/* MICFIL FIFO Status Register -- REG_MICFIL_FIFO_STAT 0x14 */
-#define MICFIL_FIFO_STAT_FIFOX_OVER(ch)	BIT(ch)
-#define MICFIL_FIFO_STAT_FIFOX_UNDER(ch)	BIT((ch) + 8)
-
-/* MICFIL DC Remover Control Register -- REG_MICFIL_DC_CTRL */
-#define MICFIL_DC_CTRL_CONFIG          MASK(15, 0)
-#define MICFIL_DC_CHX_SHIFT(ch)        ((ch) << 1)
-#define MICFIL_DC_CHX(ch)              MASK((((ch) << 1) + 1), ((ch) << 1))
-#define MICFIL_DC_CUTOFF_21HZ          0
-#define MICFIL_DC_CUTOFF_83HZ          1
-#define MICFIL_DC_CUTOFF_152Hz         2
-#define MICFIL_DC_BYPASS               3
-
-/* MICFIL HWVAD0 Control 1 Register -- REG_MICFIL_VAD0_CTRL1*/
-#define MICFIL_VAD0_CTRL1_CHSEL		MASK(26, 24)
-#define MICFIL_VAD0_CTRL1_CICOSR	MASK(19, 16)
-#define MICFIL_VAD0_CTRL1_INITT		MASK(12, 8)
-#define MICFIL_VAD0_CTRL1_ST10		BIT(4)
-#define MICFIL_VAD0_CTRL1_ERIE		BIT(3)
-#define MICFIL_VAD0_CTRL1_IE		BIT(2)
-#define MICFIL_VAD0_CTRL1_RST		BIT(1)
-#define MICFIL_VAD0_CTRL1_EN		BIT(0)
-
-/* MICFIL HWVAD0 Control 2 Register -- REG_MICFIL_VAD0_CTRL2*/
-#define MICFIL_VAD0_CTRL2_FRENDIS	BIT(31)
-#define MICFIL_VAD0_CTRL2_PREFEN	BIT(30)
-#define MICFIL_VAD0_CTRL2_FOUTDIS	BIT(28)
-#define MICFIL_VAD0_CTRL2_FRAMET	MASK(21, 16)
-#define MICFIL_VAD0_CTRL2_INPGAIN	MASK(11, 8)
-#define MICFIL_VAD0_CTRL2_HPF		MASK(1, 0)
-
-/* MICFIL HWVAD0 Signal CONFIG Register -- REG_MICFIL_VAD0_SCONFIG */
-#define MICFIL_VAD0_SCONFIG_SFILEN		BIT(31)
-#define MICFIL_VAD0_SCONFIG_SMAXEN		BIT(30)
-#define MICFIL_VAD0_SCONFIG_SGAIN		MASK(3, 0)
-
-/* MICFIL HWVAD0 Noise CONFIG Register -- REG_MICFIL_VAD0_NCONFIG */
-#define MICFIL_VAD0_NCONFIG_NFILAUT		BIT(31)
-#define MICFIL_VAD0_NCONFIG_NMINEN		BIT(30)
-#define MICFIL_VAD0_NCONFIG_NDECEN		BIT(29)
-#define MICFIL_VAD0_NCONFIG_NOREN		BIT(28)
-#define MICFIL_VAD0_NCONFIG_NFILADJ		MASK(12, 8)
-#define MICFIL_VAD0_NCONFIG_NGAIN		MASK(3, 0)
-
-/* MICFIL HWVAD0 Zero-Crossing Detector - REG_MICFIL_VAD0_ZCD */
-#define MICFIL_VAD0_ZCD_ZCDTH		MASK(25, 16)
-#define MICFIL_VAD0_ZCD_ZCDADJ		MASK(11, 8)
-#define MICFIL_VAD0_ZCD_ZCDAND		BIT(4)
-#define MICFIL_VAD0_ZCD_ZCDAUT		BIT(2)
-#define MICFIL_VAD0_ZCD_ZCDEN		BIT(0)
-
-/* MICFIL HWVAD0 Status Register - REG_MICFIL_VAD0_STAT */
-#define MICFIL_VAD0_STAT_INITF		BIT(31)
-#define MICFIL_VAD0_STAT_INSATF		BIT(16)
-#define MICFIL_VAD0_STAT_EF		BIT(15)
-#define MICFIL_VAD0_STAT_IF		BIT(0)
-
-/* MICFIL Output Control Register */
-#define MICFIL_OUTGAIN_CHX_SHIFT(v)	(4 * (v))
-
-/* Constants */
-#define MICFIL_OUTPUT_CHANNELS		8
-#define MICFIL_FIFO_NUM			8
-
-#define FIFO_PTRWID			3
-#define FIFO_LEN			BIT(FIFO_PTRWID)
-
-#define MICFIL_IRQ_LINES		4
-#define MICFIL_MAX_RETRY		25
-#define MICFIL_SLEEP_MIN		90000 /* in us */
-#define MICFIL_SLEEP_MAX		100000 /* in us */
-#define MICFIL_DMA_MAXBURST_RX		6
-
-/* HWVAD Constants */
-#define MICFIL_HWVAD_ENVELOPE_MODE	0
-#define MICFIL_HWVAD_ENERGY_MODE	1
-
-#endif /* __SOF_DRIVERS_MICFIL_H__ */
diff --git a/src/include/sof/drivers/sai.h b/src/include/sof/drivers/sai.h
deleted file mode 100644
index 10405298322d..000000000000
--- a/src/include/sof/drivers/sai.h
+++ /dev/null
@@ -1,258 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- *
- * Copyright 2019 NXP
- *
- * Author: Jerome Laclavere <jerome.laclavere@nxp.com>
- * Author: Guido Roncarolo <guido.roncarolo@nxp.com>
- */
-
-#ifndef __SOF_DRIVERS_SAI_H__
-#define __SOF_DRIVERS_SAI_H__
-
-#include <ipc/dai.h>
-#include <ipc/dai-imx.h>
-#include <rtos/bit.h>
-#include <sof/lib/dai.h>
-#include <sof/trace/trace.h>
-#include <user/trace.h>
-
-#if defined(CONFIG_IMX8M) || defined(CONFIG_IMX8ULP) || defined(CONFIG_IMX93_A55)
-#define SAI_OFS		8
-#else
-#define SAI_OFS		0
-#endif
-
-#define REG_SAI_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
-		SNDRV_PCM_FMTBIT_S24_LE |\
-		SNDRV_PCM_FMTBIT_S32_LE |\
-		SNDRV_PCM_FMTBIT_DSD_U8 |\
-		SNDRV_PCM_FMTBIT_DSD_U16_LE |\
-		SNDRV_PCM_FMTBIT_DSD_U32_LE)
-
-/* SAI Register Map Register */
-#define REG_SAI_VERID	0x00 /* SAI Version ID Register */
-#define REG_SAI_PARAM	0x04 /* SAI Parameter Register */
-#define REG_SAI_TCSR	(0x00 + SAI_OFS) /* SAI Transmit Control */
-#define REG_SAI_TCR1	(0x04 + SAI_OFS) /* SAI Transmit Configuration 1 */
-#define REG_SAI_TCR2	(0x08 + SAI_OFS) /* SAI Transmit Configuration 2 */
-#define REG_SAI_TCR3	(0x0c + SAI_OFS) /* SAI Transmit Configuration 3 */
-#define REG_SAI_TCR4	(0x10 + SAI_OFS) /* SAI Transmit Configuration 4 */
-#define REG_SAI_TCR5	(0x14 + SAI_OFS) /* SAI Transmit Configuration 5 */
-#define REG_SAI_TDR0	0x20 /* SAI Transmit Data */
-#define REG_SAI_TDR1	0x24 /* SAI Transmit Data */
-#define REG_SAI_TDR2	0x28 /* SAI Transmit Data */
-#define REG_SAI_TDR3	0x2C /* SAI Transmit Data */
-#define REG_SAI_TDR4	0x30 /* SAI Transmit Data */
-#define REG_SAI_TDR5	0x34 /* SAI Transmit Data */
-#define REG_SAI_TDR6	0x38 /* SAI Transmit Data */
-#define REG_SAI_TDR7	0x3C /* SAI Transmit Data */
-#define REG_SAI_TFR0	0x40 /* SAI Transmit FIFO */
-#define REG_SAI_TFR1	0x44 /* SAI Transmit FIFO */
-#define REG_SAI_TFR2	0x48 /* SAI Transmit FIFO */
-#define REG_SAI_TFR3	0x4C /* SAI Transmit FIFO */
-#define REG_SAI_TFR4	0x50 /* SAI Transmit FIFO */
-#define REG_SAI_TFR5	0x54 /* SAI Transmit FIFO */
-#define REG_SAI_TFR6	0x58 /* SAI Transmit FIFO */
-#define REG_SAI_TFR7	0x5C /* SAI Transmit FIFO */
-#define REG_SAI_TMR	0x60 /* SAI Transmit Mask */
-#define REG_SAI_TTCTL	0x70 /* SAI Transmit Timestamp Control Register */
-#define REG_SAI_TTCTN	0x74 /* SAI Transmit Timestamp Counter Register */
-#define REG_SAI_TBCTN	0x78 /* SAI Transmit Bit Counter Register */
-#define REG_SAI_TTCAP	0x7C /* SAI Transmit Timestamp Capture */
-
-#define REG_SAI_RCSR	(0x80 + SAI_OFS) /* SAI Receive Control */
-#define REG_SAI_RCR1	(0x84 + SAI_OFS) /* SAI Receive Configuration 1 */
-#define REG_SAI_RCR2	(0x88 + SAI_OFS) /* SAI Receive Configuration 2 */
-#define REG_SAI_RCR3	(0x8c + SAI_OFS) /* SAI Receive Configuration 3 */
-#define REG_SAI_RCR4	(0x90 + SAI_OFS) /* SAI Receive Configuration 4 */
-#define REG_SAI_RCR5	(0x94 + SAI_OFS) /* SAI Receive Configuration 5 */
-#define REG_SAI_RDR0	0xa0 /* SAI Receive Data */
-#define REG_SAI_RDR1	0xa4 /* SAI Receive Data */
-#define REG_SAI_RDR2	0xa8 /* SAI Receive Data */
-#define REG_SAI_RDR3	0xac /* SAI Receive Data */
-#define REG_SAI_RDR4	0xb0 /* SAI Receive Data */
-#define REG_SAI_RDR5	0xb4 /* SAI Receive Data */
-#define REG_SAI_RDR6	0xb8 /* SAI Receive Data */
-#define REG_SAI_RDR7	0xbc /* SAI Receive Data */
-#define REG_SAI_RFR0	0xc0 /* SAI Receive FIFO */
-#define REG_SAI_RFR1	0xc4 /* SAI Receive FIFO */
-#define REG_SAI_RFR2	0xc8 /* SAI Receive FIFO */
-#define REG_SAI_RFR3	0xcc /* SAI Receive FIFO */
-#define REG_SAI_RFR4	0xd0 /* SAI Receive FIFO */
-#define REG_SAI_RFR5	0xd4 /* SAI Receive FIFO */
-#define REG_SAI_RFR6	0xd8 /* SAI Receive FIFO */
-#define REG_SAI_RFR7	0xdc /* SAI Receive FIFO */
-#define REG_SAI_RMR	0xe0 /* SAI Receive Mask */
-#define REG_SAI_RTCTL	0xf0 /* SAI Receive Timestamp Control Register */
-#define REG_SAI_RTCTN	0xf4 /* SAI Receive Timestamp Counter Register */
-#define REG_SAI_RBCTN	0xf8 /* SAI Receive Bit Counter Register */
-#define REG_SAI_RTCAP	0xfc /* SAI Receive Timestamp Capture */
-
-#define REG_SAI_MCTL	0x100 /* SAI MCLK Control Register */
-#define REG_SAI_MDIV	0x104 /* SAI MCLK Divide Register */
-
-#define REG_SAI_XCSR(rx)	(rx ? REG_SAI_RCSR : REG_SAI_TCSR)
-#define REG_SAI_XCR1(rx)	(rx ? REG_SAI_RCR1 : REG_SAI_TCR1)
-#define REG_SAI_XCR2(rx)	(rx ? REG_SAI_RCR2 : REG_SAI_TCR2)
-#define REG_SAI_XCR3(rx)	(rx ? REG_SAI_RCR3 : REG_SAI_TCR3)
-#define REG_SAI_XCR4(rx)	(rx ? REG_SAI_RCR4 : REG_SAI_TCR4)
-#define REG_SAI_XCR5(rx)	(rx ? REG_SAI_RCR5 : REG_SAI_TCR5)
-#define REG_SAI_XMR(rx)		(rx ? REG_SAI_RMR  : REG_SAI_TMR)
-
-#define REG_SAI_XMR_MASK        0xffffffff
-
-/* SAI Transmit/Receive Control Register */
-#define REG_SAI_CSR_TERE	BIT(31)
-#define REG_SAI_CSR_SE		BIT(30)
-#define REG_SAI_CSR_FR		BIT(25)
-#define REG_SAI_CSR_SR		BIT(24)
-#define REG_SAI_CSR_XF_SHIFT	16
-#define REG_SAI_CSR_XF_W_SHIFT	18
-#define REG_SAI_CSR_XF_MASK	MASK(REG_SAI_CSR_XF_SHIFT + 4, \
-		REG_SAI_CSR_XF_SHIFT)
-#define REG_SAI_CSR_XF_W_MASK	MASK(REG_SAI_CSR_XF_W_SHIFT + 2,\
-		REG_SAI_CSR_XF_W_SHIFT)
-#define REG_SAI_CSR_WSF		BIT(20)
-#define REG_SAI_CSR_SEF		BIT(19)
-#define REG_SAI_CSR_FEF		BIT(18)
-#define REG_SAI_CSR_FWF		BIT(17)
-#define REG_SAI_CSR_FRF		BIT(16)
-#define REG_SAI_CSR_XIE_SHIFT	8
-#define REG_SAI_CSR_XIE_MASK	MASK(REG_SAI_CSR_XIE_SHIFT + 4,\
-		REG_SAI_CSR_XIE_SHIFT)
-#define REG_SAI_CSR_WSIE	BIT(12)
-#define REG_SAI_CSR_SEIE	BIT(11)
-#define REG_SAI_CSR_FEIE	BIT(10)
-#define REG_SAI_CSR_FWIE	BIT(9)
-#define REG_SAI_CSR_FRIE	BIT(8)
-#define REG_SAI_CSR_FWDE	BIT(1)
-#define REG_SAI_CSR_FRDE	BIT(0)
-
-/* SAI Transmit and Receive Configuration 1 Register */
-#if defined(CONFIG_IMX8M) || defined(CONFIG_IMX93_A55)
-#define REG_SAI_CR1_RFW_MASK	0x7f
-#else
-#define REG_SAI_CR1_RFW_MASK	0x3f
-#endif
-
-/* SAI Transmit and Receive Configuration 2 Register */
-#define REG_SAI_CR2_SYNC	SET_BITS(31, 30, 1)
-#define REG_SAI_CR2_SYNC_MASK	MASK(31, 30)
-#define REG_SAI_CR2_MSEL_MASK	MASK(27, 26)
-#define REG_SAI_CR2_MSEL_BUS	SET_BITS(27, 26, 0)
-#define REG_SAI_CR2_MSEL_MCLK1	SET_BITS(27, 26, 1)
-#define REG_SAI_CR2_MSEL_MCLK2	SET_BITS(27, 26, 2)
-#define REG_SAI_CR2_MSEL_MCLK3	SET_BITS(27, 26, 3)
-#define REG_SAI_CR2_MSEL(id)	((id) << 26)
-#define REG_SAI_CR2_BCP		BIT(25)
-#define REG_SAI_CR2_BCD_MSTR	BIT(24)
-#define REG_SAI_CR2_BYP		BIT(23) /* BCLK bypass */
-#define REG_SAI_CR2_BYP_MASK	BIT(23)
-#define REG_SAI_CR2_DIV_MASK	0xff
-
-/* SAI Transmit and Receive Configuration 3 Register */
-#define REG_SAI_CR3_TRCE_MASK	MASK(23, 16)
-#define REG_SAI_CR3_TRCE(x)	(x << 16)
-#define REG_SAI_CR3_WDFL(x)	(x)
-#define REG_SAI_CR3_WDFL_MASK	0x1f
-
-/* SAI Transmit and Receive Configuration 4 Register */
-
-#define REG_SAI_CR4_FCONT	BIT(28)
-#define REG_SAI_CR4_FCOMB_SHIFT BIT(26)
-#define REG_SAI_CR4_FCOMB_SOFT  BIT(27)
-#define REG_SAI_CR4_FCOMB_MASK	MASK(27, 26)
-#define REG_SAI_CR4_FPACK_8     (0x2 << 24)
-#define REG_SAI_CR4_FPACK_16    (0x3 << 24)
-#define REG_SAI_CR4_FPACK_MASK  MASK(25, 24)
-#define REG_SAI_CR4_FRSZ(x)	(((x) - 1) << 16)
-#define REG_SAI_CR4_FRSZ_MASK	MASK(20, 16)
-#define REG_SAI_CR4_SYWD(x)	(((x) - 1) << 8)
-#define REG_SAI_CR4_SYWD_MASK	MASK(12, 8)
-#define REG_SAI_CR4_CHMOD	BIT(5)
-#define REG_SAI_CR4_CHMOD_MASK	BIT(5)
-#define REG_SAI_CR4_MF		BIT(4)
-#define REG_SAI_CR4_FSE		BIT(3)
-#define REG_SAI_CR4_FSP		BIT(1)
-#define REG_SAI_CR4_FSD_MSTR	BIT(0)
-
-/* SAI Transmit and Receive Configuration 5 Register */
-#define REG_SAI_CR5_WNW(x)	(((x) - 1) << 24)
-#define REG_SAI_CR5_WNW_MASK	MASK(28, 24)
-#define REG_SAI_CR5_W0W(x)	(((x) - 1) << 16)
-#define REG_SAI_CR5_W0W_MASK	MASK(20, 16)
-#define REG_SAI_CR5_FBT(x)	(((x) - 1) << 8)
-#define REG_SAI_CR5_FBT_MASK	MASK(12, 8)
-
-/* SAI MCLK Control Register */
-#define REG_SAI_MCTL_MCLK_EN	BIT(30)	/* MCLK Enable */
-#define REG_SAI_MCTL_MSEL_MASK	MASK(25, 24)
-#define REG_SAI_MCTL_MSEL(id)   ((id) << 24)
-#define REG_SAI_MCTL_MSEL_BUS	SET_BITS(25, 24, 0)
-#define REG_SAI_MCTL_MSEL_MCLK1	SET_BITS(25, 24, 1)
-#define REG_SAI_MCTL_MSEL_MCLK2	SET_BITS(25, 24, 2)
-#define REG_SAI_MCTL_MSEL_MCLK3	SET_BITS(25, 24, 3)
-#define REG_SAI_MCTL_DIV_EN	BIT(23)
-#define REG_SAI_MCTL_DIV_MASK	0xFF
-
-/* SAI VERID Register */
-#define REG_SAI_VER_ID_SHIFT	16
-#define REG_SAI_VER_ID_MASK	MASK(REG_SAI_VER_ID_SHIFT + 15,\
-		REG_SAI_VER_ID_SHIFT)
-#define REG_SAI_VER_EFIFO_EN	BIT(0)
-#define REG_SAI_VER_TSTMP_EN	BIT(1)
-
-/* SAI PARAM Register */
-#define REG_SAI_PAR_SPF_SHIFT	16
-#define REG_SAI_PAR_SPF_MASK	MASK(REG_SAI_PAR_SPF_SHIFT + 3,\
-		REG_SAI_PAR_SPF_SHIFT)
-#define REG_SAI_PAR_WPF_SHIFT	8
-#define REG_SAI_PAR_WPF_MASK	MASK(REG_SAI_PAR_WPF_SHIFT + 3,\
-		REG_SAI_PAR_WPF_SHIFT)
-#define REG_SAI_PAR_DLN_MASK	(0x0F)
-
-/* SAI MCLK Divide Register */
-#define REG_SAI_MDIV_MASK	0xFFFFF
-
-/* SAI type */
-#define REG_SAI_DMA		BIT(0)
-#define REG_SAI_USE_AC97	BIT(1)
-#define REG_SAI_NET		BIT(2)
-#define REG_SAI_TRA_SYN		BIT(3)
-#define REG_SAI_REC_SYN		BIT(4)
-#define REG_SAI_USE_I2S_SLAVE	BIT(5)
-
-#define REG_FMT_TRANSMITTER	0
-#define REG_FMT_RECEIVER	1
-
-/* SAI clock sources */
-#define REG_SAI_CLK_BUS		0
-#define REG_SAI_CLK_MAST1	1
-#define REG_SAI_CLK_MAST2	2
-#define REG_SAI_CLK_MAST3	3
-
-#define REG_SAI_MCLK_MAX	4
-
-/* SAI data transfer numbers per DMA request */
-#define REG_SAI_MAXBURST_TX 6
-#define REG_SAI_MAXBURST_RX 6
-
-#define SAI_FLAG_PMQOS   BIT(0)
-
-#if defined(CONFIG_IMX8M) || defined(CONFIG_IMX93_A55)
-#define SAI_FIFO_WORD_SIZE	128
-#elif defined CONFIG_IMX8ULP
-#define SAI_FIFO_WORD_SIZE	16
-#else
-#define SAI_FIFO_WORD_SIZE	64
-#endif
-
-extern const struct dai_driver sai_driver;
-
-/* SAI private data */
-struct sai_pdata {
-	struct sof_ipc_dai_config config;
-	struct sof_ipc_dai_sai_params params;
-};
-
-#endif /*__SOF_DRIVERS_SAI_H__ */
diff --git a/src/include/sof/drivers/sdma.h b/src/include/sof/drivers/sdma.h
deleted file mode 100644
index 62f1f1c4101d..000000000000
--- a/src/include/sof/drivers/sdma.h
+++ /dev/null
@@ -1,346 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- *
- * Copyright 2020 NXP
- *
- * Author: Paul Olaru <paul.olaru@nxp.com>
- */
-
-#ifndef __SOF_DRIVERS_SDMA_H__
-#define __SOF_DRIVERS_SDMA_H__
-
-#define SDMA_MC0PTR		0x0000 /* platform 0 control block */
-#define SDMA_INTR		0x0004 /* Active interrupts, W1C */
-#define SDMA_STOP_STAT		0x0008 /* Channel stop/status, W1C */
-#define SDMA_HSTART		0x000C /* Channel start */
-
-/* Prevent hardware requests from starting channels */
-#define SDMA_EVTOVR		0x0010 /* Event override */
-
-/* Set to 0 to prevent channels from ever starting */
-#define SDMA_DSPOVR		0x0014 /* Channel BP override */
-#define SDMA_HOSTOVR		0x0018 /* ARM platform override */
-
-/* Channels which are pending; you can also start channels here;
- * `done` instruction will clear this.
- */
-#define SDMA_EVTPEND		0x001C /* Pending events */
-
-/* Bit 0 resets the SDMA; bit 1 forces reschedule as if `done` was done */
-#define SDMA_RESET		0x0024 /* Reset register */
-
-/* New HW request for already pending/running channel; XRUN? */
-#define SDMA_EVTERR		0x0028 /* DMA request error */
-
-#define SDMA_INTRMASK		0x002C /* ARM platform interrupt mask */
-#define SDMA_PSW		0x0030 /* Schedule status */
-
-/* Mirror of SDMA_EVTERR which doesn't clear on reads */
-#define SDMA_EVTERRDBG		0x0034 /* DMA request error register */
-
-#define SDMA_CONFIG		0x0038 /* Configuration register */
-#define SDMA_CONFIG_ACR		BIT(4)
-#define SDMA_CONFIG_CSM_MSK	MASK(1, 0)
-#define SDMA_CONFIG_CSM_STATIC	SET_BITS(1, 0, 0) /* Static ctx switch */
-#define SDMA_CONFIG_CSM_DYN_LP	SET_BITS(1, 0, 1) /* Low power; unused */
-#define SDMA_CONFIG_CSM_DYN_NL	SET_BITS(1, 0, 2) /* No loops; unused */
-#define SDMA_CONFIG_CSM_DYN	SET_BITS(1, 0, 3) /* Fully dynamic ctx switch */
-
-#define SDMA_LOCK		0x003C /* Lock firmware until reset */
-
-/* OnCE debug registers; unsupported, mentioned for completeness */
-/* Should I use these for accessing contexts?! */
-#define SDMA_ONCE_ENB		0x0040 /* Enable OnCE */
-#define SDMA_ONCE_DATA		0x0044 /* OnCE data register */
-#define SDMA_ONCE_INSTR		0x0048 /* OnCE instruction register */
-#define SDMA_ONCE_STAT		0x004C /* OnCE status register */
-#define SDMA_ONCE_CMD		0x0050 /* OnCE command register */
-
-/* Illegal instruction trap handler address */
-#define SDMA_ILLINSTADDR	0x0058
-
-#define SDMA_CHN0ADDR		0x005C /* Channel 0 boot address */
-
-/* Hardware DMA requests 0-47, useful for debug */
-#define SDMA_EVT_MIRROR		0x0060 /* DMA requests */
-#define SDMA_EVT_MIRROR2	0x0064 /* DMA requests */
-
-/* Cross-trigger events configuration registers
- * Unsupported by this driver
- */
-#define SDMA_XTRIG_CONF1	0x0070
-#define SDMA_XTRIG_CONF2	0x0074
-
-/* Channel priority registers; priorities 1-7 are useful, 0 means don't
- * start. Higher number priority is higher priority.
- */
-#define SDMA_CHNPRI(chan)	(0x0100 + 4 * (chan))
-
-#define SDMA_DEFPRI		4
-#define SDMA_MAXPRI		7
-
-#define SDMA_HWEVENTS_COUNT	48
-
-/* Channel to HW mapping; no default values */
-#define SDMA_CHNENBL(hwchan)	(0x0200 + 4 * (hwchan))
-
-/* SDMA DONE0/DONE1 configurations; each of 32 events can stop channels
- * from 0 to 7
- */
-#define SDMA_DONE0_CONFIG	0x1000
-#define SDMA_DONE1_CONFIG	0x1004
-
-#define SDMA_DONE0_CONFIG_DONE_SEL	BIT(7)
-#define SDMA_DONE0_CONFIG_DONE_DIS	BIT(6)
-
-#define SDMA_WATERMARK_LEVEL_N_FIFOS(x)		SET_BITS(15, 12, x)
-#define SDMA_WATERMARK_LEVEL_OFF_FIFOS(x)	SET_BITS(19, 16, x)
-#define SDMA_WATERMARK_LEVEL_WORDS_PER_FIFO(x)	SET_BITS(31, 28, x)
-#define SDMA_WATERMARK_LEVEL_SW_DONE		BIT(23)
-#define SDMA_WATERMARK_LEVEL_SW_DONE_SEL_OFF	24
-
-/* Buffer descriptor first word */
-/* Count: Data buffer size, in words */
-#define SDMA_BD_COUNT_MASK	MASK(15, 0)
-#define SDMA_BD_COUNT(n)	SET_BITS(15, 0, n)
-#define SDMA_BD_MAX_COUNT	SDMA_BD_COUNT_MASK
-/* Done bit, when 1 SDMA is active */
-#define SDMA_BD_DONE		BIT(16)
-/* Wrap bit, last BD in circular buffer */
-#define SDMA_BD_WRAP		BIT(17)
-/* Continuous, transfer can bleed into next BD */
-#define SDMA_BD_CONT		BIT(18)
-/* Interrupt, should DSP receive interrupt when this BD is complete? */
-#define SDMA_BD_INT		BIT(19)
-/* Error (status bit), if some error happened while processing this BD */
-#define SDMA_BD_ERROR		BIT(20)
-/* Last: SDMA sets it when there is no more data to transfer */
-#define SDMA_BD_LAST		BIT(21)
-/* Bit 22 is reserved */
-/* Bit 23 is undocumented, but used in existing drivers; I think it
- * means that buf_xaddr contains a valid value
- */
-#define SDMA_BD_EXTD		BIT(23)
-
-/* CMD: Command, differentiator for functionality of scripts; can also
- * hold error codes returned by SDMA scripts.
- */
-#define SDMA_BD_CMD_MASK	MASK(31, 24)
-#define SDMA_BD_CMD(cmd)	SET_BITS(31, 24, cmd)
-
-/* We don't need more than 4 buffer descriptors per channel */
-#define SDMA_MAX_BDS		4
-
-#define SDMA_CMD_C0_SET_PM		0x4
-#define SDMA_CMD_C0_SET_DM		0x1
-#define SDMA_CMD_C0_GET_PM		0x8
-#define SDMA_CMD_C0_GET_DM		0x2
-#define SDMA_CMD_C0_SETCTX(chan)	(((chan) << 3) | 7)
-#define SDMA_CMD_C0_GETCTX(chan)	(((chan) << 3) | 6)
-/* Used by the actual data transfer scripts, the width of each
- * elementary transfer; set in command field. Default is 32-bit.
- */
-#define SDMA_CMD_XFER_SIZE(s) ((s) == 8 ? 1 : (s) == 16 ? 2 : (s) == 24 ? 3 : 0)
-
-#define SDMA_SRAM_CONTEXTS_BASE		0x800
-
-/* SDMA channel types; you can add more as required */
-/* AP2AP is memory to memory */
-#define SDMA_CHAN_TYPE_AP2AP		0
-/* AP2MCU is host to DAI, slow path but works with DSP OCRAM */
-#define SDMA_CHAN_TYPE_AP2MCU		1
-#define SDMA_CHAN_TYPE_MCU2AP		2
-/* SHP2MCU is host to DAI, faster but only works with SDRAM */
-#define SDMA_CHAN_TYPE_SHP2MCU		3
-#define SDMA_CHAN_TYPE_MCU2SHP		4
-/* used for multi-fifo script */
-#define SDMA_CHAN_TYPE_SAI2MCU		5
-
-/* TODO check and move these to platform data */
-#define SDMA_SCRIPT_AP2AP_OFF		644
-#define SDMA_SCRIPT_AP2MCU_OFF		685
-#define SDMA_SCRIPT_MCU2AP_OFF		749
-#define SDMA_SCRIPT_SHP2MCU_OFF		893
-#define SDMA_SCRIPT_MCU2SHP_OFF		962
-#define SDMA_SCRIPT_SAI2MCU_OFF		6710
-
-#if CONFIG_HAVE_SDMA_FIRMWARE
-
-/*
- * From "sdma_script_code_imx7d_4_5.h"
- */
-
-/* SDMA RAM image start address and size */
-#define RAM_CODE_START_ADDR     6144
-#define RAM_CODE_SIZE           1315
-
-/* buffer that holds the SDMA RAM image */
-static const short sdma_code[] = {
-0xc1e5, 0x57db, 0x52f3, 0x6a01, 0x52fb, 0x6ad3, 0x52fb, 0x1a1c,
-0x6ac3, 0x62e8, 0x0211, 0x3aff, 0x0830, 0x02d0, 0x7c3f, 0x008f,
-0x003f, 0x00d5, 0x7d01, 0x008d, 0x05a0, 0x5deb, 0x0478, 0x7d03,
-0x0479, 0x7d1c, 0x7c20, 0x0479, 0x7c15, 0x56ee, 0x0660, 0x7d05,
-0x6509, 0x7e33, 0x620a, 0x7e31, 0x9829, 0x620a, 0x7e2e, 0x6509,
-0x7e2c, 0x0512, 0x0512, 0x02ad, 0x6ac8, 0x7f27, 0x2003, 0x4800,
-0x7ced, 0x9841, 0x7802, 0x6209, 0x6ac8, 0x9840, 0x0015, 0x7802,
-0x620a, 0x6ac8, 0x9840, 0x0015, 0x0015, 0x7802, 0x620b, 0x6ac8,
-0x7c14, 0x6ddf, 0x7f12, 0x077f, 0x7d09, 0x52fb, 0x1a04, 0x6ac3,
-0x6ad3, 0x62c8, 0x2a04, 0x6ac8, 0x52fb, 0x6ad3, 0x0000, 0x55eb,
-0x4d00, 0x7d07, 0xc1fc, 0x57db, 0x9806, 0x0007, 0x68cc, 0x680c,
-0xc215, 0xc20c, 0x9801, 0xc1d9, 0xc1e5, 0x57db, 0x52f3, 0x6a01,
-0x080f, 0x0011, 0x18ff, 0x00bf, 0x5ce3, 0x00d5, 0x7d01, 0x008d,
-0x05a0, 0x5deb, 0x56fb, 0x0478, 0x7d03, 0x0479, 0x7d28, 0x7c33,
-0x0479, 0x7c1a, 0x0b70, 0x0311, 0x53eb, 0x0360, 0x7d05, 0x6509,
-0x7e5f, 0x620a, 0x7e5d, 0x9880, 0x620a, 0x7e5a, 0x6509, 0x7e58,
-0x0512, 0x0512, 0x02ad, 0x5a06, 0x7f53, 0x2003, 0x4800, 0x7ced,
-0x0b70, 0x0311, 0x5313, 0x98b0, 0xd8c8, 0x6209, 0x5a06, 0x069c,
-0x2701, 0x2001, 0x4f00, 0x7cf9, 0x4800, 0x7cf6, 0x98af, 0x0015,
-0xd8c8, 0x620a, 0x5a06, 0x069c, 0x2701, 0x2001, 0x4f00, 0x7cf9,
-0x4800, 0x7cf6, 0x98af, 0x0015, 0x0015, 0xd8c8, 0x620b, 0x5a06,
-0x069c, 0x2701, 0x2001, 0x4f00, 0x7cf9, 0x4800, 0x7cf6, 0x7c28,
-0x57db, 0x0777, 0x7c0c, 0x0710, 0x3f0f, 0x0717, 0x0717, 0x0e70,
-0x0611, 0x0c70, 0x0411, 0x069c, 0x069f, 0x0c01, 0x5c06, 0x0000,
-0x54e3, 0x57db, 0x55eb, 0x4d00, 0x7d16, 0xc1fc, 0x57db, 0x9860,
-0x56fb, 0x57db, 0x048f, 0x0711, 0x3ff0, 0x0715, 0x0715, 0x0715,
-0x0715, 0x0410, 0x0411, 0x3c0f, 0x1c01, 0x0417, 0x0417, 0x0006,
-0x0007, 0x680c, 0xc215, 0xc20c, 0x985d, 0xc1d9, 0xc1e5, 0x57db,
-0x5fe3, 0x57e3, 0x52f3, 0x6a21, 0x008f, 0x00d5, 0x7d01, 0x008d,
-0x05a0, 0x5deb, 0x56fb, 0x0478, 0x7d03, 0x0479, 0x7d2a, 0x7c31,
-0x0479, 0x7c20, 0x0b70, 0x0311, 0x53eb, 0x0f00, 0x0360, 0x7d05,
-0x6509, 0x7e37, 0x620a, 0x7e35, 0x9901, 0x620a, 0x7e32, 0x6509,
-0x7e30, 0x0512, 0x0512, 0x02ad, 0x0760, 0x7c02, 0x5a06, 0x9909,
-0x5a26, 0x7f27, 0x1f01, 0x2003, 0x4800, 0x7ce8, 0x0b70, 0x0311,
-0x5313, 0x992a, 0x0015, 0x7804, 0x6209, 0x5a06, 0x6209, 0x5a26,
-0x9929, 0x0015, 0x0015, 0x7804, 0x620a, 0x5a06, 0x620a, 0x5a26,
-0x9929, 0x0015, 0x0015, 0x0015, 0x7804, 0x620b, 0x5a06, 0x620b,
-0x5a26, 0x7c07, 0x0000, 0x55eb, 0x4d00, 0x7d06, 0xc1fc, 0x57e3,
-0x98e4, 0x0007, 0x680c, 0xc215, 0xc20c, 0x98e1, 0x0b70, 0x0311,
-0x5313, 0x076c, 0x7c01, 0xc1d9, 0x5efb, 0x068a, 0x076b, 0x7c01,
-0xc1d9, 0x5ef3, 0x59db, 0x58d3, 0x018f, 0x0110, 0x390f, 0x008b,
-0xc13c, 0x7d2b, 0x5ac0, 0x5bc8, 0xc14e, 0x7c27, 0x0388, 0x0689,
-0x5ce3, 0x0dff, 0x0511, 0x1dff, 0x05bc, 0x073e, 0x4d00, 0x7d18,
-0x0870, 0x0011, 0x077e, 0x7d09, 0x077d, 0x7d02, 0x5228, 0x9961,
-0x52f8, 0x54db, 0x02bc, 0x02cc, 0x7c09, 0x077c, 0x7d02, 0x5228,
-0x996a, 0x52f8, 0x54d3, 0x02bc, 0x02cc, 0x7d09, 0x0400, 0x9958,
-0x008b, 0x52c0, 0x53c8, 0xc159, 0x7dd6, 0x0200, 0x9948, 0x08ff,
-0x00bf, 0x077f, 0x7d15, 0x0488, 0x00d5, 0x7d01, 0x008d, 0x05a0,
-0x5deb, 0x028f, 0x0212, 0x0212, 0x3aff, 0x05da, 0x7c02, 0x073e,
-0x9995, 0x02a4, 0x02dd, 0x7d02, 0x073e, 0x9995, 0x075e, 0x9995,
-0x55eb, 0x4d00, 0x7c02, 0x0598, 0x5deb, 0x52f3, 0x54fb, 0x076a,
-0x7d26, 0x076c, 0x7d01, 0x99d2, 0x076b, 0x7c57, 0x0769, 0x7d04,
-0x0768, 0x7d02, 0x0e01, 0x99ac, 0x5893, 0x00d6, 0x7d01, 0x008e,
-0x5593, 0x05a0, 0x5d93, 0x06a0, 0x7802, 0x5502, 0x5d04, 0x7c1d,
-0x4e00, 0x7c08, 0x0769, 0x7d03, 0x5502, 0x7e17, 0x99b9, 0x5d04,
-0x7f14, 0x0689, 0x5093, 0x4800, 0x7d01, 0x99a4, 0x9a1d, 0x0015,
-0x7806, 0x5502, 0x5d04, 0x074f, 0x5502, 0x5d24, 0x072f, 0x7c01,
-0x9a1d, 0x0017, 0x076f, 0x7c01, 0x2001, 0x5593, 0x009d, 0x0007,
-0xda24, 0x9970, 0x6cd3, 0x0769, 0x7d04, 0x0768, 0x7d02, 0x0e01,
-0x99e1, 0x5893, 0x00d6, 0x7d01, 0x008e, 0x5593, 0x05a0, 0x5d93,
-0x06a0, 0x7802, 0x5502, 0x6dc8, 0x7c0f, 0x4e00, 0x7c08, 0x0769,
-0x7d03, 0x5502, 0x7e09, 0x99ee, 0x6dc8, 0x7f06, 0x0689, 0x5093,
-0x4800, 0x7d01, 0x99d9, 0x9a1d, 0x9a17, 0x6ac3, 0x0769, 0x7d04,
-0x0768, 0x7d02, 0x0e01, 0x9a04, 0x5893, 0x00d6, 0x7d01, 0x008e,
-0x5593, 0x05a0, 0x5d93, 0x06a0, 0x7802, 0x65c8, 0x5d04, 0x7c0f,
-0x4e00, 0x7c08, 0x0769, 0x7d03, 0x65c8, 0x7e09, 0x9a11, 0x5d04,
-0x7f06, 0x0689, 0x5093, 0x4800, 0x7d01, 0x99fc, 0x9a1d, 0x5593,
-0x009d, 0x0007, 0x6cff, 0xda24, 0x9970, 0x0000, 0x54e3, 0x55eb,
-0x4d00, 0x7c01, 0x9970, 0x9958, 0x54e3, 0x55eb, 0x0aff, 0x0211,
-0x1aff, 0x077f, 0x7c02, 0x05a0, 0x9a31, 0x009d, 0x058c, 0x05ba,
-0x05a0, 0x0210, 0x04ba, 0x04ad, 0x0454, 0x0006, 0xc1d9, 0xc1e5,
-0x57db, 0x52f3, 0x6a05, 0x5ce3, 0x080f, 0x0011, 0x18ff, 0x00bf,
-0x00d5, 0x7d01, 0x008d, 0x05a0, 0x56fb, 0x0478, 0x7d03, 0x0479,
-0x7d28, 0x7c1a, 0x0479, 0x7c31, 0x0b70, 0x0311, 0x53eb, 0x5206,
-0x7e60, 0x0360, 0x7d02, 0x0210, 0x0212, 0x6a09, 0x7f5a, 0x0212,
-0x6a09, 0x7f57, 0x0212, 0x6a09, 0x7f54, 0x2003, 0x4800, 0x7cef,
-0x0b70, 0x0311, 0x5313, 0x9a88, 0x0015, 0x0015, 0xdaa1, 0x5206,
-0x6a0b, 0x069c, 0x2001, 0x2701, 0x4f00, 0x7cf9, 0x4800, 0x7cf6,
-0x9a87, 0x0015, 0xdaa1, 0x5206, 0x6a0a, 0x069c, 0x2001, 0x2701,
-0x4f00, 0x7cf9, 0x4800, 0x7cf6, 0x9a87, 0xdaa1, 0x5206, 0x6a09,
-0x069c, 0x2001, 0x2701, 0x4f00, 0x7cf9, 0x4800, 0x7cf6, 0x7c29,
-0x6a28, 0x7f27, 0x57db, 0x0777, 0x7c0c, 0x0710, 0x3f0f, 0x0717,
-0x0717, 0x0e70, 0x0611, 0x0c70, 0x0411, 0x069c, 0x069f, 0x0c01,
-0x5c06, 0x0000, 0x54e3, 0x57db, 0x4d00, 0x7d15, 0xc1fc, 0x57db,
-0x9a3b, 0x56fb, 0x57db, 0x048f, 0x0711, 0x3ff0, 0x0715, 0x0715,
-0x0715, 0x0715, 0x0410, 0x0411, 0x3c0f, 0x1c01, 0x0417, 0x0417,
-0x0006, 0xc279, 0x0454, 0xc20c, 0x9a38, 0xc1d9, 0xc1e5, 0x57db,
-0x52f3, 0x6a05, 0x008f, 0x00d5, 0x7d01, 0x008d, 0x05a0, 0x56fb,
-0x0478, 0x7d03, 0x0479, 0x7d29, 0x7c1f, 0x0479, 0x7c2e, 0x5de3,
-0x0d70, 0x0511, 0x55ed, 0x0f00, 0x0760, 0x7d02, 0x5206, 0x9ad1,
-0x5226, 0x7e33, 0x0560, 0x7d02, 0x0210, 0x0212, 0x6a09, 0x7f2d,
-0x0212, 0x6a09, 0x7f2a, 0x0212, 0x6a09, 0x7f27, 0x1f01, 0x2003,
-0x4800, 0x7cea, 0x55e3, 0x9afc, 0x0015, 0x0015, 0x0015, 0x7804,
-0x5206, 0x6a0b, 0x5226, 0x6a0b, 0x9afb, 0x0015, 0x0015, 0x7804,
-0x5206, 0x6a0a, 0x5226, 0x6a0a, 0x9afb, 0x0015, 0x7804, 0x5206,
-0x6a09, 0x5226, 0x6a09, 0x7c09, 0x6a28, 0x7f07, 0x0000, 0x57db,
-0x4d00, 0x7d05, 0xc1fc, 0x57db, 0x9aba, 0xc279, 0x0454, 0xc20c,
-0x9ab7, 0xc1e5, 0x57db, 0x52f3, 0x6a05, 0x56fb, 0x028e, 0x1a94,
-0x6ac3, 0x62c8, 0x0269, 0x7d26, 0x1e94, 0x6ec3, 0x6ed3, 0x62c8,
-0x0a01, 0x0211, 0x6ac8, 0x2694, 0x1e98, 0x6ec3, 0x62c8, 0x2698,
-0x6ec3, 0x0260, 0x7d0f, 0x1e98, 0x6ec3, 0x62c8, 0x026c, 0x7d03,
-0x2698, 0x6ec3, 0x9b48, 0x0a10, 0x0211, 0x6ed3, 0x6ac8, 0x2698,
-0x6ec3, 0x9b58, 0x62c8, 0x9b34, 0x6a09, 0x7f18, 0x2501, 0x4d00,
-0x7d1f, 0x9b1c, 0x6ee3, 0x008f, 0x05d8, 0x7d01, 0x008d, 0x62c8,
-0x6a09, 0x7f0c, 0x2501, 0x2001, 0x7cfa, 0x57db, 0x4d00, 0x7d10,
-0x6a28, 0x7f04, 0x0000, 0xc1fc, 0x57db, 0x9b0d, 0x0007, 0x6204,
-0x6a0c, 0x9b55, 0x6a28, 0x7ffa, 0x6204, 0xc27c, 0x0458, 0x0454,
-0x08ff, 0x0011, 0x18ff, 0x00bc, 0x00cd, 0x7c01, 0x9b48, 0x6a28,
-0x7fed, 0x6204, 0xc27c, 0xc20c, 0x9b0a, 0xc1d9, 0xc1e5, 0x57db,
-0x52f3, 0x6a05, 0x56fb, 0x028e, 0x1a94, 0x5202, 0x0269, 0x7d1d,
-0x1e94, 0x5206, 0x0248, 0x5a06, 0x2694, 0x1e98, 0x5206, 0x024c,
-0x5a06, 0x2698, 0x1e98, 0x5206, 0x0260, 0x7c0a, 0x2698, 0x5206,
-0x026e, 0x7d23, 0x6a09, 0x7f1d, 0x2501, 0x4d00, 0x7d24, 0x9b7a,
-0x6a28, 0x7f17, 0x6204, 0xc27c, 0x9bab, 0x008f, 0x05d8, 0x7d01,
-0x008d, 0x05a0, 0x5206, 0x026e, 0x7d10, 0x6a09, 0x7f0a, 0x2001,
-0x7cf9, 0x6a28, 0x7f06, 0x0000, 0x4d00, 0x7d0d, 0xc1fc, 0x57db,
-0x9b6a, 0x0007, 0x6204, 0x6a0c, 0x9ba8, 0x6a28, 0x7ffa, 0x6204,
-0xc27c, 0x0458, 0x0454, 0x6a28, 0x7ff4, 0xc20c, 0x9b67, 0xdbf3,
-0x57db, 0x52f3, 0x6a05, 0x69c7, 0x008f, 0x00d5, 0x7d01, 0x008d,
-0x05a0, 0x0478, 0x7d03, 0x0479, 0x7d1c, 0x7c15, 0x0479, 0x7c1e,
-0x56ee, 0x62c8, 0x7e28, 0x0660, 0x7d02, 0x0210, 0x0212, 0x6a09,
-0x7f22, 0x0212, 0x6a09, 0x7f1f, 0x0212, 0x6a09, 0x7f1c, 0x2003,
-0x4800, 0x7cef, 0x9be2, 0x0015, 0x0015, 0x7802, 0x62c8, 0x6a0b,
-0x9be1, 0x0015, 0x7802, 0x62c8, 0x6a0a, 0x9be1, 0x7802, 0x62c8,
-0x6a09, 0x7c09, 0x6a28, 0x7f07, 0x4d00, 0x7d07, 0x52d3, 0x0801,
-0x5802, 0x0400, 0x9bb3, 0xc279, 0x0454, 0x52d3, 0x0801, 0x5802,
-0x0401, 0xdc0b, 0x9bb0, 0x0b70, 0x0311, 0x5313, 0x5fdb, 0x070a,
-0x58d3, 0x008b, 0x5efb, 0xc13c, 0x7d15, 0x5ac0, 0x5bc8, 0xc14e,
-0x7c11, 0x0388, 0x5df0, 0x0dff, 0x0511, 0x1dff, 0x05bc, 0x4d00,
-0x7d04, 0x9c0a, 0x0708, 0x5fdb, 0x070a, 0x008b, 0x52c3, 0x53cb,
-0xc159, 0x7dec, 0x0200, 0x9bfb, 0x6e01, 0x610b, 0x7e2f, 0x620b,
-0x7e2d, 0x630b, 0x7e2b, 0x0d0c, 0x0417, 0x0417, 0x0417, 0x049d,
-0x1d08, 0x05cc, 0x7c01, 0x0d0c, 0x6ad1, 0x0f00, 0x0742, 0x6fc8,
-0x6fdd, 0x7f1c, 0x008e, 0x009d, 0x6801, 0x670b, 0x7e17, 0x6bd5,
-0x0804, 0x7802, 0x6fc8, 0x0712, 0x7c11, 0x670b, 0x7e0f, 0x0804,
-0x7802, 0x6fc8, 0x0712, 0x7c0a, 0x6fdd, 0x7f08, 0x69d1, 0x0f01,
-0x6fc8, 0x6fdd, 0x7f03, 0x0101, 0x0400, 0x9c20, 0x0007, 0x68ff,
-0x680c, 0x0200, 0x9c20, 0xdc90, 0x57db, 0x52f3, 0x6a05, 0x52fb,
-0x6ac7, 0x008f, 0x00d5, 0x7d01, 0x008d, 0x05a0, 0x0478, 0x7d03,
-0x0479, 0x7d1c, 0x7c15, 0x0479, 0x7c1e, 0x56ee, 0x62c8, 0x7e28,
-0x0660, 0x7d02, 0x0210, 0x0212, 0x6a09, 0x7f22, 0x0212, 0x6a09,
-0x7f1f, 0x0212, 0x6a09, 0x7f1c, 0x2003, 0x4800, 0x7cef, 0x9c7f,
-0x0015, 0x0015, 0x7802, 0x62c8, 0x6a0b, 0x9c7e, 0x0015, 0x7802,
-0x62c8, 0x6a0a, 0x9c7e, 0x7802, 0x62c8, 0x6a09, 0x7c09, 0x6a28,
-0x7f07, 0x4d00, 0x7d07, 0x52d3, 0x0801, 0x5802, 0x0400, 0x9c4f,
-0xc279, 0x0454, 0x52d3, 0x0801, 0x5802, 0x0401, 0xdca8, 0x9c4c,
-0x0b70, 0x0311, 0x5313, 0x5fdb, 0x070a, 0x58d3, 0x008b, 0x5efb,
-0xc13c, 0x7d15, 0x5ac0, 0x5bc8, 0xc14e, 0x7c11, 0x0388, 0x5df0,
-0x0dff, 0x0511, 0x1dff, 0x05bc, 0x4d00, 0x7d04, 0x9ca7, 0x0708,
-0x5fdb, 0x070a, 0x008b, 0x52c3, 0x53cb, 0xc159, 0x7dec, 0x0200,
-0x9c98, 0xdd02, 0x52f3, 0x6a01, 0x57db, 0x52fb, 0x077f, 0x7d02,
-0x6ad3, 0x9cbb, 0x6ad7, 0x008f, 0x38ff, 0x00d5, 0x7d01, 0x008d,
-0x05a0, 0x5deb, 0x0478, 0x7d03, 0x0479, 0x7d1c, 0x7c20, 0x0479,
-0x7c15, 0x56ee, 0x0660, 0x7d05, 0x6509, 0x7e2a, 0x620a, 0x7e28,
-0x9cd5, 0x620a, 0x7e25, 0x6509, 0x7e23, 0x0512, 0x0512, 0x02ad,
-0x6ac8, 0x7f1e, 0x2003, 0x4800, 0x7ced, 0x9ced, 0x7802, 0x6209,
-0x6ac8, 0x9cec, 0x0015, 0x7802, 0x620a, 0x6ac8, 0x9cec, 0x0015,
-0x0015, 0x7802, 0x620b, 0x6ac8, 0x7c0b, 0x6ddf, 0x7f09, 0x0000,
-0x55eb, 0x4d00, 0x7d09, 0x52d3, 0x0801, 0x5802, 0x0400, 0x9cb4,
-0x0007, 0x68cc, 0x680c, 0xc215, 0x52d3, 0x0801, 0x5802, 0x0401,
-0xdd1a, 0x9cb2, 0x0b70, 0x0311, 0x5313, 0x5fdb, 0x070a, 0x58d3,
-0x008b, 0x5efb, 0xc13c, 0x7d15, 0x5ac0, 0x5bc8, 0xc14e, 0x7c11,
-0x0388, 0x5df0, 0x0dff, 0x0511, 0x1dff, 0x05bc, 0x4d00, 0x7d04,
-0x9d19, 0x0708, 0x5fdb, 0x070a, 0x008b, 0x52c3, 0x53cb, 0xc159,
-0x7dec, 0x0200, 0x9d0a
-};
-#endif
-
-#endif /* __SOF_DRIVERS_SDMA_H__ */
diff --git a/src/include/sof/drivers/spi.h b/src/include/sof/drivers/spi.h
deleted file mode 100644
index 1af887100a98..000000000000
--- a/src/include/sof/drivers/spi.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- *
- * Copyright(c) 2017 Intel Corporation. All rights reserved.
- *
- * Author: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
- */
-
-#ifndef __SOF_DRIVERS_SPI_H__
-#define __SOF_DRIVERS_SPI_H__
-
-#include <stddef.h>
-#include <stdint.h>
-
-enum spi_type {
-	SOF_SPI_INTEL_SLAVE,
-	SOF_SPI_INTEL_MASTER,
-};
-
-enum spi_xfer_direction {
-	SPI_DIR_RX,
-	SPI_DIR_TX,
-};
-
-struct spi_plat_fifo_data {
-	uint32_t handshake;
-};
-
-struct spi_platform_data {
-	uint32_t base;
-	struct spi_plat_fifo_data fifo[2];
-	enum spi_type type;
-};
-
-struct spi;
-
-int spi_push(struct spi *spi, const void *data, size_t size);
-int spi_probe(struct spi *spi);
-struct spi *spi_get(enum spi_type type);
-int spi_install(const struct spi_platform_data *plat, size_t n);
-void spi_init(void);
-
-#endif /* __SOF_DRIVERS_SPI_H__ */
diff --git a/src/include/sof/ut.h b/src/include/sof/ut.h
index 9fa30fbf3a59..97dd7801941e 100644
--- a/src/include/sof/ut.h
+++ b/src/include/sof/ut.h
@@ -10,7 +10,7 @@
 
 /* UT_STATIC makes function unit-testable (non-static) when built for unit tests
  */
-#if defined UNIT_TEST || defined __ZEPHYR__  || CONFIG_LIBRARY_STATIC
+#if defined UNIT_TEST || defined __ZEPHYR__  || CONFIG_LIBRARY
 #define UT_STATIC
 #else
 #define UT_STATIC static
diff --git a/src/ipc/ipc3/handler.c b/src/ipc/ipc3/handler.c
index 25831cf1c772..e1b8df9eca9e 100644
--- a/src/ipc/ipc3/handler.c
+++ b/src/ipc/ipc3/handler.c
@@ -975,15 +975,6 @@ static int ipc_glb_gdb_debug(uint32_t header)
 #if CONFIG_GDBSTUB
 	ipc_enter_gdb = true;
 	return 0;
-// TODO: remove old GDB stub?
-#elif CONFIG_GDB_DEBUG
-	gdb_init_debug_exception();
-	gdb_init();
-	/* TODO: this asm should be in arch/include/debug/debug.h
-	 * with a generic name and trigger debug exception
-	 */
-	asm volatile("_break 0, 0");
-	return 0;
 #else
 	return -EINVAL;
 #endif
diff --git a/src/platform/CMakeLists.txt b/src/platform/CMakeLists.txt
index e43c21e1ac0d..57c10444a23e 100644
--- a/src/platform/CMakeLists.txt
+++ b/src/platform/CMakeLists.txt
@@ -2,31 +2,4 @@
 
 if(CONFIG_LIBRARY)
 	add_subdirectory(library)
-	return()
-endif()
-
-if(CONFIG_TIGERLAKE)
-	add_subdirectory(tigerlake)
-elseif(CONFIG_IMX8 OR CONFIG_IMX8X)
-	add_subdirectory(imx8)
-elseif(CONFIG_IMX8M)
-	add_subdirectory(imx8m)
-elseif(CONFIG_IMX8M_CM7)
-	add_subdirectory(imx8m_cm7)
-elseif(CONFIG_IMX8ULP)
-	add_subdirectory(imx8ulp)
-elseif(CONFIG_AMD)
-	add_subdirectory(amd)
-elseif(CONFIG_MT8186)
-	add_subdirectory(mt8186)
-elseif(CONFIG_MT8188)
-	add_subdirectory(mt8188)
-elseif(CONFIG_MT8195)
-        add_subdirectory(mt8195)
-elseif(CONFIG_MT8196)
-        add_subdirectory(mt8196)
-elseif(CONFIG_MT8365)
-	add_subdirectory(mt8365)
-elseif(PLATFORM STREQUAL "qemu_xtensa")
-	add_subdirectory(qemu_xtensa)
 endif()
diff --git a/src/platform/Kconfig b/src/platform/Kconfig
index cc86bb74c197..46758df1c1dd 100644
--- a/src/platform/Kconfig
+++ b/src/platform/Kconfig
@@ -59,13 +59,6 @@ config LIBRARY
 	  Library builds are not intended to be run on DSP, but to be used by
 	  user-space applications.
 
-config LIBRARY_STATIC
-	bool "Build Library as static archive"
-	depends on LIBRARY
-	help
-	  Select if you want to build a static library otherwise a dynamic
-	  shared library will be built.
-
 config ZEPHYR_POSIX
 	bool "Build for Zephyr native_posix board"
 	help
@@ -107,9 +100,6 @@ config IMX8
 	select DUMMY_DMA
 	select XT_WAITI_DELAY
 	select IMX
-	select IMX_EDMA
-	select IMX_ESAI
-	select IMX_INTERRUPT_IRQSTEER
 	help
 	  Select if your target platform is imx8-compatible
 
@@ -123,9 +113,6 @@ config IMX8X
 	select DUMMY_DMA
 	select XT_WAITI_DELAY
 	select IMX
-	select IMX_EDMA
-	select IMX_ESAI
-	select IMX_INTERRUPT_IRQSTEER
 	help
 	  Select if your target platform is imx8x-compatible
 
@@ -139,9 +126,6 @@ config IMX8M
 	select DUMMY_DMA
 	select XT_WAITI_DELAY
 	select IMX
-	select IMX_SDMA
-	select IMX_MICFIL
-	select IMX_INTERRUPT_IRQSTEER
 	help
 	  Select if your target platform is imx8m-compatible
 
@@ -163,8 +147,6 @@ config IMX8ULP
 	select DUMMY_DMA
 	select XT_WAITI_DELAY
 	select IMX
-	select IMX_EDMA
-	select IMX_INTERRUPT_GENERIC
 	help
 	 Select if your target platform is imx8ulp-compatible.
 	 imx.8ulp support dsp.
@@ -187,18 +169,6 @@ config IMX95
 	help
 	  Select if your target platform is imx95-compatible.
 
-config RENOIR
-	bool "Build for Renoir"
-	select XT_INTERRUPT_LEVEL_5
-	select XT_INTERRUPT_LEVEL_3
-	select XT_INTERRUPT_LEVEL_1
-	select XT_INTERRUPT_LEVEL_4
-	select XT_WAITI_DELAY
-	select AMD
-	select SCHEDULE_DMA_MULTI_CHANNEL
-	help
-	 Select if your target platform is renoir-compatible
-
 config REMBRANDT
 	bool "Build for Rembrandt"
 	select XT_INTERRUPT_LEVEL_5
@@ -212,32 +182,6 @@ config REMBRANDT
 	help
 	 Select if your target platform is rembrandt-compatible
 
-config VANGOGH
-	bool "Build for Vangogh"
-	select XT_INTERRUPT_LEVEL_5
-	select XT_INTERRUPT_LEVEL_3
-	select XT_INTERRUPT_LEVEL_1
-	select XT_INTERRUPT_LEVEL_4
-	select XT_WAITI_DELAY
-	select XTENSA_EXCLUSIVE
-	select AMD
-	select SCHEDULE_DMA_MULTI_CHANNEL
-	help
-	 Select if your target platform is vangogh-compatible
-
-config ACP_6_3
-	bool "Build for ACP_6_3"
-	select XT_INTERRUPT_LEVEL_5
-	select XT_INTERRUPT_LEVEL_3
-	select XT_INTERRUPT_LEVEL_1
-	select XT_INTERRUPT_LEVEL_4
-	select XT_WAITI_DELAY
-	select XTENSA_EXCLUSIVE
-	select AMD
-	select SCHEDULE_DMA_MULTI_CHANNEL
-	help
-	 Select if your target platform is acp_6_3-compatible
-
 config ACP_7_0
 	bool "Build for ACP_7_0"
 	select XT_INTERRUPT_LEVEL_5
@@ -264,65 +208,6 @@ config ACP_7_X
 	help
 	 Select if your target platform is acp_7_x-compatible
 
-config MT8186
-	bool "Build for MTK MT8186 (XTOS)"
-	select XT_INTERRUPT_LEVEL_1
-	select XT_INTERRUPT_LEVEL_2
-	select XT_INTERRUPT_LEVEL_3
-	select XT_INTERRUPT_LEVEL_4
-	select DUMMY_DMA
-	select HOST_PTABLE
-	select XT_WAITI_DELAY
-	select MEDIATEK
-	select XTENSA_EXCLUSIVE
-	select SCHEDULE_DMA_MULTI_CHANNEL
-	help
-	 Select if your target platform is mt8186-compatible
-	 Builds legacy/xtos firmware
-
-config MT8188
-	bool "Build for MTK MT8188 (XTOS)"
-	select XT_INTERRUPT_LEVEL_1
-	select XT_INTERRUPT_LEVEL_2
-	select XT_INTERRUPT_LEVEL_3
-	select XT_INTERRUPT_LEVEL_4
-	select DUMMY_DMA
-	select HOST_PTABLE
-	select XT_WAITI_DELAY
-	select MEDIATEK
-	select XTENSA_EXCLUSIVE
-	select SCHEDULE_DMA_MULTI_CHANNEL
-	help
-	 Select if your target platform is mt8188-compatible.
-	 Builds legacy/xtos firmware
-
-config MT8195
-	bool "Build for MTK MT8195 (XTOS)"
-	select XT_INTERRUPT_LEVEL_1
-	select XT_INTERRUPT_LEVEL_2
-	select XT_INTERRUPT_LEVEL_3
-	select DUMMY_DMA
-	select HOST_PTABLE
-	select MEDIATEK
-	select XTENSA_EXCLUSIVE
-	select SCHEDULE_DMA_MULTI_CHANNEL
-	help
-	  Select if your target platform is mt8195-compatible
-	  Builds legacy/xtos firmware
-
-config MT8365
-	bool "Build for MTK MT8365"
-	select XT_INTERRUPT_LEVEL_1
-	select XT_INTERRUPT_LEVEL_2
-	select XT_INTERRUPT_LEVEL_3
-	select DUMMY_DMA
-	select HOST_PTABLE
-	select MEDIATEK
-	select XTENSA_EXCLUSIVE
-	select SCHEDULE_DMA_MULTI_CHANNEL
-	help
-	  Select if your target platform is mt8365-compatible
-
 config MTK
 	bool "Build for Mediatek (Zephyr)"
 	select SCHEDULE_DMA_MULTI_CHANNEL if !ZEPHYR_NATIVE_DRIVERS
@@ -330,27 +215,6 @@ config MTK
 	help
 	  Select if your target is a Mediatek DSP.  Builds Zephyr firmware.
 
-config MT8196
-	bool "Build for MTK MT8196"
-	select XT_INTERRUPT_LEVEL_1
-	select XT_INTERRUPT_LEVEL_2
-	select XT_INTERRUPT_LEVEL_3
-	select XT_INTERRUPT_LEVEL_4
-	select DUMMY_DMA
-	select HOST_PTABLE
-	select XT_WAITI_DELAY
-	select MEDIATEK
-	select XTENSA_EXCLUSIVE
-	select SCHEDULE_DMA_MULTI_CHANNEL
-	help
-          This configuration enables support for the MediaTek MT8196 platform.
-          It includes necessary interrupt levels, DMA support, and other
-          platform-specific features required for the proper functioning of
-          the MT8196 SoC. Enabling this option will ensure that the build
-          system includes all relevant drivers and configurations for MT8196.
-
-          Select this option if your target platform is MT8196-compatible.
-
 endchoice
 
 config ESP32P4_PIE_SIMD
@@ -362,7 +226,7 @@ config ESP32P4_PIE_SIMD
 	  128-bit vector SIMD engine for audio processing kernels (volume, mixer, etc.).
 
 #
-# For non-Zephyr builds like testbench, cmocka and SOF ALSA plugin,
+# For non-Zephyr builds like testbench and cmocka,
 # set core count separately.
 #
 if !ZEPHYR_SOF_MODULE
@@ -413,12 +277,6 @@ config IMX
 	  This has to be selected for every i.MX NXP platform.
 	  It enables NXP platforms-specific features.
 
-config  MEDIATEK
-	bool
-	help
-	  This has to be selected for every MediaTek platform.
-	  It enables MediaTek platforms-specific features.
-
 config AMD
 	bool
 	help
@@ -560,17 +418,9 @@ config RIMAGE_SIGNING_SCHEMA
 	default "imx8m_cm7" if IMX8M_CM7
 	default "imx8ulp" if IMX8ULP
 	default "imx95" if IMX95
-	default "rn" if RENOIR
 	default "rmb" if REMBRANDT
-	default "vangogh" if VANGOGH
-	default "acp_6_3" if ACP_6_3
 	default "acp_7_0" if ACP_7_0
 	default "acp_7_x" if ACP_7_X
-	default "mt8186" if MT8186
-	default "mt8188" if MT8188
-	default "mt8195" if MT8195
-	default "mt8196" if MT8196
-	default "mt8365" if MT8365
 	default ""
 	help
 	  Signing schema name used by rimage to decide how to build final binary
@@ -616,8 +466,6 @@ config XTENSA_EXCLUSIVE
 
 config FORCE_DMA_COPY_WHOLE_BLOCK
 	bool
-	default y if MT8195
-	default y if MT8365
 	depends on HOST_PTABLE
 	help
 	  The host component forces DMA to copy the block size to avoid
diff --git a/src/platform/amd/CMakeLists.txt b/src/platform/amd/CMakeLists.txt
deleted file mode 100644
index 9ae93911168d..000000000000
--- a/src/platform/amd/CMakeLists.txt
+++ /dev/null
@@ -1,17 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-if(CONFIG_RENOIR OR CONFIG_VANGOGH OR CONFIG_REMBRANDT OR CONFIG_ACP_6_3 OR CONFIG_ACP_7_0)
-	add_subdirectory(common)
-endif()
-if(CONFIG_RENOIR)
-	add_subdirectory(renoir)
-elseif(CONFIG_REMBRANDT)
-	add_subdirectory(rembrandt)
-elseif(CONFIG_VANGOGH)
-	add_subdirectory(vangogh)
-elseif(CONFIG_ACP_6_3)
-	add_subdirectory(acp_6_3)
-elseif(CONFIG_ACP_7_0)
-	add_subdirectory(acp_7_0)
-elseif(CONFIG_ACP_7_X)
-	add_subdirectory(acp_7_x)
-endif()
diff --git a/src/platform/amd/acp_6_3/CMakeLists.txt b/src/platform/amd/acp_6_3/CMakeLists.txt
deleted file mode 100644
index ec909d60035f..000000000000
--- a/src/platform/amd/acp_6_3/CMakeLists.txt
+++ /dev/null
@@ -1,5 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-
-add_subdirectory(lib)
-
-add_local_sources(sof platform.c)
diff --git a/src/platform/amd/acp_6_3/acp_6_3.x.in b/src/platform/amd/acp_6_3/acp_6_3.x.in
deleted file mode 100644
index 44de135f96f3..000000000000
--- a/src/platform/amd/acp_6_3/acp_6_3.x.in
+++ /dev/null
@@ -1,581 +0,0 @@
-/*
- * Linker Script for AMD ACP_6_3
- *
- * This script is run through the GNU C preprocessor to align the memory
- * offsets with headers.
- *
- * Use spaces for formatting as cpp ignore tab sizes.
- */
-
-#include <sof/lib/memory.h>
-#include <xtensa/config/core-isa.h>
-
-OUTPUT_ARCH(xtensa)
-
-MEMORY
-{
-  vector_reset_text :
-        org = XCHAL_RESET_VECTOR_PADDR,
-        len = SOF_MEM_RESET_TEXT_SIZE
-  vector_reset_lit :
-        org = XCHAL_RESET_VECTOR_PADDR + SOF_MEM_RESET_TEXT_SIZE,
-        len = SOF_MEM_RESET_LIT_SIZE
-  vector_base_text :
-        org = XCHAL_WINDOW_VECTORS_VADDR, //XCHAL_VECBASE_RESET_PADDR,
-        len = SOF_MEM_VECBASE_LIT_SIZE
-  vector_int2_lit :
-        org = XCHAL_INTLEVEL2_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
-        len = SOF_MEM_VECT_LIT_SIZE
-  vector_int2_text :
-        org = XCHAL_INTLEVEL2_VECTOR_PADDR,
-        len = SOF_MEM_VECT_TEXT_SIZE
-  vector_int3_lit :
-        org = XCHAL_INTLEVEL3_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
-        len = SOF_MEM_VECT_LIT_SIZE
-  vector_int3_text :
-        org = XCHAL_INTLEVEL3_VECTOR_PADDR,
-        len = SOF_MEM_VECT_TEXT_SIZE
-  vector_int4_lit :
-        org = XCHAL_INTLEVEL4_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
-        len = SOF_MEM_VECT_LIT_SIZE
-  vector_int4_text :
-        org = XCHAL_INTLEVEL4_VECTOR_PADDR,
-        len = SOF_MEM_VECT_TEXT_SIZE
-  vector_int5_lit :
-        org = XCHAL_INTLEVEL5_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
-        len = SOF_MEM_VECT_LIT_SIZE
-  vector_int5_text :
-        org = XCHAL_INTLEVEL5_VECTOR_PADDR,
-        len = SOF_MEM_VECT_TEXT_SIZE
-  vector_int6_lit :
-        org = XCHAL_INTLEVEL6_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
-        len = SOF_MEM_VECT_LIT_SIZE
-  vector_int6_text :
-        org = XCHAL_INTLEVEL6_VECTOR_PADDR,
-        len = SOF_MEM_VECT_TEXT_SIZE
-
-  vector_int7_lit :
-        org = XCHAL_INTLEVEL7_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
-        len = SOF_MEM_VECT_LIT_SIZE
-  vector_int7_text :
-        org = XCHAL_INTLEVEL7_VECTOR_PADDR,
-        len = SOF_MEM_VECT_TEXT_SIZE
-  vector_kernel_lit :
-        org = XCHAL_KERNEL_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
-        len = SOF_MEM_VECT_LIT_SIZE
-  vector_kernel_text :
-        org = XCHAL_KERNEL_VECTOR_PADDR,
-        len = SOF_MEM_VECT_TEXT_SIZE
-  vector_user_lit :
-        org = XCHAL_USER_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
-        len = SOF_MEM_VECT_LIT_SIZE
-  vector_user_text :
-        org = XCHAL_USER_VECTOR_PADDR,
-        len = SOF_MEM_VECT_TEXT_SIZE
-  vector_double_lit :
-        org = XCHAL_DOUBLEEXC_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
-        len = SOF_MEM_VECT_LIT_SIZE
-  vector_double_text :
-        org = XCHAL_DOUBLEEXC_VECTOR_PADDR,
-        len = SOF_MEM_VECT_TEXT_SIZE
-  sof_iram_text_start :
-        org = XCHAL_DOUBLEEXC_VECTOR_PADDR + SOF_MEM_VECT_TEXT_SIZE,
-        len =  IRAM_BASE + (XCHAL_DOUBLEEXC_VECTOR_PADDR + SOF_MEM_VECT_TEXT_SIZE)
-  sof_sdram0 :
-        org = DRAM0_BASE,
-        len = DRAM0_SIZE + DRAM1_SIZE - SOF_STACK_SIZE
-  system_heap :
-        org = HEAP_SYSTEM_BASE,
-        len = HEAP_SYSTEM_SIZE
-  system_runtime_heap :
-        org = HEAP_SYS_RUNTIME_BASE,
-        len = HEAP_SYS_RUNTIME_SIZE
-  runtime_heap :
-        org = HEAP_RUNTIME_BASE,
-        len = HEAP_RUNTIME_SIZE
-  buffer_heap :
-        org = HEAP_BUFFER_BASE,
-        len = HEAP_BUFFER_SIZE
- sof_stack :
-        org = SOF_STACK_END,
-        len = SOF_STACK_BASE - SOF_STACK_END,
-sof_sdram1 :
-        org = DRAM1_BASE,
-        len = DRAM1_SIZE
-sof_sram1 :
-        org = SRAM1_BASE,
-        len = SRAM1_SIZE
-  static_uuid_entries_seg (!ari) :
-	org = UUID_ENTRY_ELF_BASE,
-	len = UUID_ENTRY_ELF_SIZE
-  static_log_entries_seg (!ari) :
-        org = LOG_ENTRY_ELF_BASE,
-        len = LOG_ENTRY_ELF_SIZE
- fw_metadata_seg (!ari) :
-        org = EXT_MANIFEST_ELF_BASE,
-        len = EXT_MANIFEST_ELF_SIZE
-}
-
-PHDRS
-{
-  vector_reset_text_phdr PT_LOAD;
-  vector_reset_lit_phdr PT_LOAD;
-  vector_base_text_phdr PT_LOAD;
-  vector_base_lit_phdr PT_LOAD;
-  vector_int2_text_phdr PT_LOAD;
-  vector_int2_lit_phdr PT_LOAD;
-  vector_int3_text_phdr PT_LOAD;
-  vector_int3_lit_phdr PT_LOAD;
-  vector_int4_text_phdr PT_LOAD;
-  vector_int4_lit_phdr PT_LOAD;
-  vector_int5_text_phdr PT_LOAD;
-  vector_int5_lit_phdr PT_LOAD;
-  vector_int6_text_phdr PT_LOAD;
-  vector_int6_lit_phdr PT_LOAD;
-  vector_int7_text_phdr PT_LOAD;
-  vector_int7_lit_phdr PT_LOAD;
-  vector_kernel_text_phdr PT_LOAD;
-  vector_kernel_lit_phdr PT_LOAD;
-  vector_user_text_phdr PT_LOAD;
-  vector_user_lit_phdr PT_LOAD;
-  vector_double_text_phdr PT_LOAD;
-  vector_double_lit_phdr PT_LOAD;
-  sof_iram_text_start_phdr PT_LOAD;
-  sof_sdram0_phdr PT_LOAD;
-  sof_sram1_phdr PT_LOAD;
-  sof_stack_phdr PT_LOAD;
-  system_heap_phdr PT_LOAD;
-  system_runtime_heap_phdr PT_LOAD;
-  runtime_heap_phdr PT_LOAD;
-  buffer_heap_phdr PT_LOAD;
-  sof_sdram1_phdr PT_LOAD;
-  static_uuid_entries_phdr PT_NOTE;
-  static_log_entries_phdr PT_NOTE;
- metadata_entries_phdr PT_NOTE;
-}
-
-/*  Default entry point:  */
-ENTRY(_ResetVector)
-_rom_store_table = 0;
-
-/* ABI0 does not use Window base */
-PROVIDE(_memmap_vecbase_reset = XCHAL_WINDOW_VECTORS_VADDR);
-
-/* Various memory-map dependent cache attribute settings: */
-_memmap_cacheattr_wb_base = 0x20004400;
-_memmap_cacheattr_wt_base = 0x20001100;
-_memmap_cacheattr_bp_base = 0x20002200;
-_memmap_cacheattr_unused_mask = 0x0FFF00FF;
-_memmap_cacheattr_wb_trapnull = 0x2222442F;
-_memmap_cacheattr_wba_trapnull = 0x2222442F;
-_memmap_cacheattr_wbna_trapnull = 0x2222552F;
-_memmap_cacheattr_wt_trapnull = 0x2222112F;
-_memmap_cacheattr_bp_trapnull = 0x2222222F;
-_memmap_cacheattr_wb_strict = 0x2FFF44FF;
-_memmap_cacheattr_wt_strict = 0x2FFF11FF;
-_memmap_cacheattr_bp_strict = 0x2FFF22FF;
-_memmap_cacheattr_wb_allvalid = 0x22224422;
-_memmap_cacheattr_wt_allvalid = 0x22221122;
-_memmap_cacheattr_bp_allvalid = 0x22222222;
-PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wbna_trapnull);
-_EXT_MAN_ALIGN_ = 16;
-EXTERN(ext_man_fw_ver)
-
-
-SECTIONS
-{
-  .ResetVector.text : ALIGN(4)
-  {
-    _ResetVector_text_start = ABSOLUTE(.);
-    KEEP (*(.ResetVector.text))
-    _ResetVector_text_end = ABSOLUTE(.);
-  } >vector_reset_text :vector_reset_text_phdr
-
-  .ResetVector.literal : ALIGN(4)
-  {
-    _ResetVector_literal_start = ABSOLUTE(.);
-    *(.ResetVector.literal)
-    _ResetVector_literal_end = ABSOLUTE(.);
-  } >vector_reset_lit :vector_reset_lit_phdr
-
-  .WindowVectors.text : ALIGN(4)
-  {
-    _WindowVectors_text_start = ABSOLUTE(.);
-    KEEP (*(.WindowVectors.text))
-    _WindowVectors_text_end = ABSOLUTE(.);
-  } >vector_base_text :vector_base_text_phdr
-
-  .Level2InterruptVector.literal : ALIGN(4)
-  {
-    _Level2InterruptVector_literal_start = ABSOLUTE(.);
-    *(.Level2InterruptVector.literal)
-    _Level2InterruptVector_literal_end = ABSOLUTE(.);
-  } >vector_int2_lit :vector_int2_lit_phdr
-
-  .Level2InterruptVector.text : ALIGN(4)
-  {
-    _Level2InterruptVector_text_start = ABSOLUTE(.);
-    KEEP (*(.Level2InterruptVector.text))
-    _Level2InterruptVector_text_end = ABSOLUTE(.);
-  } >vector_int2_text :vector_int2_text_phdr
-
-  .Level3InterruptVector.literal : ALIGN(4)
-  {
-    _Level3InterruptVector_literal_start = ABSOLUTE(.);
-    *(.Level3InterruptVector.literal)
-    _Level3InterruptVector_literal_end = ABSOLUTE(.);
-  } >vector_int3_lit :vector_int3_lit_phdr
-
-  .Level3InterruptVector.text : ALIGN(4)
-  {
-    _Level3InterruptVector_text_start = ABSOLUTE(.);
-    KEEP (*(.Level3InterruptVector.text))
-    _Level3InterruptVector_text_end = ABSOLUTE(.);
-  } >vector_int3_text :vector_int3_text_phdr
-
-  .Level4InterruptVector.literal : ALIGN(4)
-  {
-    _Level4InterruptVector_literal_start = ABSOLUTE(.);
-    *(.Level4InterruptVector.literal)
-    _Level4InterruptVector_literal_end = ABSOLUTE(.);
-  } >vector_int4_lit :vector_int4_lit_phdr
-
-  .Level4InterruptVector.text : ALIGN(4)
-  {
-    _Level4InterruptVector_text_start = ABSOLUTE(.);
-    KEEP (*(.Level4InterruptVector.text))
-    _Level4InterruptVector_text_end = ABSOLUTE(.);
-  } >vector_int4_text :vector_int4_text_phdr
-
-  .Level5InterruptVector.literal : ALIGN(4)
-  {
-    _Level5InterruptVector_literal_start = ABSOLUTE(.);
-    *(.Level5InterruptVector.literal)
-    _Level5InterruptVector_literal_end = ABSOLUTE(.);
-  } >vector_int5_lit :vector_int5_lit_phdr
-
-  .Level5InterruptVector.text : ALIGN(4)
-  {
-    _Level5InterruptVector_text_start = ABSOLUTE(.);
-    KEEP (*(.Level5InterruptVector.text))
-    _Level5InterruptVector_text_end = ABSOLUTE(.);
-  } >vector_int5_text :vector_int5_text_phdr
-
-  .DebugExceptionVector.literal : ALIGN(4)
-  {
-    _DebugExceptionVector_literal_start = ABSOLUTE(.);
-    *(.DebugExceptionVector.literal)
-    _DebugExceptionVector_literal_end = ABSOLUTE(.);
-  } >vector_int6_lit :vector_int6_lit_phdr
-
-  .DebugExceptionVector.text : ALIGN(4)
-  {
-    _DebugExceptionVector_text_start = ABSOLUTE(.);
-    KEEP (*(.DebugExceptionVector.text))
-    _DebugExceptionVector_text_end = ABSOLUTE(.);
-  } >vector_int6_text :vector_int6_text_phdr
-
-  .NMIExceptionVector.literal : ALIGN(4)
-  {
-    _NMIExceptionVector_literal_start = ABSOLUTE(.);
-    *(.NMIExceptionVector.literal)
-    _NMIExceptionVector_literal_end = ABSOLUTE(.);
-  } >vector_int7_lit :vector_int5_lit_phdr
-
-  .NMIExceptionVector.text : ALIGN(4)
-  {
-    _NMIExceptionVector_text_start = ABSOLUTE(.);
-    KEEP (*(.NMIExceptionVector.text))
-    _NMIExceptionVector_text_end = ABSOLUTE(.);
-  } >vector_int7_text :vector_int5_text_phdr
-
-  .KernelExceptionVector.literal : ALIGN(4)
-  {
-    _KernelExceptionVector_literal_start = ABSOLUTE(.);
-    *(.KernelExceptionVector.literal)
-    _KernelExceptionVector_literal_end = ABSOLUTE(.);
-  } >vector_kernel_lit :vector_kernel_lit_phdr
-
-  .KernelExceptionVector.text : ALIGN(4)
-  {
-    _KernelExceptionVector_text_start = ABSOLUTE(.);
-    KEEP (*(.KernelExceptionVector.text))
-    _KernelExceptionVector_text_end = ABSOLUTE(.);
-  } >vector_kernel_text :vector_kernel_text_phdr
-
-  .UserExceptionVector.literal : ALIGN(4)
-  {
-    _UserExceptionVector_literal_start = ABSOLUTE(.);
-    *(.UserExceptionVector.literal)
-    _UserExceptionVector_literal_end = ABSOLUTE(.);
-  } >vector_user_lit :vector_user_lit_phdr
-
-  .UserExceptionVector.text : ALIGN(4)
-  {
-    _UserExceptionVector_text_start = ABSOLUTE(.);
-    KEEP (*(.UserExceptionVector.text))
-    _UserExceptionVector_text_end = ABSOLUTE(.);
-  } >vector_user_text :vector_user_text_phdr
-
-  .DoubleExceptionVector.literal : ALIGN(4)
-  {
-    _DoubleExceptionVector_literal_start = ABSOLUTE(.);
-    *(.DoubleExceptionVector.literal)
-    _DoubleExceptionVector_literal_end = ABSOLUTE(.);
-  } >vector_double_lit :vector_double_lit_phdr
-
-  .DoubleExceptionVector.text : ALIGN(4)
-  {
-    _DoubleExceptionVector_text_start = ABSOLUTE(.);
-    KEEP (*(.DoubleExceptionVector.text))
-    _DoubleExceptionVector_text_end = ABSOLUTE(.);
-  } >vector_double_text :vector_double_text_phdr
-
-  .iram.text : ALIGN(4)
-  {
-    _stext = .;
-    _iram_text_start = ABSOLUTE(.);
-    *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)
-    _iram_text_end = ABSOLUTE(.);
-  } >sof_iram_text_start :sof_iram_text_start_phdr
-
-	/* stack */
- _end = SOF_STACK_END;
-  PROVIDE(end = SOF_STACK_END);
-  _stack_sentry = SOF_STACK_END;
-  __stack = SOF_STACK_BASE;
-
-  .text : ALIGN(4)
-  {
-    _stext = .;
-    _text_start = ABSOLUTE(.);
-    *(.entry.text)
-    *(.init.literal)
-    KEEP(*(.init))
-    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
-    *(.fini.literal)
-    KEEP(*(.fini))
-    *(.gnu.version)
-    _text_end = ABSOLUTE(.);
-    _etext = .;
-  } >sof_iram_text_start :sof_iram_text_start_phdr
-
-  .rodata : ALIGN(4)
-  {
-    _rodata_start = ABSOLUTE(.);
-    *(.rodata)
-    *(.rodata.*)
-    *(.gnu.linkonce.r.*)
-    *(.rodata1)
-    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);
-    KEEP (*(.xt_except_table))
-    KEEP (*(.gcc_except_table))
-    *(.gnu.linkonce.e.*)
-    *(.gnu.version_r)
-    KEEP (*(.eh_frame))
-    /*  C++ constructor and destructor tables, properly ordered:  */
-    KEEP (*crtbegin.o(.ctors))
-    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
-    KEEP (*(SORT(.ctors.*)))
-    KEEP (*(.ctors))
-    KEEP (*crtbegin.o(.dtors))
-    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
-    KEEP (*(SORT(.dtors.*)))
-    KEEP (*(.dtors))
-    /*  C++ exception handlers table:  */
-    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);
-    *(.xt_except_desc)
-    *(.gnu.linkonce.h.*)
-    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
-    *(.xt_except_desc_end)
-    *(.dynamic)
-    *(.gnu.version_d)
-    . = ALIGN(4);		/* this table MUST be 4-byte aligned */
-    _bss_table_start = ABSOLUTE(.);
-    LONG(_bss_start)
-    LONG(_bss_end)
-    _bss_table_end = ABSOLUTE(.);
-    _rodata_end = ABSOLUTE(.);
-  } >sof_sram1 :sof_sram1_phdr
-
-  .module_init : ALIGN(4)
-  {
-   _module_init_start = ABSOLUTE(.);
-    *(*.initcall)
-    _module_init_end = ABSOLUTE(.);
-  } >sof_sram1 :sof_sram1_phdr
-
-  .data : ALIGN(4)
-  {
-    _data_start = ABSOLUTE(.);
-    *(.data)
-    *(.data.*)
-    *(.gnu.linkonce.d.*)
-    KEEP(*(.gnu.linkonce.d.*personality*))
-    *(.data1)
-    *(.sdata)
-    *(.sdata.*)
-    *(.gnu.linkonce.s.*)
-    *(.sdata2)
-    *(.sdata2.*)
-    *(.gnu.linkonce.s2.*)
-    KEEP(*(.jcr))
-    _trace_ctx_start = ABSOLUTE(.);
-    *(.trace_ctx)
-    _trace_ctx_end = ABSOLUTE(.);
-    _data_end = ABSOLUTE(.);
-  } >sof_sram1 :sof_sram1_phdr
-
-  .lit4 : ALIGN(4)
-  {
-    _lit4_start = ABSOLUTE(.);
-    *(*.lit4)
-    *(.lit4.*)
-    *(.gnu.linkonce.lit4.*)
-    _lit4_end = ABSOLUTE(.);
-  } >sof_sram1 :sof_sram1_phdr
-
-  .fw_ready : ALIGN(4)
-  {
-    KEEP (*(.fw_ready))
-  } >sof_sram1 :sof_sram1_phdr
-
-
-  .bss (NOLOAD) : ALIGN(8)
-  {
-    . = ALIGN (8);
-    _bss_start = ABSOLUTE(.);
-    *(.dynsbss)
-    *(.sbss)
-    *(.sbss.*)
-    *(.gnu.linkonce.sb.*)
-    *(.scommon)
-    *(.sbss2)
-    *(.sbss2.*)
-    *(.gnu.linkonce.sb2.*)
-    *(.dynbss)
-    *(.bss)
-    *(.bss.*)
-    *(.gnu.linkonce.b.*)
-    *(COMMON)
-    . = ALIGN (8);
-    _bss_end = ABSOLUTE(.);
-  } >sof_sram1 :sof_sram1_phdr
-
-
-.sof_stack (NOLOAD) : ALIGN(8)
-  {
-    . = ALIGN (4096);
-    _sof_stack_start = ABSOLUTE(.);
-    . = . + SOF_STACK_TOTAL_SIZE;
-    _sof_stack_end = ABSOLUTE(.);
-  } >sof_stack :sof_stack_phdr
-
-  .reset.rodata : ALIGN(4)
-  {
-    _reset_rodata_start = ABSOLUTE(.);
-    *(.reset.rodata)
-    _reset_rodata_end = ABSOLUTE(.);
-  } >sof_sram1 :sof_sram1_phdr
-
-
-  .system_heap (NOLOAD) : ALIGN(8)
-  {
-    . = ALIGN (32);
-    _system_heap_start = ABSOLUTE(.);
-    . = . + HEAP_SYSTEM_SIZE;
-    _system_heap_end = ABSOLUTE(.);
-  } >system_heap :system_heap_phdr
-
-  .system_runtime_heap (NOLOAD) : ALIGN(8)
-  {
-    . = ALIGN (HEAP_BUF_ALIGNMENT);
-    _system_runtime_heap_start = ABSOLUTE(.);
-    . = . + HEAP_SYS_RUNTIME_SIZE;
-    _system_runtime_heap_end = ABSOLUTE(.);
-  } >system_runtime_heap :system_runtime_heap_phdr
-
-  .runtime_heap (NOLOAD) : ALIGN(8)
-  {
-    . = ALIGN (32);
-    _runtime_heap_start = ABSOLUTE(.);
-    . = . + HEAP_RUNTIME_SIZE;
-    _runtime_heap_end = ABSOLUTE(.);
-  } >runtime_heap :runtime_heap_phdr
-
-  .buffer_heap (NOLOAD) : ALIGN(8)
-  {
-    . = ALIGN (HEAP_BUF_ALIGNMENT);
-    _buffer_heap_start = ABSOLUTE(.);
-    . = . + HEAP_BUFFER_SIZE;
-    _buffer_heap_end = ABSOLUTE(.);
-  } >buffer_heap :buffer_heap_phdr
-
-  .static_uuid_entries (COPY) : ALIGN(1024)
-  {
-    *(*.static_uuids)
-  } > static_uuid_entries_seg :static_uuid_entries_phdr
-
-  .static_log_entries (COPY) : ALIGN(1024)
-  {
-    *(*.static_log*)
-  } > static_log_entries_seg :static_log_entries_phdr
-
-  .debug  0 :  { *(.debug) }
-  .line  0 :  { *(.line) }
-  .debug_srcinfo  0 :  { *(.debug_srcinfo) }
-  .debug_sfnames  0 :  { *(.debug_sfnames) }
-  .debug_aranges  0 :  { *(.debug_aranges) }
-  .debug_pubnames  0 :  { *(.debug_pubnames) }
-  .debug_info  0 :  { *(.debug_info) }
-  .debug_abbrev  0 :  { *(.debug_abbrev) }
-  .debug_line  0 :  { *(.debug_line) }
-  .debug_frame  0 :  { *(.debug_frame) }
-  .debug_str  0 :  { *(.debug_str) }
-  .debug_loc  0 :  { *(.debug_loc) }
-  .debug_macinfo  0 :  { *(.debug_macinfo) }
-  .debug_weaknames  0 :  { *(.debug_weaknames) }
-  .debug_funcnames  0 :  { *(.debug_funcnames) }
-  .debug_typenames  0 :  { *(.debug_typenames) }
-  .debug_varnames  0 :  { *(.debug_varnames) }
-
-  .xt.insn 0 :
-  {
-    KEEP (*(.xt.insn))
-    KEEP (*(.gnu.linkonce.x.*))
-  }
-  .xt.prop 0 :
-  {
-    KEEP (*(.xt.prop))
-    KEEP (*(.xt.prop.*))
-    KEEP (*(.gnu.linkonce.prop.*))
-  }
-  .xt.lit 0 :
-  {
-    KEEP (*(.xt.lit))
-    KEEP (*(.xt.lit.*))
-    KEEP (*(.gnu.linkonce.p.*))
-  }
-  .xt.profile_range 0 :
-  {
-    KEEP (*(.xt.profile_range))
-    KEEP (*(.gnu.linkonce.profile_range.*))
-  }
-  .xt.profile_ranges 0 :
-  {
-    KEEP (*(.xt.profile_ranges))
-    KEEP (*(.gnu.linkonce.xt.profile_ranges.*))
-  }
-  .xt.profile_files 0 :
-  {
-    KEEP (*(.xt.profile_files))
-    KEEP (*(.gnu.linkonce.xt.profile_files.*))
-  }
-
- .fw_metadata (COPY) : ALIGN(1024)
-  {
-    KEEP (*(.fw_metadata))
-    . = ALIGN(_EXT_MAN_ALIGN_);
-  } >fw_metadata_seg :metadata_entries_phdr
-
-}
diff --git a/src/platform/amd/acp_6_3/include/arch/xtensa/config/core-isa.h b/src/platform/amd/acp_6_3/include/arch/xtensa/config/core-isa.h
deleted file mode 100644
index e006725edc39..000000000000
--- a/src/platform/amd/acp_6_3/include/arch/xtensa/config/core-isa.h
+++ /dev/null
@@ -1,714 +0,0 @@
-/* 
- * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
- *				processor CORE configuration
- *
- *  See <xtensa/config/core.h>, which includes this file, for more details.
- */
-
-/* Xtensa processor core configuration information.
-
-   Customer ID=7490; Build=0xa28f5; Copyright (c) 1999-2022 Tensilica Inc.
-
-   Permission is hereby granted, free of charge, to any person obtaining
-   a copy of this software and associated documentation files (the
-   "Software"), to deal in the Software without restriction, including
-   without limitation the rights to use, copy, modify, merge, publish,
-   distribute, sublicense, and/or sell copies of the Software, and to
-   permit persons to whom the Software is furnished to do so, subject to
-   the following conditions:
-
-   The above copyright notice and this permission notice shall be included
-   in all copies or substantial portions of the Software.
-
-   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
-
-#ifndef XTENSA_CORE_CONFIGURATION_H_
-#define XTENSA_CORE_CONFIGURATION_H_
-
-
-/****************************************************************************
-	    Parameters Useful for Any Code, USER or PRIVILEGED
- ****************************************************************************/
-
-/*
- *  Note:  Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
- *  configured, and a value of 0 otherwise.  These macros are always defined.
- */
-
-
-/*----------------------------------------------------------------------
-				ISA
-  ----------------------------------------------------------------------*/
-
-#define XCHAL_HAVE_BE			0	/* big-endian byte ordering */
-#define XCHAL_HAVE_WINDOWED		1	/* windowed registers option */
-#define XCHAL_NUM_AREGS			64	/* num of physical addr regs */
-#define XCHAL_NUM_AREGS_LOG2		6	/* log2(XCHAL_NUM_AREGS) */
-#define XCHAL_MAX_INSTRUCTION_SIZE	16	/* max instr bytes (3..8) */
-#define XCHAL_HAVE_DEBUG		1	/* debug option */
-#define XCHAL_HAVE_DENSITY		1	/* 16-bit instructions */
-#define XCHAL_HAVE_LOOPS		1	/* zero-overhead loops */
-#define XCHAL_LOOP_BUFFER_SIZE		256	/* zero-ov. loop instr buffer size */
-#define XCHAL_HAVE_NSA			1	/* NSA/NSAU instructions */
-#define XCHAL_HAVE_MINMAX		1	/* MIN/MAX instructions */
-#define XCHAL_HAVE_SEXT			1	/* SEXT instruction */
-#define XCHAL_HAVE_DEPBITS		0	/* DEPBITS instruction */
-#define XCHAL_HAVE_CLAMPS		1	/* CLAMPS instruction */
-#define XCHAL_HAVE_MUL16		1	/* MUL16S/MUL16U instructions */
-#define XCHAL_HAVE_MUL32		1	/* MULL instruction */
-#define XCHAL_HAVE_MUL32_HIGH		1	/* MULUH/MULSH instructions */
-#define XCHAL_HAVE_DIV32		1	/* QUOS/QUOU/REMS/REMU instructions */
-#define XCHAL_HAVE_L32R			1	/* L32R instruction */
-#define XCHAL_HAVE_ABSOLUTE_LITERALS	0	/* non-PC-rel (extended) L32R */
-#define XCHAL_HAVE_CONST16		0	/* CONST16 instruction */
-#define XCHAL_HAVE_ADDX			1	/* ADDX#/SUBX# instructions */
-#define XCHAL_HAVE_EXCLUSIVE            0	/* L32EX/S32EX instructions */
-#define XCHAL_HAVE_WIDE_BRANCHES	0	/* B*.W18 or B*.W15 instr's */
-#define XCHAL_HAVE_PREDICTED_BRANCHES	0	/* B[EQ/EQZ/NE/NEZ]T instr's */
-#define XCHAL_HAVE_CALL4AND12		1	/* (obsolete option) */
-#define XCHAL_HAVE_ABS			1	/* ABS instruction */
-#define XCHAL_HAVE_RELEASE_SYNC		1	/* L32AI/S32RI instructions */
-#define XCHAL_HAVE_S32C1I		1	/* S32C1I instruction */
-#define XCHAL_HAVE_SPECULATION		0	/* speculation */
-#define XCHAL_HAVE_FULL_RESET		1	/* all regs/state reset */
-#define XCHAL_NUM_CONTEXTS		1	/* */
-#define XCHAL_NUM_MISC_REGS		2	/* num of scratch regs (0..4) */
-#define XCHAL_HAVE_TAP_MASTER		0	/* JTAG TAP control instr's */
-#define XCHAL_HAVE_PRID			0	/* processor ID register */
-#define XCHAL_HAVE_EXTERN_REGS		1	/* WER/RER instructions */
-#define XCHAL_HAVE_MX			0	/* MX core (Tensilica internal) */
-#define XCHAL_HAVE_MP_INTERRUPTS	0	/* interrupt distributor port */
-#define XCHAL_HAVE_MP_RUNSTALL		0	/* core RunStall control port */
-#define XCHAL_HAVE_PSO			0	/* Power Shut-Off */
-#define XCHAL_HAVE_PSO_CDM		0	/* core/debug/mem pwr domains */
-#define XCHAL_HAVE_PSO_FULL_RETENTION	0	/* all regs preserved on PSO */
-#define XCHAL_HAVE_THREADPTR		1	/* THREADPTR register */
-#define XCHAL_HAVE_BOOLEANS		1	/* boolean registers */
-#define XCHAL_HAVE_CP			1	/* CPENABLE reg (coprocessor) */
-#define XCHAL_CP_MAXCFG			2	/* max allowed cp id plus one */
-#define XCHAL_HAVE_MAC16		0	/* MAC16 package */
-#define XCHAL_HAVE_LX			1	/* LX core */
-#define XCHAL_HAVE_NX			0	/* NX core (starting RH) */
-
-#define XCHAL_HAVE_SUPERGATHER		0	/* SuperGather */
-
-#define XCHAL_HAVE_FUSION		0	/* Fusion*/
-#define XCHAL_HAVE_FUSION_FP		0	/* Fusion FP option */
-#define XCHAL_HAVE_FUSION_LOW_POWER	0	/* Fusion Low Power option */
-#define XCHAL_HAVE_FUSION_AES		0	/* Fusion BLE/Wifi AES-128 CCM option */
-#define XCHAL_HAVE_FUSION_CONVENC	0	/* Fusion Conv Encode option */
-#define XCHAL_HAVE_FUSION_LFSR_CRC	0	/* Fusion LFSR-CRC option */
-#define XCHAL_HAVE_FUSION_BITOPS	0	/* Fusion Bit Operations Support option */
-#define XCHAL_HAVE_FUSION_AVS		0	/* Fusion AVS option */
-#define XCHAL_HAVE_FUSION_16BIT_BASEBAND 0	/* Fusion 16-bit Baseband option */
-#define XCHAL_HAVE_FUSION_VITERBI	0	/* Fusion Viterbi option */
-#define XCHAL_HAVE_FUSION_SOFTDEMAP	0	/* Fusion Soft Bit Demap option */
-#define XCHAL_HAVE_HIFIPRO		0	/* HiFiPro Audio Engine pkg */
-#define XCHAL_HAVE_HIFI5		1	/* HiFi5 Audio Engine pkg */
-#define XCHAL_HAVE_HIFI5_NN_MAC		1	/* HiFi5 Audio Engine NN-MAC option */
-#define XCHAL_HAVE_HIFI5_VFPU		1	/* HiFi5 Audio Engine Single-Precision VFPU option */
-#define XCHAL_HAVE_HIFI5_HP_VFPU	1	/* HiFi5 Audio Engine Half-Precision VFPU option */
-#define XCHAL_HAVE_HIFI4		0	/* HiFi4 Audio Engine pkg */
-#define XCHAL_HAVE_HIFI4_VFPU		1	/* HiFi4 Audio Engine VFPU option */
-#define XCHAL_HAVE_HIFI3		1	/* HiFi3 Audio Engine pkg */
-#define XCHAL_HAVE_HIFI3_VFPU		1	/* HiFi3 Audio Engine VFPU option */
-#define XCHAL_HAVE_HIFI3Z		0	/* HiFi3Z Audio Engine pkg */
-#define XCHAL_HAVE_HIFI3Z_VFPU	0	/* HiFi3Z Audio Engine VFPU option */
-#define XCHAL_HAVE_HIFI2		0	/* HiFi2 Audio Engine pkg */
-#define XCHAL_HAVE_HIFI2EP		0	/* HiFi2EP */
-#define XCHAL_HAVE_HIFI_MINI		0	
-
-
-
-#define XCHAL_HAVE_VECTORFPU2005	0	/* vector floating-point pkg */
-#define XCHAL_HAVE_USER_DPFPU		0       /* user DP floating-point pkg */
-#define XCHAL_HAVE_USER_SPFPU		1       /* user SP floating-point pkg */
-#define XCHAL_HAVE_FP			1	/* single prec floating point */
-#define XCHAL_HAVE_FP_DIV		1	/* FP with DIV instructions */
-#define XCHAL_HAVE_FP_RECIP		1	/* FP with RECIP instructions */
-#define XCHAL_HAVE_FP_SQRT		1	/* FP with SQRT instructions */
-#define XCHAL_HAVE_FP_RSQRT		1	/* FP with RSQRT instructions */
-#define XCHAL_HAVE_DFP			0	/* double precision FP pkg */
-#define XCHAL_HAVE_DFP_DIV		0	/* DFP with DIV instructions */
-#define XCHAL_HAVE_DFP_RECIP		0	/* DFP with RECIP instructions*/
-#define XCHAL_HAVE_DFP_SQRT		0	/* DFP with SQRT instructions */
-#define XCHAL_HAVE_DFP_RSQRT		0	/* DFP with RSQRT instructions*/
-#define XCHAL_HAVE_DFP_ACCEL		0	/* double precision FP acceleration pkg */
-#define XCHAL_HAVE_DFP_accel		XCHAL_HAVE_DFP_ACCEL	/* for backward compatibility */
-
-#define XCHAL_HAVE_DFPU_SINGLE_ONLY	0	/* DFPU Coprocessor, single precision only */
-#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE	0	/* DFPU Coprocessor, single and double precision */
-#define XCHAL_HAVE_VECTRA1		0	/* Vectra I  pkg */
-#define XCHAL_HAVE_VECTRALX		0	/* Vectra LX pkg */
-
-#define XCHAL_HAVE_FUSIONG		0    /* FusionG */
-#define XCHAL_HAVE_FUSIONG3		0    /* FusionG3 */
-#define XCHAL_HAVE_FUSIONG6		0    /* FusionG6 */
-#define XCHAL_HAVE_FUSIONG_SP_VFPU	0    /* sp_vfpu option on FusionG */
-#define XCHAL_HAVE_FUSIONG_DP_VFPU	0    /* dp_vfpu option on FusionG */
-#define XCHAL_FUSIONG_SIMD32		0    /* simd32 for FusionG */
-
-#define XCHAL_HAVE_FUSIONJ		0    /* FusionJ */
-#define XCHAL_HAVE_FUSIONJ6		0    /* FusionJ6 */
-#define XCHAL_HAVE_FUSIONJ_SP_VFPU	0    /* sp_vfpu option on FusionJ */
-#define XCHAL_HAVE_FUSIONJ_DP_VFPU	0    /* dp_vfpu option on FusionJ */
-#define XCHAL_FUSIONJ_SIMD32		0    /* simd32 for FusionJ */
-
-#define XCHAL_HAVE_PDX			0    /* PDX-LX */
-#define XCHAL_PDX_SIMD32		0    /* simd32 for PDX */
-#define XCHAL_HAVE_PDX4			0    /* PDX4-LX */
-#define XCHAL_HAVE_PDX8			0    /* PDX8-LX */
-#define XCHAL_HAVE_PDX16		0    /* PDX16-LX */
-#define XCHAL_HAVE_PDXNX 		0    /* PDX-NX */
-
-#define XCHAL_HAVE_CONNXD2		0	/* ConnX D2 pkg */
-#define XCHAL_HAVE_CONNXD2_DUALLSFLIX   0	/* ConnX D2 & Dual LoadStore Flix */
-#define XCHAL_HAVE_BALL			0
-#define XCHAL_HAVE_BALLAP		0
-#define XCHAL_HAVE_BBE16		0	/* ConnX BBE16 pkg */
-#define XCHAL_HAVE_BBE16_RSQRT		0	/* BBE16 & vector recip sqrt */
-#define XCHAL_HAVE_BBE16_VECDIV		0	/* BBE16 & vector divide */
-#define XCHAL_HAVE_BBE16_DESPREAD	0	/* BBE16 & despread */
-#define XCHAL_HAVE_CONNX_B10            0    /* ConnX B10 pkg*/
-#define XCHAL_HAVE_CONNX_B20            0    /* ConnX B20 pkg*/
-#define XCHAL_HAVE_CONNX_B_DP_VFPU      0    /* Double-precision Vector Floating-point option on ConnX B10 & B20 */
-#define XCHAL_HAVE_CONNX_B_SP_VFPU      0    /* Single-precision Vector Floating-point option on ConnX B10 & B20 */
-#define XCHAL_HAVE_CONNX_B_SPX_VFPU     0    /* Single-precision Extended Vector Floating-point option on ConnX B10 & B20 */
-#define XCHAL_HAVE_CONNX_B_HPX_VFPU     0    /* Half-precision Extended Vector Floating-point option on ConnX B10 & B20 */
-#define XCHAL_HAVE_CONNX_B_32B_MAC      0    /* 32-bit vector MAC (real and complex), FIR & FFT option on ConnX B10 & B20 */
-#define XCHAL_HAVE_CONNX_B_VITERBI      0    /* Viterbi option on ConnX B10 & B20 */
-#define XCHAL_HAVE_CONNX_B_TURBO        0    /* Turbo option on ConnX B10 & B20 */
-#define XCHAL_HAVE_CONNX_B_LDPC         0    /* LDPC option on ConnX B10 & B20 */
-#define XCHAL_HAVE_BBENEP		0	/* ConnX BBENEP pkgs */
-#define XCHAL_HAVE_BBENEP_SP_VFPU	0       /* sp_vfpu option on BBE-EP */
-#define XCHAL_HAVE_BSP3			0	/* ConnX BSP3 pkg */
-#define XCHAL_HAVE_BSP3_TRANSPOSE	0	/* BSP3 & transpose32x32 */
-#define XCHAL_HAVE_SSP16		0	/* ConnX SSP16 pkg */
-#define XCHAL_HAVE_SSP16_VITERBI	0	/* SSP16 & viterbi */
-#define XCHAL_HAVE_TURBO16		0	/* ConnX Turbo16 pkg */
-#define XCHAL_HAVE_BBP16		0	/* ConnX BBP16 pkg */
-#define XCHAL_HAVE_FLIX3		0	/* basic 3-way FLIX option */
-#define XCHAL_HAVE_GRIVPEP		0	/* General Release of IVPEP */
-#define XCHAL_HAVE_GRIVPEP_HISTOGRAM	0       /* Histogram option on GRIVPEP */
-
-#define XCHAL_HAVE_VISION	        0     /* Vision P5/P6 */
-#define XCHAL_VISION_SIMD16             0     /* simd16 for Vision P5/P6 */
-#define XCHAL_VISION_TYPE               0     /* Vision P5, P6, Q6, Q7 or Q8 */
-#define XCHAL_VISION_QUAD_MAC_TYPE      0     /* quad_mac option on Vision P6 */
-#define XCHAL_HAVE_VISION_HISTOGRAM     0     /* histogram option on Vision P5/P6 */
-#define XCHAL_HAVE_VISION_DP_VFPU       0     /* dp_vfpu option on Vision Q7/Q8 */
-#define XCHAL_HAVE_VISION_SP_VFPU       0     /* sp_vfpu option on Vision P5/P6/Q6/Q7 */
-#define XCHAL_HAVE_VISION_SP_VFPU_2XFMAC 0     /* sp_vfpu_2xfma option on Vision Q7 */
-#define XCHAL_HAVE_VISION_HP_VFPU       0     /* hp_vfpu option on Vision P6/Q6 */
-#define XCHAL_HAVE_VISION_HP_VFPU_2XFMAC 0     /* hp_vfpu_2xfma option on Vision Q7 */
-
-#define XCHAL_HAVE_VISIONC	        0     /* Vision C */
-
-#define XCHAL_HAVE_XNNE			0		/* XNNE */
-
-/*----------------------------------------------------------------------
-				MISC
-  ----------------------------------------------------------------------*/
-
-#define XCHAL_NUM_LOADSTORE_UNITS	2	/* load/store units */
-#define XCHAL_NUM_WRITEBUFFER_ENTRIES	16	/* size of write buffer */
-#define XCHAL_INST_FETCH_WIDTH		16	/* instr-fetch width in bytes */
-#define XCHAL_DATA_WIDTH		16	/* data width in bytes */
-#define XCHAL_DATA_PIPE_DELAY		2	/* d-side pipeline delay
-						   (1 = 5-stage, 2 = 7-stage) */
-#define XCHAL_CLOCK_GATING_GLOBAL	1	/* global clock gating */
-#define XCHAL_CLOCK_GATING_FUNCUNIT	1	/* funct. unit clock gating */
-/*  In T1050, applies to selected core load and store instructions (see ISA): */
-#define XCHAL_UNALIGNED_LOAD_EXCEPTION	1	/* unaligned loads cause exc. */
-#define XCHAL_UNALIGNED_STORE_EXCEPTION	1	/* unaligned stores cause exc.*/
-#define XCHAL_UNALIGNED_LOAD_HW		0	/* unaligned loads work in hw */
-#define XCHAL_UNALIGNED_STORE_HW	0	/* unaligned stores work in hw*/
-
-#define XCHAL_UNIFIED_LOADSTORE         0
-
-#define XCHAL_SW_VERSION		1406000	/* sw version of this header */
-#define XCHAL_SW_VERSION_MAJOR		14000	/* major ver# of sw          */
-#define XCHAL_SW_VERSION_MINOR		6	/* minor ver# of sw          */
-#define XCHAL_SW_VERSION_MICRO		0	/* micro ver# of sw          */
-#define XCHAL_SW_MINOR_VERSION		1406000	/* with zeroed micro */
-#define XCHAL_SW_MICRO_VERSION		1406000
-
-#define XCHAL_CORE_ID			"ACP_6_3_HiFi5_PROD_Linux"	/* alphanum core name
-						   (CoreID) set in the Xtensa
-						   Processor Generator */
-
-#define XCHAL_BUILD_UNIQUE_ID		0x000A28F5	/* 22-bit sw build ID */
-
-/*
- *  These definitions describe the hardware targeted by this software.
- */
-#define XCHAL_HW_CONFIGID0		0xC3038286	/* ConfigID hi 32 bits*/
-#define XCHAL_HW_CONFIGID1		0x29892812	/* ConfigID lo 32 bits*/
-#define XCHAL_HW_VERSION_NAME		"LX7.1.6"	/* full version name */
-#define XCHAL_HW_VERSION_MAJOR		2810	/* major ver# of targeted hw */
-#define XCHAL_HW_VERSION_MINOR		6	/* minor ver# of targeted hw */
-#define XCHAL_HW_VERSION_MICRO		0	/* subdot ver# of targeted hw */
-#define XCHAL_HW_VERSION		281060	/* major*100+(major<2810 ? minor : minor*10+micro) */
-#define XCHAL_HW_REL_LX7		1
-#define XCHAL_HW_REL_LX7_1		1
-#define XCHAL_HW_REL_LX7_1_6		1
-#define XCHAL_HW_CONFIGID_RELIABLE	1
-/*  If software targets a *range* of hardware versions, these are the bounds: */
-#define XCHAL_HW_MIN_VERSION_MAJOR	2810	/* major v of earliest tgt hw */
-#define XCHAL_HW_MIN_VERSION_MINOR	6	/* minor v of earliest tgt hw */
-#define XCHAL_HW_MIN_VERSION_MICRO	0	/* micro v of earliest tgt hw */
-#define XCHAL_HW_MIN_VERSION		281060	/* earliest targeted hw */
-#define XCHAL_HW_MAX_VERSION_MAJOR	2810	/* major v of latest tgt hw */
-#define XCHAL_HW_MAX_VERSION_MINOR	6	/* minor v of latest tgt hw */
-#define XCHAL_HW_MAX_VERSION_MICRO	0	/* micro v of latest tgt hw */
-#define XCHAL_HW_MAX_VERSION		281060	/* latest targeted hw */
-
-/*  Config is enabled for functional safety: */
-#define XCHAL_HAVE_FUNC_SAFETY		0
-
-/*  Config is enabled for secure operation: */
-#define XCHAL_HAVE_SECURE     		0
-
-#define XCHAL_HAVE_APB			0 
-
-/*----------------------------------------------------------------------
-				CACHE
-  ----------------------------------------------------------------------*/
-
-#define XCHAL_ICACHE_LINESIZE		128	/* I-cache line size in bytes */
-#define XCHAL_DCACHE_LINESIZE		128	/* D-cache line size in bytes */
-#define XCHAL_ICACHE_LINEWIDTH		7	/* log2(I line size in bytes) */
-#define XCHAL_DCACHE_LINEWIDTH		7	/* log2(D line size in bytes) */
-
-#define XCHAL_ICACHE_SIZE		131072	/* I-cache size in bytes or 0 */
-#define XCHAL_ICACHE_SIZE_LOG2		17
-#define XCHAL_DCACHE_SIZE		131072	/* D-cache size in bytes or 0 */
-#define XCHAL_DCACHE_SIZE_LOG2		17
-
-#define XCHAL_DCACHE_IS_WRITEBACK	1	/* writeback feature */
-#define XCHAL_DCACHE_IS_COHERENT	0	/* MP coherence feature */
-
-#define XCHAL_HAVE_PREFETCH		1	/* PREFCTL register */
-#define XCHAL_HAVE_PREFETCH_L1		1	/* prefetch to L1 cache */
-#define XCHAL_PREFETCH_CASTOUT_LINES	1	/* dcache pref. castout bufsz */
-#define XCHAL_PREFETCH_ENTRIES		16	/* cache prefetch entries */
-#define XCHAL_PREFETCH_BLOCK_ENTRIES	8	/* prefetch block streams */
-#define XCHAL_HAVE_CACHE_BLOCKOPS	1	/* block prefetch for caches */
-#define XCHAL_HAVE_CME_DOWNGRADES	0
-#define XCHAL_HAVE_ICACHE_TEST		1	/* Icache test instructions */
-#define XCHAL_HAVE_DCACHE_TEST		1	/* Dcache test instructions */
-#define XCHAL_HAVE_ICACHE_DYN_WAYS	1	/* Icache dynamic way support */
-#define XCHAL_HAVE_DCACHE_DYN_WAYS	1	/* Dcache dynamic way support */
-#define XCHAL_HAVE_ICACHE_DYN_ENABLE	1	/* Icache enabled via MEMCTL */
-#define XCHAL_HAVE_DCACHE_DYN_ENABLE	1	/* Dcache enabled via MEMCTL */
-
-#define XCHAL_L1SCACHE_SIZE		0
-#define XCHAL_L1SCACHE_SIZE_LOG2	0
-#define XCHAL_L1SCACHE_WAYS		1
-#define XCHAL_L1SCACHE_WAYS_LOG2	0
-#define XCHAL_L1SCACHE_ACCESS_SIZE	0
-#define XCHAL_L1SCACHE_BANKS		1
-
-#define XCHAL_L1VCACHE_SIZE		0
-
-#define XCHAL_HAVE_L2			0	/* NX L2 cache controller */
-#define XCHAL_HAVE_L2_CACHE		0
-#define XCHAL_NUM_CORES_IN_CLUSTER	0
-
-/* PRID_ID macros are for internal use only ... subject to removal */
-#define PRID_ID_SHIFT           0
-#define PRID_ID_BITS            4
-#define PRID_ID_MASK            0x0000000F
-
-/*  This one is a form of caching, though not architecturally visible:  */
-#define XCHAL_HAVE_BRANCH_PREDICTION	0	/* branch [target] prediction */
-
-
-
-
-/****************************************************************************
-    Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
- ****************************************************************************/
-
-
-#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
-
-/*----------------------------------------------------------------------
-				CACHE
-  ----------------------------------------------------------------------*/
-
-#define XCHAL_HAVE_PIF			1	/* any outbound bus present */
-
-#define XCHAL_HAVE_AXI			1	/* AXI bus */
-#define XCHAL_HAVE_AXI_ECC		1	/* ECC on AXI bus */
-#define XCHAL_HAVE_ACELITE		0	/* ACELite bus */
-
-#define XCHAL_HAVE_PIF_WR_RESP			1	/* pif write response */
-#define XCHAL_HAVE_PIF_REQ_ATTR			1	/* pif attribute */
-
-/*  If present, cache size in bytes == (ways * 2^(linewidth + setwidth)).  */
-
-/*  Number of cache sets in log2(lines per way):  */
-#define XCHAL_ICACHE_SETWIDTH		8
-#define XCHAL_DCACHE_SETWIDTH		8
-
-/*  Cache set associativity (number of ways):  */
-#define XCHAL_ICACHE_WAYS		4
-#define XCHAL_ICACHE_WAYS_LOG2		2
-#define XCHAL_DCACHE_WAYS		4
-#define XCHAL_DCACHE_WAYS_LOG2		2
-
-/*  Cache features:  */
-#define XCHAL_ICACHE_LINE_LOCKABLE	1
-#define XCHAL_DCACHE_LINE_LOCKABLE	1
-#define XCHAL_ICACHE_ECC_PARITY		0
-#define XCHAL_DCACHE_ECC_PARITY		0
-#define XCHAL_ICACHE_ECC_WIDTH		4
-#define XCHAL_DCACHE_ECC_WIDTH		1
-
-/*  Cache access size in bytes (affects operation of SICW instruction):  */
-#define XCHAL_ICACHE_ACCESS_SIZE	16
-#define XCHAL_DCACHE_ACCESS_SIZE	16
-
-#define XCHAL_DCACHE_BANKS		2	/* number of banks */
-
-/* The number of Cache lines associated with a single cache tag */
-#define XCHAL_DCACHE_LINES_PER_TAG_LOG2	0
-
-/*  Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits):  */
-#define XCHAL_CA_BITS			4
-
-
-/*----------------------------------------------------------------------
-			INTERNAL I/D RAM/ROMs and XLMI
-  ----------------------------------------------------------------------*/
-#define XCHAL_NUM_INSTROM		0	/* number of core instr. ROMs */
-#define XCHAL_NUM_INSTRAM		1	/* number of core instr. RAMs */
-#define XCHAL_NUM_DATAROM		0	/* number of core data ROMs */
-#define XCHAL_NUM_DATARAM		1	/* number of core data RAMs */
-#define XCHAL_NUM_URAM			0	/* number of core unified RAMs*/
-#define XCHAL_NUM_XLMI			0	/* number of core XLMI ports */
-#define	XCHAL_HAVE_IRAMCFG		0	/* IRAMxCFG register present */
-#define	XCHAL_HAVE_DRAMCFG		0	/* DRAMxCFG register present */
-
-/*  Instruction RAM 0:  */
-#define XCHAL_INSTRAM0_VADDR		0x7F000000	/* virtual address */
-#define XCHAL_INSTRAM0_PADDR		0x7F000000	/* physical address */
-#define XCHAL_INSTRAM0_SIZE		524288	/* size in bytes */
-#define XCHAL_INSTRAM0_ECC_PARITY	0	/* ECC/parity type, 0=none */
-#define XCHAL_HAVE_INSTRAM0		1
-#define XCHAL_INSTRAM0_HAVE_IDMA	0	/* idma supported by this local memory */
-
-/*  Data RAM 0:  */
-#define XCHAL_DATARAM0_VADDR		0xE0000000	/* virtual address */
-#define XCHAL_DATARAM0_PADDR		0xE0000000	/* physical address */
-#define XCHAL_DATARAM0_SIZE		524288	/* size in bytes */
-#define XCHAL_DATARAM0_ECC_PARITY	0	/* ECC/parity type, 0=none */
-#define XCHAL_DATARAM0_BANKS		2	/* number of banks */
-#define XCHAL_HAVE_DATARAM0		1
-#define XCHAL_DATARAM0_HAVE_IDMA	0	/* idma supported by this local memory */
-
-#define XCHAL_HAVE_IMEM_LOADSTORE	1	/* can load/store to IROM/IRAM*/
-
-
-/*----------------------------------------------------------------------
-			IDMA
-  ----------------------------------------------------------------------*/
-
-#define XCHAL_HAVE_IDMA			0
-
-
-
-/*----------------------------------------------------------------------
-			INTERRUPTS and TIMERS
-  ----------------------------------------------------------------------*/
-
-#define XCHAL_HAVE_INTERRUPTS		1	/* interrupt option */
-#define XCHAL_HAVE_NMI			1	/* non-maskable interrupt */
-#define XCHAL_HAVE_CCOUNT		1	/* CCOUNT reg. (timer option) */
-#define XCHAL_NUM_TIMERS		2	/* number of CCOMPAREn regs */
-#define XCHAL_NUM_INTERRUPTS		9	/* number of interrupts */
-#define XCHAL_NUM_INTERRUPTS_LOG2	4	/* ceil(log2(NUM_INTERRUPTS)) */
-#define XCHAL_NUM_EXTINTERRUPTS		5	/* num of external interrupts */
-#define XCHAL_NUM_INTLEVELS		6	/* number of interrupt levels
-						   (not including level zero) */
-
-
-#define XCHAL_HAVE_HIGHPRI_INTERRUPTS	1   /* med/high-pri. interrupts */
-#define XCHAL_EXCM_LEVEL		5	/* level masked by PS.EXCM */
-	/* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
-
-/*  Masks of interrupts at each interrupt level:  */
-#define XCHAL_INTLEVEL1_MASK		0x00000143
-#define XCHAL_INTLEVEL2_MASK		0x00000004
-#define XCHAL_INTLEVEL3_MASK		0x00000008
-#define XCHAL_INTLEVEL4_MASK		0x00000010
-#define XCHAL_INTLEVEL5_MASK		0x00000020
-#define XCHAL_INTLEVEL6_MASK		0x00000000
-#define XCHAL_INTLEVEL7_MASK		0x00000080
-
-/*  Masks of interrupts at each range 1..n of interrupt levels:  */
-#define XCHAL_INTLEVEL1_ANDBELOW_MASK	0x00000143
-#define XCHAL_INTLEVEL2_ANDBELOW_MASK	0x00000147
-#define XCHAL_INTLEVEL3_ANDBELOW_MASK	0x0000014F
-#define XCHAL_INTLEVEL4_ANDBELOW_MASK	0x0000015F
-#define XCHAL_INTLEVEL5_ANDBELOW_MASK	0x0000017F
-#define XCHAL_INTLEVEL6_ANDBELOW_MASK	0x0000017F
-#define XCHAL_INTLEVEL7_ANDBELOW_MASK	0x000001FF
-
-/*  Level of each interrupt:  */
-#define XCHAL_INT0_LEVEL		1
-#define XCHAL_INT1_LEVEL		1
-#define XCHAL_INT2_LEVEL		2
-#define XCHAL_INT3_LEVEL		3
-#define XCHAL_INT4_LEVEL		4
-#define XCHAL_INT5_LEVEL		5
-#define XCHAL_INT6_LEVEL		1
-#define XCHAL_INT7_LEVEL		7
-#define XCHAL_INT8_LEVEL		1
-#define XCHAL_DEBUGLEVEL		6	/* debug interrupt level */
-#define XCHAL_HAVE_DEBUG_EXTERN_INT	1	/* OCD external db interrupt */
-#define XCHAL_NMILEVEL			7	/* NMI "level" (for use with
-						   EXCSAVE/EPS/EPC_n, RFI n) */
-
-/*  Type of each interrupt:  */
-#define XCHAL_INT0_TYPE 	XTHAL_INTTYPE_TIMER
-#define XCHAL_INT1_TYPE 	XTHAL_INTTYPE_SOFTWARE
-#define XCHAL_INT2_TYPE 	XTHAL_INTTYPE_WRITE_ERROR
-#define XCHAL_INT3_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT4_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT5_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT6_TYPE 	XTHAL_INTTYPE_TIMER
-#define XCHAL_INT7_TYPE 	XTHAL_INTTYPE_NMI
-#define XCHAL_INT8_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-
-/*  Masks of interrupts for each type of interrupt:  */
-#define XCHAL_INTTYPE_MASK_UNCONFIGURED	0xFFFFFE00
-#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL	0x00000138
-#define XCHAL_INTTYPE_MASK_EXTERN_EDGE	0x00000000
-#define XCHAL_INTTYPE_MASK_NMI		0x00000080
-#define XCHAL_INTTYPE_MASK_SOFTWARE	0x00000002
-#define XCHAL_INTTYPE_MASK_TIMER	0x00000041
-#define XCHAL_INTTYPE_MASK_ETIE		0x00000000
-#define XCHAL_INTTYPE_MASK_WRITE_ERROR	0x00000004
-#define XCHAL_INTTYPE_MASK_DBG_REQUEST	0x00000000
-#define XCHAL_INTTYPE_MASK_BREAKIN	0x00000000
-#define XCHAL_INTTYPE_MASK_TRAX		0x00000000
-#define XCHAL_INTTYPE_MASK_PROFILING	0x00000000
-#define XCHAL_INTTYPE_MASK_IDMA_DONE	0x00000000
-#define XCHAL_INTTYPE_MASK_IDMA_ERR	0x00000000
-#define XCHAL_INTTYPE_MASK_GS_ERR	0x00000000
-#define XCHAL_INTTYPE_MASK_L2_ERR	0x00000000
-#define XCHAL_INTTYPE_MASK_L2_STATUS	0x00000000
-#define XCHAL_INTTYPE_MASK_COR_ECC_ERR	0x00000000
-#define XCHAL_INTTYPE_MASK_WWDT		0x00000000
-#define XCHAL_INTTYPE_MASK_FXLK		0x00000000
-
-/*  Interrupt numbers assigned to specific interrupt sources:  */
-#define XCHAL_TIMER0_INTERRUPT		0	/* CCOMPARE0 */
-#define XCHAL_TIMER1_INTERRUPT		6	/* CCOMPARE1 */
-#define XCHAL_TIMER2_INTERRUPT		XTHAL_TIMER_UNCONFIGURED
-#define XCHAL_TIMER3_INTERRUPT		XTHAL_TIMER_UNCONFIGURED
-#define XCHAL_NMI_INTERRUPT		7	/* non-maskable interrupt */
-#define XCHAL_WRITE_ERROR_INTERRUPT	2
-
-/*  Interrupt numbers for levels at which only one interrupt is configured:  */
-#define XCHAL_INTLEVEL2_NUM		2
-#define XCHAL_INTLEVEL3_NUM		3
-#define XCHAL_INTLEVEL4_NUM		4
-#define XCHAL_INTLEVEL5_NUM		5
-#define XCHAL_INTLEVEL7_NUM		7
-/*  (There are many interrupts each at level(s) 1.)  */
-
-
-/*
- *  External interrupt mapping.
- *  These macros describe how Xtensa processor interrupt numbers
- *  (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
- *  map to external BInterrupt<n> pins, for those interrupts
- *  configured as external (level-triggered, edge-triggered, or NMI).
- *  See the Xtensa processor databook for more details.
- */
-
-/*  Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number:  */
-#define XCHAL_EXTINT0_NUM		3	/* (intlevel 3) */
-#define XCHAL_EXTINT1_NUM		4	/* (intlevel 4) */
-#define XCHAL_EXTINT2_NUM		5	/* (intlevel 5) */
-#define XCHAL_EXTINT3_NUM		7	/* (intlevel 7) */
-#define XCHAL_EXTINT4_NUM		8	/* (intlevel 1) */
-/*  EXTERNAL BInterrupt pin numbers mapped to each core interrupt number:  */
-#define XCHAL_INT3_EXTNUM		0	/* (intlevel 3) */
-#define XCHAL_INT4_EXTNUM		1	/* (intlevel 4) */
-#define XCHAL_INT5_EXTNUM		2	/* (intlevel 5) */
-#define XCHAL_INT7_EXTNUM		3	/* (intlevel 7) */
-#define XCHAL_INT8_EXTNUM		4	/* (intlevel 1) */
-
-#define	XCHAL_HAVE_ISB			0	/* No ISB */
-#define	XCHAL_ISB_VADDR			0	/* N/A    */
-#define	XCHAL_HAVE_ITB			0	/* No ITB */
-#define	XCHAL_ITB_VADDR			0	/* N/A    */
-
-#define	XCHAL_HAVE_KSL			0	/* Kernel Stack Limit */
-#define	XCHAL_HAVE_ISL			0	/* Interrupt Stack Limit */
-#define	XCHAL_HAVE_PSL			0	/* Pageable Stack Limit */
-
-
-/*----------------------------------------------------------------------
-			EXCEPTIONS and VECTORS
-  ----------------------------------------------------------------------*/
-
-#define XCHAL_XEA_VERSION		2	/* Xtensa Exception Architecture
-						   number: 1 == XEA1 (until T1050)
-							   2 == XEA2 (T1040 onwards)
-							   3 == XEA3 (LX8/NX/SX onwards)
-							   0 == XEAX (extern) or TX */
-#define XCHAL_HAVE_XEA1			0	/* Exception Architecture 1 */
-#define XCHAL_HAVE_XEA2			1	/* Exception Architecture 2 */
-#define XCHAL_HAVE_XEA3			0	/* Exception Architecture 3 */
-#define XCHAL_HAVE_XEAX			0	/* External Exception Arch. */
-#define XCHAL_HAVE_EXCEPTIONS		1	/* exception option */
-#define XCHAL_HAVE_IMPRECISE_EXCEPTIONS	0	/* imprecise exception option */
-#define	XCHAL_EXCCAUSE_NUM		64	/* Number of exceptions */
-#define XCHAL_HAVE_HALT			0	/* halt architecture option */
-#define XCHAL_HAVE_BOOTLOADER		0	/* boot loader (for TX) */
-#define XCHAL_HAVE_MEM_ECC_PARITY	0	/* local memory ECC/parity */
-#define XCHAL_HAVE_VECTOR_SELECT	0	/* relocatable vectors */
-#define XCHAL_HAVE_VECBASE		0	/* relocatable vectors */
-
-#define XCHAL_RESET_VECOFS		0x00000000
-#define XCHAL_RESET_VECTOR_VADDR	0x7F000000
-#define XCHAL_RESET_VECTOR_PADDR	0x7F000000
-#define XCHAL_USER_VECOFS		0x00000000
-#define XCHAL_USER_VECTOR_VADDR		0x7F000740
-#define XCHAL_USER_VECTOR_PADDR		0x7F000740
-#define XCHAL_KERNEL_VECOFS		0x00000000
-#define XCHAL_KERNEL_VECTOR_VADDR	0x7F000700
-#define XCHAL_KERNEL_VECTOR_PADDR	0x7F000700
-#define XCHAL_DOUBLEEXC_VECOFS		0x00000000
-#define XCHAL_DOUBLEEXC_VECTOR_VADDR	0x7F0007C0
-#define XCHAL_DOUBLEEXC_VECTOR_PADDR	0x7F0007C0
-#define XCHAL_WINDOW_OF4_VECOFS		0x00000000
-#define XCHAL_WINDOW_UF4_VECOFS		0x00000040
-#define XCHAL_WINDOW_OF8_VECOFS		0x00000080
-#define XCHAL_WINDOW_UF8_VECOFS		0x000000C0
-#define XCHAL_WINDOW_OF12_VECOFS	0x00000100
-#define XCHAL_WINDOW_UF12_VECOFS	0x00000140
-#define XCHAL_WINDOW_VECTORS_VADDR	0x7F000400
-#define XCHAL_WINDOW_VECTORS_PADDR	0x7F000400
-#define XCHAL_INTLEVEL2_VECOFS		0x00000000
-#define XCHAL_INTLEVEL2_VECTOR_VADDR	0x7F000580
-#define XCHAL_INTLEVEL2_VECTOR_PADDR	0x7F000580
-#define XCHAL_INTLEVEL3_VECOFS		0x00000000
-#define XCHAL_INTLEVEL3_VECTOR_VADDR	0x7F0005C0
-#define XCHAL_INTLEVEL3_VECTOR_PADDR	0x7F0005C0
-#define XCHAL_INTLEVEL4_VECOFS		0x00000000
-#define XCHAL_INTLEVEL4_VECTOR_VADDR	0x7F000600
-#define XCHAL_INTLEVEL4_VECTOR_PADDR	0x7F000600
-#define XCHAL_INTLEVEL5_VECOFS		0x00000000
-#define XCHAL_INTLEVEL5_VECTOR_VADDR	0x7F000640
-#define XCHAL_INTLEVEL5_VECTOR_PADDR	0x7F000640
-#define XCHAL_INTLEVEL6_VECOFS		0x00000000
-#define XCHAL_INTLEVEL6_VECTOR_VADDR	0x7F000680
-#define XCHAL_INTLEVEL6_VECTOR_PADDR	0x7F000680
-#define XCHAL_DEBUG_VECOFS		XCHAL_INTLEVEL6_VECOFS
-#define XCHAL_DEBUG_VECTOR_VADDR	XCHAL_INTLEVEL6_VECTOR_VADDR
-#define XCHAL_DEBUG_VECTOR_PADDR	XCHAL_INTLEVEL6_VECTOR_PADDR
-#define XCHAL_NMI_VECOFS		0x00000000
-#define XCHAL_NMI_VECTOR_VADDR		0x7F0006C0
-#define XCHAL_NMI_VECTOR_PADDR		0x7F0006C0
-#define XCHAL_INTLEVEL7_VECOFS		XCHAL_NMI_VECOFS
-#define XCHAL_INTLEVEL7_VECTOR_VADDR	XCHAL_NMI_VECTOR_VADDR
-#define XCHAL_INTLEVEL7_VECTOR_PADDR	XCHAL_NMI_VECTOR_PADDR
-
-
-/*----------------------------------------------------------------------
-				DEBUG MODULE
-  ----------------------------------------------------------------------*/
-
-/*  Misc  */
-#define XCHAL_HAVE_DEBUG_ERI		0	/* ERI to debug module */
-#define XCHAL_HAVE_DEBUG_APB		0	/* APB to debug module */
-#define XCHAL_HAVE_DEBUG_JTAG		1	/* JTAG to debug module */
-
-/*  On-Chip Debug (OCD)  */
-#define XCHAL_HAVE_OCD			1	/* OnChipDebug option */
-#define XCHAL_NUM_IBREAK		2	/* number of IBREAKn regs */
-#define XCHAL_NUM_DBREAK		2	/* number of DBREAKn regs */
-#define XCHAL_HAVE_OCD_DIR_ARRAY	0	/* faster OCD option (to LX4) */
-#define XCHAL_HAVE_OCD_LS32DDR		1	/* L32DDR/S32DDR (faster OCD) */
-
-/*  TRAX (in core)  */
-#define XCHAL_HAVE_TRAX			0	/* TRAX in debug module */
-#define XCHAL_TRAX_MEM_SIZE		0	/* TRAX memory size in bytes */
-#define XCHAL_TRAX_MEM_SHAREABLE	0	/* start/end regs; ready sig. */
-#define XCHAL_TRAX_ATB_WIDTH		0	/* ATB width (bits), 0=no ATB */
-#define XCHAL_TRAX_TIME_WIDTH		0	/* timestamp bitwidth, 0=none */
-
-/*  Perf counters  */
-#define XCHAL_NUM_PERF_COUNTERS		0	/* performance counters */
-
-
-/*----------------------------------------------------------------------
-				MMU
-  ----------------------------------------------------------------------*/
-
-/*  See core-matmap.h header file for more details.  */
-
-#define XCHAL_HAVE_TLBS			1	/* inverse of HAVE_CACHEATTR */
-#define XCHAL_HAVE_SPANNING_WAY		1	/* one way maps I+D 4GB vaddr */
-#define XCHAL_SPANNING_WAY		0	/* TLB spanning way number */
-#define XCHAL_HAVE_IDENTITY_MAP		0	/* vaddr == paddr always */
-#define XCHAL_HAVE_CACHEATTR		0	/* CACHEATTR register present */
-#define XCHAL_HAVE_MIMIC_CACHEATTR	0	/* region protection */
-#define XCHAL_HAVE_XLT_CACHEATTR	1	/* region prot. w/translation */
-#define XCHAL_HAVE_PTP_MMU		0	/* full MMU (with page table
-						   [autorefill] and protection)
-						   usable for an MMU-based OS */
-
-/*  If none of the above last 5 are set, it's a custom TLB configuration.  */
-
-#define XCHAL_MMU_ASID_BITS		0	/* number of bits in ASIDs */
-#define XCHAL_MMU_RINGS			1	/* number of rings (1..4) */
-#define XCHAL_MMU_RING_BITS		0	/* num of bits in RING field */
-
-/*----------------------------------------------------------------------
-				MPU
-  ----------------------------------------------------------------------*/
-#define XCHAL_HAVE_MPU			0 
-#define XCHAL_MPU_ENTRIES		0
-#define XCHAL_MPU_LOCK			0
-
-#define XCHAL_MPU_ALIGN_REQ		1	/* MPU requires alignment of entries to background map */
-#define XCHAL_MPU_BACKGROUND_ENTRIES	0	/* number of entries in bg map*/
-#define XCHAL_MPU_BG_CACHEADRDIS	0	/* default CACHEADRDIS for bg */
- 
-#define XCHAL_MPU_ALIGN_BITS		0
-#define XCHAL_MPU_ALIGN			0
-
-/*-----------------------------------------------------------------------
-				CSR Parity
-------------------------------------------------------------------------*/
-#define XCHAL_HAVE_CSR_PARITY		0
-
-
-/*----------------------------------------------------------------------
-				FLEX-LOCK
-------------------------------------------------------------------------*/
-
-#define XCHAL_HAVE_FXLK			0
-
-/*----------------------------------------------------------------------
-				WWDT (Windowed Watchdog Timer)
-------------------------------------------------------------------------*/
-#define XCHAL_HAVE_WWDT			0
-#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
-
-
-#endif /* XTENSA_CORE_CONFIGURATION_H_ */
-
diff --git a/src/platform/amd/acp_6_3/include/arch/xtensa/config/core-matmap.h b/src/platform/amd/acp_6_3/include/arch/xtensa/config/core-matmap.h
deleted file mode 100644
index 5195b5230905..000000000000
--- a/src/platform/amd/acp_6_3/include/arch/xtensa/config/core-matmap.h
+++ /dev/null
@@ -1,317 +0,0 @@
-/* 
- * xtensa/config/core-matmap.h -- Memory access and translation mapping
- *	parameters (CHAL) of the Xtensa processor core configuration.
- *
- *  If you are using Xtensa Tools, see <xtensa/config/core.h> (which includes
- *  this file) for more details.
- *
- *  In the Xtensa processor products released to date, all parameters
- *  defined in this file are derivable (at least in theory) from
- *  information contained in the core-isa.h header file.
- *  In particular, the following core configuration parameters are relevant:
- *	XCHAL_HAVE_CACHEATTR
- *	XCHAL_HAVE_MIMIC_CACHEATTR
- *	XCHAL_HAVE_XLT_CACHEATTR
- *	XCHAL_HAVE_PTP_MMU
- *	XCHAL_ITLB_ARF_ENTRIES_LOG2
- *	XCHAL_DTLB_ARF_ENTRIES_LOG2
- *	XCHAL_DCACHE_IS_WRITEBACK
- *	XCHAL_ICACHE_SIZE		(presence of I-cache)
- *	XCHAL_DCACHE_SIZE		(presence of D-cache)
- *	XCHAL_HW_VERSION_MAJOR
- *	XCHAL_HW_VERSION_MINOR
- */
-
-/* Customer ID=7490; Build=0xa28f5; Copyright (c) 1999-2022 Tensilica Inc.
-
-   Permission is hereby granted, free of charge, to any person obtaining
-   a copy of this software and associated documentation files (the
-   "Software"), to deal in the Software without restriction, including
-   without limitation the rights to use, copy, modify, merge, publish,
-   distribute, sublicense, and/or sell copies of the Software, and to
-   permit persons to whom the Software is furnished to do so, subject to
-   the following conditions:
-
-   The above copyright notice and this permission notice shall be included
-   in all copies or substantial portions of the Software.
-
-   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
-
-
-#ifndef XTENSA_CONFIG_CORE_MATMAP_H
-#define XTENSA_CONFIG_CORE_MATMAP_H
-
-
-/*----------------------------------------------------------------------
-			CACHE (MEMORY ACCESS) ATTRIBUTES
-  ----------------------------------------------------------------------*/
-
-
-
-/*  Cache Attribute encodings -- lists of access modes for each cache attribute:  */
-#define XCHAL_FCA_LIST		XTHAL_FAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_FAM_CACHED	XCHAL_SEP \
-				XTHAL_FAM_BYPASS	XCHAL_SEP \
-				XTHAL_FAM_CACHED	XCHAL_SEP \
-				XTHAL_FAM_CACHED	XCHAL_SEP \
-				XTHAL_FAM_CACHED	XCHAL_SEP \
-				XTHAL_FAM_BYPASS	XCHAL_SEP \
-				XTHAL_FAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_FAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_FAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_FAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_FAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_FAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_FAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_FAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_FAM_EXCEPTION
-#define XCHAL_LCA_LIST		XTHAL_LAM_CACHED_NOALLOC	XCHAL_SEP \
-				XTHAL_LAM_CACHED	XCHAL_SEP \
-				XTHAL_LAM_BYPASSG	XCHAL_SEP \
-				XTHAL_LAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_LAM_CACHED	XCHAL_SEP \
-				XTHAL_LAM_CACHED	XCHAL_SEP \
-				XTHAL_LAM_BYPASSG	XCHAL_SEP \
-				XTHAL_LAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_LAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_LAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_LAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_LAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_LAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_LAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_LAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_LAM_EXCEPTION
-#define XCHAL_SCA_LIST		XTHAL_SAM_WRITETHRU	XCHAL_SEP \
-				XTHAL_SAM_WRITETHRU	XCHAL_SEP \
-				XTHAL_SAM_BYPASS	XCHAL_SEP \
-				XTHAL_SAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_SAM_WRITEBACK	XCHAL_SEP \
-				XTHAL_SAM_WRITEBACK_NOALLOC	XCHAL_SEP \
-				XTHAL_SAM_BYPASS	XCHAL_SEP \
-				XTHAL_SAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_SAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_SAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_SAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_SAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_SAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_SAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_SAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_SAM_EXCEPTION
-
-#define XCHAL_CA_R   (0xC0 | 0x40000000)
-#define XCHAL_CA_RX  (0xD0 | 0x40000000)
-#define XCHAL_CA_RW  (0xE0 | 0x40000000)
-#define XCHAL_CA_RWX (0xF0 | 0x40000000)
-
-/*
- *  Specific encoded cache attribute values of general interest.
- *  If a specific cache mode is not available, the closest available
- *  one is returned instead (eg. writethru instead of writeback,
- *  bypass instead of writethru).
- */
-#define XCHAL_CA_BYPASS  		2	/* cache disabled (bypassed) mode */
-#define XCHAL_CA_BYPASSBUF  		6	/* cache disabled (bypassed) bufferable mode */
-#define XCHAL_CA_WRITETHRU		1	/* cache enabled (write-through) mode */
-#define XCHAL_CA_WRITEBACK		4	/* cache enabled (write-back) mode */
-#define XCHAL_HAVE_CA_WRITEBACK_NOALLOC	1	/* write-back no-allocate availability */
-#define XCHAL_CA_WRITEBACK_NOALLOC	5	/* cache enabled (write-back no-allocate) mode */
-#define XCHAL_CA_ILLEGAL		15	/* no access allowed (all cause exceptions) mode */
-
-/*----------------------------------------------------------------------
-				MMU
-  ----------------------------------------------------------------------*/
-
-/*
- *  General notes on MMU parameters.
- *
- *  Terminology:
- *	ASID = address-space ID (acts as an "extension" of virtual addresses)
- *	VPN  = virtual page number
- *	PPN  = physical page number
- *	CA   = encoded cache attribute (access modes)
- *	TLB  = translation look-aside buffer (term is stretched somewhat here)
- *	I    = instruction (fetch accesses)
- *	D    = data (load and store accesses)
- *	way  = each TLB (ITLB and DTLB) consists of a number of "ways"
- *		that simultaneously match the virtual address of an access;
- *		a TLB successfully translates a virtual address if exactly
- *		one way matches the vaddr; if none match, it is a miss;
- *		if multiple match, one gets a "multihit" exception;
- *		each way can be independently configured in terms of number of
- *		entries, page sizes, which fields are writable or constant, etc.
- *	set  = group of contiguous ways with exactly identical parameters
- *	ARF  = auto-refill; hardware services a 1st-level miss by loading a PTE
- *		from the page table and storing it in one of the auto-refill ways;
- *		if this PTE load also misses, a miss exception is posted for s/w.
- *	min-wired = a "min-wired" way can be used to map a single (minimum-sized)
- * 		page arbitrarily under program control; it has a single entry,
- *		is non-auto-refill (some other way(s) must be auto-refill),
- *		all its fields (VPN, PPN, ASID, CA) are all writable, and it
- *		supports the XCHAL_MMU_MIN_PTE_PAGE_SIZE page size (a current
- *		restriction is that this be the only page size it supports).
- *
- *  TLB way entries are virtually indexed.
- *  TLB ways that support multiple page sizes:
- *	- must have all writable VPN and PPN fields;
- *	- can only use one page size at any given time (eg. setup at startup),
- *	  selected by the respective ITLBCFG or DTLBCFG special register,
- *	  whose bits n*4+3 .. n*4 index the list of page sizes for way n
- *	  (XCHAL_xTLB_SETm_PAGESZ_LOG2_LIST for set m corresponding to way n);
- *	  this list may be sparse for auto-refill ways because auto-refill
- *	  ways have independent lists of supported page sizes sharing a
- *	  common encoding with PTE entries; the encoding is the index into
- *	  this list; unsupported sizes for a given way are zero in the list;
- *	  selecting unsupported sizes results in undefine hardware behaviour;
- *	- is only possible for ways 0 thru 7 (due to ITLBCFG/DTLBCFG definition).
- */
-
-#define XCHAL_MMU_ASID_INVALID		0	/* ASID value indicating invalid address space */
-#define XCHAL_MMU_ASID_KERNEL		0	/* ASID value indicating kernel (ring 0) address space */
-#define XCHAL_MMU_SR_BITS		0	/* number of size-restriction bits supported */
-#define XCHAL_MMU_CA_BITS		4	 /* number of bits needed to hold cache attribute encoding */
-#define XCHAL_MMU_MAX_PTE_PAGE_SIZE	29	/* max page size in a PTE structure (log2) */
-#define XCHAL_MMU_MIN_PTE_PAGE_SIZE	29	/* min page size in a PTE structure (log2) */
-
-
-/***  Instruction TLB:  ***/
-
-#define XCHAL_ITLB_WAY_BITS		0	/* number of bits holding the ways */
-#define XCHAL_ITLB_WAYS			1	/* number of ways (n-way set-associative TLB) */
-#define XCHAL_ITLB_ARF_WAYS		0	/* number of auto-refill ways */
-#define XCHAL_ITLB_SETS			1	/* number of sets (groups of ways with identical settings) */
-
-/*  Way set to which each way belongs:  */
-#define XCHAL_ITLB_WAY0_SET		0
-
-/*  Ways sets that are used by hardware auto-refill (ARF):  */
-#define XCHAL_ITLB_ARF_SETS		0	/* number of auto-refill sets */
-
-/*  Way sets that are "min-wired" (see terminology comment above):  */
-#define XCHAL_ITLB_MINWIRED_SETS	0	/* number of "min-wired" sets */
-
-
-/*  ITLB way set 0 (group of ways 0 thru 0):  */
-#define XCHAL_ITLB_SET0_WAY			0	/* index of first way in this way set */
-#define XCHAL_ITLB_SET0_WAYS			1	/* number of (contiguous) ways in this way set */
-#define XCHAL_ITLB_SET0_ENTRIES_LOG2		3	/* log2(number of entries in this way) */
-#define XCHAL_ITLB_SET0_ENTRIES			8	/* number of entries in this way (always a power of 2) */
-#define XCHAL_ITLB_SET0_ARF			0	/* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
-#define XCHAL_ITLB_SET0_PAGESIZES		1	/* number of supported page sizes in this way */
-#define XCHAL_ITLB_SET0_PAGESZ_BITS		0	/* number of bits to encode the page size */
-#define XCHAL_ITLB_SET0_PAGESZ_LOG2_MIN		29	/* log2(minimum supported page size) */
-#define XCHAL_ITLB_SET0_PAGESZ_LOG2_MAX		29	/* log2(maximum supported page size) */
-#define XCHAL_ITLB_SET0_PAGESZ_LOG2_LIST	29	/* list of log2(page size)s, separated by XCHAL_SEP;
-							   2^PAGESZ_BITS entries in list, unsupported entries are zero */
-#define XCHAL_ITLB_SET0_ASID_CONSTMASK		0	/* constant ASID bits; 0 if all writable */
-#define XCHAL_ITLB_SET0_VPN_CONSTMASK		0x00000000	/* constant VPN bits, not including entry index bits; 0 if all writable */
-#define XCHAL_ITLB_SET0_PPN_CONSTMASK		0	/* constant PPN bits, including entry index bits; 0 if all writable */
-#define XCHAL_ITLB_SET0_CA_CONSTMASK		0	/* constant CA bits; 0 if all writable */
-#define XCHAL_ITLB_SET0_ASID_RESET		0	/* 1 if ASID reset values defined (and all writable); 0 otherwise */
-#define XCHAL_ITLB_SET0_VPN_RESET		0	/* 1 if VPN reset values defined (and all writable); 0 otherwise */
-#define XCHAL_ITLB_SET0_PPN_RESET		1	/* 1 if PPN reset values defined (and all writable); 0 otherwise */
-#define XCHAL_ITLB_SET0_CA_RESET		1	/* 1 if CA reset values defined (and all writable); 0 otherwise */
-/*  Constant VPN values for each entry of ITLB way set 0 (because VPN_CONSTMASK is non-zero):  */
-#define XCHAL_ITLB_SET0_E0_VPN_CONST		0x00000000
-#define XCHAL_ITLB_SET0_E1_VPN_CONST		0x20000000
-#define XCHAL_ITLB_SET0_E2_VPN_CONST		0x40000000
-#define XCHAL_ITLB_SET0_E3_VPN_CONST		0x60000000
-#define XCHAL_ITLB_SET0_E4_VPN_CONST		0x80000000
-#define XCHAL_ITLB_SET0_E5_VPN_CONST		0xA0000000
-#define XCHAL_ITLB_SET0_E6_VPN_CONST		0xC0000000
-#define XCHAL_ITLB_SET0_E7_VPN_CONST		0xE0000000
-/*  Reset PPN values for each entry of ITLB way set 0 (because SET0_PPN_RESET is non-zero):  */
-#define XCHAL_ITLB_SET0_E0_PPN_RESET		0x00000000
-#define XCHAL_ITLB_SET0_E1_PPN_RESET		0x20000000
-#define XCHAL_ITLB_SET0_E2_PPN_RESET		0x40000000
-#define XCHAL_ITLB_SET0_E3_PPN_RESET		0x60000000
-#define XCHAL_ITLB_SET0_E4_PPN_RESET		0x80000000
-#define XCHAL_ITLB_SET0_E5_PPN_RESET		0xA0000000
-#define XCHAL_ITLB_SET0_E6_PPN_RESET		0xC0000000
-#define XCHAL_ITLB_SET0_E7_PPN_RESET		0xE0000000
-/*  Reset CA values for each entry of ITLB way set 0 (because SET0_CA_RESET is non-zero):  */
-#define XCHAL_ITLB_SET0_E0_CA_RESET		0x02
-#define XCHAL_ITLB_SET0_E1_CA_RESET		0x02
-#define XCHAL_ITLB_SET0_E2_CA_RESET		0x02
-#define XCHAL_ITLB_SET0_E3_CA_RESET		0x02
-#define XCHAL_ITLB_SET0_E4_CA_RESET		0x02
-#define XCHAL_ITLB_SET0_E5_CA_RESET		0x02
-#define XCHAL_ITLB_SET0_E6_CA_RESET		0x02
-#define XCHAL_ITLB_SET0_E7_CA_RESET		0x02
-
-
-/***  Data TLB:  ***/
-
-#define XCHAL_DTLB_WAY_BITS		0	/* number of bits holding the ways */
-#define XCHAL_DTLB_WAYS			1	/* number of ways (n-way set-associative TLB) */
-#define XCHAL_DTLB_ARF_WAYS		0	/* number of auto-refill ways */
-#define XCHAL_DTLB_SETS			1	/* number of sets (groups of ways with identical settings) */
-
-/*  Way set to which each way belongs:  */
-#define XCHAL_DTLB_WAY0_SET		0
-
-/*  Ways sets that are used by hardware auto-refill (ARF):  */
-#define XCHAL_DTLB_ARF_SETS		0	/* number of auto-refill sets */
-
-/*  Way sets that are "min-wired" (see terminology comment above):  */
-#define XCHAL_DTLB_MINWIRED_SETS	0	/* number of "min-wired" sets */
-
-
-/*  DTLB way set 0 (group of ways 0 thru 0):  */
-#define XCHAL_DTLB_SET0_WAY			0	/* index of first way in this way set */
-#define XCHAL_DTLB_SET0_WAYS			1	/* number of (contiguous) ways in this way set */
-#define XCHAL_DTLB_SET0_ENTRIES_LOG2		3	/* log2(number of entries in this way) */
-#define XCHAL_DTLB_SET0_ENTRIES			8	/* number of entries in this way (always a power of 2) */
-#define XCHAL_DTLB_SET0_ARF			0	/* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
-#define XCHAL_DTLB_SET0_PAGESIZES		1	/* number of supported page sizes in this way */
-#define XCHAL_DTLB_SET0_PAGESZ_BITS		0	/* number of bits to encode the page size */
-#define XCHAL_DTLB_SET0_PAGESZ_LOG2_MIN		29	/* log2(minimum supported page size) */
-#define XCHAL_DTLB_SET0_PAGESZ_LOG2_MAX		29	/* log2(maximum supported page size) */
-#define XCHAL_DTLB_SET0_PAGESZ_LOG2_LIST	29	/* list of log2(page size)s, separated by XCHAL_SEP;
-							   2^PAGESZ_BITS entries in list, unsupported entries are zero */
-#define XCHAL_DTLB_SET0_ASID_CONSTMASK		0	/* constant ASID bits; 0 if all writable */
-#define XCHAL_DTLB_SET0_VPN_CONSTMASK		0x00000000	/* constant VPN bits, not including entry index bits; 0 if all writable */
-#define XCHAL_DTLB_SET0_PPN_CONSTMASK		0	/* constant PPN bits, including entry index bits; 0 if all writable */
-#define XCHAL_DTLB_SET0_CA_CONSTMASK		0	/* constant CA bits; 0 if all writable */
-#define XCHAL_DTLB_SET0_ASID_RESET		0	/* 1 if ASID reset values defined (and all writable); 0 otherwise */
-#define XCHAL_DTLB_SET0_VPN_RESET		0	/* 1 if VPN reset values defined (and all writable); 0 otherwise */
-#define XCHAL_DTLB_SET0_PPN_RESET		1	/* 1 if PPN reset values defined (and all writable); 0 otherwise */
-#define XCHAL_DTLB_SET0_CA_RESET		1	/* 1 if CA reset values defined (and all writable); 0 otherwise */
-/*  Constant VPN values for each entry of DTLB way set 0 (because VPN_CONSTMASK is non-zero):  */
-#define XCHAL_DTLB_SET0_E0_VPN_CONST		0x00000000
-#define XCHAL_DTLB_SET0_E1_VPN_CONST		0x20000000
-#define XCHAL_DTLB_SET0_E2_VPN_CONST		0x40000000
-#define XCHAL_DTLB_SET0_E3_VPN_CONST		0x60000000
-#define XCHAL_DTLB_SET0_E4_VPN_CONST		0x80000000
-#define XCHAL_DTLB_SET0_E5_VPN_CONST		0xA0000000
-#define XCHAL_DTLB_SET0_E6_VPN_CONST		0xC0000000
-#define XCHAL_DTLB_SET0_E7_VPN_CONST		0xE0000000
-/*  Reset PPN values for each entry of DTLB way set 0 (because SET0_PPN_RESET is non-zero):  */
-#define XCHAL_DTLB_SET0_E0_PPN_RESET		0x00000000
-#define XCHAL_DTLB_SET0_E1_PPN_RESET		0x20000000
-#define XCHAL_DTLB_SET0_E2_PPN_RESET		0x40000000
-#define XCHAL_DTLB_SET0_E3_PPN_RESET		0x60000000
-#define XCHAL_DTLB_SET0_E4_PPN_RESET		0x80000000
-#define XCHAL_DTLB_SET0_E5_PPN_RESET		0xA0000000
-#define XCHAL_DTLB_SET0_E6_PPN_RESET		0xC0000000
-#define XCHAL_DTLB_SET0_E7_PPN_RESET		0xE0000000
-/*  Reset CA values for each entry of DTLB way set 0 (because SET0_CA_RESET is non-zero):  */
-#define XCHAL_DTLB_SET0_E0_CA_RESET		0x02
-#define XCHAL_DTLB_SET0_E1_CA_RESET		0x02
-#define XCHAL_DTLB_SET0_E2_CA_RESET		0x02
-#define XCHAL_DTLB_SET0_E3_CA_RESET		0x02
-#define XCHAL_DTLB_SET0_E4_CA_RESET		0x02
-#define XCHAL_DTLB_SET0_E5_CA_RESET		0x02
-#define XCHAL_DTLB_SET0_E6_CA_RESET		0x02
-#define XCHAL_DTLB_SET0_E7_CA_RESET		0x02
-
-
-
-
-#endif /*XTENSA_CONFIG_CORE_MATMAP_H*/
-
diff --git a/src/platform/amd/acp_6_3/include/arch/xtensa/config/defs.h b/src/platform/amd/acp_6_3/include/arch/xtensa/config/defs.h
deleted file mode 100644
index 0da4586ce0d3..000000000000
--- a/src/platform/amd/acp_6_3/include/arch/xtensa/config/defs.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/* Definitions for Xtensa instructions, types, and protos. */
-
-/* Customer ID=12153; Build=0x878bf; Copyright (c) 2003-2004 Tensilica Inc.
-
-   Permission is hereby granted, free of charge, to any person obtaining
-   a copy of this software and associated documentation files (the
-   "Software"), to deal in the Software without restriction, including
-   without limitation the rights to use, copy, modify, merge, publish,
-   distribute, sublicense, and/or sell copies of the Software, and to
-   permit persons to whom the Software is furnished to do so, subject to
-   the following conditions:
-
-   The above copyright notice and this permission notice shall be included
-   in all copies or substantial portions of the Software.
-
-   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
-
-/* NOTE: This file exists only for backward compatibility with T1050
-   and earlier Xtensa releases.  It includes only a subset of the
-   available header files.  */
-
-#ifndef _XTENSA_BASE_HEADER
-#define _XTENSA_BASE_HEADER
-
-#ifdef __XTENSA__
-
-#include <xtensa/tie/xt_core.h>
-#include <xtensa/tie/xt_misc.h>
-#include <xtensa/tie/xt_booleans.h>
-
-#endif /* __XTENSA__ */
-#endif /* !_XTENSA_BASE_HEADER */
diff --git a/src/platform/amd/acp_6_3/include/arch/xtensa/config/specreg.h b/src/platform/amd/acp_6_3/include/arch/xtensa/config/specreg.h
deleted file mode 100644
index 0c54c7290dd6..000000000000
--- a/src/platform/amd/acp_6_3/include/arch/xtensa/config/specreg.h
+++ /dev/null
@@ -1,108 +0,0 @@
-/*
- * Xtensa Special Register symbolic names
- */
-
-/* $Id: //depot/rel/Homewood/ib.6/Xtensa/SWConfig/hal/specreg.h.tpp#1 $ */
-
-/* Customer ID=7490; Build=0xa28f5; Copyright (c) 1998-2002 Tensilica Inc.
-
-   Permission is hereby granted, free of charge, to any person obtaining
-   a copy of this software and associated documentation files (the
-   "Software"), to deal in the Software without restriction, including
-   without limitation the rights to use, copy, modify, merge, publish,
-   distribute, sublicense, and/or sell copies of the Software, and to
-   permit persons to whom the Software is furnished to do so, subject to
-   the following conditions:
-
-   The above copyright notice and this permission notice shall be included
-   in all copies or substantial portions of the Software.
-
-   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
-
-#ifndef XTENSA_SPECREG_H
-#define XTENSA_SPECREG_H
-
-/*  Include these special register bitfield definitions, for historical reasons:  */
-#include <xtensa/corebits.h>
-
-
-/*  Special registers:  */
-#define LBEG		0
-#define LEND		1
-#define LCOUNT		2
-#define SAR		3
-#define BR		4
-#define SCOMPARE1	12
-#define PREFCTL		40
-#define WINDOWBASE	72
-#define WINDOWSTART	73
-#define IBREAKENABLE	96
-#define MEMCTL		97
-#define ATOMCTL		99
-#define DDR		104
-#define IBREAKA_0	128
-#define IBREAKA_1	129
-#define DBREAKA_0	144
-#define DBREAKA_1	145
-#define DBREAKC_0	160
-#define DBREAKC_1	161
-#define EPC_1		177
-#define EPC_2		178
-#define EPC_3		179
-#define EPC_4		180
-#define EPC_5		181
-#define EPC_6		182
-#define EPC_7		183
-#define DEPC		192
-#define EPS_2		194
-#define EPS_3		195
-#define EPS_4		196
-#define EPS_5		197
-#define EPS_6		198
-#define EPS_7		199
-#define EXCSAVE_1	209
-#define EXCSAVE_2	210
-#define EXCSAVE_3	211
-#define EXCSAVE_4	212
-#define EXCSAVE_5	213
-#define EXCSAVE_6	214
-#define EXCSAVE_7	215
-#define CPENABLE	224
-#define INTERRUPT	226
-#define INTENABLE	228
-#define PS		230
-#define EXCCAUSE	232
-#define DEBUGCAUSE	233
-#define CCOUNT		234
-#define PRID		235
-#define ICOUNT		236
-#define ICOUNTLEVEL	237
-#define EXCVADDR	238
-#define CCOMPARE_0	240
-#define CCOMPARE_1	241
-#define MISC_REG_0	244
-#define MISC_REG_1	245
-
-
-/*  Special cases (bases of special register series):  */
-#define IBREAKA		128
-#define DBREAKA		144
-#define DBREAKC		160
-#define EPC		176
-#define EPS		192
-#define EXCSAVE		208
-#define CCOMPARE	240
-
-/*  Special names for read-only and write-only interrupt registers:  */
-#define INTREAD		226
-#define INTSET		226
-#define INTCLEAR	227
-
-#endif /* XTENSA_SPECREG_H */
-
diff --git a/src/platform/amd/acp_6_3/include/arch/xtensa/config/system.h b/src/platform/amd/acp_6_3/include/arch/xtensa/config/system.h
deleted file mode 100644
index 31459310d3d7..000000000000
--- a/src/platform/amd/acp_6_3/include/arch/xtensa/config/system.h
+++ /dev/null
@@ -1,262 +0,0 @@
-/* 
- * xtensa/config/system.h -- HAL definitions that are dependent on SYSTEM configuration
- *
- *  NOTE: The location and contents of this file are highly subject to change.
- *
- *  Source for configuration-independent binaries (which link in a
- *  configuration-specific HAL library) must NEVER include this file.
- *  The HAL itself has historically included this file in some instances,
- *  but this is not appropriate either, because the HAL is meant to be
- *  core-specific but system independent.
- */
-
-/* Customer ID=7490; Build=0xa28f5; Copyright (c) 2000-2010 Tensilica Inc.
-
-   Permission is hereby granted, free of charge, to any person obtaining
-   a copy of this software and associated documentation files (the
-   "Software"), to deal in the Software without restriction, including
-   without limitation the rights to use, copy, modify, merge, publish,
-   distribute, sublicense, and/or sell copies of the Software, and to
-   permit persons to whom the Software is furnished to do so, subject to
-   the following conditions:
-
-   The above copyright notice and this permission notice shall be included
-   in all copies or substantial portions of the Software.
-
-   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
-
-
-#ifndef XTENSA_CONFIG_SYSTEM_H
-#define XTENSA_CONFIG_SYSTEM_H
-
-
-/*----------------------------------------------------------------------
-				CONFIGURED SOFTWARE OPTIONS
-  ----------------------------------------------------------------------*/
-
-#define XSHAL_USE_ABSOLUTE_LITERALS	0	/* (sw-only option, whether software uses absolute literals) */
-#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals.  */
-
-#define XSHAL_ABI			XTHAL_ABI_WINDOWED	/* (sw-only option, selected ABI) */
-/*  The above maps to one of the following constants:  */
-#define XTHAL_ABI_WINDOWED		0
-#define XTHAL_ABI_CALL0			1
-
-#define XSHAL_CLIB			XTHAL_CLIB_XCLIB	/* (sw-only option, selected C library) */
-/*  The above maps to one of the following constants:  */
-#define XTHAL_CLIB_NEWLIB		0
-#define XTHAL_CLIB_UCLIBC		1
-#define XTHAL_CLIB_XCLIB		2
-
-#define XSHAL_USE_FLOATING_POINT	1
-
-#define XSHAL_FLOATING_POINT_ABI        1
-
-/*  SW workarounds enabled for HW errata:  */
-
-/*----------------------------------------------------------------------
-				DEVICE ADDRESSES
-  ----------------------------------------------------------------------*/
-
-/*
- *  Strange place to find these, but the configuration GUI
- *  allows moving these around to account for various core
- *  configurations.  Specific boards (and their BSP software)
- *  will have specific meanings for these components.
- */
-
-/*  I/O Block areas:  */
-#define XSHAL_IOBLOCK_CACHED_VADDR	0x70000000
-#define XSHAL_IOBLOCK_CACHED_PADDR	0x70000000
-#define XSHAL_IOBLOCK_CACHED_SIZE	0x0E000000
-
-#define XSHAL_IOBLOCK_BYPASS_VADDR	0x90000000
-#define XSHAL_IOBLOCK_BYPASS_PADDR	0x90000000
-#define XSHAL_IOBLOCK_BYPASS_SIZE	0x0E000000
-
-/*  System ROM:  */
-#define XSHAL_ROM_VADDR		0x50000000
-#define XSHAL_ROM_PADDR		0x50000000
-#define XSHAL_ROM_SIZE		0x00020000
-/*  Largest available area (free of vectors):  */
-#define XSHAL_ROM_AVAIL_VADDR	0x50000000
-#define XSHAL_ROM_AVAIL_VSIZE	0x00020000
-
-/*  System RAM:  */
-#define XSHAL_RAM_VADDR		0x60000000
-#define XSHAL_RAM_PADDR		0x60000000
-#define XSHAL_RAM_VSIZE		0x1F000000
-#define XSHAL_RAM_PSIZE		0x1F000000
-#define XSHAL_RAM_SIZE		XSHAL_RAM_PSIZE
-/*  Largest available area (free of vectors):  */
-#define XSHAL_RAM_AVAIL_VADDR	0x60000000
-#define XSHAL_RAM_AVAIL_VSIZE	0x1F000000
-
-/*
- *  Shadow system RAM (same device as system RAM, at different address).
- *  (Emulation boards need this for the SONIC Ethernet driver
- *   when data caches are configured for writeback mode.)
- *  NOTE: on full MMU configs, this points to the BYPASS virtual address
- *  of system RAM, ie. is the same as XSHAL_RAM_* except that virtual
- *  addresses are viewed through the BYPASS static map rather than
- *  the CACHED static map.
- */
-#define XSHAL_RAM_BYPASS_VADDR		0x20000000
-#define XSHAL_RAM_BYPASS_PADDR		0x20000000
-#define XSHAL_RAM_BYPASS_PSIZE		0x1F000000
-
-/*  Alternate system RAM (different device than system RAM):  */
-
-/*  Some available location in which to place devices in a simulation (eg. XTMP):  */
-#define XSHAL_SIMIO_CACHED_VADDR	0xC0000000
-#define XSHAL_SIMIO_BYPASS_VADDR	0xC0000000
-#define XSHAL_SIMIO_PADDR		0xC0000000
-#define XSHAL_SIMIO_SIZE		0x20000000
-
-
-/*----------------------------------------------------------------------
- *  For use by reference testbench exit and diagnostic routines.
- */
-#define XSHAL_MAGIC_EXIT		0xc0000000
-#define XSHAL_STL_INFO_LOCATION		0x9ffffffc
-
-/*----------------------------------------------------------------------
- *			DEVICE-ADDRESS DEPENDENT...
- *
- *  Values written to CACHEATTR special register (or its equivalent)
- *  to enable and disable caches in various modes.
- *----------------------------------------------------------------------*/
-
-/*----------------------------------------------------------------------
-			BACKWARD COMPATIBILITY ...
-  ----------------------------------------------------------------------*/
-
-/*
- *  NOTE:  the following two macros are DEPRECATED.  Use the latter
- *  board-specific macros instead, which are specially tuned for the
- *  particular target environments' memory maps.
- */
-#define XSHAL_CACHEATTR_BYPASS		XSHAL_XT2000_CACHEATTR_BYPASS	/* disable caches in bypass mode */
-#define XSHAL_CACHEATTR_DEFAULT		XSHAL_XT2000_CACHEATTR_DEFAULT	/* default setting to enable caches (no writeback!) */
-
-/*----------------------------------------------------------------------
-				GENERIC
-  ----------------------------------------------------------------------*/
-
-/*  For the following, a 512MB region is used if it contains a system (PIF) RAM,
- *  system (PIF) ROM, local memory, or XLMI.  */
-
-/*  These set any unused 512MB region to cache-BYPASS attribute:  */
-#define XSHAL_ALLVALID_CACHEATTR_WRITEBACK	0x42224422	/* enable caches in write-back mode */
-#define XSHAL_ALLVALID_CACHEATTR_WRITEALLOC	0x12221122	/* enable caches in write-allocate mode */
-#define XSHAL_ALLVALID_CACHEATTR_WRITETHRU	0x12221122	/* enable caches in write-through mode */
-#define XSHAL_ALLVALID_CACHEATTR_BYPASS		0x22222222	/* disable caches in bypass mode */
-#define XSHAL_ALLVALID_CACHEATTR_DEFAULT	XSHAL_ALLVALID_CACHEATTR_WRITEBACK	/* default setting to enable caches */
-
-/*  These set any unused 512MB region to ILLEGAL attribute:  */
-#define XSHAL_STRICT_CACHEATTR_WRITEBACK	0x4FFF44FF	/* enable caches in write-back mode */
-#define XSHAL_STRICT_CACHEATTR_WRITEALLOC	0x1FFF11FF	/* enable caches in write-allocate mode */
-#define XSHAL_STRICT_CACHEATTR_WRITETHRU	0x1FFF11FF	/* enable caches in write-through mode */
-#define XSHAL_STRICT_CACHEATTR_BYPASS		0x2FFF22FF	/* disable caches in bypass mode */
-#define XSHAL_STRICT_CACHEATTR_DEFAULT		XSHAL_STRICT_CACHEATTR_WRITEBACK	/* default setting to enable caches */
-
-/*  These set the first 512MB, if unused, to ILLEGAL attribute to help catch
- *  NULL-pointer dereference bugs; all other unused 512MB regions are set
- *  to cache-BYPASS attribute:  */
-#define XSHAL_TRAPNULL_CACHEATTR_WRITEBACK	0x4222442F	/* enable caches in write-back mode */
-#define XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC	0x1222112F	/* enable caches in write-allocate mode */
-#define XSHAL_TRAPNULL_CACHEATTR_WRITETHRU	0x1222112F	/* enable caches in write-through mode */
-#define XSHAL_TRAPNULL_CACHEATTR_BYPASS		0x2222222F	/* disable caches in bypass mode */
-#define XSHAL_TRAPNULL_CACHEATTR_DEFAULT	XSHAL_TRAPNULL_CACHEATTR_WRITEBACK	/* default setting to enable caches */
-
-/*----------------------------------------------------------------------
-			ISS (Instruction Set Simulator) SPECIFIC ...
-  ----------------------------------------------------------------------*/
-
-/*  For now, ISS defaults to the TRAPNULL settings:  */
-#define XSHAL_ISS_CACHEATTR_WRITEBACK	XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
-#define XSHAL_ISS_CACHEATTR_WRITEALLOC	XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC
-#define XSHAL_ISS_CACHEATTR_WRITETHRU	XSHAL_TRAPNULL_CACHEATTR_WRITETHRU
-#define XSHAL_ISS_CACHEATTR_BYPASS	XSHAL_TRAPNULL_CACHEATTR_BYPASS
-#define XSHAL_ISS_CACHEATTR_DEFAULT	XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
-
-#define XSHAL_ISS_PIPE_REGIONS	0
-#define XSHAL_ISS_SDRAM_REGIONS	0
-
-
-/*----------------------------------------------------------------------
-			XT2000 BOARD SPECIFIC ...
-  ----------------------------------------------------------------------*/
-
-/*  For the following, a 512MB region is used if it contains any system RAM,
- *  system ROM, local memory, XLMI, or other XT2000 board device or memory.
- *  Regions containing devices are forced to cache-BYPASS mode regardless
- *  of whether the macro is _WRITEBACK vs. _BYPASS etc.  */
-
-/*  These set any 512MB region unused on the XT2000 to ILLEGAL attribute:  */
-#define XSHAL_XT2000_CACHEATTR_WRITEBACK	0x4FF2442F	/* enable caches in write-back mode */
-#define XSHAL_XT2000_CACHEATTR_WRITEALLOC	0x1FF2112F	/* enable caches in write-allocate mode */
-#define XSHAL_XT2000_CACHEATTR_WRITETHRU	0x1FF2112F	/* enable caches in write-through mode */
-#define XSHAL_XT2000_CACHEATTR_BYPASS		0x2FF2222F	/* disable caches in bypass mode */
-#define XSHAL_XT2000_CACHEATTR_DEFAULT		XSHAL_XT2000_CACHEATTR_WRITEBACK	/* default setting to enable caches */
-
-#define XSHAL_XT2000_PIPE_REGIONS	0x00000000	/* BusInt pipeline regions */
-#define XSHAL_XT2000_SDRAM_REGIONS	0x00000044	/* BusInt SDRAM regions */
-
-
-/*----------------------------------------------------------------------
-				VECTOR INFO AND SIZES
-  ----------------------------------------------------------------------*/
-
-#define XSHAL_VECTORS_PACKED		0	/* UNUSED */
-#define XSHAL_STATIC_VECTOR_SELECT	0
-#define XSHAL_RESET_VECTOR_VADDR	0x7F000000
-#define XSHAL_RESET_VECTOR_PADDR	0x7F000000
-
-/*
- *  Sizes allocated to vectors by the system (memory map) configuration.
- *  These sizes are constrained by core configuration (eg. one vector's
- *  code cannot overflow into another vector) but are dependent on the
- *  system or board (or LSP) memory map configuration.
- *
- *  Whether or not each vector happens to be in a system ROM is also
- *  a system configuration matter, sometimes useful, included here also:
- */
-#define XSHAL_RESET_VECTOR_SIZE	0x00000300
-#define XSHAL_RESET_VECTOR_ISROM	0
-#define XSHAL_USER_VECTOR_SIZE	0x00000038
-#define XSHAL_USER_VECTOR_ISROM	0
-#define XSHAL_PROGRAMEXC_VECTOR_SIZE	XSHAL_USER_VECTOR_SIZE	/* for backward compatibility */
-#define XSHAL_USEREXC_VECTOR_SIZE	XSHAL_USER_VECTOR_SIZE	/* for backward compatibility */
-#define XSHAL_KERNEL_VECTOR_SIZE	0x00000038
-#define XSHAL_KERNEL_VECTOR_ISROM	0
-#define XSHAL_STACKEDEXC_VECTOR_SIZE	XSHAL_KERNEL_VECTOR_SIZE	/* for backward compatibility */
-#define XSHAL_KERNELEXC_VECTOR_SIZE	XSHAL_KERNEL_VECTOR_SIZE	/* for backward compatibility */
-#define XSHAL_DOUBLEEXC_VECTOR_SIZE	0x00000040
-#define XSHAL_DOUBLEEXC_VECTOR_ISROM	0
-#define XSHAL_WINDOW_VECTORS_SIZE	0x00000178
-#define XSHAL_WINDOW_VECTORS_ISROM	0
-#define XSHAL_INTLEVEL2_VECTOR_SIZE	0x00000038
-#define XSHAL_INTLEVEL2_VECTOR_ISROM	0
-#define XSHAL_INTLEVEL3_VECTOR_SIZE	0x00000038
-#define XSHAL_INTLEVEL3_VECTOR_ISROM	0
-#define XSHAL_INTLEVEL4_VECTOR_SIZE	0x00000038
-#define XSHAL_INTLEVEL4_VECTOR_ISROM	0
-#define XSHAL_INTLEVEL5_VECTOR_SIZE	0x00000038
-#define XSHAL_INTLEVEL5_VECTOR_ISROM	0
-#define XSHAL_INTLEVEL6_VECTOR_SIZE	0x00000038
-#define XSHAL_INTLEVEL6_VECTOR_ISROM	0
-#define XSHAL_DEBUG_VECTOR_SIZE		XSHAL_INTLEVEL6_VECTOR_SIZE
-#define XSHAL_DEBUG_VECTOR_ISROM	XSHAL_INTLEVEL6_VECTOR_ISROM
-#define XSHAL_NMI_VECTOR_SIZE	0x00000038
-#define XSHAL_NMI_VECTOR_ISROM	0
-#define XSHAL_INTLEVEL7_VECTOR_SIZE	XSHAL_NMI_VECTOR_SIZE
-
-#endif /*XTENSA_CONFIG_SYSTEM_H*/
-
diff --git a/src/platform/amd/acp_6_3/include/arch/xtensa/config/tie-asm.h b/src/platform/amd/acp_6_3/include/arch/xtensa/config/tie-asm.h
deleted file mode 100644
index ce8f0103809b..000000000000
--- a/src/platform/amd/acp_6_3/include/arch/xtensa/config/tie-asm.h
+++ /dev/null
@@ -1,366 +0,0 @@
-/* 
- * tie-asm.h -- compile-time HAL assembler definitions dependent on CORE & TIE
- *
- *  NOTE:  This header file is not meant to be included directly.
- */
-
-/* This header file contains assembly-language definitions (assembly
-   macros, etc.) for this specific Xtensa processor's TIE extensions
-   and options.  It is customized to this Xtensa processor configuration.
-
-   Customer ID=7490; Build=0xa28f5; Copyright (c) 1999-2022 Cadence Design Systems Inc.
-
-   Permission is hereby granted, free of charge, to any person obtaining
-   a copy of this software and associated documentation files (the
-   "Software"), to deal in the Software without restriction, including
-   without limitation the rights to use, copy, modify, merge, publish,
-   distribute, sublicense, and/or sell copies of the Software, and to
-   permit persons to whom the Software is furnished to do so, subject to
-   the following conditions:
-
-   The above copyright notice and this permission notice shall be included
-   in all copies or substantial portions of the Software.
-
-   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
-
-#ifndef _XTENSA_CORE_TIE_ASM_H
-#define _XTENSA_CORE_TIE_ASM_H
-
-#include <xtensa/coreasm.h>
-
-/*  Selection parameter values for save-area save/restore macros:  */
-/*  Option vs. TIE:  */
-#define XTHAL_SAS_TIE	0x0001	/* custom extension or coprocessor */
-#define XTHAL_SAS_OPT	0x0002	/* optional (and not a coprocessor) */
-#define XTHAL_SAS_ANYOT	0x0003	/* both of the above */
-/*  Whether used automatically by compiler:  */
-#define XTHAL_SAS_NOCC	0x0004	/* not used by compiler w/o special opts/code */
-#define XTHAL_SAS_CC	0x0008	/* used by compiler without special opts/code */
-#define XTHAL_SAS_ANYCC	0x000C	/* both of the above */
-/*  ABI handling across function calls:  */
-#define XTHAL_SAS_CALR	0x0010	/* caller-saved */
-#define XTHAL_SAS_CALE	0x0020	/* callee-saved */
-#define XTHAL_SAS_GLOB	0x0040	/* global across function calls (in thread) */
-#define XTHAL_SAS_ANYABI	0x0070	/* all of the above three */
-/*  Misc  */
-#define XTHAL_SAS_ALL	0xFFFF	/* include all default NCP contents */
-#define XTHAL_SAS3(optie,ccuse,abi)	( ((optie) & XTHAL_SAS_ANYOT)  \
-					| ((ccuse) & XTHAL_SAS_ANYCC)  \
-					| ((abi)   & XTHAL_SAS_ANYABI) )
-
-
-    /*
-      *  Macro to store all non-coprocessor (extra) custom TIE and optional state
-      *  (not including zero-overhead loop registers).
-      *  Required parameters:
-      *      ptr         Save area pointer address register (clobbered)
-      *                  (register must contain a 4 byte aligned address).
-      *      at1..at4    Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
-      *                  registers are clobbered, the remaining are unused).
-      *  Optional parameters:
-      *      continue    If macro invoked as part of a larger store sequence, set to 1
-      *                  if this is not the first in the sequence.  Defaults to 0.
-      *      ofs         Offset from start of larger sequence (from value of first ptr
-      *                  in sequence) at which to store.  Defaults to next available space
-      *                  (or 0 if <continue> is 0).
-      *      select      Select what category(ies) of registers to store, as a bitmask
-      *                  (see XTHAL_SAS_xxx constants).  Defaults to all registers.
-      *      alloc       Select what category(ies) of registers to allocate; if any
-      *                  category is selected here that is not in <select>, space for
-      *                  the corresponding registers is skipped without doing any store.
-      */
-    .macro xchal_ncp_store  ptr at1 at2 at3 at4  continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
-	xchal_sa_start	\continue, \ofs
-	// Optional global registers used by default by the compiler:
-	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
-	xchal_sa_align	\ptr, 0, 1016, 4, 4
-	rur.threadptr	\at1		// threadptr option
-	s32i	\at1, \ptr, .Lxchal_ofs_+0
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
-	.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
-	xchal_sa_align	\ptr, 0, 1016, 4, 4
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
-	.endif
-	// Optional caller-saved registers not used by default by the compiler:
-	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
-	xchal_sa_align	\ptr, 0, 1012, 4, 4
-	rsr.br	\at1		// boolean option
-	s32i	\at1, \ptr, .Lxchal_ofs_+0
-	rsr.scompare1	\at1		// conditional store option
-	s32i	\at1, \ptr, .Lxchal_ofs_+4
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 8
-	.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
-	xchal_sa_align	\ptr, 0, 1012, 4, 4
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 8
-	.endif
-    .endm	// xchal_ncp_store
-
-    /*
-      *  Macro to load all non-coprocessor (extra) custom TIE and optional state
-      *  (not including zero-overhead loop registers).
-      *  Required parameters:
-      *      ptr         Save area pointer address register (clobbered)
-      *                  (register must contain a 4 byte aligned address).
-      *      at1..at4    Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
-      *                  registers are clobbered, the remaining are unused).
-      *  Optional parameters:
-      *      continue    If macro invoked as part of a larger load sequence, set to 1
-      *                  if this is not the first in the sequence.  Defaults to 0.
-      *      ofs         Offset from start of larger sequence (from value of first ptr
-      *                  in sequence) at which to load.  Defaults to next available space
-      *                  (or 0 if <continue> is 0).
-      *      select      Select what category(ies) of registers to load, as a bitmask
-      *                  (see XTHAL_SAS_xxx constants).  Defaults to all registers.
-      *      alloc       Select what category(ies) of registers to allocate; if any
-      *                  category is selected here that is not in <select>, space for
-      *                  the corresponding registers is skipped without doing any load.
-      */
-    .macro xchal_ncp_load  ptr at1 at2 at3 at4  continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
-	xchal_sa_start	\continue, \ofs
-	// Optional global registers used by default by the compiler:
-	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
-	xchal_sa_align	\ptr, 0, 1016, 4, 4
-	l32i	\at1, \ptr, .Lxchal_ofs_+0
-	wur.threadptr	\at1		// threadptr option
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
-	.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
-	xchal_sa_align	\ptr, 0, 1016, 4, 4
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
-	.endif
-	// Optional caller-saved registers not used by default by the compiler:
-	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
-	xchal_sa_align	\ptr, 0, 1012, 4, 4
-	l32i	\at1, \ptr, .Lxchal_ofs_+0
-	wsr.br	\at1		// boolean option
-	l32i	\at1, \ptr, .Lxchal_ofs_+4
-	wsr.scompare1	\at1		// conditional store option
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 8
-	.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
-	xchal_sa_align	\ptr, 0, 1012, 4, 4
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 8
-	.endif
-    .endm	// xchal_ncp_load
-
-
-#define XCHAL_NCP_NUM_ATMPS	1
-
-    /* 
-     *  Macro to store the state of TIE coprocessor AudioEngineLX.
-     *  Required parameters:
-     *      ptr         Save area pointer address register (clobbered)
-     *                  (register must contain a 16 byte aligned address).
-     *      at1..at4    Four temporary address registers (first XCHAL_CP1_NUM_ATMPS
-     *                  registers are clobbered, the remaining are unused).
-     *  Optional parameters are the same as for xchal_ncp_store.
-     */
-#define xchal_cp_AudioEngineLX_store	xchal_cp1_store
-    .macro	xchal_cp1_store  ptr at1 at2 at3 at4  continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
-	xchal_sa_start \continue, \ofs
-	// Custom caller-saved registers not used by default by the compiler:
-	.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
-	xchal_sa_align	\ptr, 0, 0, 16, 16
-	ae_s64.i	aed0, \ptr, .Lxchal_ofs_+56
-	addi.a	\ptr, \ptr, 64
-	ae_s64.i	aed1, \ptr, .Lxchal_ofs_+0
-	ae_s64.i	aed2, \ptr, .Lxchal_ofs_+8
-	ae_s64.i	aed3, \ptr, .Lxchal_ofs_+16
-	ae_s64.i	aed4, \ptr, .Lxchal_ofs_+24
-	ae_s64.i	aed5, \ptr, .Lxchal_ofs_+32
-	ae_s64.i	aed6, \ptr, .Lxchal_ofs_+40
-	ae_s64.i	aed7, \ptr, .Lxchal_ofs_+48
-	ae_s64.i	aed8, \ptr, .Lxchal_ofs_+56
-	addi.a	\ptr, \ptr, 64
-	ae_s64.i	aed9, \ptr, .Lxchal_ofs_+0
-	ae_s64.i	aed10, \ptr, .Lxchal_ofs_+8
-	ae_s64.i	aed11, \ptr, .Lxchal_ofs_+16
-	ae_s64.i	aed12, \ptr, .Lxchal_ofs_+24
-	ae_s64.i	aed13, \ptr, .Lxchal_ofs_+32
-	ae_s64.i	aed14, \ptr, .Lxchal_ofs_+40
-	ae_s64.i	aed15, \ptr, .Lxchal_ofs_+48
-	ae_s64.i	aed16, \ptr, .Lxchal_ofs_+56
-	addi.a	\ptr, \ptr, 64
-	ae_s64.i	aed17, \ptr, .Lxchal_ofs_+0
-	ae_s64.i	aed18, \ptr, .Lxchal_ofs_+8
-	ae_s64.i	aed19, \ptr, .Lxchal_ofs_+16
-	ae_s64.i	aed20, \ptr, .Lxchal_ofs_+24
-	ae_s64.i	aed21, \ptr, .Lxchal_ofs_+32
-	ae_s64.i	aed22, \ptr, .Lxchal_ofs_+40
-	ae_s64.i	aed23, \ptr, .Lxchal_ofs_+48
-	ae_s64.i	aed24, \ptr, .Lxchal_ofs_+56
-	addi.a	\ptr, \ptr, 64
-	ae_s64.i	aed25, \ptr, .Lxchal_ofs_+0
-	ae_s64.i	aed26, \ptr, .Lxchal_ofs_+8
-	ae_s64.i	aed27, \ptr, .Lxchal_ofs_+16
-	ae_s64.i	aed28, \ptr, .Lxchal_ofs_+24
-	ae_s64.i	aed29, \ptr, .Lxchal_ofs_+32
-	ae_s64.i	aed30, \ptr, .Lxchal_ofs_+40
-	ae_s64.i	aed31, \ptr, .Lxchal_ofs_+48
-	ae_movae	\at1, aep0
-	s8i	\at1, \ptr, .Lxchal_ofs_+56
-	ae_movae	\at1, aep1
-	s8i	\at1, \ptr, .Lxchal_ofs_+57
-	ae_movae	\at1, aep2
-	s8i	\at1, \ptr, .Lxchal_ofs_+58
-	ae_movae	\at1, aep3
-	s8i	\at1, \ptr, .Lxchal_ofs_+59
-	addi.a	\ptr, \ptr, 64
-	ae_salign128.i	u0, \ptr, .Lxchal_ofs_+0
-	ae_salign128.i	u1, \ptr, .Lxchal_ofs_+16
-	ae_salign128.i	u2, \ptr, .Lxchal_ofs_+32
-	ae_salign128.i	u3, \ptr, .Lxchal_ofs_+48
-	addi.a	\ptr, \ptr, -320
-	ae_movdrzbvc	aed0		// ureg AE_ZBIASV8C
-	ae_s64.i	aed0, \ptr, .Lxchal_ofs_+0 + 0
-	ae_movvfcrfsr	aed0		// ureg FCR_FSR
-	ae_s64.i	aed0, \ptr, .Lxchal_ofs_+8 + 0
-	rur.ae_ovf_sar	\at1		// ureg 240
-	s32i	\at1, \ptr, .Lxchal_ofs_+16
-	rur.ae_bithead	\at1		// ureg 241
-	s32i	\at1, \ptr, .Lxchal_ofs_+20
-	rur.ae_ts_fts_bu_bp	\at1		// ureg 242
-	s32i	\at1, \ptr, .Lxchal_ofs_+24
-	rur.ae_cw_sd_no	\at1		// ureg 243
-	s32i	\at1, \ptr, .Lxchal_ofs_+28
-	rur.ae_cbegin0	\at1		// ureg 246
-	s32i	\at1, \ptr, .Lxchal_ofs_+32
-	rur.ae_cend0	\at1		// ureg 247
-	s32i	\at1, \ptr, .Lxchal_ofs_+36
-	rur.ae_cbegin1	\at1		// ureg 248
-	s32i	\at1, \ptr, .Lxchal_ofs_+40
-	rur.ae_cend1	\at1		// ureg 249
-	s32i	\at1, \ptr, .Lxchal_ofs_+44
-	rur.ae_cbegin2	\at1		// ureg 250
-	s32i	\at1, \ptr, .Lxchal_ofs_+48
-	rur.ae_cend2	\at1		// ureg 251
-	s32i	\at1, \ptr, .Lxchal_ofs_+52
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 384
-	.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
-	xchal_sa_align	\ptr, 0, 0, 16, 16
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 384
-	.endif
-    .endm	// xchal_cp1_store
-
-    /* 
-     *  Macro to load the state of TIE coprocessor AudioEngineLX.
-     *  Required parameters:
-     *      ptr         Save area pointer address register (clobbered)
-     *                  (register must contain a 16 byte aligned address).
-     *      at1..at4    Four temporary address registers (first XCHAL_CP1_NUM_ATMPS
-     *                  registers are clobbered, the remaining are unused).
-     *  Optional parameters are the same as for xchal_ncp_load.
-     */
-#define xchal_cp_AudioEngineLX_load	xchal_cp1_load
-    .macro	xchal_cp1_load  ptr at1 at2 at3 at4  continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
-	xchal_sa_start \continue, \ofs
-	// Custom caller-saved registers not used by default by the compiler:
-	.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
-	xchal_sa_align	\ptr, 0, 0, 16, 16
-	ae_l64.i	aed0, \ptr, .Lxchal_ofs_+0 + 0		// ureg AE_ZBIASV8C
-	ae_movzbvcdr	aed0
-	ae_l64.i	aed0, \ptr, .Lxchal_ofs_+8 + 0		// ureg FCR_FSR
-	ae_movfcrfsrv	aed0
-	l32i	\at1, \ptr, .Lxchal_ofs_+16
-	wur.ae_ovf_sar	\at1		// ureg 240
-	l32i	\at1, \ptr, .Lxchal_ofs_+20
-	wur.ae_bithead	\at1		// ureg 241
-	l32i	\at1, \ptr, .Lxchal_ofs_+24
-	wur.ae_ts_fts_bu_bp	\at1		// ureg 242
-	l32i	\at1, \ptr, .Lxchal_ofs_+28
-	wur.ae_cw_sd_no	\at1		// ureg 243
-	l32i	\at1, \ptr, .Lxchal_ofs_+32
-	wur.ae_cbegin0	\at1		// ureg 246
-	l32i	\at1, \ptr, .Lxchal_ofs_+36
-	wur.ae_cend0	\at1		// ureg 247
-	l32i	\at1, \ptr, .Lxchal_ofs_+40
-	wur.ae_cbegin1	\at1		// ureg 248
-	l32i	\at1, \ptr, .Lxchal_ofs_+44
-	wur.ae_cend1	\at1		// ureg 249
-	l32i	\at1, \ptr, .Lxchal_ofs_+48
-	wur.ae_cbegin2	\at1		// ureg 250
-	l32i	\at1, \ptr, .Lxchal_ofs_+52
-	wur.ae_cend2	\at1		// ureg 251
-	ae_l64.i	aed0, \ptr, .Lxchal_ofs_+56
-	addi.a	\ptr, \ptr, 64
-	ae_l64.i	aed1, \ptr, .Lxchal_ofs_+0
-	ae_l64.i	aed2, \ptr, .Lxchal_ofs_+8
-	ae_l64.i	aed3, \ptr, .Lxchal_ofs_+16
-	ae_l64.i	aed4, \ptr, .Lxchal_ofs_+24
-	ae_l64.i	aed5, \ptr, .Lxchal_ofs_+32
-	ae_l64.i	aed6, \ptr, .Lxchal_ofs_+40
-	ae_l64.i	aed7, \ptr, .Lxchal_ofs_+48
-	ae_l64.i	aed8, \ptr, .Lxchal_ofs_+56
-	addi.a	\ptr, \ptr, 64
-	ae_l64.i	aed9, \ptr, .Lxchal_ofs_+0
-	ae_l64.i	aed10, \ptr, .Lxchal_ofs_+8
-	ae_l64.i	aed11, \ptr, .Lxchal_ofs_+16
-	ae_l64.i	aed12, \ptr, .Lxchal_ofs_+24
-	ae_l64.i	aed13, \ptr, .Lxchal_ofs_+32
-	ae_l64.i	aed14, \ptr, .Lxchal_ofs_+40
-	ae_l64.i	aed15, \ptr, .Lxchal_ofs_+48
-	ae_l64.i	aed16, \ptr, .Lxchal_ofs_+56
-	addi.a	\ptr, \ptr, 64
-	ae_l64.i	aed17, \ptr, .Lxchal_ofs_+0
-	ae_l64.i	aed18, \ptr, .Lxchal_ofs_+8
-	ae_l64.i	aed19, \ptr, .Lxchal_ofs_+16
-	ae_l64.i	aed20, \ptr, .Lxchal_ofs_+24
-	ae_l64.i	aed21, \ptr, .Lxchal_ofs_+32
-	ae_l64.i	aed22, \ptr, .Lxchal_ofs_+40
-	ae_l64.i	aed23, \ptr, .Lxchal_ofs_+48
-	ae_l64.i	aed24, \ptr, .Lxchal_ofs_+56
-	addi.a	\ptr, \ptr, 64
-	ae_l64.i	aed25, \ptr, .Lxchal_ofs_+0
-	ae_l64.i	aed26, \ptr, .Lxchal_ofs_+8
-	ae_l64.i	aed27, \ptr, .Lxchal_ofs_+16
-	ae_l64.i	aed28, \ptr, .Lxchal_ofs_+24
-	ae_l64.i	aed29, \ptr, .Lxchal_ofs_+32
-	ae_l64.i	aed30, \ptr, .Lxchal_ofs_+40
-	ae_l64.i	aed31, \ptr, .Lxchal_ofs_+48
-	addi.a	\ptr, \ptr, 56
-	l8ui	\at1, \ptr, .Lxchal_ofs_+0
-	ae_movea	aep0, \at1
-	l8ui	\at1, \ptr, .Lxchal_ofs_+1
-	ae_movea	aep1, \at1
-	l8ui	\at1, \ptr, .Lxchal_ofs_+2
-	ae_movea	aep2, \at1
-	l8ui	\at1, \ptr, .Lxchal_ofs_+3
-	ae_movea	aep3, \at1
-	addi.a	\ptr, \ptr, 8
-	ae_lalign128.i	u0, \ptr, .Lxchal_ofs_+0
-	ae_lalign128.i	u1, \ptr, .Lxchal_ofs_+16
-	ae_lalign128.i	u2, \ptr, .Lxchal_ofs_+32
-	ae_lalign128.i	u3, \ptr, .Lxchal_ofs_+48
-	.set	.Lxchal_pofs_, .Lxchal_pofs_ + 320
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 64
-	.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
-	xchal_sa_align	\ptr, 0, 0, 16, 16
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 384
-	.endif
-    .endm	// xchal_cp1_load
-
-#define XCHAL_CP1_NUM_ATMPS	1
-#define XCHAL_SA_NUM_ATMPS	1
-
-	/*  Empty macros for unconfigured coprocessors:  */
-	.macro xchal_cp0_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp0_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp2_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp2_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp3_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp3_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp4_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp4_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp5_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp5_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp6_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp6_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp7_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp7_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-
-#endif /*_XTENSA_CORE_TIE_ASM_H*/
-
diff --git a/src/platform/amd/acp_6_3/include/arch/xtensa/config/tie.h b/src/platform/amd/acp_6_3/include/arch/xtensa/config/tie.h
deleted file mode 100644
index 22fe621c7127..000000000000
--- a/src/platform/amd/acp_6_3/include/arch/xtensa/config/tie.h
+++ /dev/null
@@ -1,211 +0,0 @@
-/* 
- * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
- *
- *  NOTE:  This header file is not meant to be included directly.
- */
-
-/* This header file describes this specific Xtensa processor's TIE extensions
-   that extend basic Xtensa core functionality.  It is customized to this
-   Xtensa processor configuration.
-
-   Customer ID=7490; Build=0xa28f5; Copyright (c) 1999-2022 Cadence Design Systems Inc.
-
-   Permission is hereby granted, free of charge, to any person obtaining
-   a copy of this software and associated documentation files (the
-   "Software"), to deal in the Software without restriction, including
-   without limitation the rights to use, copy, modify, merge, publish,
-   distribute, sublicense, and/or sell copies of the Software, and to
-   permit persons to whom the Software is furnished to do so, subject to
-   the following conditions:
-
-   The above copyright notice and this permission notice shall be included
-   in all copies or substantial portions of the Software.
-
-   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
-
-#ifndef XTENSA_CORE_TIE_H
-#define XTENSA_CORE_TIE_H
-
-/* parasoft-begin-suppress ALL "This file not MISRA checked." */
-
-#define XCHAL_CP_NUM			1	/* number of coprocessors */
-#define XCHAL_CP_MAX			2	/* max CP ID + 1 (0 if none) */
-#define XCHAL_CP_MASK			0x02	/* bitmask of all CPs by ID */
-#define XCHAL_CP_PORT_MASK		0x00	/* bitmask of only port CPs */
-
-/*  Basic parameters of each coprocessor:  */
-#define XCHAL_CP1_NAME			"AudioEngineLX"
-#define XCHAL_CP1_IDENT			AudioEngineLX
-#define XCHAL_CP1_SA_SIZE		384	/* size of state save area */
-#define XCHAL_CP1_SA_ALIGN		16	/* min alignment of save area */
-#define XCHAL_CP_ID_AUDIOENGINELX   	1	/* coprocessor ID (0..7) */
-
-/*  Filler info for unassigned coprocessors, to simplify arrays etc:  */
-#define XCHAL_CP0_SA_SIZE		0
-#define XCHAL_CP0_SA_ALIGN		1
-#define XCHAL_CP2_SA_SIZE		0
-#define XCHAL_CP2_SA_ALIGN		1
-#define XCHAL_CP3_SA_SIZE		0
-#define XCHAL_CP3_SA_ALIGN		1
-#define XCHAL_CP4_SA_SIZE		0
-#define XCHAL_CP4_SA_ALIGN		1
-#define XCHAL_CP5_SA_SIZE		0
-#define XCHAL_CP5_SA_ALIGN		1
-#define XCHAL_CP6_SA_SIZE		0
-#define XCHAL_CP6_SA_ALIGN		1
-#define XCHAL_CP7_SA_SIZE		0
-#define XCHAL_CP7_SA_ALIGN		1
-
-/*  Save area for non-coprocessor optional and custom (TIE) state:  */
-#define XCHAL_NCP_SA_SIZE		12
-#define XCHAL_NCP_SA_ALIGN		4
-
-/*  Total save area for optional and custom state (NCP + CPn):  */
-#define XCHAL_TOTAL_SA_SIZE		400	/* with 16-byte align padding */
-#define XCHAL_TOTAL_SA_ALIGN		16	/* actual minimum alignment */
-
-/*
- * Detailed contents of save areas.
- * NOTE:  caller must define the XCHAL_SA_REG macro (not defined here)
- * before expanding the XCHAL_xxx_SA_LIST() macros.
- *
- * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
- *		dbnum,base,regnum,bitsz,gapsz,reset,x...)
- *
- *	s = passed from XCHAL_*_LIST(s), eg. to select how to expand
- *	ccused = set if used by compiler without special options or code
- *	abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
- *	kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
- *	opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg)
- *	name = lowercase reg name (no quotes)
- *	galign = group byte alignment (power of 2) (galign >= align)
- *	align = register byte alignment (power of 2)
- *	asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz)
- *	  (not including any pad bytes required to galign this or next reg)
- *	dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>)
- *	base = reg shortname w/o index (or sr=special, ur=TIE user reg)
- *	regnum = reg index in regfile, or special/TIE-user reg number
- *	bitsz = number of significant bits (regfile width, or ur/sr mask bits)
- *	gapsz = intervening bits, if bitsz bits not stored contiguously
- *	(padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize)
- *	reset = register reset value (or 0 if undefined at reset)
- *	x = reserved for future use (0 until then)
- *
- *  To filter out certain registers, e.g. to expand only the non-global
- *  registers used by the compiler, you can do something like this:
- *
- *  #define XCHAL_SA_REG(s,ccused,p...)	SELCC##ccused(p)
- *  #define SELCC0(p...)
- *  #define SELCC1(abikind,p...)	SELAK##abikind(p)
- *  #define SELAK0(p...)		REG(p)
- *  #define SELAK1(p...)		REG(p)
- *  #define SELAK2(p...)
- *  #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \
- *		...what you want to expand...
- */
-
-#define XCHAL_NCP_SA_NUM	3
-#define XCHAL_NCP_SA_LIST(s)	\
- XCHAL_SA_REG(s,1,2,1,1,      threadptr, 4, 4, 4,0x03E7,  ur,231, 32,0,0,0) \
- XCHAL_SA_REG(s,0,0,0,1,             br, 4, 4, 4,0x0204,  sr,4  , 16,0,0,0) \
- XCHAL_SA_REG(s,0,0,0,1,      scompare1, 4, 4, 4,0x020C,  sr,12 , 32,0,0,0)
-
-#define XCHAL_CP0_SA_NUM	0
-#define XCHAL_CP0_SA_LIST(s)	/* empty */
-
-#define XCHAL_CP1_SA_NUM	52
-#define XCHAL_CP1_SA_LIST(s)	\
- XCHAL_SA_REG(s,0,0,1,0,    ae_zbiasv8c,16, 8, 8,0x1029,  ur,-1 , 16,0,0,0) \
- XCHAL_SA_REG(s,0,0,1,0,        fcr_fsr, 8, 8, 8,0x102A,  ur,-1 ,  7,0,0,0) \
- XCHAL_SA_REG(s,0,0,1,0,     ae_ovf_sar, 4, 4, 4,0x03F0,  ur,240, 15,0,0,0) \
- XCHAL_SA_REG(s,0,0,1,0,     ae_bithead, 4, 4, 4,0x03F1,  ur,241, 32,0,0,0) \
- XCHAL_SA_REG(s,0,0,1,0,ae_ts_fts_bu_bp, 4, 4, 4,0x03F2,  ur,242, 16,0,0,0) \
- XCHAL_SA_REG(s,0,0,1,0,    ae_cw_sd_no, 4, 4, 4,0x03F3,  ur,243, 29,0,0,0) \
- XCHAL_SA_REG(s,0,0,1,0,     ae_cbegin0, 4, 4, 4,0x03F6,  ur,246, 32,0,0,0) \
- XCHAL_SA_REG(s,0,0,1,0,       ae_cend0, 4, 4, 4,0x03F7,  ur,247, 32,0,0,0) \
- XCHAL_SA_REG(s,0,0,1,0,     ae_cbegin1, 4, 4, 4,0x03F8,  ur,248, 32,0,0,0) \
- XCHAL_SA_REG(s,0,0,1,0,       ae_cend1, 4, 4, 4,0x03F9,  ur,249, 32,0,0,0) \
- XCHAL_SA_REG(s,0,0,1,0,     ae_cbegin2, 4, 4, 4,0x03FA,  ur,250, 32,0,0,0) \
- XCHAL_SA_REG(s,0,0,1,0,       ae_cend2, 4, 4, 4,0x03FB,  ur,251, 32,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aed0, 8, 8, 8,0x1000, aed,0  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aed1, 8, 8, 8,0x1001, aed,1  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aed2, 8, 8, 8,0x1002, aed,2  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aed3, 8, 8, 8,0x1003, aed,3  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aed4, 8, 8, 8,0x1004, aed,4  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aed5, 8, 8, 8,0x1005, aed,5  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aed6, 8, 8, 8,0x1006, aed,6  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aed7, 8, 8, 8,0x1007, aed,7  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aed8, 8, 8, 8,0x1008, aed,8  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aed9, 8, 8, 8,0x1009, aed,9  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed10, 8, 8, 8,0x100A, aed,10 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed11, 8, 8, 8,0x100B, aed,11 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed12, 8, 8, 8,0x100C, aed,12 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed13, 8, 8, 8,0x100D, aed,13 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed14, 8, 8, 8,0x100E, aed,14 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed15, 8, 8, 8,0x100F, aed,15 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed16, 8, 8, 8,0x1010, aed,16 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed17, 8, 8, 8,0x1011, aed,17 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed18, 8, 8, 8,0x1012, aed,18 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed19, 8, 8, 8,0x1013, aed,19 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed20, 8, 8, 8,0x1014, aed,20 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed21, 8, 8, 8,0x1015, aed,21 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed22, 8, 8, 8,0x1016, aed,22 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed23, 8, 8, 8,0x1017, aed,23 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed24, 8, 8, 8,0x1018, aed,24 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed25, 8, 8, 8,0x1019, aed,25 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed26, 8, 8, 8,0x101A, aed,26 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed27, 8, 8, 8,0x101B, aed,27 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed28, 8, 8, 8,0x101C, aed,28 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed29, 8, 8, 8,0x101D, aed,29 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed30, 8, 8, 8,0x101E, aed,30 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed31, 8, 8, 8,0x101F, aed,31 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aep0, 1, 1, 1,0x1024, aep,0  ,  8,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aep1, 1, 1, 1,0x1025, aep,1  ,  8,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aep2, 1, 1, 1,0x1026, aep,2  ,  8,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aep3, 1, 1, 1,0x1027, aep,3  ,  8,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,             u0,16,16,16,0x1020,   u,0  ,128,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,             u1,16,16,16,0x1021,   u,1  ,128,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,             u2,16,16,16,0x1022,   u,2  ,128,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,             u3,16,16,16,0x1023,   u,3  ,128,0,0,0)
-
-#define XCHAL_CP2_SA_NUM	0
-#define XCHAL_CP2_SA_LIST(s)	/* empty */
-
-#define XCHAL_CP3_SA_NUM	0
-#define XCHAL_CP3_SA_LIST(s)	/* empty */
-
-#define XCHAL_CP4_SA_NUM	0
-#define XCHAL_CP4_SA_LIST(s)	/* empty */
-
-#define XCHAL_CP5_SA_NUM	0
-#define XCHAL_CP5_SA_LIST(s)	/* empty */
-
-#define XCHAL_CP6_SA_NUM	0
-#define XCHAL_CP6_SA_LIST(s)	/* empty */
-
-#define XCHAL_CP7_SA_NUM	0
-#define XCHAL_CP7_SA_LIST(s)	/* empty */
-
-/* Byte length of instruction from its first nibble (op0 field), per FLIX.  */
-#define XCHAL_OP0_FORMAT_LENGTHS	3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,16
-/* Byte length of instruction from its first byte, per FLIX.  */
-#define XCHAL_BYTE0_FORMAT_LENGTHS	\
-	3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,16, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,16,\
-	3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,16, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,16,\
-	3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,16, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,16,\
-	3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,16, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,16,\
-	3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,16, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,16,\
-	3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,16, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,16,\
-	3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,16, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,16,\
-	3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,16, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,16
-
-/* parasoft-end-suppress ALL "This file not MISRA checked." */
-
-#endif /* XTENSA_CORE_TIE_H */
-
diff --git a/src/platform/amd/acp_6_3/include/arch/xtensa/tie/xt_datacache.h b/src/platform/amd/acp_6_3/include/arch/xtensa/tie/xt_datacache.h
deleted file mode 100644
index 8e83064e2923..000000000000
--- a/src/platform/amd/acp_6_3/include/arch/xtensa/tie/xt_datacache.h
+++ /dev/null
@@ -1,132 +0,0 @@
-// Customer ID=12153; Build=0x878bf; Copyright (c) 2017 Cadence Design Systems, Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-/* Definitions for the xt_datacache TIE package */
-
-/* Do not modify. This is automatically generated.*/
-
-#ifndef _XTENSA_xt_datacache_HEADER
-#define _XTENSA_xt_datacache_HEADER
-
-/* parasoft-begin-suppress ALL "This file not MISRA checked." */
-
-#ifdef __XTENSA__
-#ifdef __XCC__
-
-#ifndef _ASMLANGUAGE
-#ifndef _NOCLANGUAGE
-#ifndef __ASSEMBLER__
-
-#include <xtensa/tie/xt_core.h>
-
-/*
- * The following prototypes describe intrinsic functions
- * corresponding to TIE instructions.  Some TIE instructions
- * may produce multiple results (designated as "out" operands
- * in the iclass section) or may have operands used as both
- * inputs and outputs (designated as "inout").  However, the C
- * and C++ languages do not provide syntax that can express
- * the in/out/inout constraints of TIE intrinsics.
- * Nevertheless, the compiler understands these constraints
- * and will check that the intrinsic functions are used
- * correctly.  To improve the readability of these prototypes,
- * the "out" and "inout" parameters are marked accordingly
- * with comments.
- */
-
-extern void _TIE_xt_datacache_DHI(const int * s, immediate i);
-extern void _TIE_xt_datacache_DHI_B(const int * s, int i);
-extern void _TIE_xt_datacache_DHU(const int * s, immediate i);
-extern void _TIE_xt_datacache_DHWB(const int * s, immediate i);
-extern void _TIE_xt_datacache_DHWBI(const int * s, immediate i);
-extern void _TIE_xt_datacache_DHWBI_B(const int * s, int i);
-extern void _TIE_xt_datacache_DHWB_B(const int * s, int i);
-extern void _TIE_xt_datacache_DII(const int * s, immediate i);
-extern void _TIE_xt_datacache_DIU(const int * s, immediate i);
-extern void _TIE_xt_datacache_DIWB(const int * s, immediate i);
-extern void _TIE_xt_datacache_DIWBI(const int * s, immediate i);
-extern void _TIE_xt_datacache_DIWBUI_P(const int * s /*inout*/);
-extern void _TIE_xt_datacache_DPFL(const int * s, immediate i);
-extern void _TIE_xt_datacache_DPFM_B(const int * s, int i);
-extern void _TIE_xt_datacache_DPFM_BF(const int * s, int i);
-extern void _TIE_xt_datacache_DPFR(const int * s, immediate i);
-extern void _TIE_xt_datacache_DPFRO(const int * s, immediate i);
-extern void _TIE_xt_datacache_DPFR_B(const int * s, int i);
-extern void _TIE_xt_datacache_DPFR_BF(const int * s, int i);
-extern void _TIE_xt_datacache_DPFW(const int * s, immediate i);
-extern void _TIE_xt_datacache_DPFWO(const int * s, immediate i);
-extern void _TIE_xt_datacache_DPFW_B(const int * s, int i);
-extern void _TIE_xt_datacache_DPFW_BF(const int * s, int i);
-extern int _TIE_xt_datacache_LDCT(const int * s);
-extern int _TIE_xt_datacache_LDCW(const int * s);
-extern void _TIE_xt_datacache_PFEND_A(void);
-extern void _TIE_xt_datacache_PFEND_O(void);
-extern void _TIE_xt_datacache_PFNXT_F(void);
-extern void _TIE_xt_datacache_PFWAIT_A(void);
-extern void _TIE_xt_datacache_PFWAIT_R(void);
-extern void _TIE_xt_datacache_SDCT(int t, int * s);
-extern void _TIE_xt_datacache_SDCW(int t, int * s);
-
-#endif /*__ASSEMBLER__*/
-#endif /*_NOCLANGUAGE*/
-#endif /*_ASMLANGUAGE*/
-
-#define XT_DHI _TIE_xt_datacache_DHI
-#define XT_DHI_B _TIE_xt_datacache_DHI_B
-#define XT_DHU _TIE_xt_datacache_DHU
-#define XT_DHWB _TIE_xt_datacache_DHWB
-#define XT_DHWBI _TIE_xt_datacache_DHWBI
-#define XT_DHWBI_B _TIE_xt_datacache_DHWBI_B
-#define XT_DHWB_B _TIE_xt_datacache_DHWB_B
-#define XT_DII _TIE_xt_datacache_DII
-#define XT_DIU _TIE_xt_datacache_DIU
-#define XT_DIWB _TIE_xt_datacache_DIWB
-#define XT_DIWBI _TIE_xt_datacache_DIWBI
-#define XT_DIWBUI_P _TIE_xt_datacache_DIWBUI_P
-#define XT_DPFL _TIE_xt_datacache_DPFL
-#define XT_DPFM_B _TIE_xt_datacache_DPFM_B
-#define XT_DPFM_BF _TIE_xt_datacache_DPFM_BF
-#define XT_DPFR _TIE_xt_datacache_DPFR
-#define XT_DPFRO _TIE_xt_datacache_DPFRO
-#define XT_DPFR_B _TIE_xt_datacache_DPFR_B
-#define XT_DPFR_BF _TIE_xt_datacache_DPFR_BF
-#define XT_DPFW _TIE_xt_datacache_DPFW
-#define XT_DPFWO _TIE_xt_datacache_DPFWO
-#define XT_DPFW_B _TIE_xt_datacache_DPFW_B
-#define XT_DPFW_BF _TIE_xt_datacache_DPFW_BF
-#define XT_LDCT _TIE_xt_datacache_LDCT
-#define XT_LDCW _TIE_xt_datacache_LDCW
-#define XT_PFEND_A _TIE_xt_datacache_PFEND_A
-#define XT_PFEND_O _TIE_xt_datacache_PFEND_O
-#define XT_PFNXT_F _TIE_xt_datacache_PFNXT_F
-#define XT_PFWAIT_A _TIE_xt_datacache_PFWAIT_A
-#define XT_PFWAIT_R _TIE_xt_datacache_PFWAIT_R
-#define XT_SDCT _TIE_xt_datacache_SDCT
-#define XT_SDCW _TIE_xt_datacache_SDCW
-
-#endif /* __XCC__ */
-
-#endif /* __XTENSA__ */
-
-
-/* parasoft-end-suppress ALL "This file not MISRA checked." */
-
-#endif /* !_XTENSA_xt_datacache_HEADER */
diff --git a/src/platform/amd/acp_6_3/include/platform/chip_offset_byte.h b/src/platform/amd/acp_6_3/include/platform/chip_offset_byte.h
deleted file mode 100644
index ac60c3d6cc1c..000000000000
--- a/src/platform/amd/acp_6_3/include/platform/chip_offset_byte.h
+++ /dev/null
@@ -1,230 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- *
- * Copyright(c) 2023 AMD.All rights reserved.
- *
- * Author:	Basavaraj Hiregoudar <basavaraj.hiregoudar@amd.com>
- *		    SaiSurya, Ch <saisurya.chakkaveeravenkatanaga@amd.com>
- */
-
-#ifndef _ACP_6_3_OFFSET_HEADER
-#define _ACP_6_3_OFFSET_HEADER
-
-#define PU_REGISTER_BASE        (0x9FD00000 - 0x01240000)
-#define PU_SCRATCH_REG_BASE	    (0x9FF00000 - 0x01250000)
-
-/* Registers from ACP_DMA block */
-#define ACP_DMA_CNTL_0			0x1240000
-#define ACP_DMA_DSCR_STRT_IDX_0		0x1240020
-#define ACP_DMA_DSCR_CNT_0		0x1240040
-#define ACP_DMA_PRIO_0			0x1240060
-#define ACP_DMA_DESC_BASE_ADDR		0x12400E0
-#define ACP_DMA_DESC_MAX_NUM_DSCR	0x12400E4
-#define ACP_DMA_CH_STS			0x12400E8
-
-/* Registers from ACP_MISC block */
-#define ACP_CLKMUX_SEL			0x124102C
-#define ACP_I2S_196MHZ_CLK_SEL  0x124105C
-#define ACP_DSP0_INTR_CNTL		0x1241800
-#define ACP_DSP0_INTR_STAT		0x1241804
-#define ACP_DSP_SW_INTR_CNTL		0x1241808
-#define ACP_DSP_SW_INTR_STAT		0x124180C
-#define ACP_SW_INTR_TRIG		0x1241810
-#define DSP_INTERRUPT_ROUTING_CTRL_0	0x1241814
-#define DSP_INTERRUPT_ROUTING_CTRL_1	0x1241818
-#define ACP_FUTURE_REG_ACLK_0		0x1241854
-#define ACP_AXI2DAGB_SEM_0		0x1241874
-#define ACP_DSP0_INTR_CNTL1		0x1241920
-#define ACP_DSP0_INTR_STAT1		0x1241924
-#define ACP_SRBM_CLIENT_BASE_ADDR	0x12419EC
-#define ACP_SRBM_CLIENT_RDDATA		0x12419F0
-#define ACP_SRBM_CYCLE_STS		0x12419F4
-#define ACP_SRBM_CLIENT_CONFIG		0x12419F8
-
-/* Registers from ACP_P1_MISC block */
-#define ACP_EXTERNAL_INTR_ENB		0x1241A00
-
-/* Registers from ACP_AUDIO_BUFFERS block */
-#define ACP_AUDIO_RX_RINGBUFADDR                      0x1242000
-#define ACP_AUDIO_RX_RINGBUFSIZE                      0x1242004
-#define ACP_AUDIO_RX_LINKPOSITIONCNTR                 0x1242008
-#define ACP_AUDIO_RX_FIFOADDR                         0x124200C
-#define ACP_AUDIO_RX_FIFOSIZE                         0x1242010
-#define ACP_AUDIO_RX_DMA_SIZE                         0x1242014
-#define ACP_AUDIO_RX_LINEARPOSITIONCNTR_HIGH          0x1242018
-#define ACP_AUDIO_RX_LINEARPOSITIONCNTR_LOW           0x124201C
-#define ACP_AUDIO_RX_INTR_WATERMARK_SIZE              0x1242020
-#define ACP_AUDIO_TX_RINGBUFADDR                      0x1242024
-#define ACP_AUDIO_TX_RINGBUFSIZE                      0x1242028
-#define ACP_AUDIO_TX_LINKPOSITIONCNTR                 0x124202C
-#define ACP_AUDIO_TX_FIFOADDR                         0x1242030
-#define ACP_AUDIO_TX_FIFOSIZE                         0x1242034
-#define ACP_AUDIO_TX_DMA_SIZE                         0x1242038
-#define ACP_AUDIO_TX_LINEARPOSITIONCNTR_HIGH          0x124203C
-#define ACP_AUDIO_TX_LINEARPOSITIONCNTR_LOW           0x1242040
-#define ACP_AUDIO_TX_INTR_WATERMARK_SIZE              0x1242044
-
-#define ACP_BT_RX_RINGBUFADDR                         0x1242048
-#define ACP_BT_RX_RINGBUFSIZE                         0x124204C
-#define ACP_BT_RX_FIFOADDR                            0x1242054
-#define ACP_BT_RX_FIFOSIZE                            0x1242058
-#define ACP_BT_RX_DMA_SIZE                            0x124205C
-#define ACP_BT_RX_LINEARPOSITIONCNTR_HIGH             0x1242060
-#define ACP_BT_RX_LINEARPOSITIONCNTR_LOW              0x1242064
-#define ACP_BT_RX_INTR_WATERMARK_SIZE                 0x1242068
-#define ACP_BT_TX_RINGBUFADDR                         0x124206C
-#define ACP_BT_TX_RINGBUFSIZE                         0x1242070
-#define ACP_BT_TX_FIFOADDR                            0x1242078
-#define ACP_BT_TX_FIFOSIZE                            0x124207C
-#define ACP_BT_TX_DMA_SIZE                            0x1242080
-#define ACP_BT_TX_LINEARPOSITIONCNTR_HIGH             0x1242084
-#define ACP_BT_TX_LINEARPOSITIONCNTR_LOW              0x1242088
-#define ACP_BT_TX_INTR_WATERMARK_SIZE                 0x124208C
-
-#define ACP_HS_RX_RINGBUFADDR                         0x1242090
-#define ACP_HS_RX_RINGBUFSIZE                         0x1242094
-#define ACP_HS_RX_FIFOADDR                            0x124209C
-#define ACP_HS_RX_FIFOSIZE                            0x12420A0
-#define ACP_HS_RX_DMA_SIZE                            0x12420A4
-#define ACP_HS_RX_LINEARPOSITIONCNTR_HIGH             0x12420A8
-#define ACP_HS_RX_LINEARPOSITIONCNTR_LOW              0x12420AC
-#define ACP_HS_RX_INTR_WATERMARK_SIZE                 0x12420B0
-#define ACP_HS_TX_RINGBUFADDR                         0x12420B4
-#define ACP_HS_TX_RINGBUFSIZE                         0x12420B8
-#define ACP_HS_TX_FIFOADDR                            0x12420C0
-#define ACP_HS_TX_FIFOSIZE                            0x12420C4
-#define ACP_HS_TX_DMA_SIZE                            0x12420C8
-#define ACP_HS_TX_LINEARPOSITIONCNTR_HIGH             0x12420CC
-#define ACP_HS_TX_LINEARPOSITIONCNTR_LOW              0x12420D0
-#define ACP_HS_TX_INTR_WATERMARK_SIZE                 0x12420D4
-
-/* Registers from ACP_I2S_TDM block */
-#define ACP_I2STDM_IER			0x1242400
-#define ACP_I2STDM_IRER			0x1242404
-#define ACP_I2STDM_RXFRMT		0x1242408
-#define ACP_I2STDM_ITER			0x124240C
-#define ACP_I2STDM_TXFRMT		0x1242410
-#define ACP_I2STDM0_MSTRCLKGEN		0x1242414
-#define ACP_I2STDM2_MSTRCLKGEN		0x124241C
-
-/* Registers from ACP_BT_TDM block */
-#define ACP_BTTDM_IER			0x1242800
-#define ACP_BTTDM_IRER			0x1242804
-#define ACP_BTTDM_ITER			0x124280C
-#define ACP_HSTDM_IER			0x1242814
-#define ACP_HSTDM_IRER			0x1242818
-#define ACP_HSTDM_RXFRMT		0x124281C
-#define ACP_HSTDM_ITER			0x1242820
-#define ACP_HSTDM_TXFRMT		0x1242824
-
-/* Registers from ACP_WOV block */
-#define ACP_WOV_PDM_ENABLE			0x1242C04
-#define ACP_WOV_PDM_DMA_ENABLE			0x1242C08
-#define ACP_WOV_RX_RINGBUFADDR			0x1242C0C
-#define ACP_WOV_RX_RINGBUFSIZE			0x1242C10
-#define ACP_WOV_RX_INTR_WATERMARK_SIZE		0x1242C20
-#define ACP_WOV_PDM_FIFO_FLUSH			0x1242C24
-#define ACP_WOV_PDM_NO_OF_CHANNELS		0x1242C28
-#define ACP_WOV_PDM_DECIMATION_FACTOR		0x1242C2C
-#define ACP_WOV_MISC_CTRL			0x1242C5C
-#define ACP_WOV_CLK_CTRL			0x1242C60
-
-#define ACP_SW_EN                                     0x1243000
-#define ACP_SW_EN_STATUS                              0x1243004
-#define ACP_SW_AUDIO_TX_EN                            0x1243010
-#define ACP_SW_AUDIO_TX_EN_STATUS                     0x1243014
-#define ACP_SW_BT_TX_EN                               0x1243050
-#define ACP_SW_BT_TX_EN_STATUS                        0x1243054
-#define ACP_SW_HS_TX_EN                          0x124306C
-#define ACP_SW_HS_TX_EN_STATUS                   0x1243070
-#define ACP_SW_AUDIO_RX_EN                            0x1243088
-#define ACP_SW_AUDIO_RX_EN_STATUS                     0x124308C
-#define ACP_SW_BT_RX_EN                               0x1243128
-#define ACP_SW_BT_RX_EN_STATUS                        0x124312C
-#define ACP_SW_HS_RX_EN                          0x1243144
-#define ACP_SW_HS_RX_EN_STATUS                   0x1243148
-/* Registers from ACP_P1_AUDIO_BUFFERS block */
-#define ACP_P1_I2S_RX_RINGBUFADDR		0x1243A00
-#define ACP_P1_I2S_RX_RINGBUFSIZE		0x1243A04
-#define ACP_P1_I2S_RX_FIFOADDR			0x1243A0C
-#define ACP_P1_I2S_RX_FIFOSIZE			0x1243A10
-#define ACP_P1_I2S_RX_DMA_SIZE			0x1243A14
-#define ACP_P1_I2S_RX_LINEARPOSITIONCNTR_HIGH	0x1243A18
-#define ACP_P1_I2S_RX_LINEARPOSITIONCNTR_LOW	0x1243A1C
-#define ACP_P1_I2S_RX_INTR_WATERMARK_SIZE	0x1243A20
-#define ACP_P1_I2S_TX_RINGBUFADDR		0x1243A24
-#define ACP_P1_I2S_TX_RINGBUFSIZE		0x1243A28
-#define ACP_P1_I2S_TX_FIFOADDR			0x1243A30
-#define ACP_P1_I2S_TX_FIFOSIZE			0x1243A34
-#define ACP_P1_I2S_TX_DMA_SIZE			0x1243A38
-#define ACP_P1_I2S_TX_LINEARPOSITIONCNTR_HIGH	0x1243A3C
-#define ACP_P1_I2S_TX_LINEARPOSITIONCNTR_LOW	0x1243A40
-#define ACP_P1_I2S_TX_INTR_WATERMARK_SIZE	0x1243A44
-#define ACP_P1_BT_RX_RINGBUFADDR		0x1243A48
-#define ACP_P1_BT_RX_RINGBUFSIZE		0x1243A4C
-#define ACP_P1_BT_RX_FIFOADDR			0x1243A54
-#define ACP_P1_BT_RX_FIFOSIZE			0x1243A58
-#define ACP_P1_BT_RX_DMA_SIZE			0x1243A5C
-#define ACP_P1_BT_RX_LINEARPOSITIONCNTR_HIGH	0x1243A60
-#define ACP_P1_BT_RX_LINEARPOSITIONCNTR_LOW	0x1243A64
-#define ACP_P1_BT_RX_INTR_WATERMARK_SIZE	0x1243A68
-#define ACP_P1_BT_TX_RINGBUFADDR		0x1243A6C
-#define ACP_P1_BT_TX_RINGBUFSIZE		0x1243A70
-#define ACP_P1_BT_TX_FIFOADDR			0x1243A78
-#define ACP_P1_BT_TX_FIFOSIZE			0x1243A7C
-#define ACP_P1_BT_TX_DMA_SIZE			0x1243A80
-#define ACP_P1_BT_TX_LINEARPOSITIONCNTR_HIGH	0x1243A84
-#define ACP_P1_BT_TX_LINEARPOSITIONCNTR_LOW	0x1243A88
-#define ACP_P1_BT_TX_INTR_WATERMARK_SIZE	0x1243A8C
-#define ACP_P1_HS_RX_RINGBUFADDR		0x1243A90
-#define ACP_P1_HS_RX_RINGBUFSIZE		0x1243A94
-#define ACP_P1_HS_RX_FIFOADDR			0x1243A9C
-#define ACP_P1_HS_RX_FIFOSIZE			0x1243AA0
-#define ACP_P1_HS_RX_DMA_SIZE			0x1243AA4
-#define ACP_P1_HS_RX_LINEARPOSITIONCNTR_HIGH	0x1243AA8
-#define ACP_P1_HS_RX_LINEARPOSITIONCNTR_LOW	0x1243AAC
-#define ACP_P1_HS_RX_INTR_WATERMARK_SIZE	0x1243AB0
-#define ACP_P1_HS_TX_RINGBUFADDR		0x1243AB4
-#define ACP_P1_HS_TX_RINGBUFSIZE		0x1243AB8
-#define ACP_P1_HS_TX_FIFOADDR			0x1243AC0
-#define ACP_P1_HS_TX_FIFOSIZE			0x1243AC4
-#define ACP_P1_HS_TX_DMA_SIZE			0x1243AC8
-#define ACP_P1_HS_TX_LINEARPOSITIONCNTR_HIGH	0x1243ACC
-#define ACP_P1_HS_TX_LINEARPOSITIONCNTR_LOW	0x1243AD0
-#define ACP_P1_HS_TX_INTR_WATERMARK_SIZE	0x1243AD4
-
-#define ACP_P1_SW_EN				0x1243C00
-#define ACP_P1_SW_BT_TX_EN			0x1243C50
-#define ACP_P1_SW_BT_TX_EN_STATUS	0x1243C54
-#define ACP_P1_SW_BT_RX_EN			0x1243D28
-#define ACP_P1_SW_BT_RX_EN_STATUS	0x1243D2C
-#define MP1_SMN_C2PMSG_69	0x58A14
-#define MP1_SMN_C2PMSG_85	0x58A54
-#define MP1_SMN_C2PMSG_93	0x58A74
-
-#define CLK5_ROOTREFCLKMUX_1                          0x6c0c8
-#define CLK5_CLK_PLL_REFCLK_RATE_STARTUP              0x6C0D0
-#define CLK5_CLK_PLL_REQ                              0x6C0DC
-#define CLK5_CLK1_DFS_CNTL                            0x6C1B0
-#define CLK5_CLK1_CURRENT_CNT                         0x6C348
-#define CLK5_CLK0_DFS_CNTL                            0x6C1A4
-#define CLK5_CLK0_CURRENT_CNT                         0x6C344
-#define CLK5_CLK0_BYPASS_CNTL                         0x6C200
-#define CLK5_CLK1_BYPASS_CNTL                         0x6C224
-#define CLK5_CLK0_DFS_STATUS                          0x6C1AC
-#define CLK5_CLK1_DFS_STATUS                          0x6C1B8
-#define CLK5_SPLL_FIELD_2                             0x6C114
-#define CLK5_CLK_PLL_PWR_REQ                          0x6C2C0
-#define CLK5_CLK_DFSBYPASS_CONTROL                    0x6C2C8
-#define CLK5_CLK_FSM_STATUS                           0x6C2D4
-#define CLK5_SPLL_FUSE_1                              0x6C0F8
-#define CLK5_SPLL_FUSE_2                              0x6C0FC
-#define CLK5_SPLL_FIELD_7                             0x6C128
-#define CLK5_SPLL_FIELD_9                             0x6C130
-#define CLK5_SPLL_FIELD_6nm                           0x6C138
-#define CLK5_SPLL_FIELD_4                             0x6C11C
-#define CLK5_SPLL_FIELD_5nm_BUS_CTRL                  0x6c140
-#define CLK5_SPLL_FIELD_5nm_BUS_WDATA                 0x6c144
-#define CLK5_SPLL_FIELD_5nm_BUS_STATUS                0x6c148
-#define CLK5_CLK_PLL_RESET_STOP_TIMER                 0x6C180
-
-#endif
diff --git a/src/platform/amd/acp_6_3/include/platform/chip_registers.h b/src/platform/amd/acp_6_3/include/platform/chip_registers.h
deleted file mode 100644
index 5ea907e2ff5b..000000000000
--- a/src/platform/amd/acp_6_3/include/platform/chip_registers.h
+++ /dev/null
@@ -1,1062 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- *
- * Copyright(c) 2023 AMD.All rights reserved.
- *
- * Author:      Basavaraj Hiregoudar <basavaraj.hiregoudar@amd.com>
- *              SaiSurya, Ch <saisurya.chakkaveeravenkatanaga@amd.com>
- */
-#if !defined(_ACP_6_3_REG_HEADER)
-#define _ACP_6_3_REG_HEADER
-
-typedef	union acp_dma_cntl_0 {
-	struct {
-	unsigned int	dmachrst:1;
-	unsigned int	dmachrun:1;
-	unsigned int	dmachiocen:1;
-	unsigned int	:29;
-	} bits;
-	unsigned int	u32all;
-} acp_dma_cntl_0_t;
-
-typedef	union acp_dma_ch_sts {
-	struct {
-	unsigned int	dmachrunsts:8;
-	unsigned int	:24;
-	} bits;
-	unsigned int	u32all;
-} acp_dma_ch_sts_t;
-
-typedef	union acp_external_intr_enb {
-	struct {
-	unsigned int	acpextintrenb:1;
-	unsigned int	:31;
-	} bits;
-	unsigned int	u32all;
-} acp_external_intr_enb_t;
-
-typedef	union acp_dsp0_intr_cntl {
-	struct {
-	unsigned int	dmaiocmask:8;
-	unsigned int	:8;
-	unsigned int	wov_dma_intr_mask:1;
-	unsigned int	:6;
-	unsigned int	audio_buffer_int_mask:6;
-	unsigned int	:3;
-	} bits;
-	unsigned int	u32all;
-} acp_dsp0_intr_cntl_t;
-
-typedef	union acp_dsp0_intr_stat {
-	struct {
-	unsigned int	dmaiocstat:8;
-	unsigned int	:8;
-	unsigned int	wov_dma_stat:1;
-	unsigned int	:6;
-	unsigned int	audio_buffer_int_stat:6;
-	unsigned int	:3;
-	} bits;
-	unsigned int	u32all;
-} acp_dsp0_intr_stat_t;
-
-typedef	union acp_dsp0_intr_cntl1 {
-	struct {
-		unsigned int	acp_fusion_dsp_ext_timer1_timeoutmask :1;
-		unsigned int	fusion_dsp_watchdog_timeoutmask :1;
-		unsigned int	soundwire_mask :1;
-		unsigned int	audio_buffer_int_mask :6;
-		unsigned int	:23;
-	} bits;
-	unsigned int	u32all;
-} acp_dsp0_intr_cntl1_t;
-
-typedef union acp_dsp0_intr_stat1 {
-	struct {
-		unsigned int	acp_fusion_dsp_timer1_timeoutstat :1;
-		unsigned int	fusion_dsp_watchdog_timeoutstat :1;
-		unsigned int	soundwire_stat :1;
-		unsigned int	audio_buffer_int_stat :6;
-		unsigned int	:23;
-	} bits;
-	unsigned int	u32all;
-} acp_dsp0_intr_stat1_t;
-
-typedef	union acp_dsp_sw_intr_cntl {
-	struct {
-	unsigned int	:2;
-	unsigned int	dsp0_to_host_intr_mask:1;
-	unsigned int	:29;
-	} bits;
-	unsigned int	u32all;
-} acp_dsp_sw_intr_cntl_t;
-
-typedef	union acp_dsp_sw_intr_stat {
-	struct {
-	unsigned int	host_to_dsp0_intr1_stat:1;
-	unsigned int	host_to_dsp0_intr2_stat:1;
-	unsigned int	dsp0_to_host_intr_stat:1;
-	unsigned int	host_to_dsp0_intr3_stat:1;
-	unsigned int	:28;
-	} bits;
-	unsigned int	u32all;
-} acp_dsp_sw_intr_stat_t;
-
-typedef	union acp_sw_intr_trig {
-	struct {
-	unsigned int	trig_host_to_dsp0_intr1:1;
-	unsigned int	:1;
-	unsigned int	trig_dsp0_to_host_intr:1;
-	unsigned int	:29;
-	} bits;
-	unsigned int	u32all;
-} acp_sw_intr_trig_t;
-
-typedef	union dsp_interrupt_routing_ctrl_0 {
-	struct {
-		unsigned int	dma_intr_level:3;
-		unsigned int	:18;
-		unsigned int	watchdog_intr_level:3;
-		unsigned int	az_sw_i2s_intr_level:3;
-		unsigned int	sha_intr_level:3;
-		unsigned int	:2;
-	} bits;
-	unsigned int	u32all;
-} dsp_interrupt_routing_ctrl_0_t;
-
-typedef	union dsp_interrupt_routing_ctrl_1 {
-	struct {
-		unsigned int	host_to_dsp_intr1_level:3;
-		unsigned int	host_to_dsp_intr2_level:3;
-		unsigned int	src_intr_level:3;
-		unsigned int	mailbox_intr_level:3;
-		unsigned int	error_intr_level:3;
-		unsigned int	wov_intr_level:3;
-		unsigned int	fusion_timer1_intr_level:3;
-		unsigned int	fusion_watchdog_intr_level:3;
-		unsigned int	p1_sw_i2s_intr_level:3;
-		unsigned int	:5;
-	} bits;
-	unsigned int    u32all;
-} dsp_interrupt_routing_ctrl_1_t;
-
-typedef	union acp_i2s_rx_ringbufaddr {
-	struct {
-		unsigned int	i2s_rx_ringbufaddr:27;
-		unsigned int	:5;
-	} bits;
-	unsigned int	u32all;
-} acp_i2s_rx_ringbufaddr_t;
-
-typedef	union acp_i2s_rx_ringbufsize {
-	struct {
-		unsigned int	i2s_rx_ringbufsize:26;
-		unsigned int	:6;
-	} bits;
-	unsigned int	u32all;
-} acp_i2s_rx_ringbufsize_t;
-
-typedef	union acp_i2s_rx_linkpositioncntr {
-	struct {
-		unsigned int	i2s_rx_linkpositioncntr:26;
-		unsigned int	:6;
-	} bits;
-	unsigned int	u32all;
-} acp_i2s_rx_linkpositioncntr_t;
-
-typedef	union acp_i2s_rx_fifoaddr {
-	struct {
-		unsigned int	i2s_rx_fifoaddr:27;
-		unsigned int	:5;
-	} bits;
-	unsigned int	u32all;
-} acp_i2s_rx_fifoaddr_t;
-
-typedef	union acp_i2s_rx_fifosize {
-	struct {
-		unsigned int	i2s_rx_fifosize:13;
-		unsigned int	:19;
-	} bits;
-	unsigned int	u32all;
-} acp_i2s_rx_fifosize_t;
-
-typedef	union acp_i2s_rx_dma_size {
-	struct {
-		unsigned int	i2s_rx_dma_size:13;
-		unsigned int	:19;
-	} bits;
-	unsigned int	u32all;
-} acp_i2s_rx_dma_size_t;
-
-typedef	union acp_i2s_rx_linearpositioncntr_high {
-	struct {
-		unsigned int	i2s_rx_linearpositioncntr_high:32;
-	} bits;
-	unsigned int	u32all;
-} acp_i2s_rx_linearpositioncntr_high_t;
-
-typedef	union acp_i2s_rx_linearpositioncntr_low {
-	struct {
-		unsigned int	i2s_rx_linearpositioncntr_low:32;
-	} bits;
-	unsigned int	u32all;
-} acp_i2s_rx_linearpositioncntr_low_t;
-
-typedef	union acp_i2s_rx_watermark_size {
-	struct {
-		unsigned int	i2s_rx_intr_watermark_size:26;
-		unsigned int	:6;
-	} bits;
-	unsigned int	u32all;
-} acp_i2s_rx_intr_watermark_size_t;
-
-typedef	union acp_i2s_tx_ringbufaddr {
-	struct {
-		unsigned int	i2s_tx_ringbufaddr:27;
-		unsigned int	:5;
-	} bits;
-	unsigned int	u32all;
-} acp_i2s_tx_ringbufaddr_t;
-
-typedef	union acp_i2s_tx_ringbufsize {
-	struct {
-		unsigned int	i2s_tx_ringbufsize:26;
-		unsigned int	:6;
-	} bits;
-	unsigned int	u32all;
-} acp_i2s_tx_ringbufsize_t;
-
-typedef	union acp_i2s_tx_linkpositioncntr {
-	struct {
-		unsigned int	i2s_tx_linkpositioncntr:26;
-		unsigned int	:6;
-	} bits;
-	unsigned int	u32all;
-} acp_i2s_tx_linkpositioncntr_t;
-
-typedef	union acp_i2s_tx_fifoaddr {
-	struct {
-		unsigned int	i2s_tx_fifoaddr:27;
-		unsigned int	:5;
-	} bits;
-	unsigned int	u32all;
-} acp_i2s_tx_fifoaddr_t;
-
-typedef	union acp_i2s_tx_fifosize {
-	struct {
-		unsigned int	i2s_tx_fifosize:13;
-		unsigned int	:19;
-	} bits;
-	unsigned int	u32all;
-} acp_i2s_tx_fifosize_t;
-
-typedef	union acp_i2s_tx_dma_size {
-	struct {
-		unsigned int	i2s_tx_dma_size:13;
-		unsigned int	:19;
-	} bits;
-	unsigned int	u32all;
-} acp_i2s_tx_dma_size_t;
-
-typedef	union acp_i2s_tx_linearpositioncntr_high {
-	struct {
-		unsigned int	i2s_tx_linearpositioncntr_high:32;
-	} bits;
-	unsigned int	u32all;
-} acp_i2s_tx_linearpositioncntr_hight_t;
-
-typedef	union acp_i2s_tx_linearpositioncntr_low {
-	struct {
-		unsigned int	i2s_tx_linearpositioncntr_low:32;
-	} bits;
-	unsigned int	u32all;
-} acp_i2s_tx_linearpositioncntr_low_t;
-
-typedef	union acp_i2s_tx_intr_watermark_size {
-	struct {
-		unsigned int	i2s_tx_intr_watermark_size:26;
-		unsigned int	:6;
-	} bits;
-	unsigned int	u32all;
-} acp_i2s_tx_intr_watermark_size_t;
-
-typedef	union acp_bt_rx_ringbufaddr {
-	struct {
-		unsigned int	bt_rx_ringbufaddr:27;
-		unsigned int	:5;
-	} bits;
-	unsigned int	u32all;
-} acp_bt_rx_ringbufaddr_t;
-
-typedef	union acp_bt_rx_ringbufsize {
-	struct {
-		unsigned int	bt_rx_ringbufsize:26;
-		unsigned int	:6;
-	} bits;
-	unsigned int	u32all;
-} acp_bt_rx_ringbufsize_t;
-
-typedef	union acp_bt_rx_linkpositioncntr {
-	struct {
-		unsigned int	bt_rx_linkpositioncntr:26;
-		unsigned int	:6;
-	} bits;
-	unsigned int	u32all;
-} acp_bt_rx_linkpositioncntr_t;
-
-typedef	union acp_bt_rx_fifoaddr {
-	struct {
-		unsigned int	bt_rx_fifoaddr:27;
-		unsigned int	:5;
-	} bits;
-	unsigned int	u32all;
-} acp_bt_rx_fifoaddr_t;
-
-typedef	union acp_bt_rx_fifosize {
-	struct {
-		unsigned int	bt_rx_fifosize:13;
-		unsigned int	:19;
-	} bits;
-	unsigned int	u32all;
-} acp_bt_rx_fifosize_t;
-
-typedef	union acp_bt_rx_dma_size {
-	struct {
-		unsigned int	bt_rx_dma_size:13;
-		unsigned int	:19;
-	} bits;
-	unsigned int	u32all;
-} acp_bt_rx_dma_size_t;
-
-typedef	union acp_bt_rx_linearpositioncntr_high {
-	struct {
-		unsigned int	bt_rx_linearpositioncntr_high:32;
-	} bits;
-	unsigned int	u32all;
-} acp_bt_rx_linearpositioncntr_high_t;
-
-typedef	union acp_bt_rx_linearpositioncntr_low {
-	struct {
-		unsigned int	bt_rx_linearpositioncntr_low:32;
-	} bits;
-	unsigned int	u32all;
-} acp_bt_rx_linearpositioncntr_low_t;
-
-typedef	union acp_bt_rx_intr_watermark_size {
-	struct {
-		unsigned int	bt_rx_intr_watermark_size:26;
-		unsigned int	:6;
-	} bits;
-	unsigned int	u32all;
-} acp_bt_rx_intr_watermark_size_t;
-
-typedef	union acp_bt_tx_ringbufaddr {
-	struct {
-		unsigned int	bt_tx_ringbufaddr:27;
-		unsigned int	:5;
-	} bits;
-	unsigned int	u32all;
-} acp_bt_tx_ringbufaddr_t;
-
-typedef	union acp_bt_tx_ringbufsize {
-	struct {
-		unsigned int	bt_tx_ringbufsize:26;
-		unsigned int	:6;
-	} bits;
-	unsigned int	u32all;
-} acp_bt_tx_ringbufsize_t;
-
-typedef	union acp_bt_tx_linkpositiontcntr {
-	struct {
-		unsigned int	bt_tx_linkpositioncntr:26;
-		unsigned int	:6;
-	} bits;
-	unsigned int	u32all;
-} acp_bt_tx_linkpositiontcntr_t;
-
-typedef	union acp_bt_tx_fifoaddr {
-	struct {
-		unsigned int	bt_tx_fifoaddr:27;
-		unsigned int	:5;
-	} bits;
-	unsigned int	u32all;
-} acp_bt_tx_fifoaddr_t;
-
-typedef	union acp_bt_tx_fifosize {
-	struct {
-		unsigned int	bt_tx_fifosize:13;
-		unsigned int	:19;
-	} bits;
-	unsigned int	u32all;
-} acp_bt_tx_fifosize_t;
-
-typedef	union acp_bt_tx_dmasize {
-	struct {
-		unsigned int	bt_tx_dma_size:13;
-		unsigned int	:19;
-	} bits;
-	unsigned int	u32all;
-} acp_bt_tx_dmasize_t;
-
-typedef	union acp_bt_tx_linearpositioncntr_high {
-	struct {
-		unsigned int	bt_tx_linearpositioncntr_high:32;
-	} bits;
-	unsigned int	u32all;
-} acp_bt_tx_linearpositioncntr_high_t;
-
-typedef	union acp_bt_tx_linearpositioncntr_low {
-	struct {
-		unsigned int	bt_tx_linearpositioncntr_low:32;
-	} bits;
-	unsigned int	u32all;
-} acp_bt_tx_linearpositioncntr_low_t;
-
-typedef	union acp_bt_tx_intr_watermark_size {
-	struct {
-		unsigned int	bt_tx_intr_watermark_size:26;
-		unsigned int	:6;
-	} bits;
-	unsigned int	u32all;
-} acp_bt_tx_intr_watermark_size_t;
-
-typedef	union acp_i2stdm_ier {
-	struct {
-		unsigned int	i2stdm_ien:1;
-		unsigned int	:31;
-	} bits;
-	unsigned int	u32all;
-} acp_i2stdm_ier_t;
-
-typedef	union acp_i2stdm_irer {
-	struct {
-		unsigned int	i2stdm_rx_en:1;
-		unsigned int	i2stdm_rx_protocol_mode:1;
-		unsigned int	i2stdm_rx_data_path_mode:1;
-		unsigned int	i2stdm_rx_samplen:3;
-		unsigned int	i2stdm_rx_status:1;
-		unsigned int	:25;
-	} bits;
-	unsigned int	u32all;
-} acp_i2stdm_irer_t;
-
-typedef	union acp_i2stdm_iter {
-	struct {
-		unsigned int	i2stdm_txen:1;
-		unsigned int	i2stdm_tx_protocol_mode:1;
-		unsigned int	i2stdm_tx_data_path_mode:1;
-		unsigned int	i2stdm_tx_samp_len:3;
-		unsigned int	i2stdm_tx_status:1;
-		unsigned int	:25;
-	} bits;
-	unsigned int	u32all;
-} acp_i2stdm_iter_t;
-
-typedef	union acp_bttdm_ier {
-	struct {
-		unsigned int	bttdm_ien:1;
-		unsigned int	:31;
-	} bits;
-	unsigned int	u32all;
-} acp_bttdm_ier_t;
-
-typedef	union acp_bttdm_irer {
-	struct {
-		unsigned int	bttdm_rx_en:1;
-		unsigned int	bttdm_rx_protocol_mode:1;
-		unsigned int	bttdm_rx_data_path_mode:1;
-		unsigned int	bttdm_rx_samplen:3;
-		unsigned int	bttdm_rx_status:1;
-		unsigned int	:25;
-	} bits;
-	unsigned int	u32all;
-} acp_bttdm_irer_t;
-
-typedef	union acp_bttdm_iter {
-	struct {
-		unsigned int	bttdm_txen :1;
-		unsigned int	bttdm_tx_protocol_mode :1;
-		unsigned int	bttdm_tx_data_path_mode :1;
-		unsigned int	bttdm_tx_samp_len :3;
-		unsigned int	bttdm_tx_status :1;
-		unsigned int	:25;
-	} bits;
-	unsigned int	u32all;
-} acp_bttdm_iter_t;
-
-typedef	union acp_wov_pdm_dma_enable {
-	struct {
-		unsigned int	pdm_dma_en :1;
-		unsigned int	pdm_dma_en_status :1;
-		unsigned int	:30;
-	} bits;
-unsigned int	u32all;
-} acp_wov_pdm_dma_enable_t;
-
-typedef	union acp_wov_rx_ringbufaddr {
-	struct {
-		unsigned int	rx_ringbufaddr :27;
-		unsigned int	:5;
-	} bits;
-	unsigned int	u32all;
-} acp_wov_rx_ringbufaddr_t;
-
-typedef	union acp_wov_rx_ringbufsize {
-	struct {
-		unsigned int	rx_ringbufsize :26;
-		unsigned int	:6;
-	} bits;
-	unsigned int	u32all;
-} acp_wov_rx_ringbufsize_t;
-
-typedef	union acp_wov_rx_intr_watermark_size {
-	struct {
-		unsigned int	rx_intr_watermark_size :26;
-		unsigned int	:6;
-	} bits;
-	unsigned int	u32all;
-} acp_wov_rx_intr_watermark_size_t;
-
-typedef	union acp_wov_pdm_no_of_channels {
-	struct {
-		unsigned int	pdm_no_of_channels :2;
-		unsigned int	:30;
-	} bits;
-	unsigned int	u32all;
-} acp_wov_pdm_no_of_channels_t;
-
-typedef	union acp_wov_pdm_decimation_factor {
-	struct {
-		unsigned int	pdm_decimation_factor :2;
-		unsigned int	:30;
-	} bits;
-	unsigned int	u32all;
-} acp_wov_pdm_decimation_factor_t;
-
-typedef	union acp_wov_misc_ctrl {
-	struct {
-		unsigned int	:3;
-		unsigned int	pcm_data_shift_ctrl :2;
-		unsigned int	:27;
-	} bits;
-	unsigned int	u32all;
-} acp_wov_misc_ctrl_t;
-
-typedef	union acp_wov_clk_ctrl {
-	struct {
-		unsigned int	brm_clk_ctrl :4;
-		unsigned int	pdm_vad_clkdiv :2;
-		unsigned int	:26;
-	} bits;
-	unsigned int	u32all;
-} acp_wov_clk_ctrl_t;
-
-typedef	union acp_srbm_cycle_sts {
-	struct {
-		unsigned int	srbm_clients_sts :1;
-		unsigned int	:7;
-	} bits;
-	unsigned int	u32all;
-} acp_srbm_cycle_sts_t;
-
-typedef	union acp_hs_rx_ringbufaddr {
-	struct {
-		unsigned int	hs_rx_ringbufaddr :32;
-	} bits;
-	unsigned int	u32all;
-} acp_hs_rx_ringbufaddr_t;
-
-typedef	union acp_hs_rx_ringbufsize {
-	struct {
-		unsigned int	hs_rx_ringbufsize :26;
-		unsigned int	:6;
-	} bits;
-	unsigned int	u32all;
-} acp_hs_rx_ringbufsize_t;
-
-typedef	union acp_hs_rx_linkpositioncntr {
-	struct {
-		unsigned int	hs_rx_linkpositioncntr :26;
-		unsigned int	:6;
-	} bits;
-	unsigned int	u32all;
-} acp_hs_rx_linkpositioncntr_t;
-
-typedef	union acp_hs_rx_fifoaddr {
-	struct {
-		unsigned int	hs_rx_fifoaddr :27;
-		unsigned int	:5;
-	} bits;
-	unsigned int	u32all;
-} acp_hs_rx_fifoaddr_t;
-
-typedef	union acp_hs_rx_fifosize {
-	struct {
-		unsigned int	hs_rx_fifosize :13;
-		unsigned int	:19;
-	} bits;
-	unsigned int	u32all;
-} acp_hs_rx_fifosize_t;
-
-typedef	union acp_hs_rx_dma_size {
-	struct {
-		unsigned int	hs_rx_dma_size :13;
-		unsigned int	:19;
-	} bits;
-	unsigned int	u32all;
-} acp_hs_rx_dma_size_t;
-
-typedef	union acp_hs_rx_linearpositioncntr_high {
-	struct {
-		unsigned int	hs_rx_linearpositioncntr_high :32;
-	} bits;
-	unsigned int	u32all;
-} acp_hs_rx_linearpositioncntr_high_t;
-
-typedef	union acp_hs_rx_linearpositioncntr_low {
-	struct {
-		unsigned int	hs_rx_linearpositioncntr_low :32;
-	} bits;
-	unsigned int	u32all;
-} acp_hs_rx_linearpositioncntr_low_t;
-
-typedef	union acp_hs_rx_intr_watermark_size {
-	struct {
-		unsigned int	hs_rx_intr_watermark_size :26;
-		unsigned int	:6;
-	} bits;
-	unsigned int	u32all;
-} acp_hs_rx_intr_watermark_size_t;
-
-typedef	union acp_hs_tx_ringbufaddr {
-	struct {
-		unsigned int	hs_tx_ringbufaddr :32;
-	} bits;
-	unsigned int	u32all;
-} acp_hs_tx_ringbufaddr_t;
-
-typedef	union acp_hs_tx_ringbufsize {
-	struct {
-		unsigned int	hs_tx_ringbufsize :26;
-		unsigned int	:6;
-	} bits;
-	unsigned int	u32all;
-} acp_hs_tx_ringbufsize_t;
-
-typedef	union acp_hs_tx_linkpositioncntr {
-	struct {
-		unsigned int	hs_tx_linkpositioncntr :26;
-		unsigned int	:6;
-	} bits;
-	unsigned int    u32all;
-} acp_hs_tx_linkpositioncntr_t;
-
-typedef	union acp_hs_tx_fifoaddr {
-	struct {
-		unsigned int	hs_tx_fifoaddr :27;
-		unsigned int	:5;
-	} bits;
-	unsigned int	u32all;
-} acp_hs_tx_fifoaddr_t;
-
-typedef	union acp_hs_tx_fifosize {
-	struct {
-		unsigned int	hs_tx_fifosize :13;
-		unsigned int	:19;
-	} bits;
-	unsigned int	u32all;
-} acp_hs_tx_fifosize_t;
-
-typedef	union acp_hs_tx_dma_size {
-	struct {
-		unsigned int	hs_tx_dma_size :13;
-		unsigned int	:19;
-	} bits;
-	unsigned int	u32all;
-} acp_hs_tx_dma_size_t;
-
-typedef	union acp_hs_tx_linearpositioncntr_high {
-	struct {
-		unsigned int	hs_tx_linearpositioncntr_high :32;
-	} bits;
-	unsigned int	u32all;
-} acp_hs_tx_linearpositioncntr_high_t;
-
-typedef	union acp_hs_tx_linearpositioncntr_low {
-	struct {
-		unsigned int	hs_tx_linearpositioncntr_low :32;
-	} bits;
-	unsigned int	u32all;
-} acp_hs_tx_linearpositioncntr_low_t;
-
-typedef	union acp_hs_tx_intr_watermark_size {
-	struct {
-		unsigned int	hs_tx_intr_watermark_size :26;
-		unsigned int	:6;
-	} bits;
-	unsigned int	u32all;
-} acp_hs_tx_intr_watermark_size_t;
-
-typedef	union acp_i2stdm_rxfrmt {
-	struct {
-		unsigned int	i2stdm_frame_len :9;
-		unsigned int	:6;
-		unsigned int	i2stdm_num_slots :3;
-		unsigned int	i2stdm_slot_len :5;
-		unsigned int	:9;
-	} bits;
-	unsigned int	u32all;
-} acp_i2stdm_rxfrmt_t;
-
-typedef	union acp_i2stdm_txfrmt {
-	struct {
-		unsigned int	i2stdm_frame_len :9;
-		unsigned int	:6;
-		unsigned int	i2stdm_num_slots :3;
-		unsigned int	i2stdm_slot_len :5;
-		unsigned int	:9;
-	} bits;
-	unsigned int	u32all;
-} acp_i2stdm_txfrmt_t;
-
-typedef	union acp_hstdm_ier {
-	struct {
-		unsigned int	hstdm_ien :1;
-		unsigned int	:31;
-	} bits;
-	unsigned int	u32all;
-} acp_hstdm_ier_t;
-
-typedef	union acp_hstdm_irer {
-	struct {
-		unsigned int	hstdm_rx_en :1;
-		unsigned int	hstdm_rx_protocol_mode :1;
-		unsigned int	hstdm_rx_data_path_mode :1;
-		unsigned int	hstdm_rx_samplen :3;
-		unsigned int	hstdm_rx_status :1;
-		unsigned int	:25;
-	} bits;
-	unsigned int	u32all;
-} acp_hstdm_irer_t;
-
-typedef	union acp_hstdm_rxfrmt {
-	struct {
-		unsigned int	hstdm_frame_len :9;
-		unsigned int	:6;
-		unsigned int	hstdm_num_slots :3;
-		unsigned int	hstdm_slot_len :5;
-		unsigned int	:9;
-	} bits;
-	unsigned int	u32all;
-} acp_hstdm_rxfrmt_t;
-
-typedef	union acp_hstdm_iter {
-	struct {
-		unsigned int	hstdm_txen :1;
-		unsigned int	hstdm_tx_protocol_mode :1;
-		unsigned int	hstdm_tx_data_path_mode :1;
-		unsigned int	hstdm_tx_samp_len :3;
-		unsigned int	hstdm_tx_status :1;
-		unsigned int	:25;
-	} bits;
-	unsigned int	u32all;
-} acp_hstdm_iter_t;
-
-typedef	union acp_hstdm_txfrmt {
-	struct {
-		unsigned int	hstdm_frame_len :9;
-		unsigned int	:6;
-		unsigned int	hstdm_num_slots :3;
-		unsigned int	hstdm_slot_len :5;
-		unsigned int	:9;
-	} bits;
-	unsigned int	u32all;
-} acp_hstdm_txfrmt_t;
-
-typedef union acp_clkmux_sel {
-	struct {
-		unsigned int acp_clkmux_sel : 3;
-		unsigned int : 13;
-		unsigned int acp_clkmux_div_value : 16;
-	} bits;
-	unsigned int  u32all;
-} acp_clkmux_sel_t;
-
-typedef union acp_i2stdm_mstrclkgen {
-	struct {
-		unsigned int i2stdm_master_mode : 1;
-		unsigned int i2stdm_format_mode : 1;
-		unsigned int i2stdm_lrclk_div_val : 11;
-		unsigned int i2stdm_bclk_div_val : 11;
-		unsigned int : 8;
-	} bits;
-	unsigned int  u32all;
-} acp_i2stdm_mstrclkgen_t;
-
-typedef union clk5_clk1_dfs_cntl_u {
-	struct {
-		unsigned int CLK1_DIVIDER : 7;
-		unsigned int : 25;
-	} bitfields, bits;
-	uint32_t    u32all;
-	int32_t     i32all;
-	float       f32all;
-} clk5_clk1_dfs_cntl_u_t;
-
-typedef union clk5_clk1_dfs_status_u {
-	struct {
-		unsigned int	: 16;
-		unsigned int	CLK1_DFS_DIV_REQ_IDLE   : 1;
-		unsigned int	: 2;
-		unsigned int	RO_CLK1_DFS_STATE_IDLE  : 1;
-		unsigned int	CLK1_CURRENT_DFS_DID    : 7;
-		unsigned int	: 5;
-	} bitfields, bits;
-	uint32_t    u32all;
-	int32_t     i32all;
-	float       f32all;
-} clk5_clk1_dfs_status_u_t;
-
-typedef  union clk5_clk1_bypass_cntl_u {
-	struct {
-		unsigned int CLK1_BYPASS_SEL : 3;
-		unsigned int : 13;
-		unsigned int CLK1_BYPASS_DIV : 4;
-		unsigned int : 12;
-	} bitfields, bits;
-	uint32_t    u32all;
-	int32_t     i32all;
-	float       f32all;
-} clk5_clk1_bypass_cntl_u_t;
-
-typedef union clk5_clk_fsm_status_u {
-	struct {
-		unsigned int AUTOLAUCH_FSM_FULL_SPEED_IDLE : 1;
-		unsigned int : 3;
-		unsigned int AUTOLAUCH_FSM_BYPASS_IDLE : 1;
-		unsigned int : 3;
-		unsigned int RO_FSM_PLL_STATUS_STARTED : 1;
-		unsigned int : 3;
-		unsigned int RO_FSM_PLL_STATUS_STOPPED : 1;
-		unsigned int : 3;
-		unsigned int RO_EARLY_FSM_DONE : 1;
-		unsigned int : 3;
-		unsigned int RO_DFS_GAP_ACTIVE : 1;
-		unsigned int : 3;
-		unsigned int RO_DID_FSM_IDLE : 1;
-		unsigned int : 7;
-	} bitfields, bits;
-	uint32_t    u32all;
-	int32_t     i32all;
-	float       f32all;
-} clk5_clk_fsm_status_t;
-
-typedef union clk5_clk_pll_req_u {
-	struct {
-		unsigned int fbmult_int : 9;
-		unsigned int : 3;
-		unsigned int pllspinediv : 4;
-		unsigned int fbmult_frac : 16;
-	} bitfields, bits;
-	uint32_t    u32all;
-	int32_t     i32all;
-	float       f32all;
-} clk5_clk_pll_req_u_t;
-
-typedef  union clk5_clk_pll_refclk_startup {
-	struct {
-		unsigned int  main_pll_ref_clk_rate_startup : 8;
-		unsigned int  main_pll_cfg_4_startup       : 8;
-		unsigned int  main_pll_ref_clk_div_startup : 2;
-		unsigned int  main_pll_cfg_3_startup       : 10;
-		unsigned int                              : 1;
-		unsigned int  main_pll_refclk_src_mux0_startup : 1;
-		unsigned int  main_pll_refclk_src_mux1_startup : 1;
-		unsigned int                              : 1;
-	} bitfields, bits;
-	uint32_t    u32all;
-	int32_t     i32all;
-	float       f32all;
-} clk5_clk_pll_refclk_startup_t;
-
-typedef union clk5_spll_field_2 {
-	struct{
-		unsigned int                             : 3;
-		unsigned int spll_fbdiv_mask_en          : 1;
-		unsigned int spll_fracn_en               : 1;
-		unsigned int spll_freq_jump_en           : 1;
-		unsigned int : 25;
-	} bitfields, bits;
-	uint32_t   u32all;
-	int32_t    i32all;
-	float      f32all;
-} clk5_spll_field_2_t;
-
-typedef union clk5_clk_dfsbypass_cntl {
-	struct {
-		unsigned int enter_dfs_bypass_0            : 1;
-		unsigned int enter_dfs_bypass_1            : 1;
-		unsigned int                             : 14;
-		unsigned int exit_dfs_bypass_0             : 1;
-		unsigned int exit_dfs_bypass_1             : 1;
-		unsigned int                             : 14;
-	} bitfields, bits;
-	uint32_t   u32all;
-	int32_t    i32all;
-	float      f32all;
-} clk5_clk_dfsbypass_cntl_t;
-
-typedef union clk5_clk_pll_pwr_req {
-	struct {
-		unsigned int PLL_AUTO_START_REQ          : 1;
-		unsigned int                             : 3;
-		unsigned int PLL_AUTO_STOP_REQ           : 1;
-		unsigned int                             : 3;
-		unsigned int PLL_AUTO_STOP_NOCLK_REQ     : 1;
-		unsigned int                             : 3;
-		unsigned int PLL_AUTO_STOP_REFBYPCLK_REQ : 1;
-		unsigned int                             : 3;
-		unsigned int PLL_FORCE_RESET_HIGH        : 1;
-		unsigned int                             : 15;
-	} bitfields, bits;
-	uint32_t    u32all;
-	int32_t     i32all;
-	float       f32all;
-} clk5_clk_pll_pwr_req_t;
-
-typedef union clk5_spll_fuse_1 {
-	struct {
-		unsigned int                             : 8;
-		unsigned int spll_gp_coarse_exp          : 4;
-		unsigned int spll_gp_coarse_mant         : 4;
-		unsigned int                             : 4;
-		unsigned int spll_gi_coarse_exp          : 4;
-		unsigned int                             : 1;
-		unsigned int spll_gi_coarse_mant         : 2;
-		unsigned int                             : 5;
-	} bitfields, bits;
-	uint32_t   u32all;
-	int32_t    i32all;
-	float      f32all;
-} clk5_spll_fuse_1_t;
-
-typedef union clk5_spll_fuse_2 {
-	struct {
-		unsigned int spll_tdc_resolution        : 8;
-		unsigned int spll_freq_offset_exp       : 4;
-		unsigned int spll_freq_offset_mant      : 5;
-		unsigned int                            : 15;
-	} bitfields, bits;
-	uint32_t   u32all;
-	int32_t    i32all;
-	float      f32all;
-} clk5_spll_fuse_2_t;
-
-typedef union clk5_spll_field_9 {
-	struct {
-		unsigned int                        : 16;
-		unsigned int spll_dpll_cfg_3        : 10;
-		unsigned int spll_fll_mode          : 1;
-		unsigned int                        : 5;
-	} bitfields, bits;
-	uint32_t   u32all;
-	int32_t    i32all;
-	float      f32all;
-} clk5_spll_field_9_t;
-
-typedef union clk5_spll_field_6nm {
-	struct {
-		unsigned int spll_dpll_cfg_4        : 8;
-		unsigned int spll_reg_tim_exp       : 3;
-		unsigned int spll_reg_tim_mant      : 1;
-		unsigned int spll_ref_tim_exp       : 3;
-		unsigned int spll_ref_tim_mant      : 1;
-		unsigned int spll_vco_pre_div       : 2;
-		unsigned int                        : 14;
-	} bitfields, bits;
-	uint32_t   u32all;
-	int32_t    i32all;
-	float      f32all;
-} clk5_spll_field_6nm_t;
-
-typedef union clk5_spll_field_7 {
-	struct {
-		unsigned int                            : 7;
-		unsigned int spll_pllout_sel            : 1;
-		unsigned int spll_pllout_req            : 1;
-		unsigned int spll_pllout_state          : 2;
-		unsigned int spll_postdiv_ovrd          : 4;
-		unsigned int spll_postdiv_pllout_ovrd   : 4;
-		unsigned int spll_postdiv_sync_enable   : 1;
-		unsigned int                            : 1;
-		unsigned int spll_pwr_state             : 2;
-		unsigned int                            : 1;
-		unsigned int spll_refclk_rate           : 8;
-	} bitfields, bits;
-	uint32_t   u32all;
-	int32_t    i32all;
-	float      f32all;
-} clk5_spll_field_7_t;
-
-typedef union clk5_spll_field_4 {
-	struct {
-		unsigned int spll_fcw0_frac_ovrd    : 16;
-		unsigned int pll_out_sel              : 1;
-		unsigned int                        : 3;
-		unsigned int pll_pwr_dn_state          : 2;
-		unsigned int                        : 2;
-		unsigned int spll_refclk_div        : 2;
-		unsigned int                        : 6;
-	} bitfields, bits;
-	uint32_t   u32all;
-	int32_t    i32all;
-	float      f32all;
-} clk5_spll_field_4_t;
-
-typedef union clk5_spll_field_5nm_bus_ctrl {
-	struct {
-		unsigned int bus_spll_async_mode    :1;
-		unsigned int bus_spll_apb_mode	    :1;
-		unsigned int bus_spll_addr	        :8;
-		unsigned int bus_spll_byte_en	    :4;
-		unsigned int bus_spll_rdtr	        :1;
-		unsigned int bus_spll_resetb	    :1;
-		unsigned int bus_spll_sel	        :1;
-		unsigned int bus_spll_wrtr	        :1;
-		unsigned int                        :14;
-	} bitfields, bits;
-	uint32_t   u32all;
-	int32_t    i32all;
-	float      f32all;
-} clk5_spll_field_5nm_bus_ctrl_t;
-
-typedef union clk5_spll_field_5nm_bus_wdata {
-	struct {
-		unsigned int bus_spll_wr_data;
-	} bitfields, bits;
-	uint32_t   u32all;
-	int32_t    i32all;
-	float      f32all;
-} clk5_spll_field_5nm_bus_wdata_t;
-
-typedef union clk5_rootrefclk_mux_1 {
-	struct {
-		unsigned int ROOTREFCLK_MUX_1   : 1;
-		unsigned int reserved           : 31;
-	} bitfields, bits;
-	uint32_t   u32all;
-	int32_t    i32all;
-	float      f32all;
-} clk5_rootrefclk_mux_1_t;
-
-typedef union clk5_spll_field_5nm_bus_status {
-	struct {
-		unsigned int spll_bus_error     :1;
-		unsigned int spll_bus_rd_valid  :1;
-		unsigned int spll_bus_wr_ack    :1;
-		unsigned int                    :29;
-	} bitfields, bits;
-	uint32_t   u32all;
-	int32_t    i32all;
-	float      f32all;
-} clk5_spll_field_5nm_bus_status_t;
-
-#endif
diff --git a/src/platform/amd/acp_6_3/include/platform/drivers/interrupt.h b/src/platform/amd/acp_6_3/include/platform/drivers/interrupt.h
deleted file mode 100644
index 6197427cdf92..000000000000
--- a/src/platform/amd/acp_6_3/include/platform/drivers/interrupt.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- *
- * Copyright(c) 2023 AMD.All rights reserved.
- *
- * Author:      Basavaraj Hiregoudar <basavaraj.hiregoudar@amd.com>
- *              SaiSurya, Ch <saisurya.chakkaveeravenkatanaga@amd.com>
- */
-#ifdef __SOF_DRIVERS_INTERRUPT_H__
-
-#ifndef __PLATFORM_DRIVERS_INTERRUPT_H__
-#define __PLATFORM_DRIVERS_INTERRUPT_H__
-
-#include <rtos/bit.h>
-#include <sof/lib/cpu.h>
-#include <sof/lib/memory.h>
-
-#define PLATFORM_IRQ_HW_NUM		9
-
-#define PLATFORM_IRQ_FIRST_CHILD	5
-
-#define PLATFORM_IRQ_CHILDREN		32
-
-/* IRQ numbers - wrt Tensilica DSP */
-#define IRQ_NUM_SOFTWARE0	1	/* level 1 */
-
-#define IRQ_NUM_TIMER0		0	/* level 1 */
-
-#define IRQ_NUM_EXT_LEVEL3	3	/* level 1 */
-
-#define IRQ_NUM_TIMER1		6	/* level 2 */
-
-#define IRQ_NUM_EXT_LEVEL4	4	/* level 2 */
-
-#define IRQ_NUM_EXT_LEVEL5	5	/* level 3 */
-
-/* IRQ Masks */
-#define IRQ_MASK_SOFTWARE0	BIT(IRQ_NUM_SOFTWARE0)
-
-#define IRQ_MASK_TIMER0		BIT(IRQ_NUM_TIMER0)
-
-#define IRQ_MASK_TIMER1		BIT(IRQ_NUM_TIMER1)
-
-#define IRQ_MASK_EXT_LEVEL3	BIT(IRQ_NUM_EXT_LEVEL3)
-
-#define IRQ_MASK_EXT_LEVEL4	BIT(IRQ_NUM_EXT_LEVEL4)
-
-#define IRQ_MASK_EXT_LEVEL5	BIT(IRQ_NUM_EXT_LEVEL5)
-
-#define HOST_TO_DSP_INTR	0x1
-
-#define _XTSTR(x)   # x
-
-#define XTSTR(x)    _XTSTR(x)
-
-/* Enabling flag */
-#define INTERRUPT_ENABLE	1
-
-/* Clearing flag */
-#define INTERRUPT_CLEAR		0
-
-/* Disable flag */
-#define INTERRUPT_DISABLE	0
-
-/* brief Tensilica  Interrupt Levels. */
-typedef enum {
-	acp_interrupt_level_3 = 0,
-
-	acp_interrupt_level_4,
-
-	acp_interrupt_level_5,
-
-	acp_interrupt_level_nmi,
-
-	acp_interrupt_level_max
-} artos_interrupt_levels_t;
-
-/* brief Tensilica  timer control */
-typedef enum {
-	acp_timer_cntl_disable = 0,
-
-	acp_timer_cntl_oneshot,
-
-	acp_timer_cntl_periodic,
-
-	acp_timer_cntl_max
-} artos_timer_control_t;
-
-/* Disable Host to DSP interrupt */
-void acp_dsp_sw_intr_disable(void);
-
-void acp_intr_route(void);
-
-void acp_dsp_to_host_intr_trig(void);
-
-void acp_ack_intr_from_host(void);
-
-void acp_dsp_sw_intr_enable(void);
-
-void acp_intr_enable(void);
-
-void acp_intr_disable(void);
-
-#endif /* __PLATFORM_DRIVERS_INTERRUPT_H__ */
-
-#else
-
-#error "This file shouldn't be included from outside of sof/drivers/interrupt.h"
-
-#endif /* __SOF_DRIVERS_INTERRUPT_H__ */
diff --git a/src/platform/amd/acp_6_3/include/platform/fw_scratch_mem.h b/src/platform/amd/acp_6_3/include/platform/fw_scratch_mem.h
deleted file mode 100644
index 9f77a7d33383..000000000000
--- a/src/platform/amd/acp_6_3/include/platform/fw_scratch_mem.h
+++ /dev/null
@@ -1,120 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- *
- *  Copyright(c) 2023 AMD. All rights reserved.
- *
- *  Author: Basavaraj Hiregoudar <basavaraj.hiregoudar@amd.com>
- *          SaiSurya, Ch <saisurya.chakkaveeravenkatanaga@amd.com>
- */
-#ifndef __EXT_SCRATCH_MEM_H__
-#define __EXT_SCRATCH_MEM_H__
-
-#include <sof/lib/mailbox.h>
-
-/* MAX number of DMA descriptors */
-#define MAX_NUM_DMA_DESC_DSCR	64
-#define SCRATCH_REG_OFFSET	0x1250000
-#define ACP_SRAM  0x03800000
-typedef struct acp_atu_grp_pte {
-	uint32_t low_part;
-	uint32_t high_part;
-} __attribute__((packed, aligned(4))) acp_atu_grp_pte_t;
-
-typedef union acp_cfg_dma_trns_cnt {
-	struct{
-		uint32_t  trns_cnt : 19;
-		uint32_t  reserved : 12;
-		uint32_t  ioc : 1;
-	} bits;
-	unsigned int    u32all;
-} __attribute__((packed, aligned(4))) acp_cfg_dma_trns_cnt_t;
-
-typedef struct acp_config_dma_descriptor {
-	uint32_t	src_addr;
-	uint32_t	dest_addr;
-	acp_cfg_dma_trns_cnt_t	trns_cnt;
-	uint32_t	reserved;
-} __attribute__((packed, aligned(4))) acp_cfg_dma_descriptor_t;
-
-typedef struct acp_config_dma_misc {
-	uint32_t	channelstatus;
-	uint32_t	channel;
-	uint32_t	flag;
-} __attribute__((packed, aligned(4))) acp_cfg_dma_misc_t;
-
-typedef struct  acp_scratch_memory_config {
-	/* ACP out box buffer */
-	uint8_t				acp_outbox_buffer[MAILBOX_DSPBOX_SIZE];
-
-	/* ACP in box buffer */
-	uint8_t				acp_inbox_buffer[MAILBOX_HOSTBOX_SIZE];
-
-	/* ACP debug box buffer */
-	uint8_t				acp_debug_buffer[MAILBOX_DEBUG_SIZE];
-
-	/* ACP exception box buffer */
-	uint8_t				acp_except_buffer[MAILBOX_EXCEPTION_SIZE];
-
-	/* ACP stream buffer */
-	uint8_t				acp_stream_buffer[MAILBOX_STREAM_SIZE];
-
-	/* ACP trace buffer */
-	uint8_t				acp_trace_buffer[MAILBOX_TRACE_SIZE];
-
-	/* Host msg write flag */
-	uint32_t			acp_host_msg_write;
-
-	/* Host ack flag */
-	uint32_t			acp_host_ack_write;
-
-	/* Dsp msg write flag */
-	uint32_t			acp_dsp_msg_write;
-
-	/* Dsp ack flag */
-	uint32_t			acp_dsp_ack_write;
-
-	/* ACP pte1 table */
-	acp_atu_grp_pte_t		acp_atugrp1_pte[16];
-
-	/* ACP pte2 table */
-	acp_atu_grp_pte_t		acp_atugrp2_pte[16];
-
-	/* ACP pte3 table */
-	acp_atu_grp_pte_t		acp_atugrp3_pte[16];
-
-	/* ACP pte4 table */
-	acp_atu_grp_pte_t		acp_atugrp4_pte[16];
-
-	/* ACP pte5 table */
-	acp_atu_grp_pte_t		acp_atugrp5_pte[16];
-
-	/* ACP pte6 table */
-	acp_atu_grp_pte_t		acp_atugrp6_pte[16];
-
-	/* ACP pte7 table */
-	acp_atu_grp_pte_t		acp_atugrp7_pte[16];
-
-	/* ACP pte8 table */
-	acp_atu_grp_pte_t		acp_atugrp8_pte[16];
-
-	/* ACP DMA Descriptor */
-	acp_cfg_dma_descriptor_t	acp_cfg_dma_descriptor[MAX_NUM_DMA_DESC_DSCR];
-
-	/* Stream physical offset  */
-	uint32_t			phy_offset[8];
-
-	/* Stream system memory size */
-	uint32_t			syst_buff_size[8];
-
-	/* Fifo buffers are not part of scratch memory on ACP_6_3 */
-	/* Added fifo members to align with Driver structure */
-	/* ACP transmit fifo buffer */
-	uint8_t			acp_transmit_fifo_buffer[256] __attribute__((aligned(128)));
-
-	/* ACP receive fifo buffer */
-	uint8_t			acp_receive_fifo_buffer[256] __attribute__((aligned(128)));
-
-	uint32_t			reserve[];
-} __attribute__((packed, aligned(4))) acp_scratch_mem_config_t;
-
-#endif /* __EXT_SCRATCH_MEM_H__ */
-
diff --git a/src/platform/amd/acp_6_3/include/platform/lib/memory.h b/src/platform/amd/acp_6_3/include/platform/lib/memory.h
deleted file mode 100644
index 6c9e7c7f5b36..000000000000
--- a/src/platform/amd/acp_6_3/include/platform/lib/memory.h
+++ /dev/null
@@ -1,179 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- *
- * Copyright(c) 2023 AMD.All rights reserved.
- *
- * Author:      Basavaraj Hiregoudar <basavaraj.hiregoudar@amd.com>
- *              SaiSurya, Ch <saisurya.chakkaveeravenkatanaga@amd.com>
- */
-#ifdef __SOF_LIB_MEMORY_H__
-
-#ifndef __PLATFORM_LIB_MEMORY_H__
-#define __PLATFORM_LIB_MEMORY_H__
-
-#include <rtos/cache.h>
-#include <platform/chip_offset_byte.h>
-
-/* data cache line alignment */
-#define PLATFORM_DCACHE_ALIGN	128
-
-/* physical DSP addresses */
-#define IRAM_BASE	0x7F000000
-#define IRAM_SIZE	0x60000
-
-#define DRAM0_BASE	0xE0000000
-#define DRAM0_SIZE	0x10000
-#define SRAM0_BASE	0x9FF00000
-
-#define DRAM1_BASE      0xE0010000
-#define DRAM1_SIZE      0x10000
-#define SRAM1_BASE      0x60006000
-#define SRAM1_SIZE      0x27A000
-
-#define DMA0_BASE	PU_REGISTER_BASE
-#define DMA0_SIZE	0x4
-
-/* DAI DMA register base address */
-#define DAI_BASE		(PU_REGISTER_BASE + ACP_I2S_RX_RINGBUFADDR)
-#define DAI_BASE_REM		(PU_REGISTER_BASE + ACP_P1_I2S_RX_RINGBUFADDR)
-#define DAI_SIZE		0x4
-#define BT_TX_FIFO_OFFST	(ACP_P1_BT_TX_FIFOADDR - ACP_P1_I2S_RX_RINGBUFADDR)
-#define BT_RX_FIFO_OFFST	(ACP_P1_BT_RX_FIFOADDR - ACP_P1_I2S_RX_RINGBUFADDR)
-
-#define HS_TX_FIFO_OFFST        (ACP_P1_HS_TX_FIFOADDR - ACP_P1_I2S_RX_RINGBUFADDR)
-#define HS_RX_FIFO_OFFST        (ACP_P1_HS_TX_FIFOADDR - ACP_P1_I2S_RX_RINGBUFADDR)
-#define SW0_AUDIO_TX_FIFO_OFFST       (ACP_AUDIO_TX_FIFOADDR - ACP_AUDIO_RX_RINGBUFADDR)
-#define SW0_AUDIO_RX_FIFO_OFFST       (ACP_AUDIO_RX_FIFOADDR - ACP_AUDIO_RX_RINGBUFADDR)
-
-#define BT0_TX_FIFO_OFFST	(ACP_BT_TX_FIFOADDR - ACP_AUDIO_RX_RINGBUFADDR)
-#define BT0_RX_FIFO_OFFST	(ACP_BT_RX_FIFOADDR - ACP_AUDIO_RX_RINGBUFADDR)
-
-#define HS0_TX_FIFO_OFFST        (ACP_HS_TX_FIFOADDR - ACP_AUDIO_RX_RINGBUFADDR)
-#define HS0_RX_FIFO_OFFST        (ACP_HS_TX_FIFOADDR - ACP_AUDIO_RX_RINGBUFADDR)
-
-#define UUID_ENTRY_ELF_BASE     0x1FFFA000
-#define UUID_ENTRY_ELF_SIZE     0x6000
-
-/* Log buffer  base need to be updated properly, these are used in linker scripts */
-#define LOG_ENTRY_ELF_BASE	0x20000000
-#define LOG_ENTRY_ELF_SIZE	0x2000000
-
-#define EXT_MANIFEST_ELF_BASE   (LOG_ENTRY_ELF_BASE + LOG_ENTRY_ELF_SIZE)
-#define EXT_MANIFEST_ELF_SIZE   0x2000000
-
-/* Stack configuration */
-#define SOF_STACK_SIZE		0x1000
-#define SOF_STACK_TOTAL_SIZE	SOF_STACK_SIZE
-#define SOF_STACK_END		(DRAM1_BASE + DRAM1_SIZE - SOF_STACK_SIZE)
-#define SOF_STACK_BASE		(SOF_STACK_END + SOF_STACK_SIZE)
-
-/* Mailbox configuration */
-#define SRAM_OUTBOX_BASE		SRAM0_BASE
-#define SRAM_OUTBOX_SIZE		0x400
-#define SRAM_OUTBOX_OFFSET		0
-
-#define SRAM_INBOX_BASE			(SRAM_OUTBOX_BASE + SRAM_OUTBOX_SIZE)
-#define SRAM_INBOX_SIZE			0x400
-#define SRAM_INBOX_OFFSET		SRAM_OUTBOX_SIZE
-
-#define SRAM_DEBUG_BASE			(SRAM_INBOX_BASE + SRAM_INBOX_SIZE)
-#define SRAM_DEBUG_SIZE			0x400
-#define SRAM_DEBUG_OFFSET		(SRAM_INBOX_OFFSET + SRAM_INBOX_SIZE)
-
-#define SRAM_EXCEPT_BASE		(SRAM_DEBUG_BASE + SRAM_DEBUG_SIZE)
-#define SRAM_EXCEPT_SIZE		0x400
-#define SRAM_EXCEPT_OFFSET		(SRAM_DEBUG_OFFSET + SRAM_DEBUG_SIZE)
-
-#define SRAM_STREAM_BASE		(SRAM_EXCEPT_BASE + SRAM_EXCEPT_SIZE)
-#define SRAM_STREAM_SIZE		0x400
-#define SRAM_STREAM_OFFSET		(SRAM_EXCEPT_OFFSET + SRAM_EXCEPT_SIZE)
-
-#define SRAM_TRACE_BASE			(SRAM_STREAM_BASE + SRAM_STREAM_SIZE)
-#define SRAM_TRACE_SIZE			0x400
-#define SRAM_TRACE_OFFSET		(SRAM_STREAM_OFFSET + SRAM_STREAM_SIZE)
-#define SOF_MAILBOX_SIZE		(SRAM_INBOX_SIZE + SRAM_OUTBOX_SIZE \
-					+ SRAM_DEBUG_SIZE + SRAM_EXCEPT_SIZE \
-					+ SRAM_STREAM_SIZE + SRAM_TRACE_SIZE)
-
-/* Heap section sizes for module pool */
-#define HEAP_RT_COUNT8		0
-#define HEAP_RT_COUNT16		192
-#define HEAP_RT_COUNT32		192
-#define HEAP_RT_COUNT64		128
-#define HEAP_RT_COUNT128	240
-#define HEAP_RT_COUNT256	128
-#define HEAP_RT_COUNT512	16
-#define HEAP_RT_COUNT1024	73
-#define HEAP_RT_COUNT2048	48
-
-/* Heap section sizes for system runtime heap */
-#define HEAP_SYS_RT_COUNT64	720
-#define HEAP_SYS_RT_COUNT512	240
-#define HEAP_SYS_RT_COUNT1024	91
-
-#define SIZE_OF_MEMORY_FOR_DATA_SECTION 0x60000
-
-/* Heap configuration */
-#define HEAP_SYSTEM_BASE	(SRAM1_BASE + SIZE_OF_MEMORY_FOR_DATA_SECTION)
-#define HEAP_SYSTEM_SIZE	0x40000
-#define HEAP_SYSTEM_0_BASE	HEAP_SYSTEM_BASE
-#define HEAP_SYS_RUNTIME_BASE	(HEAP_SYSTEM_BASE + HEAP_SYSTEM_SIZE)
-#define HEAP_SYS_RUNTIME_SIZE	(HEAP_SYS_RT_COUNT64 * 64 + HEAP_SYS_RT_COUNT512 * 512 + \
-				HEAP_SYS_RT_COUNT1024 * 1024)
-
-#define HEAP_RUNTIME_BASE	(HEAP_SYS_RUNTIME_BASE + HEAP_SYS_RUNTIME_SIZE)
-#define HEAP_RUNTIME_SIZE \
-				(HEAP_RT_COUNT8 * 8 + HEAP_RT_COUNT16 * 16 + \
-				HEAP_RT_COUNT32 * 32 + HEAP_RT_COUNT64 * 64 + \
-				HEAP_RT_COUNT128 * 128 + HEAP_RT_COUNT256 * 256 + \
-				HEAP_RT_COUNT512 * 512 + HEAP_RT_COUNT1024 * 1024 + \
-				HEAP_RT_COUNT2048 * 2048)
-
-#define HEAP_BUFFER_BASE	(HEAP_RUNTIME_BASE + HEAP_RUNTIME_SIZE)
-#define HEAP_BUFFER_SIZE	(0x60000)
-#define HEAP_BUFFER_BLOCK_SIZE	0x180
-#define HEAP_BUFFER_COUNT	(HEAP_BUFFER_SIZE / HEAP_BUFFER_BLOCK_SIZE)
-
-#define PLATFORM_HEAP_SYSTEM            1
-#define PLATFORM_HEAP_SYSTEM_RUNTIME    1
-#define PLATFORM_HEAP_RUNTIME           1
-#define PLATFORM_HEAP_BUFFER		1
-
-/* Vector and literal sizes - not in core-isa.h */
-#define SOF_MEM_VECT_LIT_SIZE		0x7
-#define SOF_MEM_VECT_TEXT_SIZE		0x37
-#define SOF_MEM_VECT_SIZE		(SOF_MEM_VECT_TEXT_SIZE + SOF_MEM_VECT_LIT_SIZE)
-
-#define SOF_MEM_RESET_TEXT_SIZE		0x400
-#define SOF_MEM_RESET_LIT_SIZE		0x8
-#define SOF_MEM_VECBASE_LIT_SIZE	0x178
-#define SOF_MEM_WIN_TEXT_SIZE		0x178
-
-#define SOF_MEM_RO_SIZE			0x8
-
-#define uncache_to_cache(address)	address
-#define cache_to_uncache(address)	address
-#define is_uncached(address)			0
-
-#define HEAP_BUF_ALIGNMENT		PLATFORM_DCACHE_ALIGN
-
-/* brief EDF task's default stack size in bytes */
-#define PLATFORM_TASK_DEFAULT_STACK_SIZE        3072
-
-#if !defined(__ASSEMBLER__) && !defined(LINKER)
-struct sof;
-
-void platform_init_memmap(struct sof *sof);
-
-static inline void *platform_rfree_prepare(void *ptr)
-{
-	return ptr;
-}
-#endif
-
-#endif /* __PLATFORM_LIB_MEMORY_H__ */
-
-#else
-
-#error "This file shouldn't be included from outside of sof/lib/memory.h"
-
-#endif /* __SOF_LIB_MEMORY_H__ */
diff --git a/src/platform/amd/acp_6_3/include/platform/platform.h b/src/platform/amd/acp_6_3/include/platform/platform.h
deleted file mode 100644
index 21d77802fda7..000000000000
--- a/src/platform/amd/acp_6_3/include/platform/platform.h
+++ /dev/null
@@ -1,101 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- *
- * Copyright(c) 2023 AMD.All rights reserved.
- *
- * Author:	Basavaraj Hiregoudar <basavaraj.hiregoudar@amd.com>
- *			SaiSurya, Ch <saisurya.chakkaveeravenkatanaga@amd.com>
- */
-#ifdef __SOF_PLATFORM_H__
-
-#ifndef __PLATFORM_PLATFORM_H__
-#define __PLATFORM_PLATFORM_H__
-
-#if !defined(__ASSEMBLER__) && !defined(LINKER)
-
-#include <rtos/interrupt.h>
-#include <rtos/clk.h>
-#include <sof/lib/mailbox.h>
-#include <stddef.h>
-#include <stdint.h>
-#include <platform/fw_scratch_mem.h>
-#include <platform/chip_registers.h>
-
-struct ll_schedule_domain;
-struct timer;
-
-#define PLATFORM_DEFAULT_CLOCK CLK_CPU(0)
-
-/* IPC Interrupt */
-#define PLATFORM_IPC_INTERRUPT		IRQ_EXT_IPC_LEVEL_3
-#define PLATFORM_IPC_INTERRUPT_NAME	NULL
-
-/* Host page size */
-#define HOST_PAGE_SIZE                  65536
-
-/* pipeline IRQ */
-#define PLATFORM_SCHEDULE_IRQ		IRQ_NUM_SOFTWARE0
-#define PLATFORM_SCHEDULE_IRQ_NAME	NULL
-
-/* Platform stream capabilities */
-#define PLATFORM_MAX_CHANNELS	8
-#define PLATFORM_MAX_STREAMS	5
-
-/* local buffer size of DMA tracing */
-#define DMA_TRACE_LOCAL_SIZE	(16384 + 8192) //8192
-
-/* trace bytes flushed during panic */
-#define DMA_FLUSH_TRACE_SIZE	(MAILBOX_TRACE_SIZE >> 2)
-
-/* the interval of DMA trace copying */
-#define DMA_TRACE_PERIOD		500 //1000 //50000
-
-/*
- * the interval of reschedule DMA trace copying in special case like half
- * fullness of local DMA trace buffer
- */
-#define DMA_TRACE_RESCHEDULE_TIME	100
-
-/* DSP default delay in cycles */
-#define PLATFORM_DEFAULT_DELAY	12
-
-/* default dma trace channel */
-#define DMA_TRACE_CHANNEL	7
-
-/* debug offset */
-#define ACP_SOF_FW_STATUS	0
-
-/* Platform defined panic code */
-static inline void platform_panic(uint32_t p)
-{
-	acp_sw_intr_trig_t  sw_intr_trig;
-	volatile acp_scratch_mem_config_t *pscratch_mem_cfg =
-		(volatile acp_scratch_mem_config_t *)(PU_SCRATCH_REG_BASE + SCRATCH_REG_OFFSET);
-
-	pscratch_mem_cfg->acp_dsp_msg_write = p;
-	mailbox_sw_reg_write(ACP_SOF_FW_STATUS, p);
-	/* Read the Software Interrupt controller register and update */
-	sw_intr_trig = (acp_sw_intr_trig_t)io_reg_read(PU_REGISTER_BASE + ACP_SW_INTR_TRIG);
-	/* Configures the trigger bit in ACP_DSP_SW_INTR_TRIG register */
-	sw_intr_trig.bits.trig_dsp0_to_host_intr = INTERRUPT_ENABLE;
-	/* Write the Software Interrupt trigger register */
-	io_reg_write((PU_REGISTER_BASE + ACP_SW_INTR_TRIG), sw_intr_trig.u32all);
-}
-
-/*
- * brief Platform specific CPU entering idle.
- * May be power-optimized using platform specific capabilities.
- * @param level Interrupt level.
- */
-void platform_wait_for_interrupt(int level);
-
-extern intptr_t _module_init_start;
-extern intptr_t _module_init_end;
-#endif
-
-#endif /* __PLATFORM_PLATFORM_H__ */
-
-#else
-
-#error "This file shouldn't be included from outside of sof/platform.h"
-
-#endif /* __SOF_PLATFORM_H__ */
diff --git a/src/platform/amd/acp_6_3/lib/CMakeLists.txt b/src/platform/amd/acp_6_3/lib/CMakeLists.txt
deleted file mode 100644
index 271a099cc6a9..000000000000
--- a/src/platform/amd/acp_6_3/lib/CMakeLists.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-
-add_local_sources(sof
-	clk.c
-	dai.c
-	dma.c
-	memory.c
-)
diff --git a/src/platform/amd/acp_6_3/lib/clk.c b/src/platform/amd/acp_6_3/lib/clk.c
deleted file mode 100644
index 1c6214ea00cc..000000000000
--- a/src/platform/amd/acp_6_3/lib/clk.c
+++ /dev/null
@@ -1,494 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-//
-// Copyright(c) 2023 AMD.All rights reserved.
-//
-// Author:	Basavaraj Hiregoudar <basavaraj.hiregoudar@amd.com>
-//		Maruthi Machani <maruthi.machani@amd.com>
-//		SaiSurya, Ch <saisurya.chakkaveeravenkatanaga@amd.com>
-//
-
-#include <sof/common.h>
-#include <rtos/clk.h>
-#include <sof/lib/cpu.h>
-#include <sof/lib/memory.h>
-#include <sof/lib/notifier.h>
-#include <rtos/sof.h>
-#include <rtos/atomic.h>
-#include <sof/audio/component.h>
-#include <rtos/bit.h>
-#include <sof/drivers/acp_dai_dma.h>
-#include <rtos/interrupt.h>
-#include <rtos/timer.h>
-#include <rtos/alloc.h>
-#include <rtos/clk.h>
-#include <sof/lib/cpu.h>
-#include <sof/lib/dma.h>
-#include <sof/lib/io.h>
-#include <sof/lib/pm_runtime.h>
-#include <sof/lib/notifier.h>
-#include <sof/platform.h>
-#include <sof/schedule/schedule.h>
-#include <rtos/spinlock.h>
-#include <sof/math/numbers.h>
-#include <sof/trace/trace.h>
-#include <ipc/topology.h>
-#include <user/trace.h>
-#include <errno.h>
-#include <stdbool.h>
-#include <stddef.h>
-#include <stdint.h>
-#include <platform/fw_scratch_mem.h>
-#include <platform/chip_registers.h>
-
-SOF_DEFINE_REG_UUID(acp_clk);
-
-/* unused with Zephyr, generates no output */
-DECLARE_TR_CTX(acp_clk_tr, SOF_UUID(acp_clk_uuid), LOG_LEVEL_INFO);
-
-const struct freq_table platform_cpu_freq[] = {
-	{600000000, 600000 },
-};
-
-STATIC_ASSERT(ARRAY_SIZE(platform_cpu_freq) == NUM_CPU_FREQ,
-	      invalid_number_of_cpu_frequencies);
-
-static struct clock_info platform_clocks_info[NUM_CLOCKS];
-
-void audio_pll_power_off(void);
-void audio_pll_power_on(void);
-void clk_dfs_bypassexit(void);
-void audio_pll_mode_switch(uint32_t mode, uint32_t fcw_int, uint32_t fcw_frac, uint32_t fcw_denom,
-			   uint32_t pllspinediv);
-void clk5_init_vco(void);
-void acp_6_3_reg_wait(void);
-void acp_6_3_get_boot_ref_clock(float *boot_ref_clk);
-
-typedef enum  {
-	PLL_MODE_100MHZ_NORMAL,
-	PLL_MODE_48MHZ_NORMAL,
-	PLL_MODE_32KHZ_LPPM,
-	PLL_MODE_48MHZ_LPPM,
-	PLL_MODE_100MHZ_LPPM
-} PLL_MODE;
-
-/* Enumeration for the Clock Types */
-typedef enum _acp_clock_type_ {
-	acp_aclk_clock,
-	acp_sclk_clock,
-	acp_clock_type_max,
-	acp_clock_type_force = 0xFF
-} acp_clock_type_t;
-
-static int acp_reg_read_via_smn(uint32_t reg_offset,
-				uint32_t size)
-{
-	uint32_t reg_value;
-	uint32_t delay_cnt = 10000;
-	uint32_t smn_client_base_addr = (reg_offset >> 10);
-	uint32_t region_start_addr = (smn_client_base_addr << 10);
-	uint32_t apertureid = ((reg_offset >> 20) & 0xFFF);
-	acp_srbm_cycle_sts_t  acp_srbm_cycle_sts;
-
-	io_reg_write((PU_REGISTER_BASE + ACP_SRBM_CLIENT_CONFIG), apertureid);
-	io_reg_write((PU_REGISTER_BASE + ACP_SRBM_CLIENT_BASE_ADDR), smn_client_base_addr);
-	reg_value = (uint32_t)io_reg_read(PU_REGISTER_BASE +
-	(ACP_MASTER_REG_ACCESS_ADDRESS + reg_offset - region_start_addr + ACP_FIRST_REG_OFFSET));
-	if (reg_value)
-		reg_value = 0;
-	acp_srbm_cycle_sts = (acp_srbm_cycle_sts_t)io_reg_read(PU_REGISTER_BASE +
-							       ACP_SRBM_CYCLE_STS);
-	while (delay_cnt > 0) {
-		if (!acp_srbm_cycle_sts.bits.srbm_clients_sts)
-			return (uint32_t)io_reg_read(PU_REGISTER_BASE + ACP_SRBM_CLIENT_RDDATA);
-		acp_srbm_cycle_sts = (acp_srbm_cycle_sts_t)io_reg_read(PU_REGISTER_BASE +
-									ACP_SRBM_CYCLE_STS);
-		delay_cnt--;
-	}
-	return -1;
-}
-
-static void acp_reg_write_via_smn(uint32_t reg_offset,
-				  uint32_t value, uint32_t size)
-{
-	uint32_t	delay_cnt = 10000;
-	uint32_t        smn_client_base_addr    = (reg_offset >> 10);
-	uint32_t        region_start_addr = (smn_client_base_addr << 10);
-	uint32_t	apertureid = ((reg_offset >> 20) & 0xFFF);
-	acp_srbm_cycle_sts_t      acp_srbm_cycle_sts;
-
-	io_reg_write((PU_REGISTER_BASE + ACP_SRBM_CLIENT_CONFIG), apertureid);
-	io_reg_write((PU_REGISTER_BASE + ACP_SRBM_CLIENT_BASE_ADDR), smn_client_base_addr);
-	io_reg_write((PU_REGISTER_BASE +
-		(ACP_MASTER_REG_ACCESS_ADDRESS + reg_offset - region_start_addr +
-		 ACP_FIRST_REG_OFFSET)),
-		value);
-	acp_srbm_cycle_sts =
-		(acp_srbm_cycle_sts_t)io_reg_read(PU_REGISTER_BASE + ACP_SRBM_CYCLE_STS);
-	while (delay_cnt > 0) {
-		acp_srbm_cycle_sts = (acp_srbm_cycle_sts_t)io_reg_read(PU_REGISTER_BASE +
-								ACP_SRBM_CYCLE_STS);
-		if (!acp_srbm_cycle_sts.bits.srbm_clients_sts)
-			return;
-		delay_cnt--;
-	}
-}
-
-void acp_6_3_reg_wait(void)
-{
-	int test_count = 0;
-	int val = 0;
-
-	for (test_count = 0; test_count < 255; test_count++) {
-		val = acp_reg_read_via_smn(CLK5_CLK_FSM_STATUS, sizeof(int));
-		val = val * 0;
-	}
-}
-
-void acp_6_3_get_boot_ref_clock(float *boot_ref_clk)
-{
-	clk5_clk_pll_refclk_startup_t boot_ref_clk_startup;
-	clk5_clk_pll_req_u_t clk5_clk_pll_req;
-	clk5_spll_field_2_t clk5_spll_field;
-	uint32_t spinediv      = 1;
-	float fract_part    = 0.0f;
-	float final_refclk  = 0.0f;
-
-	boot_ref_clk_startup.u32all =
-		acp_reg_read_via_smn(CLK5_CLK_PLL_REFCLK_RATE_STARTUP, sizeof(int));
-
-	clk5_spll_field_9_t  clk_spll_field_9;
-
-	clk_spll_field_9.u32all = 0x0;
-	clk_spll_field_9.u32all = acp_reg_read_via_smn(CLK5_SPLL_FIELD_9, sizeof(int));
-
-	if (clk_spll_field_9.bitfields.spll_dpll_cfg_3 == 0x2)
-		final_refclk = ((32768.0f * 128.0f) / 1000000.0f);
-	else
-		final_refclk = (float)boot_ref_clk_startup.bitfields.main_pll_ref_clk_rate_startup;
-
-	clk5_clk_pll_req.u32all = acp_reg_read_via_smn(CLK5_CLK_PLL_REQ, sizeof(int));
-	clk5_spll_field.u32all = acp_reg_read_via_smn(CLK5_SPLL_FIELD_2, sizeof(int));
-
-	spinediv = (1 << clk5_clk_pll_req.bitfields.pllspinediv);
-
-	if (clk5_spll_field.bitfields.spll_fracn_en == 1)
-		fract_part = (float)(clk5_clk_pll_req.bitfields.fbmult_frac / (float)65536.0f);
-
-	*boot_ref_clk = (float)(((final_refclk) * (clk5_clk_pll_req.bitfields.fbmult_int +
-					fract_part)) / (float)spinediv);
-}
-
-void acp_change_clock_notify(uint32_t clock_freq)
-{
-	volatile clk5_clk1_dfs_cntl_u_t dfs_cntl;
-	volatile clk5_clk1_bypass_cntl_u_t bypass_cntl;
-	volatile clk5_clk1_dfs_status_u_t dfs_status;
-	volatile uint32_t updated_clk;
-	float did = 0.0f;
-	float fraction_val = 0.0f;
-	uint32_t int_did_val = 0;
-	float boot_ref_clk;
-	acp_clock_type_t clock_type = acp_aclk_clock;
-
-	acp_6_3_get_boot_ref_clock(&boot_ref_clk);
-
-	tr_info(&acp_clk_tr, "clock_freq : %d clock_type : %d",
-		clock_freq, clock_type);
-
-	fraction_val = (float)(clock_freq / (float)1000000.0f);
-	clock_freq   = (clock_freq / 1000000);
-	if (acp_aclk_clock == clock_type) {
-		bypass_cntl.u32all = acp_reg_read_via_smn(CLK5_CLK1_BYPASS_CNTL, sizeof(int));
-		dfs_cntl.u32all = acp_reg_read_via_smn(CLK5_CLK1_DFS_CNTL, sizeof(int));
-	} else if (acp_sclk_clock == clock_type) {
-		bypass_cntl.u32all = acp_reg_read_via_smn(CLK5_CLK0_BYPASS_CNTL, sizeof(int));
-		dfs_cntl.u32all = acp_reg_read_via_smn(CLK5_CLK0_DFS_CNTL, sizeof(int));
-	}
-
-	bypass_cntl.bitfields.CLK1_BYPASS_DIV = 0;
-
-	if (clock_freq == 6 || clock_freq == 0) {
-		did = 128;
-		dfs_cntl.bitfields.CLK1_DIVIDER = 0x7F;
-		bypass_cntl.bitfields.CLK1_BYPASS_DIV = 0xF;
-	} else {
-		did  = (float)(boot_ref_clk / (float)fraction_val);
-		tr_info(&acp_clk_tr, "CLK Divider : %d boot_ref_clk : %d\n",
-			(uint32_t)(did * 100), (uint32_t)boot_ref_clk);
-
-		if (did > 62.0f) {
-			dfs_cntl.bitfields.CLK1_DIVIDER = 0x7F;
-		} else {
-			fraction_val = did - (uint8_t)(did);
-			did = did - fraction_val;
-			if (did <= 16.00f)
-				did = (did * 4.0f);
-			else if ((did > 16.0f) && (did <= 32.0f))
-				did = ((did - 16.0f) * 2.0f + 64.0f);
-			else if ((did > 32.0f) && (did <= 62.0f))
-				did = ((did - 32.0f) + 96.0f);
-
-			int_did_val = (uint32_t)(fraction_val * 100.0f);
-			fraction_val = (float)(int_did_val / 100.0f);
-
-			if (fraction_val == 0.0f)
-				dfs_cntl.bitfields.CLK1_DIVIDER = (uint8_t)(did);
-			else if (fraction_val <= 0.25f)
-				dfs_cntl.bitfields.CLK1_DIVIDER = (uint8_t)(did) + 1;
-			else if ((fraction_val > 0.25f) && (fraction_val <= 0.5f))
-				dfs_cntl.bitfields.CLK1_DIVIDER = (uint8_t)(did) + 2;
-			else if ((fraction_val > 0.5f) && (fraction_val <= 0.75f))
-				dfs_cntl.bitfields.CLK1_DIVIDER = (uint8_t)(did) + 3;
-			else if ((fraction_val > 0.75f))
-				dfs_cntl.bitfields.CLK1_DIVIDER = (uint8_t)(did) + 4;
-		}
-	}
-
-	if (acp_aclk_clock == clock_type) {
-		acp_reg_write_via_smn(CLK5_CLK1_BYPASS_CNTL, bypass_cntl.u32all, sizeof(int));
-		acp_reg_write_via_smn(CLK5_CLK1_DFS_CNTL, dfs_cntl.u32all, sizeof(int));
-		dfs_status.u32all = acp_reg_read_via_smn(CLK5_CLK1_DFS_STATUS, sizeof(int));
-		acp_6_3_reg_wait();
-
-		do {
-			dfs_status.u32all = acp_reg_read_via_smn(CLK5_CLK1_DFS_STATUS, sizeof(int));
-			tr_info(&acp_clk_tr, "ACLK1 CLK1_DIVIDER : %d dfsstatus %d ",
-				dfs_cntl.u32all, dfs_status.u32all);
-		} while (dfs_status.bitfields.CLK1_DFS_DIV_REQ_IDLE == 0);
-		updated_clk = acp_reg_read_via_smn(CLK5_CLK1_CURRENT_CNT, sizeof(int));
-		acp_6_3_reg_wait();
-
-		if (updated_clk < (clock_freq * 10)) {
-			dfs_cntl.bitfields.CLK1_DIVIDER -= 1;
-			dfs_status.u32all               = 0;
-			acp_reg_write_via_smn(CLK5_CLK1_DFS_CNTL, dfs_cntl.u32all, sizeof(int));
-			do {
-				dfs_status.u32all =
-					acp_reg_read_via_smn(CLK5_CLK1_DFS_STATUS,
-							     sizeof(int));
-				dfs_cntl.u32all =
-					acp_reg_read_via_smn(CLK5_CLK1_DFS_CNTL,
-							     sizeof(int));
-				tr_info(&acp_clk_tr, "ACLK2 CLK1_DIVIDER:%d dfsstatus %d ",
-					dfs_cntl.u32all, dfs_status.u32all);
-			} while (dfs_status.bitfields.CLK1_DFS_DIV_REQ_IDLE == 0);
-		}
-		updated_clk = acp_reg_read_via_smn(CLK5_CLK1_CURRENT_CNT, sizeof(int));
-	} else if (acp_sclk_clock == clock_type) {
-		acp_reg_write_via_smn(CLK5_CLK0_BYPASS_CNTL, bypass_cntl.u32all, sizeof(int));
-		acp_reg_write_via_smn(CLK5_CLK0_DFS_CNTL, dfs_cntl.u32all, sizeof(int));
-		dfs_status.u32all = acp_reg_read_via_smn(CLK5_CLK0_DFS_STATUS, sizeof(int));
-		acp_6_3_reg_wait();
-
-		do {
-			dfs_status.u32all = acp_reg_read_via_smn(CLK5_CLK0_DFS_STATUS, sizeof(int));
-			tr_info(&acp_clk_tr, "SCLK CLK1_DIVIDER: %d",
-				dfs_cntl.u32all);
-		} while (dfs_status.bitfields.CLK1_DFS_DIV_REQ_IDLE == 0);
-
-		updated_clk = acp_reg_read_via_smn(CLK5_CLK0_CURRENT_CNT, sizeof(int));
-	}
-	tr_info(&acp_clk_tr,
-		"clock_notify:CLK1_DIVIDER :%x boot_ref_clk : %d ClkReq : %d FinalClockValue: %d",
-		dfs_cntl.u32all, (uint32_t)boot_ref_clk,
-		clock_freq, updated_clk);
-}
-
-void audio_pll_power_off(void)
-{
-	volatile clk5_clk_pll_pwr_req_t clk5_clk_pll_pwr_req;
-	volatile clk5_clk_fsm_status_t  clk5_clk_fsm_status;
-	int count = 0;
-
-	for (count = 0; count < 10; count++) {
-		clk5_clk_pll_pwr_req.u32all =
-			acp_reg_read_via_smn(CLK5_CLK_PLL_PWR_REQ, sizeof(int));
-		clk5_clk_pll_pwr_req.bitfields.PLL_AUTO_STOP_REQ = 1;
-
-		acp_reg_write_via_smn(CLK5_CLK_PLL_PWR_REQ,
-				      clk5_clk_pll_pwr_req.u32all, sizeof(int));
-		acp_6_3_reg_wait();
-
-		clk5_clk_fsm_status.u32all = acp_reg_read_via_smn(CLK5_CLK_FSM_STATUS, sizeof(int));
-
-		if (clk5_clk_fsm_status.bitfields.RO_FSM_PLL_STATUS_STOPPED == 1)
-			break;
-	}
-}
-
-void audio_pll_power_on(void)
-{
-	volatile clk5_clk_pll_pwr_req_t clk5_clk_pll_pwr_req;
-	volatile clk5_clk_fsm_status_t  clk5_clk_fsm_status;
-	int count = 0;
-
-	for (count = 0; count < 10; count++) {
-		clk5_clk_pll_pwr_req.u32all =
-			acp_reg_read_via_smn(CLK5_CLK_PLL_PWR_REQ, sizeof(int));
-		clk5_clk_pll_pwr_req.bitfields.PLL_AUTO_START_REQ = 1;
-
-		acp_reg_write_via_smn(CLK5_CLK_PLL_PWR_REQ,
-				      clk5_clk_pll_pwr_req.u32all,
-				      sizeof(int));
-		acp_6_3_reg_wait();
-
-		clk5_clk_fsm_status.u32all = acp_reg_read_via_smn(CLK5_CLK_FSM_STATUS, sizeof(int));
-		if (clk5_clk_fsm_status.bitfields.RO_FSM_PLL_STATUS_STARTED == 1)
-			break;
-		acp_6_3_reg_wait();
-	}
-}
-
-void clk_dfs_bypassexit(void)
-{
-	volatile clk5_clk_dfsbypass_cntl_t clk5_clk_dfsbypass_cntl;
-
-	clk5_clk_dfsbypass_cntl = (clk5_clk_dfsbypass_cntl_t)acp_reg_read_via_smn
-				(CLK5_CLK_DFSBYPASS_CONTROL, sizeof(int));
-
-	clk5_clk_dfsbypass_cntl.bitfields.exit_dfs_bypass_0 = 1;
-	clk5_clk_dfsbypass_cntl.bitfields.exit_dfs_bypass_1 = 1;
-
-	acp_reg_write_via_smn(CLK5_CLK_DFSBYPASS_CONTROL,
-			      clk5_clk_dfsbypass_cntl.u32all,
-			      sizeof(int));
-}
-
-void audio_pll_mode_switch(uint32_t mode, uint32_t fcw_int, uint32_t fcw_frac, uint32_t fcw_denom,
-			   uint32_t pllspinediv)
-{
-	volatile clk5_spll_fuse_1_t  clk_spll_fuse1;
-	volatile clk5_spll_fuse_2_t  clk_spll_fuse2;
-	volatile clk5_spll_field_9_t  clk_spll_field_9;
-	volatile clk5_spll_field_6nm_t  clk_spll_field_6nm;
-	volatile clk5_spll_field_7_t  clk_spll_field_7;
-	volatile clk5_spll_field_4_t  clk_spll_field_4;
-	volatile clk5_spll_field_5nm_bus_ctrl_t  clk_spll_field_5nm_bus_ctrl;
-	volatile clk5_spll_field_5nm_bus_wdata_t  clk_spll_field_5nm_bus_wdata;
-	volatile clk5_spll_field_5nm_bus_status_t  clk_spll_field_5nm_bus_status;
-	volatile clk5_rootrefclk_mux_1_t clk_rootrefclkmux;
-	volatile clk5_spll_field_2_t  clk5_spll_field_2;
-
-	clk_spll_fuse1.u32all = 0x0;
-	clk_spll_fuse2.u32all = 0x0;
-	clk_spll_field_9.u32all = 0x0;
-	clk_spll_field_6nm.u32all = 0x0;
-	clk_spll_field_7.u32all = 0x0;
-	clk_spll_field_4.u32all = 0x0;
-	clk_spll_field_5nm_bus_ctrl.u32all = 0x0;
-	clk_spll_field_5nm_bus_wdata.u32all = 0x0;
-	clk_spll_field_5nm_bus_status.u32all = 0x0;
-	clk5_spll_field_2 =
-		(clk5_spll_field_2_t)acp_reg_read_via_smn(CLK5_SPLL_FIELD_2, sizeof(int));
-
-	if (clk5_spll_field_2.bitfields.spll_fracn_en == 0)
-		clk5_spll_field_2.bitfields.spll_fracn_en = 1;
-	acp_reg_write_via_smn(CLK5_SPLL_FIELD_2, clk5_spll_field_2.u32all, sizeof(int));
-
-	switch (mode) {
-	case PLL_MODE_32KHZ_LPPM:
-		clk_rootrefclkmux.bitfields.ROOTREFCLK_MUX_1 = 0x0;
-		clk_rootrefclkmux.u32all = acp_reg_read_via_smn(CLK5_ROOTREFCLKMUX_1, sizeof(int));
-
-		clk_rootrefclkmux.bitfields.ROOTREFCLK_MUX_1    = 1;
-		acp_reg_write_via_smn(CLK5_ROOTREFCLKMUX_1, clk_rootrefclkmux.u32all, sizeof(int));
-
-		clk_spll_fuse1.bitfields.spll_gp_coarse_exp     = 0x5;
-		clk_spll_fuse1.bitfields.spll_gp_coarse_mant    = 0x0;
-		clk_spll_fuse1.bitfields.spll_gi_coarse_exp     = 0x7;
-		clk_spll_fuse1.bitfields.spll_gi_coarse_mant    = 0x0;
-
-		clk_spll_fuse2.bitfields.spll_tdc_resolution    = 0xe8;
-		clk_spll_fuse2.bitfields.spll_freq_offset_exp   = 0xa;
-		clk_spll_fuse2.bitfields.spll_freq_offset_mant  = 0xe;
-
-		clk_spll_field_9.bitfields.spll_dpll_cfg_3      = 2;
-		clk_spll_field_6nm.bitfields.spll_dpll_cfg_4    = 0x60;
-		clk_spll_field_6nm.bitfields.spll_vco_pre_div   = 3;
-		clk_spll_field_7.bitfields.spll_refclk_rate     = 4;
-		clk_spll_field_7.bitfields.spll_pwr_state       = 1;
-		clk_spll_field_4.bitfields.spll_refclk_div      = 0;
-
-		acp_reg_write_via_smn(CLK5_SPLL_FUSE_1, clk_spll_fuse1.u32all, sizeof(int));
-		acp_reg_write_via_smn(CLK5_SPLL_FUSE_2, clk_spll_fuse2.u32all, sizeof(int));
-		acp_reg_write_via_smn(CLK5_SPLL_FIELD_9, clk_spll_field_9.u32all, sizeof(int));
-		acp_reg_write_via_smn(CLK5_SPLL_FIELD_6nm, clk_spll_field_6nm.u32all, sizeof(int));
-		acp_reg_write_via_smn(CLK5_SPLL_FIELD_7, clk_spll_field_7.u32all, sizeof(int));
-		acp_reg_write_via_smn(CLK5_SPLL_FIELD_4, clk_spll_field_4.u32all, sizeof(int));
-
-		clk_spll_field_5nm_bus_wdata.bitfields.bus_spll_wr_data = 0x00400000;
-		acp_reg_write_via_smn(CLK5_SPLL_FIELD_5nm_BUS_WDATA,
-				      clk_spll_field_5nm_bus_wdata.u32all,
-				      sizeof(int));
-
-		clk_spll_field_5nm_bus_ctrl.u32all =
-			acp_reg_read_via_smn(CLK5_SPLL_FIELD_5nm_BUS_CTRL,
-					     sizeof(int));
-		clk_spll_field_5nm_bus_ctrl.bitfields.bus_spll_async_mode   = 1;
-		clk_spll_field_5nm_bus_ctrl.bitfields.bus_spll_apb_mode     = 0;
-		clk_spll_field_5nm_bus_ctrl.bitfields.bus_spll_addr         = 0xa;
-		clk_spll_field_5nm_bus_ctrl.bitfields.bus_spll_byte_en      = 0xf;
-		clk_spll_field_5nm_bus_ctrl.bitfields.bus_spll_rdtr         =
-					!clk_spll_field_5nm_bus_ctrl.bitfields.bus_spll_rdtr;
-		clk_spll_field_5nm_bus_ctrl.bitfields.bus_spll_resetb       = 1;
-		clk_spll_field_5nm_bus_ctrl.bitfields.bus_spll_sel          = 1;
-		clk_spll_field_5nm_bus_ctrl.bitfields.bus_spll_wrtr         = 1;
-		acp_reg_write_via_smn(CLK5_SPLL_FIELD_5nm_BUS_CTRL,
-				      clk_spll_field_5nm_bus_ctrl.u32all,
-				      sizeof(int));
-		do {
-			clk_spll_field_5nm_bus_status.u32all =
-				acp_reg_read_via_smn(CLK5_SPLL_FIELD_5nm_BUS_STATUS,
-						     sizeof(int));
-		} while (clk_spll_field_5nm_bus_status.bitfields.spll_bus_rd_valid !=
-			 clk_spll_field_5nm_bus_ctrl.bitfields.bus_spll_rdtr);
-
-		acp_reg_write_via_smn(CLK5_CLK_PLL_RESET_STOP_TIMER, 0xbbb11aa, sizeof(int));
-		break;
-	default:
-		tr_err(&acp_clk_tr, "ERROR: Invalid PLL Mode");
-		return;
-	}
-
-	clk5_clk_pll_req_u_t  clk5_clk_pll_req;
-
-	clk5_clk_pll_req.u32all = 0;
-	clk5_clk_pll_req =
-		(clk5_clk_pll_req_u_t)acp_reg_read_via_smn(CLK5_CLK_PLL_REQ, sizeof(int));
-	clk5_clk_pll_req.bitfields.fbmult_int   = fcw_int;
-
-	if (clk5_spll_field_2.bitfields.spll_fracn_en)
-		clk5_clk_pll_req.bitfields.fbmult_frac  = fcw_frac;
-	clk5_clk_pll_req.bitfields.pllspinediv  = pllspinediv;
-	acp_reg_write_via_smn(CLK5_CLK_PLL_REQ, clk5_clk_pll_req.u32all, sizeof(int));
-}
-
-void clk5_init_vco(void)
-{
-	audio_pll_power_off();
-	audio_pll_mode_switch(PLL_MODE_32KHZ_LPPM, 0x125, 0, 0, 0);
-
-	audio_pll_power_on();
-
-	clk_dfs_bypassexit();
-	acp_reg_write_via_smn(CLK5_CLK1_BYPASS_CNTL, 0, sizeof(int));
-}
-
-void platform_clock_init(struct sof *sof)
-{
-	int i = 0;
-
-	sof->clocks = platform_clocks_info;
-	for (i = 0; i < CONFIG_CORE_COUNT; i++) {
-		sof->clocks[i] = (struct clock_info) {
-			.freqs_num = NUM_CPU_FREQ,
-			.freqs = platform_cpu_freq,
-			.default_freq_idx = CPU_DEFAULT_IDX,
-			.current_freq_idx = CPU_DEFAULT_IDX,
-			.notification_id = NOTIFIER_ID_CPU_FREQ,
-			.notification_mask = NOTIFIER_TARGET_CORE_MASK(i),
-			.set_freq = NULL,
-		};
-	}
-	clk5_init_vco();
-}
diff --git a/src/platform/amd/acp_6_3/lib/dai.c b/src/platform/amd/acp_6_3/lib/dai.c
deleted file mode 100644
index c280d8a28c85..000000000000
--- a/src/platform/amd/acp_6_3/lib/dai.c
+++ /dev/null
@@ -1,296 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-//
-//Copyright(c) 2023 AMD. All rights reserved.
-//
-//Author:       Basavaraj Hiregoudar <basavaraj.hiregoudar@amd.com>
-//              SaiSurya, Ch <saisurya.chakkaveeravenkatanaga@amd.com>
-
-#include <sof/common.h>
-#include <sof/drivers/acp_dai_dma.h>
-#include <sof/lib/dai.h>
-#include <sof/lib/memory.h>
-#include <rtos/sof.h>
-#include <rtos/spinlock.h>
-#include <ipc/dai.h>
-#include <ipc/stream.h>
-
-static struct dai acp_dmic_dai[] = {
-	{
-		.index = 0,
-		.plat_data = {
-			.base = DMA0_BASE,
-			.fifo[SOF_IPC_STREAM_PLAYBACK] = {
-			.offset         = DMA0_BASE,
-			.depth          = 8,
-			.handshake      = 0,
-			},
-			.base = DMA0_BASE,
-			.fifo[SOF_IPC_STREAM_CAPTURE] = {
-			.offset		= DMA0_BASE,
-			.depth		= 8,
-			.handshake	= 1,
-			},
-		},
-		.drv = &acp_dmic_dai_driver,
-	},
-};
-
-static struct dai hsdai[] = {
-	{
-		.index = 0,
-		.plat_data = {
-			.base = DAI_BASE_REM,
-			.fifo[SOF_IPC_STREAM_PLAYBACK] = {
-			.offset         = DAI_BASE_REM + HS_TX_FIFO_OFFST,
-			.depth          = 8,
-			.handshake      = 1,
-			},
-			.fifo[SOF_IPC_STREAM_CAPTURE] = {
-			.offset         = DAI_BASE_REM + HS_RX_FIFO_OFFST,
-			.depth          = 8,
-			.handshake      = 0,
-			},
-		},
-		.drv = &acp_hsdai_driver,
-	},
-	{
-		.index = 1,
-		.plat_data = {
-			.base = DAI_BASE_REM,
-			.fifo[SOF_IPC_STREAM_PLAYBACK] = {
-			.offset         = DAI_BASE_REM + HS_TX_FIFO_OFFST,
-			.depth          = 8,
-			.handshake      = 1,
-			},
-			.fifo[SOF_IPC_STREAM_CAPTURE] = {
-			.offset         = DAI_BASE_REM + HS_RX_FIFO_OFFST,
-			.depth          = 8,
-			.handshake      = 0,
-			},
-		},
-		.drv = &acp_hsdai_driver,
-	}
-};
-
-static struct dai swaudiodai[] = {
-	{
-		.index = DI_SDW0_ACP_SW_AUDIO_TX,
-		.plat_data = {
-			.base = DAI_BASE_REM,
-			.fifo[SOF_IPC_STREAM_PLAYBACK] = {
-			.offset         = DAI_BASE_REM + SW0_AUDIO_TX_FIFO_OFFST,
-			.handshake      = SDW0_ACP_SW_AUDIO_TX_EN_CH,
-			}
-		},
-		.drv = &acp_swaudiodai_driver,
-	},
-	{
-		.index = DI_SDW0_ACP_SW_AUDIO_RX,
-		.plat_data = {
-			.base = DAI_BASE_REM,
-			.fifo[SOF_IPC_STREAM_CAPTURE] = {
-			.offset         = DAI_BASE_REM + SW0_AUDIO_RX_FIFO_OFFST,
-			.handshake      = SDW0_ACP_SW_AUDIO_RX_EN_CH,
-			},
-		},
-		.drv = &acp_swaudiodai_driver,
-	},
-	{
-		.index = DI_SDW0_ACP_SW_BT_TX,
-		.plat_data = {
-			.base = DAI_BASE_REM,
-			.fifo[SOF_IPC_STREAM_PLAYBACK] = {
-			.offset         = DAI_BASE_REM + BT0_TX_FIFO_OFFST,
-			.handshake      = SDW0_ACP_SW_BT_TX_EN_CH,
-			}
-		},
-		.drv = &acp_swaudiodai_driver,
-	},
-	{
-		.index = DI_SDW0_ACP_SW_BT_RX,
-		.plat_data = {
-			.base = DAI_BASE_REM,
-			.fifo[SOF_IPC_STREAM_CAPTURE] = {
-			.offset         = DAI_BASE_REM + BT0_RX_FIFO_OFFST,
-			.handshake      = SDW0_ACP_SW_BT_RX_EN_CH,
-			},
-		},
-		.drv = &acp_swaudiodai_driver,
-	},
-	{
-		.index = DI_SDW0_ACP_SW_HS_TX,
-		.plat_data = {
-			.base = DAI_BASE_REM,
-			.fifo[SOF_IPC_STREAM_PLAYBACK] = {
-			.offset         = DAI_BASE_REM + HS0_TX_FIFO_OFFST,
-			.handshake      = SDW0_ACP_SW_HS_TX_EN_CH,
-			}
-		},
-		.drv = &acp_swaudiodai_driver,
-	},
-	{
-		.index = DI_SDW0_ACP_SW_HS_RX,
-		.plat_data = {
-			.base = DAI_BASE_REM,
-			.fifo[SOF_IPC_STREAM_CAPTURE] = {
-			.offset         = DAI_BASE_REM + HS0_RX_FIFO_OFFST,
-			.handshake      = SDW0_ACP_SW_HS_RX_EN_CH,
-			},
-		},
-		.drv = &acp_swaudiodai_driver,
-	},
-	{
-		.index = DI_SDW1_ACP_P1_SW_BT_TX,
-		.plat_data = {
-			.base = DAI_BASE_REM,
-			.fifo[SOF_IPC_STREAM_PLAYBACK] = {
-			.offset         = DAI_BASE_REM + BT_TX_FIFO_OFFST,
-			.handshake      = SDW1_ACP_P1_SW_BT_TX_EN_CH,
-			}
-		},
-		.drv = &acp_swaudiodai_driver,
-	},
-	{
-		.index = DI_SDW1_ACP_P1_SW_BT_RX,
-		.plat_data = {
-			.base = DAI_BASE_REM,
-			.fifo[SOF_IPC_STREAM_CAPTURE] = {
-			.offset         = DAI_BASE_REM + BT_RX_FIFO_OFFST,
-			.handshake      = SDW1_ACP_P1_SW_BT_RX_EN_CH,
-			},
-		},
-		.drv = &acp_swaudiodai_driver,
-	},
-};
-
-#ifdef ACP_SP_ENABLE
-static struct dai spdai[] = {
-	{
-		.index = 0,
-		.plat_data = {
-			.base = DAI_BASE,
-			.fifo[SOF_IPC_STREAM_PLAYBACK] = {
-				.offset         = DAI_BASE + BT_TX_FIFO_OFFST,
-				.depth          = 8,
-				.handshake      = 5,
-			},
-			.fifo[SOF_IPC_STREAM_CAPTURE] = {
-				.offset         = DAI_BASE + BT_RX_FIFO_OFFST,
-				.depth          = 8,
-				.handshake      = 4,
-			},
-		},
-		.drv = &acp_spdai_driver,
-	}
-};
-
-static struct dai sp_virtual_dai[] = {
-	{
-		.index = 1,
-		.plat_data = {
-			.base = DAI_BASE,
-			.fifo[SOF_IPC_STREAM_PLAYBACK] = {
-				.offset         = DAI_BASE + BT_TX_FIFO_OFFST,
-				.depth          = 8,
-				.handshake      = 5,
-			},
-			.fifo[SOF_IPC_STREAM_CAPTURE] = {
-				.offset         = DAI_BASE + BT_RX_FIFO_OFFST,
-				.depth          = 8,
-				.handshake      = 4,
-			},
-		},
-		.drv = &acp_sp_virtual_dai_driver,
-	}
-};
-#endif
-#ifdef ACP_BT_ENABLE
-static struct dai btdai[] = {
-	{
-		.index = 0,
-		.plat_data = {
-			.base = DAI_BASE,
-			.fifo[SOF_IPC_STREAM_PLAYBACK] = {
-				.offset		= DAI_BASE + BT_TX_FIFO_OFFST,
-				.depth		= 8,
-				.handshake	= 3,
-			},
-			.fifo[SOF_IPC_STREAM_CAPTURE] = {
-				.offset		= DAI_BASE + BT_RX_FIFO_OFFST,
-				.depth		= 8,
-				.handshake	= 2,
-			},
-		},
-		.drv = &acp_btdai_driver,
-	},
-};
-#endif
-
-const struct dai_type_info dti[] = {
-	{
-		.type		= SOF_DAI_AMD_DMIC,
-		.dai_array	= acp_dmic_dai,
-		.num_dais	= ARRAY_SIZE(acp_dmic_dai)
-	},
-	{
-		.type		= SOF_DAI_AMD_HS,
-		.dai_array	= hsdai,
-		.num_dais	= ARRAY_SIZE(hsdai)
-	},
-#ifdef ACP_SP_ENABLE
-	{
-		.type		= SOF_DAI_AMD_SP,
-		.dai_array	= spdai,
-		.num_dais	= ARRAY_SIZE(spdai)
-	},
-	{
-		.type		= SOF_DAI_AMD_SP_VIRTUAL,
-		.dai_array	= sp_virtual_dai,
-		.num_dais	= ARRAY_SIZE(sp_virtual_dai)
-	},
-#endif
-#ifdef ACP_BT_ENABLE
-	{
-		.type = SOF_DAI_AMD_BT,
-		.dai_array = btdai,
-		.num_dais = ARRAY_SIZE(btdai)
-	},
-#endif
-	{
-		.type		= SOF_DAI_AMD_SW_AUDIO,
-		.dai_array	= swaudiodai,
-		.num_dais	= ARRAY_SIZE(swaudiodai)
-	},
-};
-
-const struct dai_info lib_dai = {
-	.dai_type_array = dti,
-	.num_dai_types = ARRAY_SIZE(dti)
-};
-
-int dai_init(struct sof *sof)
-{
-	int i;
-
-	/* initialize spin locks early to enable ref counting */
-	for (i = 0; i < ARRAY_SIZE(acp_dmic_dai); i++)
-		k_spinlock_init(&acp_dmic_dai[i].lock);
-	for (i = 0; i < ARRAY_SIZE(hsdai); i++)
-		k_spinlock_init(&hsdai[i].lock);
-	for (i = 0; i < ARRAY_SIZE(swaudiodai); i++)
-		k_spinlock_init(&swaudiodai[i].lock);
-#ifdef ACP_SP_ENABLE
-	for (i = 0; i < ARRAY_SIZE(spdai); i++)
-		k_spinlock_init(&spdai[i].lock);
-	/* initialize spin locks early to enable ref counting */
-	for (i = 0; i < ARRAY_SIZE(sp_virtual_dai); i++)
-		k_spinlock_init(&sp_virtual_dai[i].lock);
-#endif
-#ifdef ACP_BT_ENABLE
-	/* initialize spin locks early to enable ref counting */
-	for (i = 0; i < ARRAY_SIZE(btdai); i++)
-		k_spinlock_init(&btdai[i].lock);
-#endif
-	sof->dai_info = &lib_dai;
-	return 0;
-}
diff --git a/src/platform/amd/acp_6_3/lib/dma.c b/src/platform/amd/acp_6_3/lib/dma.c
deleted file mode 100644
index e41c081af9e9..000000000000
--- a/src/platform/amd/acp_6_3/lib/dma.c
+++ /dev/null
@@ -1,150 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-//
-//Copyright(c) 2023 AMD. All rights reserved.
-//
-//Author:       Basavaraj Hiregoudar <basavaraj.hiregoudar@amd.com>
-//              SaiSurya, Ch <saisurya.chakkaveeravenkatanaga@amd.com>
-
-#include <sof/common.h>
-#include <platform/fw_scratch_mem.h>
-#include <sof/drivers/acp_dai_dma.h>
-#include <rtos/interrupt.h>
-#include <sof/lib/dma.h>
-#include <sof/lib/memory.h>
-#include <rtos/sof.h>
-#include <rtos/spinlock.h>
-
-extern struct dma_ops acp_dma_ops;
-extern struct dma_ops acp_dmic_dma_ops;
-#ifdef ACP_BT_ENABLE
-extern struct dma_ops acp_dai_bt_dma_ops;
-#endif
-#ifdef ACP_SP_ENABLE
-extern struct dma_ops acp_dai_sp_dma_ops;
-#endif
-extern struct dma_ops acp_dai_hs_dma_ops;
-extern struct dma_ops acp_dai_sw_audio_dma_ops;
-
-struct dma dma[PLATFORM_NUM_DMACS] = {
-{
-	.plat_data = {
-		.id		= DMA_ID_DMA0,
-		.dir		= DMA_DIR_LMEM_TO_HMEM | DMA_DIR_HMEM_TO_LMEM,
-		.devs		= DMA_DEV_HOST,
-		.base		= DMA0_BASE,
-		.chan_size	= DMA0_SIZE,
-		.channels	= 8,
-		.irq		= IRQ_NUM_EXT_LEVEL5,
-		.irq_name = "irqsteer1",
-	},
-	.ops	= &acp_dma_ops,
-},
-{
-	.plat_data = {
-		.id		= DMA_ID_DAI_HS,
-		.dir		= DMA_DIR_DEV_TO_MEM | DMA_DIR_MEM_TO_DEV,
-		.devs		= DMA_DEV_SP,
-		.caps		= DMA_CAP_SP,
-		.base		= DMA0_BASE,
-		.chan_size	= DMA0_SIZE,
-		.channels	= 8,
-		.irq		= IRQ_NUM_EXT_LEVEL5,
-		.irq_name = "irqsteer1",
-	},
-	.ops = &acp_dai_hs_dma_ops,
-},
-{
-	.plat_data = {
-		.id		= DMA_ID_DAI_SW_AUDIO,
-		.dir		= DMA_DIR_DEV_TO_MEM | DMA_DIR_MEM_TO_DEV,
-		.devs		= DMA_DEV_SW,
-		.caps		= DMA_CAP_SW,
-		.base		= DMA0_BASE,
-		.chan_size	= DMA0_SIZE,
-		.channels	= 8,
-		.irq		= IRQ_NUM_EXT_LEVEL5,
-		.irq_name = "irqsteer1",
-	},
-	.ops = &acp_dai_sw_audio_dma_ops,
-},
-
-{
-	.plat_data = {
-		.id		= DMA_ID_DAI_DMIC,
-		.dir		= DMA_DIR_DEV_TO_MEM,
-		.devs		= DMA_DEV_DMIC,
-		.caps		= DMA_CAP_DMIC,
-		.base		= DMA0_BASE,
-		.chan_size	= DMA0_SIZE,
-		.channels	= 8,
-		.irq		= IRQ_NUM_EXT_LEVEL4,
-	},
-	.ops = &acp_dmic_dma_ops,
-},
-#ifdef ACP_SP_ENABLE
-{
-	.plat_data = {
-		.id		= DMA_ID_DAI_SP,
-		.dir		= DMA_DIR_DEV_TO_MEM | DMA_DIR_MEM_TO_DEV,
-		.devs		= DMA_DEV_SP,
-		.caps		= DMA_CAP_SP,
-		.base		= DMA0_BASE,
-		.chan_size	= DMA0_SIZE,
-		.channels	= 8,
-		.irq		= IRQ_NUM_EXT_LEVEL5,
-	},
-	.ops	= &acp_dai_sp_dma_ops,
-},
-{
-	.plat_data = {
-		.id		= DMA_ID_DAI_SP_VIRTUAL,
-		.dir		= DMA_DIR_DEV_TO_MEM | DMA_DIR_MEM_TO_DEV,
-		.devs		= DMA_DEV_SP_VIRTUAL,
-		.caps		= DMA_CAP_SP_VIRTUAL,
-		.base		= DMA0_BASE,
-		.chan_size	= DMA0_SIZE,
-		.channels	= 8,
-		.irq		= IRQ_NUM_EXT_LEVEL5,
-	},
-	.ops	= &acp_dai_sp_virtual_dma_ops,
-},
-#endif
-
-#ifdef ACP_BT_ENABLE
-{
-	.plat_data = {
-		.id             = DMA_ID_DAI,
-		.dir            = DMA_DIR_DEV_TO_MEM | DMA_DIR_MEM_TO_DEV,
-		.devs           = DMA_DEV_BT,
-		.caps           = DMA_CAP_BT,
-		.base           = DMA0_BASE,
-		.chan_size      = DMA0_SIZE,
-		.channels       = 8,
-		.irq            = IRQ_NUM_EXT_LEVEL5,
-	},
-	.ops    = &acp_dai_bt_dma_ops,
-},
-#endif
-};
-
-const struct dma_info lib_dma = {
-	.dma_array = dma,
-	.num_dmas = ARRAY_SIZE(dma)
-};
-
-int acp_dma_init(struct sof *sof)
-{
-	int i;
-	uint32_t descr_base;
-	volatile acp_scratch_mem_config_t *pscratch_mem_cfg =
-		(volatile acp_scratch_mem_config_t *)(PU_SCRATCH_REG_BASE + SCRATCH_REG_OFFSET);
-	descr_base = (uint32_t)(&pscratch_mem_cfg->acp_cfg_dma_descriptor);
-	descr_base = (descr_base - 0x9C700000);
-	io_reg_write((PU_REGISTER_BASE + ACP_DMA_DESC_BASE_ADDR), descr_base);
-	io_reg_write((PU_REGISTER_BASE + ACP_DMA_DESC_MAX_NUM_DSCR), 0x1);
-	/* early lock initialization for ref counting */
-	for (i = 0; i < ARRAY_SIZE(dma); i++)
-		k_spinlock_init(&dma[i].lock);
-	sof->dma_info = &lib_dma;
-	return 0;
-}
diff --git a/src/platform/amd/acp_6_3/lib/memory.c b/src/platform/amd/acp_6_3/lib/memory.c
deleted file mode 100644
index 363f110516b5..000000000000
--- a/src/platform/amd/acp_6_3/lib/memory.c
+++ /dev/null
@@ -1,95 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-//
-// Copyright 2023 AMD
-//
-// Author:Basavaraj Hiregoudar <basavaraj.hiregoudar@amd.com>
-
-#include <sof/common.h>
-#include <sof/lib/mm_heap.h>
-#include <sof/lib/memory.h>
-#include <sof/platform.h>
-#include <rtos/sof.h>
-#include <ipc/topology.h>
-
-/* Heap blocks for system runtime */
-static struct block_hdr sys_rt_block64[HEAP_SYS_RT_COUNT64];
-static struct block_hdr sys_rt_block512[HEAP_SYS_RT_COUNT512];
-static struct block_hdr sys_rt_block1024[HEAP_SYS_RT_COUNT1024];
-
-/* Heap memory for system runtime */
-static struct block_map sys_rt_heap_map[] = {
-	BLOCK_DEF(64, HEAP_SYS_RT_COUNT64, sys_rt_block64),
-	BLOCK_DEF(512, HEAP_SYS_RT_COUNT512, sys_rt_block512),
-	BLOCK_DEF(1024, HEAP_SYS_RT_COUNT1024, sys_rt_block1024),
-};
-
-/* Heap blocks for modules */
-static struct block_hdr mod_block16[HEAP_RT_COUNT16];
-static struct block_hdr mod_block32[HEAP_RT_COUNT32];
-static struct block_hdr mod_block64[HEAP_RT_COUNT64];
-static struct block_hdr mod_block128[HEAP_RT_COUNT128];
-static struct block_hdr mod_block256[HEAP_RT_COUNT256];
-static struct block_hdr mod_block512[HEAP_RT_COUNT512];
-static struct block_hdr mod_block1024[HEAP_RT_COUNT1024];
-static struct block_hdr mod_block2048[HEAP_RT_COUNT2048];
-
-/* Heap memory map for modules */
-static struct block_map rt_heap_map[] = {
-	BLOCK_DEF(16, HEAP_RT_COUNT16, mod_block16),
-	BLOCK_DEF(32, HEAP_RT_COUNT32, mod_block32),
-	BLOCK_DEF(64, HEAP_RT_COUNT64, mod_block64),
-	BLOCK_DEF(128, HEAP_RT_COUNT128, mod_block128),
-	BLOCK_DEF(256, HEAP_RT_COUNT256, mod_block256),
-	BLOCK_DEF(512, HEAP_RT_COUNT512, mod_block512),
-	BLOCK_DEF(1024, HEAP_RT_COUNT1024, mod_block1024),
-	BLOCK_DEF(2048, HEAP_RT_COUNT2048, mod_block2048),
-};
-
-/* Heap blocks for buffers */
-static struct block_hdr buf_block[HEAP_BUFFER_COUNT];
-
-/* Heap memory map for buffers */
-static struct block_map buf_heap_map[] = {
-	BLOCK_DEF(HEAP_BUFFER_BLOCK_SIZE, HEAP_BUFFER_COUNT, buf_block),
-};
-
-static struct mm memmap = {
-	.system[0] = {
-		.heap = HEAP_SYSTEM_BASE,
-		.size = HEAP_SYSTEM_SIZE,
-		.info = {.free = HEAP_SYSTEM_SIZE,},
-		.caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_DMA,
-	},
-	.system_runtime[0] = {
-		.blocks = ARRAY_SIZE(sys_rt_heap_map),
-		.map = sys_rt_heap_map,
-		.heap = HEAP_SYS_RUNTIME_BASE,
-		.size = HEAP_SYS_RUNTIME_SIZE,
-		.info = {.free = HEAP_SYS_RUNTIME_SIZE,},
-		.caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_DMA,
-	},
-	.runtime[0] = {
-		.blocks = ARRAY_SIZE(rt_heap_map),
-		.map = rt_heap_map,
-		.heap = HEAP_RUNTIME_BASE,
-		.size = HEAP_RUNTIME_SIZE,
-		.info = {.free = HEAP_RUNTIME_SIZE,},
-		.caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_DMA,
-	},
-	.buffer[0] = {
-		.blocks = ARRAY_SIZE(buf_heap_map),
-		.map = buf_heap_map,
-		.heap = HEAP_BUFFER_BASE,
-		.size = HEAP_BUFFER_SIZE,
-		.info = {.free = HEAP_BUFFER_SIZE,},
-		.caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_DMA | SOF_MEM_CAPS_CACHE | SOF_MEM_CAPS_HP,
-	},
-	.total = {.free = HEAP_SYSTEM_SIZE + HEAP_SYS_RUNTIME_SIZE +
-			HEAP_RUNTIME_SIZE + HEAP_BUFFER_SIZE,},
-};
-
-void platform_init_memmap(struct sof *sof)
-{
-	/* memmap has been initialized statically as a part of .data */
-	sof->memory_map = &memmap;
-}
diff --git a/src/platform/amd/acp_6_3/platform.c b/src/platform/amd/acp_6_3/platform.c
deleted file mode 100644
index e06cf8db0e2c..000000000000
--- a/src/platform/amd/acp_6_3/platform.c
+++ /dev/null
@@ -1,217 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-//
-//Copyright(c) 2023 AMD. All rights reserved.
-//
-//Author:       Basavaraj Hiregoudar <basavaraj.hiregoudar@amd.com>
-//              SaiSurya, Ch <saisurya.chakkaveeravenkatanaga@amd.com>
-
-#include <sof/compiler_info.h>
-#include <sof/debug/debug.h>
-#include <rtos/interrupt.h>
-#include <sof/drivers/acp_dai_dma.h>
-#include <sof/ipc/driver.h>
-#include <rtos/timer.h>
-#include <sof/fw-ready-metadata.h>
-#include <sof/lib/agent.h>
-#include <rtos/clk.h>
-#include <sof/lib/cpu.h>
-#include <sof/lib/dai.h>
-#include <sof/lib/dma.h>
-#include <sof/lib/mailbox.h>
-#include <sof/lib/memory.h>
-#include <sof/lib/mm_heap.h>
-#include <sof/platform.h>
-#include <sof/schedule/edf_schedule.h>
-#include <sof/schedule/ll_schedule.h>
-#include <sof/schedule/ll_schedule_domain.h>
-#include <rtos/sof.h>
-#include <sof/trace/dma-trace.h>
-#include <ipc/dai.h>
-#include <ipc/header.h>
-#include <ipc/info.h>
-#include <kernel/abi.h>
-#include <kernel/ext_manifest.h>
-#include <sof_versions.h>
-#include <errno.h>
-#include <stdint.h>
-#include <platform/chip_offset_byte.h>
-
-struct sof;
-static const struct sof_ipc_fw_ready ready
-	__attribute__((section(".fw_ready"))) = {
-	.hdr = {
-		.cmd = SOF_IPC_FW_READY,
-		.size = sizeof(struct sof_ipc_fw_ready),
-	},
-	/* dspbox is for DSP initiated IPC, hostbox is for host initiated IPC */
-	.version = {
-		.hdr.size = sizeof(struct sof_ipc_fw_version),
-		.micro = SOF_MICRO,
-		.minor = SOF_MINOR,
-		.major = SOF_MAJOR,
-#ifdef DEBUG_BUILD
-		/* only added in debug for reproducibility in releases */
-		.build = SOF_BUILD,
-		.date = __DATE__,
-		.time = __TIME__,
-#endif
-		.tag = SOF_TAG,
-		.abi_version = SOF_ABI_VERSION,
-	},
-	.flags = DEBUG_SET_FW_READY_FLAGS,
-};
-
-#define NUM_ACP_WINDOWS		6
-
-const struct ext_man_windows xsram_window
-#ifdef CONFIG_AMD_BINARY_BUILD
-		__aligned(EXT_MAN_ALIGN) __unused = {
-#else
-		__aligned(EXT_MAN_ALIGN) __section(".fw_metadata") __unused = {
-#endif
-	.hdr = {
-		.type = EXT_MAN_ELEM_WINDOW,
-		.elem_size = ALIGN_UP_COMPILE(sizeof(struct ext_man_windows), EXT_MAN_ALIGN),
-	},
-	.window = {
-		.ext_hdr	= {
-			.hdr.cmd = SOF_IPC_FW_READY,
-			.hdr.size = sizeof(struct sof_ipc_window),
-			.type   = SOF_IPC_EXT_WINDOW,
-		},
-		.num_windows    = NUM_ACP_WINDOWS,
-		.window = {
-			{
-				.type   = SOF_IPC_REGION_UPBOX,
-				.id     = 0,
-				.flags  = 0,
-				.size   = MAILBOX_DSPBOX_SIZE,
-				.offset = MAILBOX_DSPBOX_OFFSET,
-			},
-			{
-				.type   = SOF_IPC_REGION_DOWNBOX,
-				.id     = 0,
-				.flags  = 0,
-				.size   = MAILBOX_HOSTBOX_SIZE,
-				.offset = MAILBOX_HOSTBOX_OFFSET,
-			},
-			{
-				.type   = SOF_IPC_REGION_DEBUG,
-				.id     = 0,
-				.flags  = 0,
-				.size   = MAILBOX_DEBUG_SIZE,
-				.offset = MAILBOX_DEBUG_OFFSET,
-			},
-			{
-				.type   = SOF_IPC_REGION_TRACE,
-				.id     = 0,
-				.flags  = 0,
-				.size   = MAILBOX_TRACE_SIZE,
-				.offset = MAILBOX_TRACE_OFFSET,
-			},
-			{
-				.type   = SOF_IPC_REGION_STREAM,
-				.id     = 0,
-				.flags  = 0,
-				.size   = MAILBOX_STREAM_SIZE,
-				.offset = MAILBOX_STREAM_OFFSET,
-			},
-			{
-				.type   = SOF_IPC_REGION_EXCEPTION,
-				.id     = 0,
-				.flags  = 0,
-				.size   = MAILBOX_EXCEPTION_SIZE,
-				.offset = MAILBOX_EXCEPTION_OFFSET,
-			},
-		},
-	},
-};
-
-static struct timer timer = {
-	.id = TIMER0,
-	.irq = IRQ_NUM_TIMER0,
-};
-
-int platform_init(struct sof *sof)
-{
-	int ret;
-
-	sof->platform_timer = &timer;
-	sof->cpu_timers = &timer;
-	/* to view system memory */
-	interrupt_init(sof);
-	platform_interrupt_init();
-	platform_clock_init(sof);
-	scheduler_init_edf();
-	/* init low latency domains and schedulers */
-	/* CONFIG_SYSTICK_PERIOD set as PLATFORM_DEFAULT_CLOCK */
-	sof->platform_timer_domain =
-		timer_domain_init(sof->platform_timer, PLATFORM_DEFAULT_CLOCK);
-	scheduler_init_ll(sof->platform_timer_domain);
-	platform_timer_start(sof->platform_timer);
-	/*CONFIG_SYSTICK_PERIOD hardcoded as 200000*/
-	sa_init(sof, 200000);
-	clock_set_freq(CLK_CPU(cpu_get_id()), CLK_MAX_CPU_HZ);
-	/* init DMA */
-	ret = acp_dma_init(sof);
-	if (ret < 0)
-		return -ENODEV;
-	/* Init DMA platform domain */
-	sof->platform_dma_domain =
-		dma_multi_chan_domain_init(&sof->dma_info->dma_array[0],
-					   sizeof(sof->dma_info->dma_array),
-					   PLATFORM_DEFAULT_CLOCK, true);
-	sof->platform_dma_domain->full_sync = true;
-	scheduler_init_ll(sof->platform_dma_domain);
-	/* initialize the host IPC mechanisms */
-	ipc_init(sof);
-	/* initialize the DAI mechanisms */
-	ret = dai_init(sof);
-	if (ret < 0)
-		return -ENODEV;
-#if CONFIG_TRACE
-	/* Initialize DMA for Trace*/
-	trace_point(TRACE_BOOT_PLATFORM_DMA_TRACE);
-	sof->dmat->config.elem_array.elems =
-		rzalloc(SOF_MEM_FLAG_KERNEL,
-			sizeof(struct dma_sg_elem) * 1);
-	sof->dmat->config.elem_array.count = 1;
-	sof->dmat->config.elem_array.elems->dest = 0x03800000;
-	sof->dmat->config.elem_array.elems->size = 65536;
-	sof->dmat->config.scatter = 0;
-	dma_trace_init_complete(sof->dmat);
-#endif
-	/* show heap status */
-	heap_trace_all(1);
-	return 0;
-}
-
-int platform_boot_complete(uint32_t boot_message)
-{
-	acp_sw_intr_trig_t  swintrtrig;
-
-	volatile acp_scratch_mem_config_t *pscratch_mem_cfg =
-		(volatile acp_scratch_mem_config_t *)(PU_SCRATCH_REG_BASE + SCRATCH_REG_OFFSET);
-	mailbox_dspbox_write(0, &ready, sizeof(ready));
-#ifdef CONFIG_AMD_BINARY_BUILD
-	mailbox_dspbox_write(sizeof(ready), &xsram_window.window, sizeof(xsram_window.window));
-#endif
-	pscratch_mem_cfg->acp_dsp_msg_write = 1;
-	acp_dsp_to_host_intr_trig();
-	/* Configures the trigger bit in ACP_DSP_SW_INTR_TRIG register */
-	swintrtrig = (acp_sw_intr_trig_t)io_reg_read(PU_REGISTER_BASE + ACP_SW_INTR_TRIG);
-	swintrtrig.bits.trig_dsp0_to_host_intr  = INTERRUPT_DISABLE;
-	io_reg_write((PU_REGISTER_BASE + ACP_SW_INTR_TRIG), swintrtrig.u32all);
-	clock_set_freq(CLK_CPU(cpu_get_id()), CLK_DEFAULT_CPU_HZ);
-	return 0;
-}
-
-int platform_context_save(struct sof *sof)
-{
-	return 0;
-}
-
-void platform_wait_for_interrupt(int level)
-{
-	arch_wait_for_interrupt(level);
-}
diff --git a/src/platform/amd/acp_7_0/CMakeLists.txt b/src/platform/amd/acp_7_0/CMakeLists.txt
deleted file mode 100644
index ec909d60035f..000000000000
--- a/src/platform/amd/acp_7_0/CMakeLists.txt
+++ /dev/null
@@ -1,5 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-
-add_subdirectory(lib)
-
-add_local_sources(sof platform.c)
diff --git a/src/platform/amd/acp_7_0/lib/CMakeLists.txt b/src/platform/amd/acp_7_0/lib/CMakeLists.txt
deleted file mode 100644
index 271a099cc6a9..000000000000
--- a/src/platform/amd/acp_7_0/lib/CMakeLists.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-
-add_local_sources(sof
-	clk.c
-	dai.c
-	dma.c
-	memory.c
-)
diff --git a/src/platform/amd/acp_7_0/lib/dai.c b/src/platform/amd/acp_7_0/lib/dai.c
deleted file mode 100644
index 87c3f8f62a53..000000000000
--- a/src/platform/amd/acp_7_0/lib/dai.c
+++ /dev/null
@@ -1,340 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-//
-//Copyright(c) 2024, 2026 AMD. All rights reserved.
-//
-//Author:	SaiSurya, Ch <saisurya.chakkaveeravenkatanaga@amd.com>
-//	        Basavaraj Hiregoudar <basavaraj.hiregoudar@amd.com>
-//          Sivasubramanian <sravisar@amd.com>
-
-#include <sof/common.h>
-#include <sof/drivers/acp_dai_dma.h>
-#include <sof/lib/dai.h>
-#include <sof/lib/memory.h>
-#include <rtos/sof.h>
-#include <rtos/spinlock.h>
-#include <ipc/dai.h>
-#include <ipc/stream.h>
-
-static struct dai acp_dmic_dai[] = {
-	{
-		.index = 0,
-		.plat_data = {
-			.base = DMA0_BASE,
-			.fifo[SOF_IPC_STREAM_PLAYBACK] = {
-			.offset         = DMA0_BASE,
-			.depth          = 8,
-			.handshake      = 0,
-			},
-			.fifo[SOF_IPC_STREAM_CAPTURE] = {
-			.offset		= DMA0_BASE,
-			.depth		= 8,
-			.handshake	= 1,
-			},
-		},
-		.drv = &acp_dmic_dai_driver,
-	},
-};
-
-static struct dai hsdai[] = {
-	{
-		.index = 0,
-		.plat_data = {
-			.base = DAI_BASE_REM,
-			.fifo[SOF_IPC_STREAM_PLAYBACK] = {
-			.offset         = DAI_BASE_REM + HS_TX_FIFO_OFFST,
-			.depth          = 8,
-			.handshake      = 1,
-			},
-			.fifo[SOF_IPC_STREAM_CAPTURE] = {
-			.offset         = DAI_BASE_REM + HS_RX_FIFO_OFFST,
-			.depth          = 8,
-			.handshake      = 0,
-			},
-		},
-		.drv = &acp_hsdai_driver,
-	},
-	{
-		.index = 1,
-		.plat_data = {
-			.base = DAI_BASE_REM,
-			.fifo[SOF_IPC_STREAM_PLAYBACK] = {
-			.offset         = DAI_BASE_REM + HS_TX_FIFO_OFFST,
-			.depth          = 8,
-			.handshake      = 1,
-			},
-			.fifo[SOF_IPC_STREAM_CAPTURE] = {
-			.offset         = DAI_BASE_REM + HS_RX_FIFO_OFFST,
-			.depth          = 8,
-			.handshake      = 0,
-			},
-		},
-		.drv = &acp_hsdai_driver,
-	}
-};
-
-static struct dai swaudiodai[] = {
-	{
-		.index = DI_SDW0_ACP_SW_AUDIO_TX,
-		.plat_data = {
-			.base = DAI_BASE_REM,
-			.fifo[SOF_IPC_STREAM_PLAYBACK] = {
-			.offset         = DAI_BASE_REM + SW0_AUDIO_TX_FIFO_OFFST,
-			.handshake      = SDW0_ACP_SW_AUDIO_TX_EN_CH,
-			}
-		},
-		.drv = &acp_swaudiodai_driver,
-	},
-	{
-		.index = DI_SDW0_ACP_SW_AUDIO_RX,
-		.plat_data = {
-			.base = DAI_BASE_REM,
-			.fifo[SOF_IPC_STREAM_CAPTURE] = {
-			.offset         = DAI_BASE_REM + SW0_AUDIO_RX_FIFO_OFFST,
-			.handshake      = SDW0_ACP_SW_AUDIO_RX_EN_CH,
-			},
-		},
-		.drv = &acp_swaudiodai_driver,
-	},
-	{
-		.index = DI_SDW0_ACP_SW_BT_TX,
-		.plat_data = {
-			.base = DAI_BASE_REM,
-			.fifo[SOF_IPC_STREAM_PLAYBACK] = {
-			.offset         = DAI_BASE_REM + BT0_TX_FIFO_OFFST,
-			.handshake      = SDW0_ACP_SW_BT_TX_EN_CH,
-			}
-		},
-		.drv = &acp_swaudiodai_driver,
-	},
-	{
-		.index = DI_SDW0_ACP_SW_BT_RX,
-		.plat_data = {
-			.base = DAI_BASE_REM,
-			.fifo[SOF_IPC_STREAM_CAPTURE] = {
-			.offset         = DAI_BASE_REM + BT0_RX_FIFO_OFFST,
-			.handshake      = SDW0_ACP_SW_BT_RX_EN_CH,
-			},
-		},
-		.drv = &acp_swaudiodai_driver,
-	},
-	{
-		.index = DI_SDW0_ACP_SW_HS_TX,
-		.plat_data = {
-			.base = DAI_BASE_REM,
-			.fifo[SOF_IPC_STREAM_PLAYBACK] = {
-			.offset         = DAI_BASE_REM + HS0_TX_FIFO_OFFST,
-			.handshake      = SDW0_ACP_SW_HS_TX_EN_CH,
-			}
-		},
-		.drv = &acp_swaudiodai_driver,
-	},
-	{
-		.index = DI_SDW0_ACP_SW_HS_RX,
-		.plat_data = {
-			.base = DAI_BASE_REM,
-			.fifo[SOF_IPC_STREAM_CAPTURE] = {
-			.offset         = DAI_BASE_REM + HS0_RX_FIFO_OFFST,
-			.handshake      = SDW0_ACP_SW_HS_RX_EN_CH,
-			},
-		},
-		.drv = &acp_swaudiodai_driver,
-	},
-	{
-		.index = DI_SDW1_ACP_P1_SW_BT_TX,
-		.plat_data = {
-			.base = DAI_BASE_REM,
-			.fifo[SOF_IPC_STREAM_PLAYBACK] = {
-			.offset         = DAI_BASE_REM + BT_TX_FIFO_OFFST,
-			.handshake      = SDW1_ACP_P1_SW_BT_TX_EN_CH,
-			}
-		},
-		.drv = &acp_swaudiodai_driver,
-	},
-	{
-		.index = DI_SDW1_ACP_P1_SW_BT_RX,
-		.plat_data = {
-			.base = DAI_BASE_REM,
-			.fifo[SOF_IPC_STREAM_CAPTURE] = {
-			.offset         = DAI_BASE_REM + BT_RX_FIFO_OFFST,
-			.handshake      = SDW1_ACP_P1_SW_BT_RX_EN_CH,
-			},
-		},
-		.drv = &acp_swaudiodai_driver,
-	},
-	{
-		.index = DI_SDW1_ACP_P1_SW_AUDIO_TX,
-		.plat_data = {
-			.base = DAI_BASE_REM,
-			.fifo[SOF_IPC_STREAM_PLAYBACK] = {
-			.offset         = DAI_BASE_REM + SW1_AUDIO_TX_FIFO_OFFST,
-			.handshake      = SDW1_ACP_P1_SW_AUDIO_TX_EN_CH,
-			}
-		},
-		.drv = &acp_swaudiodai_driver,
-	},
-	{
-		.index = DI_SDW1_ACP_P1_SW_AUDIO_RX,
-		.plat_data = {
-			.base = DAI_BASE_REM,
-			.fifo[SOF_IPC_STREAM_CAPTURE] = {
-			.offset         = DAI_BASE_REM + SW1_AUDIO_RX_FIFO_OFFST,
-			.handshake      = SDW1_ACP_P1_SW_AUDIO_RX_EN_CH,
-			},
-		},
-		.drv = &acp_swaudiodai_driver,
-	},
-	{
-		.index = DI_SDW1_ACP_P1_SW_HS_TX,
-		.plat_data = {
-			.base = DAI_BASE_REM,
-			.fifo[SOF_IPC_STREAM_PLAYBACK] = {
-			.offset         = DAI_BASE_REM + SW1_HS_TX_FIFO_OFFST,
-			.handshake      = SDW1_ACP_P1_SW_HS_TX_EN_CH,
-			},
-		},
-		.drv = &acp_swaudiodai_driver,
-	},
-	{
-		.index = DI_SDW1_ACP_P1_SW_HS_RX,
-		.plat_data = {
-			.base = DAI_BASE_REM,
-			.fifo[SOF_IPC_STREAM_CAPTURE] = {
-			.offset         = DAI_BASE_REM + SW1_HS_RX_FIFO_OFFST,
-			.handshake      = SDW1_ACP_P1_SW_HS_RX_EN_CH,
-			},
-		},
-		.drv = &acp_swaudiodai_driver,
-	},
-};
-
-#ifdef ACP_SP_ENABLE
-static struct dai spdai[] = {
-	{
-		.index = 0,
-		.plat_data = {
-			.base = DAI_BASE,
-			.fifo[SOF_IPC_STREAM_PLAYBACK] = {
-				.offset         = DAI_BASE + BT_TX_FIFO_OFFST,
-				.depth          = 8,
-				.handshake      = 5,
-			},
-			.fifo[SOF_IPC_STREAM_CAPTURE] = {
-				.offset         = DAI_BASE + BT_RX_FIFO_OFFST,
-				.depth          = 8,
-				.handshake      = 4,
-			},
-		},
-		.drv = &acp_spdai_driver,
-	}
-};
-
-static struct dai sp_virtual_dai[] = {
-	{
-		.index = 1,
-		.plat_data = {
-			.base = DAI_BASE,
-			.fifo[SOF_IPC_STREAM_PLAYBACK] = {
-				.offset         = DAI_BASE + BT_TX_FIFO_OFFST,
-				.depth          = 8,
-				.handshake      = 5,
-			},
-			.fifo[SOF_IPC_STREAM_CAPTURE] = {
-				.offset         = DAI_BASE + BT_RX_FIFO_OFFST,
-				.depth          = 8,
-				.handshake      = 4,
-			},
-		},
-		.drv = &acp_sp_virtual_dai_driver,
-	}
-};
-#endif
-#ifdef ACP_BT_ENABLE
-static struct dai btdai[] = {
-	{
-		.index = 0,
-		.plat_data = {
-			.base = DAI_BASE,
-			.fifo[SOF_IPC_STREAM_PLAYBACK] = {
-				.offset		= DAI_BASE + BT_TX_FIFO_OFFST,
-				.depth		= 8,
-				.handshake	= 3,
-			},
-			.fifo[SOF_IPC_STREAM_CAPTURE] = {
-				.offset		= DAI_BASE + BT_RX_FIFO_OFFST,
-				.depth		= 8,
-				.handshake	= 2,
-			},
-		},
-		.drv = &acp_btdai_driver,
-	},
-};
-#endif
-
-const struct dai_type_info dti[] = {
-	{
-		.type		= SOF_DAI_AMD_DMIC,
-		.dai_array	= acp_dmic_dai,
-		.num_dais	= ARRAY_SIZE(acp_dmic_dai)
-	},
-	{
-		.type		= SOF_DAI_AMD_HS,
-		.dai_array	= hsdai,
-		.num_dais	= ARRAY_SIZE(hsdai)
-	},
-#ifdef ACP_SP_ENABLE
-	{
-		.type		= SOF_DAI_AMD_SP,
-		.dai_array	= spdai,
-		.num_dais	= ARRAY_SIZE(spdai)
-	},
-	{
-		.type		= SOF_DAI_AMD_SP_VIRTUAL,
-		.dai_array	= sp_virtual_dai,
-		.num_dais	= ARRAY_SIZE(sp_virtual_dai)
-	},
-#endif
-#ifdef ACP_BT_ENABLE
-	{
-		.type = SOF_DAI_AMD_BT,
-		.dai_array = btdai,
-		.num_dais = ARRAY_SIZE(btdai)
-	},
-#endif
-	{
-		.type		= SOF_DAI_AMD_SDW,
-		.dai_array	= swaudiodai,
-		.num_dais	= ARRAY_SIZE(swaudiodai)
-	},
-};
-
-const struct dai_info lib_dai = {
-	.dai_type_array = dti,
-	.num_dai_types = ARRAY_SIZE(dti)
-};
-
-int dai_init(struct sof *sof)
-{
-	int i;
-
-	/* initialize spin locks early to enable ref counting */
-	for (i = 0; i < ARRAY_SIZE(acp_dmic_dai); i++)
-		k_spinlock_init(&acp_dmic_dai[i].lock);
-	for (i = 0; i < ARRAY_SIZE(hsdai); i++)
-		k_spinlock_init(&hsdai[i].lock);
-	for (i = 0; i < ARRAY_SIZE(swaudiodai); i++)
-		k_spinlock_init(&swaudiodai[i].lock);
-#ifdef ACP_SP_ENABLE
-	for (i = 0; i < ARRAY_SIZE(spdai); i++)
-		k_spinlock_init(&spdai[i].lock);
-	/* initialize spin locks early to enable ref counting */
-	for (i = 0; i < ARRAY_SIZE(sp_virtual_dai); i++)
-		k_spinlock_init(&sp_virtual_dai[i].lock);
-#endif
-#ifdef ACP_BT_ENABLE
-	/* initialize spin locks early to enable ref counting */
-	for (i = 0; i < ARRAY_SIZE(btdai); i++)
-		k_spinlock_init(&btdai[i].lock);
-#endif
-	sof->dai_info = &lib_dai;
-	return 0;
-}
diff --git a/src/platform/amd/acp_7_0/lib/dma.c b/src/platform/amd/acp_7_0/lib/dma.c
deleted file mode 100644
index 60fb1e631b5e..000000000000
--- a/src/platform/amd/acp_7_0/lib/dma.c
+++ /dev/null
@@ -1,148 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-//
-//Copyright(c) 2024 AMD. All rights reserved.
-//
-//Author:	SaiSurya, Ch <saisurya.chakkaveeravenkatanaga@amd.com>
-
-#include <sof/common.h>
-#include <platform/fw_scratch_mem.h>
-#include <sof/drivers/acp_dai_dma.h>
-#include <rtos/interrupt.h>
-#include <sof/lib/dma.h>
-#include <sof/lib/memory.h>
-#include <rtos/sof.h>
-#include <rtos/spinlock.h>
-
-extern struct dma_ops acp_dma_ops;
-extern struct dma_ops acp_dmic_dma_ops;
-#ifdef ACP_BT_ENABLE
-extern struct dma_ops acp_dai_bt_dma_ops;
-#endif
-#ifdef ACP_SP_ENABLE
-extern struct dma_ops acp_dai_sp_dma_ops;
-#endif
-extern struct dma_ops acp_dai_hs_dma_ops;
-extern struct dma_ops acp_dai_sw_audio_dma_ops;
-
-struct dma dma[PLATFORM_NUM_DMACS] = {
-{
-	.plat_data = {
-		.id		= DMA_ID_DMA0,
-		.dir		= DMA_DIR_LMEM_TO_HMEM | DMA_DIR_HMEM_TO_LMEM,
-		.devs		= DMA_DEV_HOST,
-		.base		= DMA0_BASE,
-		.chan_size	= DMA0_SIZE,
-		.channels	= 8,
-		.irq		= IRQ_NUM_EXT_LEVEL5,
-		.irq_name = "irqsteer1",
-	},
-	.ops	= &acp_dma_ops,
-},
-{
-	.plat_data = {
-		.id		= DMA_ID_DAI_HS,
-		.dir		= DMA_DIR_DEV_TO_MEM | DMA_DIR_MEM_TO_DEV,
-		.devs		= DMA_DEV_SP,
-		.caps		= DMA_CAP_SP,
-		.base		= DMA0_BASE,
-		.chan_size	= DMA0_SIZE,
-		.channels	= 8,
-		.irq		= IRQ_NUM_EXT_LEVEL5,
-		.irq_name = "irqsteer1",
-	},
-	.ops = &acp_dai_hs_dma_ops,
-},
-{
-	.plat_data = {
-		.id		= DMA_ID_DAI_SW_AUDIO,
-		.dir		= DMA_DIR_DEV_TO_MEM | DMA_DIR_MEM_TO_DEV,
-		.devs		= DMA_DEV_SW,
-		.caps		= DMA_CAP_SW,
-		.base		= DMA0_BASE,
-		.chan_size	= DMA0_SIZE,
-		.channels	= 12,
-		.irq		= IRQ_NUM_EXT_LEVEL5,
-		.irq_name = "irqsteer1",
-	},
-	.ops = &acp_dai_sw_audio_dma_ops,
-},
-{
-	.plat_data = {
-		.id		= DMA_ID_DAI_DMIC,
-		.dir		= DMA_DIR_DEV_TO_MEM,
-		.devs		= DMA_DEV_DMIC,
-		.caps		= DMA_CAP_DMIC,
-		.base		= DMA0_BASE,
-		.chan_size	= DMA0_SIZE,
-		.channels	= 8,
-		.irq		= IRQ_NUM_EXT_LEVEL4,
-	},
-	.ops = &acp_dmic_dma_ops,
-},
-#ifdef ACP_SP_ENABLE
-{
-	.plat_data = {
-		.id		= DMA_ID_DAI_SP,
-		.dir		= DMA_DIR_DEV_TO_MEM | DMA_DIR_MEM_TO_DEV,
-		.devs		= DMA_DEV_SP,
-		.caps		= DMA_CAP_SP,
-		.base		= DMA0_BASE,
-		.chan_size	= DMA0_SIZE,
-		.channels	= 8,
-		.irq		= IRQ_NUM_EXT_LEVEL5,
-	},
-	.ops	= &acp_dai_sp_dma_ops,
-},
-{
-	.plat_data = {
-		.id		= DMA_ID_DAI_SP_VIRTUAL,
-		.dir		= DMA_DIR_DEV_TO_MEM | DMA_DIR_MEM_TO_DEV,
-		.devs		= DMA_DEV_SP_VIRTUAL,
-		.caps		= DMA_CAP_SP_VIRTUAL,
-		.base		= DMA0_BASE,
-		.chan_size	= DMA0_SIZE,
-		.channels	= 8,
-		.irq		= IRQ_NUM_EXT_LEVEL5,
-	},
-	.ops	= &acp_dai_sp_virtual_dma_ops,
-},
-#endif
-
-#ifdef ACP_BT_ENABLE
-{
-	.plat_data = {
-		.id             = DMA_ID_DAI,
-		.dir            = DMA_DIR_DEV_TO_MEM | DMA_DIR_MEM_TO_DEV,
-		.devs           = DMA_DEV_BT,
-		.caps           = DMA_CAP_BT,
-		.base           = DMA0_BASE,
-		.chan_size      = DMA0_SIZE,
-		.channels       = 8,
-		.irq            = IRQ_NUM_EXT_LEVEL5,
-	},
-	.ops    = &acp_dai_bt_dma_ops,
-},
-#endif
-};
-
-const struct dma_info lib_dma = {
-	.dma_array = dma,
-	.num_dmas = ARRAY_SIZE(dma)
-};
-
-int acp_dma_init(struct sof *sof)
-{
-	int i;
-	uint32_t descr_base;
-	volatile acp_scratch_mem_config_t *pscratch_mem_cfg =
-		(volatile acp_scratch_mem_config_t *)(PU_SCRATCH_REG_BASE + SCRATCH_REG_OFFSET);
-	descr_base = (uint32_t)(&pscratch_mem_cfg->acp_cfg_dma_descriptor);
-	descr_base = (descr_base - 0x9C700000);
-	io_reg_write((PU_REGISTER_BASE + ACP_DMA_DESC_BASE_ADDR), descr_base);
-	io_reg_write((PU_REGISTER_BASE + ACP_DMA_DESC_MAX_NUM_DSCR), 0x1);
-	/* early lock initialization for ref counting */
-	for (i = 0; i < ARRAY_SIZE(dma); i++)
-		k_spinlock_init(&dma[i].lock);
-	sof->dma_info = &lib_dma;
-	return 0;
-}
diff --git a/src/platform/amd/acp_7_0/lib/memory.c b/src/platform/amd/acp_7_0/lib/memory.c
deleted file mode 100644
index fa1caa2ae726..000000000000
--- a/src/platform/amd/acp_7_0/lib/memory.c
+++ /dev/null
@@ -1,96 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-//
-// Copyright(c) 2024 AMD. All rights reserved.
-//
-// Author:	SaiSurya, Ch <saisurya.chakkaveeravenkatanaga@amd.com>
-
-
-#include <sof/common.h>
-#include <sof/lib/mm_heap.h>
-#include <sof/lib/memory.h>
-#include <sof/platform.h>
-#include <rtos/sof.h>
-#include <ipc/topology.h>
-
-/* Heap blocks for system runtime */
-static struct block_hdr sys_rt_block64[HEAP_SYS_RT_COUNT64];
-static struct block_hdr sys_rt_block512[HEAP_SYS_RT_COUNT512];
-static struct block_hdr sys_rt_block1024[HEAP_SYS_RT_COUNT1024];
-
-/* Heap memory for system runtime */
-static struct block_map sys_rt_heap_map[] = {
-	BLOCK_DEF(64, HEAP_SYS_RT_COUNT64, sys_rt_block64),
-	BLOCK_DEF(512, HEAP_SYS_RT_COUNT512, sys_rt_block512),
-	BLOCK_DEF(1024, HEAP_SYS_RT_COUNT1024, sys_rt_block1024),
-};
-
-/* Heap blocks for modules */
-static struct block_hdr mod_block16[HEAP_RT_COUNT16];
-static struct block_hdr mod_block32[HEAP_RT_COUNT32];
-static struct block_hdr mod_block64[HEAP_RT_COUNT64];
-static struct block_hdr mod_block128[HEAP_RT_COUNT128];
-static struct block_hdr mod_block256[HEAP_RT_COUNT256];
-static struct block_hdr mod_block512[HEAP_RT_COUNT512];
-static struct block_hdr mod_block1024[HEAP_RT_COUNT1024];
-static struct block_hdr mod_block2048[HEAP_RT_COUNT2048];
-
-/* Heap memory map for modules */
-static struct block_map rt_heap_map[] = {
-	BLOCK_DEF(16, HEAP_RT_COUNT16, mod_block16),
-	BLOCK_DEF(32, HEAP_RT_COUNT32, mod_block32),
-	BLOCK_DEF(64, HEAP_RT_COUNT64, mod_block64),
-	BLOCK_DEF(128, HEAP_RT_COUNT128, mod_block128),
-	BLOCK_DEF(256, HEAP_RT_COUNT256, mod_block256),
-	BLOCK_DEF(512, HEAP_RT_COUNT512, mod_block512),
-	BLOCK_DEF(1024, HEAP_RT_COUNT1024, mod_block1024),
-	BLOCK_DEF(2048, HEAP_RT_COUNT2048, mod_block2048),
-};
-
-/* Heap blocks for buffers */
-static struct block_hdr buf_block[HEAP_BUFFER_COUNT];
-
-/* Heap memory map for buffers */
-static struct block_map buf_heap_map[] = {
-	BLOCK_DEF(HEAP_BUFFER_BLOCK_SIZE, HEAP_BUFFER_COUNT, buf_block),
-};
-
-static struct mm memmap = {
-	.system[0] = {
-		.heap = HEAP_SYSTEM_BASE,
-		.size = HEAP_SYSTEM_SIZE,
-		.info = {.free = HEAP_SYSTEM_SIZE,},
-		.caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_DMA,
-	},
-	.system_runtime[0] = {
-		.blocks = ARRAY_SIZE(sys_rt_heap_map),
-		.map = sys_rt_heap_map,
-		.heap = HEAP_SYS_RUNTIME_BASE,
-		.size = HEAP_SYS_RUNTIME_SIZE,
-		.info = {.free = HEAP_SYS_RUNTIME_SIZE,},
-		.caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_DMA,
-	},
-	.runtime[0] = {
-		.blocks = ARRAY_SIZE(rt_heap_map),
-		.map = rt_heap_map,
-		.heap = HEAP_RUNTIME_BASE,
-		.size = HEAP_RUNTIME_SIZE,
-		.info = {.free = HEAP_RUNTIME_SIZE,},
-		.caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_DMA,
-	},
-	.buffer[0] = {
-		.blocks = ARRAY_SIZE(buf_heap_map),
-		.map = buf_heap_map,
-		.heap = HEAP_BUFFER_BASE,
-		.size = HEAP_BUFFER_SIZE,
-		.info = {.free = HEAP_BUFFER_SIZE,},
-		.caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_DMA | SOF_MEM_CAPS_CACHE | SOF_MEM_CAPS_HP,
-	},
-	.total = {.free = HEAP_SYSTEM_SIZE + HEAP_SYS_RUNTIME_SIZE +
-			HEAP_RUNTIME_SIZE + HEAP_BUFFER_SIZE,},
-};
-
-void platform_init_memmap(struct sof *sof)
-{
-	/* memmap has been initialized statically as a part of .data */
-	sof->memory_map = &memmap;
-}
diff --git a/src/platform/amd/acp_7_x/CMakeLists.txt b/src/platform/amd/acp_7_x/CMakeLists.txt
deleted file mode 100644
index 3108ac12f8db..000000000000
--- a/src/platform/amd/acp_7_x/CMakeLists.txt
+++ /dev/null
@@ -1,4 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-
-add_subdirectory(lib)
-add_local_sources(sof platform.c)
diff --git a/src/platform/amd/acp_7_x/lib/CMakeLists.txt b/src/platform/amd/acp_7_x/lib/CMakeLists.txt
deleted file mode 100644
index 147d9d9bea93..000000000000
--- a/src/platform/amd/acp_7_x/lib/CMakeLists.txt
+++ /dev/null
@@ -1,5 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-
-add_local_sources(sof
-	clk.c
-)
diff --git a/src/platform/amd/common/CMakeLists.txt b/src/platform/amd/common/CMakeLists.txt
deleted file mode 100644
index fe55f14509aa..000000000000
--- a/src/platform/amd/common/CMakeLists.txt
+++ /dev/null
@@ -1,3 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-
-add_local_sources(sof)
diff --git a/src/platform/amd/rembrandt/CMakeLists.txt b/src/platform/amd/rembrandt/CMakeLists.txt
deleted file mode 100644
index ec909d60035f..000000000000
--- a/src/platform/amd/rembrandt/CMakeLists.txt
+++ /dev/null
@@ -1,5 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-
-add_subdirectory(lib)
-
-add_local_sources(sof platform.c)
diff --git a/src/platform/amd/rembrandt/lib/CMakeLists.txt b/src/platform/amd/rembrandt/lib/CMakeLists.txt
deleted file mode 100644
index 163fe4463158..000000000000
--- a/src/platform/amd/rembrandt/lib/CMakeLists.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-
-add_local_sources(sof
-	clk.c
-	dai.c
-	dma.c
-)
diff --git a/src/platform/amd/renoir/CMakeLists.txt b/src/platform/amd/renoir/CMakeLists.txt
deleted file mode 100644
index ec909d60035f..000000000000
--- a/src/platform/amd/renoir/CMakeLists.txt
+++ /dev/null
@@ -1,5 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-
-add_subdirectory(lib)
-
-add_local_sources(sof platform.c)
diff --git a/src/platform/amd/renoir/include/arch/xtensa/config/core-isa.h b/src/platform/amd/renoir/include/arch/xtensa/config/core-isa.h
deleted file mode 100644
index d620328c2b4b..000000000000
--- a/src/platform/amd/renoir/include/arch/xtensa/config/core-isa.h
+++ /dev/null
@@ -1,534 +0,0 @@
-/* 
- * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
- *				processor CORE configuration
- *
- *  See <xtensa/config/core.h>, which includes this file, for more details.
- */
-
-/* Xtensa processor core configuration information.
-
-   Customer ID=12153; Build=0x72343; Copyright (c) 1999-2018 Tensilica Inc.
-
-   Permission is hereby granted, free of charge, to any person obtaining
-   a copy of this software and associated documentation files (the
-   "Software"), to deal in the Software without restriction, including
-   without limitation the rights to use, copy, modify, merge, publish,
-   distribute, sublicense, and/or sell copies of the Software, and to
-   permit persons to whom the Software is furnished to do so, subject to
-   the following conditions:
-
-   The above copyright notice and this permission notice shall be included
-   in all copies or substantial portions of the Software.
-
-   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
-
-#ifndef _XTENSA_CORE_CONFIGURATION_H
-#define _XTENSA_CORE_CONFIGURATION_H
-
-
-/****************************************************************************
-	    Parameters Useful for Any Code, USER or PRIVILEGED
- ****************************************************************************/
-
-/*
- *  Note:  Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
- *  configured, and a value of 0 otherwise.  These macros are always defined.
- */
-
-
-/*----------------------------------------------------------------------
-				ISA
-  ----------------------------------------------------------------------*/
-
-#define XCHAL_HAVE_BE			0	/* big-endian byte ordering */
-#define XCHAL_HAVE_WINDOWED		1	/* windowed registers option */
-#define XCHAL_NUM_AREGS			32	/* num of physical addr regs */
-#define XCHAL_NUM_AREGS_LOG2		5	/* log2(XCHAL_NUM_AREGS) */
-#define XCHAL_MAX_INSTRUCTION_SIZE	8	/* max instr bytes (3..8) */
-#define XCHAL_HAVE_DEBUG		1	/* debug option */
-#define XCHAL_HAVE_DENSITY		1	/* 16-bit instructions */
-#define XCHAL_HAVE_LOOPS		1	/* zero-overhead loops */
-#define XCHAL_LOOP_BUFFER_SIZE		0	/* zero-ov. loop instr buffer size */
-#define XCHAL_HAVE_NSA			1	/* NSA/NSAU instructions */
-#define XCHAL_HAVE_MINMAX		1	/* MIN/MAX instructions */
-#define XCHAL_HAVE_SEXT			1	/* SEXT instruction */
-#define XCHAL_HAVE_DEPBITS		0	/* DEPBITS instruction */
-#define XCHAL_HAVE_CLAMPS		1	/* CLAMPS instruction */
-#define XCHAL_HAVE_MUL16		1	/* MUL16S/MUL16U instructions */
-#define XCHAL_HAVE_MUL32		1	/* MULL instruction */
-#define XCHAL_HAVE_MUL32_HIGH		1	/* MULUH/MULSH instructions */
-#define XCHAL_HAVE_DIV32		1	/* QUOS/QUOU/REMS/REMU instructions */
-#define XCHAL_HAVE_L32R			1	/* L32R instruction */
-#define XCHAL_HAVE_ABSOLUTE_LITERALS	0	/* non-PC-rel (extended) L32R */
-#define XCHAL_HAVE_CONST16		0	/* CONST16 instruction */
-#define XCHAL_HAVE_ADDX			1	/* ADDX#/SUBX# instructions */
-#define XCHAL_HAVE_WIDE_BRANCHES	0	/* B*.W18 or B*.W15 instr's */
-#define XCHAL_HAVE_PREDICTED_BRANCHES	0	/* B[EQ/EQZ/NE/NEZ]T instr's */
-#define XCHAL_HAVE_CALL4AND12		1	/* (obsolete option) */
-#define XCHAL_HAVE_ABS			1	/* ABS instruction */
-/*#define XCHAL_HAVE_POPC		0*/	/* POPC instruction */
-/*#define XCHAL_HAVE_CRC		0*/	/* CRC instruction */
-#define XCHAL_HAVE_RELEASE_SYNC		1	/* L32AI/S32RI instructions */
-#define XCHAL_HAVE_S32C1I		1	/* S32C1I instruction */
-#define XCHAL_HAVE_SPECULATION		0	/* speculation */
-#define XCHAL_HAVE_FULL_RESET		1	/* all regs/state reset */
-#define XCHAL_NUM_CONTEXTS		1	/* */
-#define XCHAL_NUM_MISC_REGS		2	/* num of scratch regs (0..4) */
-#define XCHAL_HAVE_TAP_MASTER		0	/* JTAG TAP control instr's */
-#define XCHAL_HAVE_PRID			1	/* processor ID register */
-#define XCHAL_HAVE_EXTERN_REGS		1	/* WER/RER instructions */
-#define XCHAL_HAVE_MX			0	/* MX core (Tensilica internal) */
-#define XCHAL_HAVE_MP_INTERRUPTS	0	/* interrupt distributor port */
-#define XCHAL_HAVE_MP_RUNSTALL		0	/* core RunStall control port */
-#define XCHAL_HAVE_PSO			0	/* Power Shut-Off */
-#define XCHAL_HAVE_PSO_CDM		0	/* core/debug/mem pwr domains */
-#define XCHAL_HAVE_PSO_FULL_RETENTION	0	/* all regs preserved on PSO */
-#define XCHAL_HAVE_THREADPTR		1	/* THREADPTR register */
-#define XCHAL_HAVE_BOOLEANS		1	/* boolean registers */
-#define XCHAL_HAVE_CP			1	/* CPENABLE reg (coprocessor) */
-#define XCHAL_CP_MAXCFG			2	/* max allowed cp id plus one */
-#define XCHAL_HAVE_MAC16		1	/* MAC16 package */
-
-#define XCHAL_HAVE_FUSION		 0	/* Fusion*/
-#define XCHAL_HAVE_FUSION_FP	 0	        /* Fusion FP option */
-#define XCHAL_HAVE_FUSION_LOW_POWER 0	/* Fusion Low Power option */
-#define XCHAL_HAVE_FUSION_AES	 0	        /* Fusion BLE/Wifi AES-128 CCM option */
-#define XCHAL_HAVE_FUSION_CONVENC	 0       /* Fusion Conv Encode option */
-#define XCHAL_HAVE_FUSION_LFSR_CRC	 0	/* Fusion LFSR-CRC option */
-#define XCHAL_HAVE_FUSION_BITOPS	 0	/* Fusion Bit Operations Support option */
-#define XCHAL_HAVE_FUSION_AVS	 0	/* Fusion AVS option */
-#define XCHAL_HAVE_FUSION_16BIT_BASEBAND	 0	/* Fusion 16-bit Baseband option */
-#define XCHAL_HAVE_FUSION_VITERBI        0     /* Fusion Viterbi option */
-#define XCHAL_HAVE_FUSION_SOFTDEMAP      0   /* Fusion Soft Bit Demap option */
-#define XCHAL_HAVE_HIFIPRO		0	/* HiFiPro Audio Engine pkg */
-#define XCHAL_HAVE_HIFI4		0	/* HiFi4 Audio Engine pkg */
-#define XCHAL_HAVE_HIFI4_VFPU		0	/* HiFi4 Audio Engine VFPU option */
-#define XCHAL_HAVE_HIFI3		1	/* HiFi3 Audio Engine pkg */
-#define XCHAL_HAVE_HIFI3_VFPU		0	/* HiFi3 Audio Engine VFPU option */
-#define XCHAL_HAVE_HIFI2		0	/* HiFi2 Audio Engine pkg */
-#define XCHAL_HAVE_HIFI2EP		0	/* HiFi2EP */
-#define XCHAL_HAVE_HIFI_MINI		0	
-
-
-#define XCHAL_HAVE_VECTORFPU2005	0	/* vector or user floating-point pkg */
-#define XCHAL_HAVE_USER_DPFPU         0       /* user DP floating-point pkg */
-#define XCHAL_HAVE_USER_SPFPU         0       /* user DP floating-point pkg */
-#define XCHAL_HAVE_FP                 1      /* single prec floating point */
-#define XCHAL_HAVE_FP_DIV             1  /* FP with DIV instructions */
-#define XCHAL_HAVE_FP_RECIP           1        /* FP with RECIP instructions */
-#define XCHAL_HAVE_FP_SQRT            1 /* FP with SQRT instructions */
-#define XCHAL_HAVE_FP_RSQRT           1        /* FP with RSQRT instructions */
-#define XCHAL_HAVE_DFP                        1     /* double precision FP pkg */
-#define XCHAL_HAVE_DFP_DIV            1 /* DFP with DIV instructions */
-#define XCHAL_HAVE_DFP_RECIP          1       /* DFP with RECIP instructions*/
-#define XCHAL_HAVE_DFP_SQRT           1        /* DFP with SQRT instructions */
-#define XCHAL_HAVE_DFP_RSQRT          1       /* DFP with RSQRT instructions*/
-#define XCHAL_HAVE_DFP_ACCEL		0	/* double precision FP acceleration pkg */
-#define XCHAL_HAVE_DFP_accel		XCHAL_HAVE_DFP_ACCEL				/* for backward compatibility */
-
-#define XCHAL_HAVE_DFPU_SINGLE_ONLY    0                 	/* DFPU Coprocessor, single precision only */
-#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE  1               	/* DFPU Coprocessor, single and double precision */
-#define XCHAL_HAVE_VECTRA1		0	/* Vectra I  pkg */
-#define XCHAL_HAVE_VECTRALX		0	/* Vectra LX pkg */
-#define XCHAL_HAVE_PDX4		        0	/* PDX4 */
-#define XCHAL_HAVE_CONNXD2		0	/* ConnX D2 pkg */
-#define XCHAL_HAVE_CONNXD2_DUALLSFLIX   0	/* ConnX D2 & Dual LoadStore Flix */
-#define XCHAL_HAVE_BBE16		0	/* ConnX BBE16 pkg */
-#define XCHAL_HAVE_BBE16_RSQRT		0	/* BBE16 & vector recip sqrt */
-#define XCHAL_HAVE_BBE16_VECDIV		0	/* BBE16 & vector divide */
-#define XCHAL_HAVE_BBE16_DESPREAD	0	/* BBE16 & despread */
-#define XCHAL_HAVE_BBENEP		0	/* ConnX BBENEP pkgs */
-#define XCHAL_HAVE_BSP3			0	/* ConnX BSP3 pkg */
-#define XCHAL_HAVE_BSP3_TRANSPOSE	0	/* BSP3 & transpose32x32 */
-#define XCHAL_HAVE_SSP16		0	/* ConnX SSP16 pkg */
-#define XCHAL_HAVE_SSP16_VITERBI	0	/* SSP16 & viterbi */
-#define XCHAL_HAVE_TURBO16		0	/* ConnX Turbo16 pkg */
-#define XCHAL_HAVE_BBP16		0	/* ConnX BBP16 pkg */
-#define XCHAL_HAVE_FLIX3		0	/* basic 3-way FLIX option */
-#define XCHAL_HAVE_GRIVPEP              0   /*  GRIVPEP is General Release of IVPEP */
-#define XCHAL_HAVE_GRIVPEP_HISTOGRAM    0   /* Histogram option on GRIVPEP */
-
-
-/*----------------------------------------------------------------------
-				MISC
-  ----------------------------------------------------------------------*/
-
-#define XCHAL_NUM_LOADSTORE_UNITS	1	/* load/store units */
-#define XCHAL_NUM_WRITEBUFFER_ENTRIES	16	/* size of write buffer */
-#define XCHAL_INST_FETCH_WIDTH		8	/* instr-fetch width in bytes */
-#define XCHAL_DATA_WIDTH		8	/* data width in bytes */
-#define XCHAL_DATA_PIPE_DELAY		2	/* d-side pipeline delay
-						   (1 = 5-stage, 2 = 7-stage) */
-#define XCHAL_CLOCK_GATING_GLOBAL	1	/* global clock gating */
-#define XCHAL_CLOCK_GATING_FUNCUNIT	1	/* funct. unit clock gating */
-/*  In T1050, applies to selected core load and store instructions (see ISA): */
-#define XCHAL_UNALIGNED_LOAD_EXCEPTION	1	/* unaligned loads cause exc. */
-#define XCHAL_UNALIGNED_STORE_EXCEPTION	1	/* unaligned stores cause exc.*/
-#define XCHAL_UNALIGNED_LOAD_HW		0	/* unaligned loads work in hw */
-#define XCHAL_UNALIGNED_STORE_HW	0	/* unaligned stores work in hw*/
-
-#define XCHAL_SW_VERSION		1100004	/* sw version of this header */
-
-#define XCHAL_CORE_ID			"ACP_3_1_001_PROD"	/* alphanum core name
-						   (CoreID) set in the Xtensa
-						   Processor Generator */
-
-#define XCHAL_BUILD_UNIQUE_ID		0x00072343	/* 22-bit sw build ID */
-
-/*
- *  These definitions describe the hardware targeted by this software.
- */
-#define XCHAL_HW_CONFIGID0		0xC2F0CFFE	/* ConfigID hi 32 bits*/
-#define XCHAL_HW_CONFIGID1		0x1D072343	/* ConfigID lo 32 bits*/
-#define XCHAL_HW_VERSION_NAME		"LX6.0.4"	/* full version name */
-#define XCHAL_HW_VERSION_MAJOR		2600	/* major ver# of targeted hw */
-#define XCHAL_HW_VERSION_MINOR		4	/* minor ver# of targeted hw */
-#define XCHAL_HW_VERSION		260004	/* major*100+minor */
-#define XCHAL_HW_REL_LX6		1
-#define XCHAL_HW_REL_LX6_0		1
-#define XCHAL_HW_REL_LX6_0_4		1
-#define XCHAL_HW_CONFIGID_RELIABLE	1
-/*  If software targets a *range* of hardware versions, these are the bounds: */
-#define XCHAL_HW_MIN_VERSION_MAJOR	2600	/* major v of earliest tgt hw */
-#define XCHAL_HW_MIN_VERSION_MINOR	4	/* minor v of earliest tgt hw */
-#define XCHAL_HW_MIN_VERSION		260004	/* earliest targeted hw */
-#define XCHAL_HW_MAX_VERSION_MAJOR	2600	/* major v of latest tgt hw */
-#define XCHAL_HW_MAX_VERSION_MINOR	4	/* minor v of latest tgt hw */
-#define XCHAL_HW_MAX_VERSION		260004	/* latest targeted hw */
-
-
-/*----------------------------------------------------------------------
-				CACHE
-  ----------------------------------------------------------------------*/
-
-#define XCHAL_ICACHE_LINESIZE		8	/* I-cache line size in bytes */
-#define XCHAL_DCACHE_LINESIZE		8	/* D-cache line size in bytes */
-#define XCHAL_ICACHE_LINEWIDTH		3	/* log2(I line size in bytes) */
-#define XCHAL_DCACHE_LINEWIDTH		3	/* log2(D line size in bytes) */
-
-#define XCHAL_ICACHE_SIZE		0	/* I-cache size in bytes or 0 */
-#define XCHAL_DCACHE_SIZE		0	/* D-cache size in bytes or 0 */
-
-#define XCHAL_DCACHE_IS_WRITEBACK	0	/* writeback feature */
-#define XCHAL_DCACHE_IS_COHERENT	0	/* MP coherence feature */
-
-#define XCHAL_HAVE_PREFETCH		0	/* PREFCTL register */
-#define XCHAL_HAVE_PREFETCH_L1		0	/* prefetch to L1 dcache */
-#define XCHAL_PREFETCH_CASTOUT_LINES	0	/* dcache pref. castout bufsz */
-#define XCHAL_PREFETCH_ENTRIES		0	/* cache prefetch entries */
-#define XCHAL_PREFETCH_BLOCK_ENTRIES	0	/* prefetch block streams */
-#define XCHAL_HAVE_CACHE_BLOCKOPS	0	/* block prefetch for caches */
-#define XCHAL_HAVE_ICACHE_TEST		0	/* Icache test instructions */
-#define XCHAL_HAVE_DCACHE_TEST		0	/* Dcache test instructions */
-#define XCHAL_HAVE_ICACHE_DYN_WAYS	0	/* Icache dynamic way support */
-#define XCHAL_HAVE_DCACHE_DYN_WAYS	0	/* Dcache dynamic way support */
-
-
-
-
-/****************************************************************************
-    Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
- ****************************************************************************/
-
-
-#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
-
-/*----------------------------------------------------------------------
-				CACHE
-  ----------------------------------------------------------------------*/
-
-#define XCHAL_HAVE_PIF			1	/* any outbound PIF present */
-#define XCHAL_HAVE_AXI			1	/* AXI bus */
-
-#define XCHAL_HAVE_PIF_WR_RESP			1	/* pif write response */
-#define XCHAL_HAVE_PIF_REQ_ATTR			0	/* pif attribute */
-
-/*  If present, cache size in bytes == (ways * 2^(linewidth + setwidth)).  */
-
-/*  Number of cache sets in log2(lines per way):  */
-#define XCHAL_ICACHE_SETWIDTH		0
-#define XCHAL_DCACHE_SETWIDTH		0
-
-/*  Cache set associativity (number of ways):  */
-#define XCHAL_ICACHE_WAYS		1
-#define XCHAL_DCACHE_WAYS		1
-
-/*  Cache features:  */
-#define XCHAL_ICACHE_LINE_LOCKABLE	0
-#define XCHAL_DCACHE_LINE_LOCKABLE	0
-#define XCHAL_ICACHE_ECC_PARITY		0
-#define XCHAL_DCACHE_ECC_PARITY		0
-
-/*  Cache access size in bytes (affects operation of SICW instruction):  */
-#define XCHAL_ICACHE_ACCESS_SIZE	1
-#define XCHAL_DCACHE_ACCESS_SIZE	1
-
-#define XCHAL_DCACHE_BANKS		0	/* number of banks */
-
-/*  Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits):  */
-#define XCHAL_CA_BITS			4
-
-
-/*----------------------------------------------------------------------
-			INTERNAL I/D RAM/ROMs and XLMI
-  ----------------------------------------------------------------------*/
-
-#define XCHAL_NUM_INSTROM		0	/* number of core instr. ROMs */
-#define XCHAL_NUM_INSTRAM		1	/* number of core instr. RAMs */
-#define XCHAL_NUM_DATAROM		0	/* number of core data ROMs */
-#define XCHAL_NUM_DATARAM		1	/* number of core data RAMs */
-#define XCHAL_NUM_URAM			0	/* number of core unified RAMs*/
-#define XCHAL_NUM_XLMI			0	/* number of core XLMI ports */
-
-/*  Instruction RAM 0:  */
-#define XCHAL_INSTRAM0_VADDR		0x20000000	/* virtual address */
-#define XCHAL_INSTRAM0_PADDR		0x20000000	/* physical address */
-#define XCHAL_INSTRAM0_SIZE		1048576	/* size in bytes */
-#define XCHAL_INSTRAM0_ECC_PARITY	0	/* ECC/parity type, 0=none */
-
-/*  Data RAM 0:  */
-#define XCHAL_DATARAM0_VADDR		0x21000000	/* virtual address */
-#define XCHAL_DATARAM0_PADDR		0x21000000	/* physical address */
-#define XCHAL_DATARAM0_SIZE		1048576	/* size in bytes */
-#define XCHAL_DATARAM0_ECC_PARITY	0	/* ECC/parity type, 0=none */
-#define XCHAL_DATARAM0_BANKS		1	/* number of banks */
-
-#define XCHAL_HAVE_IMEM_LOADSTORE	1	/* can load/store to IROM/IRAM*/
-
-
-/*----------------------------------------------------------------------
-			INTERRUPTS and TIMERS
-  ----------------------------------------------------------------------*/
-
-#define XCHAL_HAVE_INTERRUPTS		1	/* interrupt option */
-#define XCHAL_HAVE_HIGHPRI_INTERRUPTS	1	/* med/high-pri. interrupts */
-#define XCHAL_HAVE_NMI			1	/* non-maskable interrupt */
-#define XCHAL_HAVE_CCOUNT		1	/* CCOUNT reg. (timer option) */
-#define XCHAL_NUM_TIMERS		2	/* number of CCOMPAREn regs */
-#define XCHAL_NUM_INTERRUPTS		8	/* number of interrupts */
-#define XCHAL_NUM_INTERRUPTS_LOG2	3	/* ceil(log2(NUM_INTERRUPTS)) */
-#define XCHAL_NUM_EXTINTERRUPTS		4	/* num of external interrupts */
-#define XCHAL_NUM_INTLEVELS		6	/* number of interrupt levels
-						   (not including level zero) */
-#define XCHAL_EXCM_LEVEL		5	/* level masked by PS.EXCM */
-	/* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
-
-/*  Masks of interrupts at each interrupt level:  */
-#define XCHAL_INTLEVEL1_MASK		0x00000003
-#define XCHAL_INTLEVEL2_MASK		0x00000004
-#define XCHAL_INTLEVEL3_MASK		0x00000008
-#define XCHAL_INTLEVEL4_MASK		0x00000010
-#define XCHAL_INTLEVEL5_MASK		0x00000060
-#define XCHAL_INTLEVEL6_MASK		0x00000000
-#define XCHAL_INTLEVEL7_MASK		0x00000080
-
-/*  Masks of interrupts at each range 1..n of interrupt levels:  */
-#define XCHAL_INTLEVEL1_ANDBELOW_MASK	0x00000003
-#define XCHAL_INTLEVEL2_ANDBELOW_MASK	0x00000007
-#define XCHAL_INTLEVEL3_ANDBELOW_MASK	0x0000000F
-#define XCHAL_INTLEVEL4_ANDBELOW_MASK	0x0000001F
-#define XCHAL_INTLEVEL5_ANDBELOW_MASK	0x0000007F
-#define XCHAL_INTLEVEL6_ANDBELOW_MASK	0x0000007F
-#define XCHAL_INTLEVEL7_ANDBELOW_MASK	0x000000FF
-
-/*  Level of each interrupt:  */
-#define XCHAL_INT0_LEVEL		1
-#define XCHAL_INT1_LEVEL		1
-#define XCHAL_INT2_LEVEL		2
-#define XCHAL_INT3_LEVEL		3
-#define XCHAL_INT4_LEVEL		4
-#define XCHAL_INT5_LEVEL		5
-#define XCHAL_INT6_LEVEL		5
-#define XCHAL_INT7_LEVEL		7
-#define XCHAL_DEBUGLEVEL		6	/* debug interrupt level */
-#define XCHAL_HAVE_DEBUG_EXTERN_INT	1	/* OCD external db interrupt */
-#define XCHAL_NMILEVEL			7	/* NMI "level" (for use with
-						   EXCSAVE/EPS/EPC_n, RFI n) */
-
-/*  Type of each interrupt:  */
-#define XCHAL_INT0_TYPE 	XTHAL_INTTYPE_TIMER
-#define XCHAL_INT1_TYPE 	XTHAL_INTTYPE_SOFTWARE
-#define XCHAL_INT2_TYPE 	XTHAL_INTTYPE_WRITE_ERROR
-#define XCHAL_INT3_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT4_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT5_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT6_TYPE 	XTHAL_INTTYPE_TIMER
-#define XCHAL_INT7_TYPE 	XTHAL_INTTYPE_NMI
-
-/*  Masks of interrupts for each type of interrupt:  */
-#define XCHAL_INTTYPE_MASK_UNCONFIGURED	0xFFFFFF00
-#define XCHAL_INTTYPE_MASK_SOFTWARE	0x00000002
-#define XCHAL_INTTYPE_MASK_EXTERN_EDGE	0x00000000
-#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL	0x00000038
-#define XCHAL_INTTYPE_MASK_TIMER	0x00000041
-#define XCHAL_INTTYPE_MASK_NMI		0x00000080
-#define XCHAL_INTTYPE_MASK_WRITE_ERROR	0x00000004
-#define XCHAL_INTTYPE_MASK_PROFILING	0x00000000
-
-/*  Interrupt numbers assigned to specific interrupt sources:  */
-#define XCHAL_TIMER0_INTERRUPT		0	/* CCOMPARE0 */
-#define XCHAL_TIMER1_INTERRUPT		6	/* CCOMPARE1 */
-#define XCHAL_TIMER2_INTERRUPT		XTHAL_TIMER_UNCONFIGURED
-#define XCHAL_TIMER3_INTERRUPT		XTHAL_TIMER_UNCONFIGURED
-#define XCHAL_NMI_INTERRUPT		7	/* non-maskable interrupt */
-#define XCHAL_WRITE_ERROR_INTERRUPT	2	/* write-error interrupt */
-
-/*  Interrupt numbers for levels at which only one interrupt is configured:  */
-#define XCHAL_INTLEVEL2_NUM		2
-#define XCHAL_INTLEVEL3_NUM		3
-#define XCHAL_INTLEVEL4_NUM		4
-#define XCHAL_INTLEVEL7_NUM		7
-/*  (There are many interrupts each at level(s) 1, 5.)  */
-
-
-/*
- *  External interrupt mapping.
- *  These macros describe how Xtensa processor interrupt numbers
- *  (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
- *  map to external BInterrupt<n> pins, for those interrupts
- *  configured as external (level-triggered, edge-triggered, or NMI).
- *  See the Xtensa processor databook for more details.
- */
-
-/*  Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number:  */
-#define XCHAL_EXTINT0_NUM		3	/* (intlevel 3) */
-#define XCHAL_EXTINT1_NUM		4	/* (intlevel 4) */
-#define XCHAL_EXTINT2_NUM		5	/* (intlevel 5) */
-#define XCHAL_EXTINT3_NUM		7	/* (intlevel 7) */
-/*  EXTERNAL BInterrupt pin numbers mapped to each core interrupt number:  */
-#define XCHAL_INT3_EXTNUM		0	/* (intlevel 3) */
-#define XCHAL_INT4_EXTNUM		1	/* (intlevel 4) */
-#define XCHAL_INT5_EXTNUM		2	/* (intlevel 5) */
-#define XCHAL_INT7_EXTNUM		3	/* (intlevel 7) */
-
-
-/*----------------------------------------------------------------------
-			EXCEPTIONS and VECTORS
-  ----------------------------------------------------------------------*/
-
-#define XCHAL_XEA_VERSION		2	/* Xtensa Exception Architecture
-						   number: 1 == XEA1 (old)
-							   2 == XEA2 (new)
-							   0 == XEAX (extern) or TX */
-#define XCHAL_HAVE_XEA1			0	/* Exception Architecture 1 */
-#define XCHAL_HAVE_XEA2			1	/* Exception Architecture 2 */
-#define XCHAL_HAVE_XEAX			0	/* External Exception Arch. */
-#define XCHAL_HAVE_EXCEPTIONS		1	/* exception option */
-#define XCHAL_HAVE_HALT			0	/* halt architecture option */
-#define XCHAL_HAVE_BOOTLOADER		0	/* boot loader (for TX) */
-#define XCHAL_HAVE_MEM_ECC_PARITY	0	/* local memory ECC/parity */
-#define XCHAL_HAVE_VECTOR_SELECT	1	/* relocatable vectors */
-#define XCHAL_HAVE_VECBASE		1	/* relocatable vectors */
-#define XCHAL_VECBASE_RESET_VADDR	0x20000400  /* VECBASE reset value */
-#define XCHAL_VECBASE_RESET_PADDR	0x20000400
-#define XCHAL_RESET_VECBASE_OVERLAP	0
-
-#define XCHAL_RESET_VECTOR0_VADDR	0x20000000
-#define XCHAL_RESET_VECTOR0_PADDR	0x20000000
-#define XCHAL_RESET_VECTOR1_VADDR	0x20000800
-#define XCHAL_RESET_VECTOR1_PADDR	0x20000800
-#define XCHAL_RESET_VECTOR_VADDR	0x20000000
-#define XCHAL_RESET_VECTOR_PADDR	0x20000000
-#define XCHAL_USER_VECOFS		0x00000340
-#define XCHAL_USER_VECTOR_VADDR		0x20000740
-#define XCHAL_USER_VECTOR_PADDR		0x20000740
-#define XCHAL_KERNEL_VECOFS		0x00000300
-#define XCHAL_KERNEL_VECTOR_VADDR	0x20000700
-#define XCHAL_KERNEL_VECTOR_PADDR	0x20000700
-#define XCHAL_DOUBLEEXC_VECOFS		0x000003C0
-#define XCHAL_DOUBLEEXC_VECTOR_VADDR	0x200007C0
-#define XCHAL_DOUBLEEXC_VECTOR_PADDR	0x200007C0
-#define XCHAL_WINDOW_OF4_VECOFS		0x00000000
-#define XCHAL_WINDOW_UF4_VECOFS		0x00000040
-#define XCHAL_WINDOW_OF8_VECOFS		0x00000080
-#define XCHAL_WINDOW_UF8_VECOFS		0x000000C0
-#define XCHAL_WINDOW_OF12_VECOFS	0x00000100
-#define XCHAL_WINDOW_UF12_VECOFS	0x00000140
-#define XCHAL_WINDOW_VECTORS_VADDR	0x20000400
-#define XCHAL_WINDOW_VECTORS_PADDR	0x20000400
-#define XCHAL_INTLEVEL2_VECOFS		0x00000180
-#define XCHAL_INTLEVEL2_VECTOR_VADDR	0x20000580
-#define XCHAL_INTLEVEL2_VECTOR_PADDR	0x20000580
-#define XCHAL_INTLEVEL3_VECOFS		0x000001C0
-#define XCHAL_INTLEVEL3_VECTOR_VADDR	0x200005C0
-#define XCHAL_INTLEVEL3_VECTOR_PADDR	0x200005C0
-#define XCHAL_INTLEVEL4_VECOFS		0x00000200
-#define XCHAL_INTLEVEL4_VECTOR_VADDR	0x20000600
-#define XCHAL_INTLEVEL4_VECTOR_PADDR	0x20000600
-#define XCHAL_INTLEVEL5_VECOFS		0x00000240
-#define XCHAL_INTLEVEL5_VECTOR_VADDR	0x20000640
-#define XCHAL_INTLEVEL5_VECTOR_PADDR	0x20000640
-#define XCHAL_INTLEVEL6_VECOFS		0x00000280
-#define XCHAL_INTLEVEL6_VECTOR_VADDR	0x20000680
-#define XCHAL_INTLEVEL6_VECTOR_PADDR	0x20000680
-#define XCHAL_DEBUG_VECOFS		XCHAL_INTLEVEL6_VECOFS
-#define XCHAL_DEBUG_VECTOR_VADDR	XCHAL_INTLEVEL6_VECTOR_VADDR
-#define XCHAL_DEBUG_VECTOR_PADDR	XCHAL_INTLEVEL6_VECTOR_PADDR
-#define XCHAL_NMI_VECOFS		0x000002C0
-#define XCHAL_NMI_VECTOR_VADDR		0x200006C0
-#define XCHAL_NMI_VECTOR_PADDR		0x200006C0
-#define XCHAL_INTLEVEL7_VECOFS		XCHAL_NMI_VECOFS
-#define XCHAL_INTLEVEL7_VECTOR_VADDR	XCHAL_NMI_VECTOR_VADDR
-#define XCHAL_INTLEVEL7_VECTOR_PADDR	XCHAL_NMI_VECTOR_PADDR
-
-
-/*----------------------------------------------------------------------
-				DEBUG MODULE
-  ----------------------------------------------------------------------*/
-
-/*  Misc  */
-#define XCHAL_HAVE_DEBUG_ERI		0	/* ERI to debug module */
-#define XCHAL_HAVE_DEBUG_APB		0	/* APB to debug module */
-#define XCHAL_HAVE_DEBUG_JTAG		1	/* JTAG to debug module */
-
-/*  On-Chip Debug (OCD)  */
-#define XCHAL_HAVE_OCD			1	/* OnChipDebug option */
-#define XCHAL_NUM_IBREAK		2	/* number of IBREAKn regs */
-#define XCHAL_NUM_DBREAK		2	/* number of DBREAKn regs */
-#define XCHAL_HAVE_OCD_DIR_ARRAY	0	/* faster OCD option (to LX4) */
-#define XCHAL_HAVE_OCD_LS32DDR		1	/* L32DDR/S32DDR (faster OCD) */
-
-/*  TRAX (in core)  */
-#define XCHAL_HAVE_TRAX			0	/* TRAX in debug module */
-#define XCHAL_TRAX_MEM_SIZE		0	/* TRAX memory size in bytes */
-#define XCHAL_TRAX_MEM_SHAREABLE	0	/* start/end regs; ready sig. */
-#define XCHAL_TRAX_ATB_WIDTH		0	/* ATB width (bits), 0=no ATB */
-#define XCHAL_TRAX_TIME_WIDTH		0	/* timestamp bitwidth, 0=none */
-
-/*  Perf counters  */
-#define XCHAL_NUM_PERF_COUNTERS		0	/* performance counters */
-
-
-/*----------------------------------------------------------------------
-				MMU
-  ----------------------------------------------------------------------*/
-
-/*  See core-matmap.h header file for more details.  */
-
-#define XCHAL_HAVE_TLBS			1	/* inverse of HAVE_CACHEATTR */
-#define XCHAL_HAVE_SPANNING_WAY		1	/* one way maps I+D 4GB vaddr */
-#define XCHAL_SPANNING_WAY		0	/* TLB spanning way number */
-#define XCHAL_HAVE_IDENTITY_MAP		1	/* vaddr == paddr always */
-#define XCHAL_HAVE_CACHEATTR		0	/* CACHEATTR register present */
-#define XCHAL_HAVE_MIMIC_CACHEATTR	1	/* region protection */
-#define XCHAL_HAVE_XLT_CACHEATTR	0	/* region prot. w/translation */
-#define XCHAL_HAVE_PTP_MMU		0	/* full MMU (with page table
-						   [autorefill] and protection)
-						   usable for an MMU-based OS */
-/*  If none of the above last 4 are set, it's a custom TLB configuration.  */
-
-#define XCHAL_MMU_ASID_BITS		0	/* number of bits in ASIDs */
-#define XCHAL_MMU_RINGS			1	/* number of rings (1..4) */
-#define XCHAL_MMU_RING_BITS		0	/* num of bits in RING field */
-
-#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
-
-
-#endif /* _XTENSA_CORE_CONFIGURATION_H */
-
diff --git a/src/platform/amd/renoir/include/arch/xtensa/config/core-matmap.h b/src/platform/amd/renoir/include/arch/xtensa/config/core-matmap.h
deleted file mode 100644
index c455815cd9d1..000000000000
--- a/src/platform/amd/renoir/include/arch/xtensa/config/core-matmap.h
+++ /dev/null
@@ -1,318 +0,0 @@
-/* 
- * xtensa/config/core-matmap.h -- Memory access and translation mapping
- *	parameters (CHAL) of the Xtensa processor core configuration.
- *
- *  If you are using Xtensa Tools, see <xtensa/config/core.h> (which includes
- *  this file) for more details.
- *
- *  In the Xtensa processor products released to date, all parameters
- *  defined in this file are derivable (at least in theory) from
- *  information contained in the core-isa.h header file.
- *  In particular, the following core configuration parameters are relevant:
- *	XCHAL_HAVE_CACHEATTR
- *	XCHAL_HAVE_MIMIC_CACHEATTR
- *	XCHAL_HAVE_XLT_CACHEATTR
- *	XCHAL_HAVE_PTP_MMU
- *	XCHAL_ITLB_ARF_ENTRIES_LOG2
- *	XCHAL_DTLB_ARF_ENTRIES_LOG2
- *	XCHAL_DCACHE_IS_WRITEBACK
- *	XCHAL_ICACHE_SIZE		(presence of I-cache)
- *	XCHAL_DCACHE_SIZE		(presence of D-cache)
- *	XCHAL_HW_VERSION_MAJOR
- *	XCHAL_HW_VERSION_MINOR
- */
-
-/* Customer ID=12153; Build=0x72343; Copyright (c) 1999-2018 Tensilica Inc.
-
-   Permission is hereby granted, free of charge, to any person obtaining
-   a copy of this software and associated documentation files (the
-   "Software"), to deal in the Software without restriction, including
-   without limitation the rights to use, copy, modify, merge, publish,
-   distribute, sublicense, and/or sell copies of the Software, and to
-   permit persons to whom the Software is furnished to do so, subject to
-   the following conditions:
-
-   The above copyright notice and this permission notice shall be included
-   in all copies or substantial portions of the Software.
-
-   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
-
-
-#ifndef XTENSA_CONFIG_CORE_MATMAP_H
-#define XTENSA_CONFIG_CORE_MATMAP_H
-
-
-/*----------------------------------------------------------------------
-			CACHE (MEMORY ACCESS) ATTRIBUTES
-  ----------------------------------------------------------------------*/
-
-
-/*  Cache Attribute encodings -- lists of access modes for each cache attribute:  */
-#define XCHAL_FCA_LIST		XTHAL_FAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_FAM_BYPASS	XCHAL_SEP \
-				XTHAL_FAM_BYPASS	XCHAL_SEP \
-				XTHAL_FAM_BYPASS	XCHAL_SEP \
-				XTHAL_FAM_BYPASS	XCHAL_SEP \
-				XTHAL_FAM_BYPASS	XCHAL_SEP \
-				XTHAL_FAM_BYPASS	XCHAL_SEP \
-				XTHAL_FAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_FAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_FAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_FAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_FAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_FAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_FAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_FAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_FAM_EXCEPTION
-#define XCHAL_LCA_LIST		XTHAL_LAM_BYPASSG	XCHAL_SEP \
-				XTHAL_LAM_BYPASSG	XCHAL_SEP \
-				XTHAL_LAM_BYPASSG	XCHAL_SEP \
-				XTHAL_LAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_LAM_BYPASSG	XCHAL_SEP \
-				XTHAL_LAM_BYPASSG	XCHAL_SEP \
-				XTHAL_LAM_BYPASSG	XCHAL_SEP \
-				XTHAL_LAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_LAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_LAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_LAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_LAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_LAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_LAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_LAM_BYPASSG	XCHAL_SEP \
-				XTHAL_LAM_EXCEPTION
-#define XCHAL_SCA_LIST		XTHAL_SAM_BYPASS	XCHAL_SEP \
-				XTHAL_SAM_BYPASS	XCHAL_SEP \
-				XTHAL_SAM_BYPASS	XCHAL_SEP \
-				XTHAL_SAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_SAM_BYPASS	XCHAL_SEP \
-				XTHAL_SAM_BYPASS	XCHAL_SEP \
-				XTHAL_SAM_BYPASS	XCHAL_SEP \
-				XTHAL_SAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_SAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_SAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_SAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_SAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_SAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_SAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_SAM_BYPASS	XCHAL_SEP \
-				XTHAL_SAM_EXCEPTION
-
-
-/*
- *  Specific encoded cache attribute values of general interest.
- *  If a specific cache mode is not available, the closest available
- *  one is returned instead (eg. writethru instead of writeback,
- *  bypass instead of writethru).
- */
-#define XCHAL_CA_BYPASS  		2	/* cache disabled (bypassed) mode */
-#define XCHAL_CA_BYPASSBUF  		6	/* cache disabled (bypassed) bufferable mode */
-#define XCHAL_CA_WRITETHRU		2	/* cache enabled (write-through) mode */
-#define XCHAL_CA_WRITEBACK		2	/* cache enabled (write-back) mode */
-#define XCHAL_HAVE_CA_WRITEBACK_NOALLOC	0	/* write-back no-allocate availability */
-#define XCHAL_CA_WRITEBACK_NOALLOC	2	/* cache enabled (write-back no-allocate) mode */
-#define XCHAL_CA_BYPASS_RW  		0	/* cache disabled (bypassed) mode (no exec) */
-#define XCHAL_CA_WRITETHRU_RW		0	/* cache enabled (write-through) mode (no exec) */
-#define XCHAL_CA_WRITEBACK_RW		0	/* cache enabled (write-back) mode (no exec) */
-#define XCHAL_CA_WRITEBACK_NOALLOC_RW	0	/* cache enabled (write-back no-allocate) mode (no exec) */
-#define XCHAL_CA_ILLEGAL		15	/* no access allowed (all cause exceptions) mode */
-#define XCHAL_CA_ISOLATE		0	/* cache isolate (accesses go to cache not memory) mode */
-
-
-/*----------------------------------------------------------------------
-				MMU
-  ----------------------------------------------------------------------*/
-
-/*
- *  General notes on MMU parameters.
- *
- *  Terminology:
- *	ASID = address-space ID (acts as an "extension" of virtual addresses)
- *	VPN  = virtual page number
- *	PPN  = physical page number
- *	CA   = encoded cache attribute (access modes)
- *	TLB  = translation look-aside buffer (term is stretched somewhat here)
- *	I    = instruction (fetch accesses)
- *	D    = data (load and store accesses)
- *	way  = each TLB (ITLB and DTLB) consists of a number of "ways"
- *		that simultaneously match the virtual address of an access;
- *		a TLB successfully translates a virtual address if exactly
- *		one way matches the vaddr; if none match, it is a miss;
- *		if multiple match, one gets a "multihit" exception;
- *		each way can be independently configured in terms of number of
- *		entries, page sizes, which fields are writable or constant, etc.
- *	set  = group of contiguous ways with exactly identical parameters
- *	ARF  = auto-refill; hardware services a 1st-level miss by loading a PTE
- *		from the page table and storing it in one of the auto-refill ways;
- *		if this PTE load also misses, a miss exception is posted for s/w.
- *	min-wired = a "min-wired" way can be used to map a single (minimum-sized)
- * 		page arbitrarily under program control; it has a single entry,
- *		is non-auto-refill (some other way(s) must be auto-refill),
- *		all its fields (VPN, PPN, ASID, CA) are all writable, and it
- *		supports the XCHAL_MMU_MIN_PTE_PAGE_SIZE page size (a current
- *		restriction is that this be the only page size it supports).
- *
- *  TLB way entries are virtually indexed.
- *  TLB ways that support multiple page sizes:
- *	- must have all writable VPN and PPN fields;
- *	- can only use one page size at any given time (eg. setup at startup),
- *	  selected by the respective ITLBCFG or DTLBCFG special register,
- *	  whose bits n*4+3 .. n*4 index the list of page sizes for way n
- *	  (XCHAL_xTLB_SETm_PAGESZ_LOG2_LIST for set m corresponding to way n);
- *	  this list may be sparse for auto-refill ways because auto-refill
- *	  ways have independent lists of supported page sizes sharing a
- *	  common encoding with PTE entries; the encoding is the index into
- *	  this list; unsupported sizes for a given way are zero in the list;
- *	  selecting unsupported sizes results in undefined hardware behaviour;
- *	- is only possible for ways 0 thru 7 (due to ITLBCFG/DTLBCFG definition).
- */
-
-#define XCHAL_MMU_ASID_INVALID		0	/* ASID value indicating invalid address space */
-#define XCHAL_MMU_ASID_KERNEL		0	/* ASID value indicating kernel (ring 0) address space */
-#define XCHAL_MMU_SR_BITS		0	/* number of size-restriction bits supported */
-#define XCHAL_MMU_CA_BITS		4	/* number of bits needed to hold cache attribute encoding */
-#define XCHAL_MMU_MAX_PTE_PAGE_SIZE	29	/* max page size in a PTE structure (log2) */
-#define XCHAL_MMU_MIN_PTE_PAGE_SIZE	29	/* min page size in a PTE structure (log2) */
-
-
-/***  Instruction TLB:  ***/
-
-#define XCHAL_ITLB_WAY_BITS		0	/* number of bits holding the ways */
-#define XCHAL_ITLB_WAYS			1	/* number of ways (n-way set-associative TLB) */
-#define XCHAL_ITLB_ARF_WAYS		0	/* number of auto-refill ways */
-#define XCHAL_ITLB_SETS			1	/* number of sets (groups of ways with identical settings) */
-
-/*  Way set to which each way belongs:  */
-#define XCHAL_ITLB_WAY0_SET		0
-
-/*  Ways sets that are used by hardware auto-refill (ARF):  */
-#define XCHAL_ITLB_ARF_SETS		0	/* number of auto-refill sets */
-
-/*  Way sets that are "min-wired" (see terminology comment above):  */
-#define XCHAL_ITLB_MINWIRED_SETS	0	/* number of "min-wired" sets */
-
-
-/*  ITLB way set 0 (group of ways 0 thru 0):  */
-#define XCHAL_ITLB_SET0_WAY			0	/* index of first way in this way set */
-#define XCHAL_ITLB_SET0_WAYS			1	/* number of (contiguous) ways in this way set */
-#define XCHAL_ITLB_SET0_ENTRIES_LOG2		3	/* log2(number of entries in this way) */
-#define XCHAL_ITLB_SET0_ENTRIES			8	/* number of entries in this way (always a power of 2) */
-#define XCHAL_ITLB_SET0_ARF			0	/* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
-#define XCHAL_ITLB_SET0_PAGESIZES		1	/* number of supported page sizes in this way */
-#define XCHAL_ITLB_SET0_PAGESZ_BITS		0	/* number of bits to encode the page size */
-#define XCHAL_ITLB_SET0_PAGESZ_LOG2_MIN		29	/* log2(minimum supported page size) */
-#define XCHAL_ITLB_SET0_PAGESZ_LOG2_MAX		29	/* log2(maximum supported page size) */
-#define XCHAL_ITLB_SET0_PAGESZ_LOG2_LIST	29	/* list of log2(page size)s, separated by XCHAL_SEP;
-							   2^PAGESZ_BITS entries in list, unsupported entries are zero */
-#define XCHAL_ITLB_SET0_ASID_CONSTMASK		0	/* constant ASID bits; 0 if all writable */
-#define XCHAL_ITLB_SET0_VPN_CONSTMASK		0x00000000	/* constant VPN bits, not including entry index bits; 0 if all writable */
-#define XCHAL_ITLB_SET0_PPN_CONSTMASK		0xE0000000	/* constant PPN bits, including entry index bits; 0 if all writable */
-#define XCHAL_ITLB_SET0_CA_CONSTMASK		0	/* constant CA bits; 0 if all writable */
-#define XCHAL_ITLB_SET0_ASID_RESET		0	/* 1 if ASID reset values defined (and all writable); 0 otherwise */
-#define XCHAL_ITLB_SET0_VPN_RESET		0	/* 1 if VPN reset values defined (and all writable); 0 otherwise */
-#define XCHAL_ITLB_SET0_PPN_RESET		0	/* 1 if PPN reset values defined (and all writable); 0 otherwise */
-#define XCHAL_ITLB_SET0_CA_RESET		1	/* 1 if CA reset values defined (and all writable); 0 otherwise */
-/*  Constant VPN values for each entry of ITLB way set 0 (because VPN_CONSTMASK is non-zero):  */
-#define XCHAL_ITLB_SET0_E0_VPN_CONST		0x00000000
-#define XCHAL_ITLB_SET0_E1_VPN_CONST		0x20000000
-#define XCHAL_ITLB_SET0_E2_VPN_CONST		0x40000000
-#define XCHAL_ITLB_SET0_E3_VPN_CONST		0x60000000
-#define XCHAL_ITLB_SET0_E4_VPN_CONST		0x80000000
-#define XCHAL_ITLB_SET0_E5_VPN_CONST		0xA0000000
-#define XCHAL_ITLB_SET0_E6_VPN_CONST		0xC0000000
-#define XCHAL_ITLB_SET0_E7_VPN_CONST		0xE0000000
-/*  Constant PPN values for each entry of ITLB way set 0 (because PPN_CONSTMASK is non-zero):  */
-#define XCHAL_ITLB_SET0_E0_PPN_CONST		0x00000000
-#define XCHAL_ITLB_SET0_E1_PPN_CONST		0x20000000
-#define XCHAL_ITLB_SET0_E2_PPN_CONST		0x40000000
-#define XCHAL_ITLB_SET0_E3_PPN_CONST		0x60000000
-#define XCHAL_ITLB_SET0_E4_PPN_CONST		0x80000000
-#define XCHAL_ITLB_SET0_E5_PPN_CONST		0xA0000000
-#define XCHAL_ITLB_SET0_E6_PPN_CONST		0xC0000000
-#define XCHAL_ITLB_SET0_E7_PPN_CONST		0xE0000000
-/*  Reset CA values for each entry of ITLB way set 0 (because SET0_CA_RESET is non-zero):  */
-#define XCHAL_ITLB_SET0_E0_CA_RESET		0x02
-#define XCHAL_ITLB_SET0_E1_CA_RESET		0x02
-#define XCHAL_ITLB_SET0_E2_CA_RESET		0x02
-#define XCHAL_ITLB_SET0_E3_CA_RESET		0x02
-#define XCHAL_ITLB_SET0_E4_CA_RESET		0x02
-#define XCHAL_ITLB_SET0_E5_CA_RESET		0x02
-#define XCHAL_ITLB_SET0_E6_CA_RESET		0x02
-#define XCHAL_ITLB_SET0_E7_CA_RESET		0x02
-
-
-/***  Data TLB:  ***/
-
-#define XCHAL_DTLB_WAY_BITS		0	/* number of bits holding the ways */
-#define XCHAL_DTLB_WAYS			1	/* number of ways (n-way set-associative TLB) */
-#define XCHAL_DTLB_ARF_WAYS		0	/* number of auto-refill ways */
-#define XCHAL_DTLB_SETS			1	/* number of sets (groups of ways with identical settings) */
-
-/*  Way set to which each way belongs:  */
-#define XCHAL_DTLB_WAY0_SET		0
-
-/*  Ways sets that are used by hardware auto-refill (ARF):  */
-#define XCHAL_DTLB_ARF_SETS		0	/* number of auto-refill sets */
-
-/*  Way sets that are "min-wired" (see terminology comment above):  */
-#define XCHAL_DTLB_MINWIRED_SETS	0	/* number of "min-wired" sets */
-
-
-/*  DTLB way set 0 (group of ways 0 thru 0):  */
-#define XCHAL_DTLB_SET0_WAY			0	/* index of first way in this way set */
-#define XCHAL_DTLB_SET0_WAYS			1	/* number of (contiguous) ways in this way set */
-#define XCHAL_DTLB_SET0_ENTRIES_LOG2		3	/* log2(number of entries in this way) */
-#define XCHAL_DTLB_SET0_ENTRIES			8	/* number of entries in this way (always a power of 2) */
-#define XCHAL_DTLB_SET0_ARF			0	/* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
-#define XCHAL_DTLB_SET0_PAGESIZES		1	/* number of supported page sizes in this way */
-#define XCHAL_DTLB_SET0_PAGESZ_BITS		0	/* number of bits to encode the page size */
-#define XCHAL_DTLB_SET0_PAGESZ_LOG2_MIN		29	/* log2(minimum supported page size) */
-#define XCHAL_DTLB_SET0_PAGESZ_LOG2_MAX		29	/* log2(maximum supported page size) */
-#define XCHAL_DTLB_SET0_PAGESZ_LOG2_LIST	29	/* list of log2(page size)s, separated by XCHAL_SEP;
-							   2^PAGESZ_BITS entries in list, unsupported entries are zero */
-#define XCHAL_DTLB_SET0_ASID_CONSTMASK		0	/* constant ASID bits; 0 if all writable */
-#define XCHAL_DTLB_SET0_VPN_CONSTMASK		0x00000000	/* constant VPN bits, not including entry index bits; 0 if all writable */
-#define XCHAL_DTLB_SET0_PPN_CONSTMASK		0xE0000000	/* constant PPN bits, including entry index bits; 0 if all writable */
-#define XCHAL_DTLB_SET0_CA_CONSTMASK		0	/* constant CA bits; 0 if all writable */
-#define XCHAL_DTLB_SET0_ASID_RESET		0	/* 1 if ASID reset values defined (and all writable); 0 otherwise */
-#define XCHAL_DTLB_SET0_VPN_RESET		0	/* 1 if VPN reset values defined (and all writable); 0 otherwise */
-#define XCHAL_DTLB_SET0_PPN_RESET		0	/* 1 if PPN reset values defined (and all writable); 0 otherwise */
-#define XCHAL_DTLB_SET0_CA_RESET		1	/* 1 if CA reset values defined (and all writable); 0 otherwise */
-/*  Constant VPN values for each entry of DTLB way set 0 (because VPN_CONSTMASK is non-zero):  */
-#define XCHAL_DTLB_SET0_E0_VPN_CONST		0x00000000
-#define XCHAL_DTLB_SET0_E1_VPN_CONST		0x20000000
-#define XCHAL_DTLB_SET0_E2_VPN_CONST		0x40000000
-#define XCHAL_DTLB_SET0_E3_VPN_CONST		0x60000000
-#define XCHAL_DTLB_SET0_E4_VPN_CONST		0x80000000
-#define XCHAL_DTLB_SET0_E5_VPN_CONST		0xA0000000
-#define XCHAL_DTLB_SET0_E6_VPN_CONST		0xC0000000
-#define XCHAL_DTLB_SET0_E7_VPN_CONST		0xE0000000
-/*  Constant PPN values for each entry of DTLB way set 0 (because PPN_CONSTMASK is non-zero):  */
-#define XCHAL_DTLB_SET0_E0_PPN_CONST		0x00000000
-#define XCHAL_DTLB_SET0_E1_PPN_CONST		0x20000000
-#define XCHAL_DTLB_SET0_E2_PPN_CONST		0x40000000
-#define XCHAL_DTLB_SET0_E3_PPN_CONST		0x60000000
-#define XCHAL_DTLB_SET0_E4_PPN_CONST		0x80000000
-#define XCHAL_DTLB_SET0_E5_PPN_CONST		0xA0000000
-#define XCHAL_DTLB_SET0_E6_PPN_CONST		0xC0000000
-#define XCHAL_DTLB_SET0_E7_PPN_CONST		0xE0000000
-/*  Reset CA values for each entry of DTLB way set 0 (because SET0_CA_RESET is non-zero):  */
-#define XCHAL_DTLB_SET0_E0_CA_RESET		0x02
-#define XCHAL_DTLB_SET0_E1_CA_RESET		0x02
-#define XCHAL_DTLB_SET0_E2_CA_RESET		0x02
-#define XCHAL_DTLB_SET0_E3_CA_RESET		0x02
-#define XCHAL_DTLB_SET0_E4_CA_RESET		0x02
-#define XCHAL_DTLB_SET0_E5_CA_RESET		0x02
-#define XCHAL_DTLB_SET0_E6_CA_RESET		0x02
-#define XCHAL_DTLB_SET0_E7_CA_RESET		0x02
-
-
-
-
-#endif /*XTENSA_CONFIG_CORE_MATMAP_H*/
-
diff --git a/src/platform/amd/renoir/include/arch/xtensa/config/defs.h b/src/platform/amd/renoir/include/arch/xtensa/config/defs.h
deleted file mode 100644
index 0e3500014cd1..000000000000
--- a/src/platform/amd/renoir/include/arch/xtensa/config/defs.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/* Definitions for Xtensa instructions, types, and protos. */
-
-/* Customer ID=12153; Build=0x72343; Copyright (c) 2003-2004 Tensilica Inc.
-
-   Permission is hereby granted, free of charge, to any person obtaining
-   a copy of this software and associated documentation files (the
-   "Software"), to deal in the Software without restriction, including
-   without limitation the rights to use, copy, modify, merge, publish,
-   distribute, sublicense, and/or sell copies of the Software, and to
-   permit persons to whom the Software is furnished to do so, subject to
-   the following conditions:
-
-   The above copyright notice and this permission notice shall be included
-   in all copies or substantial portions of the Software.
-
-   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
-
-/* NOTE: This file exists only for backward compatibility with T1050
-   and earlier Xtensa releases.  It includes only a subset of the
-   available header files.  */
-
-#ifndef _XTENSA_BASE_HEADER
-#define _XTENSA_BASE_HEADER
-
-#ifdef __XTENSA__
-
-#include <xtensa/tie/xt_core.h>
-#include <xtensa/tie/xt_misc.h>
-#include <xtensa/tie/xt_booleans.h>
-
-#endif /* __XTENSA__ */
-#endif /* !_XTENSA_BASE_HEADER */
diff --git a/src/platform/amd/renoir/include/arch/xtensa/config/specreg.h b/src/platform/amd/renoir/include/arch/xtensa/config/specreg.h
deleted file mode 100644
index ae2eaaf0b6ea..000000000000
--- a/src/platform/amd/renoir/include/arch/xtensa/config/specreg.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * Xtensa Special Register symbolic names
- */
-
-/* $Id: //depot/rel/Eaglenest/Xtensa/SWConfig/hal/specreg.h.tpp#1 $ */
-
-/* Customer ID=12153; Build=0x72343; Copyright (c) 1998-2002 Tensilica Inc.
-
-   Permission is hereby granted, free of charge, to any person obtaining
-   a copy of this software and associated documentation files (the
-   "Software"), to deal in the Software without restriction, including
-   without limitation the rights to use, copy, modify, merge, publish,
-   distribute, sublicense, and/or sell copies of the Software, and to
-   permit persons to whom the Software is furnished to do so, subject to
-   the following conditions:
-
-   The above copyright notice and this permission notice shall be included
-   in all copies or substantial portions of the Software.
-
-   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
-
-#ifndef XTENSA_SPECREG_H
-#define XTENSA_SPECREG_H
-
-/*  Include these special register bitfield definitions, for historical reasons:  */
-#include <xtensa/corebits.h>
-
-
-/*  Special registers:  */
-#define LBEG		0
-#define LEND		1
-#define LCOUNT		2
-#define SAR		3
-#define BR		4
-#define SCOMPARE1	12
-#define ACCLO		16
-#define ACCHI		17
-#define MR_0		32
-#define MR_1		33
-#define MR_2		34
-#define MR_3		35
-#define WINDOWBASE	72
-#define WINDOWSTART	73
-#define IBREAKENABLE	96
-#define ATOMCTL		99
-#define DDR		104
-#define IBREAKA_0	128
-#define IBREAKA_1	129
-#define DBREAKA_0	144
-#define DBREAKA_1	145
-#define DBREAKC_0	160
-#define DBREAKC_1	161
-#define EPC_1		177
-#define EPC_2		178
-#define EPC_3		179
-#define EPC_4		180
-#define EPC_5		181
-#define EPC_6		182
-#define EPC_7		183
-#define DEPC		192
-#define EPS_2		194
-#define EPS_3		195
-#define EPS_4		196
-#define EPS_5		197
-#define EPS_6		198
-#define EPS_7		199
-#define EXCSAVE_1	209
-#define EXCSAVE_2	210
-#define EXCSAVE_3	211
-#define EXCSAVE_4	212
-#define EXCSAVE_5	213
-#define EXCSAVE_6	214
-#define EXCSAVE_7	215
-#define CPENABLE	224
-#define INTERRUPT	226
-#define INTENABLE	228
-#define PS		230
-#define VECBASE		231
-#define EXCCAUSE	232
-#define DEBUGCAUSE	233
-#define CCOUNT		234
-#define PRID		235
-#define ICOUNT		236
-#define ICOUNTLEVEL	237
-#define EXCVADDR	238
-#define CCOMPARE_0	240
-#define CCOMPARE_1	241
-#define MISC_REG_0	244
-#define MISC_REG_1	245
-
-/*  Special cases (bases of special register series):  */
-#define MR		32
-#define IBREAKA		128
-#define DBREAKA		144
-#define DBREAKC		160
-#define EPC		176
-#define EPS		192
-#define EXCSAVE		208
-#define CCOMPARE	240
-
-/*  Special names for read-only and write-only interrupt registers:  */
-#define INTREAD		226
-#define INTSET		226
-#define INTCLEAR	227
-
-#endif /* XTENSA_SPECREG_H */
-
diff --git a/src/platform/amd/renoir/include/arch/xtensa/config/system.h b/src/platform/amd/renoir/include/arch/xtensa/config/system.h
deleted file mode 100644
index fb070b1918a1..000000000000
--- a/src/platform/amd/renoir/include/arch/xtensa/config/system.h
+++ /dev/null
@@ -1,271 +0,0 @@
-/* 
- * xtensa/config/system.h -- HAL definitions that are dependent on SYSTEM configuration
- *
- *  NOTE: The location and contents of this file are highly subject to change.
- *
- *  Source for configuration-independent binaries (which link in a
- *  configuration-specific HAL library) must NEVER include this file.
- *  The HAL itself has historically included this file in some instances,
- *  but this is not appropriate either, because the HAL is meant to be
- *  core-specific but system independent.
- */
-
-/* Customer ID=12153; Build=0x72343; Copyright (c) 2000-2010 Tensilica Inc.
-
-   Permission is hereby granted, free of charge, to any person obtaining
-   a copy of this software and associated documentation files (the
-   "Software"), to deal in the Software without restriction, including
-   without limitation the rights to use, copy, modify, merge, publish,
-   distribute, sublicense, and/or sell copies of the Software, and to
-   permit persons to whom the Software is furnished to do so, subject to
-   the following conditions:
-
-   The above copyright notice and this permission notice shall be included
-   in all copies or substantial portions of the Software.
-
-   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
-
-
-#ifndef XTENSA_CONFIG_SYSTEM_H
-#define XTENSA_CONFIG_SYSTEM_H
-
-/*#include <xtensa/hal.h>*/
-
-
-
-/*----------------------------------------------------------------------
-				CONFIGURED SOFTWARE OPTIONS
-  ----------------------------------------------------------------------*/
-
-#define XSHAL_USE_ABSOLUTE_LITERALS	0	/* (sw-only option, whether software uses absolute literals) */
-#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals.  */
-
-#define XSHAL_ABI			XTHAL_ABI_WINDOWED	/* (sw-only option, selected ABI) */
-/*  The above maps to one of the following constants:  */
-#define XTHAL_ABI_WINDOWED		0
-#define XTHAL_ABI_CALL0			1
-/*  Alternatives:  */
-/*#define XSHAL_WINDOWED_ABI		1*/	/* set if windowed ABI selected */
-/*#define XSHAL_CALL0_ABI		0*/	/* set if call0 ABI selected */
-
-#define XSHAL_CLIB			XTHAL_CLIB_NEWLIB	/* (sw-only option, selected C library) */
-/*  The above maps to one of the following constants:  */
-#define XTHAL_CLIB_NEWLIB		0
-#define XTHAL_CLIB_UCLIBC		1
-#define XTHAL_CLIB_XCLIB		2
-/*  Alternatives:  */
-/*#define XSHAL_NEWLIB			1*/	/* set if newlib C library selected */
-/*#define XSHAL_UCLIBC			0*/	/* set if uCLibC C library selected */
-/*#define XSHAL_XCLIB			0*/	/* set if Xtensa C library selected */
-
-#define XSHAL_USE_FLOATING_POINT	1
-
-#define XSHAL_FLOATING_POINT_ABI	0
-
-/*  SW workarounds enabled for HW errata:  */
-
-/*----------------------------------------------------------------------
-				DEVICE ADDRESSES
-  ----------------------------------------------------------------------*/
-
-/*
- *  Strange place to find these, but the configuration GUI
- *  allows moving these around to account for various core
- *  configurations.  Specific boards (and their BSP software)
- *  will have specific meanings for these components.
- */
-
-/*  I/O Block areas:  */
-#define XSHAL_IOBLOCK_CACHED_VADDR	0x70000000
-#define XSHAL_IOBLOCK_CACHED_PADDR	0x70000000
-#define XSHAL_IOBLOCK_CACHED_SIZE	0x0E000000
-
-#define XSHAL_IOBLOCK_BYPASS_VADDR	0x50000000
-#define XSHAL_IOBLOCK_BYPASS_PADDR	0x50000000
-#define XSHAL_IOBLOCK_BYPASS_SIZE	0x0E000000
-
-/*  System ROM:  */
-/*#define XSHAL_ROM_[VP]ADDR		...not configured...*/
-/*#define XSHAL_ROM_SIZE		...not configured...*/
-/*#define XSHAL_ROM_AVAIL_V{ADDR,SIZE}	...not configured...*/
-
-/*  System RAM:  */
-#define XSHAL_RAM_VADDR		0x40000000
-#define XSHAL_RAM_PADDR		0x40000000
-#define XSHAL_RAM_VSIZE		0x40000000
-#define XSHAL_RAM_PSIZE		0x40000000
-#define XSHAL_RAM_SIZE		XSHAL_RAM_PSIZE
-/*  Largest available area (free of vectors):  */
-#define XSHAL_RAM_AVAIL_VADDR	0x40000000
-#define XSHAL_RAM_AVAIL_VSIZE	0x40000000
-
-/*
- *  Shadow system RAM (same device as system RAM, at different address).
- *  (Emulation boards need this for the SONIC Ethernet driver
- *   when data caches are configured for writeback mode.)
- *  NOTE: on full MMU configs, this points to the BYPASS virtual address
- *  of system RAM, ie. is the same as XSHAL_RAM_* except that virtual
- *  addresses are viewed through the BYPASS static map rather than
- *  the CACHED static map.
- */
-#define XSHAL_RAM_BYPASS_VADDR		0x80000000
-#define XSHAL_RAM_BYPASS_PADDR		0x80000000
-#define XSHAL_RAM_BYPASS_PSIZE		0x20000000
-
-/*  Alternate system RAM (different device than system RAM):  */
-/*#define XSHAL_ALTRAM_[VP]ADDR		...not configured...*/
-/*#define XSHAL_ALTRAM_SIZE		...not configured...*/
-
-/*  Some available location in which to place devices in a simulation (eg. XTMP):  */
-#define XSHAL_SIMIO_CACHED_VADDR	0xC0000000
-#define XSHAL_SIMIO_BYPASS_VADDR	0xC0000000
-#define XSHAL_SIMIO_PADDR		0xC0000000
-#define XSHAL_SIMIO_SIZE		0x20000000
-
-
-/*----------------------------------------------------------------------
- *  For use by reference testbench exit and diagnostic routines.
- */
-#define XSHAL_MAGIC_EXIT		0x0
-
-/*----------------------------------------------------------------------
- *			DEVICE-ADDRESS DEPENDENT...
- *
- *  Values written to CACHEATTR special register (or its equivalent)
- *  to enable and disable caches in various modes.
- *----------------------------------------------------------------------*/
-
-/*----------------------------------------------------------------------
-			BACKWARD COMPATIBILITY ...
-  ----------------------------------------------------------------------*/
-
-/*
- *  NOTE:  the following two macros are DEPRECATED.  Use the latter
- *  board-specific macros instead, which are specially tuned for the
- *  particular target environments' memory maps.
- */
-#define XSHAL_CACHEATTR_BYPASS		XSHAL_XT2000_CACHEATTR_BYPASS	/* disable caches in bypass mode */
-#define XSHAL_CACHEATTR_DEFAULT		XSHAL_XT2000_CACHEATTR_DEFAULT	/* default setting to enable caches (no writeback!) */
-
-/*----------------------------------------------------------------------
-				GENERIC
-  ----------------------------------------------------------------------*/
-
-/*  For the following, a 512MB region is used if it contains a system (PIF) RAM,
- *  system (PIF) ROM, local memory, or XLMI.  */
-
-/*  These set any unused 512MB region to cache-BYPASS attribute:  */
-#define XSHAL_ALLVALID_CACHEATTR_WRITEBACK	0x22221112	/* enable caches in write-back mode */
-#define XSHAL_ALLVALID_CACHEATTR_WRITEALLOC	0x22221112	/* enable caches in write-allocate mode */
-#define XSHAL_ALLVALID_CACHEATTR_WRITETHRU	0x22221112	/* enable caches in write-through mode */
-#define XSHAL_ALLVALID_CACHEATTR_BYPASS		0x22222222	/* disable caches in bypass mode */
-#define XSHAL_ALLVALID_CACHEATTR_DEFAULT	XSHAL_ALLVALID_CACHEATTR_WRITEBACK	/* default setting to enable caches */
-
-/*  These set any unused 512MB region to ILLEGAL attribute:  */
-#define XSHAL_STRICT_CACHEATTR_WRITEBACK	0xFFFF111F	/* enable caches in write-back mode */
-#define XSHAL_STRICT_CACHEATTR_WRITEALLOC	0xFFFF111F	/* enable caches in write-allocate mode */
-#define XSHAL_STRICT_CACHEATTR_WRITETHRU	0xFFFF111F	/* enable caches in write-through mode */
-#define XSHAL_STRICT_CACHEATTR_BYPASS		0xFFFF222F	/* disable caches in bypass mode */
-#define XSHAL_STRICT_CACHEATTR_DEFAULT		XSHAL_STRICT_CACHEATTR_WRITEBACK	/* default setting to enable caches */
-
-/*  These set the first 512MB, if unused, to ILLEGAL attribute to help catch
- *  NULL-pointer dereference bugs; all other unused 512MB regions are set
- *  to cache-BYPASS attribute:  */
-#define XSHAL_TRAPNULL_CACHEATTR_WRITEBACK	0x2222111F	/* enable caches in write-back mode */
-#define XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC	0x2222111F	/* enable caches in write-allocate mode */
-#define XSHAL_TRAPNULL_CACHEATTR_WRITETHRU	0x2222111F	/* enable caches in write-through mode */
-#define XSHAL_TRAPNULL_CACHEATTR_BYPASS		0x2222222F	/* disable caches in bypass mode */
-#define XSHAL_TRAPNULL_CACHEATTR_DEFAULT	XSHAL_TRAPNULL_CACHEATTR_WRITEBACK	/* default setting to enable caches */
-
-/*----------------------------------------------------------------------
-			ISS (Instruction Set Simulator) SPECIFIC ...
-  ----------------------------------------------------------------------*/
-
-/*  For now, ISS defaults to the TRAPNULL settings:  */
-#define XSHAL_ISS_CACHEATTR_WRITEBACK	XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
-#define XSHAL_ISS_CACHEATTR_WRITEALLOC	XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC
-#define XSHAL_ISS_CACHEATTR_WRITETHRU	XSHAL_TRAPNULL_CACHEATTR_WRITETHRU
-#define XSHAL_ISS_CACHEATTR_BYPASS	XSHAL_TRAPNULL_CACHEATTR_BYPASS
-#define XSHAL_ISS_CACHEATTR_DEFAULT	XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
-
-#define XSHAL_ISS_PIPE_REGIONS	0
-#define XSHAL_ISS_SDRAM_REGIONS	0
-
-
-/*----------------------------------------------------------------------
-			XT2000 BOARD SPECIFIC ...
-  ----------------------------------------------------------------------*/
-
-/*  For the following, a 512MB region is used if it contains any system RAM,
- *  system ROM, local memory, XLMI, or other XT2000 board device or memory.
- *  Regions containing devices are forced to cache-BYPASS mode regardless
- *  of whether the macro is _WRITEBACK vs. _BYPASS etc.  */
-
-/*  These set any 512MB region unused on the XT2000 to ILLEGAL attribute:  */
-#define XSHAL_XT2000_CACHEATTR_WRITEBACK	0xFFF2121F	/* enable caches in write-back mode */
-#define XSHAL_XT2000_CACHEATTR_WRITEALLOC	0xFFF2121F	/* enable caches in write-allocate mode */
-#define XSHAL_XT2000_CACHEATTR_WRITETHRU	0xFFF2121F	/* enable caches in write-through mode */
-#define XSHAL_XT2000_CACHEATTR_BYPASS		0xFFF2222F	/* disable caches in bypass mode */
-#define XSHAL_XT2000_CACHEATTR_DEFAULT		XSHAL_XT2000_CACHEATTR_WRITEBACK	/* default setting to enable caches */
-
-#define XSHAL_XT2000_PIPE_REGIONS	0x00000000	/* BusInt pipeline regions */
-#define XSHAL_XT2000_SDRAM_REGIONS	0x00000110	/* BusInt SDRAM regions */
-
-
-/*----------------------------------------------------------------------
-				VECTOR INFO AND SIZES
-  ----------------------------------------------------------------------*/
-
-#define XSHAL_VECTORS_PACKED		0
-#define XSHAL_STATIC_VECTOR_SELECT	0
-#define XSHAL_RESET_VECTOR_VADDR	0x20000000
-#define XSHAL_RESET_VECTOR_PADDR	0x20000000
-
-/*
- *  Sizes allocated to vectors by the system (memory map) configuration.
- *  These sizes are constrained by core configuration (eg. one vector's
- *  code cannot overflow into another vector) but are dependent on the
- *  system or board (or LSP) memory map configuration.
- *
- *  Whether or not each vector happens to be in a system ROM is also
- *  a system configuration matter, sometimes useful, included here also:
- */
-#define XSHAL_RESET_VECTOR_SIZE	0x00000300
-#define XSHAL_RESET_VECTOR_ISROM	0
-#define XSHAL_USER_VECTOR_SIZE	0x00000038
-#define XSHAL_USER_VECTOR_ISROM	0
-#define XSHAL_PROGRAMEXC_VECTOR_SIZE	XSHAL_USER_VECTOR_SIZE	/* for backward compatibility */
-#define XSHAL_USEREXC_VECTOR_SIZE	XSHAL_USER_VECTOR_SIZE	/* for backward compatibility */
-#define XSHAL_KERNEL_VECTOR_SIZE	0x00000038
-#define XSHAL_KERNEL_VECTOR_ISROM	0
-#define XSHAL_STACKEDEXC_VECTOR_SIZE	XSHAL_KERNEL_VECTOR_SIZE	/* for backward compatibility */
-#define XSHAL_KERNELEXC_VECTOR_SIZE	XSHAL_KERNEL_VECTOR_SIZE	/* for backward compatibility */
-#define XSHAL_DOUBLEEXC_VECTOR_SIZE	0x00000040
-#define XSHAL_DOUBLEEXC_VECTOR_ISROM	0
-#define XSHAL_WINDOW_VECTORS_SIZE	0x00000178
-#define XSHAL_WINDOW_VECTORS_ISROM	0
-#define XSHAL_INTLEVEL2_VECTOR_SIZE	0x00000038
-#define XSHAL_INTLEVEL2_VECTOR_ISROM	0
-#define XSHAL_INTLEVEL3_VECTOR_SIZE	0x00000038
-#define XSHAL_INTLEVEL3_VECTOR_ISROM	0
-#define XSHAL_INTLEVEL4_VECTOR_SIZE	0x00000038
-#define XSHAL_INTLEVEL4_VECTOR_ISROM	0
-#define XSHAL_INTLEVEL5_VECTOR_SIZE	0x00000038
-#define XSHAL_INTLEVEL5_VECTOR_ISROM	0
-#define XSHAL_INTLEVEL6_VECTOR_SIZE	0x00000038
-#define XSHAL_INTLEVEL6_VECTOR_ISROM	0
-#define XSHAL_DEBUG_VECTOR_SIZE		XSHAL_INTLEVEL6_VECTOR_SIZE
-#define XSHAL_DEBUG_VECTOR_ISROM	XSHAL_INTLEVEL6_VECTOR_ISROM
-#define XSHAL_NMI_VECTOR_SIZE	0x00000038
-#define XSHAL_NMI_VECTOR_ISROM	0
-#define XSHAL_INTLEVEL7_VECTOR_SIZE	XSHAL_NMI_VECTOR_SIZE
-
-
-#endif /*XTENSA_CONFIG_SYSTEM_H*/
-
diff --git a/src/platform/amd/renoir/include/arch/xtensa/config/tie-asm.h b/src/platform/amd/renoir/include/arch/xtensa/config/tie-asm.h
deleted file mode 100644
index 68a172f0de2d..000000000000
--- a/src/platform/amd/renoir/include/arch/xtensa/config/tie-asm.h
+++ /dev/null
@@ -1,409 +0,0 @@
-/* 
- * tie-asm.h -- compile-time HAL assembler definitions dependent on CORE & TIE
- *
- *  NOTE:  This header file is not meant to be included directly.
- */
-
-/* This header file contains assembly-language definitions (assembly
-   macros, etc.) for this specific Xtensa processor's TIE extensions
-   and options.  It is customized to this Xtensa processor configuration.
-
-   Customer ID=12153; Build=0x72343; Copyright (c) 1999-2018 Cadence Design Systems Inc.
-
-   Permission is hereby granted, free of charge, to any person obtaining
-   a copy of this software and associated documentation files (the
-   "Software"), to deal in the Software without restriction, including
-   without limitation the rights to use, copy, modify, merge, publish,
-   distribute, sublicense, and/or sell copies of the Software, and to
-   permit persons to whom the Software is furnished to do so, subject to
-   the following conditions:
-
-   The above copyright notice and this permission notice shall be included
-   in all copies or substantial portions of the Software.
-
-   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
-
-#ifndef _XTENSA_CORE_TIE_ASM_H
-#define _XTENSA_CORE_TIE_ASM_H
-
-/*  Selection parameter values for save-area save/restore macros:  */
-/*  Option vs. TIE:  */
-#define XTHAL_SAS_TIE	0x0001	/* custom extension or coprocessor */
-#define XTHAL_SAS_OPT	0x0002	/* optional (and not a coprocessor) */
-#define XTHAL_SAS_ANYOT	0x0003	/* both of the above */
-/*  Whether used automatically by compiler:  */
-#define XTHAL_SAS_NOCC	0x0004	/* not used by compiler w/o special opts/code */
-#define XTHAL_SAS_CC	0x0008	/* used by compiler without special opts/code */
-#define XTHAL_SAS_ANYCC	0x000C	/* both of the above */
-/*  ABI handling across function calls:  */
-#define XTHAL_SAS_CALR	0x0010	/* caller-saved */
-#define XTHAL_SAS_CALE	0x0020	/* callee-saved */
-#define XTHAL_SAS_GLOB	0x0040	/* global across function calls (in thread) */
-#define XTHAL_SAS_ANYABI	0x0070	/* all of the above three */
-/*  Misc  */
-#define XTHAL_SAS_ALL	0xFFFF	/* include all default NCP contents */
-#define XTHAL_SAS3(optie,ccuse,abi)	( ((optie) & XTHAL_SAS_ANYOT)  \
-					| ((ccuse) & XTHAL_SAS_ANYCC)  \
-					| ((abi)   & XTHAL_SAS_ANYABI) )
-
-
-    /*
-      *  Macro to store all non-coprocessor (extra) custom TIE and optional state
-      *  (not including zero-overhead loop registers).
-      *  Required parameters:
-      *      ptr         Save area pointer address register (clobbered)
-      *                  (register must contain a 4 byte aligned address).
-      *      at1..at4    Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
-      *                  registers are clobbered, the remaining are unused).
-      *  Optional parameters:
-      *      continue    If macro invoked as part of a larger store sequence, set to 1
-      *                  if this is not the first in the sequence.  Defaults to 0.
-      *      ofs         Offset from start of larger sequence (from value of first ptr
-      *                  in sequence) at which to store.  Defaults to next available space
-      *                  (or 0 if <continue> is 0).
-      *      select      Select what category(ies) of registers to store, as a bitmask
-      *                  (see XTHAL_SAS_xxx constants).  Defaults to all registers.
-      *      alloc       Select what category(ies) of registers to allocate; if any
-      *                  category is selected here that is not in <select>, space for
-      *                  the corresponding registers is skipped without doing any store.
-      */
-    .macro xchal_ncp_store  ptr at1 at2 at3 at4  continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
-	xchal_sa_start	\continue, \ofs
-	// Optional global registers used by default by the compiler:
-	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
-	xchal_sa_align	\ptr, 0, 1016, 4, 4
-	rur.THREADPTR	\at1		// threadptr option
-	s32i	\at1, \ptr, .Lxchal_ofs_+0
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
-	.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
-	xchal_sa_align	\ptr, 0, 1016, 4, 4
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
-	.endif
-	// Optional caller-saved registers used by default by the compiler:
-	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select)
-	xchal_sa_align	\ptr, 0, 1012, 4, 4
-	rsr.ACCLO	\at1		// MAC16 option
-	s32i	\at1, \ptr, .Lxchal_ofs_+0
-	rsr.ACCHI	\at1		// MAC16 option
-	s32i	\at1, \ptr, .Lxchal_ofs_+4
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 8
-	.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
-	xchal_sa_align	\ptr, 0, 1012, 4, 4
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 8
-	.endif
-	// Optional caller-saved registers not used by default by the compiler:
-	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
-	xchal_sa_align	\ptr, 0, 996, 4, 4
-	rsr.BR	\at1		// boolean option
-	s32i	\at1, \ptr, .Lxchal_ofs_+0
-	rsr.SCOMPARE1	\at1		// conditional store option
-	s32i	\at1, \ptr, .Lxchal_ofs_+4
-	rsr.M0	\at1		// MAC16 option
-	s32i	\at1, \ptr, .Lxchal_ofs_+8
-	rsr.M1	\at1		// MAC16 option
-	s32i	\at1, \ptr, .Lxchal_ofs_+12
-	rsr.M2	\at1		// MAC16 option
-	s32i	\at1, \ptr, .Lxchal_ofs_+16
-	rsr.M3	\at1		// MAC16 option
-	s32i	\at1, \ptr, .Lxchal_ofs_+20
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 24
-	.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
-	xchal_sa_align	\ptr, 0, 996, 4, 4
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 24
-	.endif
-    .endm	// xchal_ncp_store
-
-    /*
-      *  Macro to load all non-coprocessor (extra) custom TIE and optional state
-      *  (not including zero-overhead loop registers).
-      *  Required parameters:
-      *      ptr         Save area pointer address register (clobbered)
-      *                  (register must contain a 4 byte aligned address).
-      *      at1..at4    Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
-      *                  registers are clobbered, the remaining are unused).
-      *  Optional parameters:
-      *      continue    If macro invoked as part of a larger load sequence, set to 1
-      *                  if this is not the first in the sequence.  Defaults to 0.
-      *      ofs         Offset from start of larger sequence (from value of first ptr
-      *                  in sequence) at which to load.  Defaults to next available space
-      *                  (or 0 if <continue> is 0).
-      *      select      Select what category(ies) of registers to load, as a bitmask
-      *                  (see XTHAL_SAS_xxx constants).  Defaults to all registers.
-      *      alloc       Select what category(ies) of registers to allocate; if any
-      *                  category is selected here that is not in <select>, space for
-      *                  the corresponding registers is skipped without doing any load.
-      */
-    .macro xchal_ncp_load  ptr at1 at2 at3 at4  continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
-	xchal_sa_start	\continue, \ofs
-	// Optional global registers used by default by the compiler:
-	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
-	xchal_sa_align	\ptr, 0, 1016, 4, 4
-	l32i	\at1, \ptr, .Lxchal_ofs_+0
-	wur.THREADPTR	\at1		// threadptr option
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
-	.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
-	xchal_sa_align	\ptr, 0, 1016, 4, 4
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
-	.endif
-	// Optional caller-saved registers used by default by the compiler:
-	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select)
-	xchal_sa_align	\ptr, 0, 1012, 4, 4
-	l32i	\at1, \ptr, .Lxchal_ofs_+0
-	wsr.ACCLO	\at1		// MAC16 option
-	l32i	\at1, \ptr, .Lxchal_ofs_+4
-	wsr.ACCHI	\at1		// MAC16 option
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 8
-	.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
-	xchal_sa_align	\ptr, 0, 1012, 4, 4
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 8
-	.endif
-	// Optional caller-saved registers not used by default by the compiler:
-	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
-	xchal_sa_align	\ptr, 0, 996, 4, 4
-	l32i	\at1, \ptr, .Lxchal_ofs_+0
-	wsr.BR	\at1		// boolean option
-	l32i	\at1, \ptr, .Lxchal_ofs_+4
-	wsr.SCOMPARE1	\at1		// conditional store option
-	l32i	\at1, \ptr, .Lxchal_ofs_+8
-	wsr.M0	\at1		// MAC16 option
-	l32i	\at1, \ptr, .Lxchal_ofs_+12
-	wsr.M1	\at1		// MAC16 option
-	l32i	\at1, \ptr, .Lxchal_ofs_+16
-	wsr.M2	\at1		// MAC16 option
-	l32i	\at1, \ptr, .Lxchal_ofs_+20
-	wsr.M3	\at1		// MAC16 option
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 24
-	.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
-	xchal_sa_align	\ptr, 0, 996, 4, 4
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 24
-	.endif
-    .endm	// xchal_ncp_load
-
-
-#define XCHAL_NCP_NUM_ATMPS	1
-
-    /* 
-     *  Macro to store the state of TIE coprocessor FPU.
-     *  Required parameters:
-     *      ptr         Save area pointer address register (clobbered)
-     *                  (register must contain a 8 byte aligned address).
-     *      at1..at4    Four temporary address registers (first XCHAL_CP0_NUM_ATMPS
-     *                  registers are clobbered, the remaining are unused).
-     *  Optional parameters are the same as for xchal_ncp_store.
-     */
-#define xchal_cp_FPU_store	xchal_cp0_store
-    .macro	xchal_cp0_store  ptr at1 at2 at3 at4  continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
-	xchal_sa_start \continue, \ofs
-	// Custom caller-saved registers not used by default by the compiler:
-	.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
-	xchal_sa_align	\ptr, 0, 1008, 8, 8
-	rur.FCR	\at1		// ureg 232
-	s32i	\at1, \ptr, .Lxchal_ofs_+0
-	rur.FSR	\at1		// ureg 233
-	s32i	\at1, \ptr, .Lxchal_ofs_+4
-	sdi	f0, \ptr, .Lxchal_ofs_+8
-	sdi	f1, \ptr, .Lxchal_ofs_+16
-	sdi	f2, \ptr, .Lxchal_ofs_+24
-	sdi	f3, \ptr, .Lxchal_ofs_+32
-	sdi	f4, \ptr, .Lxchal_ofs_+40
-	sdi	f5, \ptr, .Lxchal_ofs_+48
-	sdi	f6, \ptr, .Lxchal_ofs_+56
-	sdi	f7, \ptr, .Lxchal_ofs_+64
-	sdi	f8, \ptr, .Lxchal_ofs_+72
-	sdi	f9, \ptr, .Lxchal_ofs_+80
-	sdi	f10, \ptr, .Lxchal_ofs_+88
-	sdi	f11, \ptr, .Lxchal_ofs_+96
-	sdi	f12, \ptr, .Lxchal_ofs_+104
-	sdi	f13, \ptr, .Lxchal_ofs_+112
-	sdi	f14, \ptr, .Lxchal_ofs_+120
-	sdi	f15, \ptr, .Lxchal_ofs_+128
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 136
-	.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
-	xchal_sa_align	\ptr, 0, 1008, 8, 8
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 136
-	.endif
-    .endm	// xchal_cp0_store
-
-    /* 
-     *  Macro to load the state of TIE coprocessor FPU.
-     *  Required parameters:
-     *      ptr         Save area pointer address register (clobbered)
-     *                  (register must contain a 8 byte aligned address).
-     *      at1..at4    Four temporary address registers (first XCHAL_CP0_NUM_ATMPS
-     *                  registers are clobbered, the remaining are unused).
-     *  Optional parameters are the same as for xchal_ncp_load.
-     */
-#define xchal_cp_FPU_load	xchal_cp0_load
-    .macro	xchal_cp0_load  ptr at1 at2 at3 at4  continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
-	xchal_sa_start \continue, \ofs
-	// Custom caller-saved registers not used by default by the compiler:
-	.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
-	xchal_sa_align	\ptr, 0, 1008, 8, 8
-	l32i	\at1, \ptr, .Lxchal_ofs_+0
-	wur.FCR	\at1		// ureg 232
-	l32i	\at1, \ptr, .Lxchal_ofs_+4
-	wur.FSR	\at1		// ureg 233
-	ldi	f0, \ptr, .Lxchal_ofs_+8
-	ldi	f1, \ptr, .Lxchal_ofs_+16
-	ldi	f2, \ptr, .Lxchal_ofs_+24
-	ldi	f3, \ptr, .Lxchal_ofs_+32
-	ldi	f4, \ptr, .Lxchal_ofs_+40
-	ldi	f5, \ptr, .Lxchal_ofs_+48
-	ldi	f6, \ptr, .Lxchal_ofs_+56
-	ldi	f7, \ptr, .Lxchal_ofs_+64
-	ldi	f8, \ptr, .Lxchal_ofs_+72
-	ldi	f9, \ptr, .Lxchal_ofs_+80
-	ldi	f10, \ptr, .Lxchal_ofs_+88
-	ldi	f11, \ptr, .Lxchal_ofs_+96
-	ldi	f12, \ptr, .Lxchal_ofs_+104
-	ldi	f13, \ptr, .Lxchal_ofs_+112
-	ldi	f14, \ptr, .Lxchal_ofs_+120
-	ldi	f15, \ptr, .Lxchal_ofs_+128
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 136
-	.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
-	xchal_sa_align	\ptr, 0, 1008, 8, 8
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 136
-	.endif
-    .endm	// xchal_cp0_load
-
-#define XCHAL_CP0_NUM_ATMPS	1
-    /* 
-     *  Macro to store the state of TIE coprocessor AudioEngineLX.
-     *  Required parameters:
-     *      ptr         Save area pointer address register (clobbered)
-     *                  (register must contain a 8 byte aligned address).
-     *      at1..at4    Four temporary address registers (first XCHAL_CP1_NUM_ATMPS
-     *                  registers are clobbered, the remaining are unused).
-     *  Optional parameters are the same as for xchal_ncp_store.
-     */
-#define xchal_cp_AudioEngineLX_store	xchal_cp1_store
-    .macro	xchal_cp1_store  ptr at1 at2 at3 at4  continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
-	xchal_sa_start \continue, \ofs
-	// Custom caller-saved registers not used by default by the compiler:
-	.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
-	xchal_sa_align	\ptr, 0, 0, 8, 8
-	rur.AE_OVF_SAR	\at1		// ureg 240
-	s32i	\at1, \ptr, .Lxchal_ofs_+0
-	rur.AE_BITHEAD	\at1		// ureg 241
-	s32i	\at1, \ptr, .Lxchal_ofs_+4
-	rur.AE_TS_FTS_BU_BP	\at1		// ureg 242
-	s32i	\at1, \ptr, .Lxchal_ofs_+8
-	rur.AE_CW_SD_NO	\at1		// ureg 243
-	s32i	\at1, \ptr, .Lxchal_ofs_+12
-	rur.AE_CBEGIN0	\at1		// ureg 246
-	s32i	\at1, \ptr, .Lxchal_ofs_+16
-	rur.AE_CEND0	\at1		// ureg 247
-	s32i	\at1, \ptr, .Lxchal_ofs_+20
-	ae_s64.i	aed0, \ptr, .Lxchal_ofs_+24
-	ae_s64.i	aed1, \ptr, .Lxchal_ofs_+32
-	ae_s64.i	aed2, \ptr, .Lxchal_ofs_+40
-	ae_s64.i	aed3, \ptr, .Lxchal_ofs_+48
-	ae_s64.i	aed4, \ptr, .Lxchal_ofs_+56
-	addi	\ptr, \ptr, 64
-	ae_s64.i	aed5, \ptr, .Lxchal_ofs_+0
-	ae_s64.i	aed6, \ptr, .Lxchal_ofs_+8
-	ae_s64.i	aed7, \ptr, .Lxchal_ofs_+16
-	ae_s64.i	aed8, \ptr, .Lxchal_ofs_+24
-	ae_s64.i	aed9, \ptr, .Lxchal_ofs_+32
-	ae_s64.i	aed10, \ptr, .Lxchal_ofs_+40
-	ae_s64.i	aed11, \ptr, .Lxchal_ofs_+48
-	ae_s64.i	aed12, \ptr, .Lxchal_ofs_+56
-	addi	\ptr, \ptr, 64
-	ae_s64.i	aed13, \ptr, .Lxchal_ofs_+0
-	ae_s64.i	aed14, \ptr, .Lxchal_ofs_+8
-	ae_s64.i	aed15, \ptr, .Lxchal_ofs_+16
-	ae_salign64.i	u0, \ptr, .Lxchal_ofs_+24
-	ae_salign64.i	u1, \ptr, .Lxchal_ofs_+32
-	ae_salign64.i	u2, \ptr, .Lxchal_ofs_+40
-	ae_salign64.i	u3, \ptr, .Lxchal_ofs_+48
-	.set	.Lxchal_pofs_, .Lxchal_pofs_ + 128
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 56
-	.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
-	xchal_sa_align	\ptr, 0, 0, 8, 8
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 184
-	.endif
-    .endm	// xchal_cp1_store
-
-    /* 
-     *  Macro to load the state of TIE coprocessor AudioEngineLX.
-     *  Required parameters:
-     *      ptr         Save area pointer address register (clobbered)
-     *                  (register must contain a 8 byte aligned address).
-     *      at1..at4    Four temporary address registers (first XCHAL_CP1_NUM_ATMPS
-     *                  registers are clobbered, the remaining are unused).
-     *  Optional parameters are the same as for xchal_ncp_load.
-     */
-#define xchal_cp_AudioEngineLX_load	xchal_cp1_load
-    .macro	xchal_cp1_load  ptr at1 at2 at3 at4  continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
-	xchal_sa_start \continue, \ofs
-	// Custom caller-saved registers not used by default by the compiler:
-	.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
-	xchal_sa_align	\ptr, 0, 0, 8, 8
-	l32i	\at1, \ptr, .Lxchal_ofs_+0
-	wur.AE_OVF_SAR	\at1		// ureg 240
-	l32i	\at1, \ptr, .Lxchal_ofs_+4
-	wur.AE_BITHEAD	\at1		// ureg 241
-	l32i	\at1, \ptr, .Lxchal_ofs_+8
-	wur.AE_TS_FTS_BU_BP	\at1		// ureg 242
-	l32i	\at1, \ptr, .Lxchal_ofs_+12
-	wur.AE_CW_SD_NO	\at1		// ureg 243
-	l32i	\at1, \ptr, .Lxchal_ofs_+16
-	wur.AE_CBEGIN0	\at1		// ureg 246
-	l32i	\at1, \ptr, .Lxchal_ofs_+20
-	wur.AE_CEND0	\at1		// ureg 247
-	ae_l64.i	aed0, \ptr, .Lxchal_ofs_+24
-	ae_l64.i	aed1, \ptr, .Lxchal_ofs_+32
-	ae_l64.i	aed2, \ptr, .Lxchal_ofs_+40
-	ae_l64.i	aed3, \ptr, .Lxchal_ofs_+48
-	ae_l64.i	aed4, \ptr, .Lxchal_ofs_+56
-	addi	\ptr, \ptr, 64
-	ae_l64.i	aed5, \ptr, .Lxchal_ofs_+0
-	ae_l64.i	aed6, \ptr, .Lxchal_ofs_+8
-	ae_l64.i	aed7, \ptr, .Lxchal_ofs_+16
-	ae_l64.i	aed8, \ptr, .Lxchal_ofs_+24
-	ae_l64.i	aed9, \ptr, .Lxchal_ofs_+32
-	ae_l64.i	aed10, \ptr, .Lxchal_ofs_+40
-	ae_l64.i	aed11, \ptr, .Lxchal_ofs_+48
-	ae_l64.i	aed12, \ptr, .Lxchal_ofs_+56
-	addi	\ptr, \ptr, 64
-	ae_l64.i	aed13, \ptr, .Lxchal_ofs_+0
-	ae_l64.i	aed14, \ptr, .Lxchal_ofs_+8
-	ae_l64.i	aed15, \ptr, .Lxchal_ofs_+16
-	addi	\ptr, \ptr, 24
-	ae_lalign64.i	u0, \ptr, .Lxchal_ofs_+0
-	ae_lalign64.i	u1, \ptr, .Lxchal_ofs_+8
-	ae_lalign64.i	u2, \ptr, .Lxchal_ofs_+16
-	ae_lalign64.i	u3, \ptr, .Lxchal_ofs_+24
-	.set	.Lxchal_pofs_, .Lxchal_pofs_ + 152
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 32
-	.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
-	xchal_sa_align	\ptr, 0, 0, 8, 8
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 184
-	.endif
-    .endm	// xchal_cp1_load
-
-#define XCHAL_CP1_NUM_ATMPS	1
-#define XCHAL_SA_NUM_ATMPS	1
-
-	/*  Empty macros for unconfigured coprocessors:  */
-	.macro xchal_cp2_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp2_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp3_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp3_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp4_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp4_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp5_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp5_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp6_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp6_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp7_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp7_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-
-#endif /*_XTENSA_CORE_TIE_ASM_H*/
-
diff --git a/src/platform/amd/renoir/include/arch/xtensa/config/tie.h b/src/platform/amd/renoir/include/arch/xtensa/config/tie.h
deleted file mode 100644
index 697f28a6b840..000000000000
--- a/src/platform/amd/renoir/include/arch/xtensa/config/tie.h
+++ /dev/null
@@ -1,208 +0,0 @@
-/* 
- * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
- *
- *  NOTE:  This header file is not meant to be included directly.
- */
-
-/* This header file describes this specific Xtensa processor's TIE extensions
-   that extend basic Xtensa core functionality.  It is customized to this
-   Xtensa processor configuration.
-
-   Customer ID=12153; Build=0x72343; Copyright (c) 1999-2018 Cadence Design Systems Inc.
-
-   Permission is hereby granted, free of charge, to any person obtaining
-   a copy of this software and associated documentation files (the
-   "Software"), to deal in the Software without restriction, including
-   without limitation the rights to use, copy, modify, merge, publish,
-   distribute, sublicense, and/or sell copies of the Software, and to
-   permit persons to whom the Software is furnished to do so, subject to
-   the following conditions:
-
-   The above copyright notice and this permission notice shall be included
-   in all copies or substantial portions of the Software.
-
-   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
-
-#ifndef _XTENSA_CORE_TIE_H
-#define _XTENSA_CORE_TIE_H
-
-#define XCHAL_CP_NUM			2	/* number of coprocessors */
-#define XCHAL_CP_MAX			2	/* max CP ID + 1 (0 if none) */
-#define XCHAL_CP_MASK			0x03	/* bitmask of all CPs by ID */
-#define XCHAL_CP_PORT_MASK		0x00	/* bitmask of only port CPs */
-
-/*  Basic parameters of each coprocessor:  */
-#define XCHAL_CP0_NAME			"FPU"
-#define XCHAL_CP0_IDENT			FPU
-#define XCHAL_CP0_SA_SIZE		136	/* size of state save area */
-#define XCHAL_CP0_SA_ALIGN		8	/* min alignment of save area */
-#define XCHAL_CP_ID_FPU             	0	/* coprocessor ID (0..7) */
-#define XCHAL_CP1_NAME			"AudioEngineLX"
-#define XCHAL_CP1_IDENT			AudioEngineLX
-#define XCHAL_CP1_SA_SIZE		184	/* size of state save area */
-#define XCHAL_CP1_SA_ALIGN		8	/* min alignment of save area */
-#define XCHAL_CP_ID_AUDIOENGINELX   	1	/* coprocessor ID (0..7) */
-
-/*  Filler info for unassigned coprocessors, to simplify arrays etc:  */
-#define XCHAL_CP2_SA_SIZE		0
-#define XCHAL_CP2_SA_ALIGN		1
-#define XCHAL_CP3_SA_SIZE		0
-#define XCHAL_CP3_SA_ALIGN		1
-#define XCHAL_CP4_SA_SIZE		0
-#define XCHAL_CP4_SA_ALIGN		1
-#define XCHAL_CP5_SA_SIZE		0
-#define XCHAL_CP5_SA_ALIGN		1
-#define XCHAL_CP6_SA_SIZE		0
-#define XCHAL_CP6_SA_ALIGN		1
-#define XCHAL_CP7_SA_SIZE		0
-#define XCHAL_CP7_SA_ALIGN		1
-
-/*  Save area for non-coprocessor optional and custom (TIE) state:  */
-#define XCHAL_NCP_SA_SIZE		36
-#define XCHAL_NCP_SA_ALIGN		4
-
-/*  Total save area for optional and custom state (NCP + CPn):  */
-#define XCHAL_TOTAL_SA_SIZE		368	/* with 16-byte align padding */
-#define XCHAL_TOTAL_SA_ALIGN		8	/* actual minimum alignment */
-
-/*
- * Detailed contents of save areas.
- * NOTE:  caller must define the XCHAL_SA_REG macro (not defined here)
- * before expanding the XCHAL_xxx_SA_LIST() macros.
- *
- * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
- *		dbnum,base,regnum,bitsz,gapsz,reset,x...)
- *
- *	s = passed from XCHAL_*_LIST(s), eg. to select how to expand
- *	ccused = set if used by compiler without special options or code
- *	abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
- *	kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
- *	opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg)
- *	name = lowercase reg name (no quotes)
- *	galign = group byte alignment (power of 2) (galign >= align)
- *	align = register byte alignment (power of 2)
- *	asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz)
- *	  (not including any pad bytes required to galign this or next reg)
- *	dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>)
- *	base = reg shortname w/o index (or sr=special, ur=TIE user reg)
- *	regnum = reg index in regfile, or special/TIE-user reg number
- *	bitsz = number of significant bits (regfile width, or ur/sr mask bits)
- *	gapsz = intervening bits, if bitsz bits not stored contiguously
- *	(padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize)
- *	reset = register reset value (or 0 if undefined at reset)
- *	x = reserved for future use (0 until then)
- *
- *  To filter out certain registers, e.g. to expand only the non-global
- *  registers used by the compiler, you can do something like this:
- *
- *  #define XCHAL_SA_REG(s,ccused,p...)	SELCC##ccused(p)
- *  #define SELCC0(p...)
- *  #define SELCC1(abikind,p...)	SELAK##abikind(p)
- *  #define SELAK0(p...)		REG(p)
- *  #define SELAK1(p...)		REG(p)
- *  #define SELAK2(p...)
- *  #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \
- *		...what you want to expand...
- */
-
-#define XCHAL_NCP_SA_NUM	9
-#define XCHAL_NCP_SA_LIST(s)	\
- XCHAL_SA_REG(s,1,2,1,1,      threadptr, 4, 4, 4,0x03E7,  ur,231, 32,0,0,0) \
- XCHAL_SA_REG(s,1,0,0,1,          acclo, 4, 4, 4,0x0210,  sr,16 , 32,0,0,0) \
- XCHAL_SA_REG(s,1,0,0,1,          acchi, 4, 4, 4,0x0211,  sr,17 ,  8,0,0,0) \
- XCHAL_SA_REG(s,0,0,0,1,             br, 4, 4, 4,0x0204,  sr,4  , 16,0,0,0) \
- XCHAL_SA_REG(s,0,0,0,1,      scompare1, 4, 4, 4,0x020C,  sr,12 , 32,0,0,0) \
- XCHAL_SA_REG(s,0,0,0,1,             m0, 4, 4, 4,0x0220,  sr,32 , 32,0,0,0) \
- XCHAL_SA_REG(s,0,0,0,1,             m1, 4, 4, 4,0x0221,  sr,33 , 32,0,0,0) \
- XCHAL_SA_REG(s,0,0,0,1,             m2, 4, 4, 4,0x0222,  sr,34 , 32,0,0,0) \
- XCHAL_SA_REG(s,0,0,0,1,             m3, 4, 4, 4,0x0223,  sr,35 , 32,0,0,0)
-
-#define XCHAL_CP0_SA_NUM	18
-#define XCHAL_CP0_SA_LIST(s)	\
- XCHAL_SA_REG(s,0,0,1,0,            fcr, 8, 4, 4,0x03E8,  ur,232, 32,0,0,0) \
- XCHAL_SA_REG(s,0,0,1,0,            fsr, 4, 4, 4,0x03E9,  ur,233, 32,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,             f0, 8, 8, 8,0x0030,   f,0  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,             f1, 8, 8, 8,0x0031,   f,1  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,             f2, 8, 8, 8,0x0032,   f,2  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,             f3, 8, 8, 8,0x0033,   f,3  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,             f4, 8, 8, 8,0x0034,   f,4  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,             f5, 8, 8, 8,0x0035,   f,5  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,             f6, 8, 8, 8,0x0036,   f,6  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,             f7, 8, 8, 8,0x0037,   f,7  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,             f8, 8, 8, 8,0x0038,   f,8  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,             f9, 8, 8, 8,0x0039,   f,9  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,            f10, 8, 8, 8,0x003A,   f,10 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,            f11, 8, 8, 8,0x003B,   f,11 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,            f12, 8, 8, 8,0x003C,   f,12 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,            f13, 8, 8, 8,0x003D,   f,13 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,            f14, 8, 8, 8,0x003E,   f,14 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,            f15, 8, 8, 8,0x003F,   f,15 , 64,0,0,0)
-
-#define XCHAL_CP1_SA_NUM	26
-#define XCHAL_CP1_SA_LIST(s)	\
- XCHAL_SA_REG(s,0,0,1,0,     ae_ovf_sar, 8, 4, 4,0x03F0,  ur,240,  8,0,0,0) \
- XCHAL_SA_REG(s,0,0,1,0,     ae_bithead, 4, 4, 4,0x03F1,  ur,241, 32,0,0,0) \
- XCHAL_SA_REG(s,0,0,1,0,ae_ts_fts_bu_bp, 4, 4, 4,0x03F2,  ur,242, 16,0,0,0) \
- XCHAL_SA_REG(s,0,0,1,0,    ae_cw_sd_no, 4, 4, 4,0x03F3,  ur,243, 29,0,0,0) \
- XCHAL_SA_REG(s,0,0,1,0,     ae_cbegin0, 4, 4, 4,0x03F6,  ur,246, 32,0,0,0) \
- XCHAL_SA_REG(s,0,0,1,0,       ae_cend0, 4, 4, 4,0x03F7,  ur,247, 32,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aed0, 8, 8, 8,0x1010, aed,0  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aed1, 8, 8, 8,0x1011, aed,1  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aed2, 8, 8, 8,0x1012, aed,2  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aed3, 8, 8, 8,0x1013, aed,3  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aed4, 8, 8, 8,0x1014, aed,4  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aed5, 8, 8, 8,0x1015, aed,5  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aed6, 8, 8, 8,0x1016, aed,6  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aed7, 8, 8, 8,0x1017, aed,7  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aed8, 8, 8, 8,0x1018, aed,8  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aed9, 8, 8, 8,0x1019, aed,9  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed10, 8, 8, 8,0x101A, aed,10 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed11, 8, 8, 8,0x101B, aed,11 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed12, 8, 8, 8,0x101C, aed,12 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed13, 8, 8, 8,0x101D, aed,13 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed14, 8, 8, 8,0x101E, aed,14 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed15, 8, 8, 8,0x101F, aed,15 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,             u0, 8, 8, 8,0x1020,   u,0  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,             u1, 8, 8, 8,0x1021,   u,1  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,             u2, 8, 8, 8,0x1022,   u,2  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,             u3, 8, 8, 8,0x1023,   u,3  , 64,0,0,0)
-
-#define XCHAL_CP2_SA_NUM	0
-#define XCHAL_CP2_SA_LIST(s)	/* empty */
-
-#define XCHAL_CP3_SA_NUM	0
-#define XCHAL_CP3_SA_LIST(s)	/* empty */
-
-#define XCHAL_CP4_SA_NUM	0
-#define XCHAL_CP4_SA_LIST(s)	/* empty */
-
-#define XCHAL_CP5_SA_NUM	0
-#define XCHAL_CP5_SA_LIST(s)	/* empty */
-
-#define XCHAL_CP6_SA_NUM	0
-#define XCHAL_CP6_SA_LIST(s)	/* empty */
-
-#define XCHAL_CP7_SA_NUM	0
-#define XCHAL_CP7_SA_LIST(s)	/* empty */
-
-/* Byte length of instruction from its first nibble (op0 field), per FLIX.  */
-#define XCHAL_OP0_FORMAT_LENGTHS	3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8
-/* Byte length of instruction from its first byte, per FLIX.  */
-#define XCHAL_BYTE0_FORMAT_LENGTHS	\
-	3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8,\
-	3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8,\
-	3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8,\
-	3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8,\
-	3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8,\
-	3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8,\
-	3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8,\
-	3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8
-
-#endif /*_XTENSA_CORE_TIE_H*/
-
diff --git a/src/platform/amd/renoir/include/platform/chip_offset_byte.h b/src/platform/amd/renoir/include/platform/chip_offset_byte.h
deleted file mode 100644
index b8f670f9b570..000000000000
--- a/src/platform/amd/renoir/include/platform/chip_offset_byte.h
+++ /dev/null
@@ -1,122 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- *
- * Copyright(c) 2021 AMD.All rights reserved.
- *
- * Author:      Basavaraj Hiregoudar <basavaraj.hiregoudar@amd.com>
- *              Anup Kulkarni <anup.kulkarni@amd.com>
- *              Bala Kishore <balakishore.pati@amd.com>
- */
-#ifndef _rn_OFFSET_HEADER
-#define _rn_OFFSET_HEADER
-
-#define PU_REGISTER_BASE        (0x22040000 - 0x01240000)
-
-/* Registers from ACP_DMA block */
-#define ACP_DMA_CNTL_0                                0x1240000
-#define ACP_DMA_DESC_BASE_ADDR                        0x12400E0
-#define ACP_DMA_DESC_MAX_NUM_DSCR                     0x12400E4
-#define ACP_DMA_CH_STS                                0x12400E8
-
-#define ACP_DMA_DSCR_STRT_IDX_0                       0x1240020
-#define ACP_DMA_DSCR_CNT_0                            0x1240040
-#define ACP_DMA_PRIO_0                                0x1240060
-
-/* Registers from ACP_MISC block */
-#define ACP_CLKMUX_SEL				      0x1241424
-#define ACP_EXTERNAL_INTR_ENB                         0x1241800
-#define ACP_EXTERNAL_INTR_STAT                        0x1241808
-#define ACP_DSP0_INTR_CNTL                            0x124180C
-#define ACP_DSP0_INTR_STAT                            0x1241810
-#define ACP_DSP_SW_INTR_CNTL                          0x1241814
-#define ACP_DSP_SW_INTR_STAT                          0x1241818
-#define ACP_SW_INTR_TRIG                              0x124181C
-#define ACP_SMU_MAILBOX                               0x1241820
-#define DSP_INTERRUPT_ROUTING_CTRL                    0x1241824
-#define ACP_FUTURE_REG_ACLK_0                         0x1241860
-#define ACP_TIMER                                     0x1241874
-#define ACP_TIMER_CNTL                                0x1241878
-#define ACP_AXI2DAGB_SEM_0			      0x1241880
-
-#define ACP_SRBM_CLIENT_BASE_ADDR                     0x1241BBC
-#define ACP_SRBM_Client_RDDATA                        0x1241BC0
-#define ACP_SRBM_CYCLE_STS                            0x1241BC4
-#define ACP_SRBM_CLIENT_CONFIG                        0x1241BC8
-
-/* Registers from ACP_AUDIO_BUFFERS block */
-#define ACP_I2S_RX_RINGBUFADDR                        0x1242000
-#define ACP_I2S_RX_RINGBUFSIZE                        0x1242004
-#define ACP_I2S_RX_LINKPOSITIONCNTR                   0x1242008
-#define ACP_I2S_RX_FIFOADDR                           0x124200C
-#define ACP_I2S_RX_FIFOSIZE                           0x1242010
-#define ACP_I2S_RX_DMA_SIZE                           0x1242014
-#define ACP_I2S_RX_LINEARPOSITIONCNTR_HIGH            0x1242018
-#define ACP_I2S_RX_LINEARPOSITIONCNTR_LOW             0x124201C
-#define ACP_I2S_RX_INTR_WATERMARK_SIZE                0x1242020
-#define ACP_I2S_TX_RINGBUFADDR                        0x1242024
-#define ACP_I2S_TX_RINGBUFSIZE                        0x1242028
-#define ACP_I2S_TX_LINKPOSITIONCNTR                   0x124202C
-#define ACP_I2S_TX_FIFOADDR                           0x1242030
-#define ACP_I2S_TX_FIFOSIZE                           0x1242034
-#define ACP_I2S_TX_DMA_SIZE                           0x1242038
-#define ACP_I2S_TX_LINEARPOSITIONCNTR_HIGH            0x124203C
-#define ACP_I2S_TX_LINEARPOSITIONCNTR_LOW             0x1242040
-#define ACP_I2S_TX_INTR_WATERMARK_SIZE                0x1242044
-#define ACP_BT_RX_RINGBUFADDR                         0x1242048
-#define ACP_BT_RX_RINGBUFSIZE                         0x124204C
-#define ACP_BT_RX_LINKPOSITIONCNTR                    0x1242050
-#define ACP_BT_RX_FIFOADDR                            0x1242054
-#define ACP_BT_RX_FIFOSIZE                            0x1242058
-#define ACP_BT_RX_DMA_SIZE                            0x124205C
-#define ACP_BT_RX_LINEARPOSITIONCNTR_HIGH             0x1242060
-#define ACP_BT_RX_LINEARPOSITIONCNTR_LOW              0x1242064
-#define ACP_BT_RX_INTR_WATERMARK_SIZE                 0x1242068
-#define ACP_BT_TX_RINGBUFADDR                         0x124206C
-#define ACP_BT_TX_RINGBUFSIZE                         0x1242070
-#define ACP_BT_TX_LINKPOSITIONCNTR                    0x1242074
-#define ACP_BT_TX_FIFOADDR                            0x1242078
-#define ACP_BT_TX_FIFOSIZE                            0x124207C
-#define ACP_BT_TX_DMA_SIZE                            0x1242080
-#define ACP_BT_TX_LINEARPOSITIONCNTR_HIGH             0x1242084
-#define ACP_BT_TX_LINEARPOSITIONCNTR_LOW              0x1242088
-#define ACP_BT_TX_INTR_WATERMARK_SIZE                 0x124208C
-
-/* Registers from ACP_I2S_TDM block */
-#define ACP_I2STDM_IER                                0x1242400
-#define ACP_I2STDM_IRER                               0x1242404
-#define ACP_I2STDM_RXFRMT                             0x1242408
-#define ACP_I2STDM_ITER                               0x124240C
-#define ACP_I2STDM_TXFRMT                             0x1242410
-
-
-/* Registers from ACP_BT_TDM block */
-#define ACP_BTTDM_IER                                 0x1242800
-#define ACP_BTTDM_IRER                                0x1242804
-#define ACP_BTTDM_RXFRMT                              0x1242808
-#define ACP_BTTDM_ITER                                0x124280C
-#define ACP_BTTDM_TXFRMT                              0x1242810
-
-
-/* Registers from ACP_WOV block */
-#define ACP_WOV_VAD_ENABLE                            0x1242C00
-#define ACP_WOV_PDM_ENABLE                            0x1242C04
-#define ACP_WOV_PDM_DMA_ENABLE                        0x1242C08
-#define ACP_WOV_RX_RINGBUFADDR                        0x1242C0C
-#define ACP_WOV_RX_RINGBUFSIZE                        0x1242C10
-#define ACP_WOV_RX_LINKPOSITIONCNTR                   0x1242C14
-#define ACP_WOV_RX_LINEARPOSITIONCNTR_HIGH            0x1242C18
-#define ACP_WOV_RX_LINEARPOSITIONCNTR_LOW             0x1242C1C
-#define ACP_WOV_RX_INTR_WATERMARK_SIZE                0x1242C20
-#define ACP_WOV_PDM_FIFO_FLUSH                        0x1242C24
-#define ACP_WOV_PDM_NO_OF_CHANNELS                    0x1242C28
-#define ACP_WOV_PDM_DECIMATION_FACTOR                 0x1242C2C
-#define ACP_WOV_PDM_VAD_CTRL                          0x1242C30
-
-#define ACP_WOV_MISC_CTRL                             0x1242C5C
-#define ACP_WOV_CLK_CTRL                              0x1242C60
-#define ACP_PDM_VAD_DYNAMIC_CLK_GATING_EN             0x1242C64
-#define ACP_WOV_ERROR_STATUS_REGISTER                 0x1242C68
-
-#define MP1_SMN_C2PMSG_69                             0x58A14
-#define MP1_SMN_C2PMSG_85                             0x58A54
-#define MP1_SMN_C2PMSG_93                             0x58A74
-#endif
diff --git a/src/platform/amd/renoir/include/platform/chip_registers.h b/src/platform/amd/renoir/include/platform/chip_registers.h
deleted file mode 100644
index 643050afb9f9..000000000000
--- a/src/platform/amd/renoir/include/platform/chip_registers.h
+++ /dev/null
@@ -1,546 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- *
- * Copyright(c) 2021 AMD.All rights reserved.
- *
- * Author:      Basavaraj Hiregoudar <basavaraj.hiregoudar@amd.com>
- *              Anup Kulkarni <anup.kulkarni@amd.com>
- *              Bala Kishore <balakishore.pati@amd.com>
- */
-#if !defined(_RN_REG_HEADER)
-#define _RN_REG_HEADER
-
-typedef	union acp_dma_cntl_0 {
-	struct {
-	unsigned int	dmachrst:1;
-	unsigned int	dmachrun:1;
-	unsigned int	dmachiocen:1;
-	unsigned int	:29;
-	} bits;
-unsigned int	u32all;
-} acp_dma_cntl_0_t;
-
-typedef	union acp_dma_ch_sts {
-	struct {
-	unsigned int	dmachrunsts:8;
-	unsigned int	:24;
-	} bits;
-unsigned int	u32all;
-} acp_dma_ch_sts_t;
-
-typedef	union acp_external_intr_enb {
-	struct {
-	unsigned int	acpextintrenb:1;
-	unsigned int	:31;
-	} bits;
-unsigned int	u32all;
-} acp_external_intr_enb_t;
-
-typedef	union acp_dsp0_intr_cntl {
-	struct {
-	unsigned int	dmaiocmask:8;
-	unsigned int	:8;
-	unsigned int	wov_dma_intr_mask:1;
-	unsigned int	:6;
-	unsigned int	audio_buffer_int_mask:6;
-	unsigned int	:3;
-	} bits;
-unsigned int	u32all;
-} acp_dsp0_intr_cntl_t;
-
-typedef	union acp_dsp0_intr_stat {
-	struct {
-	unsigned int	dmaiocstat:8;
-	unsigned int	:8;
-	unsigned int	wov_dma_stat:1;
-	unsigned int	:6;
-	unsigned int	audio_buffer_int_stat:6;
-	unsigned int	:3;
-	} bits;
-unsigned int	u32all;
-} acp_dsp0_intr_stat_t;
-
-typedef	union acp_dsp_sw_intr_cntl {
-	struct {
-	unsigned int	:2;
-	unsigned int	dsp0_to_host_intr_mask:1;
-	unsigned int	:29;
-	} bits;
-unsigned int	u32all;
-} acp_dsp_sw_intr_cntl_t;
-
-typedef	union acp_dsp_sw_intr_stat {
-	struct {
-	unsigned int	host_to_dsp0_intr1_stat:1;
-	unsigned int	host_to_dsp0_intr2_stat:1;
-	unsigned int	dsp0_to_host_intr_stat:1;
-	unsigned int	host_to_dsp0_intr3_stat:1;
-	unsigned int	:28;
-	} bits;
-unsigned int	u32all;
-} acp_dsp_sw_intr_stat_t;
-
-typedef	union acp_sw_intr_trig {
-	struct {
-	unsigned int	trig_host_to_dsp0_intr1:1;
-	unsigned int	:1;
-	unsigned int	trig_dsp0_to_host_intr:1;
-	unsigned int	:29;
-	} bits;
-unsigned int	u32all;
-} acp_sw_intr_trig_t;
-
-typedef	union dsp_interrupt_routing_ctrl {
-	struct {
-	unsigned int	dma_intr_level:2;
-	unsigned int	:14;
-	unsigned int	az_sw_i2s_intr_level:2;
-	unsigned int	:2;
-	unsigned int	host_to_dsp_intr1_level:2;
-	unsigned int	:8;
-	unsigned int	wov_intr_level:2;
-	} bits;
-unsigned int	u32all;
-} dsp_interrupt_routing_ctrl_t;
-
-typedef	union acp_i2s_rx_ringbufaddr {
-	struct {
-	unsigned int	i2s_rx_ringbufaddr:27;
-	unsigned int	:5;
-	} bits;
-unsigned int	u32all;
-} acp_i2s_rx_ringbufaddr_t;
-
-typedef	union acp_i2s_rx_ringbufsize {
-	struct {
-	unsigned int	i2s_rx_ringbufsize:26;
-	unsigned int	:6;
-	} bits;
-unsigned int	u32all;
-} acp_i2s_rx_ringbufsize_t;
-
-typedef	union acp_i2s_rx_linkpositioncntr {
-	struct {
-	unsigned int	i2s_rx_linkpositioncntr:26;
-	unsigned int	:6;
-	} bits;
-unsigned int	u32all;
-} acp_i2s_rx_linkpositioncntr_t;
-
-typedef	union acp_i2s_rx_fifoaddr {
-	struct {
-	unsigned int	i2s_rx_fifoaddr:27;
-	unsigned int	:5;
-	} bits;
-unsigned int	u32all;
-} acp_i2s_rx_fifoaddr_t;
-
-typedef	union acp_i2s_rx_fifosize {
-	struct {
-	unsigned int	i2s_rx_fifosize:13;
-	unsigned int	:19;
-	} bits;
-unsigned int	u32all;
-} acp_i2s_rx_fifosize_t;
-
-typedef	union acp_i2s_rx_dma_size {
-	struct {
-	unsigned int	i2s_rx_dma_size:13;
-	unsigned int	:19;
-	} bits;
-unsigned int	u32all;
-} acp_i2s_rx_dma_size_t;
-
-typedef	union acp_i2s_rx_linearpositioncntr_high {
-	struct {
-	unsigned int	i2s_rx_linearpositioncntr_high:32;
-	} bits;
-unsigned int	u32all;
-} acp_i2s_rx_linearpositioncntr_high_t;
-
-typedef	union acp_i2s_rx_linearpositioncntr_low {
-	struct {
-	unsigned int	i2s_rx_linearpositioncntr_low:32;
-	} bits;
-unsigned int	u32all;
-} acp_i2s_rx_linearpositioncntr_low_t;
-
-typedef	union acp_i2s_rx_watermark_size {
-	struct {
-	unsigned int	i2s_rx_intr_watermark_size:26;
-	unsigned int	:6;
-	} bits;
-unsigned int	u32all;
-} acp_i2s_rx_intr_watermark_size_t;
-
-typedef	union acp_i2s_tx_ringbufaddr {
-	struct {
-	unsigned int	i2s_tx_ringbufaddr:27;
-	unsigned int	:5;
-	} bits;
-unsigned int	u32all;
-} acp_i2s_tx_ringbufaddr_t;
-
-typedef	union acp_i2s_tx_ringbufsize {
-	struct {
-	unsigned int	i2s_tx_ringbufsize:26;
-	unsigned int	:6;
-	} bits;
-unsigned int	u32all;
-} acp_i2s_tx_ringbufsize_t;
-
-typedef	union acp_i2s_tx_linkpositioncntr {
-	struct {
-	unsigned int	i2s_tx_linkpositioncntr:26;
-	unsigned int	:6;
-	} bits;
-unsigned int	u32all;
-} acp_i2s_tx_linkpositioncntr_t;
-
-typedef	union acp_i2s_tx_fifoaddr {
-	struct {
-	unsigned int	i2s_tx_fifoaddr:27;
-	unsigned int	:5;
-	} bits;
-unsigned int	u32all;
-} acp_i2s_tx_fifoaddr_t;
-
-typedef	union acp_i2s_tx_fifosize {
-	struct {
-	unsigned int	i2s_tx_fifosize:13;
-	unsigned int	:19;
-	} bits;
-unsigned int	u32all;
-} acp_i2s_tx_fifosize_t;
-
-typedef	union acp_i2s_tx_dma_size {
-	struct {
-	unsigned int	i2s_tx_dma_size:13;
-	unsigned int	:19;
-	} bits;
-unsigned int	u32all;
-} acp_i2s_tx_dma_size_t;
-
-typedef	union acp_i2s_tx_linearpositioncntr_high {
-	struct {
-	unsigned int	i2s_tx_linearpositioncntr_high:32;
-	} bits;
-unsigned int	u32all;
-} acp_i2s_tx_linearpositioncntr_hight_t;
-
-typedef	union acp_i2s_tx_linearpositioncntr_low {
-	struct {
-	unsigned int	i2s_tx_linearpositioncntr_low:32;
-	} bits;
-unsigned int	u32all;
-} acp_i2s_tx_linearpositioncntr_low_t;
-
-typedef	union acp_i2s_tx_intr_watermark_size {
-	struct {
-	unsigned int	i2s_tx_intr_watermark_size:26;
-	unsigned int	:6;
-	} bits;
-unsigned int	u32all;
-} acp_i2s_tx_intr_watermark_size_t;
-
-typedef	union acp_bt_rx_ringbufaddr {
-	struct {
-	unsigned int	bt_rx_ringbufaddr:27;
-	unsigned int	:5;
-	} bits;
-unsigned int	u32all;
-} acp_bt_rx_ringbufaddr_t;
-
-typedef	union acp_bt_rx_ringbufsize {
-	struct {
-	unsigned int	bt_rx_ringbufsize:26;
-	unsigned int	:6;
-	} bits;
-unsigned int	u32all;
-} acp_bt_rx_ringbufsize_t;
-
-typedef	union acp_bt_rx_linkpositioncntr {
-	struct {
-	unsigned int	bt_rx_linkpositioncntr:26;
-	unsigned int	:6;
-	} bits;
-unsigned int	u32all;
-} acp_bt_rx_linkpositioncntr_t;
-
-typedef	union acp_bt_rx_fifoaddr {
-	struct {
-	unsigned int	bt_rx_fifoaddr:27;
-	unsigned int	:5;
-	} bits;
-unsigned int	u32all;
-} acp_bt_rx_fifoaddr_t;
-
-typedef	union acp_bt_rx_fifosize {
-	struct {
-	unsigned int	bt_rx_fifosize:13;
-	unsigned int	:19;
-	} bits;
-unsigned int	u32all;
-} acp_bt_rx_fifosize_t;
-
-typedef	union acp_bt_rx_dma_size {
-	struct {
-	unsigned int	bt_rx_dma_size:13;
-	unsigned int	:19;
-	} bits;
-unsigned int	u32all;
-} acp_bt_rx_dma_size_t;
-
-typedef	union acp_bt_rx_linearpositioncntr_high {
-	struct {
-	unsigned int	bt_rx_linearpositioncntr_high:32;
-	} bits;
-unsigned int	u32all;
-} acp_bt_rx_linearpositioncntr_high_t;
-
-typedef	union acp_bt_rx_linearpositioncntr_low {
-	struct {
-	unsigned int	bt_rx_linearpositioncntr_low:32;
-	} bits;
-unsigned int	u32all;
-} acp_bt_rx_linearpositioncntr_low_t;
-
-typedef	union acp_bt_rx_intr_watermark_size {
-	struct {
-	unsigned int	bt_rx_intr_watermark_size:26;
-	unsigned int	:6;
-	} bits;
-unsigned int	u32all;
-} acp_bt_rx_intr_watermark_size_t;
-
-typedef	union acp_bt_tx_ringbufaddr {
-	struct {
-	unsigned int	bt_tx_ringbufaddr:27;
-	unsigned int	:5;
-	} bits;
-unsigned int	u32all;
-} acp_bt_tx_ringbufaddr_t;
-
-typedef	union acp_bt_tx_ringbufsize {
-	struct {
-	unsigned int	bt_tx_ringbufsize:26;
-	unsigned int	:6;
-	} bits;
-unsigned int	u32all;
-} acp_bt_tx_ringbufsize_t;
-
-typedef	union acp_bt_tx_linkpositiontcntr {
-	struct {
-	unsigned int	bt_tx_linkpositioncntr:26;
-	unsigned int	:6;
-	} bits;
-unsigned int	u32all;
-} acp_bt_tx_linkpositiontcntr_t;
-
-typedef	union acp_bt_tx_fifoaddr {
-	struct {
-	unsigned int	bt_tx_fifoaddr:27;
-	unsigned int	:5;
-	} bits;
-unsigned int	u32all;
-} acp_bt_tx_fifoaddr_t;
-
-typedef	union acp_bt_tx_fifosize {
-	struct {
-	unsigned int	bt_tx_fifosize:13;
-	unsigned int	:19;
-	} bits;
-unsigned int	u32all;
-} acp_bt_tx_fifosize_t;
-typedef	union acp_bt_tx_dmasize {
-	struct {
-	unsigned int	bt_tx_dma_size:13;
-	unsigned int	:19;
-	} bits;
-unsigned int	u32all;
-} acp_bt_tx_dmasize_t;
-
-typedef	union acp_bt_tx_linearpositioncntr_high {
-	struct {
-	unsigned int	bt_tx_linearpositioncntr_high:32;
-	} bits;
-unsigned int	u32all;
-} acp_bt_tx_linearpositioncntr_high_t;
-
-typedef	union acp_bt_tx_linearpositioncntr_low {
-	struct {
-	unsigned int	bt_tx_linearpositioncntr_low:32;
-	} bits;
-unsigned int	u32all;
-} acp_bt_tx_linearpositioncntr_low_t;
-
-typedef	union acp_bt_tx_intr_watermark_size {
-	struct {
-	unsigned int	bt_tx_intr_watermark_size:26;
-	unsigned int	:6;
-	} bits;
-unsigned int	u32all;
-} acp_bt_tx_intr_watermark_size_t;
-
-typedef	union acp_i2stdm_ier {
-	struct {
-	unsigned int	i2stdm_ien:1;
-	unsigned int	:31;
-	} bits;
-unsigned int	u32all;
-} acp_i2stdm_ier_t;
-typedef	union acp_i2stdm_irer {
-	struct {
-	unsigned int	i2stdm_rx_en:1;
-	unsigned int	i2stdm_rx_protocol_mode:1;
-	unsigned int	i2stdm_rx_data_path_mode:1;
-	unsigned int	i2stdm_rx_samplen:3;
-	unsigned int	i2stdm_rx_status:1;
-	unsigned int	:25;
-
-	} bits;
-unsigned int	u32all;
-} acp_i2stdm_irer_t;
-
-typedef	union acp_i2stdm_iter {
-	struct {
-	unsigned int	i2stdm_txen:1;
-	unsigned int	i2stdm_tx_protocol_mode:1;
-	unsigned int	i2stdm_tx_data_path_mode:1;
-	unsigned int	i2stdm_tx_samp_len:3;
-	unsigned int	i2stdm_tx_status:1;
-	unsigned int	:25;
-	} bits;
-unsigned int	u32all;
-} acp_i2stdm_iter_t;
-
-typedef	union acp_bttdm_ier {
-	struct {
-	unsigned int	bttdm_ien:1;
-	unsigned int	:31;
-	} bits;
-unsigned int	u32all;
-} acp_bttdm_ier_t;
-
-typedef	union acp_bttdm_irer {
-	struct {
-	unsigned int	bttdm_rx_en:1;
-	unsigned int	bttdm_rx_protocol_mode:1;
-	unsigned int	bttdm_rx_data_path_mode:1;
-	unsigned int	bttdm_rx_samplen:3;
-	unsigned int	bttdm_rx_status:1;
-	unsigned int	:25;
-	} bits;
-unsigned int	u32all;
-} acp_bttdm_irer_t;
-
-typedef	union acp_bttdm_iter {
-	struct {
-	unsigned int	bttdm_txen:1;
-	unsigned int	bttdm_tx_protocol_mode:1;
-	unsigned int	bttdm_tx_data_path_mode:1;
-	unsigned int	bttdm_tx_samp_len:3;
-	unsigned int	bttdm_tx_status:1;
-	unsigned int	:25;
-	} bits;
-unsigned int	u32all;
-} acp_bttdm_iter_t;
-
-typedef	union acp_wov_pdm_dma_enable {
-	struct {
-	unsigned int	pdm_dma_en:1;
-	unsigned int	pdm_dma_en_status:1;
-	unsigned int	:30;
-	} bits;
-unsigned int	u32all;
-} acp_wov_pdm_dma_enable_t;
-
-typedef	union acp_wov_rx_ringbufaddr {
-	struct {
-	unsigned int	rx_ringbufaddr:27;
-	unsigned int	:5;
-	} bits;
-unsigned int	u32all;
-} acp_wov_rx_ringbufaddr_t;
-
-typedef	union acp_wov_rx_ringbufsize {
-	struct {
-	unsigned int	rx_ringbufsize:26;
-	unsigned int	:6;
-	} bits;
-unsigned int	u32all;
-} acp_wov_rx_ringbufsize_t;
-
-typedef	union acp_wov_rx_intr_watermark_size {
-	struct {
-	unsigned int	rx_intr_watermark_size:26;
-	unsigned int	:6;
-	} bits;
-unsigned int	u32all;
-} acp_wov_rx_intr_watermark_size_t;
-
-typedef	union acp_wov_pdm_no_of_channels {
-	struct {
-	unsigned int	pdm_no_of_channels:2;
-	unsigned int	:30;
-	} bits;
-unsigned int	u32all;
-} acp_wov_pdm_no_of_channels_t;
-
-typedef	union acp_wov_pdm_decimation_factor {
-	struct {
-	unsigned int	pdm_decimation_factor:2;
-	unsigned int	:30;
-	} bits;
-unsigned int	u32all;
-} acp_wov_pdm_decimation_factor_t;
-
-typedef	union acp_wov_misc_ctrl {
-	struct {
-	unsigned int	:3;
-	unsigned int	pcm_data_shift_ctrl:2;
-	unsigned int	:27;
-	} bits;
-unsigned int	u32all;
-} acp_wov_misc_ctrl_t;
-
-typedef	union acp_wov_clk_ctrl {
-	struct {
-	unsigned int	brm_clk_ctrl:4;
-	unsigned int	pdm_vad_clkdiv:2;
-	unsigned int	:26;
-	} bits;
-unsigned int	u32all;
-} acp_wov_clk_ctrl_t;
-
-typedef	union acp_srbm_cycle_sts {
-	struct {
-	unsigned int	srbm_clients_sts:1;
-	unsigned int	:7;
-
-	} bits;
-unsigned int	u32all;
-} acp_srbm_cycle_sts_t;
-
-typedef	union acp_i2stdm_rxfrmt {
-	struct {
-		unsigned int	i2stdm_frame_len :9;
-		unsigned int	:6;
-		unsigned int	i2stdm_num_slots :3;
-		unsigned int	i2stdm_slot_len :5;
-		unsigned int	:9;
-	} bits;
-	unsigned int	u32all;
-} acp_i2stdm_rxfrmt_t;
-typedef	union acp_i2stdm_txfrmt {
-	struct {
-		unsigned int	i2stdm_frame_len :9;
-		unsigned int	:6;
-		unsigned int	i2stdm_num_slots :3;
-		unsigned int	i2stdm_slot_len :5;
-		unsigned int	:9;
-	} bits;
-	unsigned int	u32all;
-} acp_i2stdm_txfrmt_t;
-
-#endif
-
diff --git a/src/platform/amd/renoir/include/platform/drivers/interrupt.h b/src/platform/amd/renoir/include/platform/drivers/interrupt.h
deleted file mode 100644
index 328ffb832ca6..000000000000
--- a/src/platform/amd/renoir/include/platform/drivers/interrupt.h
+++ /dev/null
@@ -1,112 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- *
- * Copyright(c) 2021 AMD.All rights reserved.
- *
- * Author:      Basavaraj Hiregoudar <basavaraj.hiregoudar@amd.com>
- *              Anup Kulkarni <anup.kulkarni@amd.com>
- *              Bala Kishore <balakishore.pati@amd.com>
- */
-#ifdef __SOF_DRIVERS_INTERRUPT_H__
-
-#ifndef __PLATFORM_DRIVERS_INTERRUPT_H__
-#define __PLATFORM_DRIVERS_INTERRUPT_H__
-
-#include <rtos/bit.h>
-#include <sof/lib/cpu.h>
-#include <sof/lib/memory.h>
-
-#define PLATFORM_IRQ_HW_NUM		8
-
-#define PLATFORM_IRQ_FIRST_CHILD	PLATFORM_IRQ_HW_NUM
-
-#define PLATFORM_IRQ_CHILDREN		0
-
-/* IRQ numbers - wrt Tensilica DSP */
-#define IRQ_NUM_SOFTWARE0	1	/* level 1 */
-
-#define IRQ_NUM_TIMER0		0	/* level 1 */
-
-#define IRQ_NUM_EXT_LEVEL3	3	/* level 1 */
-
-#define IRQ_NUM_TIMER1		6	/* level 2 */
-
-#define IRQ_NUM_EXT_LEVEL4	4	/* level 2 */
-
-#define IRQ_NUM_EXT_LEVEL5	5	/* level 3 */
-
-/* IRQ Masks */
-#define IRQ_MASK_SOFTWARE0	(1 << IRQ_NUM_SOFTWARE0)
-
-#define IRQ_MASK_TIMER0		(1 << IRQ_NUM_TIMER0)
-
-#define IRQ_MASK_TIMER1		(1 << IRQ_NUM_TIMER1)
-
-#define IRQ_MASK_EXT_LEVEL3	(1 << IRQ_NUM_EXT_LEVEL3)
-
-#define IRQ_MASK_EXT_LEVEL4	(1 << IRQ_NUM_EXT_LEVEL4)
-
-#define IRQ_MASK_EXT_LEVEL5	(1 << IRQ_NUM_EXT_LEVEL5)
-
-
-#define HOST_TO_DSP_INTR	0x1
-
-#define _XTSTR(x)   # x
-
-#define XTSTR(x)    _XTSTR(x)
-
-
-/* Enabling flag */
-#define INTERRUPT_ENABLE	1
-
-/* Clearing flag */
-#define INTERRUPT_CLEAR		0
-
-/* Disable flag */
-#define INTERRUPT_DISABLE	0
-
-/* brief Tensilica  Interrupt Levels. */
-typedef enum {
-	acp_interrupt_level_3 = 0,
-
-	acp_interrupt_level_4,
-
-	acp_interrupt_level_5,
-
-	acp_interrupt_level_nmi,
-
-	acp_interrupt_level_max
-} artos_interrupt_levels_t;
-
-/* brief Tensilica  timer control */
-typedef enum {
-	acp_timer_cntl_disable = 0,
-
-	acp_timer_cntl_oneshot,
-
-	acp_timer_cntl_periodic,
-
-	acp_timer_cntl_max
-} artos_timer_control_t;
-
-/* Disable Host to DSP interrupt */
-void acp_dsp_sw_intr_disable(void);
-
-void acp_intr_route(void);
-
-void acp_dsp_to_host_intr_trig(void);
-
-void acp_ack_intr_from_host(void);
-
-void acp_dsp_sw_intr_enable(void);
-
-void acp_intr_enable(void);
-
-void acp_intr_disable(void);
-
-#endif /* __PLATFORM_DRIVERS_INTERRUPT_H__ */
-
-#else
-
-#error "This file shouldn't be included from outside of sof/drivers/interrupt.h"
-
-#endif /* __SOF_DRIVERS_INTERRUPT_H__ */
diff --git a/src/platform/amd/renoir/include/platform/fw_scratch_mem.h b/src/platform/amd/renoir/include/platform/fw_scratch_mem.h
deleted file mode 100644
index db779b8cfb03..000000000000
--- a/src/platform/amd/renoir/include/platform/fw_scratch_mem.h
+++ /dev/null
@@ -1,119 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- *
- *  Copyright(c) 2021 AMD. All rights reserved.
- *
- *  Author: Basavaraj Hiregoudar <basavaraj.hiregoudar@amd.com>
- *          Anup Kulkarni <anup.kulkarni@amd.com>
- *          Bala Kishore <balakishore.pati@amd.com>
- */
-#ifndef __EXT_SCRATCH_MEM_H__
-#define __EXT_SCRATCH_MEM_H__
-
-#include <sof/lib/mailbox.h>
-
-/* MAX number of DMA descriptors */
-#define MAX_NUM_DMA_DESC_DSCR	64
-#define SCRATCH_REG_OFFSET	0x1250000
-
-typedef struct acp_atu_grp_pte {
-	uint32_t low_part;
-	uint32_t high_part;
-} __attribute__((packed, aligned(4))) acp_atu_grp_pte_t;
-
-typedef union acp_cfg_dma_trns_cnt {
-	struct{
-		uint32_t  trns_cnt : 19;
-		uint32_t  reserved : 12;
-		uint32_t  ioc : 1;
-	} bits;
-	unsigned int    u32all;
-} __attribute__((packed, aligned(4))) acp_cfg_dma_trns_cnt_t;
-
-typedef struct acp_config_dma_descriptor {
-	uint32_t	src_addr;
-	uint32_t	dest_addr;
-	acp_cfg_dma_trns_cnt_t	trns_cnt;
-	uint32_t	reserved;
-} __attribute__((packed, aligned(4))) acp_cfg_dma_descriptor_t;
-
-typedef struct acp_config_dma_misc {
-	uint32_t	channelstatus;
-	uint32_t	channel;
-	uint32_t	flag;
-} __attribute__((packed, aligned(4))) acp_cfg_dma_misc_t;
-
-typedef struct  acp_scratch_memory_config {
-	/* ACP out box buffer */
-	uint8_t				acp_outbox_buffer[MAILBOX_DSPBOX_SIZE];
-
-	/* ACP in box buffer */
-	uint8_t				acp_inbox_buffer[MAILBOX_HOSTBOX_SIZE];
-
-	/* ACP debug box buffer */
-	uint8_t				acp_debug_buffer[MAILBOX_DEBUG_SIZE];
-
-	/* ACP exception box buffer */
-	uint8_t				acp_except_buffer[MAILBOX_EXCEPTION_SIZE];
-
-	/* ACP stream buffer */
-	uint8_t				acp_stream_buffer[MAILBOX_STREAM_SIZE];
-
-	/* ACP trace buffer */
-	uint8_t				acp_trace_buffer[MAILBOX_TRACE_SIZE];
-
-	/* Host msg write flag */
-	uint32_t			acp_host_msg_write;
-
-	/* Host ack flag */
-	uint32_t			acp_host_ack_write;
-
-	/* Dsp msg write flag */
-	uint32_t			acp_dsp_msg_write;
-
-	/* Dsp ack flag */
-	uint32_t			acp_dsp_ack_write;
-
-	/* ACP pte1 table */
-	acp_atu_grp_pte_t		acp_atugrp1_pte[16];
-
-	/* ACP pte2 table */
-	acp_atu_grp_pte_t		acp_atugrp2_pte[16];
-
-	/* ACP pte3 table */
-	acp_atu_grp_pte_t		acp_atugrp3_pte[16];
-
-	/* ACP pte4 table */
-	acp_atu_grp_pte_t		acp_atugrp4_pte[16];
-
-	/* ACP pte5 table */
-	acp_atu_grp_pte_t		acp_atugrp5_pte[16];
-
-	/* ACP pte6 table */
-	acp_atu_grp_pte_t		acp_atugrp6_pte[16];
-
-	/* ACP pte7 table */
-	acp_atu_grp_pte_t		acp_atugrp7_pte[16];
-
-	/* ACP pte8 table */
-	acp_atu_grp_pte_t		acp_atugrp8_pte[16];
-
-	/* ACP DMA Descriptor */
-	acp_cfg_dma_descriptor_t	acp_cfg_dma_descriptor[MAX_NUM_DMA_DESC_DSCR];
-
-	/* Stream physical offset  */
-	uint32_t			phy_offset[8];
-
-	/* Stream system memeory size */
-	uint32_t			syst_buff_size[8];
-
-	/* ACP transmit fifo buffer */
-	uint8_t				acp_transmit_fifo_buffer[768];
-
-	/* ACP receive fifo buffer */
-	uint8_t				acp_receive_fifo_buffer[768];
-
-	uint32_t			reserve[];
-} __attribute__((packed, aligned(4))) acp_scratch_mem_config_t;
-
-#endif /* __EXT_SCRATCH_MEM_H__ */
-
diff --git a/src/platform/amd/renoir/include/platform/lib/memory.h b/src/platform/amd/renoir/include/platform/lib/memory.h
deleted file mode 100644
index d9a3825fbc86..000000000000
--- a/src/platform/amd/renoir/include/platform/lib/memory.h
+++ /dev/null
@@ -1,164 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- *
- * Copyright(c) 2021 AMD.All rights reserved.
- *
- * Author:      Basavaraj Hiregoudar <basavaraj.hiregoudar@amd.com>
- *              Anup Kulkarni <anup.kulkarni@amd.com>
- *              Bala Kishore <balakishore.pati@amd.com>
- */
-#ifdef __SOF_LIB_MEMORY_H__
-
-#ifndef __PLATFORM_LIB_MEMORY_H__
-#define __PLATFORM_LIB_MEMORY_H__
-
-#include <rtos/cache.h>
-#include <platform/chip_offset_byte.h>
-
-/* data cache line alignment */
-#define PLATFORM_DCACHE_ALIGN	64
-
-/* physical DSP addresses */
-
-#define IRAM_BASE	0x20000000
-#define IRAM_SIZE	0x40000
-
-#define DRAM0_BASE	0x21000000
-#define DRAM0_SIZE	0x36000
-#define DRAM1_SIZE	0xA8000
-
-
-#define DMA0_BASE	PU_REGISTER_BASE
-#define DMA0_SIZE	0x4
-
-/* DAI DMA register base address */
-#define DAI_BASE		(PU_REGISTER_BASE + ACP_I2S_RX_RINGBUFADDR)
-#define DAI_SIZE		0x4
-#define BT_TX_FIFO_OFFST	(ACP_BT_TX_FIFOADDR - ACP_I2S_RX_RINGBUFADDR)
-#define BT_RX_FIFO_OFFST	(ACP_BT_RX_FIFOADDR - ACP_I2S_RX_RINGBUFADDR)
-
-#define UUID_ENTRY_ELF_BASE     0x1FFFA000
-#define UUID_ENTRY_ELF_SIZE     0x6000
-
-/* Log buffer  base need to be updated properly, these are used in linker scripts */
-#define LOG_ENTRY_ELF_BASE	0x20000000
-#define LOG_ENTRY_ELF_SIZE	0x2000000
-
-#define EXT_MANIFEST_ELF_BASE   (LOG_ENTRY_ELF_BASE + LOG_ENTRY_ELF_SIZE)
-#define EXT_MANIFEST_ELF_SIZE   0x2000000
-
-/* Stack configuration */
-#define SOF_STACK_SIZE		(CONFIG_SOF_STACK_SIZE)
-#define SOF_STACK_TOTAL_SIZE	SOF_STACK_SIZE
-#define SOF_STACK_END		(DRAM0_BASE + DRAM0_SIZE)
-#define SOF_STACK_BASE		(SOF_STACK_END + SOF_STACK_SIZE)
-
-/* Mailbox configuration */
-#define SRAM_OUTBOX_BASE		0x22050000
-#define SRAM_OUTBOX_SIZE		0x400
-#define SRAM_OUTBOX_OFFSET		0
-
-#define SRAM_INBOX_BASE			(SRAM_OUTBOX_BASE + SRAM_OUTBOX_SIZE)
-#define SRAM_INBOX_SIZE			0x400
-#define SRAM_INBOX_OFFSET		SRAM_OUTBOX_SIZE
-
-#define SRAM_DEBUG_BASE			(SRAM_INBOX_BASE + SRAM_INBOX_SIZE)
-#define SRAM_DEBUG_SIZE			0x400
-#define SRAM_DEBUG_OFFSET		(SRAM_INBOX_OFFSET + SRAM_INBOX_SIZE)
-
-#define SRAM_EXCEPT_BASE		(SRAM_DEBUG_BASE + SRAM_DEBUG_SIZE)
-#define SRAM_EXCEPT_SIZE		0x400
-#define SRAM_EXCEPT_OFFSET		(SRAM_DEBUG_OFFSET + SRAM_DEBUG_SIZE)
-
-#define SRAM_STREAM_BASE		(SRAM_EXCEPT_BASE + SRAM_EXCEPT_SIZE)
-#define SRAM_STREAM_SIZE		0x400
-#define SRAM_STREAM_OFFSET		(SRAM_EXCEPT_OFFSET + SRAM_EXCEPT_SIZE)
-
-#define SRAM_TRACE_BASE			(SRAM_STREAM_BASE + SRAM_STREAM_SIZE)
-#define SRAM_TRACE_SIZE			0x400
-#define SRAM_TRACE_OFFSET		(SRAM_STREAM_OFFSET + SRAM_STREAM_SIZE)
-#define SOF_MAILBOX_SIZE		(SRAM_INBOX_SIZE + SRAM_OUTBOX_SIZE \
-					+ SRAM_DEBUG_SIZE + SRAM_EXCEPT_SIZE \
-					+ SRAM_STREAM_SIZE + SRAM_TRACE_SIZE)
-
-/* Heap section sizes for module pool */
-#define HEAP_RT_COUNT8		0
-#define HEAP_RT_COUNT16		48
-#define HEAP_RT_COUNT32		48
-#define HEAP_RT_COUNT64		32
-#define HEAP_RT_COUNT128	48
-#define HEAP_RT_COUNT256	32
-#define HEAP_RT_COUNT512	4
-#define HEAP_RT_COUNT1024	12
-#define HEAP_RT_COUNT2048	12
-
-/* Heap section sizes for system runtime heap */
-#define HEAP_SYS_RT_COUNT64	64
-#define HEAP_SYS_RT_COUNT512	8
-#define HEAP_SYS_RT_COUNT1024	4
-
-/* Heap configuration */
-#define HEAP_SYSTEM_BASE	SOF_STACK_BASE
-#define HEAP_SYSTEM_SIZE	0xe000
-#define HEAP_SYSTEM_0_BASE	HEAP_SYSTEM_BASE
-#define HEAP_SYS_RUNTIME_BASE	(HEAP_SYSTEM_BASE + HEAP_SYSTEM_SIZE)
-#define HEAP_SYS_RUNTIME_SIZE	(HEAP_SYS_RT_COUNT64 * 64 + HEAP_SYS_RT_COUNT512 * 512 + \
-				HEAP_SYS_RT_COUNT1024 * 1024)
-
-#define HEAP_RUNTIME_BASE	(HEAP_SYS_RUNTIME_BASE + HEAP_SYS_RUNTIME_SIZE)
-#define HEAP_RUNTIME_SIZE \
-				(HEAP_RT_COUNT8 * 8 + HEAP_RT_COUNT16 * 16 + \
-				HEAP_RT_COUNT32 * 32 + HEAP_RT_COUNT64 * 64 + \
-				HEAP_RT_COUNT128 * 128 + HEAP_RT_COUNT256 * 256 + \
-				HEAP_RT_COUNT512 * 512 + HEAP_RT_COUNT1024 * 1024 + \
-				HEAP_RT_COUNT2048 * 2048)
-
-#define HEAP_BUFFER_BASE	(HEAP_RUNTIME_BASE + HEAP_RUNTIME_SIZE)
-#define HEAP_BUFFER_SIZE	(0xF000)
-#define HEAP_BUFFER_BLOCK_SIZE	0x180
-#define HEAP_BUFFER_COUNT	(HEAP_BUFFER_SIZE / HEAP_BUFFER_BLOCK_SIZE)
-
-#define PLATFORM_HEAP_SYSTEM		1 /* one per core */
-#define PLATFORM_HEAP_SYSTEM_RUNTIME	1 /* one per core */
-#define PLATFORM_HEAP_RUNTIME		1
-#define PLATFORM_HEAP_BUFFER		1
-
-/* Vector and literal sizes - not in core-isa.h */
-#define SOF_MEM_VECT_LIT_SIZE		0x7
-#define SOF_MEM_VECT_TEXT_SIZE		0x37
-#define SOF_MEM_VECT_SIZE		(SOF_MEM_VECT_TEXT_SIZE + SOF_MEM_VECT_LIT_SIZE)
-
-#define SOF_MEM_RESET_TEXT_SIZE		0x400
-#define SOF_MEM_RESET_LIT_SIZE		0x8
-#define SOF_MEM_VECBASE_LIT_SIZE	0x178
-#define SOF_MEM_WIN_TEXT_SIZE		0x178
-
-#define SOF_MEM_RO_SIZE			0x8
-
-#define uncache_to_cache(address)	address
-#define cache_to_uncache(address)	address
-#define cache_to_uncache_init(address)	address
-#define is_uncached(address)		0
-
-#define HEAP_BUF_ALIGNMENT		PLATFORM_DCACHE_ALIGN
-
-/* brief EDF task's default stack size in bytes */
-#define PLATFORM_TASK_DEFAULT_STACK_SIZE        3072
-
-#if !defined(__ASSEMBLER__) && !defined(LINKER)
-struct sof;
-
-void platform_init_memmap(struct sof *sof);
-
-static inline void *platform_rfree_prepare(void *ptr)
-{
-	return ptr;
-}
-#endif
-
-#endif /* __PLATFORM_LIB_MEMORY_H__ */
-
-#else
-
-#error "This file shouldn't be included from outside of sof/lib/memory.h"
-
-#endif /* __SOF_LIB_MEMORY_H__ */
diff --git a/src/platform/amd/renoir/include/platform/platform.h b/src/platform/amd/renoir/include/platform/platform.h
deleted file mode 100644
index e3b7cd58ea03..000000000000
--- a/src/platform/amd/renoir/include/platform/platform.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- *
- * Copyright(c) 2021 AMD.All rights reserved.
- *
- * Author:	Basavaraj Hiregoudar <basavaraj.hiregoudar@amd.com>
- *		Anup Kulkarni <anup.kulkarni@amd.com>
- *		Bala Kishore <balakishore.pati@amd.com>
- */
-#ifdef __SOF_PLATFORM_H__
-
-#ifndef __PLATFORM_PLATFORM_H__
-#define __PLATFORM_PLATFORM_H__
-
-#if !defined(__ASSEMBLER__) && !defined(LINKER)
-
-#include <rtos/interrupt.h>
-#include <rtos/clk.h>
-#include <sof/lib/mailbox.h>
-#include <stddef.h>
-#include <stdint.h>
-#include <platform/fw_scratch_mem.h>
-#include <platform/chip_registers.h>
-
-struct ll_schedule_domain;
-struct timer;
-
-#define PLATFORM_DEFAULT_CLOCK CLK_CPU(0)
-
-/* IPC Interrupt */
-#define PLATFORM_IPC_INTERRUPT		IRQ_EXT_IPC_LEVEL_3
-#define PLATFORM_IPC_INTERRUPT_NAME	NULL
-
-/* Host page size */
-#define HOST_PAGE_SIZE                  65536
-
-/* pipeline IRQ */
-#define PLATFORM_SCHEDULE_IRQ		IRQ_NUM_SOFTWARE0
-#define PLATFORM_SCHEDULE_IRQ_NAME	NULL
-
-/* Platform stream capabilities */
-#define PLATFORM_MAX_CHANNELS	8
-#define PLATFORM_MAX_STREAMS	5
-
-/* local buffer size of DMA tracing */
-#define DMA_TRACE_LOCAL_SIZE	8192
-
-/* trace bytes flushed during panic */
-#define DMA_FLUSH_TRACE_SIZE	(MAILBOX_TRACE_SIZE >> 2)
-
-/* the interval of DMA trace copying */
-#define DMA_TRACE_PERIOD		500000
-
-/*
- * the interval of reschedule DMA trace copying in special case like half
- * fullness of local DMA trace buffer
- */
-#define DMA_TRACE_RESCHEDULE_TIME	100
-
-/* DSP default delay in cycles */
-#define PLATFORM_DEFAULT_DELAY	12
-
-/* default dma trace channel */
-#define DMA_TRACE_CHANNEL	7
-
-/* debug offset */
-#define ACP_SOF_FW_STATUS	0
-
-/* Platform defined panic code */
-static inline void platform_panic(uint32_t p)
-{
-	acp_sw_intr_trig_t  sw_intr_trig;
-	volatile acp_scratch_mem_config_t *pscratch_mem_cfg =
-		(volatile acp_scratch_mem_config_t *)(PU_REGISTER_BASE + SCRATCH_REG_OFFSET);
-
-	pscratch_mem_cfg->acp_dsp_msg_write = p;
-	mailbox_sw_reg_write(ACP_SOF_FW_STATUS, p);
-	/* Read the Software Interrupt controller register and update */
-	sw_intr_trig = (acp_sw_intr_trig_t) io_reg_read(PU_REGISTER_BASE + ACP_SW_INTR_TRIG);
-	/* Configures the trigger bit in ACP_DSP_SW_INTR_TRIG register */
-	sw_intr_trig.bits.trig_dsp0_to_host_intr = INTERRUPT_ENABLE;
-	/* Write the Software Interrupt trigger register */
-	io_reg_write((PU_REGISTER_BASE + ACP_SW_INTR_TRIG), sw_intr_trig.u32all);
-}
-
-/*
- * brief Platform specific CPU entering idle.
- * May be power-optimized using platform specific capabilities.
- * @param level Interrupt level.
- */
-void platform_wait_for_interrupt(int level);
-
-extern intptr_t _module_init_start;
-extern intptr_t _module_init_end;
-#endif
-
-#endif /* __PLATFORM_PLATFORM_H__ */
-
-#else
-
-#error "This file shouldn't be included from outside of sof/platform.h"
-
-#endif /* __SOF_PLATFORM_H__ */
diff --git a/src/platform/amd/renoir/lib/CMakeLists.txt b/src/platform/amd/renoir/lib/CMakeLists.txt
deleted file mode 100644
index 271a099cc6a9..000000000000
--- a/src/platform/amd/renoir/lib/CMakeLists.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-
-add_local_sources(sof
-	clk.c
-	dai.c
-	dma.c
-	memory.c
-)
diff --git a/src/platform/amd/renoir/lib/clk.c b/src/platform/amd/renoir/lib/clk.c
deleted file mode 100644
index ea81e756e9a1..000000000000
--- a/src/platform/amd/renoir/lib/clk.c
+++ /dev/null
@@ -1,138 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-//
-// Copyright(c) 2021 AMD. All rights reserved.
-//
-// Author: Basavaraj Hiregoudar<basavaraj.hiregoudar@amd.com>
-
-#include <sof/common.h>
-#include <rtos/clk.h>
-#include <sof/lib/cpu.h>
-#include <sof/lib/memory.h>
-#include <sof/lib/notifier.h>
-#include <rtos/sof.h>
-#include <platform/chip_registers.h>
-
-static struct freq_table platform_cpu_freq[] = {
-	{200000000, 200000 },
-};
-
-STATIC_ASSERT(NUM_CPU_FREQ == ARRAY_SIZE(platform_cpu_freq),
-			      invalid_number_of_cpu_frequencies);
-
-static struct clock_info platform_clocks_info[NUM_CLOCKS];
-
-static int acp_reg_read_via_smn(uint32_t reg_offset,
-				uint32_t size)
-{
-	uint32_t reg_value;
-	uint32_t delay_cnt = 10000;
-	uint32_t smn_client_base_addr = (reg_offset >> 10);
-	uint32_t region_start_addr = (smn_client_base_addr << 10);
-	acp_srbm_cycle_sts_t  acp_srbm_cycle_sts;
-
-	/* Configuring the MP1 Aperture Id in SRB_client_config register */
-	io_reg_write((PU_REGISTER_BASE + ACP_SRBM_CLIENT_CONFIG), MP1_APERTURE_ID);
-	/* Configuring the base address of MP1 */
-	io_reg_write((PU_REGISTER_BASE + ACP_SRBM_CLIENT_BASE_ADDR), smn_client_base_addr);
-	/* dummy read to the to the address offset 0x3400 */
-	/* Master config offset to access register outside of ACP */
-	reg_value = (uint32_t)io_reg_read(PU_REGISTER_BASE +
-	(ACP_MASTER_REG_ACCESS_ADDRESS + reg_offset - region_start_addr + ACP_FIRST_REG_OFFSET));
-	if (reg_value)
-		reg_value = 0;
-	/* reading status register to check above read request is completed or not */
-	acp_srbm_cycle_sts = (acp_srbm_cycle_sts_t)io_reg_read(PU_REGISTER_BASE +
-							       ACP_SRBM_CYCLE_STS);
-	/* Waiting for status to be set to '0' */
-	while (delay_cnt > 0) {
-		if (!acp_srbm_cycle_sts.bits.srbm_clients_sts) {
-			/* when status is '0' from above read the data from data register */
-			return (uint32_t) io_reg_read(PU_REGISTER_BASE + ACP_SRBM_Client_RDDATA);
-		}
-		acp_srbm_cycle_sts = (acp_srbm_cycle_sts_t)io_reg_read(PU_REGISTER_BASE +
-									ACP_SRBM_CYCLE_STS);
-		delay_cnt--;
-	}
-	return -1;
-}
-
-static void acp_reg_write_via_smn(uint32_t reg_offset,
-				  uint32_t value, uint32_t size)
-{
-	uint32_t	delay_cnt = 10000;
-	uint32_t        smn_client_base_addr    = (reg_offset >> 10);
-	uint32_t        region_start_addr = (smn_client_base_addr << 10);
-	acp_srbm_cycle_sts_t      acp_srbm_cycle_sts;
-
-	/* Configuring the MP1 Aperture Id in SRB_client_config register */
-	io_reg_write((PU_REGISTER_BASE + ACP_SRBM_CLIENT_CONFIG), MP1_APERTURE_ID);
-	/* Configuring the base address of MP1 */
-	io_reg_write((PU_REGISTER_BASE + ACP_SRBM_CLIENT_BASE_ADDR), smn_client_base_addr);
-	/* write to the address offset 0x3400
-	 *  Master config offset to access register outside of ACP
-	 */
-	io_reg_write((PU_REGISTER_BASE + (ACP_MASTER_REG_ACCESS_ADDRESS + reg_offset - region_start_addr + ACP_FIRST_REG_OFFSET)), value);
-	/* reading status register to check above read request is completed or not */
-	acp_srbm_cycle_sts = (acp_srbm_cycle_sts_t)io_reg_read(PU_REGISTER_BASE + ACP_SRBM_CYCLE_STS);
-	/* Waiting for status to be set to '0' */
-	while (delay_cnt > 0) {
-		acp_srbm_cycle_sts = (acp_srbm_cycle_sts_t)io_reg_read(PU_REGISTER_BASE +
-								ACP_SRBM_CYCLE_STS);
-		if (!acp_srbm_cycle_sts.bits.srbm_clients_sts)
-			return;
-		delay_cnt--;
-	}
-}
-
-static void  get_response_from_smu(void)
-{
-	uint32_t ret_value;
-	uint32_t count = 0;
-
-	do {
-		ret_value = acp_reg_read_via_smn(MP1_SMN_C2PMSG_93, sizeof(int));
-		if (count > 0x007fffff)
-			count = 0;
-		count++;
-	} while (ret_value == 0);
-}
-
-
-void acp_change_clock_notify(uint32_t	clock_freq)
-{
-	/* converting Hz to Mhz */
-	clock_freq = (clock_freq / 1000000);
-	/* Writing response zero to the response register
-	 * so that it cab reset to '0' for further response
-	 */
-	acp_reg_write_via_smn(MP1_SMN_C2PMSG_93,
-				0, sizeof(int));
-	/* Writing clock frequency value in Mhz in the Argument register */
-	acp_reg_write_via_smn(MP1_SMN_C2PMSG_85,
-				clock_freq, sizeof(int));
-	/* Writing Message to message register */
-	/* Writing Aclk change message to message register */
-	acp_reg_write_via_smn(MP1_SMN_C2PMSG_69,
-				ACP_SMU_MSG_SET_ACLK, sizeof(int));
-	/* Waiting for SMU response */
-	get_response_from_smu();
-}
-
-void platform_clock_init(struct sof *sof)
-{
-	int i;
-
-	sof->clocks = platform_clocks_info;
-
-	for (i = 0; i < PLATFORM_CORE_COUNT; i++) {
-		sof->clocks[i] = (struct clock_info) {
-			.freqs_num = NUM_CPU_FREQ,
-			.freqs = platform_cpu_freq,
-			.default_freq_idx = CPU_DEFAULT_IDX,
-			.current_freq_idx = CPU_DEFAULT_IDX,
-			.notification_id = NOTIFIER_ID_CPU_FREQ,
-			.notification_mask = NOTIFIER_TARGET_CORE_MASK(i),
-			.set_freq = NULL,
-		};
-	}
-}
diff --git a/src/platform/amd/renoir/lib/dai.c b/src/platform/amd/renoir/lib/dai.c
deleted file mode 100644
index b104790716fc..000000000000
--- a/src/platform/amd/renoir/lib/dai.c
+++ /dev/null
@@ -1,138 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-//
-//Copyright(c) 2021 AMD. All rights reserved.
-//
-//Author:       Basavaraj Hiregoudar <basavaraj.hiregoudar@amd.com>
-//              Anup Kulkarni <anup.kulkarni@amd.com>
-//              Bala Kishore <balakishore.pati@amd.com>
-
-#include <sof/common.h>
-#include <sof/drivers/acp_dai_dma.h>
-#include <sof/lib/dai.h>
-#include <sof/lib/memory.h>
-#include <rtos/sof.h>
-#include <rtos/spinlock.h>
-#include <ipc/dai.h>
-#include <ipc/stream.h>
-
-static struct dai acp_dmic_dai[] = {
-	{
-		.index = 0,
-		.plat_data = {
-			.base = DMA0_BASE,
-			.fifo[SOF_IPC_STREAM_PLAYBACK] = {
-			.offset		= DMA0_BASE,
-			.depth		= 8,
-			.handshake	= 0,
-			},
-			.fifo[SOF_IPC_STREAM_CAPTURE] = {
-			.offset		= DMA0_BASE,
-			.depth		= 8,
-			.handshake	= 1,
-			},
-		},
-		.drv = &acp_dmic_dai_driver,
-	},
-};
-
-static struct dai spdai[] = {
-	{
-		.index = 0,
-		.plat_data = {
-			.base = DAI_BASE,
-			.fifo[SOF_IPC_STREAM_PLAYBACK] = {
-				.offset         = DAI_BASE + BT_TX_FIFO_OFFST,
-				.depth          = 8,
-				.handshake      = 5,
-			},
-			.fifo[SOF_IPC_STREAM_CAPTURE] = {
-				.offset         = DAI_BASE + BT_RX_FIFO_OFFST,
-				.depth          = 8,
-				.handshake      = 4,
-			},
-		},
-		.drv = &acp_spdai_driver,
-	},
-	{
-	.index = 1,
-	.plat_data = {
-		.base = DAI_BASE,
-		.fifo[SOF_IPC_STREAM_PLAYBACK] = {
-			.offset         = DAI_BASE + BT_TX_FIFO_OFFST,
-			.depth          = 8,
-			.handshake      = 5,
-		},
-		.fifo[SOF_IPC_STREAM_CAPTURE] = {
-			.offset         = DAI_BASE + BT_RX_FIFO_OFFST,
-			.depth          = 8,
-			.handshake      = 4,
-		},
-	},
-	.drv = &acp_spdai_driver,
-	}
-};
-
-#ifdef ACP_BT_ENABLE
-static struct dai btdai[] = {
-	{
-		.index = 0,
-		.plat_data = {
-			.base = DAI_BASE,
-			.fifo[SOF_IPC_STREAM_PLAYBACK] = {
-				.offset		= DAI_BASE + BT_TX_FIFO_OFFST,
-				.depth		= 8,
-				.handshake	= 3,
-			},
-			.fifo[SOF_IPC_STREAM_CAPTURE] = {
-				.offset		= DAI_BASE + BT_RX_FIFO_OFFST,
-				.depth		= 8,
-				.handshake	= 2,
-			},
-		},
-		.drv = &acp_btdai_driver,
-	},
-};
-#endif
-
-const struct dai_type_info dti[] = {
-	{
-		.type = SOF_DAI_AMD_DMIC,
-		.dai_array = acp_dmic_dai,
-		.num_dais = ARRAY_SIZE(acp_dmic_dai)
-	},
-	{
-		.type		= SOF_DAI_AMD_SP,
-		.dai_array	= spdai,
-		.num_dais	= ARRAY_SIZE(spdai)
-	},
-#ifdef ACP_BT_ENABLE
-	{
-		.type = SOF_DAI_AMD_BT,
-		.dai_array = btdai,
-		.num_dais = ARRAY_SIZE(btdai)
-	},
-#endif
-};
-
-const struct dai_info lib_dai = {
-	.dai_type_array = dti,
-	.num_dai_types = ARRAY_SIZE(dti)
-};
-
-int dai_init(struct sof *sof)
-{
-	int i;
-	/* initialize spin locks early to enable ref counting */
-	for (i = 0; i < ARRAY_SIZE(acp_dmic_dai); i++)
-		k_spinlock_init(&acp_dmic_dai[i].lock);
-	/* initialize spin locks early to enable ref counting */
-	for (i = 0; i < ARRAY_SIZE(spdai); i++)
-		k_spinlock_init(&spdai[i].lock);
-#ifdef ACP_BT_ENABLE
-	/* initialize spin locks early to enable ref counting */
-	for (i = 0; i < ARRAY_SIZE(btdai); i++)
-		k_spinlock_init(&btdai[i].lock);
-#endif
-	sof->dai_info = &lib_dai;
-	return 0;
-}
diff --git a/src/platform/amd/renoir/lib/dma.c b/src/platform/amd/renoir/lib/dma.c
deleted file mode 100644
index 2183a3464951..000000000000
--- a/src/platform/amd/renoir/lib/dma.c
+++ /dev/null
@@ -1,105 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-//
-//Copyright(c) 2021 AMD. All rights reserved.
-//
-//Author:       Basavaraj Hiregoudar <basavaraj.hiregoudar@amd.com>
-//              Anup Kulkarni <anup.kulkarni@amd.com>
-//              Bala Kishore <balakishore.pati@amd.com>
-
-#include <sof/common.h>
-#include <platform/fw_scratch_mem.h>
-#include <sof/drivers/acp_dai_dma.h>
-#include <rtos/interrupt.h>
-#include <sof/lib/dma.h>
-#include <sof/lib/memory.h>
-#include <rtos/sof.h>
-#include <rtos/spinlock.h>
-
-#define ACP_ADDR_MASK	0x20000000
-
-extern struct dma_ops acp_dma_ops;
-extern struct dma_ops acp_dmic_dma_ops;
-#ifdef ACP_BT_ENABLE
-extern struct dma_ops acp_dai_bt_dma_ops;
-#endif
-extern struct dma_ops acp_dai_sp_dma_ops;
-
-static struct dma dma[PLATFORM_NUM_DMACS] = {
-{
-	.plat_data = {
-		.id		= DMA_ID_DMA0,
-		.dir		= DMA_DIR_LMEM_TO_HMEM | DMA_DIR_HMEM_TO_LMEM,
-		.devs		= DMA_DEV_HOST,
-		.base		= DMA0_BASE,
-		.chan_size	= DMA0_SIZE,
-		.channels	= 8,
-		.irq		= IRQ_NUM_EXT_LEVEL5,
-	},
-	.ops	= &acp_dma_ops,
-},
-{
-	.plat_data = {
-		.id		= DMA_ID_DAI_DMIC,
-		.dir		= DMA_DIR_DEV_TO_MEM,
-		.devs		= DMA_DEV_DMIC,
-		.caps		= DMA_CAP_DMIC,
-		.base		= DMA0_BASE,
-		.chan_size	= DMA0_SIZE,
-		.channels	= 8,
-		.irq		= IRQ_NUM_EXT_LEVEL4,
-	},
-	.ops = &acp_dmic_dma_ops,
-},
-{
-	.plat_data = {
-		.id		= DMA_ID_DAI_SP,
-		.dir		= DMA_DIR_DEV_TO_MEM | DMA_DIR_MEM_TO_DEV,
-		.devs		= DMA_DEV_SP,
-		.caps		= DMA_CAP_SP,
-		.base		= DMA0_BASE,
-		.chan_size	= DMA0_SIZE,
-		.channels	= 8,
-		.irq		= IRQ_NUM_EXT_LEVEL5,
-	},
-	.ops	= &acp_dai_sp_dma_ops,
-},
-#ifdef ACP_BT_ENABLE
-{
-	.plat_data = {
-		.id             = DMA_ID_DAI,
-		.dir            = DMA_DIR_DEV_TO_MEM | DMA_DIR_MEM_TO_DEV,
-		.devs           = DMA_DEV_BT,
-		.caps           = DMA_CAP_BT,
-		.base           = DMA0_BASE,
-		.chan_size      = DMA0_SIZE,
-		.channels       = 8,
-		.irq            = IRQ_NUM_EXT_LEVEL5,
-	},
-	.ops    = &acp_dai_bt_dma_ops,
-},
-#endif
-};
-
-static const struct dma_info lib_dma = {
-	.dma_array = cache_to_uncache_init((struct dma *)dma),
-	.num_dmas = ARRAY_SIZE(dma)
-};
-
-int acp_dma_init(struct sof *sof)
-{
-	int i;
-	uint32_t descr_base;
-	volatile acp_scratch_mem_config_t *pscratch_mem_cfg =
-		(volatile acp_scratch_mem_config_t *)(PU_REGISTER_BASE + SCRATCH_REG_OFFSET);
-
-	descr_base = (uint32_t)(&pscratch_mem_cfg->acp_cfg_dma_descriptor);
-	descr_base = (descr_base - ACP_ADDR_MASK);
-	/* configure dma descriptor base addr */
-	io_reg_write((PU_REGISTER_BASE + ACP_DMA_DESC_BASE_ADDR), descr_base);
-	io_reg_write((PU_REGISTER_BASE + ACP_DMA_DESC_MAX_NUM_DSCR), 0x1);
-	/* early lock initialization for ref counting */
-	for (i = 0; i < ARRAY_SIZE(dma); i++)
-		k_spinlock_init(&dma[i].lock);
-	sof->dma_info = &lib_dma;
-	return 0;
-}
diff --git a/src/platform/amd/renoir/lib/memory.c b/src/platform/amd/renoir/lib/memory.c
deleted file mode 100644
index bfee7c08174d..000000000000
--- a/src/platform/amd/renoir/lib/memory.c
+++ /dev/null
@@ -1,95 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-//
-// Copyright 2021 AMD
-//
-// Author:Basavaraj Hiregoudar <basavaraj.hiregoudar@amd.com>
-
-#include <sof/common.h>
-#include <sof/lib/mm_heap.h>
-#include <sof/lib/memory.h>
-#include <sof/platform.h>
-#include <rtos/sof.h>
-#include <ipc/topology.h>
-
-/* Heap blocks for system runtime */
-static struct block_hdr sys_rt_block64[HEAP_SYS_RT_COUNT64];
-static struct block_hdr sys_rt_block512[HEAP_SYS_RT_COUNT512];
-static struct block_hdr sys_rt_block1024[HEAP_SYS_RT_COUNT1024];
-
-/* Heap memory for system runtime */
-static struct block_map sys_rt_heap_map[] = {
-	BLOCK_DEF(64, HEAP_SYS_RT_COUNT64, sys_rt_block64),
-	BLOCK_DEF(512, HEAP_SYS_RT_COUNT512, sys_rt_block512),
-	BLOCK_DEF(1024, HEAP_SYS_RT_COUNT1024, sys_rt_block1024),
-};
-
-/* Heap blocks for modules */
-static struct block_hdr mod_block16[HEAP_RT_COUNT16];
-static struct block_hdr mod_block32[HEAP_RT_COUNT32];
-static struct block_hdr mod_block64[HEAP_RT_COUNT64];
-static struct block_hdr mod_block128[HEAP_RT_COUNT128];
-static struct block_hdr mod_block256[HEAP_RT_COUNT256];
-static struct block_hdr mod_block512[HEAP_RT_COUNT512];
-static struct block_hdr mod_block1024[HEAP_RT_COUNT1024];
-static struct block_hdr mod_block2048[HEAP_RT_COUNT2048];
-
-/* Heap memory map for modules */
-static struct block_map rt_heap_map[] = {
-	BLOCK_DEF(16, HEAP_RT_COUNT16, mod_block16),
-	BLOCK_DEF(32, HEAP_RT_COUNT32, mod_block32),
-	BLOCK_DEF(64, HEAP_RT_COUNT64, mod_block64),
-	BLOCK_DEF(128, HEAP_RT_COUNT128, mod_block128),
-	BLOCK_DEF(256, HEAP_RT_COUNT256, mod_block256),
-	BLOCK_DEF(512, HEAP_RT_COUNT512, mod_block512),
-	BLOCK_DEF(1024, HEAP_RT_COUNT1024, mod_block1024),
-	BLOCK_DEF(2048, HEAP_RT_COUNT2048, mod_block2048),
-};
-
-/* Heap blocks for buffers */
-static struct block_hdr buf_block[HEAP_BUFFER_COUNT];
-
-/* Heap memory map for buffers */
-static struct block_map buf_heap_map[] = {
-	BLOCK_DEF(HEAP_BUFFER_BLOCK_SIZE, HEAP_BUFFER_COUNT, buf_block),
-};
-
-static struct mm memmap = {
-	.system[0] = {
-		.heap = HEAP_SYSTEM_BASE,
-		.size = HEAP_SYSTEM_SIZE,
-		.info = {.free = HEAP_SYSTEM_SIZE,},
-		.caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_DMA,
-	},
-	.system_runtime[0] = {
-		.blocks = ARRAY_SIZE(sys_rt_heap_map),
-		.map = sys_rt_heap_map,
-		.heap = HEAP_SYS_RUNTIME_BASE,
-		.size = HEAP_SYS_RUNTIME_SIZE,
-		.info = {.free = HEAP_SYS_RUNTIME_SIZE,},
-		.caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_DMA,
-	},
-	.runtime[0] = {
-		.blocks = ARRAY_SIZE(rt_heap_map),
-		.map = rt_heap_map,
-		.heap = HEAP_RUNTIME_BASE,
-		.size = HEAP_RUNTIME_SIZE,
-		.info = {.free = HEAP_RUNTIME_SIZE,},
-		.caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_DMA,
-	},
-	.buffer[0] = {
-		.blocks = ARRAY_SIZE(buf_heap_map),
-		.map = buf_heap_map,
-		.heap = HEAP_BUFFER_BASE,
-		.size = HEAP_BUFFER_SIZE,
-		.info = {.free = HEAP_BUFFER_SIZE,},
-		.caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_DMA | SOF_MEM_CAPS_CACHE | SOF_MEM_CAPS_HP,
-	},
-	.total = {.free = HEAP_SYSTEM_SIZE + HEAP_SYS_RUNTIME_SIZE +
-			HEAP_RUNTIME_SIZE + HEAP_BUFFER_SIZE,},
-};
-
-void platform_init_memmap(struct sof *sof)
-{
-	/* memmap has been initialized statically as a part of .data */
-	sof->memory_map = &memmap;
-}
diff --git a/src/platform/amd/renoir/platform.c b/src/platform/amd/renoir/platform.c
deleted file mode 100644
index bccbd7c5c399..000000000000
--- a/src/platform/amd/renoir/platform.c
+++ /dev/null
@@ -1,206 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-//
-//Copyright(c) 2021 AMD. All rights reserved.
-//
-//Author:       Basavaraj Hiregoudar <basavaraj.hiregoudar@amd.com>
-//              Anup Kulkarni <anup.kulkarni@amd.com>
-//              Bala Kishore <balakishore.pati@amd.com>
-
-#include <sof/compiler_info.h>
-#include <sof/debug/debug.h>
-#include <rtos/interrupt.h>
-#include <sof/drivers/acp_dai_dma.h>
-#include <sof/ipc/driver.h>
-#include <rtos/timer.h>
-#include <sof/fw-ready-metadata.h>
-#include <sof/lib/agent.h>
-#include <rtos/clk.h>
-#include <sof/lib/cpu.h>
-#include <sof/lib/dai.h>
-#include <sof/lib/dma.h>
-#include <sof/lib/mailbox.h>
-#include <sof/lib/memory.h>
-#include <sof/lib/mm_heap.h>
-#include <sof/platform.h>
-#include <sof/schedule/edf_schedule.h>
-#include <sof/schedule/ll_schedule.h>
-#include <sof/schedule/ll_schedule_domain.h>
-#include <rtos/sof.h>
-#include <sof/trace/dma-trace.h>
-#include <ipc/dai.h>
-#include <ipc/header.h>
-#include <ipc/info.h>
-#include <kernel/abi.h>
-#include <kernel/ext_manifest.h>
-#include <sof_versions.h>
-#include <errno.h>
-#include <stdint.h>
-#include <platform/chip_offset_byte.h>
-
-struct sof;
-static const struct sof_ipc_fw_ready ready
-	__attribute__((section(".fw_ready"))) = {
-	.hdr = {
-		.cmd = SOF_IPC_FW_READY,
-		.size = sizeof(struct sof_ipc_fw_ready),
-	},
-	/* dspbox is for DSP initiated IPC, hostbox is for host initiated IPC */
-	.version = {
-		.hdr.size = sizeof(struct sof_ipc_fw_version),
-		.micro = SOF_MICRO,
-		.minor = SOF_MINOR,
-		.major = SOF_MAJOR,
-#ifdef DEBUG_BUILD
-		/* only added in debug for reproducability in releases */
-		.build = SOF_BUILD,
-		.date = __DATE__,
-		.time = __TIME__,
-#endif
-		.tag = SOF_TAG,
-		.abi_version = SOF_ABI_VERSION,
-	},
-	.flags = DEBUG_SET_FW_READY_FLAGS,
-};
-
-#define NUM_ACP_WINDOWS		6
-
-const struct ext_man_windows xsram_window
-		__aligned(EXT_MAN_ALIGN) __section(".fw_metadata") __unused = {
-	.hdr = {
-		.type = EXT_MAN_ELEM_WINDOW,
-		.elem_size = ALIGN_UP_COMPILE(sizeof(struct ext_man_windows), EXT_MAN_ALIGN),
-	},
-	.window = {
-		.ext_hdr	= {
-			.hdr.cmd = SOF_IPC_FW_READY,
-			.hdr.size = sizeof(struct sof_ipc_window),
-			.type   = SOF_IPC_EXT_WINDOW,
-		},
-		.num_windows    = NUM_ACP_WINDOWS,
-		.window = {
-			{
-				.type   = SOF_IPC_REGION_UPBOX,
-				.id     = 0,
-				.flags  = 0,
-				.size   = MAILBOX_DSPBOX_SIZE,
-				.offset = MAILBOX_DSPBOX_OFFSET,
-			},
-			{
-				.type   = SOF_IPC_REGION_DOWNBOX,
-				.id     = 0,
-				.flags  = 0,
-				.size   = MAILBOX_HOSTBOX_SIZE,
-				.offset = MAILBOX_HOSTBOX_OFFSET,
-			},
-			{
-				.type   = SOF_IPC_REGION_DEBUG,
-				.id     = 0,
-				.flags  = 0,
-				.size   = MAILBOX_DEBUG_SIZE,
-				.offset = MAILBOX_DEBUG_OFFSET,
-			},
-			{
-				.type   = SOF_IPC_REGION_TRACE,
-				.id     = 0,
-				.flags  = 0,
-				.size   = MAILBOX_TRACE_SIZE,
-				.offset = MAILBOX_TRACE_OFFSET,
-			},
-			{
-				.type   = SOF_IPC_REGION_STREAM,
-				.id     = 0,
-				.flags  = 0,
-				.size   = MAILBOX_STREAM_SIZE,
-				.offset = MAILBOX_STREAM_OFFSET,
-			},
-			{
-				.type   = SOF_IPC_REGION_EXCEPTION,
-				.id     = 0,
-				.flags  = 0,
-				.size   = MAILBOX_EXCEPTION_SIZE,
-				.offset = MAILBOX_EXCEPTION_OFFSET,
-			},
-		},
-	},
-};
-
-static struct timer timer_shared = {
-	.id = TIMER0,
-	.irq = IRQ_NUM_TIMER0,
-};
-
-int platform_init(struct sof *sof)
-{
-	int ret;
-
-	sof->platform_timer = &timer_shared;
-	sof->cpu_timers = sof->platform_timer;
-
-	/* to view system memory */
-	platform_interrupt_init();
-	platform_clock_init(sof);
-	scheduler_init_edf();
-	/* init low latency domains and schedulers */
-	/* CONFIG_SYSTICK_PERIOD set as PLATFORM_DEFAULT_CLOCK */
-	sof->platform_timer_domain = timer_domain_init(sof->platform_timer,
-						PLATFORM_DEFAULT_CLOCK);
-	scheduler_init_ll(sof->platform_timer_domain);
-	platform_timer_start(sof->platform_timer);
-	/*CONFIG_SYSTICK_PERIOD hardcoded as 200000*/
-	sa_init(sof, 200000);
-	clock_set_freq(CLK_CPU(cpu_get_id()), CLK_MAX_CPU_HZ);
-	/* init DMA */
-	ret = acp_dma_init(sof);
-	if (ret < 0)
-		return -ENODEV;
-	/* Init DMA platform domain */
-	sof->platform_dma_domain = dma_multi_chan_domain_init(&sof->dma_info->dma_array[0],
-			sizeof(sof->dma_info->dma_array), PLATFORM_DEFAULT_CLOCK, true);
-	sof->platform_dma_domain->full_sync = true;
-	scheduler_init_ll(sof->platform_dma_domain);
-	/* initialize the host IPC mechanisms */
-	ipc_init(sof);
-	/* initialize the DAI mechanisms */
-	ret = dai_init(sof);
-	if (ret < 0)
-		return -ENODEV;
-#if CONFIG_TRACE
-	/* Initialize DMA for Trace*/
-	trace_point(TRACE_BOOT_PLATFORM_DMA_TRACE);
-	sof->dmat->config.elem_array.elems = rzalloc(SOF_MEM_FLAG_KERNEL,
-							sizeof(struct dma_sg_elem) * 1);
-	sof->dmat->config.elem_array.count = 1;
-	sof->dmat->config.elem_array.elems->dest = 0x03800000;
-	sof->dmat->config.elem_array.elems->size = 65536;
-	sof->dmat->config.scatter = 0;
-	dma_trace_init_complete(sof->dmat);
-#endif
-	/* show heap status */
-	heap_trace_all(1);
-	return 0;
-}
-
-int platform_boot_complete(uint32_t boot_message)
-{
-	acp_sw_intr_trig_t  swintrtrig;
-	volatile acp_scratch_mem_config_t *pscratch_mem_cfg =
-		(volatile acp_scratch_mem_config_t *)(PU_REGISTER_BASE + SCRATCH_REG_OFFSET);
-	mailbox_dspbox_write(0, &ready, sizeof(ready));
-	pscratch_mem_cfg->acp_dsp_msg_write = 1;
-	acp_dsp_to_host_intr_trig();
-	/* Configures the trigger bit in ACP_DSP_SW_INTR_TRIG register */
-	swintrtrig = (acp_sw_intr_trig_t)io_reg_read(PU_REGISTER_BASE + ACP_SW_INTR_TRIG);
-	swintrtrig.bits.trig_dsp0_to_host_intr  = INTERRUPT_DISABLE;
-	io_reg_write((PU_REGISTER_BASE + ACP_SW_INTR_TRIG), swintrtrig.u32all);
-	clock_set_freq(CLK_CPU(cpu_get_id()), CLK_DEFAULT_CPU_HZ);
-	return 0;
-}
-int platform_context_save(struct sof *sof)
-{
-	return 0;
-}
-
-void platform_wait_for_interrupt(int level)
-{
-	arch_wait_for_interrupt(level);
-}
diff --git a/src/platform/amd/renoir/renoir.x.in b/src/platform/amd/renoir/renoir.x.in
deleted file mode 100644
index 34792f24dee9..000000000000
--- a/src/platform/amd/renoir/renoir.x.in
+++ /dev/null
@@ -1,560 +0,0 @@
-/*
- * Linker Script for AMD Renoir
- *
- * This script is run through the GNU C preprocessor to align the memory
- * offsets with headers.
- *
- * Use spaces for formatting as cpp ignore tab sizes.
- */
-
-#include <sof/lib/memory.h>
-#include <xtensa/config/core-isa.h>
-
-OUTPUT_ARCH(xtensa)
-
-MEMORY
-{
-  vector_reset_text :
-        org = XCHAL_RESET_VECTOR0_PADDR,
-        len = SOF_MEM_RESET_TEXT_SIZE
-  vector_reset_lit :
-        org = XCHAL_RESET_VECTOR0_PADDR + SOF_MEM_RESET_TEXT_SIZE,
-        len = SOF_MEM_RESET_LIT_SIZE
-  vector_base_text :
-        org = XCHAL_VECBASE_RESET_PADDR,
-        len = SOF_MEM_VECBASE_LIT_SIZE
-  vector_int2_lit :
-        org = XCHAL_INTLEVEL2_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
-        len = SOF_MEM_VECT_LIT_SIZE
-  vector_int2_text :
-        org = XCHAL_INTLEVEL2_VECTOR_PADDR,
-        len = SOF_MEM_VECT_TEXT_SIZE
-  vector_int3_lit :
-        org = XCHAL_INTLEVEL3_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
-        len = SOF_MEM_VECT_LIT_SIZE
-  vector_int3_text :
-        org = XCHAL_INTLEVEL3_VECTOR_PADDR,
-        len = SOF_MEM_VECT_TEXT_SIZE
-  vector_int4_lit :
-        org = XCHAL_INTLEVEL4_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
-        len = SOF_MEM_VECT_LIT_SIZE
-  vector_int4_text :
-        org = XCHAL_INTLEVEL4_VECTOR_PADDR,
-        len = SOF_MEM_VECT_TEXT_SIZE
-  vector_int5_lit :
-        org = XCHAL_INTLEVEL5_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
-        len = SOF_MEM_VECT_LIT_SIZE
-  vector_int5_text :
-        org = XCHAL_INTLEVEL5_VECTOR_PADDR,
-        len = SOF_MEM_VECT_TEXT_SIZE
-  vector_kernel_lit :
-        org = XCHAL_KERNEL_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
-        len = SOF_MEM_VECT_LIT_SIZE
-  vector_kernel_text :
-        org = XCHAL_KERNEL_VECTOR_PADDR,
-        len = SOF_MEM_VECT_TEXT_SIZE
-  vector_user_lit :
-        org = XCHAL_USER_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
-        len = SOF_MEM_VECT_LIT_SIZE
-  vector_user_text :
-        org = XCHAL_USER_VECTOR_PADDR,
-        len = SOF_MEM_VECT_TEXT_SIZE
-  vector_double_lit :
-        org = XCHAL_DOUBLEEXC_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
-        len = SOF_MEM_VECT_LIT_SIZE
-  vector_double_text :
-        org = XCHAL_DOUBLEEXC_VECTOR_PADDR,
-        len = SOF_MEM_VECT_TEXT_SIZE
-  sof_iram_text_start :
-        org = XCHAL_DOUBLEEXC_VECTOR_PADDR + SOF_MEM_VECT_TEXT_SIZE,
-        len =  IRAM_BASE + (XCHAL_DOUBLEEXC_VECTOR_PADDR + SOF_MEM_VECT_TEXT_SIZE)
-  sof_sdram0 :
-        org = DRAM0_BASE,
-        len = DRAM0_SIZE
-  system_heap :
-        org = HEAP_SYSTEM_BASE,
-        len = HEAP_SYSTEM_SIZE
-  system_runtime_heap :
-        org = HEAP_SYS_RUNTIME_BASE,
-        len = HEAP_SYS_RUNTIME_SIZE
-  runtime_heap :
-        org = HEAP_RUNTIME_BASE,
-        len = HEAP_RUNTIME_SIZE
-  buffer_heap :
-        org = HEAP_BUFFER_BASE,
-        len = HEAP_BUFFER_SIZE
- sof_stack :
-        org = SOF_STACK_END,
-        len = SOF_STACK_BASE - SOF_STACK_END,
-sof_sdram1 :
-        org = HEAP_BUFFER_BASE + HEAP_BUFFER_SIZE,
-        len = DRAM1_SIZE- (HEAP_SYSTEM_SIZE +HEAP_SYS_RUNTIME_SIZE + HEAP_RUNTIME_SIZE + HEAP_BUFFER_SIZE + SOF_STACK_SIZE )
-  static_uuid_entries_seg (!ari) :
-	org = UUID_ENTRY_ELF_BASE,
-	len = UUID_ENTRY_ELF_SIZE
-  static_log_entries_seg (!ari) :
-        org = LOG_ENTRY_ELF_BASE,
-        len = LOG_ENTRY_ELF_SIZE
- fw_metadata_seg (!ari) :
-        org = EXT_MANIFEST_ELF_BASE,
-        len = EXT_MANIFEST_ELF_SIZE
-}
-
-PHDRS
-{
-  vector_reset_text_phdr PT_LOAD;
-  vector_reset_lit_phdr PT_LOAD;
-  vector_base_text_phdr PT_LOAD;
-  vector_base_lit_phdr PT_LOAD;
-  vector_int2_text_phdr PT_LOAD;
-  vector_int2_lit_phdr PT_LOAD;
-  vector_int3_text_phdr PT_LOAD;
-  vector_int3_lit_phdr PT_LOAD;
-  vector_int4_text_phdr PT_LOAD;
-  vector_int4_lit_phdr PT_LOAD;
-  vector_int5_text_phdr PT_LOAD;
-  vector_int5_lit_phdr PT_LOAD;
-  vector_kernel_text_phdr PT_LOAD;
-  vector_kernel_lit_phdr PT_LOAD;
-  vector_user_text_phdr PT_LOAD;
-  vector_user_lit_phdr PT_LOAD;
-  vector_double_text_phdr PT_LOAD;
-  vector_double_lit_phdr PT_LOAD;
-  sof_iram_text_start_phdr PT_LOAD;
-  sof_sdram0_phdr PT_LOAD;
-   sof_stack_phdr PT_LOAD;
-  system_heap_phdr PT_LOAD;
-  system_runtime_heap_phdr PT_LOAD;
-  runtime_heap_phdr PT_LOAD;
-  buffer_heap_phdr PT_LOAD;
-  sof_sdram1_phdr PT_LOAD;
-  static_uuid_entries_phdr PT_NOTE;
-  static_log_entries_phdr PT_NOTE;
- metadata_entries_phdr PT_NOTE;
-}
-
-/*  Default entry point:  */
-ENTRY(_ResetVector)
-_rom_store_table = 0;
-
-/* ABI0 does not use Window base */
-PROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR);
-
-/* Various memory-map dependent cache attribute settings: */
-_memmap_cacheattr_wb_base = 0x44024000;
-_memmap_cacheattr_wt_base = 0x11021000;
-_memmap_cacheattr_bp_base = 0x22022000;
-_memmap_cacheattr_unused_mask = 0x00F00FFF;
-_memmap_cacheattr_wb_trapnull = 0x4422422F;
-_memmap_cacheattr_wba_trapnull = 0x4422422F;
-_memmap_cacheattr_wbna_trapnull = 0x25222222;
-_memmap_cacheattr_wt_trapnull = 0x1122122F;
-_memmap_cacheattr_bp_trapnull = 0x2222222F;
-_memmap_cacheattr_wb_strict = 0x44F24FFF;
-_memmap_cacheattr_wt_strict = 0x11F21FFF;
-_memmap_cacheattr_bp_strict = 0x22F22FFF;
-_memmap_cacheattr_wb_allvalid = 0x44224222;
-_memmap_cacheattr_wt_allvalid = 0x11221222;
-_memmap_cacheattr_bp_allvalid = 0x22222222;
-PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wbna_trapnull);
-_EXT_MAN_ALIGN_ = 16;
-EXTERN(ext_man_fw_ver)
-
-
-SECTIONS
-{
-  .ResetVector.text : ALIGN(4)
-  {
-    _ResetVector_text_start = ABSOLUTE(.);
-    KEEP (*(.ResetVector.text))
-    _ResetVector_text_end = ABSOLUTE(.);
-  } >vector_reset_text :vector_reset_text_phdr
-
-  .ResetVector.literal : ALIGN(4)
-  {
-    _ResetVector_literal_start = ABSOLUTE(.);
-    *(.ResetVector.literal)
-    _ResetVector_literal_end = ABSOLUTE(.);
-  } >vector_reset_lit :vector_reset_lit_phdr
-
-  .WindowVectors.text : ALIGN(4)
-  {
-    _WindowVectors_text_start = ABSOLUTE(.);
-    KEEP (*(.WindowVectors.text))
-    _WindowVectors_text_end = ABSOLUTE(.);
-  } >vector_base_text :vector_base_text_phdr
-
-  .Level2InterruptVector.literal : ALIGN(4)
-  {
-    _Level2InterruptVector_literal_start = ABSOLUTE(.);
-    *(.Level2InterruptVector.literal)
-    _Level2InterruptVector_literal_end = ABSOLUTE(.);
-  } >vector_int2_lit :vector_int2_lit_phdr
-
-  .Level2InterruptVector.text : ALIGN(4)
-  {
-    _Level2InterruptVector_text_start = ABSOLUTE(.);
-    KEEP (*(.Level2InterruptVector.text))
-    _Level2InterruptVector_text_end = ABSOLUTE(.);
-  } >vector_int2_text :vector_int2_text_phdr
-
-  .Level3InterruptVector.literal : ALIGN(4)
-  {
-    _Level3InterruptVector_literal_start = ABSOLUTE(.);
-    *(.Level3InterruptVector.literal)
-    _Level3InterruptVector_literal_end = ABSOLUTE(.);
-  } >vector_int3_lit :vector_int3_lit_phdr
-
-  .Level3InterruptVector.text : ALIGN(4)
-  {
-    _Level3InterruptVector_text_start = ABSOLUTE(.);
-    KEEP (*(.Level3InterruptVector.text))
-    _Level3InterruptVector_text_end = ABSOLUTE(.);
-  } >vector_int3_text :vector_int3_text_phdr
-
-  .Level4InterruptVector.literal : ALIGN(4)
-  {
-    _Level4InterruptVector_literal_start = ABSOLUTE(.);
-    *(.Level4InterruptVector.literal)
-    _Level4InterruptVector_literal_end = ABSOLUTE(.);
-  } >vector_int4_lit :vector_int4_lit_phdr
-
-  .Level4InterruptVector.text : ALIGN(4)
-  {
-    _Level4InterruptVector_text_start = ABSOLUTE(.);
-    KEEP (*(.Level4InterruptVector.text))
-    _Level4InterruptVector_text_end = ABSOLUTE(.);
-  } >vector_int4_text :vector_int4_text_phdr
-
-  .Level5InterruptVector.literal : ALIGN(4)
-  {
-    _Level5InterruptVector_literal_start = ABSOLUTE(.);
-    *(.Level5InterruptVector.literal)
-    _Level5InterruptVector_literal_end = ABSOLUTE(.);
-  } >vector_int5_lit :vector_int5_lit_phdr
-
-  .Level5InterruptVector.text : ALIGN(4)
-  {
-    _Level5InterruptVector_text_start = ABSOLUTE(.);
-    KEEP (*(.Level5InterruptVector.text))
-    _Level5InterruptVector_text_end = ABSOLUTE(.);
-  } >vector_int5_text :vector_int5_text_phdr
-
-  .DebugExceptionVector.literal : ALIGN(4)
-  {
-    _DebugExceptionVector_literal_start = ABSOLUTE(.);
-    *(.DebugExceptionVector.literal)
-    _DebugExceptionVector_literal_end = ABSOLUTE(.);
-  } >vector_int4_lit :vector_int4_lit_phdr
-
-  .DebugExceptionVector.text : ALIGN(4)
-  {
-    _DebugExceptionVector_text_start = ABSOLUTE(.);
-    KEEP (*(.DebugExceptionVector.text))
-    _DebugExceptionVector_text_end = ABSOLUTE(.);
-  } >vector_int4_text :vector_int4_text_phdr
-
-  .NMIExceptionVector.literal : ALIGN(4)
-  {
-    _NMIExceptionVector_literal_start = ABSOLUTE(.);
-    *(.NMIExceptionVector.literal)
-    _NMIExceptionVector_literal_end = ABSOLUTE(.);
-  } >vector_int5_lit :vector_int5_lit_phdr
-
-  .NMIExceptionVector.text : ALIGN(4)
-  {
-    _NMIExceptionVector_text_start = ABSOLUTE(.);
-    KEEP (*(.NMIExceptionVector.text))
-    _NMIExceptionVector_text_end = ABSOLUTE(.);
-  } >vector_int5_text :vector_int5_text_phdr
-
-  .KernelExceptionVector.literal : ALIGN(4)
-  {
-    _KernelExceptionVector_literal_start = ABSOLUTE(.);
-    *(.KernelExceptionVector.literal)
-    _KernelExceptionVector_literal_end = ABSOLUTE(.);
-  } >vector_kernel_lit :vector_kernel_lit_phdr
-
-  .KernelExceptionVector.text : ALIGN(4)
-  {
-    _KernelExceptionVector_text_start = ABSOLUTE(.);
-    KEEP (*(.KernelExceptionVector.text))
-    _KernelExceptionVector_text_end = ABSOLUTE(.);
-  } >vector_kernel_text :vector_kernel_text_phdr
-
-  .UserExceptionVector.literal : ALIGN(4)
-  {
-    _UserExceptionVector_literal_start = ABSOLUTE(.);
-    *(.UserExceptionVector.literal)
-    _UserExceptionVector_literal_end = ABSOLUTE(.);
-  } >vector_user_lit :vector_user_lit_phdr
-
-  .UserExceptionVector.text : ALIGN(4)
-  {
-    _UserExceptionVector_text_start = ABSOLUTE(.);
-    KEEP (*(.UserExceptionVector.text))
-    _UserExceptionVector_text_end = ABSOLUTE(.);
-  } >vector_user_text :vector_user_text_phdr
-
-  .DoubleExceptionVector.literal : ALIGN(4)
-  {
-    _DoubleExceptionVector_literal_start = ABSOLUTE(.);
-    *(.DoubleExceptionVector.literal)
-    _DoubleExceptionVector_literal_end = ABSOLUTE(.);
-  } >vector_double_lit :vector_double_lit_phdr
-
-  .DoubleExceptionVector.text : ALIGN(4)
-  {
-    _DoubleExceptionVector_text_start = ABSOLUTE(.);
-    KEEP (*(.DoubleExceptionVector.text))
-    _DoubleExceptionVector_text_end = ABSOLUTE(.);
-  } >vector_double_text :vector_double_text_phdr
-
-  .iram.text : ALIGN(4)
-  {
-    _stext = .;
-    _iram_text_start = ABSOLUTE(.);
-    *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)
-    _iram_text_end = ABSOLUTE(.);
-  } >sof_iram_text_start :sof_iram_text_start_phdr
-
-	/* stack */
- _end = SOF_STACK_END;
-  PROVIDE(end = SOF_STACK_END);
-  _stack_sentry = SOF_STACK_END;
-  __stack = SOF_STACK_BASE;
-
-  .text : ALIGN(4)
-  {
-    _stext = .;
-    _text_start = ABSOLUTE(.);
-    *(.entry.text)
-    *(.init.literal)
-    KEEP(*(.init))
-    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
-    *(.fini.literal)
-    KEEP(*(.fini))
-    *(.gnu.version)
-    _text_end = ABSOLUTE(.);
-    _etext = .;
-  } >sof_iram_text_start :sof_iram_text_start_phdr
-
-
-  .rodata : ALIGN(4)
-  {
-    _rodata_start = ABSOLUTE(.);
-    *(.rodata)
-    *(.rodata.*)
-    *(.gnu.linkonce.r.*)
-    *(.rodata1)
-    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);
-    KEEP (*(.xt_except_table))
-    KEEP (*(.gcc_except_table))
-    *(.gnu.linkonce.e.*)
-    *(.gnu.version_r)
-    KEEP (*(.eh_frame))
-    /*  C++ constructor and destructor tables, properly ordered:  */
-    KEEP (*crtbegin.o(.ctors))
-    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
-    KEEP (*(SORT(.ctors.*)))
-    KEEP (*(.ctors))
-    KEEP (*crtbegin.o(.dtors))
-    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
-    KEEP (*(SORT(.dtors.*)))
-    KEEP (*(.dtors))
-    /*  C++ exception handlers table:  */
-    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);
-    *(.xt_except_desc)
-    *(.gnu.linkonce.h.*)
-    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
-    *(.xt_except_desc_end)
-    *(.dynamic)
-    *(.gnu.version_d)
-    . = ALIGN(4);		/* this table MUST be 4-byte aligned */
-    _bss_table_start = ABSOLUTE(.);
-    LONG(_bss_start)
-    LONG(_bss_end)
-    _bss_table_end = ABSOLUTE(.);
-    _rodata_end = ABSOLUTE(.);
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-
-  .module_init : ALIGN(4)
-  {
-   _module_init_start = ABSOLUTE(.);
-    *(*.initcall)
-    _module_init_end = ABSOLUTE(.);
-  } >sof_sdram0 :sof_sdram0_phdr
-
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-  {
-    _data_start = ABSOLUTE(.);
-    *(.data)
-    *(.data.*)
-    *(.gnu.linkonce.d.*)
-    KEEP(*(.gnu.linkonce.d.*personality*))
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-    *(.sdata)
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-    *(*.lit4)
-    *(.lit4.*)
-    *(.gnu.linkonce.lit4.*)
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-  {
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-
-
-  .bss (NOLOAD) : ALIGN(8)
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-
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-.sof_stack (NOLOAD) : ALIGN(8)
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-  .reset.rodata : ALIGN(4)
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-  {
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diff --git a/src/platform/amd/vangogh/CMakeLists.txt b/src/platform/amd/vangogh/CMakeLists.txt
deleted file mode 100644
index ec909d60035f..000000000000
--- a/src/platform/amd/vangogh/CMakeLists.txt
+++ /dev/null
@@ -1,5 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-
-add_subdirectory(lib)
-
-add_local_sources(sof platform.c)
diff --git a/src/platform/amd/vangogh/include/arch/xtensa/config/core-isa.h b/src/platform/amd/vangogh/include/arch/xtensa/config/core-isa.h
deleted file mode 100644
index d6d5af62f9ea..000000000000
--- a/src/platform/amd/vangogh/include/arch/xtensa/config/core-isa.h
+++ /dev/null
@@ -1,672 +0,0 @@
-/*
- * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
- *				processor CORE configuration
- *
- *  See <xtensa/config/core.h>, which includes this file, for more details.
- */
-
-/* Xtensa processor core configuration information.
-
-   Customer ID=7490; Build=0x8176c; Copyright (c) 1999-2019 Tensilica Inc.
-
-   Permission is hereby granted, free of charge, to any person obtaining
-   a copy of this software and associated documentation files (the
-   "Software"), to deal in the Software without restriction, including
-   without limitation the rights to use, copy, modify, merge, publish,
-   distribute, sublicense, and/or sell copies of the Software, and to
-   permit persons to whom the Software is furnished to do so, subject to
-   the following conditions:
-
-   The above copyright notice and this permission notice shall be included
-   in all copies or substantial portions of the Software.
-
-   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*/
-
-#ifndef _XTENSA_CORE_CONFIGURATION_H
-#define _XTENSA_CORE_CONFIGURATION_H
-
-//depot/dev/Homewood/Xtensa/SWConfig/hal/core-common.h.tph#24 - edit change 444323 (text+ko)
-
-/****************************************************************************
-	    Parameters Useful for Any Code, USER or PRIVILEGED
- ****************************************************************************/
-
-/*
- *  Note:  Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
- *  configured, and a value of 0 otherwise.  These macros are always defined.
- */
-
-/*----------------------------------------------------------------------
-				ISA
-  ----------------------------------------------------------------------
-*/
-
-#define XCHAL_HAVE_BE			0	/* big-endian byte ordering */
-#define XCHAL_HAVE_WINDOWED		1	/* windowed registers option */
-#define XCHAL_NUM_AREGS			64	/* num of physical addr regs */
-#define XCHAL_NUM_AREGS_LOG2		6	/* log2(XCHAL_NUM_AREGS) */
-#define XCHAL_MAX_INSTRUCTION_SIZE	8	/* max instr bytes (3..8) */
-#define XCHAL_HAVE_DEBUG		1	/* debug option */
-#define XCHAL_HAVE_DENSITY		1	/* 16-bit instructions */
-#define XCHAL_HAVE_LOOPS		1	/* zero-overhead loops */
-#define XCHAL_LOOP_BUFFER_SIZE		256	/* zero-ov. loop instr buffer size */
-#define XCHAL_HAVE_NSA			1	/* NSA/NSAU instructions */
-#define XCHAL_HAVE_MINMAX		1	/* MIN/MAX instructions */
-#define XCHAL_HAVE_SEXT			1	/* SEXT instruction */
-#define XCHAL_HAVE_DEPBITS		0	/* DEPBITS instruction */
-#define XCHAL_HAVE_CLAMPS		1	/* CLAMPS instruction */
-#define XCHAL_HAVE_MUL16		1	/* MUL16S/MUL16U instructions */
-#define XCHAL_HAVE_MUL32		1	/* MULL instruction */
-#define XCHAL_HAVE_MUL32_HIGH		1	/* MULUH/MULSH instructions */
-#define XCHAL_HAVE_DIV32		1	/* QUOS/QUOU/REMS/REMU instructions */
-#define XCHAL_HAVE_L32R			1	/* L32R instruction */
-#define XCHAL_HAVE_ABSOLUTE_LITERALS	0	/* non-PC-rel (extended) L32R */
-#define XCHAL_HAVE_CONST16		0	/* CONST16 instruction */
-#define XCHAL_HAVE_ADDX			1	/* ADDX#/SUBX# instructions */
-#define XCHAL_HAVE_EXCLUSIVE            0	/* L32EX/S32EX instructions */
-#define XCHAL_HAVE_WIDE_BRANCHES	0	/* B*.W18 or B*.W15 instr's */
-#define XCHAL_HAVE_PREDICTED_BRANCHES	0	/* B[EQ/EQZ/NE/NEZ]T instr's */
-#define XCHAL_HAVE_CALL4AND12		1	/* (obsolete option) */
-#define XCHAL_HAVE_ABS			1	/* ABS instruction */
-#define XCHAL_HAVE_RELEASE_SYNC		1	/* L32AI/S32RI instructions */
-#define XCHAL_HAVE_S32C1I		1	/* S32C1I instruction */
-#define XCHAL_HAVE_SPECULATION		0	/* speculation */
-#define XCHAL_HAVE_FULL_RESET		1	/* all regs/state reset */
-#define XCHAL_NUM_CONTEXTS		1	/* */
-#define XCHAL_NUM_MISC_REGS		2	/* num of scratch regs (0..4) */
-#define XCHAL_HAVE_TAP_MASTER		0	/* JTAG TAP control instr's */
-#define XCHAL_HAVE_PRID			1	/* processor ID register */
-#define XCHAL_HAVE_EXTERN_REGS		1	/* WER/RER instructions */
-#define XCHAL_HAVE_MX			0	/* MX core (Tensilica internal) */
-#define XCHAL_HAVE_MP_INTERRUPTS	0	/* interrupt distributor port */
-#define XCHAL_HAVE_MP_RUNSTALL		0	/* core RunStall control port */
-#define XCHAL_HAVE_PSO			0	/* Power Shut-Off */
-#define XCHAL_HAVE_PSO_CDM		0	/* core/debug/mem pwr domains */
-#define XCHAL_HAVE_PSO_FULL_RETENTION	0	/* all regs preserved on PSO */
-#define XCHAL_HAVE_THREADPTR		1	/* THREADPTR register */
-#define XCHAL_HAVE_BOOLEANS		1	/* boolean registers */
-#define XCHAL_HAVE_CP			1	/* CPENABLE reg (coprocessor) */
-#define XCHAL_CP_MAXCFG			2	/* max allowed cp id plus one */
-#define XCHAL_HAVE_MAC16		0	/* MAC16 package */
-#define XCHAL_HAVE_LX			1	/* LX core */
-#define XCHAL_HAVE_NX			0	/* NX core (starting RH) */
-
-#define XCHAL_HAVE_SUPERGATHER		0	/* SuperGather */
-
-#define XCHAL_HAVE_FUSION		0	/* Fusion*/
-#define XCHAL_HAVE_FUSION_FP		0	/* Fusion FP option */
-#define XCHAL_HAVE_FUSION_LOW_POWER	0	/* Fusion Low Power option */
-#define XCHAL_HAVE_FUSION_AES		0	/* Fusion BLE/Wifi AES-128 CCM option */
-#define XCHAL_HAVE_FUSION_CONVENC	0	/* Fusion Conv Encode option */
-#define XCHAL_HAVE_FUSION_LFSR_CRC	0	/* Fusion LFSR-CRC option */
-#define XCHAL_HAVE_FUSION_BITOPS	0	/* Fusion Bit Operations Support option */
-#define XCHAL_HAVE_FUSION_AVS		0	/* Fusion AVS option */
-#define XCHAL_HAVE_FUSION_16BIT_BASEBAND 0	/* Fusion 16-bit Baseband option */
-#define XCHAL_HAVE_FUSION_VITERBI	0	/* Fusion Viterbi option */
-#define XCHAL_HAVE_FUSION_SOFTDEMAP	0	/* Fusion Soft Bit Demap option */
-#define XCHAL_HAVE_HIFIPRO		0	/* HiFiPro Audio Engine pkg */
-#define XCHAL_HAVE_HIFI5		0	/* HiFi5 Audio Engine pkg */
-#define XCHAL_HAVE_HIFI5_NN_MAC		0	/* HiFi5 Audio Engine NN-MAC option */
-#define XCHAL_HAVE_HIFI5_VFPU		0	/* HiFi5 Audio Engine Single-Precision VFPU option */
-#define XCHAL_HAVE_HIFI5_HP_VFPU	0	/* HiFi5 Audio Engine Half-Precision VFPU option */
-#define XCHAL_HAVE_HIFI4		0	/* HiFi4 Audio Engine pkg */
-#define XCHAL_HAVE_HIFI4_VFPU		0	/* HiFi4 Audio Engine VFPU option */
-#define XCHAL_HAVE_HIFI3		1	/* HiFi3 Audio Engine pkg */
-#define XCHAL_HAVE_HIFI3_VFPU		1	/* HiFi3 Audio Engine VFPU option */
-#define XCHAL_HAVE_HIFI3Z		1	/* HiFi3Z Audio Engine pkg */
-#define XCHAL_HAVE_HIFI3Z_VFPU	1	/* HiFi3Z Audio Engine VFPU option */
-#define XCHAL_HAVE_HIFI2		0	/* HiFi2 Audio Engine pkg */
-#define XCHAL_HAVE_HIFI2EP		0	/* HiFi2EP */
-#define XCHAL_HAVE_HIFI_MINI		0
-
-
-
-#define XCHAL_HAVE_VECTORFPU2005	0	/* vector floating-point pkg */
-#define XCHAL_HAVE_USER_DPFPU		0       /* user DP floating-point pkg */
-#define XCHAL_HAVE_USER_SPFPU		1       /* user SP floating-point pkg */
-#define XCHAL_HAVE_FP			1	/* single prec floating point */
-#define XCHAL_HAVE_FP_DIV		1	/* FP with DIV instructions */
-#define XCHAL_HAVE_FP_RECIP		1	/* FP with RECIP instructions */
-#define XCHAL_HAVE_FP_SQRT		1	/* FP with SQRT instructions */
-#define XCHAL_HAVE_FP_RSQRT		1	/* FP with RSQRT instructions */
-#define XCHAL_HAVE_DFP			0	/* double precision FP pkg */
-#define XCHAL_HAVE_DFP_DIV		0	/* DFP with DIV instructions */
-#define XCHAL_HAVE_DFP_RECIP		0	/* DFP with RECIP instructions*/
-#define XCHAL_HAVE_DFP_SQRT		0	/* DFP with SQRT instructions */
-#define XCHAL_HAVE_DFP_RSQRT		0	/* DFP with RSQRT instructions*/
-#define XCHAL_HAVE_DFP_ACCEL		0	/* double precision FP acceleration pkg */
-#define XCHAL_HAVE_DFP_accel		XCHAL_HAVE_DFP_ACCEL	/* for backward compatibility */
-
-#define XCHAL_HAVE_DFPU_SINGLE_ONLY	0	/* DFPU Coprocessor, single precision only */
-#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE	0	/* DFPU Coprocessor, single and double precision */
-#define XCHAL_HAVE_VECTRA1		0	/* Vectra I  pkg */
-#define XCHAL_HAVE_VECTRALX		0	/* Vectra LX pkg */
-
-#define XCHAL_HAVE_FUSIONG		0    /* FusionG */
-#define XCHAL_HAVE_FUSIONG3		0    /* FusionG3 */
-#define XCHAL_HAVE_FUSIONG6		0    /* FusionG6 */
-#define XCHAL_HAVE_FUSIONG_SP_VFPU	0    /* sp_vfpu option on FusionG */
-#define XCHAL_HAVE_FUSIONG_DP_VFPU	0    /* dp_vfpu option on FusionG */
-#define XCHAL_FUSIONG_SIMD32		0    /* simd32 for FusionG */
-
-#define XCHAL_HAVE_FUSIONJ		0    /* FusionJ */
-#define XCHAL_HAVE_FUSIONJ6		0    /* FusionJ6 */
-#define XCHAL_HAVE_FUSIONJ_SP_VFPU	0    /* sp_vfpu option on FusionJ */
-#define XCHAL_HAVE_FUSIONJ_DP_VFPU	0    /* dp_vfpu option on FusionJ */
-#define XCHAL_FUSIONJ_SIMD32		0    /* simd32 for FusionJ */
-
-#define XCHAL_HAVE_PDX			0    /* PDX-LX */
-#define XCHAL_PDX_SIMD32		0    /* simd32 for PDX */
-#define XCHAL_HAVE_PDX4			0    /* PDX4-LX */
-#define XCHAL_HAVE_PDX8			0    /* PDX8-LX */
-#define XCHAL_HAVE_PDX16		0    /* PDX16-LX */
-#define XCHAL_HAVE_PDXNX 		0    /* PDX-NX */
-
-#define XCHAL_HAVE_CONNXD2		0	/* ConnX D2 pkg */
-#define XCHAL_HAVE_CONNXD2_DUALLSFLIX   0	/* ConnX D2 & Dual LoadStore Flix */
-#define XCHAL_HAVE_BALL			0
-#define XCHAL_HAVE_BALLAP		0
-#define XCHAL_HAVE_BBE16		0	/* ConnX BBE16 pkg */
-#define XCHAL_HAVE_BBE16_RSQRT		0	/* BBE16 & vector recip sqrt */
-#define XCHAL_HAVE_BBE16_VECDIV		0	/* BBE16 & vector divide */
-#define XCHAL_HAVE_BBE16_DESPREAD	0	/* BBE16 & despread */
-#define XCHAL_HAVE_CONNX_B10            0    /* ConnX B10 pkg*/
-#define XCHAL_HAVE_CONNX_B20            0    /* ConnX B20 pkg*/
-#define XCHAL_HAVE_CONNX_B_SP_VFPU      0    /* Single-precision Vector Floating-point option on ConnX B10 & B20 */
-#define XCHAL_HAVE_CONNX_B_SPX_VFPU     0    /* Single-precision Extended Vector Floating-point option on ConnX B10 & B20 */
-#define XCHAL_HAVE_CONNX_B_HPX_VFPU     0    /* Half-precision Extended Vector Floating-point option on ConnX B10 & B20 */
-#define XCHAL_HAVE_CONNX_B_32B_MAC      0    /* 32-bit vector MAC (real and complex), FIR & FFT option on ConnX B10 & B20 */
-#define XCHAL_HAVE_CONNX_B_VITERBI      0    /* Viterbi option on ConnX B10 & B20 */
-#define XCHAL_HAVE_CONNX_B_TURBO        0    /* Turbo option on ConnX B10 & B20 */
-#define XCHAL_HAVE_BBENEP		0	/* ConnX BBENEP pkgs */
-#define XCHAL_HAVE_BBENEP_SP_VFPU	0       /* sp_vfpu option on BBE-EP */
-#define XCHAL_HAVE_BSP3			0	/* ConnX BSP3 pkg */
-#define XCHAL_HAVE_BSP3_TRANSPOSE	0	/* BSP3 & transpose32x32 */
-#define XCHAL_HAVE_SSP16		0	/* ConnX SSP16 pkg */
-#define XCHAL_HAVE_SSP16_VITERBI	0	/* SSP16 & viterbi */
-#define XCHAL_HAVE_TURBO16		0	/* ConnX Turbo16 pkg */
-#define XCHAL_HAVE_BBP16		0	/* ConnX BBP16 pkg */
-#define XCHAL_HAVE_FLIX3		0	/* basic 3-way FLIX option */
-#define XCHAL_HAVE_GRIVPEP		0	/* General Release of IVPEP */
-#define XCHAL_HAVE_GRIVPEP_HISTOGRAM	0       /* Histogram option on GRIVPEP */
-
-#define XCHAL_HAVE_VISION	        0     /* Vision P5/P6 */
-#define XCHAL_VISION_SIMD16             0     /* simd16 for Vision P5/P6 */
-#define XCHAL_VISION_TYPE               0     /* Vision P5, P6, Q6 or Q7 */
-#define XCHAL_VISION_QUAD_MAC_TYPE      0     /* quad_mac option on Vision P6 */
-#define XCHAL_HAVE_VISION_HISTOGRAM     0     /* histogram option on Vision P5/P6 */
-#define XCHAL_HAVE_VISION_SP_VFPU       0     /* sp_vfpu option on Vision P5/P6/Q6/Q7 */
-#define XCHAL_HAVE_VISION_SP_VFPU_2XFMAC 0     /* sp_vfpu_2xfma option on Vision Q7 */
-#define XCHAL_HAVE_VISION_HP_VFPU       0     /* hp_vfpu option on Vision P6/Q6 */
-#define XCHAL_HAVE_VISION_HP_VFPU_2XFMAC 0     /* hp_vfpu_2xfma option on Vision Q7 */
-
-#define XCHAL_HAVE_VISIONC	        0     /* Vision C */
-
-#define XCHAL_HAVE_XNNE			0		/* XNNE */
-
-/*----------------------------------------------------------------------
-				MISC
-  ----------------------------------------------------------------------*/
-
-#define XCHAL_NUM_LOADSTORE_UNITS	2	/* load/store units */
-#define XCHAL_NUM_WRITEBUFFER_ENTRIES	32	/* size of write buffer */
-#define XCHAL_INST_FETCH_WIDTH		8	/* instr-fetch width in bytes */
-#define XCHAL_DATA_WIDTH		8	/* data width in bytes */
-#define XCHAL_DATA_PIPE_DELAY		2	/* d-side pipeline delay
-						   (1 = 5-stage, 2 = 7-stage) */
-#define XCHAL_CLOCK_GATING_GLOBAL	1	/* global clock gating */
-#define XCHAL_CLOCK_GATING_FUNCUNIT	1	/* funct. unit clock gating */
-/*  In T1050, applies to selected core load and store instructions (see ISA): */
-#define XCHAL_UNALIGNED_LOAD_EXCEPTION	1	/* unaligned loads cause exc. */
-#define XCHAL_UNALIGNED_STORE_EXCEPTION	1	/* unaligned stores cause exc.*/
-#define XCHAL_UNALIGNED_LOAD_HW		0	/* unaligned loads work in hw */
-#define XCHAL_UNALIGNED_STORE_HW	0	/* unaligned stores work in hw*/
-
-#define XCHAL_UNIFIED_LOADSTORE         0
-
-#define XCHAL_SW_VERSION		1401000	/* sw version of this header */
-#define XCHAL_SW_MINOR_VERSION		1401000	/* same, with zeroed micro and patch */
-#define XCHAL_SW_MICRO_VERSION		1401000	/* same, with zeroed patch */
-
-#define XCHAL_CORE_ID			"ACP_5_0_001_PROD"	/* alphanum core name
-						   (CoreID) set in the Xtensa
-						   Processor Generator */
-
-#define XCHAL_BUILD_UNIQUE_ID		0x0008176C	/* 22-bit sw build ID */
-
-/*
- *  These definitions describe the hardware targeted by this software.
- */
-#define XCHAL_HW_CONFIGID0		0xC2F3CBFE	/* ConfigID hi 32 bits*/
-#define XCHAL_HW_CONFIGID1		0x22481571	/* ConfigID lo 32 bits*/
-#define XCHAL_HW_VERSION_NAME		"LX7.0.9"	/* full version name */
-#define XCHAL_HW_VERSION_MAJOR		2700	/* major ver# of targeted hw */
-#define XCHAL_HW_VERSION_MINOR		9	/* minor ver# of targeted hw */
-#define XCHAL_HW_VERSION_MICRO			/* subdot ver# of targeted hw */
-#define XCHAL_HW_VERSION		270009	/* major*100+(major<2810 ? minor : minor*10+micro) */
-#define XCHAL_HW_REL_LX7		1
-#define XCHAL_HW_REL_LX7_0		1
-#define XCHAL_HW_REL_LX7_0_9		1
-#define XCHAL_HW_CONFIGID_RELIABLE	1
-/*  If software targets a *range* of hardware versions, these are the bounds: */
-#define XCHAL_HW_MIN_VERSION_MAJOR	2700	/* major v of earliest tgt hw */
-#define XCHAL_HW_MIN_VERSION_MINOR	9	/* minor v of earliest tgt hw */
-#define XCHAL_HW_MIN_VERSION_MICRO	0	/* micro v of earliest tgt hw */
-#define XCHAL_HW_MIN_VERSION		270009	/* earliest targeted hw */
-#define XCHAL_HW_MAX_VERSION_MAJOR	2700	/* major v of latest tgt hw */
-#define XCHAL_HW_MAX_VERSION_MINOR	9	/* minor v of latest tgt hw */
-#define XCHAL_HW_MAX_VERSION_MICRO		/* micro v of latest tgt hw */
-#define XCHAL_HW_MAX_VERSION		270009	/* latest targeted hw */
-
-/*  Config is enabled for functional safety: */
-#define XCHAL_HAVE_FUNC_SAFETY		0
-
-#define XCHAL_HAVE_APB			0 
-
-/*----------------------------------------------------------------------
-				CACHE
-  ----------------------------------------------------------------------*/
-
-#define XCHAL_ICACHE_LINESIZE		64	/* I-cache line size in bytes */
-#define XCHAL_DCACHE_LINESIZE		64	/* D-cache line size in bytes */
-#define XCHAL_ICACHE_LINEWIDTH		6	/* log2(I line size in bytes) */
-#define XCHAL_DCACHE_LINEWIDTH		6	/* log2(D line size in bytes) */
-
-#define XCHAL_ICACHE_SIZE		131072	/* I-cache size in bytes or 0 */
-#define XCHAL_ICACHE_SIZE_LOG2		17
-#define XCHAL_DCACHE_SIZE		131072	/* D-cache size in bytes or 0 */
-#define XCHAL_DCACHE_SIZE_LOG2		17
-
-#define XCHAL_DCACHE_IS_WRITEBACK	1	/* writeback feature */
-#define XCHAL_DCACHE_IS_COHERENT	0	/* MP coherence feature */
-
-#define XCHAL_HAVE_PREFETCH		1	/* PREFCTL register */
-#define XCHAL_HAVE_PREFETCH_L1		1	/* prefetch to L1 cache */
-#define XCHAL_PREFETCH_CASTOUT_LINES	1	/* dcache pref. castout bufsz */
-#define XCHAL_PREFETCH_ENTRIES		8	/* cache prefetch entries */
-#define XCHAL_PREFETCH_BLOCK_ENTRIES	0	/* prefetch block streams */
-#define XCHAL_HAVE_CACHE_BLOCKOPS	0	/* block prefetch for caches */
-#define XCHAL_HAVE_CME_DOWNGRADES	0
-#define XCHAL_HAVE_ICACHE_TEST		1	/* Icache test instructions */
-#define XCHAL_HAVE_DCACHE_TEST		1	/* Dcache test instructions */
-#define XCHAL_HAVE_ICACHE_DYN_WAYS	1	/* Icache dynamic way support */
-#define XCHAL_HAVE_DCACHE_DYN_WAYS	1	/* Dcache dynamic way support */
-#define XCHAL_HAVE_ICACHE_DYN_ENABLE	1	/* Icache enabled via MEMCTL */
-#define XCHAL_HAVE_DCACHE_DYN_ENABLE	1	/* Dcache enabled via MEMCTL */
-
-#define XCHAL_L1SCACHE_SIZE		         0
-#define XCHAL_L1SCACHE_SIZE_LOG2		 0
-#define XCHAL_L1SCACHE_WAYS              1
-#define XCHAL_L1SCACHE_WAYS_LOG2         0
-#define XCHAL_L1SCACHE_ACCESS_SIZE       0
-#define XCHAL_L1SCACHE_BANKS             1
-
-#define XCHAL_HAVE_L2			0	/* NX L2 cache controller */
-
-/*  This one is a form of caching, though not architecturally visible:  */
-#define XCHAL_HAVE_BRANCH_PREDICTION	0	/* branch [target] prediction */
-
-
-
-
-/****************************************************************************
-    Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
- ****************************************************************************/
-
-
-#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
-
-/*----------------------------------------------------------------------
-				CACHE
-  ----------------------------------------------------------------------*/
-
-#define XCHAL_HAVE_PIF			1	/* any outbound bus present */
-
-#define XCHAL_HAVE_AXI			1	/* AXI bus */
-#define XCHAL_HAVE_AXI_ECC		1	/* ECC on AXI bus */
-#define XCHAL_HAVE_ACELITE		0	/* ACELite bus */
-
-#define XCHAL_HAVE_PIF_WR_RESP			1	/* pif write response */
-#define XCHAL_HAVE_PIF_REQ_ATTR			0	/* pif attribute */
-
-/*  If present, cache size in bytes == (ways * 2^(linewidth + setwidth)).  */
-
-/*  Number of cache sets in log2(lines per way):  */
-#define XCHAL_ICACHE_SETWIDTH		9
-#define XCHAL_DCACHE_SETWIDTH		9
-
-/*  Cache set associativity (number of ways):  */
-#define XCHAL_ICACHE_WAYS		4
-#define XCHAL_ICACHE_WAYS_LOG2		2
-#define XCHAL_DCACHE_WAYS		4
-#define XCHAL_DCACHE_WAYS_LOG2		2
-
-/*  Cache features:  */
-#define XCHAL_ICACHE_LINE_LOCKABLE	1
-#define XCHAL_DCACHE_LINE_LOCKABLE	1
-#define XCHAL_ICACHE_ECC_PARITY		0
-#define XCHAL_DCACHE_ECC_PARITY		0
-#define XCHAL_ICACHE_ECC_WIDTH		4
-#define XCHAL_DCACHE_ECC_WIDTH		1
-
-/*  Cache access size in bytes (affects operation of SICW instruction):  */
-#define XCHAL_ICACHE_ACCESS_SIZE	8
-#define XCHAL_DCACHE_ACCESS_SIZE	8
-
-#define XCHAL_DCACHE_BANKS		2	/* number of banks */
-
-/* The number of Cache lines associated with a single cache tag */
-#define XCHAL_DCACHE_LINES_PER_TAG_LOG2	0
-
-/*  Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits):  */
-#define XCHAL_CA_BITS			4
-
-
-/*----------------------------------------------------------------------
-			INTERNAL I/D RAM/ROMs and XLMI
-  ----------------------------------------------------------------------*/
-#define XCHAL_NUM_INSTROM		0	/* number of core instr. ROMs */
-#define XCHAL_NUM_INSTRAM		1	/* number of core instr. RAMs */
-#define XCHAL_NUM_DATAROM		0	/* number of core data ROMs */
-#define XCHAL_NUM_DATARAM		1	/* number of core data RAMs */
-#define XCHAL_NUM_URAM			0	/* number of core unified RAMs*/
-#define XCHAL_NUM_XLMI			0	/* number of core XLMI ports */
-#define	XCHAL_HAVE_IRAMCFG		0	/* IRAMxCFG register present */
-#define	XCHAL_HAVE_DRAMCFG		0	/* DRAMxCFG register present */
-
-/*  Instruction RAM 0:  */
-#define XCHAL_INSTRAM0_VADDR		0x20000000	/* virtual address */
-#define XCHAL_INSTRAM0_PADDR		0x20000000	/* physical address */
-#define XCHAL_INSTRAM0_SIZE		1048576	/* size in bytes */
-#define XCHAL_INSTRAM0_ECC_PARITY	0	/* ECC/parity type, 0=none */
-#define XCHAL_HAVE_INSTRAM0		1
-#define XCHAL_INSTRAM0_HAVE_IDMA	0	/* idma supported by this local memory */
-
-/*  Data RAM 0:  */
-#define XCHAL_DATARAM0_VADDR		0xE0000000	/* virtual address */
-#define XCHAL_DATARAM0_PADDR		0xE0000000	/* physical address */
-#define XCHAL_DATARAM0_SIZE		1048576	/* size in bytes */
-#define XCHAL_DATARAM0_ECC_PARITY	0	/* ECC/parity type, 0=none */
-#define XCHAL_DATARAM0_BANKS		2	/* number of banks */
-#define XCHAL_HAVE_DATARAM0		1
-#define XCHAL_DATARAM0_HAVE_IDMA	0	/* idma supported by this local memory */
-
-
-#define XCHAL_HAVE_IDMA			0
-
-
-#define XCHAL_HAVE_IMEM_LOADSTORE	1	/* can load/store to IROM/IRAM*/
-
-/*----------------------------------------------------------------------
-			INTERRUPTS and TIMERS
-  ----------------------------------------------------------------------*/
-
-#define XCHAL_HAVE_INTERRUPTS		1	/* interrupt option */
-#define XCHAL_HAVE_NMI			1	/* non-maskable interrupt */
-#define XCHAL_HAVE_CCOUNT		1	/* CCOUNT reg. (timer option) */
-#define XCHAL_NUM_TIMERS		2	/* number of CCOMPAREn regs */
-#define XCHAL_NUM_INTERRUPTS		9	/* number of interrupts */
-#define XCHAL_NUM_INTERRUPTS_LOG2	4	/* ceil(log2(NUM_INTERRUPTS)) */
-#define XCHAL_NUM_EXTINTERRUPTS		5	/* num of external interrupts */
-#define XCHAL_NUM_INTLEVELS		6	/* number of interrupt levels
-						   (not including level zero) */
-
-
-#define XCHAL_HAVE_HIGHPRI_INTERRUPTS	1   /* med/high-pri. interrupts */
-#define XCHAL_EXCM_LEVEL		5	/* level masked by PS.EXCM */
-	/* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
-
-/*  Masks of interrupts at each interrupt level:  */
-#define XCHAL_INTLEVEL1_MASK		0x00000103
-#define XCHAL_INTLEVEL2_MASK		0x00000004
-#define XCHAL_INTLEVEL3_MASK		0x00000008
-#define XCHAL_INTLEVEL4_MASK		0x00000010
-#define XCHAL_INTLEVEL5_MASK		0x00000060
-#define XCHAL_INTLEVEL6_MASK		0x00000000
-#define XCHAL_INTLEVEL7_MASK		0x00000080
-
-/*  Masks of interrupts at each range 1..n of interrupt levels:  */
-#define XCHAL_INTLEVEL1_ANDBELOW_MASK	0x00000103
-#define XCHAL_INTLEVEL2_ANDBELOW_MASK	0x00000107
-#define XCHAL_INTLEVEL3_ANDBELOW_MASK	0x0000010F
-#define XCHAL_INTLEVEL4_ANDBELOW_MASK	0x0000011F
-#define XCHAL_INTLEVEL5_ANDBELOW_MASK	0x0000017F
-#define XCHAL_INTLEVEL6_ANDBELOW_MASK	0x0000017F
-#define XCHAL_INTLEVEL7_ANDBELOW_MASK	0x000001FF
-
-/*  Level of each interrupt:  */
-#define XCHAL_INT0_LEVEL		1
-#define XCHAL_INT1_LEVEL		1
-#define XCHAL_INT2_LEVEL		2
-#define XCHAL_INT3_LEVEL		3
-#define XCHAL_INT4_LEVEL		4
-#define XCHAL_INT5_LEVEL		5
-#define XCHAL_INT6_LEVEL		5
-#define XCHAL_INT7_LEVEL		7
-#define XCHAL_INT8_LEVEL		1
-#define XCHAL_DEBUGLEVEL		6	/* debug interrupt level */
-#define XCHAL_HAVE_DEBUG_EXTERN_INT	1	/* OCD external db interrupt */
-#define XCHAL_NMILEVEL			7	/* NMI "level" (for use with
-						   EXCSAVE/EPS/EPC_n, RFI n) */
-
-/*  Type of each interrupt:  */
-#define XCHAL_INT0_TYPE 	XTHAL_INTTYPE_TIMER
-#define XCHAL_INT1_TYPE 	XTHAL_INTTYPE_SOFTWARE
-#define XCHAL_INT2_TYPE 	XTHAL_INTTYPE_WRITE_ERROR
-#define XCHAL_INT3_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT4_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT5_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT6_TYPE 	XTHAL_INTTYPE_TIMER
-#define XCHAL_INT7_TYPE 	XTHAL_INTTYPE_NMI
-#define XCHAL_INT8_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-
-/*  Masks of interrupts for each type of interrupt:  */
-#define XCHAL_INTTYPE_MASK_UNCONFIGURED	0xFFFFFE00
-#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL	0x00000138
-#define XCHAL_INTTYPE_MASK_EXTERN_EDGE	0x00000000
-#define XCHAL_INTTYPE_MASK_NMI		0x00000080
-#define XCHAL_INTTYPE_MASK_SOFTWARE	0x00000002
-#define XCHAL_INTTYPE_MASK_TIMER	0x00000041
-#define XCHAL_INTTYPE_MASK_WRITE_ERROR	0x00000004
-#define XCHAL_INTTYPE_MASK_DBG_REQUEST	0x00000000
-#define XCHAL_INTTYPE_MASK_BREAKIN	0x00000000
-#define XCHAL_INTTYPE_MASK_TRAX		0x00000000
-#define XCHAL_INTTYPE_MASK_PROFILING	0x00000000
-#define XCHAL_INTTYPE_MASK_IDMA_DONE	0x00000000
-#define XCHAL_INTTYPE_MASK_IDMA_ERR	0x00000000
-#define XCHAL_INTTYPE_MASK_GS_ERR	0x00000000
-#define XCHAL_INTTYPE_MASK_L2_ERR	0x00000000
-#define XCHAL_INTTYPE_MASK_L2_STATUS	0x00000000
-#define XCHAL_INTTYPE_MASK_COR_ECC_ERR	0x00000000
-
-/*  Interrupt numbers assigned to specific interrupt sources:  */
-#define XCHAL_TIMER0_INTERRUPT		0	/* CCOMPARE0 */
-#define XCHAL_TIMER1_INTERRUPT		6	/* CCOMPARE1 */
-#define XCHAL_TIMER2_INTERRUPT		XTHAL_TIMER_UNCONFIGURED
-#define XCHAL_TIMER3_INTERRUPT		XTHAL_TIMER_UNCONFIGURED
-#define XCHAL_NMI_INTERRUPT		7	/* non-maskable interrupt */
-#define XCHAL_WRITE_ERROR_INTERRUPT	2
-
-/*  Interrupt numbers for levels at which only one interrupt is configured:  */
-#define XCHAL_INTLEVEL2_NUM		2
-#define XCHAL_INTLEVEL3_NUM		3
-#define XCHAL_INTLEVEL4_NUM		4
-#define XCHAL_INTLEVEL7_NUM		7
-/*  (There are many interrupts each at level(s) 1, 5.)  */
-
-
-/*
- *  External interrupt mapping.
- *  These macros describe how Xtensa processor interrupt numbers
- *  (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
- *  map to external BInterrupt<n> pins, for those interrupts
- *  configured as external (level-triggered, edge-triggered, or NMI).
- *  See the Xtensa processor databook for more details.
- */
-
-/*  Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number:  */
-#define XCHAL_EXTINT0_NUM		3	/* (intlevel 3) */
-#define XCHAL_EXTINT1_NUM		4	/* (intlevel 4) */
-#define XCHAL_EXTINT2_NUM		5	/* (intlevel 5) */
-#define XCHAL_EXTINT3_NUM		7	/* (intlevel 7) */
-#define XCHAL_EXTINT4_NUM		8	/* (intlevel 1) */
-/*  EXTERNAL BInterrupt pin numbers mapped to each core interrupt number:  */
-#define XCHAL_INT3_EXTNUM		0	/* (intlevel 3) */
-#define XCHAL_INT4_EXTNUM		1	/* (intlevel 4) */
-#define XCHAL_INT5_EXTNUM		2	/* (intlevel 5) */
-#define XCHAL_INT7_EXTNUM		3	/* (intlevel 7) */
-#define XCHAL_INT8_EXTNUM		4	/* (intlevel 1) */
-
-#define	XCHAL_HAVE_ISB			0	/* No ISB */
-#define	XCHAL_ISB_VADDR			0	/* N/A    */
-#define	XCHAL_HAVE_ITB			0	/* No ITB */
-#define	XCHAL_ITB_VADDR			0	/* N/A    */
-
-#define	XCHAL_HAVE_KSL			0	/* Kernel Stack Limit */
-#define	XCHAL_HAVE_ISL			0	/* Interrupt Stack Limit */
-#define	XCHAL_HAVE_PSL			0	/* Pageable Stack Limit */
-
-
-/*----------------------------------------------------------------------
-			EXCEPTIONS and VECTORS
-  ----------------------------------------------------------------------*/
-
-#define XCHAL_XEA_VERSION		2	/* Xtensa Exception Architecture
-						   number: 1 == XEA1 (until T1050)
-							   2 == XEA2 (T1040 onwards)
-							   3 == XEA3 (LX8/NX/SX onwards)
-							   0 == XEAX (extern) or TX */
-#define XCHAL_HAVE_XEA1			0	/* Exception Architecture 1 */
-#define XCHAL_HAVE_XEA2			1	/* Exception Architecture 2 */
-#define XCHAL_HAVE_XEA3			0	/* Exception Architecture 3 */
-#define XCHAL_HAVE_XEAX			0	/* External Exception Arch. */
-#define XCHAL_HAVE_EXCEPTIONS		1	/* exception option */
-#define XCHAL_HAVE_IMPRECISE_EXCEPTIONS	0	/* imprecise exception option */
-#define	XCHAL_EXCCAUSE_NUM		64	/* Number of exceptions */
-#define XCHAL_HAVE_HALT			0	/* halt architecture option */
-#define XCHAL_HAVE_BOOTLOADER		0	/* boot loader (for TX) */
-#define XCHAL_HAVE_MEM_ECC_PARITY	0	/* local memory ECC/parity */
-#define XCHAL_HAVE_VECTOR_SELECT	0	/* relocatable vectors */
-#define XCHAL_HAVE_VECBASE		0	/* relocatable vectors */
-
-#define XCHAL_RESET_VECOFS		0x00000000
-#define XCHAL_RESET_VECTOR_VADDR	0x20000000
-#define XCHAL_RESET_VECTOR_PADDR	0x20000000
-#define XCHAL_USER_VECOFS		0x00000000
-#define XCHAL_USER_VECTOR_VADDR		0x20000740
-#define XCHAL_USER_VECTOR_PADDR		0x20000740
-#define XCHAL_KERNEL_VECOFS		0x00000000
-#define XCHAL_KERNEL_VECTOR_VADDR	0x20000700
-#define XCHAL_KERNEL_VECTOR_PADDR	0x20000700
-#define XCHAL_DOUBLEEXC_VECOFS		0x00000000
-#define XCHAL_DOUBLEEXC_VECTOR_VADDR	0x200007C0
-#define XCHAL_DOUBLEEXC_VECTOR_PADDR	0x200007C0
-#define XCHAL_WINDOW_OF4_VECOFS		0x00000000
-#define XCHAL_WINDOW_UF4_VECOFS		0x00000040
-#define XCHAL_WINDOW_OF8_VECOFS		0x00000080
-#define XCHAL_WINDOW_UF8_VECOFS		0x000000C0
-#define XCHAL_WINDOW_OF12_VECOFS	0x00000100
-#define XCHAL_WINDOW_UF12_VECOFS	0x00000140
-#define XCHAL_WINDOW_VECTORS_VADDR	0x20000400
-#define XCHAL_WINDOW_VECTORS_PADDR	0x20000400
-#define XCHAL_INTLEVEL2_VECOFS		0x00000000
-#define XCHAL_INTLEVEL2_VECTOR_VADDR	0x20000580
-#define XCHAL_INTLEVEL2_VECTOR_PADDR	0x20000580
-#define XCHAL_INTLEVEL3_VECOFS		0x00000000
-#define XCHAL_INTLEVEL3_VECTOR_VADDR	0x200005C0
-#define XCHAL_INTLEVEL3_VECTOR_PADDR	0x200005C0
-#define XCHAL_INTLEVEL4_VECOFS		0x00000000
-#define XCHAL_INTLEVEL4_VECTOR_VADDR	0x20000600
-#define XCHAL_INTLEVEL4_VECTOR_PADDR	0x20000600
-#define XCHAL_INTLEVEL5_VECOFS		0x00000000
-#define XCHAL_INTLEVEL5_VECTOR_VADDR	0x20000640
-#define XCHAL_INTLEVEL5_VECTOR_PADDR	0x20000640
-#define XCHAL_INTLEVEL6_VECOFS		0x00000000
-#define XCHAL_INTLEVEL6_VECTOR_VADDR	0x20000680
-#define XCHAL_INTLEVEL6_VECTOR_PADDR	0x20000680
-#define XCHAL_DEBUG_VECOFS		XCHAL_INTLEVEL6_VECOFS
-#define XCHAL_DEBUG_VECTOR_VADDR	XCHAL_INTLEVEL6_VECTOR_VADDR
-#define XCHAL_DEBUG_VECTOR_PADDR	XCHAL_INTLEVEL6_VECTOR_PADDR
-#define XCHAL_NMI_VECOFS		0x00000000
-#define XCHAL_NMI_VECTOR_VADDR		0x200006C0
-#define XCHAL_NMI_VECTOR_PADDR		0x200006C0
-#define XCHAL_INTLEVEL7_VECOFS		XCHAL_NMI_VECOFS
-#define XCHAL_INTLEVEL7_VECTOR_VADDR	XCHAL_NMI_VECTOR_VADDR
-#define XCHAL_INTLEVEL7_VECTOR_PADDR	XCHAL_NMI_VECTOR_PADDR
-
-
-/*----------------------------------------------------------------------
-				DEBUG MODULE
-  ----------------------------------------------------------------------*/
-
-/*  Misc  */
-#define XCHAL_HAVE_DEBUG_ERI		0	/* ERI to debug module */
-#define XCHAL_HAVE_DEBUG_APB		0	/* APB to debug module */
-#define XCHAL_HAVE_DEBUG_JTAG		1	/* JTAG to debug module */
-
-/*  On-Chip Debug (OCD)  */
-#define XCHAL_HAVE_OCD			1	/* OnChipDebug option */
-#define XCHAL_NUM_IBREAK		2	/* number of IBREAKn regs */
-#define XCHAL_NUM_DBREAK		2	/* number of DBREAKn regs */
-#define XCHAL_HAVE_OCD_DIR_ARRAY	0	/* faster OCD option (to LX4) */
-#define XCHAL_HAVE_OCD_LS32DDR		1	/* L32DDR/S32DDR (faster OCD) */
-
-/*  TRAX (in core)  */
-#define XCHAL_HAVE_TRAX			0	/* TRAX in debug module */
-#define XCHAL_TRAX_MEM_SIZE		0	/* TRAX memory size in bytes */
-#define XCHAL_TRAX_MEM_SHAREABLE	0	/* start/end regs; ready sig. */
-#define XCHAL_TRAX_ATB_WIDTH		0	/* ATB width (bits), 0=no ATB */
-#define XCHAL_TRAX_TIME_WIDTH		0	/* timestamp bitwidth, 0=none */
-
-/*  Perf counters  */
-#define XCHAL_NUM_PERF_COUNTERS		0	/* performance counters */
-
-
-/*----------------------------------------------------------------------
-				MMU
-  ----------------------------------------------------------------------*/
-
-/*  See core-matmap.h header file for more details.  */
-
-#define XCHAL_HAVE_TLBS			1	/* inverse of HAVE_CACHEATTR */
-#define XCHAL_HAVE_SPANNING_WAY		1	/* one way maps I+D 4GB vaddr */
-#define XCHAL_SPANNING_WAY		0	/* TLB spanning way number */
-#define XCHAL_HAVE_IDENTITY_MAP		1	/* vaddr == paddr always */
-#define XCHAL_HAVE_CACHEATTR		0	/* CACHEATTR register present */
-#define XCHAL_HAVE_MIMIC_CACHEATTR	1	/* region protection */
-#define XCHAL_HAVE_XLT_CACHEATTR	0	/* region prot. w/translation */
-#define XCHAL_HAVE_PTP_MMU		0	/* full MMU (with page table
-						   [autorefill] and protection)
-						   usable for an MMU-based OS */
-
-/*  If none of the above last 5 are set, it's a custom TLB configuration.  */
-
-#define XCHAL_MMU_ASID_BITS		0	/* number of bits in ASIDs */
-#define XCHAL_MMU_RINGS			1	/* number of rings (1..4) */
-#define XCHAL_MMU_RING_BITS		0	/* num of bits in RING field */
-
-/*----------------------------------------------------------------------
-				MPU
-  ----------------------------------------------------------------------*/
-#define XCHAL_HAVE_MPU			0 
-#define XCHAL_MPU_ENTRIES		0
-
-#define XCHAL_MPU_ALIGN_REQ		1	/* MPU requires alignment of entries to background map */
-#define XCHAL_MPU_BACKGROUND_ENTRIES	0	/* number of entries in bg map*/
-#define XCHAL_MPU_BG_CACHEADRDIS	0	/* default CACHEADRDIS for bg */
- 
-#define XCHAL_MPU_ALIGN_BITS		0
-#define XCHAL_MPU_ALIGN			0
-
-#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
-
-
-#endif /* _XTENSA_CORE_CONFIGURATION_H */
-
diff --git a/src/platform/amd/vangogh/include/arch/xtensa/config/core-matmap.h b/src/platform/amd/vangogh/include/arch/xtensa/config/core-matmap.h
deleted file mode 100644
index 711f34d9af39..000000000000
--- a/src/platform/amd/vangogh/include/arch/xtensa/config/core-matmap.h
+++ /dev/null
@@ -1,317 +0,0 @@
-/* 
- * xtensa/config/core-matmap.h -- Memory access and translation mapping
- *	parameters (CHAL) of the Xtensa processor core configuration.
- *
- *  If you are using Xtensa Tools, see <xtensa/config/core.h> (which includes
- *  this file) for more details.
- *
- *  In the Xtensa processor products released to date, all parameters
- *  defined in this file are derivable (at least in theory) from
- *  information contained in the core-isa.h header file.
- *  In particular, the following core configuration parameters are relevant:
- *	XCHAL_HAVE_CACHEATTR
- *	XCHAL_HAVE_MIMIC_CACHEATTR
- *	XCHAL_HAVE_XLT_CACHEATTR
- *	XCHAL_HAVE_PTP_MMU
- *	XCHAL_ITLB_ARF_ENTRIES_LOG2
- *	XCHAL_DTLB_ARF_ENTRIES_LOG2
- *	XCHAL_DCACHE_IS_WRITEBACK
- *	XCHAL_ICACHE_SIZE		(presence of I-cache)
- *	XCHAL_DCACHE_SIZE		(presence of D-cache)
- *	XCHAL_HW_VERSION_MAJOR
- *	XCHAL_HW_VERSION_MINOR
- */
-
-/* Customer ID=7490; Build=0x8176c; Copyright (c) 1999-2019 Tensilica Inc.
-
-   Permission is hereby granted, free of charge, to any person obtaining
-   a copy of this software and associated documentation files (the
-   "Software"), to deal in the Software without restriction, including
-   without limitation the rights to use, copy, modify, merge, publish,
-   distribute, sublicense, and/or sell copies of the Software, and to
-   permit persons to whom the Software is furnished to do so, subject to
-   the following conditions:
-
-   The above copyright notice and this permission notice shall be included
-   in all copies or substantial portions of the Software.
-
-   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
-
-
-#ifndef XTENSA_CONFIG_CORE_MATMAP_H
-#define XTENSA_CONFIG_CORE_MATMAP_H
-
-
-/*----------------------------------------------------------------------
-			CACHE (MEMORY ACCESS) ATTRIBUTES
-  ----------------------------------------------------------------------*/
-
-
-
-/*  Cache Attribute encodings -- lists of access modes for each cache attribute:  */
-#define XCHAL_FCA_LIST		XTHAL_FAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_FAM_CACHED	XCHAL_SEP \
-				XTHAL_FAM_BYPASS	XCHAL_SEP \
-				XTHAL_FAM_CACHED	XCHAL_SEP \
-				XTHAL_FAM_CACHED	XCHAL_SEP \
-				XTHAL_FAM_CACHED	XCHAL_SEP \
-				XTHAL_FAM_BYPASS	XCHAL_SEP \
-				XTHAL_FAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_FAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_FAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_FAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_FAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_FAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_FAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_FAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_FAM_EXCEPTION
-#define XCHAL_LCA_LIST		XTHAL_LAM_CACHED_NOALLOC	XCHAL_SEP \
-				XTHAL_LAM_CACHED	XCHAL_SEP \
-				XTHAL_LAM_BYPASSG	XCHAL_SEP \
-				XTHAL_LAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_LAM_CACHED	XCHAL_SEP \
-				XTHAL_LAM_CACHED	XCHAL_SEP \
-				XTHAL_LAM_BYPASSG	XCHAL_SEP \
-				XTHAL_LAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_LAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_LAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_LAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_LAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_LAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_LAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_LAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_LAM_EXCEPTION
-#define XCHAL_SCA_LIST		XTHAL_SAM_WRITETHRU	XCHAL_SEP \
-				XTHAL_SAM_WRITETHRU	XCHAL_SEP \
-				XTHAL_SAM_BYPASS	XCHAL_SEP \
-				XTHAL_SAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_SAM_WRITEBACK	XCHAL_SEP \
-				XTHAL_SAM_WRITEBACK_NOALLOC	XCHAL_SEP \
-				XTHAL_SAM_BYPASS	XCHAL_SEP \
-				XTHAL_SAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_SAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_SAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_SAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_SAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_SAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_SAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_SAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_SAM_EXCEPTION
-
-#define XCHAL_CA_R   (0xC0 | 0x40000000)
-#define XCHAL_CA_RX  (0xD0 | 0x40000000)
-#define XCHAL_CA_RW  (0xE0 | 0x40000000)
-#define XCHAL_CA_RWX (0xF0 | 0x40000000)
-
-/*
- *  Specific encoded cache attribute values of general interest.
- *  If a specific cache mode is not available, the closest available
- *  one is returned instead (eg. writethru instead of writeback,
- *  bypass instead of writethru).
- */
-#define XCHAL_CA_BYPASS  		2	/* cache disabled (bypassed) mode */
-#define XCHAL_CA_BYPASSBUF  		6	/* cache disabled (bypassed) bufferable mode */
-#define XCHAL_CA_WRITETHRU		1	/* cache enabled (write-through) mode */
-#define XCHAL_CA_WRITEBACK		4	/* cache enabled (write-back) mode */
-#define XCHAL_HAVE_CA_WRITEBACK_NOALLOC	1	/* write-back no-allocate availability */
-#define XCHAL_CA_WRITEBACK_NOALLOC	5	/* cache enabled (write-back no-allocate) mode */
-#define XCHAL_CA_ILLEGAL		15	/* no access allowed (all cause exceptions) mode */
-
-/*----------------------------------------------------------------------
-				MMU
-  ----------------------------------------------------------------------*/
-
-/*
- *  General notes on MMU parameters.
- *
- *  Terminology:
- *	ASID = address-space ID (acts as an "extension" of virtual addresses)
- *	VPN  = virtual page number
- *	PPN  = physical page number
- *	CA   = encoded cache attribute (access modes)
- *	TLB  = translation look-aside buffer (term is stretched somewhat here)
- *	I    = instruction (fetch accesses)
- *	D    = data (load and store accesses)
- *	way  = each TLB (ITLB and DTLB) consists of a number of "ways"
- *		that simultaneously match the virtual address of an access;
- *		a TLB successfully translates a virtual address if exactly
- *		one way matches the vaddr; if none match, it is a miss;
- *		if multiple match, one gets a "multihit" exception;
- *		each way can be independently configured in terms of number of
- *		entries, page sizes, which fields are writable or constant, etc.
- *	set  = group of contiguous ways with exactly identical parameters
- *	ARF  = auto-refill; hardware services a 1st-level miss by loading a PTE
- *		from the page table and storing it in one of the auto-refill ways;
- *		if this PTE load also misses, a miss exception is posted for s/w.
- *	min-wired = a "min-wired" way can be used to map a single (minimum-sized)
- * 		page arbitrarily under program control; it has a single entry,
- *		is non-auto-refill (some other way(s) must be auto-refill),
- *		all its fields (VPN, PPN, ASID, CA) are all writable, and it
- *		supports the XCHAL_MMU_MIN_PTE_PAGE_SIZE page size (a current
- *		restriction is that this be the only page size it supports).
- *
- *  TLB way entries are virtually indexed.
- *  TLB ways that support multiple page sizes:
- *	- must have all writable VPN and PPN fields;
- *	- can only use one page size at any given time (eg. setup at startup),
- *	  selected by the respective ITLBCFG or DTLBCFG special register,
- *	  whose bits n*4+3 .. n*4 index the list of page sizes for way n
- *	  (XCHAL_xTLB_SETm_PAGESZ_LOG2_LIST for set m corresponding to way n);
- *	  this list may be sparse for auto-refill ways because auto-refill
- *	  ways have independent lists of supported page sizes sharing a
- *	  common encoding with PTE entries; the encoding is the index into
- *	  this list; unsupported sizes for a given way are zero in the list;
- *	  selecting unsupported sizes results in undefine hardware behaviour;
- *	- is only possible for ways 0 thru 7 (due to ITLBCFG/DTLBCFG definition).
- */
-
-#define XCHAL_MMU_ASID_INVALID		0	/* ASID value indicating invalid address space */
-#define XCHAL_MMU_ASID_KERNEL		0	/* ASID value indicating kernel (ring 0) address space */
-#define XCHAL_MMU_SR_BITS		0	/* number of size-restriction bits supported */
-#define XCHAL_MMU_CA_BITS		4	 /* number of bits needed to hold cache attribute encoding */
-#define XCHAL_MMU_MAX_PTE_PAGE_SIZE	29	/* max page size in a PTE structure (log2) */
-#define XCHAL_MMU_MIN_PTE_PAGE_SIZE	29	/* min page size in a PTE structure (log2) */
-
-
-/***  Instruction TLB:  ***/
-
-#define XCHAL_ITLB_WAY_BITS		0	/* number of bits holding the ways */
-#define XCHAL_ITLB_WAYS			1	/* number of ways (n-way set-associative TLB) */
-#define XCHAL_ITLB_ARF_WAYS		0	/* number of auto-refill ways */
-#define XCHAL_ITLB_SETS			1	/* number of sets (groups of ways with identical settings) */
-
-/*  Way set to which each way belongs:  */
-#define XCHAL_ITLB_WAY0_SET		0
-
-/*  Ways sets that are used by hardware auto-refill (ARF):  */
-#define XCHAL_ITLB_ARF_SETS		0	/* number of auto-refill sets */
-
-/*  Way sets that are "min-wired" (see terminology comment above):  */
-#define XCHAL_ITLB_MINWIRED_SETS	0	/* number of "min-wired" sets */
-
-
-/*  ITLB way set 0 (group of ways 0 thru 0):  */
-#define XCHAL_ITLB_SET0_WAY			0	/* index of first way in this way set */
-#define XCHAL_ITLB_SET0_WAYS			1	/* number of (contiguous) ways in this way set */
-#define XCHAL_ITLB_SET0_ENTRIES_LOG2		3	/* log2(number of entries in this way) */
-#define XCHAL_ITLB_SET0_ENTRIES			8	/* number of entries in this way (always a power of 2) */
-#define XCHAL_ITLB_SET0_ARF			0	/* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
-#define XCHAL_ITLB_SET0_PAGESIZES		1	/* number of supported page sizes in this way */
-#define XCHAL_ITLB_SET0_PAGESZ_BITS		0	/* number of bits to encode the page size */
-#define XCHAL_ITLB_SET0_PAGESZ_LOG2_MIN		29	/* log2(minimum supported page size) */
-#define XCHAL_ITLB_SET0_PAGESZ_LOG2_MAX		29	/* log2(maximum supported page size) */
-#define XCHAL_ITLB_SET0_PAGESZ_LOG2_LIST	29	/* list of log2(page size)s, separated by XCHAL_SEP;
-							   2^PAGESZ_BITS entries in list, unsupported entries are zero */
-#define XCHAL_ITLB_SET0_ASID_CONSTMASK		0	/* constant ASID bits; 0 if all writable */
-#define XCHAL_ITLB_SET0_VPN_CONSTMASK		0x00000000	/* constant VPN bits, not including entry index bits; 0 if all writable */
-#define XCHAL_ITLB_SET0_PPN_CONSTMASK		0xE0000000	/* constant PPN bits, including entry index bits; 0 if all writable */
-#define XCHAL_ITLB_SET0_CA_CONSTMASK		0	/* constant CA bits; 0 if all writable */
-#define XCHAL_ITLB_SET0_ASID_RESET		0	/* 1 if ASID reset values defined (and all writable); 0 otherwise */
-#define XCHAL_ITLB_SET0_VPN_RESET		0	/* 1 if VPN reset values defined (and all writable); 0 otherwise */
-#define XCHAL_ITLB_SET0_PPN_RESET		0	/* 1 if PPN reset values defined (and all writable); 0 otherwise */
-#define XCHAL_ITLB_SET0_CA_RESET		1	/* 1 if CA reset values defined (and all writable); 0 otherwise */
-/*  Constant VPN values for each entry of ITLB way set 0 (because VPN_CONSTMASK is non-zero):  */
-#define XCHAL_ITLB_SET0_E0_VPN_CONST		0x00000000
-#define XCHAL_ITLB_SET0_E1_VPN_CONST		0x20000000
-#define XCHAL_ITLB_SET0_E2_VPN_CONST		0x40000000
-#define XCHAL_ITLB_SET0_E3_VPN_CONST		0x60000000
-#define XCHAL_ITLB_SET0_E4_VPN_CONST		0x80000000
-#define XCHAL_ITLB_SET0_E5_VPN_CONST		0xA0000000
-#define XCHAL_ITLB_SET0_E6_VPN_CONST		0xC0000000
-#define XCHAL_ITLB_SET0_E7_VPN_CONST		0xE0000000
-/*  Constant PPN values for each entry of ITLB way set 0 (because PPN_CONSTMASK is non-zero):  */
-#define XCHAL_ITLB_SET0_E0_PPN_CONST		0x00000000
-#define XCHAL_ITLB_SET0_E1_PPN_CONST		0x20000000
-#define XCHAL_ITLB_SET0_E2_PPN_CONST		0x40000000
-#define XCHAL_ITLB_SET0_E3_PPN_CONST		0x60000000
-#define XCHAL_ITLB_SET0_E4_PPN_CONST		0x80000000
-#define XCHAL_ITLB_SET0_E5_PPN_CONST		0xA0000000
-#define XCHAL_ITLB_SET0_E6_PPN_CONST		0xC0000000
-#define XCHAL_ITLB_SET0_E7_PPN_CONST		0xE0000000
-/*  Reset CA values for each entry of ITLB way set 0 (because SET0_CA_RESET is non-zero):  */
-#define XCHAL_ITLB_SET0_E0_CA_RESET		0x02
-#define XCHAL_ITLB_SET0_E1_CA_RESET		0x02
-#define XCHAL_ITLB_SET0_E2_CA_RESET		0x02
-#define XCHAL_ITLB_SET0_E3_CA_RESET		0x02
-#define XCHAL_ITLB_SET0_E4_CA_RESET		0x02
-#define XCHAL_ITLB_SET0_E5_CA_RESET		0x02
-#define XCHAL_ITLB_SET0_E6_CA_RESET		0x02
-#define XCHAL_ITLB_SET0_E7_CA_RESET		0x02
-
-
-/***  Data TLB:  ***/
-
-#define XCHAL_DTLB_WAY_BITS		0	/* number of bits holding the ways */
-#define XCHAL_DTLB_WAYS			1	/* number of ways (n-way set-associative TLB) */
-#define XCHAL_DTLB_ARF_WAYS		0	/* number of auto-refill ways */
-#define XCHAL_DTLB_SETS			1	/* number of sets (groups of ways with identical settings) */
-
-/*  Way set to which each way belongs:  */
-#define XCHAL_DTLB_WAY0_SET		0
-
-/*  Ways sets that are used by hardware auto-refill (ARF):  */
-#define XCHAL_DTLB_ARF_SETS		0	/* number of auto-refill sets */
-
-/*  Way sets that are "min-wired" (see terminology comment above):  */
-#define XCHAL_DTLB_MINWIRED_SETS	0	/* number of "min-wired" sets */
-
-
-/*  DTLB way set 0 (group of ways 0 thru 0):  */
-#define XCHAL_DTLB_SET0_WAY			0	/* index of first way in this way set */
-#define XCHAL_DTLB_SET0_WAYS			1	/* number of (contiguous) ways in this way set */
-#define XCHAL_DTLB_SET0_ENTRIES_LOG2		3	/* log2(number of entries in this way) */
-#define XCHAL_DTLB_SET0_ENTRIES			8	/* number of entries in this way (always a power of 2) */
-#define XCHAL_DTLB_SET0_ARF			0	/* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
-#define XCHAL_DTLB_SET0_PAGESIZES		1	/* number of supported page sizes in this way */
-#define XCHAL_DTLB_SET0_PAGESZ_BITS		0	/* number of bits to encode the page size */
-#define XCHAL_DTLB_SET0_PAGESZ_LOG2_MIN		29	/* log2(minimum supported page size) */
-#define XCHAL_DTLB_SET0_PAGESZ_LOG2_MAX		29	/* log2(maximum supported page size) */
-#define XCHAL_DTLB_SET0_PAGESZ_LOG2_LIST	29	/* list of log2(page size)s, separated by XCHAL_SEP;
-							   2^PAGESZ_BITS entries in list, unsupported entries are zero */
-#define XCHAL_DTLB_SET0_ASID_CONSTMASK		0	/* constant ASID bits; 0 if all writable */
-#define XCHAL_DTLB_SET0_VPN_CONSTMASK		0x00000000	/* constant VPN bits, not including entry index bits; 0 if all writable */
-#define XCHAL_DTLB_SET0_PPN_CONSTMASK		0xE0000000	/* constant PPN bits, including entry index bits; 0 if all writable */
-#define XCHAL_DTLB_SET0_CA_CONSTMASK		0	/* constant CA bits; 0 if all writable */
-#define XCHAL_DTLB_SET0_ASID_RESET		0	/* 1 if ASID reset values defined (and all writable); 0 otherwise */
-#define XCHAL_DTLB_SET0_VPN_RESET		0	/* 1 if VPN reset values defined (and all writable); 0 otherwise */
-#define XCHAL_DTLB_SET0_PPN_RESET		0	/* 1 if PPN reset values defined (and all writable); 0 otherwise */
-#define XCHAL_DTLB_SET0_CA_RESET		1	/* 1 if CA reset values defined (and all writable); 0 otherwise */
-/*  Constant VPN values for each entry of DTLB way set 0 (because VPN_CONSTMASK is non-zero):  */
-#define XCHAL_DTLB_SET0_E0_VPN_CONST		0x00000000
-#define XCHAL_DTLB_SET0_E1_VPN_CONST		0x20000000
-#define XCHAL_DTLB_SET0_E2_VPN_CONST		0x40000000
-#define XCHAL_DTLB_SET0_E3_VPN_CONST		0x60000000
-#define XCHAL_DTLB_SET0_E4_VPN_CONST		0x80000000
-#define XCHAL_DTLB_SET0_E5_VPN_CONST		0xA0000000
-#define XCHAL_DTLB_SET0_E6_VPN_CONST		0xC0000000
-#define XCHAL_DTLB_SET0_E7_VPN_CONST		0xE0000000
-/*  Constant PPN values for each entry of DTLB way set 0 (because PPN_CONSTMASK is non-zero):  */
-#define XCHAL_DTLB_SET0_E0_PPN_CONST		0x00000000
-#define XCHAL_DTLB_SET0_E1_PPN_CONST		0x20000000
-#define XCHAL_DTLB_SET0_E2_PPN_CONST		0x40000000
-#define XCHAL_DTLB_SET0_E3_PPN_CONST		0x60000000
-#define XCHAL_DTLB_SET0_E4_PPN_CONST		0x80000000
-#define XCHAL_DTLB_SET0_E5_PPN_CONST		0xA0000000
-#define XCHAL_DTLB_SET0_E6_PPN_CONST		0xC0000000
-#define XCHAL_DTLB_SET0_E7_PPN_CONST		0xE0000000
-/*  Reset CA values for each entry of DTLB way set 0 (because SET0_CA_RESET is non-zero):  */
-#define XCHAL_DTLB_SET0_E0_CA_RESET		0x02
-#define XCHAL_DTLB_SET0_E1_CA_RESET		0x02
-#define XCHAL_DTLB_SET0_E2_CA_RESET		0x02
-#define XCHAL_DTLB_SET0_E3_CA_RESET		0x02
-#define XCHAL_DTLB_SET0_E4_CA_RESET		0x02
-#define XCHAL_DTLB_SET0_E5_CA_RESET		0x02
-#define XCHAL_DTLB_SET0_E6_CA_RESET		0x02
-#define XCHAL_DTLB_SET0_E7_CA_RESET		0x02
-
-
-
-
-#endif /*XTENSA_CONFIG_CORE_MATMAP_H*/
-
diff --git a/src/platform/amd/vangogh/include/arch/xtensa/config/specreg.h b/src/platform/amd/vangogh/include/arch/xtensa/config/specreg.h
deleted file mode 100644
index ce2b5dc4d541..000000000000
--- a/src/platform/amd/vangogh/include/arch/xtensa/config/specreg.h
+++ /dev/null
@@ -1,108 +0,0 @@
-/*
- * Xtensa Special Register symbolic names
- */
-
-/* $Id: //depot/rel/Homewood/ib.1/Xtensa/SWConfig/hal/specreg.h.tpp#1 $ */
-
-/* Customer ID=7490; Build=0x8176c; Copyright (c) 1998-2002 Tensilica Inc.
-
-   Permission is hereby granted, free of charge, to any person obtaining
-   a copy of this software and associated documentation files (the
-   "Software"), to deal in the Software without restriction, including
-   without limitation the rights to use, copy, modify, merge, publish,
-   distribute, sublicense, and/or sell copies of the Software, and to
-   permit persons to whom the Software is furnished to do so, subject to
-   the following conditions:
-
-   The above copyright notice and this permission notice shall be included
-   in all copies or substantial portions of the Software.
-
-   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
-
-#ifndef XTENSA_SPECREG_H
-#define XTENSA_SPECREG_H
-
-/*  Include these special register bitfield definitions, for historical reasons:  */
-#include <xtensa/corebits.h>
-
-
-/*  Special registers:  */
-#define LBEG		0
-#define LEND		1
-#define LCOUNT		2
-#define SAR		3
-#define BR		4
-#define SCOMPARE1	12
-#define PREFCTL		40
-#define WINDOWBASE	72
-#define WINDOWSTART	73
-#define IBREAKENABLE	96
-#define MEMCTL		97
-#define ATOMCTL		99
-#define DDR		104
-#define IBREAKA_0	128
-#define IBREAKA_1	129
-#define DBREAKA_0	144
-#define DBREAKA_1	145
-#define DBREAKC_0	160
-#define DBREAKC_1	161
-#define EPC_1		177
-#define EPC_2		178
-#define EPC_3		179
-#define EPC_4		180
-#define EPC_5		181
-#define EPC_6		182
-#define EPC_7		183
-#define DEPC		192
-#define EPS_2		194
-#define EPS_3		195
-#define EPS_4		196
-#define EPS_5		197
-#define EPS_6		198
-#define EPS_7		199
-#define EXCSAVE_1	209
-#define EXCSAVE_2	210
-#define EXCSAVE_3	211
-#define EXCSAVE_4	212
-#define EXCSAVE_5	213
-#define EXCSAVE_6	214
-#define EXCSAVE_7	215
-#define CPENABLE	224
-#define INTERRUPT	226
-#define INTENABLE	228
-#define PS		230
-#define EXCCAUSE	232
-#define DEBUGCAUSE	233
-#define CCOUNT		234
-#define PRID		235
-#define ICOUNT		236
-#define ICOUNTLEVEL	237
-#define EXCVADDR	238
-#define CCOMPARE_0	240
-#define CCOMPARE_1	241
-#define MISC_REG_0	244
-#define MISC_REG_1	245
-
-
-/*  Special cases (bases of special register series):  */
-#define IBREAKA		128
-#define DBREAKA		144
-#define DBREAKC		160
-#define EPC		176
-#define EPS		192
-#define EXCSAVE		208
-#define CCOMPARE	240
-
-/*  Special names for read-only and write-only interrupt registers:  */
-#define INTREAD		226
-#define INTSET		226
-#define INTCLEAR	227
-
-#endif /* XTENSA_SPECREG_H */
-
diff --git a/src/platform/amd/vangogh/include/arch/xtensa/config/system.h b/src/platform/amd/vangogh/include/arch/xtensa/config/system.h
deleted file mode 100644
index cdc6537bfdc1..000000000000
--- a/src/platform/amd/vangogh/include/arch/xtensa/config/system.h
+++ /dev/null
@@ -1,256 +0,0 @@
-/* 
- * xtensa/config/system.h -- HAL definitions that are dependent on SYSTEM configuration
- *
- *  NOTE: The location and contents of this file are highly subject to change.
- *
- *  Source for configuration-independent binaries (which link in a
- *  configuration-specific HAL library) must NEVER include this file.
- *  The HAL itself has historically included this file in some instances,
- *  but this is not appropriate either, because the HAL is meant to be
- *  core-specific but system independent.
- */
-
-/* Customer ID=7490; Build=0x8176c; Copyright (c) 2000-2010 Tensilica Inc.
-
-   Permission is hereby granted, free of charge, to any person obtaining
-   a copy of this software and associated documentation files (the
-   "Software"), to deal in the Software without restriction, including
-   without limitation the rights to use, copy, modify, merge, publish,
-   distribute, sublicense, and/or sell copies of the Software, and to
-   permit persons to whom the Software is furnished to do so, subject to
-   the following conditions:
-
-   The above copyright notice and this permission notice shall be included
-   in all copies or substantial portions of the Software.
-
-   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
-
-
-#ifndef XTENSA_CONFIG_SYSTEM_H
-#define XTENSA_CONFIG_SYSTEM_H
-
-
-/*----------------------------------------------------------------------
-				CONFIGURED SOFTWARE OPTIONS
-  ----------------------------------------------------------------------*/
-
-#define XSHAL_USE_ABSOLUTE_LITERALS	0	/* (sw-only option, whether software uses absolute literals) */
-#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals.  */
-
-#define XSHAL_ABI			XTHAL_ABI_WINDOWED	/* (sw-only option, selected ABI) */
-/*  The above maps to one of the following constants:  */
-#define XTHAL_ABI_WINDOWED		0
-#define XTHAL_ABI_CALL0			1
-
-#define XSHAL_CLIB			XTHAL_CLIB_NEWLIB	/* (sw-only option, selected C library) */
-/*  The above maps to one of the following constants:  */
-#define XTHAL_CLIB_NEWLIB		0
-#define XTHAL_CLIB_UCLIBC		1
-#define XTHAL_CLIB_XCLIB		2
-
-#define XSHAL_USE_FLOATING_POINT	1
-
-#define XSHAL_FLOATING_POINT_ABI        1
-
-/*  SW workarounds enabled for HW errata:  */
-
-/*----------------------------------------------------------------------
-				DEVICE ADDRESSES
-  ----------------------------------------------------------------------*/
-
-/*
- *  Strange place to find these, but the configuration GUI
- *  allows moving these around to account for various core
- *  configurations.  Specific boards (and their BSP software)
- *  will have specific meanings for these components.
- */
-
-/*  I/O Block areas:  */
-#define XSHAL_IOBLOCK_CACHED_VADDR	0x70000000
-#define XSHAL_IOBLOCK_CACHED_PADDR	0x70000000
-#define XSHAL_IOBLOCK_CACHED_SIZE	0x0E000000
-
-#define XSHAL_IOBLOCK_BYPASS_VADDR	0x90000000
-#define XSHAL_IOBLOCK_BYPASS_PADDR	0x90000000
-#define XSHAL_IOBLOCK_BYPASS_SIZE	0x0E000000
-
-/*  System ROM:  */
-
-/*  System RAM:  */
-#define XSHAL_RAM_VADDR		0x60000000
-#define XSHAL_RAM_PADDR		0x60000000
-#define XSHAL_RAM_VSIZE		0x1FE00000
-#define XSHAL_RAM_PSIZE		0x1FE00000
-#define XSHAL_RAM_SIZE		XSHAL_RAM_PSIZE
-/*  Largest available area (free of vectors):  */
-#define XSHAL_RAM_AVAIL_VADDR	0x60000000
-#define XSHAL_RAM_AVAIL_VSIZE	0x1FE00000
-
-/*
- *  Shadow system RAM (same device as system RAM, at different address).
- *  (Emulation boards need this for the SONIC Ethernet driver
- *   when data caches are configured for writeback mode.)
- *  NOTE: on full MMU configs, this points to the BYPASS virtual address
- *  of system RAM, ie. is the same as XSHAL_RAM_* except that virtual
- *  addresses are viewed through the BYPASS static map rather than
- *  the CACHED static map.
- */
-#define XSHAL_RAM_BYPASS_VADDR		0x40000000
-#define XSHAL_RAM_BYPASS_PADDR		0x40000000
-#define XSHAL_RAM_BYPASS_PSIZE		0x1FE00000
-
-/*  Alternate system RAM (different device than system RAM):  */
-
-/*  Some available location in which to place devices in a simulation (eg. XTMP):  */
-#define XSHAL_SIMIO_CACHED_VADDR	0xC0000000
-#define XSHAL_SIMIO_BYPASS_VADDR	0xC0000000
-#define XSHAL_SIMIO_PADDR		0xC0000000
-#define XSHAL_SIMIO_SIZE		0x20000000
-
-
-/*----------------------------------------------------------------------
- *  For use by reference testbench exit and diagnostic routines.
- */
-#define XSHAL_MAGIC_EXIT		0xc0000000
-#define XSHAL_STL_INFO_LOCATION		0x4c
-
-/*----------------------------------------------------------------------
- *			DEVICE-ADDRESS DEPENDENT...
- *
- *  Values written to CACHEATTR special register (or its equivalent)
- *  to enable and disable caches in various modes.
- *----------------------------------------------------------------------*/
-
-/*----------------------------------------------------------------------
-			BACKWARD COMPATIBILITY ...
-  ----------------------------------------------------------------------*/
-
-/*
- *  NOTE:  the following two macros are DEPRECATED.  Use the latter
- *  board-specific macros instead, which are specially tuned for the
- *  particular target environments' memory maps.
- */
-#define XSHAL_CACHEATTR_BYPASS		XSHAL_XT2000_CACHEATTR_BYPASS	/* disable caches in bypass mode */
-#define XSHAL_CACHEATTR_DEFAULT		XSHAL_XT2000_CACHEATTR_DEFAULT	/* default setting to enable caches (no writeback!) */
-
-/*----------------------------------------------------------------------
-				GENERIC
-  ----------------------------------------------------------------------*/
-
-/*  For the following, a 512MB region is used if it contains a system (PIF) RAM,
- *  system (PIF) ROM, local memory, or XLMI.  */
-
-/*  These set any unused 512MB region to cache-BYPASS attribute:  */
-#define XSHAL_ALLVALID_CACHEATTR_WRITEBACK	0x42224242	/* enable caches in write-back mode */
-#define XSHAL_ALLVALID_CACHEATTR_WRITEALLOC	0x12221212	/* enable caches in write-allocate mode */
-#define XSHAL_ALLVALID_CACHEATTR_WRITETHRU	0x12221212	/* enable caches in write-through mode */
-#define XSHAL_ALLVALID_CACHEATTR_BYPASS		0x22222222	/* disable caches in bypass mode */
-#define XSHAL_ALLVALID_CACHEATTR_DEFAULT	XSHAL_ALLVALID_CACHEATTR_WRITEBACK	/* default setting to enable caches */
-
-/*  These set any unused 512MB region to ILLEGAL attribute:  */
-#define XSHAL_STRICT_CACHEATTR_WRITEBACK	0x4FFF4F4F	/* enable caches in write-back mode */
-#define XSHAL_STRICT_CACHEATTR_WRITEALLOC	0x1FFF1F1F	/* enable caches in write-allocate mode */
-#define XSHAL_STRICT_CACHEATTR_WRITETHRU	0x1FFF1F1F	/* enable caches in write-through mode */
-#define XSHAL_STRICT_CACHEATTR_BYPASS		0x2FFF2F2F	/* disable caches in bypass mode */
-#define XSHAL_STRICT_CACHEATTR_DEFAULT		XSHAL_STRICT_CACHEATTR_WRITEBACK	/* default setting to enable caches */
-
-/*  These set the first 512MB, if unused, to ILLEGAL attribute to help catch
- *  NULL-pointer dereference bugs; all other unused 512MB regions are set
- *  to cache-BYPASS attribute:  */
-#define XSHAL_TRAPNULL_CACHEATTR_WRITEBACK	0x4222424F	/* enable caches in write-back mode */
-#define XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC	0x1222121F	/* enable caches in write-allocate mode */
-#define XSHAL_TRAPNULL_CACHEATTR_WRITETHRU	0x1222121F	/* enable caches in write-through mode */
-#define XSHAL_TRAPNULL_CACHEATTR_BYPASS		0x2222222F	/* disable caches in bypass mode */
-#define XSHAL_TRAPNULL_CACHEATTR_DEFAULT	XSHAL_TRAPNULL_CACHEATTR_WRITEBACK	/* default setting to enable caches */
-
-/*----------------------------------------------------------------------
-			ISS (Instruction Set Simulator) SPECIFIC ...
-  ----------------------------------------------------------------------*/
-
-/*  For now, ISS defaults to the TRAPNULL settings:  */
-#define XSHAL_ISS_CACHEATTR_WRITEBACK	XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
-#define XSHAL_ISS_CACHEATTR_WRITEALLOC	XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC
-#define XSHAL_ISS_CACHEATTR_WRITETHRU	XSHAL_TRAPNULL_CACHEATTR_WRITETHRU
-#define XSHAL_ISS_CACHEATTR_BYPASS	XSHAL_TRAPNULL_CACHEATTR_BYPASS
-#define XSHAL_ISS_CACHEATTR_DEFAULT	XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
-
-#define XSHAL_ISS_PIPE_REGIONS	0
-#define XSHAL_ISS_SDRAM_REGIONS	0
-
-
-/*----------------------------------------------------------------------
-			XT2000 BOARD SPECIFIC ...
-  ----------------------------------------------------------------------*/
-
-/*  For the following, a 512MB region is used if it contains any system RAM,
- *  system ROM, local memory, XLMI, or other XT2000 board device or memory.
- *  Regions containing devices are forced to cache-BYPASS mode regardless
- *  of whether the macro is _WRITEBACK vs. _BYPASS etc.  */
-
-/*  These set any 512MB region unused on the XT2000 to ILLEGAL attribute:  */
-#define XSHAL_XT2000_CACHEATTR_WRITEBACK	0x4FF2424F	/* enable caches in write-back mode */
-#define XSHAL_XT2000_CACHEATTR_WRITEALLOC	0x1FF2121F	/* enable caches in write-allocate mode */
-#define XSHAL_XT2000_CACHEATTR_WRITETHRU	0x1FF2121F	/* enable caches in write-through mode */
-#define XSHAL_XT2000_CACHEATTR_BYPASS		0x2FF2222F	/* disable caches in bypass mode */
-#define XSHAL_XT2000_CACHEATTR_DEFAULT		XSHAL_XT2000_CACHEATTR_WRITEBACK	/* default setting to enable caches */
-
-#define XSHAL_XT2000_PIPE_REGIONS	0x00000000	/* BusInt pipeline regions */
-#define XSHAL_XT2000_SDRAM_REGIONS	0x00000050	/* BusInt SDRAM regions */
-
-
-/*----------------------------------------------------------------------
-				VECTOR INFO AND SIZES
-  ----------------------------------------------------------------------*/
-
-#define XSHAL_VECTORS_PACKED		0	/* UNUSED */
-#define XSHAL_STATIC_VECTOR_SELECT	0
-#define XSHAL_RESET_VECTOR_VADDR	0x20000000
-#define XSHAL_RESET_VECTOR_PADDR	0x20000000
-
-/*
- *  Sizes allocated to vectors by the system (memory map) configuration.
- *  These sizes are constrained by core configuration (eg. one vector's
- *  code cannot overflow into another vector) but are dependent on the
- *  system or board (or LSP) memory map configuration.
- *
- *  Whether or not each vector happens to be in a system ROM is also
- *  a system configuration matter, sometimes useful, included here also:
- */
-#define XSHAL_RESET_VECTOR_SIZE	0x00000300
-#define XSHAL_RESET_VECTOR_ISROM	0
-#define XSHAL_USER_VECTOR_SIZE	0x00000038
-#define XSHAL_USER_VECTOR_ISROM	0
-#define XSHAL_PROGRAMEXC_VECTOR_SIZE	XSHAL_USER_VECTOR_SIZE	/* for backward compatibility */
-#define XSHAL_USEREXC_VECTOR_SIZE	XSHAL_USER_VECTOR_SIZE	/* for backward compatibility */
-#define XSHAL_KERNEL_VECTOR_SIZE	0x00000038
-#define XSHAL_KERNEL_VECTOR_ISROM	0
-#define XSHAL_STACKEDEXC_VECTOR_SIZE	XSHAL_KERNEL_VECTOR_SIZE	/* for backward compatibility */
-#define XSHAL_KERNELEXC_VECTOR_SIZE	XSHAL_KERNEL_VECTOR_SIZE	/* for backward compatibility */
-#define XSHAL_DOUBLEEXC_VECTOR_SIZE	0x00000040
-#define XSHAL_DOUBLEEXC_VECTOR_ISROM	0
-#define XSHAL_WINDOW_VECTORS_SIZE	0x00000178
-#define XSHAL_WINDOW_VECTORS_ISROM	0
-#define XSHAL_INTLEVEL2_VECTOR_SIZE	0x00000038
-#define XSHAL_INTLEVEL2_VECTOR_ISROM	0
-#define XSHAL_INTLEVEL3_VECTOR_SIZE	0x00000038
-#define XSHAL_INTLEVEL3_VECTOR_ISROM	0
-#define XSHAL_INTLEVEL4_VECTOR_SIZE	0x00000038
-#define XSHAL_INTLEVEL4_VECTOR_ISROM	0
-#define XSHAL_INTLEVEL5_VECTOR_SIZE	0x00000038
-#define XSHAL_INTLEVEL5_VECTOR_ISROM	0
-#define XSHAL_INTLEVEL6_VECTOR_SIZE	0x00000038
-#define XSHAL_INTLEVEL6_VECTOR_ISROM	0
-#define XSHAL_DEBUG_VECTOR_SIZE		XSHAL_INTLEVEL6_VECTOR_SIZE
-#define XSHAL_DEBUG_VECTOR_ISROM	XSHAL_INTLEVEL6_VECTOR_ISROM
-#define XSHAL_NMI_VECTOR_SIZE	0x00000038
-#define XSHAL_NMI_VECTOR_ISROM	0
-#define XSHAL_INTLEVEL7_VECTOR_SIZE	XSHAL_NMI_VECTOR_SIZE
-
-#endif /*XTENSA_CONFIG_SYSTEM_H*/
-
diff --git a/src/platform/amd/vangogh/include/arch/xtensa/config/tie-asm.h b/src/platform/amd/vangogh/include/arch/xtensa/config/tie-asm.h
deleted file mode 100644
index e03bace79955..000000000000
--- a/src/platform/amd/vangogh/include/arch/xtensa/config/tie-asm.h
+++ /dev/null
@@ -1,292 +0,0 @@
-/* 
- * tie-asm.h -- compile-time HAL assembler definitions dependent on CORE & TIE
- *
- *  NOTE:  This header file is not meant to be included directly.
- */
-
-/* This header file contains assembly-language definitions (assembly
-   macros, etc.) for this specific Xtensa processor's TIE extensions
-   and options.  It is customized to this Xtensa processor configuration.
-
-   Customer ID=7490; Build=0x8176c; Copyright (c) 1999-2019 Cadence Design Systems Inc.
-
-   Permission is hereby granted, free of charge, to any person obtaining
-   a copy of this software and associated documentation files (the
-   "Software"), to deal in the Software without restriction, including
-   without limitation the rights to use, copy, modify, merge, publish,
-   distribute, sublicense, and/or sell copies of the Software, and to
-   permit persons to whom the Software is furnished to do so, subject to
-   the following conditions:
-
-   The above copyright notice and this permission notice shall be included
-   in all copies or substantial portions of the Software.
-
-   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
-
-#ifndef _XTENSA_CORE_TIE_ASM_H
-#define _XTENSA_CORE_TIE_ASM_H
-
-#include <xtensa/coreasm.h>
-
-/*  Selection parameter values for save-area save/restore macros:  */
-/*  Option vs. TIE:  */
-#define XTHAL_SAS_TIE	0x0001	/* custom extension or coprocessor */
-#define XTHAL_SAS_OPT	0x0002	/* optional (and not a coprocessor) */
-#define XTHAL_SAS_ANYOT	0x0003	/* both of the above */
-/*  Whether used automatically by compiler:  */
-#define XTHAL_SAS_NOCC	0x0004	/* not used by compiler w/o special opts/code */
-#define XTHAL_SAS_CC	0x0008	/* used by compiler without special opts/code */
-#define XTHAL_SAS_ANYCC	0x000C	/* both of the above */
-/*  ABI handling across function calls:  */
-#define XTHAL_SAS_CALR	0x0010	/* caller-saved */
-#define XTHAL_SAS_CALE	0x0020	/* callee-saved */
-#define XTHAL_SAS_GLOB	0x0040	/* global across function calls (in thread) */
-#define XTHAL_SAS_ANYABI	0x0070	/* all of the above three */
-/*  Misc  */
-#define XTHAL_SAS_ALL	0xFFFF	/* include all default NCP contents */
-#define XTHAL_SAS3(optie,ccuse,abi)	( ((optie) & XTHAL_SAS_ANYOT)  \
-					| ((ccuse) & XTHAL_SAS_ANYCC)  \
-					| ((abi)   & XTHAL_SAS_ANYABI) )
-
-
-    /*
-      *  Macro to store all non-coprocessor (extra) custom TIE and optional state
-      *  (not including zero-overhead loop registers).
-      *  Required parameters:
-      *      ptr         Save area pointer address register (clobbered)
-      *                  (register must contain a 4 byte aligned address).
-      *      at1..at4    Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
-      *                  registers are clobbered, the remaining are unused).
-      *  Optional parameters:
-      *      continue    If macro invoked as part of a larger store sequence, set to 1
-      *                  if this is not the first in the sequence.  Defaults to 0.
-      *      ofs         Offset from start of larger sequence (from value of first ptr
-      *                  in sequence) at which to store.  Defaults to next available space
-      *                  (or 0 if <continue> is 0).
-      *      select      Select what category(ies) of registers to store, as a bitmask
-      *                  (see XTHAL_SAS_xxx constants).  Defaults to all registers.
-      *      alloc       Select what category(ies) of registers to allocate; if any
-      *                  category is selected here that is not in <select>, space for
-      *                  the corresponding registers is skipped without doing any store.
-      */
-    .macro xchal_ncp_store  ptr at1 at2 at3 at4  continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
-	xchal_sa_start	\continue, \ofs
-	// Optional global registers used by default by the compiler:
-	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
-	xchal_sa_align	\ptr, 0, 1016, 4, 4
-	rur.threadptr	\at1		// threadptr option
-	s32i	\at1, \ptr, .Lxchal_ofs_+0
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
-	.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
-	xchal_sa_align	\ptr, 0, 1016, 4, 4
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
-	.endif
-	// Optional caller-saved registers not used by default by the compiler:
-	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
-	xchal_sa_align	\ptr, 0, 1012, 4, 4
-	rsr.br	\at1		// boolean option
-	s32i	\at1, \ptr, .Lxchal_ofs_+0
-	rsr.scompare1	\at1		// conditional store option
-	s32i	\at1, \ptr, .Lxchal_ofs_+4
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 8
-	.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
-	xchal_sa_align	\ptr, 0, 1012, 4, 4
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 8
-	.endif
-    .endm	// xchal_ncp_store
-
-    /*
-      *  Macro to load all non-coprocessor (extra) custom TIE and optional state
-      *  (not including zero-overhead loop registers).
-      *  Required parameters:
-      *      ptr         Save area pointer address register (clobbered)
-      *                  (register must contain a 4 byte aligned address).
-      *      at1..at4    Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
-      *                  registers are clobbered, the remaining are unused).
-      *  Optional parameters:
-      *      continue    If macro invoked as part of a larger load sequence, set to 1
-      *                  if this is not the first in the sequence.  Defaults to 0.
-      *      ofs         Offset from start of larger sequence (from value of first ptr
-      *                  in sequence) at which to load.  Defaults to next available space
-      *                  (or 0 if <continue> is 0).
-      *      select      Select what category(ies) of registers to load, as a bitmask
-      *                  (see XTHAL_SAS_xxx constants).  Defaults to all registers.
-      *      alloc       Select what category(ies) of registers to allocate; if any
-      *                  category is selected here that is not in <select>, space for
-      *                  the corresponding registers is skipped without doing any load.
-      */
-    .macro xchal_ncp_load  ptr at1 at2 at3 at4  continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
-	xchal_sa_start	\continue, \ofs
-	// Optional global registers used by default by the compiler:
-	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
-	xchal_sa_align	\ptr, 0, 1016, 4, 4
-	l32i	\at1, \ptr, .Lxchal_ofs_+0
-	wur.threadptr	\at1		// threadptr option
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
-	.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
-	xchal_sa_align	\ptr, 0, 1016, 4, 4
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
-	.endif
-	// Optional caller-saved registers not used by default by the compiler:
-	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
-	xchal_sa_align	\ptr, 0, 1012, 4, 4
-	l32i	\at1, \ptr, .Lxchal_ofs_+0
-	wsr.br	\at1		// boolean option
-	l32i	\at1, \ptr, .Lxchal_ofs_+4
-	wsr.scompare1	\at1		// conditional store option
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 8
-	.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
-	xchal_sa_align	\ptr, 0, 1012, 4, 4
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 8
-	.endif
-    .endm	// xchal_ncp_load
-
-
-#define XCHAL_NCP_NUM_ATMPS	1
-
-    /* 
-     *  Macro to store the state of TIE coprocessor AudioEngineLX.
-     *  Required parameters:
-     *      ptr         Save area pointer address register (clobbered)
-     *                  (register must contain a 8 byte aligned address).
-     *      at1..at4    Four temporary address registers (first XCHAL_CP1_NUM_ATMPS
-     *                  registers are clobbered, the remaining are unused).
-     *  Optional parameters are the same as for xchal_ncp_store.
-     */
-#define xchal_cp_AudioEngineLX_store	xchal_cp1_store
-    .macro	xchal_cp1_store  ptr at1 at2 at3 at4  continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
-	xchal_sa_start \continue, \ofs
-	// Custom caller-saved registers not used by default by the compiler:
-	.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
-	xchal_sa_align	\ptr, 0, 0, 8, 8
-	ae_s64.i	aed0, \ptr, .Lxchal_ofs_+32
-	ae_s64.i	aed1, \ptr, .Lxchal_ofs_+40
-	ae_s64.i	aed2, \ptr, .Lxchal_ofs_+48
-	ae_s64.i	aed3, \ptr, .Lxchal_ofs_+56
-	addi.a	\ptr, \ptr, 64
-	ae_s64.i	aed4, \ptr, .Lxchal_ofs_+0
-	ae_s64.i	aed5, \ptr, .Lxchal_ofs_+8
-	ae_s64.i	aed6, \ptr, .Lxchal_ofs_+16
-	ae_s64.i	aed7, \ptr, .Lxchal_ofs_+24
-	ae_s64.i	aed8, \ptr, .Lxchal_ofs_+32
-	ae_s64.i	aed9, \ptr, .Lxchal_ofs_+40
-	ae_s64.i	aed10, \ptr, .Lxchal_ofs_+48
-	ae_s64.i	aed11, \ptr, .Lxchal_ofs_+56
-	addi.a	\ptr, \ptr, 64
-	ae_s64.i	aed12, \ptr, .Lxchal_ofs_+0
-	ae_s64.i	aed13, \ptr, .Lxchal_ofs_+8
-	ae_s64.i	aed14, \ptr, .Lxchal_ofs_+16
-	ae_s64.i	aed15, \ptr, .Lxchal_ofs_+24
-	ae_salign64.i	u0, \ptr, .Lxchal_ofs_+32
-	ae_salign64.i	u1, \ptr, .Lxchal_ofs_+40
-	ae_salign64.i	u2, \ptr, .Lxchal_ofs_+48
-	ae_salign64.i	u3, \ptr, .Lxchal_ofs_+56
-	addi.a	\ptr, \ptr, -128
-	ae_movvfcrfsr	aed0		// ureg FCR_FSR
-	ae_s64.i	aed0, \ptr, .Lxchal_ofs_+0 + 0
-	rur.ae_ovf_sar	\at1		// ureg 240
-	s32i	\at1, \ptr, .Lxchal_ofs_+8
-	rur.ae_bithead	\at1		// ureg 241
-	s32i	\at1, \ptr, .Lxchal_ofs_+12
-	rur.ae_ts_fts_bu_bp	\at1		// ureg 242
-	s32i	\at1, \ptr, .Lxchal_ofs_+16
-	rur.ae_cw_sd_no	\at1		// ureg 243
-	s32i	\at1, \ptr, .Lxchal_ofs_+20
-	rur.ae_cbegin0	\at1		// ureg 246
-	s32i	\at1, \ptr, .Lxchal_ofs_+24
-	rur.ae_cend0	\at1		// ureg 247
-	s32i	\at1, \ptr, .Lxchal_ofs_+28
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 192
-	.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
-	xchal_sa_align	\ptr, 0, 0, 8, 8
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 192
-	.endif
-    .endm	// xchal_cp1_store
-
-    /* 
-     *  Macro to load the state of TIE coprocessor AudioEngineLX.
-     *  Required parameters:
-     *      ptr         Save area pointer address register (clobbered)
-     *                  (register must contain a 8 byte aligned address).
-     *      at1..at4    Four temporary address registers (first XCHAL_CP1_NUM_ATMPS
-     *                  registers are clobbered, the remaining are unused).
-     *  Optional parameters are the same as for xchal_ncp_load.
-     */
-#define xchal_cp_AudioEngineLX_load	xchal_cp1_load
-    .macro	xchal_cp1_load  ptr at1 at2 at3 at4  continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
-	xchal_sa_start \continue, \ofs
-	// Custom caller-saved registers not used by default by the compiler:
-	.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
-	xchal_sa_align	\ptr, 0, 0, 8, 8
-	ae_l64.i	aed0, \ptr, .Lxchal_ofs_+0 + 0		// ureg FCR_FSR
-	ae_movfcrfsrv	aed0
-	l32i	\at1, \ptr, .Lxchal_ofs_+8
-	wur.ae_ovf_sar	\at1		// ureg 240
-	l32i	\at1, \ptr, .Lxchal_ofs_+12
-	wur.ae_bithead	\at1		// ureg 241
-	l32i	\at1, \ptr, .Lxchal_ofs_+16
-	wur.ae_ts_fts_bu_bp	\at1		// ureg 242
-	l32i	\at1, \ptr, .Lxchal_ofs_+20
-	wur.ae_cw_sd_no	\at1		// ureg 243
-	l32i	\at1, \ptr, .Lxchal_ofs_+24
-	wur.ae_cbegin0	\at1		// ureg 246
-	l32i	\at1, \ptr, .Lxchal_ofs_+28
-	wur.ae_cend0	\at1		// ureg 247
-	ae_l64.i	aed0, \ptr, .Lxchal_ofs_+32
-	ae_l64.i	aed1, \ptr, .Lxchal_ofs_+40
-	ae_l64.i	aed2, \ptr, .Lxchal_ofs_+48
-	ae_l64.i	aed3, \ptr, .Lxchal_ofs_+56
-	addi.a	\ptr, \ptr, 64
-	ae_l64.i	aed4, \ptr, .Lxchal_ofs_+0
-	ae_l64.i	aed5, \ptr, .Lxchal_ofs_+8
-	ae_l64.i	aed6, \ptr, .Lxchal_ofs_+16
-	ae_l64.i	aed7, \ptr, .Lxchal_ofs_+24
-	ae_l64.i	aed8, \ptr, .Lxchal_ofs_+32
-	ae_l64.i	aed9, \ptr, .Lxchal_ofs_+40
-	ae_l64.i	aed10, \ptr, .Lxchal_ofs_+48
-	ae_l64.i	aed11, \ptr, .Lxchal_ofs_+56
-	addi.a	\ptr, \ptr, 64
-	ae_l64.i	aed12, \ptr, .Lxchal_ofs_+0
-	ae_l64.i	aed13, \ptr, .Lxchal_ofs_+8
-	ae_l64.i	aed14, \ptr, .Lxchal_ofs_+16
-	ae_l64.i	aed15, \ptr, .Lxchal_ofs_+24
-	addi.a	\ptr, \ptr, 32
-	ae_lalign64.i	u0, \ptr, .Lxchal_ofs_+0
-	ae_lalign64.i	u1, \ptr, .Lxchal_ofs_+8
-	ae_lalign64.i	u2, \ptr, .Lxchal_ofs_+16
-	ae_lalign64.i	u3, \ptr, .Lxchal_ofs_+24
-	.set	.Lxchal_pofs_, .Lxchal_pofs_ + 160
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 32
-	.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
-	xchal_sa_align	\ptr, 0, 0, 8, 8
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 192
-	.endif
-    .endm	// xchal_cp1_load
-
-#define XCHAL_CP1_NUM_ATMPS	1
-#define XCHAL_SA_NUM_ATMPS	1
-
-	/*  Empty macros for unconfigured coprocessors:  */
-	.macro xchal_cp0_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp0_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp2_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp2_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp3_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp3_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp4_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp4_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp5_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp5_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp6_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp6_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp7_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp7_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-
-#endif /*_XTENSA_CORE_TIE_ASM_H*/
-
diff --git a/src/platform/amd/vangogh/include/arch/xtensa/config/tie.h b/src/platform/amd/vangogh/include/arch/xtensa/config/tie.h
deleted file mode 100644
index 3a5f1106d316..000000000000
--- a/src/platform/amd/vangogh/include/arch/xtensa/config/tie.h
+++ /dev/null
@@ -1,186 +0,0 @@
-/* 
- * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
- *
- *  NOTE:  This header file is not meant to be included directly.
- */
-
-/* This header file describes this specific Xtensa processor's TIE extensions
-   that extend basic Xtensa core functionality.  It is customized to this
-   Xtensa processor configuration.
-
-   Customer ID=7490; Build=0x8176c; Copyright (c) 1999-2019 Cadence Design Systems Inc.
-
-   Permission is hereby granted, free of charge, to any person obtaining
-   a copy of this software and associated documentation files (the
-   "Software"), to deal in the Software without restriction, including
-   without limitation the rights to use, copy, modify, merge, publish,
-   distribute, sublicense, and/or sell copies of the Software, and to
-   permit persons to whom the Software is furnished to do so, subject to
-   the following conditions:
-
-   The above copyright notice and this permission notice shall be included
-   in all copies or substantial portions of the Software.
-
-   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
-
-#ifndef XTENSA_CORE_TIE_H
-#define XTENSA_CORE_TIE_H
-
-/* parasoft-begin-suppress ALL "This file not MISRA checked." */
-
-#define XCHAL_CP_NUM			1	/* number of coprocessors */
-#define XCHAL_CP_MAX			2	/* max CP ID + 1 (0 if none) */
-#define XCHAL_CP_MASK			0x02	/* bitmask of all CPs by ID */
-#define XCHAL_CP_PORT_MASK		0x00	/* bitmask of only port CPs */
-
-/*  Basic parameters of each coprocessor:  */
-#define XCHAL_CP1_NAME			"AudioEngineLX"
-#define XCHAL_CP1_IDENT			AudioEngineLX
-#define XCHAL_CP1_SA_SIZE		192	/* size of state save area */
-#define XCHAL_CP1_SA_ALIGN		8	/* min alignment of save area */
-#define XCHAL_CP_ID_AUDIOENGINELX   	1	/* coprocessor ID (0..7) */
-
-/*  Filler info for unassigned coprocessors, to simplify arrays etc:  */
-#define XCHAL_CP0_SA_SIZE		0
-#define XCHAL_CP0_SA_ALIGN		1
-#define XCHAL_CP2_SA_SIZE		0
-#define XCHAL_CP2_SA_ALIGN		1
-#define XCHAL_CP3_SA_SIZE		0
-#define XCHAL_CP3_SA_ALIGN		1
-#define XCHAL_CP4_SA_SIZE		0
-#define XCHAL_CP4_SA_ALIGN		1
-#define XCHAL_CP5_SA_SIZE		0
-#define XCHAL_CP5_SA_ALIGN		1
-#define XCHAL_CP6_SA_SIZE		0
-#define XCHAL_CP6_SA_ALIGN		1
-#define XCHAL_CP7_SA_SIZE		0
-#define XCHAL_CP7_SA_ALIGN		1
-
-/*  Save area for non-coprocessor optional and custom (TIE) state:  */
-#define XCHAL_NCP_SA_SIZE		12
-#define XCHAL_NCP_SA_ALIGN		4
-
-/*  Total save area for optional and custom state (NCP + CPn):  */
-#define XCHAL_TOTAL_SA_SIZE		208	/* with 16-byte align padding */
-#define XCHAL_TOTAL_SA_ALIGN		8	/* actual minimum alignment */
-
-/*
- * Detailed contents of save areas.
- * NOTE:  caller must define the XCHAL_SA_REG macro (not defined here)
- * before expanding the XCHAL_xxx_SA_LIST() macros.
- *
- * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
- *		dbnum,base,regnum,bitsz,gapsz,reset,x...)
- *
- *	s = passed from XCHAL_*_LIST(s), eg. to select how to expand
- *	ccused = set if used by compiler without special options or code
- *	abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
- *	kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
- *	opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg)
- *	name = lowercase reg name (no quotes)
- *	galign = group byte alignment (power of 2) (galign >= align)
- *	align = register byte alignment (power of 2)
- *	asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz)
- *	  (not including any pad bytes required to galign this or next reg)
- *	dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>)
- *	base = reg shortname w/o index (or sr=special, ur=TIE user reg)
- *	regnum = reg index in regfile, or special/TIE-user reg number
- *	bitsz = number of significant bits (regfile width, or ur/sr mask bits)
- *	gapsz = intervening bits, if bitsz bits not stored contiguously
- *	(padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize)
- *	reset = register reset value (or 0 if undefined at reset)
- *	x = reserved for future use (0 until then)
- *
- *  To filter out certain registers, e.g. to expand only the non-global
- *  registers used by the compiler, you can do something like this:
- *
- *  #define XCHAL_SA_REG(s,ccused,p...)	SELCC##ccused(p)
- *  #define SELCC0(p...)
- *  #define SELCC1(abikind,p...)	SELAK##abikind(p)
- *  #define SELAK0(p...)		REG(p)
- *  #define SELAK1(p...)		REG(p)
- *  #define SELAK2(p...)
- *  #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \
- *		...what you want to expand...
- */
-
-#define XCHAL_NCP_SA_NUM	3
-#define XCHAL_NCP_SA_LIST(s)	\
- XCHAL_SA_REG(s,1,2,1,1,      threadptr, 4, 4, 4,0x03E7,  ur,231, 32,0,0,0) \
- XCHAL_SA_REG(s,0,0,0,1,             br, 4, 4, 4,0x0204,  sr,4  , 16,0,0,0) \
- XCHAL_SA_REG(s,0,0,0,1,      scompare1, 4, 4, 4,0x020C,  sr,12 , 32,0,0,0)
-
-#define XCHAL_CP0_SA_NUM	0
-#define XCHAL_CP0_SA_LIST(s)	/* empty */
-
-#define XCHAL_CP1_SA_NUM	27
-#define XCHAL_CP1_SA_LIST(s)	\
- XCHAL_SA_REG(s,0,0,1,0,        fcr_fsr, 8, 8, 8,0x1015,  ur,-1 ,  7,0,0,0) \
- XCHAL_SA_REG(s,0,0,1,0,     ae_ovf_sar, 4, 4, 4,0x03F0,  ur,240,  8,0,0,0) \
- XCHAL_SA_REG(s,0,0,1,0,     ae_bithead, 4, 4, 4,0x03F1,  ur,241, 32,0,0,0) \
- XCHAL_SA_REG(s,0,0,1,0,ae_ts_fts_bu_bp, 4, 4, 4,0x03F2,  ur,242, 16,0,0,0) \
- XCHAL_SA_REG(s,0,0,1,0,    ae_cw_sd_no, 4, 4, 4,0x03F3,  ur,243, 29,0,0,0) \
- XCHAL_SA_REG(s,0,0,1,0,     ae_cbegin0, 4, 4, 4,0x03F6,  ur,246, 32,0,0,0) \
- XCHAL_SA_REG(s,0,0,1,0,       ae_cend0, 4, 4, 4,0x03F7,  ur,247, 32,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aed0, 8, 8, 8,0x1000, aed,0  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aed1, 8, 8, 8,0x1001, aed,1  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aed2, 8, 8, 8,0x1002, aed,2  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aed3, 8, 8, 8,0x1003, aed,3  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aed4, 8, 8, 8,0x1004, aed,4  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aed5, 8, 8, 8,0x1005, aed,5  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aed6, 8, 8, 8,0x1006, aed,6  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aed7, 8, 8, 8,0x1007, aed,7  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aed8, 8, 8, 8,0x1008, aed,8  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aed9, 8, 8, 8,0x1009, aed,9  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed10, 8, 8, 8,0x100A, aed,10 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed11, 8, 8, 8,0x100B, aed,11 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed12, 8, 8, 8,0x100C, aed,12 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed13, 8, 8, 8,0x100D, aed,13 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed14, 8, 8, 8,0x100E, aed,14 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed15, 8, 8, 8,0x100F, aed,15 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,             u0, 8, 8, 8,0x1010,   u,0  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,             u1, 8, 8, 8,0x1011,   u,1  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,             u2, 8, 8, 8,0x1012,   u,2  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,             u3, 8, 8, 8,0x1013,   u,3  , 64,0,0,0)
-
-#define XCHAL_CP2_SA_NUM	0
-#define XCHAL_CP2_SA_LIST(s)	/* empty */
-
-#define XCHAL_CP3_SA_NUM	0
-#define XCHAL_CP3_SA_LIST(s)	/* empty */
-
-#define XCHAL_CP4_SA_NUM	0
-#define XCHAL_CP4_SA_LIST(s)	/* empty */
-
-#define XCHAL_CP5_SA_NUM	0
-#define XCHAL_CP5_SA_LIST(s)	/* empty */
-
-#define XCHAL_CP6_SA_NUM	0
-#define XCHAL_CP6_SA_LIST(s)	/* empty */
-
-#define XCHAL_CP7_SA_NUM	0
-#define XCHAL_CP7_SA_LIST(s)	/* empty */
-
-/* Byte length of instruction from its first nibble (op0 field), per FLIX.  */
-/* (not available, must use XCHAL_BYTE0_FORMAT_LENGTHS for this processor) */
-/* Byte length of instruction from its first byte, per FLIX.  */
-#define XCHAL_BYTE0_FORMAT_LENGTHS	\
-	3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,5,8,\
-	3,3,3,3,3,3,3,3,2,2,2,2,2,2,5,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,5,8,\
-	3,3,3,3,3,3,3,3,2,2,2,2,2,2,6,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,6,8,\
-	3,3,3,3,3,3,3,3,2,2,2,2,2,2,6,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,6,8,\
-	3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8,\
-	3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8,\
-	3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8,\
-	3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8
-
-/* parasoft-end-suppress ALL "This file not MISRA checked." */
-
-#endif /* XTENSA_CORE_TIE_H */
-
diff --git a/src/platform/amd/vangogh/include/arch/xtensa/tie/xt_datacache.h b/src/platform/amd/vangogh/include/arch/xtensa/tie/xt_datacache.h
deleted file mode 100755
index 7fcaa456ca16..000000000000
--- a/src/platform/amd/vangogh/include/arch/xtensa/tie/xt_datacache.h
+++ /dev/null
@@ -1,4 +0,0 @@
-#ifndef __cstub_xt_datacache_h__
-#define __cstub_xt_datacache_h__
-
-#endif
diff --git a/src/platform/amd/vangogh/include/platform/chip_offset_byte.h b/src/platform/amd/vangogh/include/platform/chip_offset_byte.h
deleted file mode 100644
index e6fda5f19b60..000000000000
--- a/src/platform/amd/vangogh/include/platform/chip_offset_byte.h
+++ /dev/null
@@ -1,151 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- *
- * Copyright(c) 2023 AMD.All rights reserved.
- *
- * Author:      Basavaraj Hiregoudar <basavaraj.hiregoudar@amd.com>
- *              SaiSurya, Ch <saisurya.chakkaveeravenkatanaga@amd.com>
- */
-#ifndef _VANGOGH_OFFSET_HEADER
-#define _VANGOGH_OFFSET_HEADER
-
-#define PU_REGISTER_BASE        (0x9FD00000 - 0x01240000)
-#define PU_SCRATCH_REG_BASE	(0x9FF00000 - 0x01250000)
-
-/* Registers from ACP_DMA block */
-#define ACP_DMA_CNTL_0                                0x1240000
-#define ACP_DMA_DESC_BASE_ADDR                        0x12400E0
-#define ACP_DMA_DESC_MAX_NUM_DSCR                     0x12400E4
-#define ACP_DMA_CH_STS                                0x12400E8
-
-#define ACP_DMA_DSCR_STRT_IDX_0                       0x1240020
-#define ACP_DMA_DSCR_CNT_0                            0x1240040
-#define ACP_DMA_PRIO_0                                0x1240060
-
-/* Registers from ACP_MISC block */
-#define ACP_CLKMUX_SEL				      0x124142C
-#define ACP_EXTERNAL_INTR_ENB                         0x1241800
-#define ACP_EXTERNAL_INTR_STAT                        0x1241808
-#define ACP_DSP0_INTR_CNTL                            0x124180C
-#define ACP_DSP0_INTR_STAT                            0x1241810
-#define ACP_DSP_SW_INTR_CNTL                          0x1241814
-#define ACP_DSP_SW_INTR_STAT                          0x1241818
-#define ACP_SW_INTR_TRIG                              0x124181C
-#define ACP_SMU_MAILBOX                               0x1241820
-#define DSP_INTERRUPT_ROUTING_CTRL_0		      0x1241824
-#define DSP_INTERRUPT_ROUTING_CTRL_1                  0x1241828
-#define ACP_FUTURE_REG_ACLK_0                         0x1241864
-
-#define ACP_TIMER                                     0x1241878
-#define ACP_TIMER_CNTL                                0x124187C
-#define ACP_AXI2DAGB_SEM_0			      0x1241884
-
-#define ACP_SRBM_CLIENT_BASE_ADDR                     0x1241BBC
-#define ACP_SRBM_CLIENT_RDDATA                        0x1241BC0
-#define ACP_SRBM_CYCLE_STS                            0x1241BC4
-#define ACP_SRBM_CLIENT_CONFIG                        0x1241BC8
-
-/* Registers from ACP_AUDIO_BUFFERS block */
-#define ACP_I2S_RX_RINGBUFADDR                        0x1242000
-#define ACP_I2S_RX_RINGBUFSIZE                        0x1242004
-#define ACP_I2S_RX_LINKPOSITIONCNTR                   0x1242008
-#define ACP_I2S_RX_FIFOADDR                           0x124200C
-#define ACP_I2S_RX_FIFOSIZE                           0x1242010
-#define ACP_I2S_RX_DMA_SIZE                           0x1242014
-#define ACP_I2S_RX_LINEARPOSITIONCNTR_HIGH            0x1242018
-#define ACP_I2S_RX_LINEARPOSITIONCNTR_LOW             0x124201C
-#define ACP_I2S_RX_INTR_WATERMARK_SIZE                0x1242020
-#define ACP_I2S_TX_RINGBUFADDR                        0x1242024
-#define ACP_I2S_TX_RINGBUFSIZE                        0x1242028
-#define ACP_I2S_TX_LINKPOSITIONCNTR                   0x124202C
-#define ACP_I2S_TX_FIFOADDR                           0x1242030
-#define ACP_I2S_TX_FIFOSIZE                           0x1242034
-#define ACP_I2S_TX_DMA_SIZE                           0x1242038
-#define ACP_I2S_TX_LINEARPOSITIONCNTR_HIGH            0x124203C
-#define ACP_I2S_TX_LINEARPOSITIONCNTR_LOW             0x1242040
-#define ACP_I2S_TX_INTR_WATERMARK_SIZE                0x1242044
-#define ACP_BT_RX_RINGBUFADDR                         0x1242048
-#define ACP_BT_RX_RINGBUFSIZE                         0x124204C
-#define ACP_BT_RX_LINKPOSITIONCNTR                    0x1242050
-#define ACP_BT_RX_FIFOADDR                            0x1242054
-#define ACP_BT_RX_FIFOSIZE                            0x1242058
-#define ACP_BT_RX_DMA_SIZE                            0x124205C
-#define ACP_BT_RX_LINEARPOSITIONCNTR_HIGH             0x1242060
-#define ACP_BT_RX_LINEARPOSITIONCNTR_LOW              0x1242064
-#define ACP_BT_RX_INTR_WATERMARK_SIZE                 0x1242068
-#define ACP_BT_TX_RINGBUFADDR                         0x124206C
-#define ACP_BT_TX_RINGBUFSIZE                         0x1242070
-#define ACP_BT_TX_LINKPOSITIONCNTR                    0x1242074
-#define ACP_BT_TX_FIFOADDR                            0x1242078
-#define ACP_BT_TX_FIFOSIZE                            0x124207C
-#define ACP_BT_TX_DMA_SIZE                            0x1242080
-#define ACP_BT_TX_LINEARPOSITIONCNTR_HIGH             0x1242084
-#define ACP_BT_TX_LINEARPOSITIONCNTR_LOW              0x1242088
-#define ACP_BT_TX_INTR_WATERMARK_SIZE                 0x124208C
-#define ACP_HS_RX_RINGBUFADDR			      0x1242090
-#define ACP_HS_RX_RINGBUFSIZE			      0x1242094
-#define ACP_HS_RX_LINKPOSITIONCNTR		      0x1242098
-#define ACP_HS_RX_FIFOADDR			      0x124209C
-#define ACP_HS_RX_FIFOSIZE			      0x12420A0
-#define ACP_HS_RX_DMA_SIZE			      0x12420A4
-#define ACP_HS_RX_LINEARPOSITIONCNTR_HIGH	      0x12420A8
-#define ACP_HS_RX_LINEARPOSITIONCNTR_LOW	      0x12420AC
-#define ACP_HS_RX_INTR_WATERMARK_SIZE		      0x12420B0
-#define ACP_HS_TX_RINGBUFADDR			      0x12420B4
-#define ACP_HS_TX_RINGBUFSIZE			      0x12420B8
-#define ACP_HS_TX_LINKPOSITIONCNTR		      0x12420BC
-#define ACP_HS_TX_FIFOADDR			      0x12420C0
-#define ACP_HS_TX_FIFOSIZE			      0x12420C4
-#define ACP_HS_TX_DMA_SIZE			      0x12420C8
-#define ACP_HS_TX_LINEARPOSITIONCNTR_HIGH	      0x12420CC
-#define ACP_HS_TX_LINEARPOSITIONCNTR_LOW	      0x12420D0
-#define ACP_HS_TX_INTR_WATERMARK_SIZE		      0x12420D4
-
-/* Registers from ACP_I2S_TDM block */
-#define ACP_I2STDM_IER                                0x1242400
-#define ACP_I2STDM_IRER                               0x1242404
-#define ACP_I2STDM_RXFRMT                             0x1242408
-#define ACP_I2STDM_ITER                               0x124240C
-#define ACP_I2STDM_TXFRMT                             0x1242410
-#define ACP_I2STDM0_MSTRCLKGEN			      0x1242414
-#define ACP_I2STDM1_MSTRCLKGEN			      0x1242418
-#define ACP_I2STDM2_MSTRCLKGEN                        0x124241C
-#define ACP_I2STDM_REFCLKGEN			      0x1242420
-
-/* Registers from ACP_BT_TDM block */
-#define ACP_BTTDM_IER                                 0x1242800
-#define ACP_BTTDM_IRER                                0x1242804
-#define ACP_BTTDM_RXFRMT                              0x1242808
-#define ACP_BTTDM_ITER                                0x124280C
-#define ACP_BTTDM_TXFRMT                              0x1242810
-
-/* Registers from ACP_HS_TDM block */
-#define ACP_HSTDM_IER				      0x1242814
-#define ACP_HSTDM_IRER				      0x1242818
-#define ACP_HSTDM_RXFRMT			      0x124281C
-#define ACP_HSTDM_ITER				      0x1242820
-#define ACP_HSTDM_TXFRMT			      0x1242824
-
-/* Registers from ACP_WOV block */
-#define ACP_WOV_VAD_ENABLE                            0x1242C00
-#define ACP_WOV_PDM_ENABLE                            0x1242C04
-#define ACP_WOV_PDM_DMA_ENABLE                        0x1242C08
-#define ACP_WOV_RX_RINGBUFADDR                        0x1242C0C
-#define ACP_WOV_RX_RINGBUFSIZE                        0x1242C10
-#define ACP_WOV_RX_LINKPOSITIONCNTR                   0x1242C14
-#define ACP_WOV_RX_LINEARPOSITIONCNTR_HIGH            0x1242C18
-#define ACP_WOV_RX_LINEARPOSITIONCNTR_LOW             0x1242C1C
-#define ACP_WOV_RX_INTR_WATERMARK_SIZE                0x1242C20
-#define ACP_WOV_PDM_FIFO_FLUSH                        0x1242C24
-#define ACP_WOV_PDM_NO_OF_CHANNELS                    0x1242C28
-#define ACP_WOV_PDM_DECIMATION_FACTOR                 0x1242C2C
-#define ACP_WOV_PDM_VAD_CTRL                          0x1242C30
-
-#define ACP_WOV_MISC_CTRL                             0x1242C5C
-#define ACP_WOV_CLK_CTRL                              0x1242C60
-#define ACP_PDM_VAD_DYNAMIC_CLK_GATING_EN             0x1242C64
-#define ACP_WOV_ERROR_STATUS_REGISTER                 0x1242C68
-
-#define MP1_SMN_C2PMSG_69                             0x58A14
-#define MP1_SMN_C2PMSG_85                             0x58A54
-#define MP1_SMN_C2PMSG_93                             0x58A74
-#endif
diff --git a/src/platform/amd/vangogh/include/platform/chip_registers.h b/src/platform/amd/vangogh/include/platform/chip_registers.h
deleted file mode 100644
index f7e89d18dedb..000000000000
--- a/src/platform/amd/vangogh/include/platform/chip_registers.h
+++ /dev/null
@@ -1,707 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- *
- * Copyright(c) 2023 AMD.All rights reserved.
- *
- * Author:      Basavaraj Hiregoudar <basavaraj.hiregoudar@amd.com>
- *              SaiSurya, Ch <saisurya.chakkaveeravenkatanaga@amd.com>
- */
-#if !defined(_VANGOGH_REG_HEADER)
-#define _VANGOGH_REG_HEADER
-
-typedef	union acp_dma_cntl_0 {
-	struct {
-	unsigned int	dmachrst:1;
-	unsigned int	dmachrun:1;
-	unsigned int	dmachiocen:1;
-	unsigned int	:29;
-	} bits;
-unsigned int	u32all;
-} acp_dma_cntl_0_t;
-
-typedef	union acp_dma_ch_sts {
-	struct {
-	unsigned int	dmachrunsts:8;
-	unsigned int	:24;
-	} bits;
-unsigned int	u32all;
-} acp_dma_ch_sts_t;
-
-typedef	union acp_external_intr_enb {
-	struct {
-	unsigned int	acpextintrenb:1;
-	unsigned int	:31;
-	} bits;
-unsigned int	u32all;
-} acp_external_intr_enb_t;
-
-typedef	union acp_dsp0_intr_cntl {
-	struct {
-	unsigned int	dmaiocmask:8;
-	unsigned int	:8;
-	unsigned int	wov_dma_intr_mask:1;
-	unsigned int	:6;
-	unsigned int	audio_buffer_int_mask:6;
-	unsigned int	:3;
-	} bits;
-unsigned int	u32all;
-} acp_dsp0_intr_cntl_t;
-
-typedef	union acp_dsp0_intr_stat {
-	struct {
-	unsigned int	dmaiocstat:8;
-	unsigned int	:8;
-	unsigned int	wov_dma_stat:1;
-	unsigned int	:6;
-	unsigned int	audio_buffer_int_stat:6;
-	unsigned int	:3;
-	} bits;
-unsigned int	u32all;
-} acp_dsp0_intr_stat_t;
-
-typedef	union acp_dsp_sw_intr_cntl {
-	struct {
-	unsigned int	:2;
-	unsigned int	dsp0_to_host_intr_mask:1;
-	unsigned int	:29;
-	} bits;
-unsigned int	u32all;
-} acp_dsp_sw_intr_cntl_t;
-
-typedef	union acp_dsp_sw_intr_stat {
-	struct {
-	unsigned int	host_to_dsp0_intr1_stat:1;
-	unsigned int	host_to_dsp0_intr2_stat:1;
-	unsigned int	dsp0_to_host_intr_stat:1;
-	unsigned int	host_to_dsp0_intr3_stat:1;
-	unsigned int	:28;
-	} bits;
-unsigned int	u32all;
-} acp_dsp_sw_intr_stat_t;
-
-typedef	union acp_sw_intr_trig {
-	struct {
-	unsigned int	trig_host_to_dsp0_intr1:1;
-	unsigned int	:1;
-	unsigned int	trig_dsp0_to_host_intr:1;
-	unsigned int	:29;
-	} bits;
-unsigned int	u32all;
-} acp_sw_intr_trig_t;
-
-typedef	union dsp_interrupt_routing_ctrl_0 {
-	struct {
-	unsigned int	dma_intr_level:3;
-	unsigned int	:18;
-	unsigned int	watchdog_intr_level:3;
-	unsigned int	az_sw_i2s_intr_level:3;
-	unsigned int	sha_intr_level:3;
-	unsigned int	:2;
-	} bits;
-unsigned int	u32all;
-} dsp_interrupt_routing_ctrl_0_t;
-
-typedef	union dsp_interrupt_routing_ctrl_1 {
-	struct {
-		unsigned int	host_to_dsp_intr1_level:3;
-		unsigned int	host_to_dsp_intr2_level:3;
-		unsigned int	src_intr_level:3;
-		unsigned int	mailbox_intr_level:3;
-		unsigned int	error_intr_level:3;
-		unsigned int	wov_intr_level:3;
-		unsigned int	:14;
-	} bits;
-	unsigned int    u32all;
-} dsp_interrupt_routing_ctrl_1_t;
-
-typedef	union acp_i2s_rx_ringbufaddr {
-	struct {
-	unsigned int	i2s_rx_ringbufaddr:27;
-	unsigned int	:5;
-	} bits;
-unsigned int	u32all;
-} acp_i2s_rx_ringbufaddr_t;
-
-typedef	union acp_i2s_rx_ringbufsize {
-	struct {
-	unsigned int	i2s_rx_ringbufsize:26;
-	unsigned int	:6;
-	} bits;
-unsigned int	u32all;
-} acp_i2s_rx_ringbufsize_t;
-
-typedef	union acp_i2s_rx_linkpositioncntr {
-	struct {
-	unsigned int	i2s_rx_linkpositioncntr:26;
-	unsigned int	:6;
-	} bits;
-unsigned int	u32all;
-} acp_i2s_rx_linkpositioncntr_t;
-
-typedef	union acp_i2s_rx_fifoaddr {
-	struct {
-	unsigned int	i2s_rx_fifoaddr:27;
-	unsigned int	:5;
-	} bits;
-unsigned int	u32all;
-} acp_i2s_rx_fifoaddr_t;
-
-typedef	union acp_i2s_rx_fifosize {
-	struct {
-	unsigned int	i2s_rx_fifosize:13;
-	unsigned int	:19;
-	} bits;
-unsigned int	u32all;
-} acp_i2s_rx_fifosize_t;
-
-typedef	union acp_i2s_rx_dma_size {
-	struct {
-	unsigned int	i2s_rx_dma_size:13;
-	unsigned int	:19;
-	} bits;
-unsigned int	u32all;
-} acp_i2s_rx_dma_size_t;
-
-typedef	union acp_i2s_rx_linearpositioncntr_high {
-	struct {
-	unsigned int	i2s_rx_linearpositioncntr_high:32;
-	} bits;
-unsigned int	u32all;
-} acp_i2s_rx_linearpositioncntr_high_t;
-
-typedef	union acp_i2s_rx_linearpositioncntr_low {
-	struct {
-	unsigned int	i2s_rx_linearpositioncntr_low:32;
-	} bits;
-unsigned int	u32all;
-} acp_i2s_rx_linearpositioncntr_low_t;
-
-typedef	union acp_i2s_rx_watermark_size {
-	struct {
-	unsigned int	i2s_rx_intr_watermark_size:26;
-	unsigned int	:6;
-	} bits;
-unsigned int	u32all;
-} acp_i2s_rx_intr_watermark_size_t;
-
-typedef	union acp_i2s_tx_ringbufaddr {
-	struct {
-	unsigned int	i2s_tx_ringbufaddr:27;
-	unsigned int	:5;
-	} bits;
-unsigned int	u32all;
-} acp_i2s_tx_ringbufaddr_t;
-
-typedef	union acp_i2s_tx_ringbufsize {
-	struct {
-	unsigned int	i2s_tx_ringbufsize:26;
-	unsigned int	:6;
-	} bits;
-unsigned int	u32all;
-} acp_i2s_tx_ringbufsize_t;
-
-typedef	union acp_i2s_tx_linkpositioncntr {
-	struct {
-	unsigned int	i2s_tx_linkpositioncntr:26;
-	unsigned int	:6;
-	} bits;
-unsigned int	u32all;
-} acp_i2s_tx_linkpositioncntr_t;
-
-typedef	union acp_i2s_tx_fifoaddr {
-	struct {
-	unsigned int	i2s_tx_fifoaddr:27;
-	unsigned int	:5;
-	} bits;
-unsigned int	u32all;
-} acp_i2s_tx_fifoaddr_t;
-
-typedef	union acp_i2s_tx_fifosize {
-	struct {
-	unsigned int	i2s_tx_fifosize:13;
-	unsigned int	:19;
-	} bits;
-unsigned int	u32all;
-} acp_i2s_tx_fifosize_t;
-
-typedef	union acp_i2s_tx_dma_size {
-	struct {
-	unsigned int	i2s_tx_dma_size:13;
-	unsigned int	:19;
-	} bits;
-unsigned int	u32all;
-} acp_i2s_tx_dma_size_t;
-
-typedef	union acp_i2s_tx_linearpositioncntr_high {
-	struct {
-	unsigned int	i2s_tx_linearpositioncntr_high:32;
-	} bits;
-unsigned int	u32all;
-} acp_i2s_tx_linearpositioncntr_hight_t;
-
-typedef	union acp_i2s_tx_linearpositioncntr_low {
-	struct {
-	unsigned int	i2s_tx_linearpositioncntr_low:32;
-	} bits;
-unsigned int	u32all;
-} acp_i2s_tx_linearpositioncntr_low_t;
-
-typedef	union acp_i2s_tx_intr_watermark_size {
-	struct {
-	unsigned int	i2s_tx_intr_watermark_size:26;
-	unsigned int	:6;
-	} bits;
-unsigned int	u32all;
-} acp_i2s_tx_intr_watermark_size_t;
-
-typedef	union acp_bt_rx_ringbufaddr {
-	struct {
-	unsigned int	bt_rx_ringbufaddr:27;
-	unsigned int	:5;
-	} bits;
-unsigned int	u32all;
-} acp_bt_rx_ringbufaddr_t;
-
-typedef	union acp_bt_rx_ringbufsize {
-	struct {
-	unsigned int	bt_rx_ringbufsize:26;
-	unsigned int	:6;
-	} bits;
-unsigned int	u32all;
-} acp_bt_rx_ringbufsize_t;
-
-typedef	union acp_bt_rx_linkpositioncntr {
-	struct {
-	unsigned int	bt_rx_linkpositioncntr:26;
-	unsigned int	:6;
-	} bits;
-unsigned int	u32all;
-} acp_bt_rx_linkpositioncntr_t;
-
-typedef	union acp_bt_rx_fifoaddr {
-	struct {
-	unsigned int	bt_rx_fifoaddr:27;
-	unsigned int	:5;
-	} bits;
-unsigned int	u32all;
-} acp_bt_rx_fifoaddr_t;
-
-typedef	union acp_bt_rx_fifosize {
-	struct {
-	unsigned int	bt_rx_fifosize:13;
-	unsigned int	:19;
-	} bits;
-unsigned int	u32all;
-} acp_bt_rx_fifosize_t;
-
-typedef	union acp_bt_rx_dma_size {
-	struct {
-	unsigned int	bt_rx_dma_size:13;
-	unsigned int	:19;
-	} bits;
-unsigned int	u32all;
-} acp_bt_rx_dma_size_t;
-
-typedef	union acp_bt_rx_linearpositioncntr_high {
-	struct {
-	unsigned int	bt_rx_linearpositioncntr_high:32;
-	} bits;
-unsigned int	u32all;
-} acp_bt_rx_linearpositioncntr_high_t;
-
-typedef	union acp_bt_rx_linearpositioncntr_low {
-	struct {
-	unsigned int	bt_rx_linearpositioncntr_low:32;
-	} bits;
-unsigned int	u32all;
-} acp_bt_rx_linearpositioncntr_low_t;
-
-typedef	union acp_bt_rx_intr_watermark_size {
-	struct {
-	unsigned int	bt_rx_intr_watermark_size:26;
-	unsigned int	:6;
-	} bits;
-unsigned int	u32all;
-} acp_bt_rx_intr_watermark_size_t;
-
-typedef	union acp_bt_tx_ringbufaddr {
-	struct {
-	unsigned int	bt_tx_ringbufaddr:27;
-	unsigned int	:5;
-	} bits;
-unsigned int	u32all;
-} acp_bt_tx_ringbufaddr_t;
-
-typedef	union acp_bt_tx_ringbufsize {
-	struct {
-	unsigned int	bt_tx_ringbufsize:26;
-	unsigned int	:6;
-	} bits;
-unsigned int	u32all;
-} acp_bt_tx_ringbufsize_t;
-
-typedef	union acp_bt_tx_linkpositiontcntr {
-	struct {
-	unsigned int	bt_tx_linkpositioncntr:26;
-	unsigned int	:6;
-	} bits;
-unsigned int	u32all;
-} acp_bt_tx_linkpositiontcntr_t;
-
-typedef	union acp_bt_tx_fifoaddr {
-	struct {
-	unsigned int	bt_tx_fifoaddr:27;
-	unsigned int	:5;
-	} bits;
-unsigned int	u32all;
-} acp_bt_tx_fifoaddr_t;
-
-typedef	union acp_bt_tx_fifosize {
-	struct {
-	unsigned int	bt_tx_fifosize:13;
-	unsigned int	:19;
-	} bits;
-unsigned int	u32all;
-} acp_bt_tx_fifosize_t;
-
-typedef	union acp_bt_tx_dmasize {
-	struct {
-	unsigned int	bt_tx_dma_size:13;
-	unsigned int	:19;
-	} bits;
-unsigned int	u32all;
-} acp_bt_tx_dmasize_t;
-
-typedef	union acp_bt_tx_linearpositioncntr_high {
-	struct {
-	unsigned int	bt_tx_linearpositioncntr_high:32;
-	} bits;
-unsigned int	u32all;
-} acp_bt_tx_linearpositioncntr_high_t;
-
-typedef	union acp_bt_tx_linearpositioncntr_low {
-	struct {
-	unsigned int	bt_tx_linearpositioncntr_low:32;
-	} bits;
-unsigned int	u32all;
-} acp_bt_tx_linearpositioncntr_low_t;
-
-typedef	union acp_bt_tx_intr_watermark_size {
-	struct {
-	unsigned int	bt_tx_intr_watermark_size:26;
-	unsigned int	:6;
-	} bits;
-unsigned int	u32all;
-} acp_bt_tx_intr_watermark_size_t;
-
-typedef	union acp_hs_rx_ringbufaddr {
-	struct {
-		unsigned int	hs_rx_ringbufaddr :32;
-	} bits;
-	unsigned int	u32all;
-} acp_hs_rx_ringbufaddr_t;
-
-typedef	union acp_hs_rx_ringbufsize {
-	struct {
-		unsigned int	hs_rx_ringbufsize :26;
-		unsigned int	:6;
-	} bits;
-	unsigned int	u32all;
-} acp_hs_rx_ringbufsize_t;
-
-typedef	union acp_hs_rx_linkpositioncntr {
-	struct {
-		unsigned int	hs_rx_linkpositioncntr :26;
-		unsigned int	:6;
-	} bits;
-	unsigned int	u32all;
-} acp_hs_rx_linkpositioncntr_t;
-
-typedef	union acp_hs_rx_fifoaddr {
-	struct {
-		unsigned int	hs_rx_fifoaddr :27;
-		unsigned int	:5;
-	} bits;
-	unsigned int	u32all;
-} acp_hs_rx_fifoaddr_t;
-
-typedef	union acp_hs_rx_fifosize {
-	struct {
-		unsigned int	hs_rx_fifosize :13;
-		unsigned int	:19;
-	} bits;
-	unsigned int	u32all;
-} acp_hs_rx_fifosize_t;
-
-typedef	union acp_hs_rx_dma_size {
-	struct {
-		unsigned int	hs_rx_dma_size :13;
-		unsigned int	:19;
-	} bits;
-	unsigned int	u32all;
-} acp_hs_rx_dma_size_t;
-
-typedef	union acp_hs_rx_linearpositioncntr_high {
-	struct {
-		unsigned int	hs_rx_linearpositioncntr_high :32;
-	} bits;
-	unsigned int	u32all;
-} acp_hs_rx_linearpositioncntr_high_t;
-
-typedef	union acp_hs_rx_linearpositioncntr_low {
-	struct {
-		unsigned int	hs_rx_linearpositioncntr_low :32;
-	} bits;
-	unsigned int	u32all;
-} acp_hs_rx_linearpositioncntr_low_t;
-
-typedef	union acp_hs_rx_intr_watermark_size {
-	struct {
-		unsigned int	hs_rx_intr_watermark_size :26;
-		unsigned int	:6;
-	} bits;
-	unsigned int	u32all;
-} acp_hs_rx_intr_watermark_size_t;
-
-typedef	union acp_hs_tx_ringbufaddr {
-	struct {
-		unsigned int	hs_tx_ringbufaddr :32;
-	} bits;
-	unsigned int	u32all;
-} acp_hs_tx_ringbufaddr_t;
-
-typedef	union acp_hs_tx_ringbufsize {
-	struct {
-		unsigned int	hs_tx_ringbufsize :26;
-		unsigned int	:6;
-	} bits;
-	unsigned int	u32all;
-} acp_hs_tx_ringbufsize_t;
-
-typedef	union acp_hs_tx_linkpositioncntr {
-	struct {
-		unsigned int	hs_tx_linkpositioncntr :26;
-		unsigned int	:6;
-	} bits;
-	unsigned int    u32all;
-} acp_hs_tx_linkpositioncntr_t;
-
-typedef	union acp_hs_tx_fifoaddr {
-	struct {
-		unsigned int	hs_tx_fifoaddr :27;
-		unsigned int	:5;
-	} bits;
-	unsigned int	u32all;
-} acp_hs_tx_fifoaddr_t;
-
-typedef	union acp_hs_tx_fifosize {
-	struct {
-		unsigned int	hs_tx_fifosize :13;
-		unsigned int	:19;
-	} bits;
-	unsigned int	u32all;
-} acp_hs_tx_fifosize_t;
-
-typedef	union acp_hs_tx_dma_size {
-	struct {
-		unsigned int	hs_tx_dma_size :13;
-		unsigned int	:19;
-	} bits;
-	unsigned int	u32all;
-} acp_hs_tx_dma_size_t;
-
-typedef	union acp_hs_tx_linearpositioncntr_high {
-	struct {
-		unsigned int	hs_tx_linearpositioncntr_high :32;
-	} bits;
-	unsigned int	u32all;
-} acp_hs_tx_linearpositioncntr_high_t;
-
-typedef	union acp_hs_tx_linearpositioncntr_low {
-	struct {
-		unsigned int	hs_tx_linearpositioncntr_low :32;
-	} bits;
-	unsigned int	u32all;
-} acp_hs_tx_linearpositioncntr_low_t;
-
-typedef	union acp_hs_tx_intr_watermark_size {
-	struct {
-		unsigned int	hs_tx_intr_watermark_size :26;
-		unsigned int	:6;
-	} bits;
-	unsigned int	u32all;
-} acp_hs_tx_intr_watermark_size_t;
-
-typedef	union acp_i2stdm_ier {
-	struct {
-	unsigned int	i2stdm_ien:1;
-	unsigned int	:31;
-	} bits;
-unsigned int	u32all;
-} acp_i2stdm_ier_t;
-
-typedef	union acp_i2stdm_irer {
-	struct {
-	unsigned int	i2stdm_rx_en:1;
-	unsigned int	i2stdm_rx_protocol_mode:1;
-	unsigned int	i2stdm_rx_data_path_mode:1;
-	unsigned int	i2stdm_rx_samplen:3;
-	unsigned int	i2stdm_rx_status:1;
-	unsigned int	:25;
-
-	} bits;
-unsigned int	u32all;
-} acp_i2stdm_irer_t;
-
-typedef	union acp_i2stdm_iter {
-	struct {
-	unsigned int	i2stdm_txen:1;
-	unsigned int	i2stdm_tx_protocol_mode:1;
-	unsigned int	i2stdm_tx_data_path_mode:1;
-	unsigned int	i2stdm_tx_samp_len:3;
-	unsigned int	i2stdm_tx_status:1;
-	unsigned int	:25;
-	} bits;
-unsigned int	u32all;
-} acp_i2stdm_iter_t;
-
-typedef	union acp_bttdm_ier {
-	struct {
-	unsigned int	bttdm_ien:1;
-	unsigned int	:31;
-	} bits;
-unsigned int	u32all;
-} acp_bttdm_ier_t;
-
-typedef	union acp_bttdm_irer {
-	struct {
-	unsigned int	bttdm_rx_en:1;
-	unsigned int	bttdm_rx_protocol_mode:1;
-	unsigned int	bttdm_rx_data_path_mode:1;
-	unsigned int	bttdm_rx_samplen:3;
-	unsigned int	bttdm_rx_status:1;
-	unsigned int	:25;
-	} bits;
-unsigned int	u32all;
-} acp_bttdm_irer_t;
-
-typedef	union acp_bttdm_iter {
-	struct {
-	unsigned int	bttdm_txen:1;
-	unsigned int	bttdm_tx_protocol_mode:1;
-	unsigned int	bttdm_tx_data_path_mode:1;
-	unsigned int	bttdm_tx_samp_len:3;
-	unsigned int	bttdm_tx_status:1;
-	unsigned int	:25;
-	} bits;
-unsigned int	u32all;
-} acp_bttdm_iter_t;
-
-typedef	union acp_hstdm_ier {
-	struct {
-		unsigned int	hstdm_ien :1;
-		unsigned int	:31;
-	} bits;
-	unsigned int	u32all;
-} acp_hstdm_ier_t;
-
-typedef	union acp_hstdm_irer {
-	struct {
-		unsigned int	hstdm_rx_en :1;
-		unsigned int	hstdm_rx_protocol_mode :1;
-		unsigned int	hstdm_rx_data_path_mode :1;
-		unsigned int	hstdm_rx_samplen :3;
-		unsigned int	hstdm_rx_status :1;
-		unsigned int	:25;
-	} bits;
-	unsigned int	u32all;
-} acp_hstdm_irer_t;
-
-typedef	union acp_hstdm_iter {
-	struct {
-		unsigned int	hstdm_txen :1;
-		unsigned int	hstdm_tx_protocol_mode :1;
-		unsigned int	hstdm_tx_data_path_mode :1;
-		unsigned int	hstdm_tx_samp_len :3;
-		unsigned int	hstdm_tx_status :1;
-		unsigned int	:25;
-	} bits;
-	unsigned int	u32all;
-} acp_hstdm_iter_t;
-
-typedef	union acp_wov_pdm_dma_enable {
-	struct {
-	unsigned int	pdm_dma_en:1;
-	unsigned int	pdm_dma_en_status:1;
-	unsigned int	:30;
-	} bits;
-unsigned int	u32all;
-} acp_wov_pdm_dma_enable_t;
-
-typedef	union acp_wov_rx_ringbufaddr {
-	struct {
-	unsigned int	rx_ringbufaddr:27;
-	unsigned int	:5;
-	} bits;
-unsigned int	u32all;
-} acp_wov_rx_ringbufaddr_t;
-
-typedef	union acp_wov_rx_ringbufsize {
-	struct {
-	unsigned int	rx_ringbufsize:26;
-	unsigned int	:6;
-	} bits;
-unsigned int	u32all;
-} acp_wov_rx_ringbufsize_t;
-
-typedef	union acp_wov_rx_intr_watermark_size {
-	struct {
-	unsigned int	rx_intr_watermark_size:26;
-	unsigned int	:6;
-	} bits;
-unsigned int	u32all;
-} acp_wov_rx_intr_watermark_size_t;
-
-typedef	union acp_wov_pdm_no_of_channels {
-	struct {
-	unsigned int	pdm_no_of_channels:2;
-	unsigned int	:30;
-	} bits;
-unsigned int	u32all;
-} acp_wov_pdm_no_of_channels_t;
-
-typedef	union acp_wov_pdm_decimation_factor {
-	struct {
-	unsigned int	pdm_decimation_factor:2;
-	unsigned int	:30;
-	} bits;
-unsigned int	u32all;
-} acp_wov_pdm_decimation_factor_t;
-typedef	union acp_wov_misc_ctrl {
-	struct {
-	unsigned int	:3;
-	unsigned int	pcm_data_shift_ctrl:2;
-	unsigned int	:27;
-	} bits;
-unsigned int	u32all;
-} acp_wov_misc_ctrl_t;
-
-typedef	union acp_wov_clk_ctrl {
-	struct {
-	unsigned int	brm_clk_ctrl:4;
-	unsigned int	pdm_vad_clkdiv:2;
-	unsigned int	:26;
-	} bits;
-unsigned int	u32all;
-} acp_wov_clk_ctrl_t;
-
-typedef	union acp_srbm_cycle_sts {
-	struct {
-	unsigned int	srbm_clients_sts:1;
-	unsigned int	:7;
-
-	} bits;
-unsigned int	u32all;
-} acp_srbm_cycle_sts_t;
-
-#endif
-
diff --git a/src/platform/amd/vangogh/include/platform/drivers/interrupt.h b/src/platform/amd/vangogh/include/platform/drivers/interrupt.h
deleted file mode 100644
index 6197427cdf92..000000000000
--- a/src/platform/amd/vangogh/include/platform/drivers/interrupt.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- *
- * Copyright(c) 2023 AMD.All rights reserved.
- *
- * Author:      Basavaraj Hiregoudar <basavaraj.hiregoudar@amd.com>
- *              SaiSurya, Ch <saisurya.chakkaveeravenkatanaga@amd.com>
- */
-#ifdef __SOF_DRIVERS_INTERRUPT_H__
-
-#ifndef __PLATFORM_DRIVERS_INTERRUPT_H__
-#define __PLATFORM_DRIVERS_INTERRUPT_H__
-
-#include <rtos/bit.h>
-#include <sof/lib/cpu.h>
-#include <sof/lib/memory.h>
-
-#define PLATFORM_IRQ_HW_NUM		9
-
-#define PLATFORM_IRQ_FIRST_CHILD	5
-
-#define PLATFORM_IRQ_CHILDREN		32
-
-/* IRQ numbers - wrt Tensilica DSP */
-#define IRQ_NUM_SOFTWARE0	1	/* level 1 */
-
-#define IRQ_NUM_TIMER0		0	/* level 1 */
-
-#define IRQ_NUM_EXT_LEVEL3	3	/* level 1 */
-
-#define IRQ_NUM_TIMER1		6	/* level 2 */
-
-#define IRQ_NUM_EXT_LEVEL4	4	/* level 2 */
-
-#define IRQ_NUM_EXT_LEVEL5	5	/* level 3 */
-
-/* IRQ Masks */
-#define IRQ_MASK_SOFTWARE0	BIT(IRQ_NUM_SOFTWARE0)
-
-#define IRQ_MASK_TIMER0		BIT(IRQ_NUM_TIMER0)
-
-#define IRQ_MASK_TIMER1		BIT(IRQ_NUM_TIMER1)
-
-#define IRQ_MASK_EXT_LEVEL3	BIT(IRQ_NUM_EXT_LEVEL3)
-
-#define IRQ_MASK_EXT_LEVEL4	BIT(IRQ_NUM_EXT_LEVEL4)
-
-#define IRQ_MASK_EXT_LEVEL5	BIT(IRQ_NUM_EXT_LEVEL5)
-
-#define HOST_TO_DSP_INTR	0x1
-
-#define _XTSTR(x)   # x
-
-#define XTSTR(x)    _XTSTR(x)
-
-/* Enabling flag */
-#define INTERRUPT_ENABLE	1
-
-/* Clearing flag */
-#define INTERRUPT_CLEAR		0
-
-/* Disable flag */
-#define INTERRUPT_DISABLE	0
-
-/* brief Tensilica  Interrupt Levels. */
-typedef enum {
-	acp_interrupt_level_3 = 0,
-
-	acp_interrupt_level_4,
-
-	acp_interrupt_level_5,
-
-	acp_interrupt_level_nmi,
-
-	acp_interrupt_level_max
-} artos_interrupt_levels_t;
-
-/* brief Tensilica  timer control */
-typedef enum {
-	acp_timer_cntl_disable = 0,
-
-	acp_timer_cntl_oneshot,
-
-	acp_timer_cntl_periodic,
-
-	acp_timer_cntl_max
-} artos_timer_control_t;
-
-/* Disable Host to DSP interrupt */
-void acp_dsp_sw_intr_disable(void);
-
-void acp_intr_route(void);
-
-void acp_dsp_to_host_intr_trig(void);
-
-void acp_ack_intr_from_host(void);
-
-void acp_dsp_sw_intr_enable(void);
-
-void acp_intr_enable(void);
-
-void acp_intr_disable(void);
-
-#endif /* __PLATFORM_DRIVERS_INTERRUPT_H__ */
-
-#else
-
-#error "This file shouldn't be included from outside of sof/drivers/interrupt.h"
-
-#endif /* __SOF_DRIVERS_INTERRUPT_H__ */
diff --git a/src/platform/amd/vangogh/include/platform/fw_scratch_mem.h b/src/platform/amd/vangogh/include/platform/fw_scratch_mem.h
deleted file mode 100644
index 9890110540ef..000000000000
--- a/src/platform/amd/vangogh/include/platform/fw_scratch_mem.h
+++ /dev/null
@@ -1,121 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- *
- *  Copyright(c) 2023 AMD. All rights reserved.
- *
- *  Author: Basavaraj Hiregoudar <basavaraj.hiregoudar@amd.com>
- *          SaiSurya, Ch <saisurya.chakkaveeravenkatanaga@amd.com>
- */
-#ifndef __EXT_SCRATCH_MEM_H__
-#define __EXT_SCRATCH_MEM_H__
-
-#include <sof/lib/mailbox.h>
-
-/* MAX number of DMA descriptors */
-#define MAX_NUM_DMA_DESC_DSCR	64
-#define SCRATCH_REG_OFFSET	0x1250000
-
-typedef struct acp_atu_grp_pte {
-	uint32_t low_part;
-	uint32_t high_part;
-} __attribute__((packed, aligned(4))) acp_atu_grp_pte_t;
-
-typedef union acp_cfg_dma_trns_cnt {
-	struct{
-		uint32_t  trns_cnt : 19;
-		uint32_t  reserved : 12;
-		uint32_t  ioc : 1;
-	} bits;
-	unsigned int    u32all;
-} __attribute__((packed, aligned(4))) acp_cfg_dma_trns_cnt_t;
-
-typedef struct acp_config_dma_descriptor {
-	uint32_t	src_addr;
-	uint32_t	dest_addr;
-	acp_cfg_dma_trns_cnt_t	trns_cnt;
-	uint32_t	reserved;
-} __attribute__((packed, aligned(4))) acp_cfg_dma_descriptor_t;
-
-typedef struct acp_config_dma_misc {
-	uint32_t	channelstatus;
-	uint32_t	channel;
-	uint32_t	flag;
-} __attribute__((packed, aligned(4))) acp_cfg_dma_misc_t;
-
-typedef struct  acp_scratch_memory_config {
-	/* ACP out box buffer */
-	uint8_t				acp_outbox_buffer[MAILBOX_DSPBOX_SIZE];
-
-	/* ACP in box buffer */
-	uint8_t				acp_inbox_buffer[MAILBOX_HOSTBOX_SIZE];
-
-	/* ACP debug box buffer */
-	uint8_t				acp_debug_buffer[MAILBOX_DEBUG_SIZE];
-
-	/* ACP exception box buffer */
-	uint8_t				acp_except_buffer[MAILBOX_EXCEPTION_SIZE];
-
-	/* ACP stream buffer */
-	uint8_t				acp_stream_buffer[MAILBOX_STREAM_SIZE];
-
-	/* ACP trace buffer */
-	uint8_t				acp_trace_buffer[MAILBOX_TRACE_SIZE];
-
-	/* Host msg write flag */
-	uint32_t			acp_host_msg_write;
-
-	/* Host ack flag */
-	uint32_t			acp_host_ack_write;
-
-	/* Dsp msg write flag */
-	uint32_t			acp_dsp_msg_write;
-
-	/* Dsp ack flag */
-	uint32_t			acp_dsp_ack_write;
-
-	/* ACP pte1 table */
-	acp_atu_grp_pte_t		acp_atugrp1_pte[16];
-
-	/* ACP pte2 table */
-	acp_atu_grp_pte_t		acp_atugrp2_pte[16];
-
-	/* ACP pte3 table */
-	acp_atu_grp_pte_t		acp_atugrp3_pte[16];
-
-	/* ACP pte4 table */
-	acp_atu_grp_pte_t		acp_atugrp4_pte[16];
-
-	/* ACP pte5 table */
-	acp_atu_grp_pte_t		acp_atugrp5_pte[16];
-
-	/* ACP pte6 table */
-	acp_atu_grp_pte_t		acp_atugrp6_pte[16];
-
-	/* ACP pte7 table */
-	acp_atu_grp_pte_t		acp_atugrp7_pte[16];
-
-	/* ACP pte8 table */
-	acp_atu_grp_pte_t		acp_atugrp8_pte[16];
-
-	/* ACP DMA Descriptor */
-	acp_cfg_dma_descriptor_t	acp_cfg_dma_descriptor[MAX_NUM_DMA_DESC_DSCR];
-
-	/* Stream physical offset  */
-	uint32_t			phy_offset[8];
-
-	/* Stream system memeory size */
-	uint32_t			syst_buff_size[8];
-
-	/* Fifo buffers are not part of scratch memory on Vangogh */
-	/* Added fifo members to align with Driver structure */
-	/* ACP transmit fifo buffers */
-	uint8_t			acp_transmit_fifo_buffer[768] __attribute__((aligned(64)));
-	uint8_t			acp_transmit_hs_fifo_buffer[768] __attribute__((aligned(64)));
-
-	/* ACP receive fifo buffer */
-	uint8_t			acp_receive_fifo_buffer[768] __attribute__((aligned(64)));
-
-	uint32_t			reserve[];
-} __attribute__((packed, aligned(4))) acp_scratch_mem_config_t;
-
-#endif /* __EXT_SCRATCH_MEM_H__ */
-
diff --git a/src/platform/amd/vangogh/include/platform/lib/memory.h b/src/platform/amd/vangogh/include/platform/lib/memory.h
deleted file mode 100644
index a9f42b597dd9..000000000000
--- a/src/platform/amd/vangogh/include/platform/lib/memory.h
+++ /dev/null
@@ -1,163 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- *
- * Copyright(c) 2023 AMD.All rights reserved.
- *
- * Author:      Basavaraj Hiregoudar <basavaraj.hiregoudar@amd.com>
- *              SaiSurya, Ch <saisurya.chakkaveeravenkatanaga@amd.com>
- */
-#ifdef __SOF_LIB_MEMORY_H__
-
-#ifndef __PLATFORM_LIB_MEMORY_H__
-#define __PLATFORM_LIB_MEMORY_H__
-
-#include <rtos/cache.h>
-#include <platform/chip_offset_byte.h>
-
-/* data cache line alignment */
-#define PLATFORM_DCACHE_ALIGN	64
-
-/* physical DSP addresses */
-#define IRAM_BASE	0x20000000
-#define IRAM_SIZE	0x40000
-
-#define DRAM0_BASE	0xE0000000
-#define DRAM0_SIZE	0x80000
-#define DRAM1_SIZE	0x80000
-
-#define DMA0_BASE	PU_REGISTER_BASE
-#define DMA0_SIZE	0x4
-
-/* DAI DMA register base address */
-#define DAI_BASE		(PU_REGISTER_BASE + ACP_I2S_RX_RINGBUFADDR)
-#define DAI_SIZE		0x4
-#define BT_TX_FIFO_OFFST	(ACP_BT_TX_FIFOADDR - ACP_I2S_RX_RINGBUFADDR)
-#define BT_RX_FIFO_OFFST	(ACP_BT_RX_FIFOADDR - ACP_I2S_RX_RINGBUFADDR)
-
-#define HS_TX_FIFO_OFFST        (ACP_HS_TX_FIFOADDR - ACP_I2S_RX_RINGBUFADDR)
-#define HS_RX_FIFO_OFFST        (ACP_HS_RX_FIFOADDR - ACP_I2S_RX_RINGBUFADDR)
-
-#define UUID_ENTRY_ELF_BASE     0x1FFFA000
-#define UUID_ENTRY_ELF_SIZE     0x6000
-
-/* Log buffer  base need to be updated properly, these are used in linker scripts */
-#define LOG_ENTRY_ELF_BASE	0x20000000
-#define LOG_ENTRY_ELF_SIZE	0x2000000
-
-#define EXT_MANIFEST_ELF_BASE   (LOG_ENTRY_ELF_BASE + LOG_ENTRY_ELF_SIZE)
-#define EXT_MANIFEST_ELF_SIZE   0x2000000
-
-/* Stack configuration */
-#define SOF_STACK_SIZE		0x1000
-#define SOF_STACK_TOTAL_SIZE	SOF_STACK_SIZE
-#define SOF_STACK_END		(DRAM0_BASE + DRAM0_SIZE)
-#define SOF_STACK_BASE		(SOF_STACK_END + SOF_STACK_SIZE)
-
-/* Mailbox configuration */
-#define SRAM_OUTBOX_BASE		0x9FF00000
-#define SRAM_OUTBOX_SIZE		0x400
-#define SRAM_OUTBOX_OFFSET		0
-
-#define SRAM_INBOX_BASE			(SRAM_OUTBOX_BASE + SRAM_OUTBOX_SIZE)
-#define SRAM_INBOX_SIZE			0x400
-#define SRAM_INBOX_OFFSET		SRAM_OUTBOX_SIZE
-
-#define SRAM_DEBUG_BASE			(SRAM_INBOX_BASE + SRAM_INBOX_SIZE)
-#define SRAM_DEBUG_SIZE			0x400
-#define SRAM_DEBUG_OFFSET		(SRAM_INBOX_OFFSET + SRAM_INBOX_SIZE)
-
-#define SRAM_EXCEPT_BASE		(SRAM_DEBUG_BASE + SRAM_DEBUG_SIZE)
-#define SRAM_EXCEPT_SIZE		0x400
-#define SRAM_EXCEPT_OFFSET		(SRAM_DEBUG_OFFSET + SRAM_DEBUG_SIZE)
-
-#define SRAM_STREAM_BASE		(SRAM_EXCEPT_BASE + SRAM_EXCEPT_SIZE)
-#define SRAM_STREAM_SIZE		0x400
-#define SRAM_STREAM_OFFSET		(SRAM_EXCEPT_OFFSET + SRAM_EXCEPT_SIZE)
-
-#define SRAM_TRACE_BASE			(SRAM_STREAM_BASE + SRAM_STREAM_SIZE)
-#define SRAM_TRACE_SIZE			0x400
-#define SRAM_TRACE_OFFSET		(SRAM_STREAM_OFFSET + SRAM_STREAM_SIZE)
-#define SOF_MAILBOX_SIZE		(SRAM_INBOX_SIZE + SRAM_OUTBOX_SIZE \
-					+ SRAM_DEBUG_SIZE + SRAM_EXCEPT_SIZE \
-					+ SRAM_STREAM_SIZE + SRAM_TRACE_SIZE)
-
-/* Heap section sizes for module pool */
-#define HEAP_RT_COUNT8		0
-#define HEAP_RT_COUNT16		48
-#define HEAP_RT_COUNT32		48
-#define HEAP_RT_COUNT64		32
-#define HEAP_RT_COUNT128	48
-#define HEAP_RT_COUNT256	32
-#define HEAP_RT_COUNT512	4
-#define HEAP_RT_COUNT1024	13
-#define HEAP_RT_COUNT2048	24
-
-/* Heap section sizes for system runtime heap */
-#define HEAP_SYS_RT_COUNT64	64
-#define HEAP_SYS_RT_COUNT512	22 /*vangogh-arch*/
-#define HEAP_SYS_RT_COUNT1024	30
-
-/* Heap configuration */
-#define HEAP_SYSTEM_BASE	(SOF_STACK_BASE + SOF_STACK_SIZE)
-#define HEAP_SYSTEM_SIZE	0x14400
-#define HEAP_SYSTEM_0_BASE	HEAP_SYSTEM_BASE
-#define HEAP_SYS_RUNTIME_BASE	(HEAP_SYSTEM_BASE + HEAP_SYSTEM_SIZE)
-#define HEAP_SYS_RUNTIME_SIZE	(HEAP_SYS_RT_COUNT64 * 64 + HEAP_SYS_RT_COUNT512 * 512 + \
-				HEAP_SYS_RT_COUNT1024 * 1024)
-
-#define HEAP_RUNTIME_BASE	(HEAP_SYS_RUNTIME_BASE + HEAP_SYS_RUNTIME_SIZE)
-#define HEAP_RUNTIME_SIZE \
-				(HEAP_RT_COUNT8 * 8 + HEAP_RT_COUNT16 * 16 + \
-				HEAP_RT_COUNT32 * 32 + HEAP_RT_COUNT64 * 64 + \
-				HEAP_RT_COUNT128 * 128 + HEAP_RT_COUNT256 * 256 + \
-				HEAP_RT_COUNT512 * 512 + HEAP_RT_COUNT1024 * 1024 + \
-				HEAP_RT_COUNT2048 * 2048)
-
-#define HEAP_BUFFER_BASE	(HEAP_RUNTIME_BASE + HEAP_RUNTIME_SIZE)
-#define HEAP_BUFFER_SIZE	(0x15400)
-#define HEAP_BUFFER_BLOCK_SIZE	0x180
-#define HEAP_BUFFER_COUNT	(HEAP_BUFFER_SIZE / HEAP_BUFFER_BLOCK_SIZE)
-
-#define PLATFORM_HEAP_SYSTEM            1
-#define PLATFORM_HEAP_SYSTEM_RUNTIME    1
-#define PLATFORM_HEAP_RUNTIME           1
-#define PLATFORM_HEAP_BUFFER		1
-
-/* Vector and literal sizes - not in core-isa.h */
-#define SOF_MEM_VECT_LIT_SIZE		0x7
-#define SOF_MEM_VECT_TEXT_SIZE		0x37
-#define SOF_MEM_VECT_SIZE		(SOF_MEM_VECT_TEXT_SIZE + SOF_MEM_VECT_LIT_SIZE)
-
-#define SOF_MEM_RESET_TEXT_SIZE		0x400
-#define SOF_MEM_RESET_LIT_SIZE		0x8
-#define SOF_MEM_VECBASE_LIT_SIZE	0x178
-#define SOF_MEM_WIN_TEXT_SIZE		0x178
-
-#define SOF_MEM_RO_SIZE			0x8
-
-#define uncache_to_cache(address)	address
-#define cache_to_uncache(address)	address
-#define is_uncached(address)			0
-
-#define HEAP_BUF_ALIGNMENT		PLATFORM_DCACHE_ALIGN
-
-/* brief EDF task's default stack size in bytes */
-#define PLATFORM_TASK_DEFAULT_STACK_SIZE        3072
-
-#if !defined(__ASSEMBLER__) && !defined(LINKER)
-struct sof;
-
-void platform_init_memmap(struct sof *sof);
-
-static inline void *platform_rfree_prepare(void *ptr)
-{
-	return ptr;
-}
-#endif
-
-#endif /* __PLATFORM_LIB_MEMORY_H__ */
-
-#else
-
-#error "This file shouldn't be included from outside of sof/lib/memory.h"
-
-#endif /* __SOF_LIB_MEMORY_H__ */
diff --git a/src/platform/amd/vangogh/include/platform/platform.h b/src/platform/amd/vangogh/include/platform/platform.h
deleted file mode 100644
index efdda9d6b446..000000000000
--- a/src/platform/amd/vangogh/include/platform/platform.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- *
- * Copyright(c) 2023 AMD.All rights reserved.
- *
- * Author:	Basavaraj Hiregoudar <basavaraj.hiregoudar@amd.com>
- *		SaiSurya, Ch <saisurya.chakkaveeravenkatanaga@amd.com>
- */
-#ifdef __SOF_PLATFORM_H__
-
-#ifndef __PLATFORM_PLATFORM_H__
-#define __PLATFORM_PLATFORM_H__
-
-#if !defined(__ASSEMBLER__) && !defined(LINKER)
-
-#include <rtos/interrupt.h>
-#include <rtos/clk.h>
-#include <sof/lib/mailbox.h>
-#include <stddef.h>
-#include <stdint.h>
-#include <platform/fw_scratch_mem.h>
-#include <platform/chip_registers.h>
-
-struct ll_schedule_domain;
-struct timer;
-
-#define PLATFORM_DEFAULT_CLOCK CLK_CPU(0)
-
-/* IPC Interrupt */
-#define PLATFORM_IPC_INTERRUPT		IRQ_EXT_IPC_LEVEL_3
-#define PLATFORM_IPC_INTERRUPT_NAME	NULL
-
-/* Host page size */
-#define HOST_PAGE_SIZE                  65536
-
-/* pipeline IRQ */
-#define PLATFORM_SCHEDULE_IRQ		IRQ_NUM_SOFTWARE0
-#define PLATFORM_SCHEDULE_IRQ_NAME	NULL
-
-/* Platform stream capabilities */
-#define PLATFORM_MAX_CHANNELS	4
-#define PLATFORM_MAX_STREAMS	5
-
-/* local buffer size of DMA tracing */
-#define DMA_TRACE_LOCAL_SIZE	8192
-
-/* trace bytes flushed during panic */
-#define DMA_FLUSH_TRACE_SIZE	(MAILBOX_TRACE_SIZE >> 2)
-
-/* the interval of DMA trace copying */
-#define DMA_TRACE_PERIOD		500000
-
-/*
- * the interval of reschedule DMA trace copying in special case like half
- * fullness of local DMA trace buffer
- */
-#define DMA_TRACE_RESCHEDULE_TIME	100
-
-/* DSP default delay in cycles */
-#define PLATFORM_DEFAULT_DELAY	12
-
-/* default dma trace channel */
-#define DMA_TRACE_CHANNEL	7
-
-/* debug offset */
-#define ACP_SOF_FW_STATUS	0
-
-/* Platform defined panic code */
-static inline void platform_panic(uint32_t p)
-{
-	acp_sw_intr_trig_t  sw_intr_trig;
-
-	mailbox_sw_reg_write(ACP_SOF_FW_STATUS, p);
-	/* Read the Software Interrupt controller register and update */
-	sw_intr_trig = (acp_sw_intr_trig_t)io_reg_read(PU_REGISTER_BASE + ACP_SW_INTR_TRIG);
-	/* Configures the trigger bit in ACP_DSP_SW_INTR_TRIG register */
-	sw_intr_trig.bits.trig_dsp0_to_host_intr = INTERRUPT_ENABLE;
-	/* Write the Software Interrupt trigger register */
-	io_reg_write((PU_REGISTER_BASE + ACP_SW_INTR_TRIG), sw_intr_trig.u32all);
-}
-
-/*
- * brief Platform specific CPU entering idle.
- * May be power-optimized using platform specific capabilities.
- * @param level Interrupt level.
- */
-void platform_wait_for_interrupt(int level);
-
-extern intptr_t _module_init_start;
-extern intptr_t _module_init_end;
-#endif
-
-#endif /* __PLATFORM_PLATFORM_H__ */
-
-#else
-
-#error "This file shouldn't be included from outside of sof/platform.h"
-
-#endif /* __SOF_PLATFORM_H__ */
diff --git a/src/platform/amd/vangogh/lib/CMakeLists.txt b/src/platform/amd/vangogh/lib/CMakeLists.txt
deleted file mode 100644
index 271a099cc6a9..000000000000
--- a/src/platform/amd/vangogh/lib/CMakeLists.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-
-add_local_sources(sof
-	clk.c
-	dai.c
-	dma.c
-	memory.c
-)
diff --git a/src/platform/amd/vangogh/lib/clk.c b/src/platform/amd/vangogh/lib/clk.c
deleted file mode 100644
index b91472a739ce..000000000000
--- a/src/platform/amd/vangogh/lib/clk.c
+++ /dev/null
@@ -1,145 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-//
-// Copyright(c) 2023 AMD. All rights reserved.
-//
-// Author: Basavaraj Hiregoudar<basavaraj.hiregoudar@amd.com>
-//	   SaiSurya, Ch <saisurya.chakkaveeravenkatanaga@amd.com>
-
-#include <sof/common.h>
-#include <rtos/clk.h>
-#include <sof/lib/cpu.h>
-#include <sof/lib/memory.h>
-#include <sof/lib/notifier.h>
-#include <rtos/sof.h>
-#include <rtos/spinlock.h>
-#include <platform/chip_registers.h>
-
-const struct freq_table platform_cpu_freq[] = {
-	{600000000, 600000 },
-};
-
-STATIC_ASSERT(NUM_CPU_FREQ == ARRAY_SIZE(platform_cpu_freq),
-	      invalid_number_of_cpu_frequencies);
-
-static struct clock_info platform_clocks_info[NUM_CLOCKS];
-
-static int acp_reg_read_via_smn(uint32_t reg_offset,
-				uint32_t size)
-{
-	uint32_t reg_value;
-	uint32_t delay_cnt = 10000;
-	uint32_t smn_client_base_addr = (reg_offset >> 10);
-	uint32_t region_start_addr = (smn_client_base_addr << 10);
-	uint32_t apertureid = ((reg_offset >> 20) & 0xFFF);
-	acp_srbm_cycle_sts_t  acp_srbm_cycle_sts;
-
-	/* Configuring the MP1 Aperture Id in SRB_client_config register */
-	io_reg_write((PU_REGISTER_BASE + ACP_SRBM_CLIENT_CONFIG), apertureid);
-	/* Configuring the base address of MP1 */
-	io_reg_write((PU_REGISTER_BASE + ACP_SRBM_CLIENT_BASE_ADDR), smn_client_base_addr);
-	/* dummy read to the to the address offset 0x3400 */
-	/* Master config offset to access register outside of ACP */
-	reg_value = (uint32_t)io_reg_read(PU_REGISTER_BASE +
-					 (ACP_MASTER_REG_ACCESS_ADDRESS + reg_offset -
-					  region_start_addr + ACP_FIRST_REG_OFFSET));
-	if (reg_value)
-		reg_value = 0;
-	/* reading status register to check above read request is completed or not */
-	acp_srbm_cycle_sts = (acp_srbm_cycle_sts_t)io_reg_read(PU_REGISTER_BASE +
-							       ACP_SRBM_CYCLE_STS);
-	/* Waiting for status to be set to '0' */
-	while (delay_cnt > 0) {
-		if (!acp_srbm_cycle_sts.bits.srbm_clients_sts) {
-			/* when status is '0' from above read the data from data register */
-			return (uint32_t)io_reg_read(PU_REGISTER_BASE + ACP_SRBM_CLIENT_RDDATA);
-		}
-		acp_srbm_cycle_sts = (acp_srbm_cycle_sts_t)io_reg_read(PU_REGISTER_BASE +
-									ACP_SRBM_CYCLE_STS);
-		delay_cnt--;
-	}
-	return -1;
-}
-
-static void acp_reg_write_via_smn(uint32_t reg_offset,
-				  uint32_t value, uint32_t size)
-{
-	uint32_t	delay_cnt = 10000;
-	uint32_t        smn_client_base_addr    = (reg_offset >> 10);
-	uint32_t        region_start_addr = (smn_client_base_addr << 10);
-	uint32_t	apertureid = ((reg_offset >> 20) & 0xFFF);
-	acp_srbm_cycle_sts_t      acp_srbm_cycle_sts;
-
-	/* Configuring the MP1 Aperture Id in SRB_client_config register */
-	io_reg_write((PU_REGISTER_BASE + ACP_SRBM_CLIENT_CONFIG), apertureid);
-	/* Configuring the base address of MP1 */
-	io_reg_write((PU_REGISTER_BASE + ACP_SRBM_CLIENT_BASE_ADDR), smn_client_base_addr);
-	/* write to the address offset 0x3400
-	 *  Master config offset to access register outside of ACP
-	 */
-	io_reg_write((PU_REGISTER_BASE +
-		(ACP_MASTER_REG_ACCESS_ADDRESS + reg_offset - region_start_addr +
-		ACP_FIRST_REG_OFFSET)), value);
-	/* reading status register to check above read request is completed or not */
-	acp_srbm_cycle_sts =
-		(acp_srbm_cycle_sts_t)io_reg_read(PU_REGISTER_BASE + ACP_SRBM_CYCLE_STS);
-	/* Waiting for status to be set to '0' */
-	while (delay_cnt > 0) {
-		acp_srbm_cycle_sts = (acp_srbm_cycle_sts_t)io_reg_read(PU_REGISTER_BASE +
-								ACP_SRBM_CYCLE_STS);
-		if (!acp_srbm_cycle_sts.bits.srbm_clients_sts)
-			return;
-		delay_cnt--;
-	}
-}
-
-static void  get_response_from_smu(void)
-{
-	uint32_t ret_value;
-	uint32_t count = 0;
-
-	do {
-		ret_value = acp_reg_read_via_smn(MP1_SMN_C2PMSG_93, sizeof(int));
-		if (count > 0x007fffff)
-			count = 0;
-		count++;
-	} while (ret_value == 0);
-}
-
-void acp_change_clock_notify(uint32_t	clock_freq)
-{
-	/* converting Hz to Mhz */
-	clock_freq = (clock_freq / 1000000);
-	/* Writing response zero to the response register
-	 * so that it cab reset to '0' for further response
-	 */
-	acp_reg_write_via_smn(MP1_SMN_C2PMSG_93,
-			      0, sizeof(int));
-	/* Writing clock frequency value in Mhz in the Argument register */
-	acp_reg_write_via_smn(MP1_SMN_C2PMSG_85,
-			      clock_freq, sizeof(int));
-	/* Writing Message to message register */
-	/* Writing Aclk change message to message register */
-	acp_reg_write_via_smn(MP1_SMN_C2PMSG_69,
-			      ACP_SMU_MSG_SET_ACLK, sizeof(int));
-	/* Waiting for SMU response */
-	get_response_from_smu();
-}
-
-void platform_clock_init(struct sof *sof)
-{
-	int i = 0;
-
-	sof->clocks = platform_clocks_info;
-	for (i = 0; i < CONFIG_CORE_COUNT; i++) {
-		sof->clocks[i] = (struct clock_info) {
-			.freqs_num = NUM_CPU_FREQ,
-			.freqs = platform_cpu_freq,
-			.default_freq_idx = CPU_DEFAULT_IDX,
-			.current_freq_idx = CPU_DEFAULT_IDX,
-			.notification_id = NOTIFIER_ID_CPU_FREQ,
-			.notification_mask = NOTIFIER_TARGET_CORE_MASK(i),
-			.set_freq = NULL,
-		};
-	}
-	acp_change_clock_notify(600000000);
-}
diff --git a/src/platform/amd/vangogh/lib/dai.c b/src/platform/amd/vangogh/lib/dai.c
deleted file mode 100644
index d47eee304ab4..000000000000
--- a/src/platform/amd/vangogh/lib/dai.c
+++ /dev/null
@@ -1,115 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-//
-//Copyright(c) 2023 AMD. All rights reserved.
-//
-//Author:       Basavaraj Hiregoudar <basavaraj.hiregoudar@amd.com>
-//              SaiSurya, Ch <saisurya.chakkaveeravenkatanaga@amd.com>
-
-#include <sof/common.h>
-#include <sof/drivers/acp_dai_dma.h>
-#include <sof/lib/dai.h>
-#include <sof/lib/memory.h>
-#include <rtos/sof.h>
-#include <rtos/spinlock.h>
-#include <ipc/dai.h>
-#include <ipc/stream.h>
-
-static struct dai hsdai[] = {
-	{
-		.index = 1,
-		.plat_data = {
-			.base = DAI_BASE,
-			.fifo[SOF_IPC_STREAM_PLAYBACK] = {
-			.offset         = DAI_BASE + HS_TX_FIFO_OFFST,
-			.depth          = 8,
-			.handshake      = 1,
-			},
-		},
-		.drv = &acp_hsdai_driver,
-	},
-};
-
-static struct dai spdai[] = {
-	{
-		.index = 0,
-		.plat_data = {
-			.base = DAI_BASE,
-			.fifo[SOF_IPC_STREAM_PLAYBACK] = {
-				.offset         = DAI_BASE + BT_TX_FIFO_OFFST,
-				.depth          = 8,
-				.handshake      = 5,
-			},
-			.fifo[SOF_IPC_STREAM_CAPTURE] = {
-				.offset         = DAI_BASE + BT_RX_FIFO_OFFST,
-				.depth          = 8,
-				.handshake      = 4,
-			},
-		},
-		.drv = &acp_spdai_driver,
-	}
-};
-
-#ifdef ACP_BT_ENABLE
-static struct dai btdai[] = {
-	{
-		.index = 0,
-		.plat_data = {
-			.base = DAI_BASE,
-			.fifo[SOF_IPC_STREAM_PLAYBACK] = {
-				.offset		= DAI_BASE + BT_TX_FIFO_OFFST,
-				.depth		= 8,
-				.handshake	= 3,
-			},
-			.fifo[SOF_IPC_STREAM_CAPTURE] = {
-				.offset		= DAI_BASE + BT_RX_FIFO_OFFST,
-				.depth		= 8,
-				.handshake	= 2,
-			},
-		},
-		.drv = &acp_btdai_driver,
-	},
-};
-#endif
-
-const struct dai_type_info dti[] = {
-	{
-		.type		= SOF_DAI_AMD_HS,
-		.dai_array	= hsdai,
-		.num_dais	= ARRAY_SIZE(hsdai)
-	},
-	{
-		.type		= SOF_DAI_AMD_SP,
-		.dai_array	= spdai,
-		.num_dais	= ARRAY_SIZE(spdai)
-	},
-#ifdef ACP_BT_ENABLE
-	{
-		.type = SOF_DAI_AMD_BT,
-		.dai_array = btdai,
-		.num_dais = ARRAY_SIZE(btdai)
-	},
-#endif
-};
-
-const struct dai_info lib_dai = {
-	.dai_type_array = dti,
-	.num_dai_types = ARRAY_SIZE(dti)
-};
-
-int dai_init(struct sof *sof)
-{
-	int i;
-
-	/* initialize spin locks early to enable ref counting */
-	for (i = 0; i < ARRAY_SIZE(hsdai); i++)
-		k_spinlock_init(&hsdai[i].lock);
-	for (i = 0; i < ARRAY_SIZE(spdai); i++)
-		k_spinlock_init(&spdai[i].lock);
-#ifdef ACP_BT_ENABLE
-	/* initialize spin locks early to enable ref counting */
-	for (i = 0; i < ARRAY_SIZE(btdai); i++)
-		k_spinlock_init(&btdai[i].lock);
-#endif
-	sof->dai_info = &lib_dai;
-	return 0;
-}
diff --git a/src/platform/amd/vangogh/lib/dma.c b/src/platform/amd/vangogh/lib/dma.c
deleted file mode 100644
index 3a16b1d1ba65..000000000000
--- a/src/platform/amd/vangogh/lib/dma.c
+++ /dev/null
@@ -1,107 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-//
-//Copyright(c) 2023 AMD. All rights reserved.
-//
-//Author:       Basavaraj Hiregoudar <basavaraj.hiregoudar@amd.com>
-//              SaiSurya, Ch <saisurya.chakkaveeravenkatanaga@amd.com>
-
-#include <sof/common.h>
-#include <platform/fw_scratch_mem.h>
-#include <sof/drivers/acp_dai_dma.h>
-#include <rtos/interrupt.h>
-#include <sof/lib/dma.h>
-#include <sof/lib/memory.h>
-#include <rtos/sof.h>
-#include <rtos/spinlock.h>
-
-#define ACP_ADDR_MASK	0x9DEB0000
-
-extern struct dma_ops acp_dma_ops;
-#ifdef ACP_BT_ENABLE
-extern struct dma_ops acp_dai_bt_dma_ops;
-#endif
-extern struct dma_ops acp_dai_sp_dma_ops;
-extern struct dma_ops acp_dai_hs_dma_ops;
-
-struct dma dma[PLATFORM_NUM_DMACS] = {
-{
-	.plat_data = {
-		.id		= DMA_ID_DMA0,
-		.dir		= DMA_DIR_LMEM_TO_HMEM | DMA_DIR_HMEM_TO_LMEM,
-		.devs		= DMA_DEV_HOST,
-		.base		= DMA0_BASE,
-		.chan_size	= DMA0_SIZE,
-		.channels	= 8,
-		.irq		= IRQ_NUM_EXT_LEVEL5,
-	},
-	.ops	= &acp_dma_ops,
-},
-{
-	.plat_data = {
-		.id		= DMA_ID_DAI_HS,
-		.dir		= DMA_DIR_DEV_TO_MEM | DMA_DIR_MEM_TO_DEV,
-		.devs		= DMA_DEV_HS,
-		.caps		= DMA_CAP_HS,
-		.base		= DMA0_BASE,
-		.chan_size	= DMA0_SIZE,
-		.channels	= 8,
-		.irq		= IRQ_NUM_EXT_LEVEL5,
-		.irq_name	= "irqsteer1",
-	},
-	.ops = &acp_dai_hs_dma_ops,
-},
-{
-	.plat_data = {
-		.id		= DMA_ID_DAI_SP,
-		.dir		= DMA_DIR_DEV_TO_MEM | DMA_DIR_MEM_TO_DEV,
-		.devs		= DMA_DEV_SP,
-		.caps		= DMA_CAP_SP,
-		.base		= DMA0_BASE,
-		.chan_size	= DMA0_SIZE,
-		.channels	= 8,
-		.irq		= IRQ_NUM_EXT_LEVEL5,
-		.irq_name	= "irqsteer1",
-	},
-	.ops	= &acp_dai_sp_dma_ops,
-},
-
-#ifdef ACP_BT_ENABLE
-{
-	.plat_data = {
-		.id             = DMA_ID_DAI,
-		.dir            = DMA_DIR_DEV_TO_MEM | DMA_DIR_MEM_TO_DEV,
-		.devs           = DMA_DEV_BT,
-		.caps           = DMA_CAP_BT,
-		.base           = DMA0_BASE,
-		.chan_size      = DMA0_SIZE,
-		.channels       = 8,
-		.irq            = IRQ_NUM_EXT_LEVEL5,
-	},
-	.ops    = &acp_dai_bt_dma_ops,
-},
-#endif
-};
-
-const struct dma_info lib_dma = {
-	.dma_array = dma,
-	.num_dmas = ARRAY_SIZE(dma)
-};
-
-int acp_dma_init(struct sof *sof)
-{
-	int i;
-	uint32_t descr_base;
-	volatile acp_scratch_mem_config_t *pscratch_mem_cfg =
-		(volatile acp_scratch_mem_config_t *)(PU_SCRATCH_REG_BASE + SCRATCH_REG_OFFSET);
-	descr_base = (uint32_t)(&pscratch_mem_cfg->acp_cfg_dma_descriptor);
-	descr_base = (descr_base - ACP_ADDR_MASK);
-	/* configure dma descriptor base addr */
-	io_reg_write((PU_REGISTER_BASE + ACP_DMA_DESC_BASE_ADDR), descr_base);
-	io_reg_write((PU_REGISTER_BASE + ACP_DMA_DESC_MAX_NUM_DSCR), 0x1);
-
-	/* early lock initialization for ref counting */
-	for (i = 0; i < ARRAY_SIZE(dma); i++)
-		k_spinlock_init(&dma[i].lock);
-	sof->dma_info = &lib_dma;
-	return 0;
-}
diff --git a/src/platform/amd/vangogh/lib/memory.c b/src/platform/amd/vangogh/lib/memory.c
deleted file mode 100644
index 566175154721..000000000000
--- a/src/platform/amd/vangogh/lib/memory.c
+++ /dev/null
@@ -1,96 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-//
-// Copyright 2023 AMD. All rights reserved.
-//
-// Author:Basavaraj Hiregoudar <basavaraj.hiregoudar@amd.com>
-//	  SaiSurya, Ch <saisurya.chakkaveeravenkatanaga@amd.com>
-
-#include <sof/common.h>
-#include <sof/lib/mm_heap.h>
-#include <sof/lib/memory.h>
-#include <sof/platform.h>
-#include <rtos/sof.h>
-#include <ipc/topology.h>
-
-/* Heap blocks for system runtime */
-static struct block_hdr sys_rt_block64[HEAP_SYS_RT_COUNT64];
-static struct block_hdr sys_rt_block512[HEAP_SYS_RT_COUNT512];
-static struct block_hdr sys_rt_block1024[HEAP_SYS_RT_COUNT1024];
-
-/* Heap memory for system runtime */
-static struct block_map sys_rt_heap_map[] = {
-	BLOCK_DEF(64, HEAP_SYS_RT_COUNT64, sys_rt_block64),
-	BLOCK_DEF(512, HEAP_SYS_RT_COUNT512, sys_rt_block512),
-	BLOCK_DEF(1024, HEAP_SYS_RT_COUNT1024, sys_rt_block1024),
-};
-
-/* Heap blocks for modules */
-static struct block_hdr mod_block16[HEAP_RT_COUNT16];
-static struct block_hdr mod_block32[HEAP_RT_COUNT32];
-static struct block_hdr mod_block64[HEAP_RT_COUNT64];
-static struct block_hdr mod_block128[HEAP_RT_COUNT128];
-static struct block_hdr mod_block256[HEAP_RT_COUNT256];
-static struct block_hdr mod_block512[HEAP_RT_COUNT512];
-static struct block_hdr mod_block1024[HEAP_RT_COUNT1024];
-static struct block_hdr mod_block2048[HEAP_RT_COUNT2048];
-
-/* Heap memory map for modules */
-static struct block_map rt_heap_map[] = {
-	BLOCK_DEF(16, HEAP_RT_COUNT16, mod_block16),
-	BLOCK_DEF(32, HEAP_RT_COUNT32, mod_block32),
-	BLOCK_DEF(64, HEAP_RT_COUNT64, mod_block64),
-	BLOCK_DEF(128, HEAP_RT_COUNT128, mod_block128),
-	BLOCK_DEF(256, HEAP_RT_COUNT256, mod_block256),
-	BLOCK_DEF(512, HEAP_RT_COUNT512, mod_block512),
-	BLOCK_DEF(1024, HEAP_RT_COUNT1024, mod_block1024),
-	BLOCK_DEF(2048, HEAP_RT_COUNT2048, mod_block2048),
-};
-
-/* Heap blocks for buffers */
-static struct block_hdr buf_block[HEAP_BUFFER_COUNT];
-
-/* Heap memory map for buffers */
-static struct block_map buf_heap_map[] = {
-	BLOCK_DEF(HEAP_BUFFER_BLOCK_SIZE, HEAP_BUFFER_COUNT, buf_block),
-};
-
-static struct mm memmap = {
-	.system[0] = {
-		.heap = HEAP_SYSTEM_BASE,
-		.size = HEAP_SYSTEM_SIZE,
-		.info = {.free = HEAP_SYSTEM_SIZE,},
-		.caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_DMA,
-	},
-	.system_runtime[0] = {
-		.blocks = ARRAY_SIZE(sys_rt_heap_map),
-		.map = sys_rt_heap_map,
-		.heap = HEAP_SYS_RUNTIME_BASE,
-		.size = HEAP_SYS_RUNTIME_SIZE,
-		.info = {.free = HEAP_SYS_RUNTIME_SIZE,},
-		.caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_DMA,
-	},
-	.runtime[0] = {
-		.blocks = ARRAY_SIZE(rt_heap_map),
-		.map = rt_heap_map,
-		.heap = HEAP_RUNTIME_BASE,
-		.size = HEAP_RUNTIME_SIZE,
-		.info = {.free = HEAP_RUNTIME_SIZE,},
-		.caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_DMA,
-	},
-	.buffer[0] = {
-		.blocks = ARRAY_SIZE(buf_heap_map),
-		.map = buf_heap_map,
-		.heap = HEAP_BUFFER_BASE,
-		.size = HEAP_BUFFER_SIZE,
-		.info = {.free = HEAP_BUFFER_SIZE,},
-		.caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_DMA | SOF_MEM_CAPS_CACHE | SOF_MEM_CAPS_HP,
-	},
-	.total = {.free = HEAP_SYSTEM_SIZE + HEAP_SYS_RUNTIME_SIZE +
-			HEAP_RUNTIME_SIZE + HEAP_BUFFER_SIZE,},
-};
-
-void platform_init_memmap(struct sof *sof)
-{
-	/* memmap has been initialized statically as a part of .data */
-	sof->memory_map = &memmap;
-}
diff --git a/src/platform/amd/vangogh/platform.c b/src/platform/amd/vangogh/platform.c
deleted file mode 100644
index da2c24bfb067..000000000000
--- a/src/platform/amd/vangogh/platform.c
+++ /dev/null
@@ -1,208 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-//
-//Copyright(c) 2023 AMD. All rights reserved.
-//
-//Author:       Basavaraj Hiregoudar <basavaraj.hiregoudar@amd.com>
-//              SaiSurya, Ch <saisurya.chakkaveeravenkatanaga@amd.com>
-
-#include <sof/compiler_info.h>
-#include <sof/debug/debug.h>
-#include <rtos/interrupt.h>
-#include <sof/drivers/acp_dai_dma.h>
-#include <sof/ipc/driver.h>
-#include <rtos/timer.h>
-#include <sof/fw-ready-metadata.h>
-#include <sof/lib/agent.h>
-#include <rtos/clk.h>
-#include <sof/lib/cpu.h>
-#include <sof/lib/dai.h>
-#include <sof/lib/dma.h>
-#include <sof/lib/mailbox.h>
-#include <sof/lib/memory.h>
-#include <sof/lib/mm_heap.h>
-#include <sof/platform.h>
-#include <sof/schedule/edf_schedule.h>
-#include <sof/schedule/ll_schedule.h>
-#include <sof/schedule/ll_schedule_domain.h>
-#include <rtos/sof.h>
-#include <sof/trace/dma-trace.h>
-#include <ipc/dai.h>
-#include <ipc/header.h>
-#include <ipc/info.h>
-#include <kernel/abi.h>
-#include <kernel/ext_manifest.h>
-#include <sof_versions.h>
-#include <errno.h>
-#include <stdint.h>
-#include <platform/chip_offset_byte.h>
-
-struct sof;
-static const struct sof_ipc_fw_ready ready
-	__attribute__((section(".fw_ready"))) = {
-	.hdr = {
-		.cmd = SOF_IPC_FW_READY,
-		.size = sizeof(struct sof_ipc_fw_ready),
-	},
-	/* dspbox is for DSP initiated IPC, hostbox is for host initiated IPC */
-	.version = {
-		.hdr.size = sizeof(struct sof_ipc_fw_version),
-		.micro = SOF_MICRO,
-		.minor = SOF_MINOR,
-		.major = SOF_MAJOR,
-#ifdef DEBUG_BUILD
-		/* only added in debug for reproducability in releases */
-		.build = SOF_BUILD,
-		.date = __DATE__,
-		.time = __TIME__,
-#endif
-		.tag = SOF_TAG,
-		.abi_version = SOF_ABI_VERSION,
-	},
-	.flags = DEBUG_SET_FW_READY_FLAGS,
-};
-
-#define NUM_ACP_WINDOWS		6
-
-const struct ext_man_windows xsram_window
-		__aligned(EXT_MAN_ALIGN) __unused = {
-	.hdr = {
-		.type = EXT_MAN_ELEM_WINDOW,
-		.elem_size = ALIGN_UP_COMPILE(sizeof(struct ext_man_windows), EXT_MAN_ALIGN),
-	},
-	.window = {
-		.ext_hdr	= {
-			.hdr.cmd = SOF_IPC_FW_READY,
-			.hdr.size = sizeof(struct sof_ipc_window),
-			.type   = SOF_IPC_EXT_WINDOW,
-		},
-		.num_windows    = NUM_ACP_WINDOWS,
-		.window = {
-			{
-				.type   = SOF_IPC_REGION_UPBOX,
-				.id     = 0,
-				.flags  = 0,
-				.size   = MAILBOX_DSPBOX_SIZE,
-				.offset = MAILBOX_DSPBOX_OFFSET,
-			},
-			{
-				.type   = SOF_IPC_REGION_DOWNBOX,
-				.id     = 0,
-				.flags  = 0,
-				.size   = MAILBOX_HOSTBOX_SIZE,
-				.offset = MAILBOX_HOSTBOX_OFFSET,
-			},
-			{
-				.type   = SOF_IPC_REGION_DEBUG,
-				.id     = 0,
-				.flags  = 0,
-				.size   = MAILBOX_DEBUG_SIZE,
-				.offset = MAILBOX_DEBUG_OFFSET,
-			},
-			{
-				.type   = SOF_IPC_REGION_TRACE,
-				.id     = 0,
-				.flags  = 0,
-				.size   = MAILBOX_TRACE_SIZE,
-				.offset = MAILBOX_TRACE_OFFSET,
-			},
-			{
-				.type   = SOF_IPC_REGION_STREAM,
-				.id     = 0,
-				.flags  = 0,
-				.size   = MAILBOX_STREAM_SIZE,
-				.offset = MAILBOX_STREAM_OFFSET,
-			},
-			{
-				.type   = SOF_IPC_REGION_EXCEPTION,
-				.id     = 0,
-				.flags  = 0,
-				.size   = MAILBOX_EXCEPTION_SIZE,
-				.offset = MAILBOX_EXCEPTION_OFFSET,
-			},
-		},
-	},
-};
-
-static struct timer timer = {
-	.id = TIMER0,
-	.irq = IRQ_NUM_TIMER0,
-};
-
-int platform_init(struct sof *sof)
-{
-	int ret;
-
-	sof->platform_timer = &timer;
-	sof->cpu_timers = &timer;
-	/* to view system memory */
-	interrupt_init(sof);
-	platform_interrupt_init();
-	platform_clock_init(sof);
-	scheduler_init_edf();
-	/* init low latency domains and schedulers */
-	/* CONFIG_SYSTICK_PERIOD set as PLATFORM_DEFAULT_CLOCK */
-	sof->platform_timer_domain = timer_domain_init(sof->platform_timer,
-						       PLATFORM_DEFAULT_CLOCK);
-	scheduler_init_ll(sof->platform_timer_domain);
-	platform_timer_start(sof->platform_timer);
-	/*CONFIG_SYSTICK_PERIOD hardcoded as 200000*/
-	sa_init(sof, 200000);
-	clock_set_freq(CLK_CPU(cpu_get_id()), CLK_MAX_CPU_HZ);
-	/* init DMA */
-	ret = acp_dma_init(sof);
-	if (ret < 0)
-		return -ENODEV;
-	/* Init DMA platform domain */
-	sof->platform_dma_domain = dma_multi_chan_domain_init(&sof->dma_info->dma_array[0],
-							      sizeof(sof->dma_info->dma_array),
-							      PLATFORM_DEFAULT_CLOCK, true);
-	scheduler_init_ll(sof->platform_dma_domain);
-	/* initialize the host IPC mechanisms */
-	ipc_init(sof);
-	/* initialize the DAI mechanisms */
-	ret = dai_init(sof);
-	if (ret < 0)
-		return -ENODEV;
-#if CONFIG_TRACE
-	/* Initialize DMA for Trace*/
-	trace_point(TRACE_BOOT_PLATFORM_DMA_TRACE);
-	sof->dmat->config.elem_array.elems = rzalloc(SOF_MEM_FLAG_KERNEL,
-						     sizeof(struct dma_sg_elem) * 1);
-	sof->dmat->config.elem_array.count = 1;
-	sof->dmat->config.elem_array.elems->dest = 0x03800000;
-	sof->dmat->config.elem_array.elems->size = 65536;
-	sof->dmat->config.scatter = 0;
-	dma_trace_init_complete(sof->dmat);
-#endif
-	/* show heap status */
-	heap_trace_all(1);
-	return 0;
-}
-
-int platform_boot_complete(uint32_t boot_message)
-{
-	acp_sw_intr_trig_t  swintrtrig;
-
-	volatile acp_scratch_mem_config_t *pscratch_mem_cfg =
-		(volatile acp_scratch_mem_config_t *)(PU_SCRATCH_REG_BASE + SCRATCH_REG_OFFSET);
-	mailbox_dspbox_write(0, &ready, sizeof(ready));
-	mailbox_dspbox_write(sizeof(ready), &xsram_window.window, sizeof(xsram_window.window));
-	pscratch_mem_cfg->acp_dsp_msg_write = 1;
-	acp_dsp_to_host_intr_trig();
-	/* Configures the trigger bit in ACP_DSP_SW_INTR_TRIG register */
-	swintrtrig = (acp_sw_intr_trig_t)io_reg_read(PU_REGISTER_BASE + ACP_SW_INTR_TRIG);
-	swintrtrig.bits.trig_dsp0_to_host_intr  = INTERRUPT_DISABLE;
-	io_reg_write((PU_REGISTER_BASE + ACP_SW_INTR_TRIG), swintrtrig.u32all);
-	clock_set_freq(CLK_CPU(cpu_get_id()), CLK_DEFAULT_CPU_HZ);
-	return 0;
-}
-
-int platform_context_save(struct sof *sof)
-{
-	return 0;
-}
-
-void platform_wait_for_interrupt(int level)
-{
-	arch_wait_for_interrupt(level);
-}
diff --git a/src/platform/amd/vangogh/vangogh.x.in b/src/platform/amd/vangogh/vangogh.x.in
deleted file mode 100644
index 860bf21987fb..000000000000
--- a/src/platform/amd/vangogh/vangogh.x.in
+++ /dev/null
@@ -1,577 +0,0 @@
-/*
- * Linker Script for AMD Vangogh
- *
- * This script is run through the GNU C preprocessor to align the memory
- * offsets with headers.
- *
- * Use spaces for formatting as cpp ignore tab sizes.
- */
-
-#include <sof/lib/memory.h>
-#include <xtensa/config/core-isa.h>
-
-OUTPUT_ARCH(xtensa)
-
-MEMORY
-{
-  vector_reset_text :
-        org = XCHAL_RESET_VECTOR_PADDR,
-        len = SOF_MEM_RESET_TEXT_SIZE
-  vector_reset_lit :
-        org = XCHAL_RESET_VECTOR_PADDR + SOF_MEM_RESET_TEXT_SIZE,
-        len = SOF_MEM_RESET_LIT_SIZE
-  vector_base_text :
-        org = XCHAL_WINDOW_VECTORS_VADDR, //XCHAL_VECBASE_RESET_PADDR,
-        len = SOF_MEM_VECBASE_LIT_SIZE
-  vector_int2_lit :
-        org = XCHAL_INTLEVEL2_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
-        len = SOF_MEM_VECT_LIT_SIZE
-  vector_int2_text :
-        org = XCHAL_INTLEVEL2_VECTOR_PADDR,
-        len = SOF_MEM_VECT_TEXT_SIZE
-  vector_int3_lit :
-        org = XCHAL_INTLEVEL3_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
-        len = SOF_MEM_VECT_LIT_SIZE
-  vector_int3_text :
-        org = XCHAL_INTLEVEL3_VECTOR_PADDR,
-        len = SOF_MEM_VECT_TEXT_SIZE
-  vector_int4_lit :
-        org = XCHAL_INTLEVEL4_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
-        len = SOF_MEM_VECT_LIT_SIZE
-  vector_int4_text :
-        org = XCHAL_INTLEVEL4_VECTOR_PADDR,
-        len = SOF_MEM_VECT_TEXT_SIZE
-  vector_int5_lit :
-        org = XCHAL_INTLEVEL5_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
-        len = SOF_MEM_VECT_LIT_SIZE
-  vector_int5_text :
-        org = XCHAL_INTLEVEL5_VECTOR_PADDR,
-        len = SOF_MEM_VECT_TEXT_SIZE
-  vector_int6_lit :
-        org = XCHAL_INTLEVEL6_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
-        len = SOF_MEM_VECT_LIT_SIZE
-  vector_int6_text :
-        org = XCHAL_INTLEVEL6_VECTOR_PADDR,
-        len = SOF_MEM_VECT_TEXT_SIZE
-
-  vector_int7_lit :
-        org = XCHAL_INTLEVEL7_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
-        len = SOF_MEM_VECT_LIT_SIZE
-  vector_int7_text :
-        org = XCHAL_INTLEVEL7_VECTOR_PADDR,
-        len = SOF_MEM_VECT_TEXT_SIZE
-  vector_kernel_lit :
-        org = XCHAL_KERNEL_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
-        len = SOF_MEM_VECT_LIT_SIZE
-  vector_kernel_text :
-        org = XCHAL_KERNEL_VECTOR_PADDR,
-        len = SOF_MEM_VECT_TEXT_SIZE
-  vector_user_lit :
-        org = XCHAL_USER_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
-        len = SOF_MEM_VECT_LIT_SIZE
-  vector_user_text :
-        org = XCHAL_USER_VECTOR_PADDR,
-        len = SOF_MEM_VECT_TEXT_SIZE
-  vector_double_lit :
-        org = XCHAL_DOUBLEEXC_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
-        len = SOF_MEM_VECT_LIT_SIZE
-  vector_double_text :
-        org = XCHAL_DOUBLEEXC_VECTOR_PADDR,
-        len = SOF_MEM_VECT_TEXT_SIZE
-  sof_iram_text_start :
-        org = XCHAL_DOUBLEEXC_VECTOR_PADDR + SOF_MEM_VECT_TEXT_SIZE,
-        len =  IRAM_BASE + (XCHAL_DOUBLEEXC_VECTOR_PADDR + SOF_MEM_VECT_TEXT_SIZE)
-  sof_sdram0 :
-        org = DRAM0_BASE,
-        len = DRAM0_SIZE
-  system_heap :
-        org = HEAP_SYSTEM_BASE,
-        len = HEAP_SYSTEM_SIZE
-  system_runtime_heap :
-        org = HEAP_SYS_RUNTIME_BASE,
-        len = HEAP_SYS_RUNTIME_SIZE
-  runtime_heap :
-        org = HEAP_RUNTIME_BASE,
-        len = HEAP_RUNTIME_SIZE
-  buffer_heap :
-        org = HEAP_BUFFER_BASE,
-        len = HEAP_BUFFER_SIZE
- sof_stack :
-        org = SOF_STACK_BASE,
-        len = SOF_STACK_BASE - SOF_STACK_END,
-sof_sdram1 :
-        org = HEAP_BUFFER_BASE + HEAP_BUFFER_SIZE,
-        len = DRAM1_SIZE- (HEAP_SYSTEM_SIZE +HEAP_SYS_RUNTIME_SIZE + HEAP_RUNTIME_SIZE + HEAP_BUFFER_SIZE + SOF_STACK_SIZE )
-  static_uuid_entries_seg (!ari) :
-	org = UUID_ENTRY_ELF_BASE,
-	len = UUID_ENTRY_ELF_SIZE
-  static_log_entries_seg (!ari) :
-        org = LOG_ENTRY_ELF_BASE,
-        len = LOG_ENTRY_ELF_SIZE
- fw_metadata_seg (!ari) :
-        org = EXT_MANIFEST_ELF_BASE,
-        len = EXT_MANIFEST_ELF_SIZE
-}
-
-PHDRS
-{
-  vector_reset_text_phdr PT_LOAD;
-  vector_reset_lit_phdr PT_LOAD;
-  vector_base_text_phdr PT_LOAD;
-  vector_base_lit_phdr PT_LOAD;
-  vector_int2_text_phdr PT_LOAD;
-  vector_int2_lit_phdr PT_LOAD;
-  vector_int3_text_phdr PT_LOAD;
-  vector_int3_lit_phdr PT_LOAD;
-  vector_int4_text_phdr PT_LOAD;
-  vector_int4_lit_phdr PT_LOAD;
-  vector_int5_text_phdr PT_LOAD;
-  vector_int5_lit_phdr PT_LOAD;
-  vector_int6_text_phdr PT_LOAD;
-  vector_int6_lit_phdr PT_LOAD;
-  vector_int7_text_phdr PT_LOAD;
-  vector_int7_lit_phdr PT_LOAD;
-  vector_kernel_text_phdr PT_LOAD;
-  vector_kernel_lit_phdr PT_LOAD;
-  vector_user_text_phdr PT_LOAD;
-  vector_user_lit_phdr PT_LOAD;
-  vector_double_text_phdr PT_LOAD;
-  vector_double_lit_phdr PT_LOAD;
-  sof_iram_text_start_phdr PT_LOAD;
-  sof_sdram0_phdr PT_LOAD;
-   sof_stack_phdr PT_LOAD;
-  system_heap_phdr PT_LOAD;
-  system_runtime_heap_phdr PT_LOAD;
-  runtime_heap_phdr PT_LOAD;
-  buffer_heap_phdr PT_LOAD;
-  sof_sdram1_phdr PT_LOAD;
-  static_uuid_entries_phdr PT_NOTE;
-  static_log_entries_phdr PT_NOTE;
- metadata_entries_phdr PT_NOTE;
-}
-
-/*  Default entry point:  */
-ENTRY(_ResetVector)
-_rom_store_table = 0;
-
-/* ABI0 does not use Window base */
-PROVIDE(_memmap_vecbase_reset = XCHAL_WINDOW_VECTORS_VADDR);
-
-/* Various memory-map dependent cache attribute settings: */
-_memmap_cacheattr_wb_base = 0x44024000;
-_memmap_cacheattr_wt_base = 0x11021000;
-_memmap_cacheattr_bp_base = 0x22022000;
-_memmap_cacheattr_unused_mask = 0x00F00FFF;
-_memmap_cacheattr_wb_trapnull = 0x4422422F;
-_memmap_cacheattr_wba_trapnull = 0x4422422F;
-_memmap_cacheattr_wbna_trapnull = 0x25222222;
-_memmap_cacheattr_wt_trapnull = 0x1122122F;
-_memmap_cacheattr_bp_trapnull = 0x2222222F;
-_memmap_cacheattr_wb_strict = 0x44F24FFF;
-_memmap_cacheattr_wt_strict = 0x11F21FFF;
-_memmap_cacheattr_bp_strict = 0x22F22FFF;
-_memmap_cacheattr_wb_allvalid = 0x44224222;
-_memmap_cacheattr_wt_allvalid = 0x11221222;
-_memmap_cacheattr_bp_allvalid = 0x22222222;
-PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wbna_trapnull);
-_EXT_MAN_ALIGN_ = 16;
-EXTERN(ext_man_fw_ver)
-
-
-SECTIONS
-{
-  .ResetVector.text : ALIGN(4)
-  {
-    _ResetVector_text_start = ABSOLUTE(.);
-    KEEP (*(.ResetVector.text))
-    _ResetVector_text_end = ABSOLUTE(.);
-  } >vector_reset_text :vector_reset_text_phdr
-
-  .ResetVector.literal : ALIGN(4)
-  {
-    _ResetVector_literal_start = ABSOLUTE(.);
-    *(.ResetVector.literal)
-    _ResetVector_literal_end = ABSOLUTE(.);
-  } >vector_reset_lit :vector_reset_lit_phdr
-
-  .WindowVectors.text : ALIGN(4)
-  {
-    _WindowVectors_text_start = ABSOLUTE(.);
-    KEEP (*(.WindowVectors.text))
-    _WindowVectors_text_end = ABSOLUTE(.);
-  } >vector_base_text :vector_base_text_phdr
-
-  .Level2InterruptVector.literal : ALIGN(4)
-  {
-    _Level2InterruptVector_literal_start = ABSOLUTE(.);
-    *(.Level2InterruptVector.literal)
-    _Level2InterruptVector_literal_end = ABSOLUTE(.);
-  } >vector_int2_lit :vector_int2_lit_phdr
-
-  .Level2InterruptVector.text : ALIGN(4)
-  {
-    _Level2InterruptVector_text_start = ABSOLUTE(.);
-    KEEP (*(.Level2InterruptVector.text))
-    _Level2InterruptVector_text_end = ABSOLUTE(.);
-  } >vector_int2_text :vector_int2_text_phdr
-
-  .Level3InterruptVector.literal : ALIGN(4)
-  {
-    _Level3InterruptVector_literal_start = ABSOLUTE(.);
-    *(.Level3InterruptVector.literal)
-    _Level3InterruptVector_literal_end = ABSOLUTE(.);
-  } >vector_int3_lit :vector_int3_lit_phdr
-
-  .Level3InterruptVector.text : ALIGN(4)
-  {
-    _Level3InterruptVector_text_start = ABSOLUTE(.);
-    KEEP (*(.Level3InterruptVector.text))
-    _Level3InterruptVector_text_end = ABSOLUTE(.);
-  } >vector_int3_text :vector_int3_text_phdr
-
-  .Level4InterruptVector.literal : ALIGN(4)
-  {
-    _Level4InterruptVector_literal_start = ABSOLUTE(.);
-    *(.Level4InterruptVector.literal)
-    _Level4InterruptVector_literal_end = ABSOLUTE(.);
-  } >vector_int4_lit :vector_int4_lit_phdr
-
-  .Level4InterruptVector.text : ALIGN(4)
-  {
-    _Level4InterruptVector_text_start = ABSOLUTE(.);
-    KEEP (*(.Level4InterruptVector.text))
-    _Level4InterruptVector_text_end = ABSOLUTE(.);
-  } >vector_int4_text :vector_int4_text_phdr
-
-  .Level5InterruptVector.literal : ALIGN(4)
-  {
-    _Level5InterruptVector_literal_start = ABSOLUTE(.);
-    *(.Level5InterruptVector.literal)
-    _Level5InterruptVector_literal_end = ABSOLUTE(.);
-  } >vector_int5_lit :vector_int5_lit_phdr
-
-  .Level5InterruptVector.text : ALIGN(4)
-  {
-    _Level5InterruptVector_text_start = ABSOLUTE(.);
-    KEEP (*(.Level5InterruptVector.text))
-    _Level5InterruptVector_text_end = ABSOLUTE(.);
-  } >vector_int5_text :vector_int5_text_phdr
-
-  .DebugExceptionVector.literal : ALIGN(4)
-  {
-    _DebugExceptionVector_literal_start = ABSOLUTE(.);
-    *(.DebugExceptionVector.literal)
-    _DebugExceptionVector_literal_end = ABSOLUTE(.);
-  } >vector_int6_lit :vector_int6_lit_phdr
-
-  .DebugExceptionVector.text : ALIGN(4)
-  {
-    _DebugExceptionVector_text_start = ABSOLUTE(.);
-    KEEP (*(.DebugExceptionVector.text))
-    _DebugExceptionVector_text_end = ABSOLUTE(.);
-  } >vector_int6_text :vector_int6_text_phdr
-
-  .NMIExceptionVector.literal : ALIGN(4)
-  {
-    _NMIExceptionVector_literal_start = ABSOLUTE(.);
-    *(.NMIExceptionVector.literal)
-    _NMIExceptionVector_literal_end = ABSOLUTE(.);
-  } >vector_int7_lit :vector_int5_lit_phdr
-
-  .NMIExceptionVector.text : ALIGN(4)
-  {
-    _NMIExceptionVector_text_start = ABSOLUTE(.);
-    KEEP (*(.NMIExceptionVector.text))
-    _NMIExceptionVector_text_end = ABSOLUTE(.);
-  } >vector_int7_text :vector_int5_text_phdr
-
-  .KernelExceptionVector.literal : ALIGN(4)
-  {
-    _KernelExceptionVector_literal_start = ABSOLUTE(.);
-    *(.KernelExceptionVector.literal)
-    _KernelExceptionVector_literal_end = ABSOLUTE(.);
-  } >vector_kernel_lit :vector_kernel_lit_phdr
-
-  .KernelExceptionVector.text : ALIGN(4)
-  {
-    _KernelExceptionVector_text_start = ABSOLUTE(.);
-    KEEP (*(.KernelExceptionVector.text))
-    _KernelExceptionVector_text_end = ABSOLUTE(.);
-  } >vector_kernel_text :vector_kernel_text_phdr
-
-  .UserExceptionVector.literal : ALIGN(4)
-  {
-    _UserExceptionVector_literal_start = ABSOLUTE(.);
-    *(.UserExceptionVector.literal)
-    _UserExceptionVector_literal_end = ABSOLUTE(.);
-  } >vector_user_lit :vector_user_lit_phdr
-
-  .UserExceptionVector.text : ALIGN(4)
-  {
-    _UserExceptionVector_text_start = ABSOLUTE(.);
-    KEEP (*(.UserExceptionVector.text))
-    _UserExceptionVector_text_end = ABSOLUTE(.);
-  } >vector_user_text :vector_user_text_phdr
-
-  .DoubleExceptionVector.literal : ALIGN(4)
-  {
-    _DoubleExceptionVector_literal_start = ABSOLUTE(.);
-    *(.DoubleExceptionVector.literal)
-    _DoubleExceptionVector_literal_end = ABSOLUTE(.);
-  } >vector_double_lit :vector_double_lit_phdr
-
-  .DoubleExceptionVector.text : ALIGN(4)
-  {
-    _DoubleExceptionVector_text_start = ABSOLUTE(.);
-    KEEP (*(.DoubleExceptionVector.text))
-    _DoubleExceptionVector_text_end = ABSOLUTE(.);
-  } >vector_double_text :vector_double_text_phdr
-
-  .iram.text : ALIGN(4)
-  {
-    _stext = .;
-    _iram_text_start = ABSOLUTE(.);
-    *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)
-    _iram_text_end = ABSOLUTE(.);
-  } >sof_iram_text_start :sof_iram_text_start_phdr
-
-	/* stack */
- _end = SOF_STACK_END;
-  PROVIDE(end = SOF_STACK_END);
-  _stack_sentry = SOF_STACK_END;
-  __stack = SOF_STACK_BASE;
-
-  .text : ALIGN(4)
-  {
-    _stext = .;
-    _text_start = ABSOLUTE(.);
-    *(.entry.text)
-    *(.init.literal)
-    KEEP(*(.init))
-    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
-    *(.fini.literal)
-    KEEP(*(.fini))
-    *(.gnu.version)
-    _text_end = ABSOLUTE(.);
-    _etext = .;
-  } >sof_iram_text_start :sof_iram_text_start_phdr
-
-
-  .rodata : ALIGN(4)
-  {
-    _rodata_start = ABSOLUTE(.);
-    *(.rodata)
-    *(.rodata.*)
-    *(.gnu.linkonce.r.*)
-    *(.rodata1)
-    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);
-    KEEP (*(.xt_except_table))
-    KEEP (*(.gcc_except_table))
-    *(.gnu.linkonce.e.*)
-    *(.gnu.version_r)
-    KEEP (*(.eh_frame))
-    /*  C++ constructor and destructor tables, properly ordered:  */
-    KEEP (*crtbegin.o(.ctors))
-    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
-    KEEP (*(SORT(.ctors.*)))
-    KEEP (*(.ctors))
-    KEEP (*crtbegin.o(.dtors))
-    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
-    KEEP (*(SORT(.dtors.*)))
-    KEEP (*(.dtors))
-    /*  C++ exception handlers table:  */
-    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);
-    *(.xt_except_desc)
-    *(.gnu.linkonce.h.*)
-    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
-    *(.xt_except_desc_end)
-    *(.dynamic)
-    *(.gnu.version_d)
-    . = ALIGN(4);		/* this table MUST be 4-byte aligned */
-    _bss_table_start = ABSOLUTE(.);
-    LONG(_bss_start)
-    LONG(_bss_end)
-    _bss_table_end = ABSOLUTE(.);
-    _rodata_end = ABSOLUTE(.);
-  } >sof_sdram0 :sof_sdram0_phdr
-
-  .module_init : ALIGN(4)
-  {
-   _module_init_start = ABSOLUTE(.);
-    *(*.initcall)
-    _module_init_end = ABSOLUTE(.);
-  } >sof_sdram0 :sof_sdram0_phdr
-
-  .data : ALIGN(4)
-  {
-    _data_start = ABSOLUTE(.);
-    *(.data)
-    *(.data.*)
-    *(.gnu.linkonce.d.*)
-    KEEP(*(.gnu.linkonce.d.*personality*))
-    *(.data1)
-    *(.sdata)
-    *(.sdata.*)
-    *(.gnu.linkonce.s.*)
-    *(.sdata2)
-    *(.sdata2.*)
-    *(.gnu.linkonce.s2.*)
-    KEEP(*(.jcr))
-    _trace_ctx_start = ABSOLUTE(.);
-    *(.trace_ctx)
-    _trace_ctx_end = ABSOLUTE(.);
-    _data_end = ABSOLUTE(.);
-  } >sof_sdram0 :sof_sdram0_phdr
-
-  .lit4 : ALIGN(4)
-  {
-    _lit4_start = ABSOLUTE(.);
-    *(*.lit4)
-    *(.lit4.*)
-    *(.gnu.linkonce.lit4.*)
-    _lit4_end = ABSOLUTE(.);
-  } >sof_sdram0 :sof_sdram0_phdr
-
-  .fw_ready : ALIGN(4)
-  {
-    KEEP (*(.fw_ready))
-  } >sof_sdram0 :sof_sdram0_phdr
-
-
-  .bss (NOLOAD) : ALIGN(8)
-  {
-    . = ALIGN (8);
-    _bss_start = ABSOLUTE(.);
-    *(.dynsbss)
-    *(.sbss)
-    *(.sbss.*)
-    *(.gnu.linkonce.sb.*)
-    *(.scommon)
-    *(.sbss2)
-    *(.sbss2.*)
-    *(.gnu.linkonce.sb2.*)
-    *(.dynbss)
-    *(.bss)
-    *(.bss.*)
-    *(.gnu.linkonce.b.*)
-    *(COMMON)
-    . = ALIGN (8);
-    _bss_end = ABSOLUTE(.);
-  } >sof_sdram0 :sof_sdram0_phdr
-
-
-.sof_stack (NOLOAD) : ALIGN(8)
-  {
-    . = ALIGN (4096);
-    _sof_stack_start = ABSOLUTE(.);
-    . = . + SOF_STACK_TOTAL_SIZE;
-    _sof_stack_end = ABSOLUTE(.);
-  } >sof_stack :sof_stack_phdr
-
-  .reset.rodata : ALIGN(4)
-  {
-    _reset_rodata_start = ABSOLUTE(.);
-    *(.reset.rodata)
-    _reset_rodata_end = ABSOLUTE(.);
-  } >sof_sdram0 :sof_sdram0_phdr
-
-  .system_heap (NOLOAD) : ALIGN(8)
-  {
-    . = ALIGN (32);
-    _system_heap_start = ABSOLUTE(.);
-    . = . + HEAP_SYSTEM_SIZE;
-    _system_heap_end = ABSOLUTE(.);
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-
-  .system_runtime_heap (NOLOAD) : ALIGN(8)
-  {
-    . = ALIGN (HEAP_BUF_ALIGNMENT);
-    _system_runtime_heap_start = ABSOLUTE(.);
-    . = . + HEAP_SYS_RUNTIME_SIZE;
-    _system_runtime_heap_end = ABSOLUTE(.);
-  } >system_runtime_heap :system_runtime_heap_phdr
-
-  .runtime_heap (NOLOAD) : ALIGN(8)
-  {
-    . = ALIGN (32);
-    _runtime_heap_start = ABSOLUTE(.);
-    . = . + HEAP_RUNTIME_SIZE;
-    _runtime_heap_end = ABSOLUTE(.);
-  } >runtime_heap :runtime_heap_phdr
-
-  .buffer_heap (NOLOAD) : ALIGN(8)
-  {
-    . = ALIGN (HEAP_BUF_ALIGNMENT);
-    _buffer_heap_start = ABSOLUTE(.);
-    . = . + HEAP_BUFFER_SIZE;
-    _buffer_heap_end = ABSOLUTE(.);
-  } >buffer_heap :buffer_heap_phdr
-
-  .static_uuid_entries (COPY) : ALIGN(1024)
-  {
-    *(*.static_uuids)
-  } > static_uuid_entries_seg :static_uuid_entries_phdr
-
-  .static_log_entries (COPY) : ALIGN(1024)
-  {
-    *(*.static_log*)
-  } > static_log_entries_seg :static_log_entries_phdr
-
-  .debug  0 :  { *(.debug) }
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-  .debug_typenames  0 :  { *(.debug_typenames) }
-  .debug_varnames  0 :  { *(.debug_varnames) }
-
-  .xt.insn 0 :
-  {
-    KEEP (*(.xt.insn))
-    KEEP (*(.gnu.linkonce.x.*))
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-  .xt.prop 0 :
-  {
-    KEEP (*(.xt.prop))
-    KEEP (*(.xt.prop.*))
-    KEEP (*(.gnu.linkonce.prop.*))
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-  {
-    KEEP (*(.xt.lit))
-    KEEP (*(.xt.lit.*))
-    KEEP (*(.gnu.linkonce.p.*))
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-  {
-    KEEP (*(.xt.profile_range))
-    KEEP (*(.gnu.linkonce.profile_range.*))
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-  {
-    KEEP (*(.xt.profile_ranges))
-    KEEP (*(.gnu.linkonce.xt.profile_ranges.*))
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-  .xt.profile_files 0 :
-  {
-    KEEP (*(.xt.profile_files))
-    KEEP (*(.gnu.linkonce.xt.profile_files.*))
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- .fw_metadata (COPY) : ALIGN(1024)
-  {
-    KEEP (*(.fw_metadata))
-    . = ALIGN(_EXT_MAN_ALIGN_);
-  } >fw_metadata_seg :metadata_entries_phdr
-
-}
diff --git a/src/platform/imx8/CMakeLists.txt b/src/platform/imx8/CMakeLists.txt
deleted file mode 100644
index ec909d60035f..000000000000
--- a/src/platform/imx8/CMakeLists.txt
+++ /dev/null
@@ -1,5 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-
-add_subdirectory(lib)
-
-add_local_sources(sof platform.c)
diff --git a/src/platform/imx8/lib/CMakeLists.txt b/src/platform/imx8/lib/CMakeLists.txt
deleted file mode 100644
index 271a099cc6a9..000000000000
--- a/src/platform/imx8/lib/CMakeLists.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-
-add_local_sources(sof
-	clk.c
-	dai.c
-	dma.c
-	memory.c
-)
diff --git a/src/platform/imx8/lib/dai.c b/src/platform/imx8/lib/dai.c
deleted file mode 100644
index a0f8fcc39135..000000000000
--- a/src/platform/imx8/lib/dai.c
+++ /dev/null
@@ -1,105 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-//
-// Copyright 2019 NXP
-//
-// Author: Daniel Baluta <daniel.baluta@nxp.com>
-
-#include <sof/common.h>
-#include <sof/drivers/edma.h>
-#include <sof/drivers/esai.h>
-#include <sof/drivers/sai.h>
-#include <sof/lib/dai.h>
-#include <sof/lib/memory.h>
-#include <rtos/sof.h>
-#include <rtos/spinlock.h>
-#include <ipc/dai.h>
-#include <ipc/stream.h>
-
-static struct dai esai[] = {
-{
-	.index = 0,
-	.plat_data = {
-		.base = ESAI_BASE,
-		.fifo[SOF_IPC_STREAM_PLAYBACK] = {
-			.offset		= ESAI_BASE + REG_ESAI_ETDR,
-			.depth		= 96,  /* in 4 bytes words */
-			.handshake	= EDMA_HANDSHAKE(EDMA_ESAI_IRQ,
-							 EDMA_ESAI_TX_CHAN,
-							 0),
-		},
-		.fifo[SOF_IPC_STREAM_CAPTURE] = {
-			.offset		= ESAI_BASE + REG_ESAI_ERDR,
-			.depth		= 96,  /* in 4 bytes words */
-			.handshake	= EDMA_HANDSHAKE(EDMA_ESAI_IRQ,
-							 EDMA_ESAI_RX_CHAN,
-							 0),
-		},
-	},
-	.drv = &esai_driver,
-},
-};
-
-static struct dai sai[] = {
-{
-	.index = 1,
-	.plat_data = {
-		.base = SAI_1_BASE,
-		.fifo[SOF_IPC_STREAM_PLAYBACK] = {
-			.offset		= SAI_1_BASE + REG_SAI_TDR0,
-			/* use depth to model the HW FIFO size:
-			 * each channel includes a 64 x 32 bit FIFO
-			 * that can be accessed using Transmit or
-			 * Receive Data Registers
-			 */
-			.depth		= 64,  /* in 4 bytes words */
-			.watermark	= 32, /* half the depth */
-			.handshake	= EDMA_HANDSHAKE(EDMA0_SAI_CHAN_TX_IRQ,
-							 EDMA0_SAI_CHAN_TX,
-							 0),
-		},
-		.fifo[SOF_IPC_STREAM_CAPTURE] = {
-			.offset		= SAI_1_BASE + REG_SAI_RDR0,
-			.depth		= 64,  /* in 4 bytes words */
-			.watermark	= 32, /* half the depth */
-			.handshake	= EDMA_HANDSHAKE(EDMA0_SAI_CHAN_RX_IRQ,
-							 EDMA0_SAI_CHAN_RX,
-							 0),
-		},
-	},
-	.drv = &sai_driver,
-},
-};
-
-const struct dai_type_info dti[] = {
-	{
-		.type = SOF_DAI_IMX_SAI,
-		.dai_array = cache_to_uncache_init((struct dai *)sai),
-		.num_dais = ARRAY_SIZE(sai)
-	},
-	{
-		.type = SOF_DAI_IMX_ESAI,
-		.dai_array = cache_to_uncache_init((struct dai *)esai),
-		.num_dais = ARRAY_SIZE(esai)
-	},
-};
-
-const struct dai_info lib_dai = {
-	.dai_type_array = dti,
-	.num_dai_types = ARRAY_SIZE(dti)
-};
-
-int dai_init(struct sof *sof)
-{
-	int i;
-
-	 /* initialize spin locks early to enable ref counting */
-	for (i = 0; i < ARRAY_SIZE(esai); i++)
-		k_spinlock_init(&dti[1].dai_array[i].lock);
-
-	for (i = 0; i < ARRAY_SIZE(sai); i++)
-		k_spinlock_init(&dti[0].dai_array[i].lock);
-
-	sof->dai_info = &lib_dai;
-
-	return 0;
-}
diff --git a/src/platform/imx8/lib/dma.c b/src/platform/imx8/lib/dma.c
deleted file mode 100644
index dc3efa653d0a..000000000000
--- a/src/platform/imx8/lib/dma.c
+++ /dev/null
@@ -1,65 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-//
-// Copyright 2019 NXP
-//
-// Author: Daniel Baluta <daniel.baluta@nxp.com>
-
-#include <sof/common.h>
-#include <sof/drivers/edma.h>
-#include <rtos/interrupt.h>
-#include <sof/lib/dma.h>
-#include <sof/lib/memory.h>
-#include <rtos/sof.h>
-#include <rtos/spinlock.h>
-
-extern struct dma_ops dummy_dma_ops;
-extern struct dma_ops edma_ops;
-
-static const int edma0_ints[EDMA0_CHAN_MAX] = {
-	[EDMA0_ESAI_CHAN_RX] = EDMA0_ESAI_CHAN_RX_IRQ,
-	[EDMA0_ESAI_CHAN_TX] = EDMA0_ESAI_CHAN_TX_IRQ,
-	[EDMA0_SAI_CHAN_RX] = EDMA0_SAI_CHAN_RX_IRQ,
-	[EDMA0_SAI_CHAN_TX] = EDMA0_SAI_CHAN_TX_IRQ,
-};
-
-static struct dma dma[PLATFORM_NUM_DMACS] = {
-{
-	.plat_data = {
-		.id		= DMA_ID_EDMA0,
-		.dir		= SOF_DMA_DIR_MEM_TO_DEV | SOF_DMA_DIR_DEV_TO_MEM,
-		.devs		= SOF_DMA_DEV_ESAI | SOF_DMA_DEV_SAI,
-		.base		= EDMA0_BASE,
-		.chan_size	= EDMA0_SIZE,
-		.channels	= 32,
-		.drv_plat_data	= edma0_ints,
-	},
-	.ops	= &edma_ops,
-},
-{
-	.plat_data = {
-		.id		= DMA_ID_HOST,
-		.dir		= SOF_DMA_DIR_HMEM_TO_LMEM | SOF_DMA_DIR_LMEM_TO_HMEM,
-		.devs		= SOF_DMA_DEV_HOST,
-		.channels	= 16,
-	},
-	.ops	= &dummy_dma_ops,
-},
-};
-
-static const struct dma_info lib_dma = {
-	.dma_array = cache_to_uncache_init((struct dma *)dma),
-	.num_dmas = ARRAY_SIZE(dma)
-};
-
-int dmac_init(struct sof *sof)
-{
-	int i;
-
-	/* early lock initialization for ref counting */
-	for (i = 0; i < ARRAY_SIZE(dma); i++)
-		k_spinlock_init(&dma[i].lock);
-
-	sof->dma_info = &lib_dma;
-
-	return 0;
-}
diff --git a/src/platform/imx8/lib/memory.c b/src/platform/imx8/lib/memory.c
deleted file mode 100644
index 81794bafd6d6..000000000000
--- a/src/platform/imx8/lib/memory.c
+++ /dev/null
@@ -1,99 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-//
-// Copyright 2019 NXP
-//
-// Author: Daniel Baluta <daniel.baluta@nxp.com>
-
-#include <sof/common.h>
-#include <sof/lib/mm_heap.h>
-#include <sof/lib/memory.h>
-#include <sof/platform.h>
-#include <rtos/sof.h>
-#include <ipc/topology.h>
-
-/* Heap blocks for system runtime */
-static struct block_hdr sys_rt_block64[HEAP_SYS_RT_COUNT64];
-static struct block_hdr sys_rt_block512[HEAP_SYS_RT_COUNT512];
-static struct block_hdr sys_rt_block1024[HEAP_SYS_RT_COUNT1024];
-
-/* Heap memory for system runtime */
-static struct block_map sys_rt_heap_map[] = {
-	BLOCK_DEF(64, HEAP_SYS_RT_COUNT64, sys_rt_block64),
-	BLOCK_DEF(512, HEAP_SYS_RT_COUNT512, sys_rt_block512),
-	BLOCK_DEF(1024, HEAP_SYS_RT_COUNT1024, sys_rt_block1024),
-};
-
-/* Heap blocks for modules */
-static struct block_hdr mod_block16[HEAP_RT_COUNT16];
-static struct block_hdr mod_block32[HEAP_RT_COUNT32];
-static struct block_hdr mod_block64[HEAP_RT_COUNT64];
-static struct block_hdr mod_block128[HEAP_RT_COUNT128];
-static struct block_hdr mod_block256[HEAP_RT_COUNT256];
-static struct block_hdr mod_block512[HEAP_RT_COUNT512];
-static struct block_hdr mod_block1024[HEAP_RT_COUNT1024];
-static struct block_hdr mod_block2048[HEAP_RT_COUNT2048];
-
-/* Heap memory map for modules */
-static struct block_map rt_heap_map[] = {
-	BLOCK_DEF(16, HEAP_RT_COUNT16, mod_block16),
-	BLOCK_DEF(32, HEAP_RT_COUNT32, mod_block32),
-	BLOCK_DEF(64, HEAP_RT_COUNT64, mod_block64),
-	BLOCK_DEF(128, HEAP_RT_COUNT128, mod_block128),
-	BLOCK_DEF(256, HEAP_RT_COUNT256, mod_block256),
-	BLOCK_DEF(512, HEAP_RT_COUNT512, mod_block512),
-	BLOCK_DEF(1024, HEAP_RT_COUNT1024, mod_block1024),
-	BLOCK_DEF(2048, HEAP_RT_COUNT2048, mod_block2048),
-};
-
-/* Heap blocks for buffers */
-static struct block_hdr buf_block[HEAP_BUFFER_COUNT];
-
-/* Heap memory map for buffers */
-static struct block_map buf_heap_map[] = {
-	BLOCK_DEF(HEAP_BUFFER_BLOCK_SIZE, HEAP_BUFFER_COUNT, buf_block),
-};
-
-static struct mm memmap = {
-	.system[0] = {
-		.heap = HEAP_SYSTEM_BASE,
-		.size = HEAP_SYSTEM_SIZE,
-		.info = {.free = HEAP_SYSTEM_SIZE,},
-		.caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_CACHE |
-			SOF_MEM_CAPS_DMA,
-	},
-	.system_runtime[0] = {
-		.blocks = ARRAY_SIZE(sys_rt_heap_map),
-		.map = sys_rt_heap_map,
-		.heap = HEAP_SYS_RUNTIME_BASE,
-		.size = HEAP_SYS_RUNTIME_SIZE,
-		.info = {.free = HEAP_SYS_RUNTIME_SIZE,},
-		.caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_CACHE |
-			SOF_MEM_CAPS_DMA,
-	},
-	.runtime[0] = {
-		.blocks = ARRAY_SIZE(rt_heap_map),
-		.map = rt_heap_map,
-		.heap = HEAP_RUNTIME_BASE,
-		.size = HEAP_RUNTIME_SIZE,
-		.info = {.free = HEAP_RUNTIME_SIZE,},
-		.caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_CACHE |
-			SOF_MEM_CAPS_DMA,
-	},
-	.buffer[0] = {
-		.blocks = ARRAY_SIZE(buf_heap_map),
-		.map = buf_heap_map,
-		.heap = HEAP_BUFFER_BASE,
-		.size = HEAP_BUFFER_SIZE,
-		.info = {.free = HEAP_BUFFER_SIZE,},
-		.caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_CACHE |
-			SOF_MEM_CAPS_DMA,
-	},
-	.total = {.free = HEAP_SYSTEM_SIZE + HEAP_SYS_RUNTIME_SIZE +
-			HEAP_RUNTIME_SIZE + HEAP_BUFFER_SIZE,},
-};
-
-void platform_init_memmap(struct sof *sof)
-{
-	/* memmap has been initialized statically as a part of .data */
-	sof->memory_map = &memmap;
-}
diff --git a/src/platform/imx8m/CMakeLists.txt b/src/platform/imx8m/CMakeLists.txt
deleted file mode 100644
index ec909d60035f..000000000000
--- a/src/platform/imx8m/CMakeLists.txt
+++ /dev/null
@@ -1,5 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-
-add_subdirectory(lib)
-
-add_local_sources(sof platform.c)
diff --git a/src/platform/imx8m/lib/CMakeLists.txt b/src/platform/imx8m/lib/CMakeLists.txt
deleted file mode 100644
index 271a099cc6a9..000000000000
--- a/src/platform/imx8m/lib/CMakeLists.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-
-add_local_sources(sof
-	clk.c
-	dai.c
-	dma.c
-	memory.c
-)
diff --git a/src/platform/imx8m/lib/dai.c b/src/platform/imx8m/lib/dai.c
deleted file mode 100644
index 433c27ef141a..000000000000
--- a/src/platform/imx8m/lib/dai.c
+++ /dev/null
@@ -1,197 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-//
-// Copyright 2020 NXP
-//
-// Author: Daniel Baluta <daniel.baluta@nxp.com>
-
-#include <sof/common.h>
-#include <sof/drivers/sai.h>
-#include <sof/drivers/micfil.h>
-
-#include <sof/lib/dai.h>
-#include <sof/lib/memory.h>
-#include <rtos/sof.h>
-#include <rtos/spinlock.h>
-#include <ipc/dai.h>
-#include <ipc/stream.h>
-
-static struct dai sai[] = {
-{
-	.index = 1,
-	.plat_data = {
-		.base = SAI_1_BASE,
-		.fifo[SOF_IPC_STREAM_PLAYBACK] = {
-			.offset = SAI_1_BASE + REG_SAI_TDR0,
-			.depth = 128, /* in 4 bytes words */
-			.watermark = 64, /* half the depth */
-			/* Handshake is SDMA hardware event */
-			.handshake = 1,
-		},
-		.fifo[SOF_IPC_STREAM_CAPTURE] = {
-			.offset = SAI_1_BASE + REG_SAI_RDR0,
-			.depth = 128, /* in 4 bytes words */
-			.watermark = 64, /* half the depth */
-			.handshake = 0,
-		},
-	},
-	.drv = &sai_driver,
-},
-
-{
-	.index = 2,
-	.plat_data = {
-		.base = SAI_2_BASE,
-		.fifo[SOF_IPC_STREAM_PLAYBACK] = {
-			.offset = SAI_2_BASE + REG_SAI_TDR0,
-			.depth = 128, /* in 4 bytes words */
-			.watermark = 64, /* half the depth */
-			/* Handshake is SDMA hardware event */
-			.handshake = 3,
-		},
-		.fifo[SOF_IPC_STREAM_CAPTURE] = {
-			.offset = SAI_2_BASE + REG_SAI_RDR0,
-			.depth = 128, /* in 4 bytes words */
-			.watermark = 64, /* half the depth */
-			.handshake = 2,
-		},
-	},
-	.drv = &sai_driver,
-},
-
-{
-	.index = 3,
-	.plat_data = {
-		.base = SAI_3_BASE,
-		.fifo[SOF_IPC_STREAM_PLAYBACK] = {
-			.offset = SAI_3_BASE + REG_SAI_TDR0,
-			.depth = 128, /* in 4 bytes words */
-			.watermark = 64, /* half the depth */
-			/* Handshake is SDMA hardware event */
-			.handshake = 5,
-		},
-		.fifo[SOF_IPC_STREAM_CAPTURE] = {
-			.offset = SAI_3_BASE + REG_SAI_RDR0,
-			.depth = 128, /* in 4 bytes words */
-			.watermark = 64, /* half the depth */
-			.handshake = 4,
-		},
-	},
-	.drv = &sai_driver,
-},
-
-{
-	.index = 5,
-	.plat_data = {
-		.base = SAI_5_BASE,
-		.fifo[SOF_IPC_STREAM_PLAYBACK] = {
-			.offset = SAI_5_BASE + REG_SAI_TDR0,
-			.depth = 128, /* in 4 bytes words */
-			.watermark = 64, /* half the depth */
-			/* Handshake is SDMA hardware event */
-			.handshake = 9,
-		},
-		.fifo[SOF_IPC_STREAM_CAPTURE] = {
-			.offset = SAI_5_BASE + REG_SAI_RDR0,
-			.depth = 128, /* in 4 bytes words */
-			.watermark = 64, /* half the depth */
-			.handshake = 8,
-		},
-	},
-	.drv = &sai_driver,
-},
-
-{
-	.index = 6,
-	.plat_data = {
-		.base = SAI_6_BASE,
-		.fifo[SOF_IPC_STREAM_PLAYBACK] = {
-			.offset = SAI_6_BASE + REG_SAI_TDR0,
-			.depth = 128, /* in 4 bytes words */
-			.watermark = 64, /* half the depth */
-			/* Handshake is SDMA hardware event */
-			.handshake = 11,
-		},
-		.fifo[SOF_IPC_STREAM_CAPTURE] = {
-			.offset = SAI_6_BASE + REG_SAI_RDR0,
-			.depth = 128, /* in 4 bytes words */
-			.watermark = 64, /* half the depth */
-			.handshake = 10,
-		},
-	},
-	.drv = &sai_driver,
-},
-
-{
-	.index = 7,
-	.plat_data = {
-		.base = SAI_7_BASE,
-		.fifo[SOF_IPC_STREAM_PLAYBACK] = {
-			.offset = SAI_7_BASE + REG_SAI_TDR0,
-			.depth = 128, /* in 4 bytes words */
-			.watermark = 64, /* half the depth */
-			/* Handshake is SDMA hardware event */
-			.handshake = 13,
-		},
-		.fifo[SOF_IPC_STREAM_CAPTURE] = {
-			.offset = SAI_7_BASE + REG_SAI_RDR0,
-			.depth = 128, /* in 4 bytes words */
-			.watermark = 64, /* half the depth */
-			.handshake = 12,
-		},
-	},
-	.drv = &sai_driver,
-},
-
-};
-
-static struct dai micfil[] = {
-{
-	.index = 2,
-	.plat_data = {
-		.base = MICFIL_BASE,
-		.fifo[SOF_IPC_STREAM_PLAYBACK] = {
-			.offset = 0, /* No playback */
-			.handshake = 0,
-		},
-		.fifo[SOF_IPC_STREAM_CAPTURE] = {
-			.offset = MICFIL_BASE + REG_MICFIL_DATACH0,
-			.handshake = 24,
-			.depth = 32, /* in 4 bytes words */
-		},
-	},
-
-	.drv = &micfil_driver,
-},
-};
-
-const struct dai_type_info dti[] = {
-	{
-		.type = SOF_DAI_IMX_SAI,
-		.dai_array = cache_to_uncache_init((struct dai *)sai),
-		.num_dais = ARRAY_SIZE(sai)
-	},
-	{
-		.type = SOF_DAI_IMX_MICFIL,
-		.dai_array = cache_to_uncache_init((struct dai *)micfil),
-		.num_dais = ARRAY_SIZE(micfil)
-	},
-
-};
-
-const struct dai_info lib_dai = {
-	.dai_type_array = dti,
-	.num_dai_types = ARRAY_SIZE(dti)
-};
-
-int dai_init(struct sof *sof)
-{
-	int i;
-
-	/* initialize spin locks early to enable ref counting */
-	for (i = 0; i < ARRAY_SIZE(sai); i++)
-		k_spinlock_init(&dti[0].dai_array[i].lock);
-
-	sof->dai_info = &lib_dai;
-
-	return 0;
-}
diff --git a/src/platform/imx8m/lib/dma.c b/src/platform/imx8m/lib/dma.c
deleted file mode 100644
index c9fe4a98e030..000000000000
--- a/src/platform/imx8m/lib/dma.c
+++ /dev/null
@@ -1,60 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-//
-// Copyright 2019 NXP
-//
-// Author: Daniel Baluta <daniel.baluta@nxp.com>
-
-#include <sof/common.h>
-#include <rtos/interrupt.h>
-#include <sof/lib/dma.h>
-#include <sof/lib/memory.h>
-#include <rtos/sof.h>
-#include <rtos/spinlock.h>
-
-extern struct dma_ops dummy_dma_ops;
-extern struct dma_ops sdma_ops;
-
-static struct dma dma[PLATFORM_NUM_DMACS] = {
-{
-	.plat_data = {
-		.id		= DMA_ID_HOST,
-		.dir		= SOF_DMA_DIR_HMEM_TO_LMEM | SOF_DMA_DIR_LMEM_TO_HMEM,
-		.devs		= SOF_DMA_DEV_HOST,
-		.channels	= 16,
-	},
-	.ops	= &dummy_dma_ops,
-},
-{
-	.plat_data = {
-		.id		= DMA_ID_SDMA3,
-		/* Note: support is available for MEM_TO_MEM but not
-		 * enabled as it is unneeded
-		 */
-		.dir		= SOF_DMA_DIR_MEM_TO_DEV | SOF_DMA_DIR_DEV_TO_MEM,
-		.devs		= SOF_DMA_DEV_SAI | SOF_DMA_DEV_MICFIL,
-		.base		= SDMA3_BASE,
-		.channels	= 32,
-		.irq		= SDMA3_IRQ,
-		.irq_name	= SDMA3_IRQ_NAME,
-	},
-	.ops	= &sdma_ops,
-},
-};
-
-static const struct dma_info lib_dma = {
-	.dma_array = cache_to_uncache_init((void *)dma),
-	.num_dmas = ARRAY_SIZE(dma)
-};
-
-int dmac_init(struct sof *sof)
-{
-	int i;
-
-	/* early lock initialization for ref counting */
-	for (i = 0; i < ARRAY_SIZE(dma); i++)
-		k_spinlock_init(&dma[i].lock);
-
-	sof->dma_info = &lib_dma;
-
-	return 0;
-}
diff --git a/src/platform/imx8m/lib/memory.c b/src/platform/imx8m/lib/memory.c
deleted file mode 100644
index 3f2eceee1afb..000000000000
--- a/src/platform/imx8m/lib/memory.c
+++ /dev/null
@@ -1,101 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-//
-// Copyright 2020 NXP
-//
-// Author: Daniel Baluta <daniel.baluta@nxp.com>
-
-#include <sof/common.h>
-#include <sof/lib/mm_heap.h>
-#include <sof/lib/memory.h>
-#include <sof/platform.h>
-#include <rtos/sof.h>
-#include <ipc/topology.h>
-
-/* Heap blocks for system runtime */
-static struct block_hdr sys_rt_block64[HEAP_SYS_RT_COUNT64];
-static struct block_hdr sys_rt_block512[HEAP_SYS_RT_COUNT512];
-static struct block_hdr sys_rt_block1024[HEAP_SYS_RT_COUNT1024];
-
-/* Heap memory for system runtime */
-static struct block_map sys_rt_heap_map[] = {
-	BLOCK_DEF(64, HEAP_SYS_RT_COUNT64, sys_rt_block64),
-	BLOCK_DEF(512, HEAP_SYS_RT_COUNT512, sys_rt_block512),
-	BLOCK_DEF(1024, HEAP_SYS_RT_COUNT1024, sys_rt_block1024),
-};
-
-/* Heap blocks for modules */
-static struct block_hdr mod_block16[HEAP_RT_COUNT16];
-static struct block_hdr mod_block32[HEAP_RT_COUNT32];
-static struct block_hdr mod_block64[HEAP_RT_COUNT64];
-static struct block_hdr mod_block128[HEAP_RT_COUNT128];
-static struct block_hdr mod_block256[HEAP_RT_COUNT256];
-static struct block_hdr mod_block512[HEAP_RT_COUNT512];
-static struct block_hdr mod_block1024[HEAP_RT_COUNT1024];
-static struct block_hdr mod_block2048[HEAP_RT_COUNT2048];
-static struct block_hdr mod_block4096[HEAP_RT_COUNT4096];
-
-/* Heap memory map for modules */
-static struct block_map rt_heap_map[] = {
-	BLOCK_DEF(16, HEAP_RT_COUNT16, mod_block16),
-	BLOCK_DEF(32, HEAP_RT_COUNT32, mod_block32),
-	BLOCK_DEF(64, HEAP_RT_COUNT64, mod_block64),
-	BLOCK_DEF(128, HEAP_RT_COUNT128, mod_block128),
-	BLOCK_DEF(256, HEAP_RT_COUNT256, mod_block256),
-	BLOCK_DEF(512, HEAP_RT_COUNT512, mod_block512),
-	BLOCK_DEF(1024, HEAP_RT_COUNT1024, mod_block1024),
-	BLOCK_DEF(2048, HEAP_RT_COUNT2048, mod_block2048),
-	BLOCK_DEF(4096, HEAP_RT_COUNT4096, mod_block4096),
-};
-
-/* Heap blocks for buffers */
-static struct block_hdr buf_block[HEAP_BUFFER_COUNT];
-
-/* Heap memory map for buffers */
-static struct block_map buf_heap_map[] = {
-	BLOCK_DEF(HEAP_BUFFER_BLOCK_SIZE, HEAP_BUFFER_COUNT, buf_block),
-};
-
-static struct mm memmap = {
-	.system[0] = {
-		.heap = HEAP_SYSTEM_BASE,
-		.size = HEAP_SYSTEM_SIZE,
-		.info = {.free = HEAP_SYSTEM_SIZE,},
-		.caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_CACHE |
-			SOF_MEM_CAPS_DMA,
-	},
-	.system_runtime[0] = {
-		.blocks = ARRAY_SIZE(sys_rt_heap_map),
-		.map = sys_rt_heap_map,
-		.heap = HEAP_SYS_RUNTIME_BASE,
-		.size = HEAP_SYS_RUNTIME_SIZE,
-		.info = {.free = HEAP_SYS_RUNTIME_SIZE,},
-		.caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_CACHE |
-			SOF_MEM_CAPS_DMA,
-	},
-	.runtime[0] = {
-		.blocks = ARRAY_SIZE(rt_heap_map),
-		.map = rt_heap_map,
-		.heap = HEAP_RUNTIME_BASE,
-		.size = HEAP_RUNTIME_SIZE,
-		.info = {.free = HEAP_RUNTIME_SIZE,},
-		.caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_CACHE |
-			SOF_MEM_CAPS_DMA,
-	},
-	.buffer[0] = {
-		.blocks = ARRAY_SIZE(buf_heap_map),
-		.map = buf_heap_map,
-		.heap = HEAP_BUFFER_BASE,
-		.size = HEAP_BUFFER_SIZE,
-		.info = {.free = HEAP_BUFFER_SIZE,},
-		.caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_CACHE |
-			SOF_MEM_CAPS_DMA,
-	},
-	.total = {.free = HEAP_SYSTEM_SIZE + HEAP_SYS_RUNTIME_SIZE +
-			HEAP_RUNTIME_SIZE + HEAP_BUFFER_SIZE,},
-};
-
-void platform_init_memmap(struct sof *sof)
-{
-	/* memmap has been initialized statically as a part of .data */
-	sof->memory_map = &memmap;
-}
diff --git a/src/platform/imx8ulp/CMakeLists.txt b/src/platform/imx8ulp/CMakeLists.txt
deleted file mode 100644
index ec909d60035f..000000000000
--- a/src/platform/imx8ulp/CMakeLists.txt
+++ /dev/null
@@ -1,5 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-
-add_subdirectory(lib)
-
-add_local_sources(sof platform.c)
diff --git a/src/platform/imx8ulp/lib/CMakeLists.txt b/src/platform/imx8ulp/lib/CMakeLists.txt
deleted file mode 100644
index 271a099cc6a9..000000000000
--- a/src/platform/imx8ulp/lib/CMakeLists.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-
-add_local_sources(sof
-	clk.c
-	dai.c
-	dma.c
-	memory.c
-)
diff --git a/src/platform/imx8ulp/lib/dai.c b/src/platform/imx8ulp/lib/dai.c
deleted file mode 100644
index 797bbc3260be..000000000000
--- a/src/platform/imx8ulp/lib/dai.c
+++ /dev/null
@@ -1,97 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-//
-// Copyright 2021 NXP
-//
-// Author: Zhang Peng <peng.zhang_8@nxp.com>
-
-#include <sof/common.h>
-#include <sof/drivers/edma.h>
-#include <sof/drivers/sai.h>
-#include <sof/lib/dai.h>
-#include <sof/lib/memory.h>
-#include <rtos/sof.h>
-#include <rtos/spinlock.h>
-#include <ipc/dai.h>
-#include <ipc/stream.h>
-
-static struct dai sai[] = {
-{
-	.index = 5,
-	.plat_data = {
-		.base = SAI_5_BASE,
-		.fifo[SOF_IPC_STREAM_PLAYBACK] = {
-			.offset		= SAI_5_BASE + REG_SAI_TDR0,
-			/* use depth to model the HW FIFO size:
-			 * each channel includes a 16 x 32 bit FIFO
-			 * that can be accessed using Transmit or
-			 * Receive Data Registers
-			 */
-			.depth		= 16,  /* in 4 bytes words */
-			.watermark      = 8,
-			.handshake	= EDMA_HANDSHAKE(IMX8ULP_EDMA2_CHAN0_IRQ,
-							 IMX8ULP_EDMA2_CHAN0,
-							 IMX8ULP_DMAMUX2_SAI5_TX),
-		},
-		.fifo[SOF_IPC_STREAM_CAPTURE] = {
-			.offset		= SAI_5_BASE + REG_SAI_RDR3,
-			.depth		= 16,  /* in 4 bytes words */
-			.watermark      = 8,
-			.handshake	= EDMA_HANDSHAKE(IMX8ULP_EDMA2_CHAN1_IRQ,
-							 IMX8ULP_EDMA2_CHAN1,
-							 IMX8ULP_DMAMUX2_SAI5_RX),
-		},
-	},
-	.drv = &sai_driver,
-},
-{
-	.index = 6,
-	.plat_data = {
-		.base = SAI_6_BASE,
-		.fifo[SOF_IPC_STREAM_PLAYBACK] = {
-			.offset		= SAI_6_BASE + REG_SAI_TDR2,
-			.depth		= 16,  /* in 4 bytes words */
-			.watermark      = 8,
-			.handshake	= EDMA_HANDSHAKE(IMX8ULP_EDMA2_CHAN0_IRQ,
-							 IMX8ULP_EDMA2_CHAN0,
-							 IMX8ULP_DMAMUX2_SAI6_TX),
-		},
-		.fifo[SOF_IPC_STREAM_CAPTURE] = {
-			.offset		= SAI_6_BASE + REG_SAI_RDR0,
-			.depth		= 16,  /* in 4 bytes words */
-			.watermark      = 8,
-			.handshake	= EDMA_HANDSHAKE(IMX8ULP_EDMA2_CHAN1_IRQ,
-							 IMX8ULP_EDMA2_CHAN1,
-							 IMX8ULP_DMAMUX2_SAI6_RX),
-		},
-	},
-	.drv = &sai_driver,
-},
-};
-
-const struct dai_type_info dti[] = {
-	{
-		.type = SOF_DAI_IMX_SAI,
-		.dai_array = cache_to_uncache_init((struct dai *)sai),
-		.num_dais = ARRAY_SIZE(sai)
-	},
-};
-
-const struct dai_info lib_dai = {
-	.dai_type_array = dti,
-	.num_dai_types = ARRAY_SIZE(dti)
-};
-
-int dai_init(struct sof *sof)
-{
-	int i;
-
-	 /* initialize spin locks early to enable ref counting */
-	for (i = 0; i < ARRAY_SIZE(sai); i++)
-		k_spinlock_init(&dti[0].dai_array[i].lock);
-
-	platform_shared_commit(sai, sizeof(*sai));
-
-	sof->dai_info = &lib_dai;
-
-	return 0;
-}
diff --git a/src/platform/imx8ulp/lib/dma.c b/src/platform/imx8ulp/lib/dma.c
deleted file mode 100644
index 81b3e0f09de2..000000000000
--- a/src/platform/imx8ulp/lib/dma.c
+++ /dev/null
@@ -1,65 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-//
-// Copyright 2021 NXP
-//
-// Author: Peng Zhang <peng.zhang_8@nxp.com>
-
-#include <sof/common.h>
-#include <sof/drivers/edma.h>
-#include <rtos/interrupt.h>
-#include <sof/lib/dma.h>
-#include <sof/lib/memory.h>
-#include <rtos/sof.h>
-#include <rtos/spinlock.h>
-
-extern struct dma_ops dummy_dma_ops;
-extern struct dma_ops edma_ops;
-
-static const int edma2_ints[IMX8ULP_EDMA2_CHAN_MAX] = {
-	[IMX8ULP_EDMA2_CHAN0] = IMX8ULP_EDMA2_CHAN0_IRQ,
-	[IMX8ULP_EDMA2_CHAN1] = IMX8ULP_EDMA2_CHAN1_IRQ,
-};
-
-static struct dma dma[PLATFORM_NUM_DMACS] = {
-{
-	.plat_data = {
-		.id		= DMA_ID_EDMA2,
-		.dir		= DMA_DIR_MEM_TO_DEV | DMA_DIR_DEV_TO_MEM,
-		.devs		= DMA_DEV_SAI,
-		.base		= EDMA2_BASE,
-		.chan_size	= EDMA2_SIZE,
-		.channels	= 8,
-		.drv_plat_data	= edma2_ints,
-	},
-	.ops	= &edma_ops,
-},
-{
-	.plat_data = {
-		.id		= DMA_ID_HOST,
-		.dir		= DMA_DIR_HMEM_TO_LMEM | DMA_DIR_LMEM_TO_HMEM,
-		.devs		= DMA_DEV_HOST,
-		.channels	= 16,
-	},
-	.ops	= &dummy_dma_ops,
-},
-};
-
-static const struct dma_info lib_dma = {
-	.dma_array = cache_to_uncache_init((struct dma *)dma),
-	.num_dmas = ARRAY_SIZE(dma)
-};
-
-int dmac_init(struct sof *sof)
-{
-	int i;
-
-	/* early lock initialization for ref counting */
-	for (i = 0; i < ARRAY_SIZE(dma); i++)
-		k_spinlock_init(&dma[i].lock);
-
-	platform_shared_commit(dma, sizeof(*dma));
-
-	sof->dma_info = &lib_dma;
-
-	return 0;
-}
diff --git a/src/platform/imx8ulp/lib/memory.c b/src/platform/imx8ulp/lib/memory.c
deleted file mode 100644
index 9224dae6e05f..000000000000
--- a/src/platform/imx8ulp/lib/memory.c
+++ /dev/null
@@ -1,100 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-//
-// Copyright 2021 NXP
-//
-// Author: Daniel Baluta <daniel.baluta@nxp.com>
-// Author: Zhang Peng  <peng.zhang_8@nxp.com>
-
-#include <sof/common.h>
-#include <sof/lib/mm_heap.h>
-#include <sof/lib/memory.h>
-#include <sof/platform.h>
-#include <rtos/sof.h>
-#include <ipc/topology.h>
-
-/* Heap blocks for system runtime */
-static struct block_hdr sys_rt_block64[HEAP_SYS_RT_COUNT64];
-static struct block_hdr sys_rt_block512[HEAP_SYS_RT_COUNT512];
-static struct block_hdr sys_rt_block1024[HEAP_SYS_RT_COUNT1024];
-
-/* Heap memory for system runtime */
-static struct block_map sys_rt_heap_map[] = {
-	BLOCK_DEF(64, HEAP_SYS_RT_COUNT64, sys_rt_block64),
-	BLOCK_DEF(512, HEAP_SYS_RT_COUNT512, sys_rt_block512),
-	BLOCK_DEF(1024, HEAP_SYS_RT_COUNT1024, sys_rt_block1024),
-};
-
-/* Heap blocks for modules */
-static struct block_hdr mod_block16[HEAP_RT_COUNT16];
-static struct block_hdr mod_block32[HEAP_RT_COUNT32];
-static struct block_hdr mod_block64[HEAP_RT_COUNT64];
-static struct block_hdr mod_block128[HEAP_RT_COUNT128];
-static struct block_hdr mod_block256[HEAP_RT_COUNT256];
-static struct block_hdr mod_block512[HEAP_RT_COUNT512];
-static struct block_hdr mod_block1024[HEAP_RT_COUNT1024];
-static struct block_hdr mod_block2048[HEAP_RT_COUNT2048];
-
-/* Heap memory map for modules */
-static struct block_map rt_heap_map[] = {
-	BLOCK_DEF(16, HEAP_RT_COUNT16, mod_block16),
-	BLOCK_DEF(32, HEAP_RT_COUNT32, mod_block32),
-	BLOCK_DEF(64, HEAP_RT_COUNT64, mod_block64),
-	BLOCK_DEF(128, HEAP_RT_COUNT128, mod_block128),
-	BLOCK_DEF(256, HEAP_RT_COUNT256, mod_block256),
-	BLOCK_DEF(512, HEAP_RT_COUNT512, mod_block512),
-	BLOCK_DEF(1024, HEAP_RT_COUNT1024, mod_block1024),
-	BLOCK_DEF(2048, HEAP_RT_COUNT2048, mod_block2048),
-};
-
-/* Heap blocks for buffers */
-static struct block_hdr buf_block[HEAP_BUFFER_COUNT];
-
-/* Heap memory map for buffers */
-static struct block_map buf_heap_map[] = {
-	BLOCK_DEF(HEAP_BUFFER_BLOCK_SIZE, HEAP_BUFFER_COUNT, buf_block),
-};
-
-static struct mm memmap = {
-	.system[0] = {
-		.heap = HEAP_SYSTEM_BASE,
-		.size = HEAP_SYSTEM_SIZE,
-		.info = {.free = HEAP_SYSTEM_SIZE,},
-		.caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_CACHE |
-			SOF_MEM_CAPS_DMA,
-	},
-	.system_runtime[0] = {
-		.blocks = ARRAY_SIZE(sys_rt_heap_map),
-		.map = sys_rt_heap_map,
-		.heap = HEAP_SYS_RUNTIME_BASE,
-		.size = HEAP_SYS_RUNTIME_SIZE,
-		.info = {.free = HEAP_SYS_RUNTIME_SIZE,},
-		.caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_CACHE |
-			SOF_MEM_CAPS_DMA,
-	},
-	.runtime[0] = {
-		.blocks = ARRAY_SIZE(rt_heap_map),
-		.map = rt_heap_map,
-		.heap = HEAP_RUNTIME_BASE,
-		.size = HEAP_RUNTIME_SIZE,
-		.info = {.free = HEAP_RUNTIME_SIZE,},
-		.caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_CACHE |
-			SOF_MEM_CAPS_DMA,
-	},
-	.buffer[0] = {
-		.blocks = ARRAY_SIZE(buf_heap_map),
-		.map = buf_heap_map,
-		.heap = HEAP_BUFFER_BASE,
-		.size = HEAP_BUFFER_SIZE,
-		.info = {.free = HEAP_BUFFER_SIZE,},
-		.caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_CACHE |
-			SOF_MEM_CAPS_DMA,
-	},
-	.total = {.free = HEAP_SYSTEM_SIZE + HEAP_SYS_RUNTIME_SIZE +
-			HEAP_RUNTIME_SIZE + HEAP_BUFFER_SIZE,},
-};
-
-void platform_init_memmap(struct sof *sof)
-{
-	/* memmap has been initialized statically as a part of .data */
-	sof->memory_map = &memmap;
-}
diff --git a/src/platform/imx93_a55/CMakeLists.txt b/src/platform/imx93_a55/CMakeLists.txt
deleted file mode 100644
index ec909d60035f..000000000000
--- a/src/platform/imx93_a55/CMakeLists.txt
+++ /dev/null
@@ -1,5 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-
-add_subdirectory(lib)
-
-add_local_sources(sof platform.c)
diff --git a/src/platform/imx93_a55/lib/dai.c b/src/platform/imx93_a55/lib/dai.c
deleted file mode 100644
index 5f1cb3f7e534..000000000000
--- a/src/platform/imx93_a55/lib/dai.c
+++ /dev/null
@@ -1,60 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-/*
- * Copyright 2023 NXP
- */
-
-#include <rtos/sof.h>
-#include <sof/drivers/sai.h>
-#include <sof/drivers/edma.h>
-#include <sof/lib/memory.h>
-
-static struct dai sai[] = {
-	{
-		.index = 3, /* SOF uses SAI3 */
-		.plat_data = {
-			.base = SAI3_BASE,
-			.fifo[SOF_IPC_STREAM_PLAYBACK] = {
-				.offset = SAI3_BASE + REG_SAI_TDR0,
-				.depth = 128, /* number of 32-bit words */
-				.watermark = 64, /* needs to be half the depth */
-				.handshake = EDMA_HANDSHAKE(EDMA2_SAI3_CHAN_TX_IRQ,
-							    EDMA2_SAI3_CHAN_TX,
-							    EDMA2_SAI3_TX_MUX),
-			},
-			.fifo[SOF_IPC_STREAM_CAPTURE] = {
-				.offset = SAI3_BASE + REG_SAI_RDR0,
-				.depth = 128,
-				.watermark = 64,
-				.handshake = EDMA_HANDSHAKE(EDMA2_SAI3_CHAN_RX_IRQ,
-							    EDMA2_SAI3_CHAN_RX,
-							    EDMA2_SAI3_RX_MUX),
-			},
-		},
-		.drv = &sai_driver,
-	},
-};
-
-static const struct dai_type_info dti[] = {
-	{
-		.type = SOF_DAI_IMX_SAI,
-		.dai_array = sai,
-		.num_dais = ARRAY_SIZE(sai),
-	},
-};
-
-static const struct dai_info lib_dai = {
-	.dai_type_array = dti,
-	.num_dai_types = ARRAY_SIZE(dti)
-};
-
-int dai_init(struct sof *sof)
-{
-	int i;
-
-	for (i = 0; i < ARRAY_SIZE(sai); i++)
-		k_spinlock_init(&dti[0].dai_array[i].lock);
-
-	sof->dai_info = &lib_dai;
-
-	return 0;
-}
diff --git a/src/platform/imx93_a55/lib/dma.c b/src/platform/imx93_a55/lib/dma.c
deleted file mode 100644
index 280748711647..000000000000
--- a/src/platform/imx93_a55/lib/dma.c
+++ /dev/null
@@ -1,58 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-/*
- * Copyright 2023 NXP
- */
-
-#include <rtos/sof.h>
-#include <sof/lib/dma.h>
-#include <sof/drivers/edma.h>
-
-extern struct dma_ops dummy_dma_ops;
-extern struct dma_ops edma_ops;
-
-static const int edma2_ints[EDMA2_CHAN_MAX] = {
-	[EDMA2_SAI3_CHAN_RX] = EDMA2_SAI3_CHAN_RX_IRQ,
-	[EDMA2_SAI3_CHAN_TX] = EDMA2_SAI3_CHAN_TX_IRQ,
-};
-
-static struct dma dma[PLATFORM_NUM_DMACS] = {
-	{
-		.plat_data = {
-			.id = DMA_ID_EDMA2,
-			.dir = DMA_DIR_MEM_TO_DEV | DMA_DIR_DEV_TO_MEM,
-			.devs = DMA_DEV_SAI,
-			.base = EDMA2_BASE,
-			.chan_size = EDMA2_CHAN_SIZE,
-			.channels = EDMA2_CHAN_MAX,
-			.drv_plat_data = edma2_ints,
-		},
-		.ops = &edma_ops,
-	},
-	{
-		.plat_data = {
-			.id = DMA_ID_HOST,
-			.dir = DMA_DIR_HMEM_TO_LMEM | DMA_DIR_LMEM_TO_HMEM,
-			.devs = DMA_DEV_HOST,
-			.channels = 16
-		},
-		.ops = &dummy_dma_ops,
-	},
-};
-
-static const struct dma_info lib_dma = {
-	.dma_array = dma,
-	.num_dmas = ARRAY_SIZE(dma)
-};
-
-int dmac_init(struct sof *sof)
-{
-	int i;
-
-	/* early lock initialization for ref counting */
-	for (i = 0; i < ARRAY_SIZE(dma); i++)
-		k_spinlock_init(&dma[i].lock);
-
-	sof->dma_info = &lib_dma;
-
-	return 0;
-}
diff --git a/src/platform/mt8186/CMakeLists.txt b/src/platform/mt8186/CMakeLists.txt
deleted file mode 100644
index 1b9e043186fe..000000000000
--- a/src/platform/mt8186/CMakeLists.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-
-add_subdirectory(lib)
-
-add_local_sources(sof platform.c afe-platform.c)
-target_include_directories(sof_options INTERFACE ${PROJECT_SOURCE_DIR}/src/platform/mt8186/include/arch)
-target_include_directories(sof_options INTERFACE ${PROJECT_SOURCE_DIR}/src/platform/mt8186/include/platform)
diff --git a/src/platform/mt8186/afe-platform.c b/src/platform/mt8186/afe-platform.c
deleted file mode 100644
index e91a6a01367f..000000000000
--- a/src/platform/mt8186/afe-platform.c
+++ /dev/null
@@ -1,300 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-/*
- * Copyright(c) 2022 MediaTek. All rights reserved.
- *
- * Author: Chunxu Li <chunxu.li@mediatek.com>
- */
-
-#include <sof/common.h>
-#include <errno.h>
-#include <sof/drivers/afe-drv.h>
-#include <mt8186-afe-regs.h>
-#include <mt8186-afe-common.h>
-
-/*
- * AFE: Audio Front-End
- *
- * frontend (memif):
- *   memory interface
- *   UL (uplink for capture)
- *   DL (downlink for playback)
- * backend:
- *   TDM In
- *   TMD Out
- *   DMIC
- *   GASRC
- *   I2S Out
- *   I2S In
- *   etc.
- * interconn:
- *   inter-connection,
- *   connect frontends and backends as DSP path
- */
-
-static const struct mtk_base_memif_data memif_data[MT8186_MEMIF_NUM] = {
-	[MT8186_MEMIF_DL1] = {
-		.name = "DL1",
-		.id = MT8186_MEMIF_DL1,
-		.reg_ofs_base = AFE_DL1_BASE,
-		.reg_ofs_cur = AFE_DL1_CUR,
-		.reg_ofs_end = AFE_DL1_END,
-		.reg_ofs_base_msb = AFE_DL1_BASE_MSB,
-		.reg_ofs_cur_msb = AFE_DL1_CUR_MSB,
-		.reg_ofs_end_msb = AFE_DL1_END_MSB,
-		.fs_reg = AFE_DL1_CON0,
-		.fs_shift = DL1_MODE_SFT,
-		.fs_maskbit = DL1_MODE_MASK,
-		.mono_reg = AFE_DL1_CON0,
-		.mono_shift = DL1_MONO_SFT,
-		.enable_reg = AFE_DAC_CON0,
-		.enable_shift = DL1_ON_SFT,
-		.hd_reg = AFE_DL1_CON0,
-		.hd_shift = DL1_HD_MODE_SFT,
-		.hd_align_reg = AFE_DL1_CON0,
-		.hd_align_mshift = DL1_HALIGN_SFT,
-		.agent_disable_reg = -1,
-		.agent_disable_shift = -1,
-		.ch_num_reg = -1,
-		.ch_num_shift = -1,
-		.ch_num_maskbit = -1,
-		.msb_reg = -1,
-		.msb_shift = -1,
-		.msb2_reg = -1,
-		.msb2_shift = -1,
-		.pbuf_reg = AFE_DL1_CON0,
-		.pbuf_mask = DL1_PBUF_SIZE_MASK,
-		.pbuf_shift = DL1_PBUF_SIZE_SFT,
-		.minlen_reg = AFE_DL1_CON0,
-		.minlen_mask = DL1_MINLEN_MASK,
-		.minlen_shift = DL1_MINLEN_SFT,
-	},
-	[MT8186_MEMIF_DL2] = {
-		.name = "DL2",
-		.id = MT8186_MEMIF_DL2,
-		.reg_ofs_base = AFE_DL2_BASE,
-		.reg_ofs_cur = AFE_DL2_CUR,
-		.reg_ofs_end = AFE_DL2_END,
-		.reg_ofs_base_msb = AFE_DL2_BASE_MSB,
-		.reg_ofs_cur_msb = AFE_DL2_CUR_MSB,
-		.reg_ofs_end_msb = AFE_DL2_END_MSB,
-		.fs_reg = AFE_DL2_CON0,
-		.fs_shift = DL2_MODE_SFT,
-		.fs_maskbit = DL2_MODE_MASK,
-		.mono_reg = AFE_DL2_CON0,
-		.mono_shift = DL2_MONO_SFT,
-		.enable_reg = AFE_DAC_CON0,
-		.enable_shift = DL2_ON_SFT,
-		.hd_reg = AFE_DL2_CON0,
-		.hd_shift = DL2_HD_MODE_SFT,
-		.hd_align_reg = AFE_DL2_CON0,
-		.hd_align_mshift = DL2_HALIGN_SFT,
-		.agent_disable_reg = -1,
-		.agent_disable_shift = -1,
-		.ch_num_reg = -1,
-		.ch_num_shift = -1,
-		.ch_num_maskbit = -1,
-		.msb_reg = -1,
-		.msb_shift = -1,
-		.msb2_reg = -1,
-		.msb2_shift = -1,
-		.pbuf_reg = AFE_DL2_CON0,
-		.pbuf_mask = DL2_PBUF_SIZE_MASK,
-		.pbuf_shift = DL2_PBUF_SIZE_SFT,
-		.minlen_reg = AFE_DL2_CON0,
-		.minlen_mask = DL2_MINLEN_MASK,
-		.minlen_shift = DL2_MINLEN_SFT,
-	},
-	[MT8186_MEMIF_UL1] = {
-		.name = "UL1",
-		.id = MT8186_MEMIF_UL1,
-		.reg_ofs_base = AFE_VUL12_BASE,
-		.reg_ofs_cur = AFE_VUL12_CUR,
-		.reg_ofs_end = AFE_VUL12_END,
-		.reg_ofs_base_msb = AFE_VUL12_BASE_MSB,
-		.reg_ofs_cur_msb = AFE_VUL12_CUR_MSB,
-		.reg_ofs_end_msb = AFE_VUL12_END_MSB,
-		.fs_reg = AFE_VUL12_CON0,
-		.fs_shift = VUL12_MODE_SFT,
-		.fs_maskbit = VUL12_MODE_MASK,
-		.mono_reg = AFE_VUL12_CON0,
-		.mono_shift = VUL12_MONO_SFT,
-		.quad_ch_reg = AFE_VUL12_CON0,
-		.quad_ch_mask = VUL12_4CH_EN_MASK,
-		.quad_ch_shift = VUL12_4CH_EN_SFT,
-		.enable_reg = AFE_DAC_CON0,
-		.enable_shift = VUL12_ON_SFT,
-		.hd_reg = AFE_VUL12_CON0,
-		.hd_shift = VUL12_HD_MODE_SFT,
-		.hd_align_reg = AFE_VUL12_CON0,
-		.hd_align_mshift = VUL12_HALIGN_SFT,
-		.agent_disable_reg = -1,
-		.agent_disable_shift = -1,
-		.ch_num_reg = -1,
-		.ch_num_shift = -1,
-		.ch_num_maskbit = -1,
-		.msb_reg = -1,
-		.msb_shift = -1,
-		.msb2_reg = -1,
-		.msb2_shift = -1,
-	},
-	[MT8186_MEMIF_UL2] = {
-		.name = "UL2",
-		.id = MT8186_MEMIF_UL2,
-		.reg_ofs_base = AFE_AWB_BASE,
-		.reg_ofs_cur = AFE_AWB_CUR,
-		.reg_ofs_end = AFE_AWB_END,
-		.reg_ofs_base_msb = AFE_AWB_BASE_MSB,
-		.reg_ofs_cur_msb = AFE_AWB_CUR_MSB,
-		.reg_ofs_end_msb = AFE_AWB_END_MSB,
-		.fs_reg = AFE_AWB_CON0,
-		.fs_shift = AWB_MODE_SFT,
-		.fs_maskbit = AWB_MODE_MASK,
-		.mono_reg = AFE_AWB_CON0,
-		.mono_shift = AWB_MONO_SFT,
-		.enable_reg = AFE_DAC_CON0,
-		.enable_shift = AWB_ON_SFT,
-		.hd_reg = AFE_AWB_CON0,
-		.hd_shift = AWB_HD_MODE_SFT,
-		.hd_align_reg = AFE_AWB_CON0,
-		.hd_align_mshift = AWB_HALIGN_SFT,
-		.agent_disable_reg = -1,
-		.agent_disable_shift = -1,
-		.ch_num_reg = -1,
-		.ch_num_shift = -1,
-		.ch_num_maskbit = -1,
-		.msb_reg = -1,
-		.msb_shift = -1,
-		.msb2_reg = -1,
-		.msb2_shift = -1,
-	}
-};
-
-struct mt8186_afe_rate {
-	unsigned int rate;
-	unsigned int reg_value;
-};
-
-enum {
-	MTK_AFE_RATE_8K = 0,
-	MTK_AFE_RATE_11K = 1,
-	MTK_AFE_RATE_12K = 2,
-	MTK_AFE_RATE_384K = 3,
-	MTK_AFE_RATE_16K = 4,
-	MTK_AFE_RATE_22K = 5,
-	MTK_AFE_RATE_24K = 6,
-	MTK_AFE_RATE_352K = 7,
-	MTK_AFE_RATE_32K = 8,
-	MTK_AFE_RATE_44K = 9,
-	MTK_AFE_RATE_48K = 10,
-	MTK_AFE_RATE_88K = 11,
-	MTK_AFE_RATE_96K = 12,
-	MTK_AFE_RATE_176K = 13,
-	MTK_AFE_RATE_192K = 14,
-	MTK_AFE_RATE_260K = 15,
-};
-
-static const struct mt8186_afe_rate mt8186_afe_rates[] = {
-	{
-		.rate = 8000,
-		.reg_value = MTK_AFE_RATE_8K,
-	},
-	{
-		.rate = 12000,
-		.reg_value = MTK_AFE_RATE_12K,
-	},
-	{
-		.rate = 16000,
-		.reg_value = MTK_AFE_RATE_16K,
-	},
-	{
-		.rate = 24000,
-		.reg_value = MTK_AFE_RATE_24K,
-	},
-	{
-		.rate = 32000,
-		.reg_value = MTK_AFE_RATE_32K,
-	},
-	{
-		.rate = 48000,
-		.reg_value = MTK_AFE_RATE_48K,
-	},
-	{
-		.rate = 96000,
-		.reg_value = MTK_AFE_RATE_96K,
-	},
-	{
-		.rate = 192000,
-		.reg_value = MTK_AFE_RATE_192K,
-	},
-	{
-		.rate = 384000,
-		.reg_value = MTK_AFE_RATE_384K,
-	},
-	{
-		.rate = 11025,
-		.reg_value = MTK_AFE_RATE_11K,
-	},
-	{
-		.rate = 22050,
-		.reg_value = MTK_AFE_RATE_22K,
-	},
-	{
-		.rate = 44100,
-		.reg_value = MTK_AFE_RATE_44K,
-	},
-	{
-		.rate = 88200,
-		.reg_value = MTK_AFE_RATE_88K,
-	},
-	{
-		.rate = 176400,
-		.reg_value = MTK_AFE_RATE_176K,
-	},
-	{
-		.rate = 352800,
-		.reg_value = MTK_AFE_RATE_352K,
-	},
-};
-
-static unsigned int mt8186_afe_fs_timing(unsigned int rate)
-{
-	int i;
-
-	for (i = 0; i < ARRAY_SIZE(mt8186_afe_rates); i++)
-		if (mt8186_afe_rates[i].rate == rate)
-			return mt8186_afe_rates[i].reg_value;
-
-	return -EINVAL;
-}
-
-static unsigned int mt8186_afe_fs(unsigned int rate, int aud_blk)
-{
-	return mt8186_afe_fs_timing(rate);
-}
-
-static unsigned int mt8186_afe2adsp_addr(unsigned int addr)
-{
-	/*TODO : Need apply the address remap */
-	return addr;
-}
-
-static unsigned int mt8186_adsp2afe_addr(unsigned int addr)
-{
-	/* TODO : Need apply the address remap */
-	return addr;
-}
-
-struct mtk_base_afe_platform mtk_afe_platform = {
-	.base_addr = AFE_BASE_ADDR,
-	.memif_datas = memif_data,
-	.memif_size = MT8186_MEMIF_NUM,
-	.memif_dl_num = MT8186_MEMIF_DL_NUM,
-	.memif_32bit_supported = 0,
-	.irq_datas = NULL,
-	.irqs_size = 0,
-	.dais_size = MT8186_DAI_NUM,
-	.afe2adsp_addr = mt8186_afe2adsp_addr,
-	.adsp2afe_addr = mt8186_adsp2afe_addr,
-	.afe_fs = mt8186_afe_fs,
-	.irq_fs = mt8186_afe_fs_timing,
-};
diff --git a/src/platform/mt8186/include/arch/xtensa/config/core-isa.h b/src/platform/mt8186/include/arch/xtensa/config/core-isa.h
deleted file mode 100644
index 79bee81a1ff1..000000000000
--- a/src/platform/mt8186/include/arch/xtensa/config/core-isa.h
+++ /dev/null
@@ -1,805 +0,0 @@
-/* 
- * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
- *				processor CORE configuration
- *
- *  See <xtensa/config/core.h>, which includes this file, for more details.
- */
-
-/* Xtensa processor core configuration information.
-
-   Customer ID=16990; Build=0x904d8; Copyright (c) 1999-2020 Tensilica Inc.
-
-   Permission is hereby granted, free of charge, to any person obtaining
-   a copy of this software and associated documentation files (the
-   "Software"), to deal in the Software without restriction, including
-   without limitation the rights to use, copy, modify, merge, publish,
-   distribute, sublicense, and/or sell copies of the Software, and to
-   permit persons to whom the Software is furnished to do so, subject to
-   the following conditions:
-
-   The above copyright notice and this permission notice shall be included
-   in all copies or substantial portions of the Software.
-
-   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
-
-#ifndef XTENSA_CORE_CONFIGURATION_H_
-#define XTENSA_CORE_CONFIGURATION_H_
-
-
-/****************************************************************************
-	    Parameters Useful for Any Code, USER or PRIVILEGED
- ****************************************************************************/
-
-/*
- *  Note:  Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
- *  configured, and a value of 0 otherwise.  These macros are always defined.
- */
-
-
-/*----------------------------------------------------------------------
-				ISA
-  ----------------------------------------------------------------------*/
-
-#define XCHAL_HAVE_BE			0	/* big-endian byte ordering */
-#define XCHAL_HAVE_WINDOWED		1	/* windowed registers option */
-#define XCHAL_NUM_AREGS			64	/* num of physical addr regs */
-#define XCHAL_NUM_AREGS_LOG2		6	/* log2(XCHAL_NUM_AREGS) */
-#define XCHAL_MAX_INSTRUCTION_SIZE	16	/* max instr bytes (3..8) */
-#define XCHAL_HAVE_DEBUG		1	/* debug option */
-#define XCHAL_HAVE_DENSITY		1	/* 16-bit instructions */
-#define XCHAL_HAVE_LOOPS		1	/* zero-overhead loops */
-#define XCHAL_LOOP_BUFFER_SIZE		256	/* zero-ov. loop instr buffer size */
-#define XCHAL_HAVE_NSA			1	/* NSA/NSAU instructions */
-#define XCHAL_HAVE_MINMAX		1	/* MIN/MAX instructions */
-#define XCHAL_HAVE_SEXT			1	/* SEXT instruction */
-#define XCHAL_HAVE_DEPBITS		0	/* DEPBITS instruction */
-#define XCHAL_HAVE_CLAMPS		1	/* CLAMPS instruction */
-#define XCHAL_HAVE_MUL16		1	/* MUL16S/MUL16U instructions */
-#define XCHAL_HAVE_MUL32		1	/* MULL instruction */
-#define XCHAL_HAVE_MUL32_HIGH		0	/* MULUH/MULSH instructions */
-#define XCHAL_HAVE_DIV32		1	/* QUOS/QUOU/REMS/REMU instructions */
-#define XCHAL_HAVE_L32R			1	/* L32R instruction */
-#define XCHAL_HAVE_ABSOLUTE_LITERALS	0	/* non-PC-rel (extended) L32R */
-#define XCHAL_HAVE_CONST16		0	/* CONST16 instruction */
-#define XCHAL_HAVE_ADDX			1	/* ADDX#/SUBX# instructions */
-#define XCHAL_HAVE_EXCLUSIVE            1	/* L32EX/S32EX instructions */
-#define XCHAL_HAVE_WIDE_BRANCHES	0	/* B*.W18 or B*.W15 instr's */
-#define XCHAL_HAVE_PREDICTED_BRANCHES	0	/* B[EQ/EQZ/NE/NEZ]T instr's */
-#define XCHAL_HAVE_CALL4AND12		1	/* (obsolete option) */
-#define XCHAL_HAVE_ABS			1	/* ABS instruction */
-#define XCHAL_HAVE_RELEASE_SYNC		1	/* L32AI/S32RI instructions */
-#define XCHAL_HAVE_S32C1I		0	/* S32C1I instruction */
-#define XCHAL_HAVE_SPECULATION		0	/* speculation */
-#define XCHAL_HAVE_FULL_RESET		1	/* all regs/state reset */
-#define XCHAL_NUM_CONTEXTS		1	/* */
-#define XCHAL_NUM_MISC_REGS		4	/* num of scratch regs (0..4) */
-#define XCHAL_HAVE_TAP_MASTER		0	/* JTAG TAP control instr's */
-#define XCHAL_HAVE_PRID			1	/* processor ID register */
-#define XCHAL_HAVE_EXTERN_REGS		1	/* WER/RER instructions */
-#define XCHAL_HAVE_MX			0	/* MX core (Tensilica internal) */
-#define XCHAL_HAVE_MP_INTERRUPTS	0	/* interrupt distributor port */
-#define XCHAL_HAVE_MP_RUNSTALL		0	/* core RunStall control port */
-#define XCHAL_HAVE_PSO			0	/* Power Shut-Off */
-#define XCHAL_HAVE_PSO_CDM		0	/* core/debug/mem pwr domains */
-#define XCHAL_HAVE_PSO_FULL_RETENTION	0	/* all regs preserved on PSO */
-#define XCHAL_HAVE_THREADPTR		1	/* THREADPTR register */
-#define XCHAL_HAVE_BOOLEANS		1	/* boolean registers */
-#define XCHAL_HAVE_CP			1	/* CPENABLE reg (coprocessor) */
-#define XCHAL_CP_MAXCFG			2	/* max allowed cp id plus one */
-#define XCHAL_HAVE_MAC16		0	/* MAC16 package */
-#define XCHAL_HAVE_LX			1	/* LX core */
-#define XCHAL_HAVE_NX			0	/* NX core (starting RH) */
-
-#define XCHAL_HAVE_SUPERGATHER		0	/* SuperGather */
-
-#define XCHAL_HAVE_FUSION		0	/* Fusion*/
-#define XCHAL_HAVE_FUSION_FP		0	/* Fusion FP option */
-#define XCHAL_HAVE_FUSION_LOW_POWER	0	/* Fusion Low Power option */
-#define XCHAL_HAVE_FUSION_AES		0	/* Fusion BLE/Wifi AES-128 CCM option */
-#define XCHAL_HAVE_FUSION_CONVENC	0	/* Fusion Conv Encode option */
-#define XCHAL_HAVE_FUSION_LFSR_CRC	0	/* Fusion LFSR-CRC option */
-#define XCHAL_HAVE_FUSION_BITOPS	0	/* Fusion Bit Operations Support option */
-#define XCHAL_HAVE_FUSION_AVS		0	/* Fusion AVS option */
-#define XCHAL_HAVE_FUSION_16BIT_BASEBAND 0	/* Fusion 16-bit Baseband option */
-#define XCHAL_HAVE_FUSION_VITERBI	0	/* Fusion Viterbi option */
-#define XCHAL_HAVE_FUSION_SOFTDEMAP	0	/* Fusion Soft Bit Demap option */
-#define XCHAL_HAVE_HIFIPRO		0	/* HiFiPro Audio Engine pkg */
-#define XCHAL_HAVE_HIFI5		1	/* HiFi5 Audio Engine pkg */
-#define XCHAL_HAVE_HIFI5_NN_MAC		1	/* HiFi5 Audio Engine NN-MAC option */
-#define XCHAL_HAVE_HIFI5_VFPU		1	/* HiFi5 Audio Engine Single-Precision VFPU option */
-#define XCHAL_HAVE_HIFI5_HP_VFPU	1	/* HiFi5 Audio Engine Half-Precision VFPU option */
-#define XCHAL_HAVE_HIFI4		0	/* HiFi4 Audio Engine pkg */
-#define XCHAL_HAVE_HIFI4_VFPU		1	/* HiFi4 Audio Engine VFPU option */
-#define XCHAL_HAVE_HIFI3		1	/* HiFi3 Audio Engine pkg */
-#define XCHAL_HAVE_HIFI3_VFPU		1	/* HiFi3 Audio Engine VFPU option */
-#define XCHAL_HAVE_HIFI3Z		0	/* HiFi3Z Audio Engine pkg */
-#define XCHAL_HAVE_HIFI3Z_VFPU	0	/* HiFi3Z Audio Engine VFPU option */
-#define XCHAL_HAVE_HIFI2		0	/* HiFi2 Audio Engine pkg */
-#define XCHAL_HAVE_HIFI2EP		0	/* HiFi2EP */
-#define XCHAL_HAVE_HIFI_MINI		0	
-
-
-
-#define XCHAL_HAVE_VECTORFPU2005	0	/* vector floating-point pkg */
-#define XCHAL_HAVE_USER_DPFPU		0       /* user DP floating-point pkg */
-#define XCHAL_HAVE_USER_SPFPU		1       /* user SP floating-point pkg */
-#define XCHAL_HAVE_FP			1	/* single prec floating point */
-#define XCHAL_HAVE_FP_DIV		1	/* FP with DIV instructions */
-#define XCHAL_HAVE_FP_RECIP		1	/* FP with RECIP instructions */
-#define XCHAL_HAVE_FP_SQRT		1	/* FP with SQRT instructions */
-#define XCHAL_HAVE_FP_RSQRT		1	/* FP with RSQRT instructions */
-#define XCHAL_HAVE_DFP			0	/* double precision FP pkg */
-#define XCHAL_HAVE_DFP_DIV		0	/* DFP with DIV instructions */
-#define XCHAL_HAVE_DFP_RECIP		0	/* DFP with RECIP instructions*/
-#define XCHAL_HAVE_DFP_SQRT		0	/* DFP with SQRT instructions */
-#define XCHAL_HAVE_DFP_RSQRT		0	/* DFP with RSQRT instructions*/
-#define XCHAL_HAVE_DFP_ACCEL		0	/* double precision FP acceleration pkg */
-#define XCHAL_HAVE_DFP_accel		XCHAL_HAVE_DFP_ACCEL	/* for backward compatibility */
-
-#define XCHAL_HAVE_DFPU_SINGLE_ONLY	0	/* DFPU Coprocessor, single precision only */
-#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE	0	/* DFPU Coprocessor, single and double precision */
-#define XCHAL_HAVE_VECTRA1		0	/* Vectra I  pkg */
-#define XCHAL_HAVE_VECTRALX		0	/* Vectra LX pkg */
-
-#define XCHAL_HAVE_FUSIONG		0    /* FusionG */
-#define XCHAL_HAVE_FUSIONG3		0    /* FusionG3 */
-#define XCHAL_HAVE_FUSIONG6		0    /* FusionG6 */
-#define XCHAL_HAVE_FUSIONG_SP_VFPU	0    /* sp_vfpu option on FusionG */
-#define XCHAL_HAVE_FUSIONG_DP_VFPU	0    /* dp_vfpu option on FusionG */
-#define XCHAL_FUSIONG_SIMD32		0    /* simd32 for FusionG */
-
-#define XCHAL_HAVE_FUSIONJ		0    /* FusionJ */
-#define XCHAL_HAVE_FUSIONJ6		0    /* FusionJ6 */
-#define XCHAL_HAVE_FUSIONJ_SP_VFPU	0    /* sp_vfpu option on FusionJ */
-#define XCHAL_HAVE_FUSIONJ_DP_VFPU	0    /* dp_vfpu option on FusionJ */
-#define XCHAL_FUSIONJ_SIMD32		0    /* simd32 for FusionJ */
-
-#define XCHAL_HAVE_PDX			0    /* PDX-LX */
-#define XCHAL_PDX_SIMD32		0    /* simd32 for PDX */
-#define XCHAL_HAVE_PDX4			0    /* PDX4-LX */
-#define XCHAL_HAVE_PDX8			0    /* PDX8-LX */
-#define XCHAL_HAVE_PDX16		0    /* PDX16-LX */
-#define XCHAL_HAVE_PDXNX 		0    /* PDX-NX */
-
-#define XCHAL_HAVE_CONNXD2		0	/* ConnX D2 pkg */
-#define XCHAL_HAVE_CONNXD2_DUALLSFLIX   0	/* ConnX D2 & Dual LoadStore Flix */
-#define XCHAL_HAVE_BALL			0
-#define XCHAL_HAVE_BALLAP		0
-#define XCHAL_HAVE_BBE16		0	/* ConnX BBE16 pkg */
-#define XCHAL_HAVE_BBE16_RSQRT		0	/* BBE16 & vector recip sqrt */
-#define XCHAL_HAVE_BBE16_VECDIV		0	/* BBE16 & vector divide */
-#define XCHAL_HAVE_BBE16_DESPREAD	0	/* BBE16 & despread */
-#define XCHAL_HAVE_CONNX_B10            0    /* ConnX B10 pkg*/
-#define XCHAL_HAVE_CONNX_B20            0    /* ConnX B20 pkg*/
-#define XCHAL_HAVE_CONNX_B_DP_VFPU      0    /* Double-precision Vector Floating-point option on ConnX B10 & B20 */
-#define XCHAL_HAVE_CONNX_B_SP_VFPU      0    /* Single-precision Vector Floating-point option on ConnX B10 & B20 */
-#define XCHAL_HAVE_CONNX_B_SPX_VFPU     0    /* Single-precision Extended Vector Floating-point option on ConnX B10 & B20 */
-#define XCHAL_HAVE_CONNX_B_HPX_VFPU     0    /* Half-precision Extended Vector Floating-point option on ConnX B10 & B20 */
-#define XCHAL_HAVE_CONNX_B_32B_MAC      0    /* 32-bit vector MAC (real and complex), FIR & FFT option on ConnX B10 & B20 */
-#define XCHAL_HAVE_CONNX_B_VITERBI      0    /* Viterbi option on ConnX B10 & B20 */
-#define XCHAL_HAVE_CONNX_B_TURBO        0    /* Turbo option on ConnX B10 & B20 */
-#define XCHAL_HAVE_CONNX_B_LDPC         0    /* LDPC option on ConnX B10 & B20 */
-#define XCHAL_HAVE_BBENEP		0	/* ConnX BBENEP pkgs */
-#define XCHAL_HAVE_BBENEP_SP_VFPU	0       /* sp_vfpu option on BBE-EP */
-#define XCHAL_HAVE_BSP3			0	/* ConnX BSP3 pkg */
-#define XCHAL_HAVE_BSP3_TRANSPOSE	0	/* BSP3 & transpose32x32 */
-#define XCHAL_HAVE_SSP16		0	/* ConnX SSP16 pkg */
-#define XCHAL_HAVE_SSP16_VITERBI	0	/* SSP16 & viterbi */
-#define XCHAL_HAVE_TURBO16		0	/* ConnX Turbo16 pkg */
-#define XCHAL_HAVE_BBP16		0	/* ConnX BBP16 pkg */
-#define XCHAL_HAVE_FLIX3		0	/* basic 3-way FLIX option */
-#define XCHAL_HAVE_GRIVPEP		0	/* General Release of IVPEP */
-#define XCHAL_HAVE_GRIVPEP_HISTOGRAM	0       /* Histogram option on GRIVPEP */
-
-#define XCHAL_HAVE_VISION	        0     /* Vision P5/P6 */
-#define XCHAL_VISION_SIMD16             0     /* simd16 for Vision P5/P6 */
-#define XCHAL_VISION_TYPE               0     /* Vision P5, P6, Q6, Q7 or Q8 */
-#define XCHAL_VISION_QUAD_MAC_TYPE      0     /* quad_mac option on Vision P6 */
-#define XCHAL_HAVE_VISION_HISTOGRAM     0     /* histogram option on Vision P5/P6 */
-#define XCHAL_HAVE_VISION_DP_VFPU       0     /* dp_vfpu option on Vision Q7/Q8 */
-#define XCHAL_HAVE_VISION_SP_VFPU       0     /* sp_vfpu option on Vision P5/P6/Q6/Q7 */
-#define XCHAL_HAVE_VISION_SP_VFPU_2XFMAC 0     /* sp_vfpu_2xfma option on Vision Q7 */
-#define XCHAL_HAVE_VISION_HP_VFPU       0     /* hp_vfpu option on Vision P6/Q6 */
-#define XCHAL_HAVE_VISION_HP_VFPU_2XFMAC 0     /* hp_vfpu_2xfma option on Vision Q7 */
-
-#define XCHAL_HAVE_VISIONC	        0     /* Vision C */
-
-#define XCHAL_HAVE_XNNE			0		/* XNNE */
-
-/*----------------------------------------------------------------------
-				MISC
-  ----------------------------------------------------------------------*/
-
-#define XCHAL_NUM_LOADSTORE_UNITS	2	/* load/store units */
-#define XCHAL_NUM_WRITEBUFFER_ENTRIES	32	/* size of write buffer */
-#define XCHAL_INST_FETCH_WIDTH		16	/* instr-fetch width in bytes */
-#define XCHAL_DATA_WIDTH		16	/* data width in bytes */
-#define XCHAL_DATA_PIPE_DELAY		2	/* d-side pipeline delay
-						   (1 = 5-stage, 2 = 7-stage) */
-#define XCHAL_CLOCK_GATING_GLOBAL	1	/* global clock gating */
-#define XCHAL_CLOCK_GATING_FUNCUNIT	1	/* funct. unit clock gating */
-/*  In T1050, applies to selected core load and store instructions (see ISA): */
-#define XCHAL_UNALIGNED_LOAD_EXCEPTION	1	/* unaligned loads cause exc. */
-#define XCHAL_UNALIGNED_STORE_EXCEPTION	1	/* unaligned stores cause exc.*/
-#define XCHAL_UNALIGNED_LOAD_HW		0	/* unaligned loads work in hw */
-#define XCHAL_UNALIGNED_STORE_HW	0	/* unaligned stores work in hw*/
-
-#define XCHAL_UNIFIED_LOADSTORE         0
-
-#define XCHAL_SW_VERSION		1405000	/* sw version of this header */
-#define XCHAL_SW_VERSION_MAJOR		14000	/* major ver# of sw          */
-#define XCHAL_SW_VERSION_MINOR		5	/* minor ver# of sw          */
-#define XCHAL_SW_VERSION_MICRO		0	/* micro ver# of sw          */
-#define XCHAL_SW_MINOR_VERSION		1405000	/* with zeroed micro */
-#define XCHAL_SW_MICRO_VERSION		1405000
-
-#define XCHAL_CORE_ID			"hifi5_7stg_I64D128"	/* alphanum core name
-						   (CoreID) set in the Xtensa
-						   Processor Generator */
-
-#define XCHAL_BUILD_UNIQUE_ID		0x000904D8	/* 22-bit sw build ID */
-
-/*
- *  These definitions describe the hardware targeted by this software.
- */
-#define XCHAL_HW_CONFIGID0		0xC003B286	/* ConfigID hi 32 bits*/
-#define XCHAL_HW_CONFIGID1		0x294904D8	/* ConfigID lo 32 bits*/
-#define XCHAL_HW_VERSION_NAME		"LX7.1.5"	/* full version name */
-#define XCHAL_HW_VERSION_MAJOR		2810	/* major ver# of targeted hw */
-#define XCHAL_HW_VERSION_MINOR		5	/* minor ver# of targeted hw */
-#define XCHAL_HW_VERSION_MICRO		0	/* subdot ver# of targeted hw */
-#define XCHAL_HW_VERSION		281050	/* major*100+(major<2810 ? minor : minor*10+micro) */
-#define XCHAL_HW_REL_LX7		1
-#define XCHAL_HW_REL_LX7_1		1
-#define XCHAL_HW_REL_LX7_1_5		1
-#define XCHAL_HW_CONFIGID_RELIABLE	1
-/*  If software targets a *range* of hardware versions, these are the bounds: */
-#define XCHAL_HW_MIN_VERSION_MAJOR	2810	/* major v of earliest tgt hw */
-#define XCHAL_HW_MIN_VERSION_MINOR	5	/* minor v of earliest tgt hw */
-#define XCHAL_HW_MIN_VERSION_MICRO	0	/* micro v of earliest tgt hw */
-#define XCHAL_HW_MIN_VERSION		281050	/* earliest targeted hw */
-#define XCHAL_HW_MAX_VERSION_MAJOR	2810	/* major v of latest tgt hw */
-#define XCHAL_HW_MAX_VERSION_MINOR	5	/* minor v of latest tgt hw */
-#define XCHAL_HW_MAX_VERSION_MICRO	0	/* micro v of latest tgt hw */
-#define XCHAL_HW_MAX_VERSION		281050	/* latest targeted hw */
-
-/*  Config is enabled for functional safety: */
-#define XCHAL_HAVE_FUNC_SAFETY		0
-
-/*  Config is enabled for secure operation: */
-#define XCHAL_HAVE_SECURE     		0
-
-#define XCHAL_HAVE_APB			0 
-
-/*----------------------------------------------------------------------
-				CACHE
-  ----------------------------------------------------------------------*/
-
-#define XCHAL_ICACHE_LINESIZE		128	/* I-cache line size in bytes */
-#define XCHAL_DCACHE_LINESIZE		128	/* D-cache line size in bytes */
-#define XCHAL_ICACHE_LINEWIDTH		7	/* log2(I line size in bytes) */
-#define XCHAL_DCACHE_LINEWIDTH		7	/* log2(D line size in bytes) */
-
-#define XCHAL_ICACHE_SIZE		65536	/* I-cache size in bytes or 0 */
-#define XCHAL_ICACHE_SIZE_LOG2		16
-#define XCHAL_DCACHE_SIZE		131072	/* D-cache size in bytes or 0 */
-#define XCHAL_DCACHE_SIZE_LOG2		17
-
-#define XCHAL_DCACHE_IS_WRITEBACK	1	/* writeback feature */
-#define XCHAL_DCACHE_IS_COHERENT	0	/* MP coherence feature */
-
-#define XCHAL_HAVE_PREFETCH		1	/* PREFCTL register */
-#define XCHAL_HAVE_PREFETCH_L1		1	/* prefetch to L1 cache */
-#define XCHAL_PREFETCH_CASTOUT_LINES	2	/* dcache pref. castout bufsz */
-#define XCHAL_PREFETCH_ENTRIES		16	/* cache prefetch entries */
-#define XCHAL_PREFETCH_BLOCK_ENTRIES	8	/* prefetch block streams */
-#define XCHAL_HAVE_CACHE_BLOCKOPS	1	/* block prefetch for caches */
-#define XCHAL_HAVE_CME_DOWNGRADES	0
-#define XCHAL_HAVE_ICACHE_TEST		1	/* Icache test instructions */
-#define XCHAL_HAVE_DCACHE_TEST		1	/* Dcache test instructions */
-#define XCHAL_HAVE_ICACHE_DYN_WAYS	1	/* Icache dynamic way support */
-#define XCHAL_HAVE_DCACHE_DYN_WAYS	1	/* Dcache dynamic way support */
-#define XCHAL_HAVE_ICACHE_DYN_ENABLE	1	/* Icache enabled via MEMCTL */
-#define XCHAL_HAVE_DCACHE_DYN_ENABLE	1	/* Dcache enabled via MEMCTL */
-
-#define XCHAL_L1SCACHE_SIZE		         0
-#define XCHAL_L1SCACHE_SIZE_LOG2		 0
-#define XCHAL_L1SCACHE_WAYS              1
-#define XCHAL_L1SCACHE_WAYS_LOG2         0
-#define XCHAL_L1SCACHE_ACCESS_SIZE       0
-#define XCHAL_L1SCACHE_BANKS             1
-
-#define XCHAL_HAVE_L2			0	/* NX L2 cache controller */
-#define XCHAL_HAVE_L2_CACHE		0
-#define XCHAL_NUM_CORES_IN_CLUSTER	0
-
-/* PRID_ID macros are for internal use only ... subject to removal */
-#define PRID_ID_SHIFT           0
-#define PRID_ID_BITS            4
-#define PRID_ID_MASK            0x0000000F
-
-/*  This one is a form of caching, though not architecturally visible:  */
-#define XCHAL_HAVE_BRANCH_PREDICTION	0	/* branch [target] prediction */
-
-
-
-
-/****************************************************************************
-    Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
- ****************************************************************************/
-
-
-#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
-
-/*----------------------------------------------------------------------
-				CACHE
-  ----------------------------------------------------------------------*/
-
-#define XCHAL_HAVE_PIF			1	/* any outbound bus present */
-
-#define XCHAL_HAVE_AXI			1	/* AXI bus */
-#define XCHAL_HAVE_AXI_ECC		1	/* ECC on AXI bus */
-#define XCHAL_HAVE_ACELITE		0	/* ACELite bus */
-
-#define XCHAL_HAVE_PIF_WR_RESP			1	/* pif write response */
-#define XCHAL_HAVE_PIF_REQ_ATTR			1	/* pif attribute */
-
-/*  If present, cache size in bytes == (ways * 2^(linewidth + setwidth)).  */
-
-/*  Number of cache sets in log2(lines per way):  */
-#define XCHAL_ICACHE_SETWIDTH		7
-#define XCHAL_DCACHE_SETWIDTH		8
-
-/*  Cache set associativity (number of ways):  */
-#define XCHAL_ICACHE_WAYS		4
-#define XCHAL_ICACHE_WAYS_LOG2		2
-#define XCHAL_DCACHE_WAYS		4
-#define XCHAL_DCACHE_WAYS_LOG2		2
-
-/*  Cache features:  */
-#define XCHAL_ICACHE_LINE_LOCKABLE	1
-#define XCHAL_DCACHE_LINE_LOCKABLE	1
-#define XCHAL_ICACHE_ECC_PARITY		0
-#define XCHAL_DCACHE_ECC_PARITY		0
-#define XCHAL_ICACHE_ECC_WIDTH		4
-#define XCHAL_DCACHE_ECC_WIDTH		1
-
-/*  Cache access size in bytes (affects operation of SICW instruction):  */
-#define XCHAL_ICACHE_ACCESS_SIZE	16
-#define XCHAL_DCACHE_ACCESS_SIZE	16
-
-#define XCHAL_DCACHE_BANKS		2	/* number of banks */
-
-/* The number of Cache lines associated with a single cache tag */
-#define XCHAL_DCACHE_LINES_PER_TAG_LOG2	0
-
-/*  Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits):  */
-
-
-/*----------------------------------------------------------------------
-			INTERNAL I/D RAM/ROMs and XLMI
-  ----------------------------------------------------------------------*/
-#define XCHAL_NUM_INSTROM		0	/* number of core instr. ROMs */
-#define XCHAL_NUM_INSTRAM		2	/* number of core instr. RAMs */
-#define XCHAL_NUM_DATAROM		0	/* number of core data ROMs */
-#define XCHAL_NUM_DATARAM		1	/* number of core data RAMs */
-#define XCHAL_NUM_URAM			0	/* number of core unified RAMs*/
-#define XCHAL_NUM_XLMI			0	/* number of core XLMI ports */
-#define	XCHAL_HAVE_IRAMCFG		0	/* IRAMxCFG register present */
-#define	XCHAL_HAVE_DRAMCFG		0	/* DRAMxCFG register present */
-
-/*  Instruction RAM 0:  */
-#define XCHAL_INSTRAM0_VADDR		0x3FFF0000	/* virtual address */
-#define XCHAL_INSTRAM0_PADDR		0x3FFF0000	/* physical address */
-#define XCHAL_INSTRAM0_SIZE		32768	/* size in bytes */
-#define XCHAL_INSTRAM0_ECC_PARITY	0	/* ECC/parity type, 0=none */
-#define XCHAL_HAVE_INSTRAM0		1
-#define XCHAL_INSTRAM0_HAVE_IDMA	0	/* idma supported by this local memory */
-
-/*  Instruction RAM 1:  */
-#define XCHAL_INSTRAM1_VADDR		0x3FFF8000	/* virtual address */
-#define XCHAL_INSTRAM1_PADDR		0x3FFF8000	/* physical address */
-#define XCHAL_INSTRAM1_SIZE		4096	/* size in bytes */
-#define XCHAL_INSTRAM1_ECC_PARITY	0	/* ECC/parity type, 0=none */
-#define XCHAL_HAVE_INSTRAM1		1
-#define XCHAL_INSTRAM1_HAVE_IDMA	0	/* idma supported by this local memory */
-
-/*  Data RAM 0:  */
-#define XCHAL_DATARAM0_VADDR		0x3FFE8000	/* virtual address */
-#define XCHAL_DATARAM0_PADDR		0x3FFE8000	/* physical address */
-#define XCHAL_DATARAM0_SIZE		32768	/* size in bytes */
-#define XCHAL_DATARAM0_ECC_PARITY	0	/* ECC/parity type, 0=none */
-#define XCHAL_DATARAM0_BANKS		2	/* number of banks */
-#define XCHAL_HAVE_DATARAM0		1
-#define XCHAL_DATARAM0_HAVE_IDMA	0	/* idma supported by this local memory */
-
-#define XCHAL_HAVE_IMEM_LOADSTORE	1	/* can load/store to IROM/IRAM*/
-
-
-/*----------------------------------------------------------------------
-			IDMA
-  ----------------------------------------------------------------------*/
-
-#define XCHAL_HAVE_IDMA			0
-
-
-
-/*----------------------------------------------------------------------
-			INTERRUPTS and TIMERS
-  ----------------------------------------------------------------------*/
-
-#define XCHAL_HAVE_INTERRUPTS		1	/* interrupt option */
-#define XCHAL_HAVE_NMI			1	/* non-maskable interrupt */
-#define XCHAL_HAVE_CCOUNT		1	/* CCOUNT reg. (timer option) */
-#define XCHAL_NUM_TIMERS		3	/* number of CCOMPAREn regs */
-#define XCHAL_NUM_INTERRUPTS		32	/* number of interrupts */
-#define XCHAL_NUM_INTERRUPTS_LOG2	5	/* ceil(log2(NUM_INTERRUPTS)) */
-#define XCHAL_NUM_EXTINTERRUPTS		26	/* num of external interrupts */
-#define XCHAL_NUM_INTLEVELS		5	/* number of interrupt levels
-						   (not including level zero) */
-
-
-#define XCHAL_HAVE_HIGHPRI_INTERRUPTS	1   /* med/high-pri. interrupts */
-#define XCHAL_EXCM_LEVEL		3	/* level masked by PS.EXCM */
-	/* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
-
-/*  Masks of interrupts at each interrupt level:  */
-#define XCHAL_INTLEVEL1_MASK		0x040000FF
-#define XCHAL_INTLEVEL2_MASK		0xA800FF00
-#define XCHAL_INTLEVEL3_MASK		0x518F0000
-#define XCHAL_INTLEVEL4_MASK		0x00700000
-#define XCHAL_INTLEVEL5_MASK		0x00000000
-#define XCHAL_INTLEVEL6_MASK		0x02000000
-#define XCHAL_INTLEVEL7_MASK		0x00000000
-
-/*  Masks of interrupts at each range 1..n of interrupt levels:  */
-#define XCHAL_INTLEVEL1_ANDBELOW_MASK	0x040000FF
-#define XCHAL_INTLEVEL2_ANDBELOW_MASK	0xAC00FFFF
-#define XCHAL_INTLEVEL3_ANDBELOW_MASK	0xFD8FFFFF
-#define XCHAL_INTLEVEL4_ANDBELOW_MASK	0xFDFFFFFF
-#define XCHAL_INTLEVEL5_ANDBELOW_MASK	0xFDFFFFFF
-#define XCHAL_INTLEVEL6_ANDBELOW_MASK	0xFFFFFFFF
-#define XCHAL_INTLEVEL7_ANDBELOW_MASK	0xFFFFFFFF
-
-/*  Level of each interrupt:  */
-#define XCHAL_INT0_LEVEL		1
-#define XCHAL_INT1_LEVEL		1
-#define XCHAL_INT2_LEVEL		1
-#define XCHAL_INT3_LEVEL		1
-#define XCHAL_INT4_LEVEL		1
-#define XCHAL_INT5_LEVEL		1
-#define XCHAL_INT6_LEVEL		1
-#define XCHAL_INT7_LEVEL		1
-#define XCHAL_INT8_LEVEL		2
-#define XCHAL_INT9_LEVEL		2
-#define XCHAL_INT10_LEVEL		2
-#define XCHAL_INT11_LEVEL		2
-#define XCHAL_INT12_LEVEL		2
-#define XCHAL_INT13_LEVEL		2
-#define XCHAL_INT14_LEVEL		2
-#define XCHAL_INT15_LEVEL		2
-#define XCHAL_INT16_LEVEL		3
-#define XCHAL_INT17_LEVEL		3
-#define XCHAL_INT18_LEVEL		3
-#define XCHAL_INT19_LEVEL		3
-#define XCHAL_INT20_LEVEL		4
-#define XCHAL_INT21_LEVEL		4
-#define XCHAL_INT22_LEVEL		4
-#define XCHAL_INT23_LEVEL		3
-#define XCHAL_INT24_LEVEL		3
-#define XCHAL_INT25_LEVEL		6
-#define XCHAL_INT26_LEVEL		1
-#define XCHAL_INT27_LEVEL		2
-#define XCHAL_INT28_LEVEL		3
-#define XCHAL_INT29_LEVEL		2
-#define XCHAL_INT30_LEVEL		3
-#define XCHAL_INT31_LEVEL		2
-#define XCHAL_DEBUGLEVEL		5	/* debug interrupt level */
-#define XCHAL_HAVE_DEBUG_EXTERN_INT	1	/* OCD external db interrupt */
-#define XCHAL_NMILEVEL			6	/* NMI "level" (for use with
-						   EXCSAVE/EPS/EPC_n, RFI n) */
-
-/*  Type of each interrupt:  */
-#define XCHAL_INT0_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT1_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT2_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT3_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT4_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT5_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT6_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT7_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT8_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT9_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT10_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT11_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT12_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT13_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT14_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT15_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT16_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT17_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT18_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT19_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT20_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT21_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT22_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT23_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
-#define XCHAL_INT24_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
-#define XCHAL_INT25_TYPE 	XTHAL_INTTYPE_NMI
-#define XCHAL_INT26_TYPE 	XTHAL_INTTYPE_TIMER
-#define XCHAL_INT27_TYPE 	XTHAL_INTTYPE_TIMER
-#define XCHAL_INT28_TYPE 	XTHAL_INTTYPE_TIMER
-#define XCHAL_INT29_TYPE 	XTHAL_INTTYPE_PROFILING
-#define XCHAL_INT30_TYPE 	XTHAL_INTTYPE_WRITE_ERROR
-#define XCHAL_INT31_TYPE 	XTHAL_INTTYPE_SOFTWARE
-
-/*  Masks of interrupts for each type of interrupt:  */
-#define XCHAL_INTTYPE_MASK_UNCONFIGURED	0x00000000
-#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL	0x007FFFFF
-#define XCHAL_INTTYPE_MASK_EXTERN_EDGE	0x01800000
-#define XCHAL_INTTYPE_MASK_NMI		0x02000000
-#define XCHAL_INTTYPE_MASK_SOFTWARE	0x80000000
-#define XCHAL_INTTYPE_MASK_TIMER	0x1C000000
-#define XCHAL_INTTYPE_MASK_ETIE		0x00000000
-#define XCHAL_INTTYPE_MASK_WRITE_ERROR	0x40000000
-#define XCHAL_INTTYPE_MASK_DBG_REQUEST	0x00000000
-#define XCHAL_INTTYPE_MASK_BREAKIN	0x00000000
-#define XCHAL_INTTYPE_MASK_TRAX		0x00000000
-#define XCHAL_INTTYPE_MASK_PROFILING	0x20000000
-#define XCHAL_INTTYPE_MASK_IDMA_DONE	0x00000000
-#define XCHAL_INTTYPE_MASK_IDMA_ERR	0x00000000
-#define XCHAL_INTTYPE_MASK_GS_ERR	0x00000000
-#define XCHAL_INTTYPE_MASK_L2_ERR	0x00000000
-#define XCHAL_INTTYPE_MASK_L2_STATUS	0x00000000
-#define XCHAL_INTTYPE_MASK_COR_ECC_ERR	0x00000000
-#define XCHAL_INTTYPE_MASK_WWDT		0x00000000
-
-/*  Interrupt numbers assigned to specific interrupt sources:  */
-#define XCHAL_TIMER0_INTERRUPT		26	/* CCOMPARE0 */
-#define XCHAL_TIMER1_INTERRUPT		27	/* CCOMPARE1 */
-#define XCHAL_TIMER2_INTERRUPT		28	/* CCOMPARE2 */
-#define XCHAL_TIMER3_INTERRUPT		XTHAL_TIMER_UNCONFIGURED
-#define XCHAL_NMI_INTERRUPT		25	/* non-maskable interrupt */
-#define XCHAL_WRITE_ERROR_INTERRUPT	30
-#define XCHAL_PROFILING_INTERRUPT	29
-
-/*  Interrupt numbers for levels at which only one interrupt is configured:  */
-#define XCHAL_INTLEVEL6_NUM		25
-/*  (There are many interrupts each at level(s) 1, 2, 3, 4.)  */
-
-
-/*
- *  External interrupt mapping.
- *  These macros describe how Xtensa processor interrupt numbers
- *  (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
- *  map to external BInterrupt<n> pins, for those interrupts
- *  configured as external (level-triggered, edge-triggered, or NMI).
- *  See the Xtensa processor databook for more details.
- */
-
-/*  Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number:  */
-#define XCHAL_EXTINT0_NUM		0	/* (intlevel 1) */
-#define XCHAL_EXTINT1_NUM		1	/* (intlevel 1) */
-#define XCHAL_EXTINT2_NUM		2	/* (intlevel 1) */
-#define XCHAL_EXTINT3_NUM		3	/* (intlevel 1) */
-#define XCHAL_EXTINT4_NUM		4	/* (intlevel 1) */
-#define XCHAL_EXTINT5_NUM		5	/* (intlevel 1) */
-#define XCHAL_EXTINT6_NUM		6	/* (intlevel 1) */
-#define XCHAL_EXTINT7_NUM		7	/* (intlevel 1) */
-#define XCHAL_EXTINT8_NUM		8	/* (intlevel 2) */
-#define XCHAL_EXTINT9_NUM		9	/* (intlevel 2) */
-#define XCHAL_EXTINT10_NUM		10	/* (intlevel 2) */
-#define XCHAL_EXTINT11_NUM		11	/* (intlevel 2) */
-#define XCHAL_EXTINT12_NUM		12	/* (intlevel 2) */
-#define XCHAL_EXTINT13_NUM		13	/* (intlevel 2) */
-#define XCHAL_EXTINT14_NUM		14	/* (intlevel 2) */
-#define XCHAL_EXTINT15_NUM		15	/* (intlevel 2) */
-#define XCHAL_EXTINT16_NUM		16	/* (intlevel 3) */
-#define XCHAL_EXTINT17_NUM		17	/* (intlevel 3) */
-#define XCHAL_EXTINT18_NUM		18	/* (intlevel 3) */
-#define XCHAL_EXTINT19_NUM		19	/* (intlevel 3) */
-#define XCHAL_EXTINT20_NUM		20	/* (intlevel 4) */
-#define XCHAL_EXTINT21_NUM		21	/* (intlevel 4) */
-#define XCHAL_EXTINT22_NUM		22	/* (intlevel 4) */
-#define XCHAL_EXTINT23_NUM		23	/* (intlevel 3) */
-#define XCHAL_EXTINT24_NUM		24	/* (intlevel 3) */
-#define XCHAL_EXTINT25_NUM		25	/* (intlevel 6) */
-/*  EXTERNAL BInterrupt pin numbers mapped to each core interrupt number:  */
-#define XCHAL_INT0_EXTNUM		0	/* (intlevel 1) */
-#define XCHAL_INT1_EXTNUM		1	/* (intlevel 1) */
-#define XCHAL_INT2_EXTNUM		2	/* (intlevel 1) */
-#define XCHAL_INT3_EXTNUM		3	/* (intlevel 1) */
-#define XCHAL_INT4_EXTNUM		4	/* (intlevel 1) */
-#define XCHAL_INT5_EXTNUM		5	/* (intlevel 1) */
-#define XCHAL_INT6_EXTNUM		6	/* (intlevel 1) */
-#define XCHAL_INT7_EXTNUM		7	/* (intlevel 1) */
-#define XCHAL_INT8_EXTNUM		8	/* (intlevel 2) */
-#define XCHAL_INT9_EXTNUM		9	/* (intlevel 2) */
-#define XCHAL_INT10_EXTNUM		10	/* (intlevel 2) */
-#define XCHAL_INT11_EXTNUM		11	/* (intlevel 2) */
-#define XCHAL_INT12_EXTNUM		12	/* (intlevel 2) */
-#define XCHAL_INT13_EXTNUM		13	/* (intlevel 2) */
-#define XCHAL_INT14_EXTNUM		14	/* (intlevel 2) */
-#define XCHAL_INT15_EXTNUM		15	/* (intlevel 2) */
-#define XCHAL_INT16_EXTNUM		16	/* (intlevel 3) */
-#define XCHAL_INT17_EXTNUM		17	/* (intlevel 3) */
-#define XCHAL_INT18_EXTNUM		18	/* (intlevel 3) */
-#define XCHAL_INT19_EXTNUM		19	/* (intlevel 3) */
-#define XCHAL_INT20_EXTNUM		20	/* (intlevel 4) */
-#define XCHAL_INT21_EXTNUM		21	/* (intlevel 4) */
-#define XCHAL_INT22_EXTNUM		22	/* (intlevel 4) */
-#define XCHAL_INT23_EXTNUM		23	/* (intlevel 3) */
-#define XCHAL_INT24_EXTNUM		24	/* (intlevel 3) */
-#define XCHAL_INT25_EXTNUM		25	/* (intlevel 6) */
-
-#define	XCHAL_HAVE_ISB			0	/* No ISB */
-#define	XCHAL_ISB_VADDR			0	/* N/A    */
-#define	XCHAL_HAVE_ITB			0	/* No ITB */
-#define	XCHAL_ITB_VADDR			0	/* N/A    */
-
-#define	XCHAL_HAVE_KSL			0	/* Kernel Stack Limit */
-#define	XCHAL_HAVE_ISL			0	/* Interrupt Stack Limit */
-#define	XCHAL_HAVE_PSL			0	/* Pageable Stack Limit */
-
-
-/*----------------------------------------------------------------------
-			EXCEPTIONS and VECTORS
-  ----------------------------------------------------------------------*/
-
-#define XCHAL_XEA_VERSION		2	/* Xtensa Exception Architecture
-						   number: 1 == XEA1 (until T1050)
-							   2 == XEA2 (T1040 onwards)
-							   3 == XEA3 (LX8/NX/SX onwards)
-							   0 == XEAX (extern) or TX */
-#define XCHAL_HAVE_XEA1			0	/* Exception Architecture 1 */
-#define XCHAL_HAVE_XEA2			1	/* Exception Architecture 2 */
-#define XCHAL_HAVE_XEA3			0	/* Exception Architecture 3 */
-#define XCHAL_HAVE_XEAX			0	/* External Exception Arch. */
-#define XCHAL_HAVE_EXCEPTIONS		1	/* exception option */
-#define XCHAL_HAVE_IMPRECISE_EXCEPTIONS	0	/* imprecise exception option */
-#define	XCHAL_EXCCAUSE_NUM		64	/* Number of exceptions */
-#define XCHAL_HAVE_HALT			0	/* halt architecture option */
-#define XCHAL_HAVE_BOOTLOADER		0	/* boot loader (for TX) */
-#define XCHAL_HAVE_MEM_ECC_PARITY	0	/* local memory ECC/parity */
-#define XCHAL_HAVE_VECTOR_SELECT	1	/* relocatable vectors */
-#define XCHAL_HAVE_VECBASE		1	/* relocatable vectors */
-#define XCHAL_VECBASE_RESET_VADDR	0x4e100400  /* VECBASE reset value */
-#define XCHAL_VECBASE_RESET_PADDR	0x4e100400
-#define XCHAL_RESET_VECBASE_OVERLAP	0	/* UNUSED */
-
-#define XCHAL_RESET_VECTOR0_VADDR	0x4e100000
-#define XCHAL_RESET_VECTOR0_PADDR	0x4e100000
-#define XCHAL_RESET_VECTOR1_VADDR	0x4e100800
-#define XCHAL_RESET_VECTOR1_PADDR	0x4e100800
-#define XCHAL_RESET_VECTOR_VADDR	XCHAL_RESET_VECTOR1_VADDR
-#define XCHAL_RESET_VECTOR_PADDR	XCHAL_RESET_VECTOR1_PADDR
-#define XCHAL_USER_VECOFS		0x00000250
-#define XCHAL_USER_VECTOR_VADDR		0x4e100650
-#define XCHAL_USER_VECTOR_PADDR		0x4e100650
-#define XCHAL_KERNEL_VECOFS		0x00000230
-#define XCHAL_KERNEL_VECTOR_VADDR	0x4e100630
-#define XCHAL_KERNEL_VECTOR_PADDR	0x4e100630
-#define XCHAL_DOUBLEEXC_VECOFS		0x00000270
-#define XCHAL_DOUBLEEXC_VECTOR_VADDR	0x4e100670
-#define XCHAL_DOUBLEEXC_VECTOR_PADDR	0x4e100670
-#define XCHAL_WINDOW_OF4_VECOFS		0x00000000
-#define XCHAL_WINDOW_UF4_VECOFS		0x00000040
-#define XCHAL_WINDOW_OF8_VECOFS		0x00000080
-#define XCHAL_WINDOW_UF8_VECOFS		0x000000C0
-#define XCHAL_WINDOW_OF12_VECOFS	0x00000100
-#define XCHAL_WINDOW_UF12_VECOFS	0x00000140
-#define XCHAL_WINDOW_VECTORS_VADDR	0x4e100400
-#define XCHAL_WINDOW_VECTORS_PADDR	0x4e100400
-#define XCHAL_INTLEVEL2_VECOFS		0x00000180
-#define XCHAL_INTLEVEL2_VECTOR_VADDR	0x4e100580
-#define XCHAL_INTLEVEL2_VECTOR_PADDR	0x4e100580
-#define XCHAL_INTLEVEL3_VECOFS		0x000001A4
-#define XCHAL_INTLEVEL3_VECTOR_VADDR	0x4e1005A4
-#define XCHAL_INTLEVEL3_VECTOR_PADDR	0x4e1005A4
-#define XCHAL_INTLEVEL4_VECOFS		0x000001C8
-#define XCHAL_INTLEVEL4_VECTOR_VADDR	0x4e1005C8
-#define XCHAL_INTLEVEL4_VECTOR_PADDR	0x4e1005C8
-#define XCHAL_INTLEVEL5_VECOFS		0x000001EC
-#define XCHAL_INTLEVEL5_VECTOR_VADDR	0x4e1005EC
-#define XCHAL_INTLEVEL5_VECTOR_PADDR	0x4e1005EC
-#define XCHAL_DEBUG_VECOFS		XCHAL_INTLEVEL5_VECOFS
-#define XCHAL_DEBUG_VECTOR_VADDR	XCHAL_INTLEVEL5_VECTOR_VADDR
-#define XCHAL_DEBUG_VECTOR_PADDR	XCHAL_INTLEVEL5_VECTOR_PADDR
-#define XCHAL_NMI_VECOFS		0x00000210
-#define XCHAL_NMI_VECTOR_VADDR		0x4e100610
-#define XCHAL_NMI_VECTOR_PADDR		0x4e100610
-#define XCHAL_INTLEVEL6_VECOFS		XCHAL_NMI_VECOFS
-#define XCHAL_INTLEVEL6_VECTOR_VADDR	XCHAL_NMI_VECTOR_VADDR
-#define XCHAL_INTLEVEL6_VECTOR_PADDR	XCHAL_NMI_VECTOR_PADDR
-
-
-/*----------------------------------------------------------------------
-				DEBUG MODULE
-  ----------------------------------------------------------------------*/
-
-/*  Misc  */
-#define XCHAL_HAVE_DEBUG_ERI		1	/* ERI to debug module */
-#define XCHAL_HAVE_DEBUG_APB		1	/* APB to debug module */
-#define XCHAL_HAVE_DEBUG_JTAG		1	/* JTAG to debug module */
-
-/*  On-Chip Debug (OCD)  */
-#define XCHAL_HAVE_OCD			1	/* OnChipDebug option */
-#define XCHAL_NUM_IBREAK		2	/* number of IBREAKn regs */
-#define XCHAL_NUM_DBREAK		2	/* number of DBREAKn regs */
-#define XCHAL_HAVE_OCD_DIR_ARRAY	0	/* faster OCD option (to LX4) */
-#define XCHAL_HAVE_OCD_LS32DDR		1	/* L32DDR/S32DDR (faster OCD) */
-
-/*  TRAX (in core)  */
-#define XCHAL_HAVE_TRAX			1	/* TRAX in debug module */
-#define XCHAL_TRAX_MEM_SIZE		4096	/* TRAX memory size in bytes */
-#define XCHAL_TRAX_MEM_SHAREABLE	1	/* start/end regs; ready sig. */
-#define XCHAL_TRAX_ATB_WIDTH		32	/* ATB width (bits), 0=no ATB */
-#define XCHAL_TRAX_TIME_WIDTH		64	/* timestamp bitwidth, 0=none */
-
-/*  Perf counters  */
-#define XCHAL_NUM_PERF_COUNTERS		8	/* performance counters */
-
-
-/*----------------------------------------------------------------------
-				MMU
-  ----------------------------------------------------------------------*/
-
-/*  See core-matmap.h header file for more details.  */
-
-#define XCHAL_HAVE_TLBS			0	/* inverse of HAVE_CACHEATTR */
-#define XCHAL_HAVE_SPANNING_WAY		0	/* one way maps I+D 4GB vaddr */
-#define XCHAL_HAVE_IDENTITY_MAP		1	/* vaddr == paddr always */
-#define XCHAL_HAVE_CACHEATTR		0	/* CACHEATTR register present */
-#define XCHAL_HAVE_MIMIC_CACHEATTR	0	/* region protection */
-#define XCHAL_HAVE_XLT_CACHEATTR	0	/* region prot. w/translation */
-#define XCHAL_HAVE_PTP_MMU		0	/* full MMU (with page table
-						   [autorefill] and protection)
-						   usable for an MMU-based OS */
-
-/*  If none of the above last 5 are set, it's a custom TLB configuration.  */
-
-#define XCHAL_MMU_ASID_BITS		0	/* number of bits in ASIDs */
-#define XCHAL_MMU_RINGS			1	/* number of rings (1..4) */
-#define XCHAL_MMU_RING_BITS		0	/* num of bits in RING field */
-
-/*----------------------------------------------------------------------
-				MPU
-  ----------------------------------------------------------------------*/
-#define XCHAL_HAVE_MPU			1 
-#define XCHAL_MPU_ENTRIES		32
-#define XCHAL_MPU_LOCK			0
-
-#define XCHAL_MPU_ALIGN_REQ		1	/* MPU requires alignment of entries to background map */
-#define XCHAL_MPU_BACKGROUND_ENTRIES	2	/* number of entries in bg map*/
-#define XCHAL_MPU_BG_CACHEADRDIS	0xFF	/* default CACHEADRDIS for bg */
- 
-#define XCHAL_MPU_ALIGN_BITS		12
-#define XCHAL_MPU_ALIGN			4096
-
-/*-----------------------------------------------------------------------
-				CSR Parity
-------------------------------------------------------------------------*/
-#define XCHAL_HAVE_CSR_PARITY		0
-
-
-/*----------------------------------------------------------------------
-				FLEX-LOCK
-------------------------------------------------------------------------*/
-
-#define XCHAL_HAVE_FXLK			0
-
-/*----------------------------------------------------------------------
-				WWDT (Windowed Watchdog Timer)
-------------------------------------------------------------------------*/
-#define XCHAL_HAVE_WWDT			0
-#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
-
-
-#endif /* XTENSA_CORE_CONFIGURATION_H_ */
-
diff --git a/src/platform/mt8186/include/arch/xtensa/config/core-matmap.h b/src/platform/mt8186/include/arch/xtensa/config/core-matmap.h
deleted file mode 100644
index 8a0056ca9c21..000000000000
--- a/src/platform/mt8186/include/arch/xtensa/config/core-matmap.h
+++ /dev/null
@@ -1,106 +0,0 @@
-/* 
- * xtensa/config/core-matmap.h -- Memory access and translation mapping
- *	parameters (CHAL) of the Xtensa processor core configuration.
- *
- *  If you are using Xtensa Tools, see <xtensa/config/core.h> (which includes
- *  this file) for more details.
- *
- *  In the Xtensa processor products released to date, all parameters
- *  defined in this file are derivable (at least in theory) from
- *  information contained in the core-isa.h header file.
- *  In particular, the following core configuration parameters are relevant:
- *	XCHAL_HAVE_CACHEATTR
- *	XCHAL_HAVE_MIMIC_CACHEATTR
- *	XCHAL_HAVE_XLT_CACHEATTR
- *	XCHAL_HAVE_PTP_MMU
- *	XCHAL_ITLB_ARF_ENTRIES_LOG2
- *	XCHAL_DTLB_ARF_ENTRIES_LOG2
- *	XCHAL_DCACHE_IS_WRITEBACK
- *	XCHAL_ICACHE_SIZE		(presence of I-cache)
- *	XCHAL_DCACHE_SIZE		(presence of D-cache)
- *	XCHAL_HW_VERSION_MAJOR
- *	XCHAL_HW_VERSION_MINOR
- */
-
-/* Customer ID=16990; Build=0x904d8; Copyright (c) 1999-2020 Tensilica Inc.
-
-   Permission is hereby granted, free of charge, to any person obtaining
-   a copy of this software and associated documentation files (the
-   "Software"), to deal in the Software without restriction, including
-   without limitation the rights to use, copy, modify, merge, publish,
-   distribute, sublicense, and/or sell copies of the Software, and to
-   permit persons to whom the Software is furnished to do so, subject to
-   the following conditions:
-
-   The above copyright notice and this permission notice shall be included
-   in all copies or substantial portions of the Software.
-
-   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
-
-
-#ifndef XTENSA_CONFIG_CORE_MATMAP_H
-#define XTENSA_CONFIG_CORE_MATMAP_H
-
-
-/*----------------------------------------------------------------------
-			CACHE (MEMORY ACCESS) ATTRIBUTES
-  ----------------------------------------------------------------------*/
-/*----------------------------------------------------------------------
-				MPU
-  ----------------------------------------------------------------------*/
-
-/* Mappings for legacy constants where appropriate */
-
-#define XCHAL_CA_WRITEBACK (XTHAL_MEM_WRITEBACK | XTHAL_AR_RWXrwx)
-
-#define XCHAL_CA_WRITEBACK_NOALLOC (XTHAL_MEM_WRITEBACK_NOALLOC| XTHAL_AR_RWXrwx )
-
-#define XCHAL_CA_WRITETHRU (XTHAL_MEM_WRITETHRU | XTHAL_AR_RWXrwx)
-
-#define XCHAL_CA_ILLEGAL   (XTHAL_AR_NONE   | XTHAL_MEM_DEVICE)
-#define XCHAL_CA_BYPASS    (XTHAL_AR_RWXrwx | XTHAL_MEM_DEVICE)
-#define XCHAL_CA_BYPASSBUF    (XTHAL_AR_RWXrwx | XTHAL_MEM_DEVICE |\
-        XTHAL_MEM_BUFFERABLE)
-#define XCHAL_CA_BYPASS_RX (XTHAL_AR_RX     | XTHAL_MEM_DEVICE)
-#define XCHAL_CA_BYPASS_RW (XTHAL_AR_RW     | XTHAL_MEM_DEVICE)
-#define XCHAL_CA_BYPASS_R  (XTHAL_AR_R      | XTHAL_MEM_DEVICE)
-#define XCHAL_HAVE_CA_WRITEBACK_NOALLOC 1
-
-#define XCHAL_CA_R  (XTHAL_AR_R)
-#define XCHAL_CA_RX (XTHAL_AR_RX) 
-#define XCHAL_CA_RW (XTHAL_AR_RW) 
-#define XCHAL_CA_RWX (XTHAL_AR_RWX)
-
-
-/* 
- * Contents of MPU background map.
- * NOTE:  caller must define the XCHAL_MPU_BGMAP() macro (not defined here
- * but specified below) before expanding the XCHAL_MPU_BACKGROUND_MAP(s) macro.
- *
- * XCHAL_MPU_BGMAP(s, vaddr_start, vaddr_last, rights, memtype, x...)
- *
- *	s = passed from XCHAL_MPU_BACKGROUND_MAP(s), eg. to select how to expand
- *	vaddr_start = first byte of region (always 0 for first entry)
- *	vaddr_end = last byte of region (always 0xFFFFFFFF for last entry)
- *	rights = access rights
- *	memtype = memory type
- *	x = reserved for future use (0 until then)
- */
-/* parasoft-begin-suppress MISRA2012-RULE-20_7 "Macro use model requires s to not be in ()" */
-#define XCHAL_MPU_BACKGROUND_MAP(s) \
-	XCHAL_MPU_BGMAP(s, 0x00000000, 0x7fffffff,  7,   6, 0) \
-	XCHAL_MPU_BGMAP(s, 0x80000000, 0xffffffff,  7,   6, 0) \
-/* parasoft-end-suppress MISRA2012-RULE-20_7 "Macro use model requires s to not be in ()" */
-
-	/* end */
-
-
-
-#endif /*XTENSA_CONFIG_CORE_MATMAP_H*/
-
diff --git a/src/platform/mt8186/include/arch/xtensa/config/defs.h b/src/platform/mt8186/include/arch/xtensa/config/defs.h
deleted file mode 100644
index be3cf59f6756..000000000000
--- a/src/platform/mt8186/include/arch/xtensa/config/defs.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/* Definitions for Xtensa instructions, types, and protos. */
-
-/* Customer ID=16990; Build=0x904d8; Copyright (c) 2003-2004 Tensilica Inc.
-
-   Permission is hereby granted, free of charge, to any person obtaining
-   a copy of this software and associated documentation files (the
-   "Software"), to deal in the Software without restriction, including
-   without limitation the rights to use, copy, modify, merge, publish,
-   distribute, sublicense, and/or sell copies of the Software, and to
-   permit persons to whom the Software is furnished to do so, subject to
-   the following conditions:
-
-   The above copyright notice and this permission notice shall be included
-   in all copies or substantial portions of the Software.
-
-   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
-
-/* NOTE: This file exists only for backward compatibility with T1050
-   and earlier Xtensa releases.  It includes only a subset of the
-   available header files.  */
-
-#ifndef _XTENSA_BASE_HEADER
-#define _XTENSA_BASE_HEADER
-
-#ifdef __XTENSA__
-
-#include <xtensa/tie/xt_core.h>
-#include <xtensa/tie/xt_misc.h>
-#include <xtensa/tie/xt_booleans.h>
-
-#endif /* __XTENSA__ */
-#endif /* !_XTENSA_BASE_HEADER */
diff --git a/src/platform/mt8186/include/arch/xtensa/config/key.h b/src/platform/mt8186/include/arch/xtensa/config/key.h
deleted file mode 100644
index 8b137891791f..000000000000
--- a/src/platform/mt8186/include/arch/xtensa/config/key.h
+++ /dev/null
@@ -1 +0,0 @@
-
diff --git a/src/platform/mt8186/include/arch/xtensa/config/secure.h b/src/platform/mt8186/include/arch/xtensa/config/secure.h
deleted file mode 100644
index 561b2133c98e..000000000000
--- a/src/platform/mt8186/include/arch/xtensa/config/secure.h
+++ /dev/null
@@ -1,48 +0,0 @@
-
-/* Secure Mode defines. */
-
-/* Customer ID=16990; Build=0x904d8; Copyright (c) 2020 Cadence Design Systems, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef XTENSA_SECURE_H
-#define XTENSA_SECURE_H
-
-
-/* SRAM */
-#define XCHAL_HAVE_SECURE_SRAM	0
-
-/* INSTRAM0 */
-#define XCHAL_HAVE_SECURE_INSTRAM0	0
-
-/* INSTRAM1 */
-#define XCHAL_HAVE_SECURE_INSTRAM1	0
-
-/* DATARAM0 */
-#define XCHAL_HAVE_SECURE_DATARAM0	0
-
-/* Array of all secure regions' start/size */
-#define XCHAL_SECURE_MEM_LIST \
-{ \
-}
-
-#endif /* XTENSA_SECURE_H */
-
diff --git a/src/platform/mt8186/include/arch/xtensa/config/specreg.h b/src/platform/mt8186/include/arch/xtensa/config/specreg.h
deleted file mode 100644
index 7e4ed373ecc1..000000000000
--- a/src/platform/mt8186/include/arch/xtensa/config/specreg.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * Xtensa Special Register symbolic names
- */
-
-/* $Id: //depot/rel/Homewood/ib.5/Xtensa/SWConfig/hal/specreg.h.tpp#1 $ */
-
-/* Customer ID=16990; Build=0x904d8; Copyright (c) 1998-2002 Tensilica Inc.
-
-   Permission is hereby granted, free of charge, to any person obtaining
-   a copy of this software and associated documentation files (the
-   "Software"), to deal in the Software without restriction, including
-   without limitation the rights to use, copy, modify, merge, publish,
-   distribute, sublicense, and/or sell copies of the Software, and to
-   permit persons to whom the Software is furnished to do so, subject to
-   the following conditions:
-
-   The above copyright notice and this permission notice shall be included
-   in all copies or substantial portions of the Software.
-
-   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
-
-#ifndef XTENSA_SPECREG_H
-#define XTENSA_SPECREG_H
-
-/*  Include these special register bitfield definitions, for historical reasons:  */
-#include <xtensa/corebits.h>
-
-
-/*  Special registers:  */
-#define LBEG		0
-#define LEND		1
-#define LCOUNT		2
-#define SAR		3
-#define BR		4
-#define PREFCTL		40
-#define WINDOWBASE	72
-#define WINDOWSTART	73
-#define MPUENB		90
-#define ERACCESS	95
-#define IBREAKENABLE	96
-#define MEMCTL		97
-#define CACHEADRDIS	98
-#define DDR		104
-#define IBREAKA_0	128
-#define IBREAKA_1	129
-#define DBREAKA_0	144
-#define DBREAKA_1	145
-#define DBREAKC_0	160
-#define DBREAKC_1	161
-#define EPC_1		177
-#define EPC_2		178
-#define EPC_3		179
-#define EPC_4		180
-#define EPC_5		181
-#define EPC_6		182
-#define DEPC		192
-#define EPS_2		194
-#define EPS_3		195
-#define EPS_4		196
-#define EPS_5		197
-#define EPS_6		198
-#define EXCSAVE_1	209
-#define EXCSAVE_2	210
-#define EXCSAVE_3	211
-#define EXCSAVE_4	212
-#define EXCSAVE_5	213
-#define EXCSAVE_6	214
-#define CPENABLE	224
-#define INTERRUPT	226
-#define INTENABLE	228
-#define PS		230
-#define VECBASE		231
-#define EXCCAUSE	232
-#define DEBUGCAUSE	233
-#define CCOUNT		234
-#define PRID		235
-#define ICOUNT		236
-#define ICOUNTLEVEL	237
-#define EXCVADDR	238
-#define CCOMPARE_0	240
-#define CCOMPARE_1	241
-#define CCOMPARE_2	242
-#define MISC_REG_0	244
-#define MISC_REG_1	245
-#define MISC_REG_2	246
-#define MISC_REG_3	247
-
-
-/*  Special cases (bases of special register series):  */
-#define IBREAKA		128
-#define DBREAKA		144
-#define DBREAKC		160
-#define EPC		176
-#define EPS		192
-#define EXCSAVE		208
-#define CCOMPARE	240
-
-/*  Special names for read-only and write-only interrupt registers:  */
-#define INTREAD		226
-#define INTSET		226
-#define INTCLEAR	227
-
-#endif /* XTENSA_SPECREG_H */
-
diff --git a/src/platform/mt8186/include/arch/xtensa/config/system.h b/src/platform/mt8186/include/arch/xtensa/config/system.h
deleted file mode 100644
index e92cc4ad0433..000000000000
--- a/src/platform/mt8186/include/arch/xtensa/config/system.h
+++ /dev/null
@@ -1,254 +0,0 @@
-/* 
- * xtensa/config/system.h -- HAL definitions that are dependent on SYSTEM configuration
- *
- *  NOTE: The location and contents of this file are highly subject to change.
- *
- *  Source for configuration-independent binaries (which link in a
- *  configuration-specific HAL library) must NEVER include this file.
- *  The HAL itself has historically included this file in some instances,
- *  but this is not appropriate either, because the HAL is meant to be
- *  core-specific but system independent.
- */
-
-/* Customer ID=16990; Build=0x904d8; Copyright (c) 2000-2010 Tensilica Inc.
-
-   Permission is hereby granted, free of charge, to any person obtaining
-   a copy of this software and associated documentation files (the
-   "Software"), to deal in the Software without restriction, including
-   without limitation the rights to use, copy, modify, merge, publish,
-   distribute, sublicense, and/or sell copies of the Software, and to
-   permit persons to whom the Software is furnished to do so, subject to
-   the following conditions:
-
-   The above copyright notice and this permission notice shall be included
-   in all copies or substantial portions of the Software.
-
-   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
-
-
-#ifndef XTENSA_CONFIG_SYSTEM_H
-#define XTENSA_CONFIG_SYSTEM_H
-
-
-/*----------------------------------------------------------------------
-				CONFIGURED SOFTWARE OPTIONS
-  ----------------------------------------------------------------------*/
-
-#define XSHAL_USE_ABSOLUTE_LITERALS	0	/* (sw-only option, whether software uses absolute literals) */
-#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals.  */
-
-#define XSHAL_ABI			XTHAL_ABI_WINDOWED	/* (sw-only option, selected ABI) */
-/*  The above maps to one of the following constants:  */
-#define XTHAL_ABI_WINDOWED		0
-#define XTHAL_ABI_CALL0			1
-
-#define XSHAL_CLIB			XTHAL_CLIB_XCLIB	/* (sw-only option, selected C library) */
-/*  The above maps to one of the following constants:  */
-#define XTHAL_CLIB_NEWLIB		0
-#define XTHAL_CLIB_UCLIBC		1
-#define XTHAL_CLIB_XCLIB		2
-
-#define XSHAL_USE_FLOATING_POINT	1
-
-#define XSHAL_FLOATING_POINT_ABI        1
-
-/*  SW workarounds enabled for HW errata:  */
-
-/*----------------------------------------------------------------------
-				DEVICE ADDRESSES
-  ----------------------------------------------------------------------*/
-
-/*
- *  Strange place to find these, but the configuration GUI
- *  allows moving these around to account for various core
- *  configurations.  Specific boards (and their BSP software)
- *  will have specific meanings for these components.
- */
-
-/*  I/O Block areas:  */
-#define XSHAL_IOBLOCK_CACHED_VADDR	0x70000000
-#define XSHAL_IOBLOCK_CACHED_PADDR	0x70000000
-#define XSHAL_IOBLOCK_CACHED_SIZE	0x0E000000
-
-#define XSHAL_IOBLOCK_BYPASS_VADDR	0x90000000
-#define XSHAL_IOBLOCK_BYPASS_PADDR	0x90000000
-#define XSHAL_IOBLOCK_BYPASS_SIZE	0x0E000000
-
-/*  System ROM:  */
-
-/*  System RAM:  */
-#define XSHAL_RAM_VADDR		0x40000000
-#define XSHAL_RAM_PADDR		0x40000000
-#define XSHAL_RAM_VSIZE		0x80000000
-#define XSHAL_RAM_PSIZE		0x80000000
-#define XSHAL_RAM_SIZE		XSHAL_RAM_PSIZE
-/*  Largest available area (free of vectors):  */
-#define XSHAL_RAM_AVAIL_VADDR	0x40000AE0
-#define XSHAL_RAM_AVAIL_VSIZE	0x7FFFF520
-
-/*
- *  Shadow system RAM (same device as system RAM, at different address).
- *  (Emulation boards need this for the SONIC Ethernet driver
- *   when data caches are configured for writeback mode.)
- *  NOTE: on full MMU configs, this points to the BYPASS virtual address
- *  of system RAM, ie. is the same as XSHAL_RAM_* except that virtual
- *  addresses are viewed through the BYPASS static map rather than
- *  the CACHED static map.
- */
-#define XSHAL_RAM_BYPASS_VADDR		0xC0000000
-#define XSHAL_RAM_BYPASS_PADDR		0xC0000000
-#define XSHAL_RAM_BYPASS_PSIZE		0x20000000
-
-/*  Alternate system RAM (different device than system RAM):  */
-
-/*  Some available location in which to place devices in a simulation (eg. XTMP):  */
-#define XSHAL_SIMIO_CACHED_VADDR	0xC0000000
-#define XSHAL_SIMIO_BYPASS_VADDR	0xC0000000
-#define XSHAL_SIMIO_PADDR		0xC0000000
-#define XSHAL_SIMIO_SIZE		0x20000000
-
-
-/*----------------------------------------------------------------------
- *  For use by reference testbench exit and diagnostic routines.
- */
-#define XSHAL_MAGIC_EXIT		0xdeed2000
-#define XSHAL_STL_INFO_LOCATION		0xfffffffc
-
-/*----------------------------------------------------------------------
- *			DEVICE-ADDRESS DEPENDENT...
- *
- *  Values written to CACHEATTR special register (or its equivalent)
- *  to enable and disable caches in various modes.
- *----------------------------------------------------------------------*/
-
-/*----------------------------------------------------------------------
-			BACKWARD COMPATIBILITY ...
-  ----------------------------------------------------------------------*/
-
-/*
- *  NOTE:  the following two macros are DEPRECATED.  Use the latter
- *  board-specific macros instead, which are specially tuned for the
- *  particular target environments' memory maps.
- */
-#define XSHAL_CACHEATTR_BYPASS		XSHAL_XT2000_CACHEATTR_BYPASS	/* disable caches in bypass mode */
-#define XSHAL_CACHEATTR_DEFAULT		XSHAL_XT2000_CACHEATTR_DEFAULT	/* default setting to enable caches (no writeback!) */
-
-/*----------------------------------------------------------------------
-				GENERIC
-  ----------------------------------------------------------------------*/
-
-/*  For the following, a 512MB region is used if it contains a system (PIF) RAM,
- *  system (PIF) ROM, local memory, or XLMI.  */
-
-/*  These set any unused 512MB region to cache-BYPASS attribute:  */
-#define XSHAL_ALLVALID_CACHEATTR_WRITEBACK	0x22444442	/* enable caches in write-back mode */
-#define XSHAL_ALLVALID_CACHEATTR_WRITEALLOC	0x22111112	/* enable caches in write-allocate mode */
-#define XSHAL_ALLVALID_CACHEATTR_WRITETHRU	0x22111112	/* enable caches in write-through mode */
-#define XSHAL_ALLVALID_CACHEATTR_BYPASS		0x22222222	/* disable caches in bypass mode */
-#define XSHAL_ALLVALID_CACHEATTR_DEFAULT	XSHAL_ALLVALID_CACHEATTR_WRITEBACK	/* default setting to enable caches */
-
-/*  These set any unused 512MB region to ILLEGAL attribute:  */
-#define XSHAL_STRICT_CACHEATTR_WRITEBACK	0xFF44444F	/* enable caches in write-back mode */
-#define XSHAL_STRICT_CACHEATTR_WRITEALLOC	0xFF11111F	/* enable caches in write-allocate mode */
-#define XSHAL_STRICT_CACHEATTR_WRITETHRU	0xFF11111F	/* enable caches in write-through mode */
-#define XSHAL_STRICT_CACHEATTR_BYPASS		0xFF22222F	/* disable caches in bypass mode */
-#define XSHAL_STRICT_CACHEATTR_DEFAULT		XSHAL_STRICT_CACHEATTR_WRITEBACK	/* default setting to enable caches */
-
-/*  These set the first 512MB, if unused, to ILLEGAL attribute to help catch
- *  NULL-pointer dereference bugs; all other unused 512MB regions are set
- *  to cache-BYPASS attribute:  */
-#define XSHAL_TRAPNULL_CACHEATTR_WRITEBACK	0x2244444F	/* enable caches in write-back mode */
-#define XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC	0x2211111F	/* enable caches in write-allocate mode */
-#define XSHAL_TRAPNULL_CACHEATTR_WRITETHRU	0x2211111F	/* enable caches in write-through mode */
-#define XSHAL_TRAPNULL_CACHEATTR_BYPASS		0x2222222F	/* disable caches in bypass mode */
-#define XSHAL_TRAPNULL_CACHEATTR_DEFAULT	XSHAL_TRAPNULL_CACHEATTR_WRITEBACK	/* default setting to enable caches */
-
-/*----------------------------------------------------------------------
-			ISS (Instruction Set Simulator) SPECIFIC ...
-  ----------------------------------------------------------------------*/
-
-/*  For now, ISS defaults to the TRAPNULL settings:  */
-#define XSHAL_ISS_CACHEATTR_WRITEBACK	XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
-#define XSHAL_ISS_CACHEATTR_WRITEALLOC	XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC
-#define XSHAL_ISS_CACHEATTR_WRITETHRU	XSHAL_TRAPNULL_CACHEATTR_WRITETHRU
-#define XSHAL_ISS_CACHEATTR_BYPASS	XSHAL_TRAPNULL_CACHEATTR_BYPASS
-#define XSHAL_ISS_CACHEATTR_DEFAULT	XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
-
-#define XSHAL_ISS_PIPE_REGIONS	0
-#define XSHAL_ISS_SDRAM_REGIONS	0
-
-
-/*----------------------------------------------------------------------
-			XT2000 BOARD SPECIFIC ...
-  ----------------------------------------------------------------------*/
-
-/*  For the following, a 512MB region is used if it contains any system RAM,
- *  system ROM, local memory, XLMI, or other XT2000 board device or memory.
- *  Regions containing devices are forced to cache-BYPASS mode regardless
- *  of whether the macro is _WRITEBACK vs. _BYPASS etc.  */
-
-/*  These set any 512MB region unused on the XT2000 to ILLEGAL attribute:  */
-#define XSHAL_XT2000_CACHEATTR_WRITEBACK	0xF242444F	/* enable caches in write-back mode */
-#define XSHAL_XT2000_CACHEATTR_WRITEALLOC	0xF212111F	/* enable caches in write-allocate mode */
-#define XSHAL_XT2000_CACHEATTR_WRITETHRU	0xF212111F	/* enable caches in write-through mode */
-#define XSHAL_XT2000_CACHEATTR_BYPASS		0xF222222F	/* disable caches in bypass mode */
-#define XSHAL_XT2000_CACHEATTR_DEFAULT		XSHAL_XT2000_CACHEATTR_WRITEBACK	/* default setting to enable caches */
-
-#define XSHAL_XT2000_PIPE_REGIONS	0x00000000	/* BusInt pipeline regions */
-#define XSHAL_XT2000_SDRAM_REGIONS	0x00001010	/* BusInt SDRAM regions */
-
-
-/*----------------------------------------------------------------------
-				VECTOR INFO AND SIZES
-  ----------------------------------------------------------------------*/
-
-#define XSHAL_VECTORS_PACKED		0	/* UNUSED */
-#define XSHAL_STATIC_VECTOR_SELECT	1
-#define XSHAL_RESET_VECTOR_VADDR	0x40000800
-#define XSHAL_RESET_VECTOR_PADDR	0x40000800
-
-/*
- *  Sizes allocated to vectors by the system (memory map) configuration.
- *  These sizes are constrained by core configuration (eg. one vector's
- *  code cannot overflow into another vector) but are dependent on the
- *  system or board (or LSP) memory map configuration.
- *
- *  Whether or not each vector happens to be in a system ROM is also
- *  a system configuration matter, sometimes useful, included here also:
- */
-#define XSHAL_RESET_VECTOR_SIZE	0x000002E0
-#define XSHAL_RESET_VECTOR_ISROM	0
-#define XSHAL_USER_VECTOR_SIZE	0x0000001C
-#define XSHAL_USER_VECTOR_ISROM	0
-#define XSHAL_PROGRAMEXC_VECTOR_SIZE	XSHAL_USER_VECTOR_SIZE	/* for backward compatibility */
-#define XSHAL_USEREXC_VECTOR_SIZE	XSHAL_USER_VECTOR_SIZE	/* for backward compatibility */
-#define XSHAL_KERNEL_VECTOR_SIZE	0x0000001C
-#define XSHAL_KERNEL_VECTOR_ISROM	0
-#define XSHAL_STACKEDEXC_VECTOR_SIZE	XSHAL_KERNEL_VECTOR_SIZE	/* for backward compatibility */
-#define XSHAL_KERNELEXC_VECTOR_SIZE	XSHAL_KERNEL_VECTOR_SIZE	/* for backward compatibility */
-#define XSHAL_DOUBLEEXC_VECTOR_SIZE	0x0000001C
-#define XSHAL_DOUBLEEXC_VECTOR_ISROM	0
-#define XSHAL_WINDOW_VECTORS_SIZE	0x00000178
-#define XSHAL_WINDOW_VECTORS_ISROM	0
-#define XSHAL_INTLEVEL2_VECTOR_SIZE	0x0000001C
-#define XSHAL_INTLEVEL2_VECTOR_ISROM	0
-#define XSHAL_INTLEVEL3_VECTOR_SIZE	0x0000001C
-#define XSHAL_INTLEVEL3_VECTOR_ISROM	0
-#define XSHAL_INTLEVEL4_VECTOR_SIZE	0x0000001C
-#define XSHAL_INTLEVEL4_VECTOR_ISROM	0
-#define XSHAL_INTLEVEL5_VECTOR_SIZE	0x0000001C
-#define XSHAL_INTLEVEL5_VECTOR_ISROM	0
-#define XSHAL_DEBUG_VECTOR_SIZE		XSHAL_INTLEVEL5_VECTOR_SIZE
-#define XSHAL_DEBUG_VECTOR_ISROM	XSHAL_INTLEVEL5_VECTOR_ISROM
-#define XSHAL_NMI_VECTOR_SIZE	0x0000001C
-#define XSHAL_NMI_VECTOR_ISROM	0
-#define XSHAL_INTLEVEL6_VECTOR_SIZE	XSHAL_NMI_VECTOR_SIZE
-
-#endif /*XTENSA_CONFIG_SYSTEM_H*/
-
diff --git a/src/platform/mt8186/include/arch/xtensa/config/tie-asm.h b/src/platform/mt8186/include/arch/xtensa/config/tie-asm.h
deleted file mode 100644
index 1dd05a4d23b9..000000000000
--- a/src/platform/mt8186/include/arch/xtensa/config/tie-asm.h
+++ /dev/null
@@ -1,362 +0,0 @@
-/* 
- * tie-asm.h -- compile-time HAL assembler definitions dependent on CORE & TIE
- *
- *  NOTE:  This header file is not meant to be included directly.
- */
-
-/* This header file contains assembly-language definitions (assembly
-   macros, etc.) for this specific Xtensa processor's TIE extensions
-   and options.  It is customized to this Xtensa processor configuration.
-
-   Customer ID=16990; Build=0x904d8; Copyright (c) 1999-2020 Cadence Design Systems Inc.
-
-   Permission is hereby granted, free of charge, to any person obtaining
-   a copy of this software and associated documentation files (the
-   "Software"), to deal in the Software without restriction, including
-   without limitation the rights to use, copy, modify, merge, publish,
-   distribute, sublicense, and/or sell copies of the Software, and to
-   permit persons to whom the Software is furnished to do so, subject to
-   the following conditions:
-
-   The above copyright notice and this permission notice shall be included
-   in all copies or substantial portions of the Software.
-
-   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
-
-#ifndef _XTENSA_CORE_TIE_ASM_H
-#define _XTENSA_CORE_TIE_ASM_H
-
-#include <xtensa/coreasm.h>
-
-/*  Selection parameter values for save-area save/restore macros:  */
-/*  Option vs. TIE:  */
-#define XTHAL_SAS_TIE	0x0001	/* custom extension or coprocessor */
-#define XTHAL_SAS_OPT	0x0002	/* optional (and not a coprocessor) */
-#define XTHAL_SAS_ANYOT	0x0003	/* both of the above */
-/*  Whether used automatically by compiler:  */
-#define XTHAL_SAS_NOCC	0x0004	/* not used by compiler w/o special opts/code */
-#define XTHAL_SAS_CC	0x0008	/* used by compiler without special opts/code */
-#define XTHAL_SAS_ANYCC	0x000C	/* both of the above */
-/*  ABI handling across function calls:  */
-#define XTHAL_SAS_CALR	0x0010	/* caller-saved */
-#define XTHAL_SAS_CALE	0x0020	/* callee-saved */
-#define XTHAL_SAS_GLOB	0x0040	/* global across function calls (in thread) */
-#define XTHAL_SAS_ANYABI	0x0070	/* all of the above three */
-/*  Misc  */
-#define XTHAL_SAS_ALL	0xFFFF	/* include all default NCP contents */
-#define XTHAL_SAS3(optie,ccuse,abi)	( ((optie) & XTHAL_SAS_ANYOT)  \
-					| ((ccuse) & XTHAL_SAS_ANYCC)  \
-					| ((abi)   & XTHAL_SAS_ANYABI) )
-
-
-    /*
-      *  Macro to store all non-coprocessor (extra) custom TIE and optional state
-      *  (not including zero-overhead loop registers).
-      *  Required parameters:
-      *      ptr         Save area pointer address register (clobbered)
-      *                  (register must contain a 4 byte aligned address).
-      *      at1..at4    Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
-      *                  registers are clobbered, the remaining are unused).
-      *  Optional parameters:
-      *      continue    If macro invoked as part of a larger store sequence, set to 1
-      *                  if this is not the first in the sequence.  Defaults to 0.
-      *      ofs         Offset from start of larger sequence (from value of first ptr
-      *                  in sequence) at which to store.  Defaults to next available space
-      *                  (or 0 if <continue> is 0).
-      *      select      Select what category(ies) of registers to store, as a bitmask
-      *                  (see XTHAL_SAS_xxx constants).  Defaults to all registers.
-      *      alloc       Select what category(ies) of registers to allocate; if any
-      *                  category is selected here that is not in <select>, space for
-      *                  the corresponding registers is skipped without doing any store.
-      */
-    .macro xchal_ncp_store  ptr at1 at2 at3 at4  continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
-	xchal_sa_start	\continue, \ofs
-	// Optional global registers used by default by the compiler:
-	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
-	xchal_sa_align	\ptr, 0, 1016, 4, 4
-	rur.threadptr	\at1		// threadptr option
-	s32i	\at1, \ptr, .Lxchal_ofs_+0
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
-	.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
-	xchal_sa_align	\ptr, 0, 1016, 4, 4
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
-	.endif
-	// Optional caller-saved registers not used by default by the compiler:
-	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
-	xchal_sa_align	\ptr, 0, 1016, 4, 4
-	rsr.br	\at1		// boolean option
-	s32i	\at1, \ptr, .Lxchal_ofs_+0
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
-	.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
-	xchal_sa_align	\ptr, 0, 1016, 4, 4
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
-	.endif
-    .endm	// xchal_ncp_store
-
-    /*
-      *  Macro to load all non-coprocessor (extra) custom TIE and optional state
-      *  (not including zero-overhead loop registers).
-      *  Required parameters:
-      *      ptr         Save area pointer address register (clobbered)
-      *                  (register must contain a 4 byte aligned address).
-      *      at1..at4    Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
-      *                  registers are clobbered, the remaining are unused).
-      *  Optional parameters:
-      *      continue    If macro invoked as part of a larger load sequence, set to 1
-      *                  if this is not the first in the sequence.  Defaults to 0.
-      *      ofs         Offset from start of larger sequence (from value of first ptr
-      *                  in sequence) at which to load.  Defaults to next available space
-      *                  (or 0 if <continue> is 0).
-      *      select      Select what category(ies) of registers to load, as a bitmask
-      *                  (see XTHAL_SAS_xxx constants).  Defaults to all registers.
-      *      alloc       Select what category(ies) of registers to allocate; if any
-      *                  category is selected here that is not in <select>, space for
-      *                  the corresponding registers is skipped without doing any load.
-      */
-    .macro xchal_ncp_load  ptr at1 at2 at3 at4  continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
-	xchal_sa_start	\continue, \ofs
-	// Optional global registers used by default by the compiler:
-	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
-	xchal_sa_align	\ptr, 0, 1016, 4, 4
-	l32i	\at1, \ptr, .Lxchal_ofs_+0
-	wur.threadptr	\at1		// threadptr option
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
-	.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
-	xchal_sa_align	\ptr, 0, 1016, 4, 4
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
-	.endif
-	// Optional caller-saved registers not used by default by the compiler:
-	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
-	xchal_sa_align	\ptr, 0, 1016, 4, 4
-	l32i	\at1, \ptr, .Lxchal_ofs_+0
-	wsr.br	\at1		// boolean option
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
-	.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
-	xchal_sa_align	\ptr, 0, 1016, 4, 4
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
-	.endif
-    .endm	// xchal_ncp_load
-
-
-#define XCHAL_NCP_NUM_ATMPS	1
-
-    /* 
-     *  Macro to store the state of TIE coprocessor AudioEngineLX.
-     *  Required parameters:
-     *      ptr         Save area pointer address register (clobbered)
-     *                  (register must contain a 16 byte aligned address).
-     *      at1..at4    Four temporary address registers (first XCHAL_CP1_NUM_ATMPS
-     *                  registers are clobbered, the remaining are unused).
-     *  Optional parameters are the same as for xchal_ncp_store.
-     */
-#define xchal_cp_AudioEngineLX_store	xchal_cp1_store
-    .macro	xchal_cp1_store  ptr at1 at2 at3 at4  continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
-	xchal_sa_start \continue, \ofs
-	// Custom caller-saved registers not used by default by the compiler:
-	.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
-	xchal_sa_align	\ptr, 0, 0, 16, 16
-	ae_s64.i	aed0, \ptr, .Lxchal_ofs_+56
-	addi.a	\ptr, \ptr, 64
-	ae_s64.i	aed1, \ptr, .Lxchal_ofs_+0
-	ae_s64.i	aed2, \ptr, .Lxchal_ofs_+8
-	ae_s64.i	aed3, \ptr, .Lxchal_ofs_+16
-	ae_s64.i	aed4, \ptr, .Lxchal_ofs_+24
-	ae_s64.i	aed5, \ptr, .Lxchal_ofs_+32
-	ae_s64.i	aed6, \ptr, .Lxchal_ofs_+40
-	ae_s64.i	aed7, \ptr, .Lxchal_ofs_+48
-	ae_s64.i	aed8, \ptr, .Lxchal_ofs_+56
-	addi.a	\ptr, \ptr, 64
-	ae_s64.i	aed9, \ptr, .Lxchal_ofs_+0
-	ae_s64.i	aed10, \ptr, .Lxchal_ofs_+8
-	ae_s64.i	aed11, \ptr, .Lxchal_ofs_+16
-	ae_s64.i	aed12, \ptr, .Lxchal_ofs_+24
-	ae_s64.i	aed13, \ptr, .Lxchal_ofs_+32
-	ae_s64.i	aed14, \ptr, .Lxchal_ofs_+40
-	ae_s64.i	aed15, \ptr, .Lxchal_ofs_+48
-	ae_s64.i	aed16, \ptr, .Lxchal_ofs_+56
-	addi.a	\ptr, \ptr, 64
-	ae_s64.i	aed17, \ptr, .Lxchal_ofs_+0
-	ae_s64.i	aed18, \ptr, .Lxchal_ofs_+8
-	ae_s64.i	aed19, \ptr, .Lxchal_ofs_+16
-	ae_s64.i	aed20, \ptr, .Lxchal_ofs_+24
-	ae_s64.i	aed21, \ptr, .Lxchal_ofs_+32
-	ae_s64.i	aed22, \ptr, .Lxchal_ofs_+40
-	ae_s64.i	aed23, \ptr, .Lxchal_ofs_+48
-	ae_s64.i	aed24, \ptr, .Lxchal_ofs_+56
-	addi.a	\ptr, \ptr, 64
-	ae_s64.i	aed25, \ptr, .Lxchal_ofs_+0
-	ae_s64.i	aed26, \ptr, .Lxchal_ofs_+8
-	ae_s64.i	aed27, \ptr, .Lxchal_ofs_+16
-	ae_s64.i	aed28, \ptr, .Lxchal_ofs_+24
-	ae_s64.i	aed29, \ptr, .Lxchal_ofs_+32
-	ae_s64.i	aed30, \ptr, .Lxchal_ofs_+40
-	ae_s64.i	aed31, \ptr, .Lxchal_ofs_+48
-	ae_movae	\at1, aep0
-	s8i	\at1, \ptr, .Lxchal_ofs_+56
-	ae_movae	\at1, aep1
-	s8i	\at1, \ptr, .Lxchal_ofs_+57
-	ae_movae	\at1, aep2
-	s8i	\at1, \ptr, .Lxchal_ofs_+58
-	ae_movae	\at1, aep3
-	s8i	\at1, \ptr, .Lxchal_ofs_+59
-	addi.a	\ptr, \ptr, 64
-	ae_salign128.i	u0, \ptr, .Lxchal_ofs_+0
-	ae_salign128.i	u1, \ptr, .Lxchal_ofs_+16
-	ae_salign128.i	u2, \ptr, .Lxchal_ofs_+32
-	ae_salign128.i	u3, \ptr, .Lxchal_ofs_+48
-	addi.a	\ptr, \ptr, -320
-	ae_movdrzbvc	aed0		// ureg AE_ZBIASV8C
-	ae_s64.i	aed0, \ptr, .Lxchal_ofs_+0 + 0
-	ae_movvfcrfsr	aed0		// ureg FCR_FSR
-	ae_s64.i	aed0, \ptr, .Lxchal_ofs_+8 + 0
-	rur.ae_ovf_sar	\at1		// ureg 240
-	s32i	\at1, \ptr, .Lxchal_ofs_+16
-	rur.ae_bithead	\at1		// ureg 241
-	s32i	\at1, \ptr, .Lxchal_ofs_+20
-	rur.ae_ts_fts_bu_bp	\at1		// ureg 242
-	s32i	\at1, \ptr, .Lxchal_ofs_+24
-	rur.ae_cw_sd_no	\at1		// ureg 243
-	s32i	\at1, \ptr, .Lxchal_ofs_+28
-	rur.ae_cbegin0	\at1		// ureg 246
-	s32i	\at1, \ptr, .Lxchal_ofs_+32
-	rur.ae_cend0	\at1		// ureg 247
-	s32i	\at1, \ptr, .Lxchal_ofs_+36
-	rur.ae_cbegin1	\at1		// ureg 248
-	s32i	\at1, \ptr, .Lxchal_ofs_+40
-	rur.ae_cend1	\at1		// ureg 249
-	s32i	\at1, \ptr, .Lxchal_ofs_+44
-	rur.ae_cbegin2	\at1		// ureg 250
-	s32i	\at1, \ptr, .Lxchal_ofs_+48
-	rur.ae_cend2	\at1		// ureg 251
-	s32i	\at1, \ptr, .Lxchal_ofs_+52
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 384
-	.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
-	xchal_sa_align	\ptr, 0, 0, 16, 16
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 384
-	.endif
-    .endm	// xchal_cp1_store
-
-    /* 
-     *  Macro to load the state of TIE coprocessor AudioEngineLX.
-     *  Required parameters:
-     *      ptr         Save area pointer address register (clobbered)
-     *                  (register must contain a 16 byte aligned address).
-     *      at1..at4    Four temporary address registers (first XCHAL_CP1_NUM_ATMPS
-     *                  registers are clobbered, the remaining are unused).
-     *  Optional parameters are the same as for xchal_ncp_load.
-     */
-#define xchal_cp_AudioEngineLX_load	xchal_cp1_load
-    .macro	xchal_cp1_load  ptr at1 at2 at3 at4  continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
-	xchal_sa_start \continue, \ofs
-	// Custom caller-saved registers not used by default by the compiler:
-	.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
-	xchal_sa_align	\ptr, 0, 0, 16, 16
-	ae_l64.i	aed0, \ptr, .Lxchal_ofs_+0 + 0		// ureg AE_ZBIASV8C
-	ae_movzbvcdr	aed0
-	ae_l64.i	aed0, \ptr, .Lxchal_ofs_+8 + 0		// ureg FCR_FSR
-	ae_movfcrfsrv	aed0
-	l32i	\at1, \ptr, .Lxchal_ofs_+16
-	wur.ae_ovf_sar	\at1		// ureg 240
-	l32i	\at1, \ptr, .Lxchal_ofs_+20
-	wur.ae_bithead	\at1		// ureg 241
-	l32i	\at1, \ptr, .Lxchal_ofs_+24
-	wur.ae_ts_fts_bu_bp	\at1		// ureg 242
-	l32i	\at1, \ptr, .Lxchal_ofs_+28
-	wur.ae_cw_sd_no	\at1		// ureg 243
-	l32i	\at1, \ptr, .Lxchal_ofs_+32
-	wur.ae_cbegin0	\at1		// ureg 246
-	l32i	\at1, \ptr, .Lxchal_ofs_+36
-	wur.ae_cend0	\at1		// ureg 247
-	l32i	\at1, \ptr, .Lxchal_ofs_+40
-	wur.ae_cbegin1	\at1		// ureg 248
-	l32i	\at1, \ptr, .Lxchal_ofs_+44
-	wur.ae_cend1	\at1		// ureg 249
-	l32i	\at1, \ptr, .Lxchal_ofs_+48
-	wur.ae_cbegin2	\at1		// ureg 250
-	l32i	\at1, \ptr, .Lxchal_ofs_+52
-	wur.ae_cend2	\at1		// ureg 251
-	ae_l64.i	aed0, \ptr, .Lxchal_ofs_+56
-	addi.a	\ptr, \ptr, 64
-	ae_l64.i	aed1, \ptr, .Lxchal_ofs_+0
-	ae_l64.i	aed2, \ptr, .Lxchal_ofs_+8
-	ae_l64.i	aed3, \ptr, .Lxchal_ofs_+16
-	ae_l64.i	aed4, \ptr, .Lxchal_ofs_+24
-	ae_l64.i	aed5, \ptr, .Lxchal_ofs_+32
-	ae_l64.i	aed6, \ptr, .Lxchal_ofs_+40
-	ae_l64.i	aed7, \ptr, .Lxchal_ofs_+48
-	ae_l64.i	aed8, \ptr, .Lxchal_ofs_+56
-	addi.a	\ptr, \ptr, 64
-	ae_l64.i	aed9, \ptr, .Lxchal_ofs_+0
-	ae_l64.i	aed10, \ptr, .Lxchal_ofs_+8
-	ae_l64.i	aed11, \ptr, .Lxchal_ofs_+16
-	ae_l64.i	aed12, \ptr, .Lxchal_ofs_+24
-	ae_l64.i	aed13, \ptr, .Lxchal_ofs_+32
-	ae_l64.i	aed14, \ptr, .Lxchal_ofs_+40
-	ae_l64.i	aed15, \ptr, .Lxchal_ofs_+48
-	ae_l64.i	aed16, \ptr, .Lxchal_ofs_+56
-	addi.a	\ptr, \ptr, 64
-	ae_l64.i	aed17, \ptr, .Lxchal_ofs_+0
-	ae_l64.i	aed18, \ptr, .Lxchal_ofs_+8
-	ae_l64.i	aed19, \ptr, .Lxchal_ofs_+16
-	ae_l64.i	aed20, \ptr, .Lxchal_ofs_+24
-	ae_l64.i	aed21, \ptr, .Lxchal_ofs_+32
-	ae_l64.i	aed22, \ptr, .Lxchal_ofs_+40
-	ae_l64.i	aed23, \ptr, .Lxchal_ofs_+48
-	ae_l64.i	aed24, \ptr, .Lxchal_ofs_+56
-	addi.a	\ptr, \ptr, 64
-	ae_l64.i	aed25, \ptr, .Lxchal_ofs_+0
-	ae_l64.i	aed26, \ptr, .Lxchal_ofs_+8
-	ae_l64.i	aed27, \ptr, .Lxchal_ofs_+16
-	ae_l64.i	aed28, \ptr, .Lxchal_ofs_+24
-	ae_l64.i	aed29, \ptr, .Lxchal_ofs_+32
-	ae_l64.i	aed30, \ptr, .Lxchal_ofs_+40
-	ae_l64.i	aed31, \ptr, .Lxchal_ofs_+48
-	addi.a	\ptr, \ptr, 56
-	l8ui	\at1, \ptr, .Lxchal_ofs_+0
-	ae_movea	aep0, \at1
-	l8ui	\at1, \ptr, .Lxchal_ofs_+1
-	ae_movea	aep1, \at1
-	l8ui	\at1, \ptr, .Lxchal_ofs_+2
-	ae_movea	aep2, \at1
-	l8ui	\at1, \ptr, .Lxchal_ofs_+3
-	ae_movea	aep3, \at1
-	addi.a	\ptr, \ptr, 8
-	ae_lalign128.i	u0, \ptr, .Lxchal_ofs_+0
-	ae_lalign128.i	u1, \ptr, .Lxchal_ofs_+16
-	ae_lalign128.i	u2, \ptr, .Lxchal_ofs_+32
-	ae_lalign128.i	u3, \ptr, .Lxchal_ofs_+48
-	.set	.Lxchal_pofs_, .Lxchal_pofs_ + 320
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 64
-	.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
-	xchal_sa_align	\ptr, 0, 0, 16, 16
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 384
-	.endif
-    .endm	// xchal_cp1_load
-
-#define XCHAL_CP1_NUM_ATMPS	1
-#define XCHAL_SA_NUM_ATMPS	1
-
-	/*  Empty macros for unconfigured coprocessors:  */
-	.macro xchal_cp0_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp0_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp2_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp2_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp3_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp3_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp4_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp4_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp5_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp5_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp6_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp6_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp7_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp7_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-
-#endif /*_XTENSA_CORE_TIE_ASM_H*/
-
diff --git a/src/platform/mt8186/include/arch/xtensa/config/tie.h b/src/platform/mt8186/include/arch/xtensa/config/tie.h
deleted file mode 100644
index 8ff7910d17ab..000000000000
--- a/src/platform/mt8186/include/arch/xtensa/config/tie.h
+++ /dev/null
@@ -1,210 +0,0 @@
-/* 
- * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
- *
- *  NOTE:  This header file is not meant to be included directly.
- */
-
-/* This header file describes this specific Xtensa processor's TIE extensions
-   that extend basic Xtensa core functionality.  It is customized to this
-   Xtensa processor configuration.
-
-   Customer ID=16990; Build=0x904d8; Copyright (c) 1999-2020 Cadence Design Systems Inc.
-
-   Permission is hereby granted, free of charge, to any person obtaining
-   a copy of this software and associated documentation files (the
-   "Software"), to deal in the Software without restriction, including
-   without limitation the rights to use, copy, modify, merge, publish,
-   distribute, sublicense, and/or sell copies of the Software, and to
-   permit persons to whom the Software is furnished to do so, subject to
-   the following conditions:
-
-   The above copyright notice and this permission notice shall be included
-   in all copies or substantial portions of the Software.
-
-   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
-
-#ifndef XTENSA_CORE_TIE_H
-#define XTENSA_CORE_TIE_H
-
-/* parasoft-begin-suppress ALL "This file not MISRA checked." */
-
-#define XCHAL_CP_NUM			1	/* number of coprocessors */
-#define XCHAL_CP_MAX			2	/* max CP ID + 1 (0 if none) */
-#define XCHAL_CP_MASK			0x02	/* bitmask of all CPs by ID */
-#define XCHAL_CP_PORT_MASK		0x00	/* bitmask of only port CPs */
-
-/*  Basic parameters of each coprocessor:  */
-#define XCHAL_CP1_NAME			"AudioEngineLX"
-#define XCHAL_CP1_IDENT			AudioEngineLX
-#define XCHAL_CP1_SA_SIZE		384	/* size of state save area */
-#define XCHAL_CP1_SA_ALIGN		16	/* min alignment of save area */
-#define XCHAL_CP_ID_AUDIOENGINELX   	1	/* coprocessor ID (0..7) */
-
-/*  Filler info for unassigned coprocessors, to simplify arrays etc:  */
-#define XCHAL_CP0_SA_SIZE		0
-#define XCHAL_CP0_SA_ALIGN		1
-#define XCHAL_CP2_SA_SIZE		0
-#define XCHAL_CP2_SA_ALIGN		1
-#define XCHAL_CP3_SA_SIZE		0
-#define XCHAL_CP3_SA_ALIGN		1
-#define XCHAL_CP4_SA_SIZE		0
-#define XCHAL_CP4_SA_ALIGN		1
-#define XCHAL_CP5_SA_SIZE		0
-#define XCHAL_CP5_SA_ALIGN		1
-#define XCHAL_CP6_SA_SIZE		0
-#define XCHAL_CP6_SA_ALIGN		1
-#define XCHAL_CP7_SA_SIZE		0
-#define XCHAL_CP7_SA_ALIGN		1
-
-/*  Save area for non-coprocessor optional and custom (TIE) state:  */
-#define XCHAL_NCP_SA_SIZE		8
-#define XCHAL_NCP_SA_ALIGN		4
-
-/*  Total save area for optional and custom state (NCP + CPn):  */
-#define XCHAL_TOTAL_SA_SIZE		400	/* with 16-byte align padding */
-#define XCHAL_TOTAL_SA_ALIGN		16	/* actual minimum alignment */
-
-/*
- * Detailed contents of save areas.
- * NOTE:  caller must define the XCHAL_SA_REG macro (not defined here)
- * before expanding the XCHAL_xxx_SA_LIST() macros.
- *
- * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
- *		dbnum,base,regnum,bitsz,gapsz,reset,x...)
- *
- *	s = passed from XCHAL_*_LIST(s), eg. to select how to expand
- *	ccused = set if used by compiler without special options or code
- *	abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
- *	kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
- *	opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg)
- *	name = lowercase reg name (no quotes)
- *	galign = group byte alignment (power of 2) (galign >= align)
- *	align = register byte alignment (power of 2)
- *	asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz)
- *	  (not including any pad bytes required to galign this or next reg)
- *	dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>)
- *	base = reg shortname w/o index (or sr=special, ur=TIE user reg)
- *	regnum = reg index in regfile, or special/TIE-user reg number
- *	bitsz = number of significant bits (regfile width, or ur/sr mask bits)
- *	gapsz = intervening bits, if bitsz bits not stored contiguously
- *	(padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize)
- *	reset = register reset value (or 0 if undefined at reset)
- *	x = reserved for future use (0 until then)
- *
- *  To filter out certain registers, e.g. to expand only the non-global
- *  registers used by the compiler, you can do something like this:
- *
- *  #define XCHAL_SA_REG(s,ccused,p...)	SELCC##ccused(p)
- *  #define SELCC0(p...)
- *  #define SELCC1(abikind,p...)	SELAK##abikind(p)
- *  #define SELAK0(p...)		REG(p)
- *  #define SELAK1(p...)		REG(p)
- *  #define SELAK2(p...)
- *  #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \
- *		...what you want to expand...
- */
-
-#define XCHAL_NCP_SA_NUM	2
-#define XCHAL_NCP_SA_LIST(s)	\
- XCHAL_SA_REG(s,1,2,1,1,      threadptr, 4, 4, 4,0x03E7,  ur,231, 32,0,0,0) \
- XCHAL_SA_REG(s,0,0,0,1,             br, 4, 4, 4,0x0204,  sr,4  , 16,0,0,0)
-
-#define XCHAL_CP0_SA_NUM	0
-#define XCHAL_CP0_SA_LIST(s)	/* empty */
-
-#define XCHAL_CP1_SA_NUM	52
-#define XCHAL_CP1_SA_LIST(s)	\
- XCHAL_SA_REG(s,0,0,1,0,    ae_zbiasv8c,16, 8, 8,0x1029,  ur,-1 , 16,0,0,0) \
- XCHAL_SA_REG(s,0,0,1,0,        fcr_fsr, 8, 8, 8,0x102A,  ur,-1 ,  7,0,0,0) \
- XCHAL_SA_REG(s,0,0,1,0,     ae_ovf_sar, 4, 4, 4,0x03F0,  ur,240, 15,0,0,0) \
- XCHAL_SA_REG(s,0,0,1,0,     ae_bithead, 4, 4, 4,0x03F1,  ur,241, 32,0,0,0) \
- XCHAL_SA_REG(s,0,0,1,0,ae_ts_fts_bu_bp, 4, 4, 4,0x03F2,  ur,242, 16,0,0,0) \
- XCHAL_SA_REG(s,0,0,1,0,    ae_cw_sd_no, 4, 4, 4,0x03F3,  ur,243, 29,0,0,0) \
- XCHAL_SA_REG(s,0,0,1,0,     ae_cbegin0, 4, 4, 4,0x03F6,  ur,246, 32,0,0,0) \
- XCHAL_SA_REG(s,0,0,1,0,       ae_cend0, 4, 4, 4,0x03F7,  ur,247, 32,0,0,0) \
- XCHAL_SA_REG(s,0,0,1,0,     ae_cbegin1, 4, 4, 4,0x03F8,  ur,248, 32,0,0,0) \
- XCHAL_SA_REG(s,0,0,1,0,       ae_cend1, 4, 4, 4,0x03F9,  ur,249, 32,0,0,0) \
- XCHAL_SA_REG(s,0,0,1,0,     ae_cbegin2, 4, 4, 4,0x03FA,  ur,250, 32,0,0,0) \
- XCHAL_SA_REG(s,0,0,1,0,       ae_cend2, 4, 4, 4,0x03FB,  ur,251, 32,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aed0, 8, 8, 8,0x1000, aed,0  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aed1, 8, 8, 8,0x1001, aed,1  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aed2, 8, 8, 8,0x1002, aed,2  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aed3, 8, 8, 8,0x1003, aed,3  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aed4, 8, 8, 8,0x1004, aed,4  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aed5, 8, 8, 8,0x1005, aed,5  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aed6, 8, 8, 8,0x1006, aed,6  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aed7, 8, 8, 8,0x1007, aed,7  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aed8, 8, 8, 8,0x1008, aed,8  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aed9, 8, 8, 8,0x1009, aed,9  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed10, 8, 8, 8,0x100A, aed,10 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed11, 8, 8, 8,0x100B, aed,11 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed12, 8, 8, 8,0x100C, aed,12 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed13, 8, 8, 8,0x100D, aed,13 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed14, 8, 8, 8,0x100E, aed,14 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed15, 8, 8, 8,0x100F, aed,15 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed16, 8, 8, 8,0x1010, aed,16 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed17, 8, 8, 8,0x1011, aed,17 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed18, 8, 8, 8,0x1012, aed,18 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed19, 8, 8, 8,0x1013, aed,19 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed20, 8, 8, 8,0x1014, aed,20 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed21, 8, 8, 8,0x1015, aed,21 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed22, 8, 8, 8,0x1016, aed,22 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed23, 8, 8, 8,0x1017, aed,23 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed24, 8, 8, 8,0x1018, aed,24 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed25, 8, 8, 8,0x1019, aed,25 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed26, 8, 8, 8,0x101A, aed,26 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed27, 8, 8, 8,0x101B, aed,27 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed28, 8, 8, 8,0x101C, aed,28 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed29, 8, 8, 8,0x101D, aed,29 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed30, 8, 8, 8,0x101E, aed,30 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed31, 8, 8, 8,0x101F, aed,31 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aep0, 1, 1, 1,0x1024, aep,0  ,  8,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aep1, 1, 1, 1,0x1025, aep,1  ,  8,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aep2, 1, 1, 1,0x1026, aep,2  ,  8,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aep3, 1, 1, 1,0x1027, aep,3  ,  8,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,             u0,16,16,16,0x1020,   u,0  ,128,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,             u1,16,16,16,0x1021,   u,1  ,128,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,             u2,16,16,16,0x1022,   u,2  ,128,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,             u3,16,16,16,0x1023,   u,3  ,128,0,0,0)
-
-#define XCHAL_CP2_SA_NUM	0
-#define XCHAL_CP2_SA_LIST(s)	/* empty */
-
-#define XCHAL_CP3_SA_NUM	0
-#define XCHAL_CP3_SA_LIST(s)	/* empty */
-
-#define XCHAL_CP4_SA_NUM	0
-#define XCHAL_CP4_SA_LIST(s)	/* empty */
-
-#define XCHAL_CP5_SA_NUM	0
-#define XCHAL_CP5_SA_LIST(s)	/* empty */
-
-#define XCHAL_CP6_SA_NUM	0
-#define XCHAL_CP6_SA_LIST(s)	/* empty */
-
-#define XCHAL_CP7_SA_NUM	0
-#define XCHAL_CP7_SA_LIST(s)	/* empty */
-
-/* Byte length of instruction from its first nibble (op0 field), per FLIX.  */
-#define XCHAL_OP0_FORMAT_LENGTHS	3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,16
-/* Byte length of instruction from its first byte, per FLIX.  */
-#define XCHAL_BYTE0_FORMAT_LENGTHS	\
-	3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,16, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,16,\
-	3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,16, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,16,\
-	3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,16, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,16,\
-	3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,16, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,16,\
-	3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,16, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,16,\
-	3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,16, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,16,\
-	3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,16, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,16,\
-	3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,16, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,16
-
-/* parasoft-end-suppress ALL "This file not MISRA checked." */
-
-#endif /* XTENSA_CORE_TIE_H */
-
diff --git a/src/platform/mt8186/include/platform/drivers/idc.h b/src/platform/mt8186/include/platform/drivers/idc.h
deleted file mode 100644
index e77600345b55..000000000000
--- a/src/platform/mt8186/include/platform/drivers/idc.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2022 MediaTek. All rights reserved.
- *
- * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
- *         Tinghan Shen <tinghan.shen@mediatek.com>
- */
-
-#if defined(__XTOS_RTOS_IDC_H__) || defined(__ZEPHYR_RTOS_IDC_H__)
-
-#ifndef __PLATFORM_DRIVERS_IDC_H__
-#define __PLATFORM_DRIVERS_IDC_H__
-
-#include <stdint.h>
-
-struct idc_msg;
-
-static inline int idc_send_msg(struct idc_msg *msg, uint32_t mode)
-{
-	return 0;
-}
-
-static inline int idc_init(void)
-{
-	return 0;
-}
-
-#endif /* __PLATFORM_DRIVERS_IDC_H__ */
-
-#else
-
-#error "This file shouldn't be included from outside of Zephyr/XTOS's rtos/idc.h"
-
-#endif
diff --git a/src/platform/mt8186/include/platform/drivers/interrupt.h b/src/platform/mt8186/include/platform/drivers/interrupt.h
deleted file mode 100644
index 7be0f42c1f16..000000000000
--- a/src/platform/mt8186/include/platform/drivers/interrupt.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2022 MediaTek. All rights reserved.
- *
- * Author: Zhengnan Chen <zhengnan.chen@mediatek.com>
- *         Allen-KH Cheng <allen-kh.cheng@mediatek.com>
- *         Tinghan Shen <tinghan.shen@mediatek.com>
- */
-
-#ifdef __SOF_DRIVERS_INTERRUPT_H__
-
-#ifndef __PLATFORM_DRIVERS_INTERRUPT_H__
-#define __PLATFORM_DRIVERS_INTERRUPT_H__
-
-#include <stdint.h>
-#include <platform/drivers/mt_reg_base.h>
-
-#define PLATFORM_IRQ_HW_NUM		XCHAL_NUM_INTERRUPTS
-#define PLATFORM_IRQ_FIRST_CHILD	PLATFORM_IRQ_HW_NUM
-#define PLATFORM_IRQ_CHILDREN		32
-
-/* MTK_ADSP_IRQ_MASK */
-#define MTK_DSP_OUT_IRQ_MASK		0x3FF
-
-/* interrupt table */
-#define MTK_DSP_IRQ_UART		0
-#define MTK_DSP_IRQ_SPM			1
-#define MTK_DSP_IRQ_MAILBOX		2
-#define MTK_DSP_IRQ_DSP_TIMER0		3
-#define MTK_DSP_IRQ_DSP_TIMER1		4
-#define MTK_DSP_IRQ_CORE0		5
-#define MTK_DSP_IRQ_RSV0		6
-#define MTK_DSP_IRQ_RSV1		7
-#define MTK_DSP_IRQ_CONNSYS1		8
-#define MTK_DSP_IRQ_CONNSYS2		9
-#define MTK_DSP_IRQ_CONNSYS3		10
-#define MTK_DSP_IRQ_NNA0		11
-#define MTK_DSP_IRQ_NNA1		12
-#define MTK_DSP_IRQ_OSTIMER64		13
-#define MTK_DSP_IRQ_DMA			14
-#define MTK_DSP_IRQ_WDT			16
-#define MTK_DSP_IRQ_MDLA		17
-#define MTK_DSP_IRQ_OSTIMER32		18
-#define MTK_DSP_IRQ_NNA2		19
-#define MTK_DSP_IRQ_SCP			20
-#define MTK_DSP_IRQ_LATENCT_MON		21
-#define MTK_DSP_IRQ_BUS_TRACKER		22
-#define MTK_DSP_IRQ_WAKEUP_SRC		23
-#define MTK_DSP_IRQ_INFRA_HANG		24
-#define MTK_DSP_IRQ_NMI			25
-#define MTK_DSP_IRQ_TIMER0		26
-#define MTK_DSP_IRQ_TIMER1		27
-#define MTK_DSP_IRQ_TIMER2		28
-#define MTK_DSP_IRQ_PMU			29
-#define MTK_DSP_IRQ_WERR		30
-#define MTK_DSP_IRQ_SW			31
-
-#define MTK_MAX_IRQ_NUM			32
-
-/* grouped mailbox IRQ */
-#define MTK_DSP_IRQ_MBOX0		32
-#define MTK_DSP_IRQ_MBOX1		33
-#define MTK_DSP_IRQ_MBOX2		34
-#define MTK_DSP_IRQ_MBOX3		35
-#define MTK_DSP_IRQ_MBOX4		36
-
-#define	MTK_DSP_MBOX_MASK		0xF
-
-int mtk_irq_group_id(uint32_t irq);
-
-#endif /* __PLATFORM_DRIVERS_INTERRUPT_H__ */
-
-#else
-
-#error "This file shouldn't be included from outside of sof/drivers/interrupt.h"
-
-#endif /* __SOF_DRIVERS_INTERRUPT_H__ */
diff --git a/src/platform/mt8186/include/platform/drivers/mt_reg_base.h b/src/platform/mt8186/include/platform/drivers/mt_reg_base.h
deleted file mode 100644
index 1de4e6ad2ca1..000000000000
--- a/src/platform/mt8186/include/platform/drivers/mt_reg_base.h
+++ /dev/null
@@ -1,117 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2022 MediaTek. All rights reserved.
- *
- * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
- *         Tinghan Shen <tinghan.shen@mediatek.com>
- */
-
-#ifndef MT_REG_BASE_H
-#define MT_REG_BASE_H
-
-#define MTK_REG_TOPCKGEN_BASE		0x10000000
-#define MTK_REG_TOPCKGEN_SIZE		0x1000
-#define MTK_REG_APMIXDSYS_BASE		0x1000C000
-#define MTK_REG_APMIXDSYS_SIZE		0x1000
-
-#define MTK_DSP_REG_BASE		0x10680000 /* DSP Register base */
-#define MTK_DSP_CFGREG_BASE		0x10680000
-#define MTK_DSP_CFGREG_SIZE		0x1000
-#define MTK_DSP_CKCTRL_BASE		0x10681000
-#define MTK_DSP_CKCTRL_SIZE		0x1000
-#define MTK_DSP_OS_TIMER_BASE		0x10683000
-#define MTK_DSP_OS_TIMER_SIZE		0x1000
-#define MTK_DSP_UART0_BASE		0x10684000
-#define MTK_DSP_UART0_SIZE		0x1000
-#define MTK_DSP_TIMER_BASE		0x1068E000
-#define MTK_DSP_TIMER_SIZE		0x1000
-#define MTK_DSP_BUS_BASE		0x1068F000
-#define MTK_DSP_BUS_SIZE		0x1000
-#define MTK_DSP_AFE_BASE		0x11210000
-#define MTK_DSP_AFE_SIZE		0xF000 /* register 8k, compacted sram 52k */
-
-#define MTK_ADSP_CFGREG_SW_RSTN		(MTK_DSP_REG_BASE + 0x0000)
-#define MTK_ADSP_HIFI_IO_CONFIG		(MTK_DSP_REG_BASE + 0x000c)
-#define MTK_ADSP_IRQ_STATUS		(MTK_DSP_REG_BASE + 0x0010)
-#define MTK_ADSP_SW_INT_SET		(MTK_DSP_REG_BASE + 0x0018)
-#define MTK_ADSP_SW_INT_CLR		(MTK_DSP_REG_BASE + 0x001c)
-#define MTK_ADSP_SW_INT_32A		(MTK_DSP_REG_BASE + 0x0020)
-#define MTK_ADSP_IRQ_MASK		(MTK_DSP_REG_BASE + 0x0030)
-#define MTK_ADSP_GENERAL_IRQ_SET	(MTK_DSP_REG_BASE + 0x0034)
-#define MTK_ADSP_GENERAL_IRQ_CLR	(MTK_DSP_REG_BASE + 0x0038)
-#define MTK_ADSP_DVFSRC_STATE		(MTK_DSP_REG_BASE + 0x003c)
-#define MTK_ADSP_DVFSRC_REQ		(MTK_DSP_REG_BASE + 0x0040)
-#define MTK_ADSP_DDREN_REQ_0		(MTK_DSP_REG_BASE + 0x0044)
-#define MTK_ADSP_SPM_ACK		(MTK_DSP_REG_BASE + 0x004c)
-#define MTK_ADSP_IRQ_EN			(MTK_DSP_REG_BASE + 0x0050)
-#define MTK_ADSP_IRQ_POL_FIX		(MTK_DSP_REG_BASE + 0x0054)
-#define MTK_ADSP_SPM_WAKEUPSRC_CORE0	(MTK_DSP_REG_BASE + 0x005c)
-#define MTK_ADSP_SEMAPHORE		(MTK_DSP_REG_BASE + 0x0064)
-#define MTK_ADSP_DBG_SEL		(MTK_DSP_REG_BASE + 0x0074)
-#define MTK_ADSP_DBG_INFO		(MTK_DSP_REG_BASE + 0x0078)
-#define MTK_ADSP_WDT_CON_C0		(MTK_DSP_REG_BASE + 0x007c)
-#define MTK_ADSP_WDT_INIT_VALUE_C0	(MTK_DSP_REG_BASE + 0x0080)
-#define MTK_ADSP_WDT_CNT_C0		(MTK_DSP_REG_BASE + 0x0084)
-#define MTK_ADSP_WAKEUPSRC_MASK_C0	(MTK_DSP_REG_BASE + 0x00a0)
-#define MTK_ADSP_WAKEUPSRC_IRQ_C0	(MTK_DSP_REG_BASE + 0x00a4)
-#define MTK_ADSP2SPM_MBOX		(MTK_DSP_REG_BASE + 0x00bc)
-#define MTK_SPM2ADSP_MBOX		(MTK_DSP_REG_BASE + 0x00c0)
-#define MTK_GPR_RW_REG0			(MTK_DSP_REG_BASE + 0x0440)
-#define MTK_GPR_RW_REG1			(MTK_DSP_REG_BASE + 0x0444)
-#define MTK_GPR_RW_REG2			(MTK_DSP_REG_BASE + 0x0448)
-#define MTK_GPR_RW_REG3			(MTK_DSP_REG_BASE + 0x044c)
-#define MTK_GPR_RW_REG4			(MTK_DSP_REG_BASE + 0x0450)
-#define MTK_GPR_RW_REG5			(MTK_DSP_REG_BASE + 0x0454)
-#define MTK_GPR_RW_REG6			(MTK_DSP_REG_BASE + 0x0458)
-#define MTK_GPR_RW_REG7			(MTK_DSP_REG_BASE + 0x045c)
-#define MTK_GPR_RW_REG8			(MTK_DSP_REG_BASE + 0x0460)
-#define MTK_GPR_RW_REG9			(MTK_DSP_REG_BASE + 0x0464)
-#define MTK_GPR_RW_REG10		(MTK_DSP_REG_BASE + 0x0468)
-#define MTK_GPR_RW_REG11		(MTK_DSP_REG_BASE + 0x046c)
-#define MTK_GPR_RW_REG12		(MTK_DSP_REG_BASE + 0x0470)
-#define MTK_GPR_RW_REG13		(MTK_DSP_REG_BASE + 0x0474)
-#define MTK_GPR_RW_REG14		(MTK_DSP_REG_BASE + 0x0478)
-#define MTK_GPR_RW_REG15		(MTK_DSP_REG_BASE + 0x047c)
-#define MTK_GPR_RW_REG16		(MTK_DSP_REG_BASE + 0x0480)
-#define MTK_GPR_RW_REG17		(MTK_DSP_REG_BASE + 0x0484)
-#define MTK_GPR_RW_REG18		(MTK_DSP_REG_BASE + 0x0488)
-#define MTK_GPR_RW_REG19		(MTK_DSP_REG_BASE + 0x048c)
-#define MTK_GPR_RW_REG20		(MTK_DSP_REG_BASE + 0x0490)
-#define MTK_GPR_RW_REG21		(MTK_DSP_REG_BASE + 0x0494)
-#define MTK_GPR_RW_REG22		(MTK_DSP_REG_BASE + 0x0498)
-#define MTK_GPR_RW_REG23		(MTK_DSP_REG_BASE + 0x049c)
-#define MTK_GPR_RW_REG24		(MTK_DSP_REG_BASE + 0x04a0)
-#define MTK_GPR_RW_REG25		(MTK_DSP_REG_BASE + 0x04a4)
-#define MTK_GPR_RW_REG26		(MTK_DSP_REG_BASE + 0x04a8)
-#define MTK_GPR_RW_REG27		(MTK_DSP_REG_BASE + 0x04ac)
-#define MTK_GPR_RW_REG28		(MTK_DSP_REG_BASE + 0x04b0)  /* use for tickless status */
-#define MTK_GPR_RW_REG29		(MTK_DSP_REG_BASE + 0x04b4)
-#define MTK_ADSP_CLK_BUS_UPDATE		(MTK_DSP_REG_BASE + 0x04c0)
-#define MTK_ADSP_IRQ_OUT_MASK		(MTK_DSP_REG_BASE + 0x0500)
-#define MTK_MBOX_IRQ_IN			(MTK_DSP_REG_BASE + 0xB070)
-
-#define MTK_ADSP_BUS_SRC		(MTK_DSP_BUS_BASE + 0x140)
-
-#define MTK_ADSPPLL_CON0		(MTK_REG_APMIXDSYS_BASE + 0x304)
-#define MTK_ADSPPLL_CON1		(MTK_REG_APMIXDSYS_BASE + 0x308)
-#define MTK_ADSPPLL_CON2		(MTK_REG_APMIXDSYS_BASE + 0x30C)
-#define MTK_ADSPPLL_CON3		(MTK_REG_APMIXDSYS_BASE + 0x310)
-
-#define MTK_CLK_MODE			(MTK_REG_TOPCKGEN_BASE + 0x0)
-#define MTK_CLK_CFG_UPDATE		(MTK_REG_TOPCKGEN_BASE + 0x8)
-#define MTK_CLK_CFG_11			(MTK_REG_TOPCKGEN_BASE + 0x0EC)
-#define MTK_CLK_CFG_11_SET		(MTK_REG_TOPCKGEN_BASE + 0x0F0)
-#define MTK_CLK_CFG_11_CLR		(MTK_REG_TOPCKGEN_BASE + 0x0F4)
-#define MTK_CLK_CFG_15			(MTK_REG_TOPCKGEN_BASE + 0x180)
-#define MTK_CLK_CFG_15_SET		(MTK_REG_TOPCKGEN_BASE + 0x184)
-#define MTK_CLK_CFG_15_CLR		(MTK_REG_TOPCKGEN_BASE + 0x188)
-
-/* MBOX registers */
-#define MTK_ADSP_MBOX_REG_BASE(x)	(0x10686000 + (0x1000 * (x)))
-#define MTK_ADSP_MBOX_REG_SIZE		(0x5000)
-#define MTK_ADSP_MBOX_IN_CMD(x)		(MTK_ADSP_MBOX_REG_BASE(x) + 0x100)
-#define MTK_ADSP_MBOX_IN_CMD_CLR(x)	(MTK_ADSP_MBOX_REG_BASE(x) + 0x108)
-#define MTK_ADSP_MBOX_OUT_CMD(x)	(MTK_ADSP_MBOX_REG_BASE(x) + 0x104)
-#define MTK_ADSP_MBOX_OUT_CMD_CLR(x)	(MTK_ADSP_MBOX_REG_BASE(x) + 0x10c)
-
-#endif /* MT_REG_BASE_H */
diff --git a/src/platform/mt8186/include/platform/drivers/timer.h b/src/platform/mt8186/include/platform/drivers/timer.h
deleted file mode 100644
index f32777bd5cfa..000000000000
--- a/src/platform/mt8186/include/platform/drivers/timer.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2022 MediaTek. All rights reserved.
- *
- * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
- *         Tinghan Shen <tinghan.shen@mediatek.com>
- */
-
-#ifndef __PLATFORM_DRIVERS_TIMER_H__
-#define __PLATFORM_DRIVERS_TIMER_H__
-
-#include <rtos/bit.h>
-#include <platform/drivers/mt_reg_base.h>
-
-/*-------timer:ostimer0-------*/
-enum ostimer {
-	OSTIMER0 = 0,
-	OSTIMER1,
-	OSTIMER2,
-	OSTIMER3,
-	NR_TMRS
-};
-
-#define MTK_TIMER_CON(n)		(MTK_DSP_OS_TIMER_BASE + 0x0 + 0x10 * (n))
-#define MTK_TIMER_RST_VAL(n)		(MTK_DSP_OS_TIMER_BASE + 0x4 + 0x10 * (n))
-#define MTK_TIMER_CUR_VAL(n)		(MTK_DSP_OS_TIMER_BASE + 0x8 + 0x10 * (n))
-#define MTK_TIMER_IRQ_ACK(n)		(MTK_DSP_OS_TIMER_BASE + 0xC + 0x10 * (n))
-
-#define MTK_TIMER_ENABLE_BIT		BIT(0)
-#define MTK_TIMER_IRQ_ENABLE		BIT(0)
-#define MTK_TIMER_IRQ_STA		BIT(4)
-#define MTK_TIMER_IRQ_CLEAR		BIT(5)
-#define MTK_TIMER_CLKSRC_BIT		(BIT(4) | BIT(5))
-
-#define MTK_TIMER_CLK_SRC_OFFSET	4
-#define MTK_TIMER_CLK_SRC_CLK_26M	0
-#define MTK_TIMER_CLK_SRC_BCLK		BIT(4)
-#define MTK_TIMER_CLK_SRC_PCLK		BIT(5)
-
-/*-------platform_timer: 64 bit systimer-------*/
-#define MTK_OSTIMER_CON			(MTK_DSP_OS_TIMER_BASE + 0x80)
-#define MTK_OSTIMER_INIT_L		(MTK_DSP_OS_TIMER_BASE + 0x84)
-#define MTK_OSTIMER_INIT_H		(MTK_DSP_OS_TIMER_BASE + 0x88)
-#define MTK_OSTIMER_CUR_L		(MTK_DSP_OS_TIMER_BASE + 0x8C)
-#define MTK_OSTIMER_CUR_H		(MTK_DSP_OS_TIMER_BASE + 0x90)
-#define MTK_OSTIMER_TVAL		(MTK_DSP_OS_TIMER_BASE + 0x94)
-#define MTK_OSTIMER_IRQ_ACK		(MTK_DSP_OS_TIMER_BASE + 0x98)
-
-#define MTK_OSTIMER_EN_BIT			BIT(0)
-
-#endif /* __PLATFORM_DRIVERS_TIMER_H__ */
diff --git a/src/platform/mt8186/include/platform/lib/clk.h b/src/platform/mt8186/include/platform/lib/clk.h
deleted file mode 100644
index d48e83bd75b9..000000000000
--- a/src/platform/mt8186/include/platform/lib/clk.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2022 MediaTek. All rights reserved.
- *
- * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
- *         Tinghan Shen <tinghan.shen@mediatek.com>
- */
-
-#ifdef __SOF_LIB_CLK_H__
-
-#ifndef __PLATFORM_LIB_CLK_H__
-#define __PLATFORM_LIB_CLK_H__
-
-#include <stdint.h>
-
-struct sof;
-
-#define CPU_DEFAULT_IDX				0
-
-#define CLK_CPU(x)				(x)
-#define CLK_DEFAULT_CPU_HZ			26000000
-/* check vcore voltage before select higher frequency than 300M */
-#define CLK_MAX_CPU_HZ				300000000
-#define NUM_CLOCKS				1
-#define NUM_CPU_FREQ				3
-
-/* MTK_ADSP_CLK_BUS_UPDATE */
-#define MTK_ADSP_CLK_BUS_UPDATE_BIT		BIT(31)
-
-/* MTK_ADSP_BUS_SRC */
-#define MTK_ADSP_CLK_BUS_SRC_EMI		0
-#define MTK_ADSP_CLK_BUS_SRC_LOCAL		1
-
-/* MTK_CLK_CFG_11 */
-#define MTK_CLK_CFG_ADSP_UPDATE			BIT(16)
-#define MTK_CLK_ADSP_OFFSET			24
-#define MTK_CLK_ADSP_MASK			0x7
-#define MTK_CLK_ADSP_26M			0
-#define MTK_CLK_ADSP_ULPOSC_D_10		1 /* 25M, Not used */
-#define MTK_CLK_ADSP_DSPPLL			2
-#define MTK_CLK_ADSP_DSPPLL_2			3
-#define MTK_CLK_ADSP_DSPPLL_4			4
-#define MTK_CLK_ADSP_DSPPLL_8			5
-
-/* MTK_CLK_CFG_15 */
-#define MTK_CLK_CFG_ADSP_BUS_UPDATE		BIT(31)
-#define MTK_CLK_ADSP_BUS_OFFSET			17
-#define MTK_CLK_ADSP_BUS_MASK			0x7
-#define MTK_CLK_ADSP_BUS_26M			0
-#define MTK_CLK_ADSP_BUS_ULPOSC_D_2		1
-#define MTK_CLK_ADSP_BUS_MAINPPLL_D_5		2
-#define MTK_CLK_ADSP_BUS_MAINPPLL_D_2_D_2	3
-#define MTK_CLK_ADSP_BUS_MAINPPLL_D_3		4
-#define MTK_CLK_ADSP_BUS_RESERVED		5
-#define MTK_CLK_ADSP_BUS_UNIVPLL_D_3		6
-
-#define MTK_PLL_BASE_EN				BIT(0)
-#define MTK_PLL_PWR_ON				BIT(0)
-#define MTK_PLL_ISO_EN				BIT(1)
-
-#define MTK_PLL_DIV_RATIO_300M			0x831713B2
-#define MTK_PLL_DIV_RATIO_400M			0x831EC4ED
-
-/* List resource from low to high request */
-/* 0 is the lowest request */
-enum ADSP_HW_DSP_CLK {
-	ADSP_CLK_26M = 0,
-	ADSP_CLK_PLL_300M,
-	ADSP_CLK_PLL_400M,
-};
-
-void platform_clock_init(struct sof *sof);
-
-#endif /* __PLATFORM_LIB_CLK_H__ */
-
-#else
-
-#error "This file shouldn't be included from outside of sof/lib/clk.h"
-
-#endif /* __SOF_LIB_CLK_H__ */
diff --git a/src/platform/mt8186/include/platform/lib/cpu.h b/src/platform/mt8186/include/platform/lib/cpu.h
deleted file mode 100644
index ecbb220d5f02..000000000000
--- a/src/platform/mt8186/include/platform/lib/cpu.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2022 MediaTek. All rights reserved.
- *
- * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
- *         Tinghan Shen <tinghan.shen@mediatek.com>
- */
-
-#ifdef __SOF_LIB_CPU_H__
-
-#ifndef __PLATFORM_LIB_CPU_H__
-#define __PLATFORM_LIB_CPU_H__
-
-/** \brief Id of primary DSP core */
-#define PLATFORM_PRIMARY_CORE_ID	0
-
-#endif /* __PLATFORM_LIB_CPU_H__ */
-
-#else
-
-#error "This file shouldn't be included from outside of sof/lib/cpu.h"
-
-#endif /* __SOF_LIB_CPU_H__ */
diff --git a/src/platform/mt8186/include/platform/lib/dai.h b/src/platform/mt8186/include/platform/lib/dai.h
deleted file mode 100644
index 8d367ed32cdd..000000000000
--- a/src/platform/mt8186/include/platform/lib/dai.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2022 MediaTek. All rights reserved.
- *
- * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
- *         Tinghan Shen <tinghan.shen@mediatek.com>
- */
-
-#ifdef __SOF_LIB_DAI_H__
-
-#ifndef __PLATFORM_LIB_DAI_H__
-#define __PLATFORM_LIB_DAI_H__
-
-#endif /* __PLATFORM_LIB_DAI_H__ */
-
-#else
-
-#error "This file shouldn't be included from outside of sof/lib/dai.h"
-
-#endif /* __SOF_LIB_DAI_H__ */
diff --git a/src/platform/mt8186/include/platform/lib/dma.h b/src/platform/mt8186/include/platform/lib/dma.h
deleted file mode 100644
index a7080012ffd9..000000000000
--- a/src/platform/mt8186/include/platform/lib/dma.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2022 MediaTek. All rights reserved.
- *
- * Author: Bo Pan <bo.pan@mediatek.com>
- *         Allen-KH Cheng <allen-kh.cheng@mediatek.com>
- *         Tinghan Shen <tinghan.shen@mediatek.com>
- */
-
-#ifdef __SOF_LIB_DMA_H__
-
-#ifndef __PLATFORM_LIB_DMA_H__
-#define __PLATFORM_LIB_DMA_H__
-
-#define PLATFORM_NUM_DMACS		2
-
-/* max number of supported DMA channels */
-#define PLATFORM_MAX_DMA_CHAN		32
-
-#define DMA_ID_AFE_MEMIF		0
-#define DMA_ID_HOST			1
-
-#define dma_chan_irq(dma, chan)		dma_irq(dma)
-#define dma_chan_irq_name(dma, chan)	dma_irq_name(dma)
-
-#endif /* __PLATFORM_LIB_DMA_H__ */
-
-#else
-
-#error "This file shouldn't be included from outside of sof/lib/dma.h"
-
-#endif /* __SOF_LIB_DMA_H__ */
diff --git a/src/platform/mt8186/include/platform/lib/mailbox.h b/src/platform/mt8186/include/platform/lib/mailbox.h
deleted file mode 100644
index 37714ca7811d..000000000000
--- a/src/platform/mt8186/include/platform/lib/mailbox.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2022 MediaTek. All rights reserved.
- *
- * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
- *         Tinghan Shen <tinghan.shen@mediatek.com>
- */
-
-#ifdef __SOF_LIB_MAILBOX_H__
-
-#ifndef __PLATFORM_LIB_MAILBOX_H__
-#define __PLATFORM_LIB_MAILBOX_H__
-
-#include <sof/lib/memory.h>
-#include <stddef.h>
-#include <stdint.h>
-
-/*
- * The Window Region on MT8186 SRAM is organised like this :-
- * +--------------------------------------------------------------------------+
- * | Offset              | Region         |  Size                             |
- * +---------------------+----------------+-----------------------------------+
- * | SRAM_OUTBOX_BASE    | Outbox         |  SRAM_MAILBOX_SIZE                |
- * +---------------------+----------------+-----------------------------------+
- * | SRAM_INBOX_BASE     | Inbox          |  SRAM_INBOX_SIZE                  |
- * +---------------------+----------------+-----------------------------------+
- * | SRAM_DEBUG_BASE     | Debug data     |  SRAM_DEBUG_SIZE                  |
- * +---------------------+----------------+-----------------------------------+
- * | SRAM_EXCEPT_BASE    | Except         |  SRAM_EXCEPT_SIZE                 |
- * +---------------------+----------------+-----------------------------------+
- * | SRAM_STREAM_BASE    | Stream         |  SRAM_STREAM_SIZE                 |
- * +---------------------+----------------+-----------------------------------+
- * | SRAM_TRACE_BASE     | Trace Buffer   |  SRAM_TRACE_SIZE                  |
- * +---------------------+----------------+-----------------------------------+
- */
-
-#define MAILBOX_DSPBOX_SIZE		SRAM_OUTBOX_SIZE
-#define MAILBOX_DSPBOX_BASE		SRAM_OUTBOX_BASE
-#define MAILBOX_DSPBOX_OFFSET		SRAM_OUTBOX_OFFSET
-
-#define MAILBOX_HOSTBOX_SIZE		SRAM_INBOX_SIZE
-#define MAILBOX_HOSTBOX_BASE		SRAM_INBOX_BASE
-#define MAILBOX_HOSTBOX_OFFSET		SRAM_INBOX_OFFSET
-
-#define MAILBOX_DEBUG_SIZE		SRAM_DEBUG_SIZE
-#define MAILBOX_DEBUG_BASE		SRAM_DEBUG_BASE
-#define MAILBOX_DEBUG_OFFSET		SRAM_DEBUG_OFFSET
-
-#define MAILBOX_EXCEPTION_SIZE		SRAM_EXCEPT_SIZE
-#define MAILBOX_EXCEPTION_BASE		SRAM_EXCEPT_BASE
-#define MAILBOX_EXCEPTION_OFFSET	SRAM_EXCEPT_OFFSET
-
-#define MAILBOX_STREAM_SIZE		SRAM_STREAM_SIZE
-#define MAILBOX_STREAM_BASE		SRAM_STREAM_BASE
-#define MAILBOX_STREAM_OFFSET		SRAM_STREAM_OFFSET
-
-#define MAILBOX_TRACE_SIZE		SRAM_TRACE_SIZE
-#define MAILBOX_TRACE_BASE		SRAM_TRACE_BASE
-#define MAILBOX_TRACE_OFFSET		SRAM_TRACE_OFFSET
-
-static inline void mailbox_sw_reg_write(size_t offset, uint32_t src)
-{
-	volatile uint32_t *ptr;
-
-	ptr = (volatile uint32_t *)(MAILBOX_DEBUG_BASE + offset);
-	*ptr = src;
-}
-
-#define ADSP_IPI_OP_REQ	0x1
-#define ADSP_IPI_OP_RSP	0x2
-void trigger_irq_to_host_req(void);
-void trigger_irq_to_host_rsp(void);
-
-#endif /* __PLATFORM_LIB_MAILBOX_H__ */
-
-#else
-
-#error "This file shouldn't be included from outside of sof/lib/mailbox.h"
-
-#endif /* __SOF_LIB_MAILBOX_H__ */
diff --git a/src/platform/mt8186/include/platform/lib/memory.h b/src/platform/mt8186/include/platform/lib/memory.h
deleted file mode 100644
index 68c95bb53db0..000000000000
--- a/src/platform/mt8186/include/platform/lib/memory.h
+++ /dev/null
@@ -1,217 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2022 MediaTek. All rights reserved.
- *
- * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
- *         Tinghan Shen <tinghan.shen@mediatek.com>
- */
-
-#ifdef __SOF_LIB_MEMORY_H__
-
-#ifndef __PLATFORM_LIB_MEMORY_H__
-#define __PLATFORM_LIB_MEMORY_H__
-
-#include <rtos/cache.h>
-
-/* data cache line alignment */
-#define PLATFORM_DCACHE_ALIGN sizeof(void *)
-
-/* physical DSP addresses */
-#define SRAM_BASE			0x4e100000
-#define SRAM_SIZE			0x80000
-
-/* reset vector + rodata + module_init + text + data + bss */
-#define SOF_DATA_SIZE			0x80000
-#define VECTOR_SIZE			0x700
-#define SRAM_START			(SRAM_BASE + VECTOR_SIZE)
-
-#define DRAM_BASE			0x60000000
-#define DRAM0_SIZE			0x500000
-#define MAILBOX_BASE			(DRAM_BASE + DRAM0_SIZE)
-#define DSP_SYS_SIZE			0xA00000
-
-#define UUID_ENTRY_ELF_BASE		(SRAM_BASE + SOF_DATA_SIZE)
-#define UUID_ENTRY_ELF_SIZE		0x6000
-
-#define LOG_ENTRY_ELF_BASE		(UUID_ENTRY_ELF_BASE + UUID_ENTRY_ELF_SIZE)
-#define LOG_ENTRY_ELF_SIZE		0x20000
-#define EXT_MANIFEST_ELF_BASE		(LOG_ENTRY_ELF_BASE + LOG_ENTRY_ELF_SIZE)
-#define EXT_MANIFEST_ELF_SIZE		(SRAM_BASE + SRAM_SIZE - EXT_MANIFEST_ELF_BASE)
-
-/*
- * The Memory Layout on MT8186 are organised like this :-
- *
- * +--------------------------------------------------------------------------+
- * | Offset              | Region         |  Size                             |
- * +---------------------+----------------+-----------------------------------+
- * | SRAM_START          | RO Data        |  SOF_DATA_SIZE                    |
- * |                     | text           |                                   |
- * |                     | Data           |                                   |
- * |                     | BSS            |                                   |
- * +---------------------+----------------+-----------------------------------+
- * | fw_ready                                                                 |
- * +---------------------+----------------+-----------------------------------+
- * | static_uuid                                                              |
- * +---------------------+----------------+-----------------------------------+
- * | static_log                                                               |
- * +---------------------+----------------+-----------------------------------+
- * | fw_metadata                                                              |
- * +---------------------+----------------+-----------------------------------+
- *
- * +---------------------+----------------+-----------------------------------+
- * | SOF_DRAM_BASE       |                |  SOF_DRAM_SIZE                    |
- * +---------------------+----------------+-----------------------------------+
- * | HEAP_SYSTEM_BASE    | System Heap    |  HEAP_SYSTEM_SIZE                 |
- * +---------------------+----------------+-----------------------------------+
- * | HEAP_RUNTIME_BASE   | Runtime Heap   |  HEAP_RUNTIME_SIZE                |
- * +---------------------+----------------+-----------------------------------+
- * | HEAP_BUFFER_BASE    | Module Buffers |  HEAP_BUFFER_SIZE                 |
- * +---------------------+----------------+-----------------------------------+
- * | SOF_STACK_END       | Stack          |  SOF_STACK_SIZE                   |
- * +---------------------+----------------+-----------------------------------+
- * | SOF_STACK_BASE      |                |                                   |
- * +---------------------+----------------+-----------------------------------+
- * | MAILBOX_BASE        |                |  SOF_MAILBOX_SIZE                 |
- * +---------------------+----------------+-----------------------------------+
- */
-
-#define SRAM_OUTBOX_BASE	MAILBOX_BASE
-#define SRAM_OUTBOX_SIZE	0x1000
-#define SRAM_OUTBOX_OFFSET	0
-
-#define SRAM_INBOX_BASE		(SRAM_OUTBOX_BASE + SRAM_OUTBOX_SIZE)
-#define SRAM_INBOX_SIZE		0x1000
-#define SRAM_INBOX_OFFSET	SRAM_OUTBOX_SIZE
-
-#define SRAM_DEBUG_BASE		(SRAM_INBOX_BASE + SRAM_INBOX_SIZE)
-#define SRAM_DEBUG_SIZE		0x800
-#define SRAM_DEBUG_OFFSET	(SRAM_INBOX_OFFSET + SRAM_INBOX_SIZE)
-
-#define SRAM_EXCEPT_BASE	(SRAM_DEBUG_BASE + SRAM_DEBUG_SIZE)
-#define SRAM_EXCEPT_SIZE	0x800
-#define SRAM_EXCEPT_OFFSET	(SRAM_DEBUG_OFFSET + SRAM_DEBUG_SIZE)
-
-#define SRAM_STREAM_BASE	(SRAM_EXCEPT_BASE + SRAM_EXCEPT_SIZE)
-#define SRAM_STREAM_SIZE	0x1000
-#define SRAM_STREAM_OFFSET	(SRAM_EXCEPT_OFFSET + SRAM_EXCEPT_SIZE)
-
-#define SRAM_TRACE_BASE		(SRAM_STREAM_BASE + SRAM_STREAM_SIZE)
-#define SRAM_TRACE_SIZE		0x1000
-#define SRAM_TRACE_OFFSET	(SRAM_STREAM_OFFSET + SRAM_STREAM_SIZE)
-
-/*4K + 4K +2K + 2K + 4K + 4K = 20KB*/
-#define SOF_MAILBOX_SIZE                                        \
-	(SRAM_INBOX_SIZE + SRAM_OUTBOX_SIZE + SRAM_DEBUG_SIZE + \
-	 SRAM_EXCEPT_SIZE + SRAM_STREAM_SIZE + SRAM_TRACE_SIZE)
-
-/* SOF image on DRAM */
-#define SOF_DRAM_BASE	DRAM_BASE
-#define SOF_DRAM_SIZE	0x100000
-
-/* Heap section sizes for module pool */
-#define HEAP_RT_COUNT8		0
-#define HEAP_RT_COUNT16		48
-#define HEAP_RT_COUNT32		48
-#define HEAP_RT_COUNT64		32
-#define HEAP_RT_COUNT128	32
-#define HEAP_RT_COUNT256	32
-#define HEAP_RT_COUNT512	32
-#define HEAP_RT_COUNT1024	4
-#define HEAP_RT_COUNT2048	2
-#define HEAP_RT_COUNT4096	2
-
-/* Heap section sizes for system runtime heap */
-#define HEAP_SYS_RT_COUNT64	128
-#define HEAP_SYS_RT_COUNT512	16
-#define HEAP_SYS_RT_COUNT1024	8
-
-/* Heap configuration */
-
-#define HEAP_SYSTEM_BASE	(SOF_DRAM_BASE + SOF_DRAM_SIZE)
-#define HEAP_SYSTEM_SIZE	0x6000
-
-#define HEAP_SYS_RUNTIME_BASE	(HEAP_SYSTEM_BASE + HEAP_SYSTEM_SIZE)
-/*24KB*/
-#define HEAP_SYS_RUNTIME_SIZE                                    \
-	(HEAP_SYS_RT_COUNT64 * 64 + HEAP_SYS_RT_COUNT512 * 512 + \
-	 HEAP_SYS_RT_COUNT1024 * 1024)
-
-#define HEAP_RUNTIME_BASE (HEAP_SYS_RUNTIME_BASE + HEAP_SYS_RUNTIME_SIZE)
-/*48*(16 +32) + 32*(64 128+256) + 4*(512+1024) + 1*2048 = 24832 = 24.25KB*/
-#define HEAP_RUNTIME_SIZE                                        \
-	(HEAP_RT_COUNT8 * 8 + HEAP_RT_COUNT16 * 16 +             \
-	 HEAP_RT_COUNT32 * 32 + HEAP_RT_COUNT64 * 64 +           \
-	 HEAP_RT_COUNT128 * 128 + HEAP_RT_COUNT256 * 256 +       \
-	 HEAP_RT_COUNT512 * 512 + HEAP_RT_COUNT1024 * 1024 +     \
-	 HEAP_RT_COUNT2048 * 2048 + HEAP_RT_COUNT4096 * 4096)
-
-#define HEAP_BUFFER_BASE (HEAP_RUNTIME_BASE + HEAP_RUNTIME_SIZE)
-#define HEAP_BUFFER_SIZE                                           \
-	(DRAM0_SIZE - SOF_DRAM_SIZE - HEAP_RUNTIME_SIZE - SOF_STACK_TOTAL_SIZE -   \
-	 HEAP_SYS_RUNTIME_SIZE - HEAP_SYSTEM_SIZE)
-
-#define HEAP_BUFFER_BLOCK_SIZE		0x100
-#define HEAP_BUFFER_COUNT		(HEAP_BUFFER_SIZE / HEAP_BUFFER_BLOCK_SIZE)
-
-#define PLATFORM_HEAP_SYSTEM		1 /* one per core */
-#define PLATFORM_HEAP_SYSTEM_RUNTIME	1 /* one per core */
-#define PLATFORM_HEAP_RUNTIME		1
-#define PLATFORM_HEAP_BUFFER		1
-
-/* Stack configuration */
-#define SOF_STACK_SIZE			(CONFIG_SOF_STACK_SIZE)
-#define SOF_STACK_TOTAL_SIZE		SOF_STACK_SIZE /*4KB*/
-#define SOF_STACK_BASE			(DRAM_BASE + DRAM0_SIZE)
-#define SOF_STACK_END			(SOF_STACK_BASE - SOF_STACK_TOTAL_SIZE)
-
-/* Vector and literal sizes - not in core-isa.h */
-#define SOF_MEM_VECT_LIT_SIZE		0x4
-#define SOF_MEM_VECT_TEXT_SIZE		0x1c
-#define SOF_MEM_VECT_SIZE		(SOF_MEM_VECT_TEXT_SIZE + SOF_MEM_VECT_LIT_SIZE)
-
-#define SOF_MEM_RESET_TEXT_SIZE		0x2e0
-#define SOF_MEM_RESET_LIT_SIZE		0x120
-#define SOF_MEM_VECBASE_LIT_SIZE	0x178
-
-#define SOF_MEM_RO_SIZE			0x8
-
-#define HEAP_BUF_ALIGNMENT		DCACHE_LINE_SIZE
-
-/** \brief EDF task's default stack size in bytes. */
-#define PLATFORM_TASK_DEFAULT_STACK_SIZE	3072
-
-#if !defined(__ASSEMBLER__) && !defined(LINKER)
-
-struct sof;
-
-void platform_init_memmap(struct sof *sof);
-
-#define uncache_to_cache(address)	address
-#define cache_to_uncache(address)	address
-#define cache_to_uncache_init(address)	address
-#define is_uncached(address)		0
-
-/**
- * \brief Function for keeping shared data synchronized.
- * It's used after usage of data shared by different cores.
- * Such data is dynamically allocated with SOF_MEM_FLAG_SHARED
- * flag. Does nothing, since mt8186 doesn't support SMP.
- */
-
-static inline void *platform_rfree_prepare(void *ptr)
-{
-	return ptr;
-}
-
-#endif
-
-#define host_to_local(addr)	(addr)
-#define local_to_host(addr)	(addr)
-
-#endif /* __PLATFORM_LIB_MEMORY_H__ */
-
-#else
-
-#error "This file shouldn't be included from outside of sof/lib/memory.h"
-
-#endif /* __SOF_LIB_MEMORY_H__ */
diff --git a/src/platform/mt8186/include/platform/lib/pm_runtime.h b/src/platform/mt8186/include/platform/lib/pm_runtime.h
deleted file mode 100644
index 581f9d77f698..000000000000
--- a/src/platform/mt8186/include/platform/lib/pm_runtime.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2022 MediaTek. All rights reserved.
- *
- * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
- *         Tinghan Shen <tinghan.shen@mediatek.com>
- */
-
-#ifdef __SOF_LIB_PM_RUNTIME_H__
-
-#ifndef __PLATFORM_LIB_PM_RUNTIME_H__
-#define __PLATFORM_LIB_PM_RUNTIME_H__
-
-#include <stdint.h>
-
-struct pm_runtime_data;
-
-/**
- * \brief Initializes platform specific runtime power management.
- * \param[in,out] prd Runtime power management data.
- */
-static inline void platform_pm_runtime_init(struct pm_runtime_data *prd)
-{
-}
-
-/**
- * \brief Retrieves platform specific power management resource.
- *
- * \param[in] context Type of power management context.
- * \param[in] index Index of the device.
- * \param[in] flags Flags, set of RPM_...
- */
-static inline void platform_pm_runtime_get(uint32_t context, uint32_t index, uint32_t flags)
-{
-}
-
-/**
- * \brief Releases platform specific power management resource.
- *
- * \param[in] context Type of power management context.
- * \param[in] index Index of the device.
- * \param[in] flags Flags, set of RPM_...
- */
-static inline void platform_pm_runtime_put(uint32_t context, uint32_t index, uint32_t flags)
-{
-}
-
-static inline void platform_pm_runtime_enable(uint32_t context, uint32_t index)
-{
-}
-
-static inline void platform_pm_runtime_disable(uint32_t context, uint32_t index)
-{
-}
-
-static inline bool platform_pm_runtime_is_active(uint32_t context, uint32_t index)
-{
-	return false;
-}
-
-#endif /* __PLATFORM_LIB_PM_RUNTIME_H__ */
-
-#else
-
-#error "This file shouldn't be included from outside of sof/lib/pm_runtime.h"
-
-#endif /* __SOF_LIB_PM_RUNTIME_H__ */
diff --git a/src/platform/mt8186/include/platform/mt8186-afe-common.h b/src/platform/mt8186/include/platform/mt8186-afe-common.h
deleted file mode 100644
index 8667369820c1..000000000000
--- a/src/platform/mt8186/include/platform/mt8186-afe-common.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2022 MediaTek. All rights reserved.
- *
- * Author: Chunxu Li <chunxu.li@mediatek.com>
- */
-
-#ifndef _MT_8186_AFE_COMMON_H_
-#define _MT_8186_AFE_COMMON_H_
-
-/* AFE: the abbreviation for Audio Front End  */
-
-enum {
-	MT8186_MEMIF_START,
-	MT8186_MEMIF_DL_START = MT8186_MEMIF_START,
-	MT8186_MEMIF_DL1 = MT8186_MEMIF_DL_START,
-	MT8186_MEMIF_DL2,
-	MT8186_MEMIF_DL_END,
-	MT8186_MEMIF_UL_START = MT8186_MEMIF_DL_END,
-	MT8186_MEMIF_UL1 = MT8186_MEMIF_UL_START,
-	MT8186_MEMIF_UL2,
-	MT8186_MEMIF_UL_END,
-	MT8186_MEMIF_END = MT8186_MEMIF_UL_END,
-	MT8186_MEMIF_DL_NUM = (MT8186_MEMIF_DL_END - MT8186_MEMIF_DL_START),
-	MT8186_MEMIF_UL_NUM = (MT8186_MEMIF_UL_END - MT8186_MEMIF_UL_START),
-	MT8186_MEMIF_NUM = (MT8186_MEMIF_END - MT8186_MEMIF_START),
-};
-
-enum {
-	MT8186_IRQ_0,
-	MT8186_IRQ_1,
-	MT8186_IRQ_2,
-	MT8186_IRQ_3,
-	MT8186_IRQ_4,
-	MT8186_IRQ_5,
-	MT8186_IRQ_6,
-	MT8186_IRQ_7,
-	MT8186_IRQ_8,
-	MT8186_IRQ_9,
-	MT8186_IRQ_10,
-	MT8186_IRQ_11,
-	MT8186_IRQ_12,
-	MT8186_IRQ_13,
-	MT8186_IRQ_14,
-	MT8186_IRQ_15,
-	MT8186_IRQ_16,
-	MT8186_IRQ_17,
-	MT8186_IRQ_18,
-	MT8186_IRQ_19,
-	MT8186_IRQ_20,
-	MT8186_IRQ_21,
-	MT8186_IRQ_22,
-	MT8186_IRQ_23,
-	MT8186_IRQ_24,
-	MT8186_IRQ_25,
-	MT8186_IRQ_26,
-	MT8186_IRQ_NUM,
-};
-
-enum {
-	MT8186_AFE_IO_I2S1,
-	MT8186_AFE_IO_I2S3,
-	MT8186_AFE_IO_UL_SRC1,
-	MT8186_AFE_IO_I2S0,
-	MT8186_DAI_NUM,
-};
-
-#endif
diff --git a/src/platform/mt8186/include/platform/mt8186-afe-regs.h b/src/platform/mt8186/include/platform/mt8186-afe-regs.h
deleted file mode 100644
index d7cbede7aa1c..000000000000
--- a/src/platform/mt8186/include/platform/mt8186-afe-regs.h
+++ /dev/null
@@ -1,1737 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2022 MediaTek. All rights reserved.
- *
- * Author: Chunxu Li <chunxu.li@mediatek.com>
- */
-
-#ifndef _MT8186_REG_H_
-#define _MT8186_REG_H_
-
-#define AFE_SRAM_BASE (0x11210000 + 0x2000)
-#define AFE_SRAM_SIZE (0x9C00)
-#define AFE_BASE_ADDR (0x11210000)
-
-#define AUDIO_TOP_CON0                    (0x0000)
-#define AUDIO_TOP_CON1                    (0x0004)
-#define AUDIO_TOP_CON2                    (0x0008)
-#define AUDIO_TOP_CON3                    (0x000c)
-#define AFE_DAC_CON0                      (0x0010)
-#define AFE_I2S_CON                       (0x0018)
-#define AFE_CONN0_0                       (0x0020)
-#define AFE_CONN1_0                       (0x0024)
-#define AFE_CONN2_0                       (0x0028)
-#define AFE_CONN3_0                       (0x002c)
-#define AFE_CONN4_0                       (0x0030)
-#define AFE_I2S_CON1                      (0x0034)
-#define AFE_I2S_CON2                      (0x0038)
-#define AFE_I2S_CON3                      (0x0040)
-#define AFE_CONN5_0                       (0x0044)
-#define AFE_CONN_24BIT_0                  (0x0048)
-#define AFE_DL1_CON0                      (0x004c)
-#define AFE_DL1_BASE_MSB                  (0x0050)
-#define AFE_DL1_BASE                      (0x0054)
-#define AFE_DL1_CUR_MSB                   (0x0058)
-#define AFE_DL1_CUR                       (0x005c)
-#define AFE_DL1_END_MSB                   (0x0060)
-#define AFE_DL1_END                       (0x0064)
-#define AFE_DL2_CON0                      (0x0068)
-#define AFE_DL2_BASE_MSB                  (0x006c)
-#define AFE_DL2_BASE                      (0x0070)
-#define AFE_DL2_CUR_MSB                   (0x0074)
-#define AFE_DL2_CUR                       (0x0078)
-#define AFE_DL2_END_MSB                   (0x007c)
-#define AFE_DL2_END                       (0x0080)
-#define AFE_DL3_CON0                      (0x0084)
-#define AFE_DL3_BASE_MSB                  (0x0088)
-#define AFE_DL3_BASE                      (0x008c)
-#define AFE_DL3_CUR_MSB                   (0x0090)
-#define AFE_DL3_CUR                       (0x0094)
-#define AFE_DL3_END_MSB                   (0x0098)
-#define AFE_DL3_END                       (0x009c)
-#define AFE_CONN6_0                       (0x00bc)
-#define AFE_DL4_CON0                      (0x00cc)
-#define AFE_DL4_BASE_MSB                  (0x00d0)
-#define AFE_DL4_BASE                      (0x00d4)
-#define AFE_DL4_CUR_MSB                   (0x00d8)
-#define AFE_DL4_CUR                       (0x00dc)
-#define AFE_DL4_END_MSB                   (0x00e0)
-#define AFE_DL4_END                       (0x00e4)
-#define AFE_DL12_CON0                     (0x00e8)
-#define AFE_DL12_BASE_MSB                 (0x00ec)
-#define AFE_DL12_BASE                     (0x00f0)
-#define AFE_DL12_CUR_MSB                  (0x00f4)
-#define AFE_DL12_CUR                      (0x00f8)
-#define AFE_DL12_END_MSB                  (0x00fc)
-#define AFE_DL12_END                      (0x0100)
-#define AFE_ADDA_DL_SRC2_CON0             (0x0108)
-#define AFE_ADDA_DL_SRC2_CON1             (0x010c)
-#define AFE_ADDA_UL_SRC_CON0              (0x0114)
-#define AFE_ADDA_UL_SRC_CON1              (0x0118)
-#define AFE_ADDA_TOP_CON0                 (0x0120)
-#define AFE_ADDA_UL_DL_CON0               (0x0124)
-#define AFE_ADDA_SRC_DEBUG                (0x012c)
-#define AFE_ADDA_SRC_DEBUG_MON0           (0x0130)
-#define AFE_ADDA_SRC_DEBUG_MON1           (0x0134)
-#define AFE_ADDA_UL_SRC_MON0              (0x0148)
-#define AFE_ADDA_UL_SRC_MON1              (0x014c)
-#define AFE_SECURE_CON0                   (0x0150)
-#define AFE_SRAM_BOUND                    (0x0154)
-#define AFE_SECURE_CON1                   (0x0158)
-#define AFE_SECURE_CONN0                  (0x015c)
-#define AFE_VUL_CON0                      (0x0170)
-#define AFE_VUL_BASE_MSB                  (0x0174)
-#define AFE_VUL_BASE                      (0x0178)
-#define AFE_VUL_CUR_MSB                   (0x017c)
-#define AFE_VUL_CUR                       (0x0180)
-#define AFE_VUL_END_MSB                   (0x0184)
-#define AFE_VUL_END                       (0x0188)
-#define AFE_SIDETONE_DEBUG                (0x01d0)
-#define AFE_SIDETONE_MON                  (0x01d4)
-#define AFE_SINEGEN_CON2                  (0x01dc)
-#define AFE_SIDETONE_CON0                 (0x01e0)
-#define AFE_SIDETONE_COEFF                (0x01e4)
-#define AFE_SIDETONE_CON1                 (0x01e8)
-#define AFE_SIDETONE_GAIN                 (0x01ec)
-#define AFE_SINEGEN_CON0                  (0x01f0)
-#define AFE_TOP_CON0                      (0x0200)
-#define AFE_VUL2_CON0                     (0x020c)
-#define AFE_VUL2_BASE_MSB                 (0x0210)
-#define AFE_VUL2_BASE                     (0x0214)
-#define AFE_VUL2_CUR_MSB                  (0x0218)
-#define AFE_VUL2_CUR                      (0x021c)
-#define AFE_VUL2_END_MSB                  (0x0220)
-#define AFE_VUL2_END                      (0x0224)
-#define AFE_VUL3_CON0                     (0x0228)
-#define AFE_VUL3_BASE_MSB                 (0x022c)
-#define AFE_VUL3_BASE                     (0x0230)
-#define AFE_VUL3_CUR_MSB                  (0x0234)
-#define AFE_VUL3_CUR                      (0x0238)
-#define AFE_VUL3_END_MSB                  (0x023c)
-#define AFE_VUL3_END                      (0x0240)
-#define AFE_BUSY                          (0x0244)
-#define AFE_BUS_CFG                       (0x0250)
-#define AFE_ADDA_PREDIS_CON0              (0x0260)
-#define AFE_ADDA_PREDIS_CON1              (0x0264)
-#define AFE_I2S_MON                       (0x027c)
-#define AFE_ADDA_IIR_COEF_02_01           (0x0290)
-#define AFE_ADDA_IIR_COEF_04_03           (0x0294)
-#define AFE_ADDA_IIR_COEF_06_05           (0x0298)
-#define AFE_ADDA_IIR_COEF_08_07           (0x029c)
-#define AFE_ADDA_IIR_COEF_10_09           (0x02a0)
-#define AFE_IRQ_MCU_CON1                  (0x02e4)
-#define AFE_IRQ_MCU_CON2                  (0x02e8)
-#define AFE_DAC_MON                       (0x02ec)
-#define AFE_IRQ_MCU_CON3                  (0x02f0)
-#define AFE_IRQ_MCU_CON4                  (0x02f4)
-#define AFE_IRQ_MCU_CNT0                  (0x0300)
-#define AFE_IRQ_MCU_CNT6                  (0x0304)
-#define AFE_IRQ_MCU_CNT8                  (0x0308)
-#define AFE_IRQ0_MCU_CNT_MON              (0x0310)
-#define AFE_IRQ6_MCU_CNT_MON              (0x0314)
-#define AFE_VUL4_CON0                     (0x0358)
-#define AFE_VUL4_BASE_MSB                 (0x035c)
-#define AFE_VUL4_BASE                     (0x0360)
-#define AFE_VUL4_CUR_MSB                  (0x0364)
-#define AFE_VUL4_CUR                      (0x0368)
-#define AFE_VUL4_END_MSB                  (0x036c)
-#define AFE_VUL4_END                      (0x0370)
-#define AFE_VUL12_CON0                    (0x0374)
-#define AFE_VUL12_BASE_MSB                (0x0378)
-#define AFE_VUL12_BASE                    (0x037c)
-#define AFE_VUL12_CUR_MSB                 (0x0380)
-#define AFE_VUL12_CUR                     (0x0384)
-#define AFE_VUL12_END_MSB                 (0x0388)
-#define AFE_VUL12_END                     (0x038c)
-#define AFE_IRQ3_MCU_CNT_MON              (0x0398)
-#define AFE_IRQ4_MCU_CNT_MON              (0x039c)
-#define AFE_IRQ_MCU_CON0                  (0x03a0)
-#define AFE_IRQ_MCU_STATUS                (0x03a4)
-#define AFE_IRQ_MCU_CLR                   (0x03a8)
-#define AFE_IRQ_MCU_CNT1                  (0x03ac)
-#define AFE_IRQ_MCU_CNT2                  (0x03b0)
-#define AFE_IRQ_MCU_EN                    (0x03b4)
-#define AFE_IRQ_MCU_MON2                  (0x03b8)
-#define AFE_IRQ_MCU_CNT5                  (0x03bc)
-#define AFE_IRQ1_MCU_CNT_MON              (0x03c0)
-#define AFE_IRQ2_MCU_CNT_MON              (0x03c4)
-#define AFE_IRQ5_MCU_CNT_MON              (0x03cc)
-#define AFE_IRQ_MCU_DSP_EN                (0x03d0)
-#define AFE_IRQ_MCU_SCP_EN                (0x03d4)
-#define AFE_IRQ_MCU_CNT7                  (0x03dc)
-#define AFE_IRQ7_MCU_CNT_MON              (0x03e0)
-#define AFE_IRQ_MCU_CNT3                  (0x03e4)
-#define AFE_IRQ_MCU_CNT4                  (0x03e8)
-#define AFE_IRQ_MCU_CNT11                 (0x03ec)
-#define AFE_APLL1_TUNER_CFG               (0x03f0)
-#define AFE_APLL2_TUNER_CFG               (0x03f4)
-#define AFE_IRQ_MCU_MISS_CLR              (0x03f8)
-#define AFE_CONN33_0                      (0x0408)
-#define AFE_IRQ_MCU_CNT12                 (0x040c)
-#define AFE_GAIN1_CON0                    (0x0410)
-#define AFE_GAIN1_CON1                    (0x0414)
-#define AFE_GAIN1_CON2                    (0x0418)
-#define AFE_GAIN1_CON3                    (0x041c)
-#define AFE_CONN7_0                       (0x0420)
-#define AFE_GAIN1_CUR                     (0x0424)
-#define AFE_GAIN2_CON0                    (0x0428)
-#define AFE_GAIN2_CON1                    (0x042c)
-#define AFE_GAIN2_CON2                    (0x0430)
-#define AFE_GAIN2_CON3                    (0x0434)
-#define AFE_CONN8_0                       (0x0438)
-#define AFE_GAIN2_CUR                     (0x043c)
-#define AFE_CONN9_0                       (0x0440)
-#define AFE_CONN10_0                      (0x0444)
-#define AFE_CONN11_0                      (0x0448)
-#define AFE_CONN12_0                      (0x044c)
-#define AFE_CONN13_0                      (0x0450)
-#define AFE_CONN14_0                      (0x0454)
-#define AFE_CONN15_0                      (0x0458)
-#define AFE_CONN16_0                      (0x045c)
-#define AFE_CONN17_0                      (0x0460)
-#define AFE_CONN18_0                      (0x0464)
-#define AFE_CONN19_0                      (0x0468)
-#define AFE_CONN20_0                      (0x046c)
-#define AFE_CONN21_0                      (0x0470)
-#define AFE_CONN22_0                      (0x0474)
-#define AFE_CONN23_0                      (0x0478)
-#define AFE_CONN24_0                      (0x047c)
-#define AFE_CONN_RS_0                     (0x0494)
-#define AFE_CONN_DI_0                     (0x0498)
-#define AFE_CONN25_0                      (0x04b0)
-#define AFE_CONN26_0                      (0x04b4)
-#define AFE_CONN27_0                      (0x04b8)
-#define AFE_CONN28_0                      (0x04bc)
-#define AFE_CONN29_0                      (0x04c0)
-#define AFE_CONN30_0                      (0x04c4)
-#define AFE_CONN31_0                      (0x04c8)
-#define AFE_CONN32_0                      (0x04cc)
-#define AFE_SRAM_DELSEL_CON1              (0x04f4)
-#define AFE_CONN56_0                      (0x0500)
-#define AFE_CONN57_0                      (0x0504)
-#define AFE_CONN58_0                      (0x0508)
-#define AFE_CONN59_0                      (0x050c)
-#define AFE_CONN56_1                      (0x0510)
-#define AFE_CONN57_1                      (0x0514)
-#define AFE_CONN58_1                      (0x0518)
-#define AFE_CONN59_1                      (0x051c)
-#define PCM_INTF_CON1                     (0x0530)
-#define PCM_INTF_CON2                     (0x0538)
-#define PCM2_INTF_CON                     (0x053c)
-#define AFE_CM1_CON                       (0x0550)
-#define AFE_CM1_MON                       (0x0554)
-#define AFE_CONN34_0                      (0x0580)
-#define FPGA_CFG0                         (0x05b0)
-#define FPGA_CFG1                         (0x05b4)
-#define FPGA_CFG2                         (0x05c0)
-#define FPGA_CFG3                         (0x05c4)
-#define AUDIO_TOP_DBG_CON                 (0x05c8)
-#define AUDIO_TOP_DBG_MON0                (0x05cc)
-#define AUDIO_TOP_DBG_MON1                (0x05d0)
-#define AFE_IRQ8_MCU_CNT_MON              (0x05e4)
-#define AFE_IRQ11_MCU_CNT_MON             (0x05e8)
-#define AFE_IRQ12_MCU_CNT_MON             (0x05ec)
-#define AFE_IRQ_MCU_CNT9                  (0x0600)
-#define AFE_IRQ_MCU_CNT10                 (0x0604)
-#define AFE_IRQ_MCU_CNT13                 (0x0608)
-#define AFE_IRQ_MCU_CNT14                 (0x060c)
-#define AFE_IRQ_MCU_CNT15                 (0x0610)
-#define AFE_IRQ_MCU_CNT16                 (0x0614)
-#define AFE_IRQ_MCU_CNT17                 (0x0618)
-#define AFE_IRQ_MCU_CNT18                 (0x061c)
-#define AFE_IRQ_MCU_CNT19                 (0x0620)
-#define AFE_IRQ_MCU_CNT20                 (0x0624)
-#define AFE_IRQ_MCU_CNT21                 (0x0628)
-#define AFE_IRQ_MCU_CNT22                 (0x062c)
-#define AFE_IRQ_MCU_CNT23                 (0x0630)
-#define AFE_IRQ_MCU_CNT24                 (0x0634)
-#define AFE_IRQ_MCU_CNT25                 (0x0638)
-#define AFE_IRQ_MCU_CNT26                 (0x063c)
-#define AFE_IRQ9_MCU_CNT_MON              (0x0660)
-#define AFE_IRQ10_MCU_CNT_MON             (0x0664)
-#define AFE_IRQ13_MCU_CNT_MON             (0x0668)
-#define AFE_IRQ14_MCU_CNT_MON             (0x066c)
-#define AFE_IRQ15_MCU_CNT_MON             (0x0670)
-#define AFE_IRQ16_MCU_CNT_MON             (0x0674)
-#define AFE_IRQ17_MCU_CNT_MON             (0x0678)
-#define AFE_IRQ18_MCU_CNT_MON             (0x067c)
-#define AFE_IRQ19_MCU_CNT_MON             (0x0680)
-#define AFE_IRQ20_MCU_CNT_MON             (0x0684)
-#define AFE_IRQ21_MCU_CNT_MON             (0x0688)
-#define AFE_IRQ22_MCU_CNT_MON             (0x068c)
-#define AFE_IRQ23_MCU_CNT_MON             (0x0690)
-#define AFE_IRQ24_MCU_CNT_MON             (0x0694)
-#define AFE_IRQ25_MCU_CNT_MON             (0x0698)
-#define AFE_IRQ26_MCU_CNT_MON             (0x069c)
-#define AFE_IRQ31_MCU_CNT_MON             (0x06a0)
-#define AFE_GENERAL_REG0                  (0x0800)
-#define AFE_GENERAL_REG1                  (0x0804)
-#define AFE_GENERAL_REG2                  (0x0808)
-#define AFE_GENERAL_REG3                  (0x080c)
-#define AFE_GENERAL_REG4                  (0x0810)
-#define AFE_GENERAL_REG5                  (0x0814)
-#define AFE_GENERAL_REG6                  (0x0818)
-#define AFE_GENERAL_REG7                  (0x081c)
-#define AFE_GENERAL_REG8                  (0x0820)
-#define AFE_GENERAL_REG9                  (0x0824)
-#define AFE_GENERAL_REG10                 (0x0828)
-#define AFE_GENERAL_REG11                 (0x082c)
-#define AFE_GENERAL_REG12                 (0x0830)
-#define AFE_GENERAL_REG13                 (0x0834)
-#define AFE_GENERAL_REG14                 (0x0838)
-#define AFE_GENERAL_REG15                 (0x083c)
-#define AFE_CBIP_CFG0                     (0x0840)
-#define AFE_CBIP_MON0                     (0x0844)
-#define AFE_CBIP_SLV_MUX_MON0             (0x0848)
-#define AFE_CBIP_SLV_DECODER_MON0         (0x084c)
-#define AFE_ADDA6_MTKAIF_MON0             (0x0854)
-#define AFE_ADDA6_MTKAIF_MON1             (0x0858)
-#define AFE_AWB_CON0                      (0x085c)
-#define AFE_AWB_BASE_MSB                  (0x0860)
-#define AFE_AWB_BASE                      (0x0864)
-#define AFE_AWB_CUR_MSB                   (0x0868)
-#define AFE_AWB_CUR                       (0x086c)
-#define AFE_AWB_END_MSB                   (0x0870)
-#define AFE_AWB_END                       (0x0874)
-#define AFE_AWB2_CON0                     (0x0878)
-#define AFE_AWB2_BASE_MSB                 (0x087c)
-#define AFE_AWB2_BASE                     (0x0880)
-#define AFE_AWB2_CUR_MSB                  (0x0884)
-#define AFE_AWB2_CUR                      (0x0888)
-#define AFE_AWB2_END_MSB                  (0x088c)
-#define AFE_AWB2_END                      (0x0890)
-#define AFE_DAI_CON0                      (0x0894)
-#define AFE_DAI_BASE_MSB                  (0x0898)
-#define AFE_DAI_BASE                      (0x089c)
-#define AFE_DAI_CUR_MSB                   (0x08a0)
-#define AFE_DAI_CUR                       (0x08a4)
-#define AFE_DAI_END_MSB                   (0x08a8)
-#define AFE_DAI_END                       (0x08ac)
-#define AFE_DAI2_CON0                     (0x08b0)
-#define AFE_DAI2_BASE_MSB                 (0x08b4)
-#define AFE_DAI2_BASE                     (0x08b8)
-#define AFE_DAI2_CUR_MSB                  (0x08bc)
-#define AFE_DAI2_CUR                      (0x08c0)
-#define AFE_DAI2_END_MSB                  (0x08c4)
-#define AFE_DAI2_END                      (0x08c8)
-#define AFE_MEMIF_CON0                    (0x08cc)
-#define AFE_CONN0_1                       (0x0900)
-#define AFE_CONN1_1                       (0x0904)
-#define AFE_CONN2_1                       (0x0908)
-#define AFE_CONN3_1                       (0x090c)
-#define AFE_CONN4_1                       (0x0910)
-#define AFE_CONN5_1                       (0x0914)
-#define AFE_CONN6_1                       (0x0918)
-#define AFE_CONN7_1                       (0x091c)
-#define AFE_CONN8_1                       (0x0920)
-#define AFE_CONN9_1                       (0x0924)
-#define AFE_CONN10_1                      (0x0928)
-#define AFE_CONN11_1                      (0x092c)
-#define AFE_CONN12_1                      (0x0930)
-#define AFE_CONN13_1                      (0x0934)
-#define AFE_CONN14_1                      (0x0938)
-#define AFE_CONN15_1                      (0x093c)
-#define AFE_CONN16_1                      (0x0940)
-#define AFE_CONN17_1                      (0x0944)
-#define AFE_CONN18_1                      (0x0948)
-#define AFE_CONN19_1                      (0x094c)
-#define AFE_CONN20_1                      (0x0950)
-#define AFE_CONN21_1                      (0x0954)
-#define AFE_CONN22_1                      (0x0958)
-#define AFE_CONN23_1                      (0x095c)
-#define AFE_CONN24_1                      (0x0960)
-#define AFE_CONN25_1                      (0x0964)
-#define AFE_CONN26_1                      (0x0968)
-#define AFE_CONN27_1                      (0x096c)
-#define AFE_CONN28_1                      (0x0970)
-#define AFE_CONN29_1                      (0x0974)
-#define AFE_CONN30_1                      (0x0978)
-#define AFE_CONN31_1                      (0x097c)
-#define AFE_CONN32_1                      (0x0980)
-#define AFE_CONN33_1                      (0x0984)
-#define AFE_CONN34_1                      (0x0988)
-#define AFE_CONN_RS_1                     (0x098c)
-#define AFE_CONN_DI_1                     (0x0990)
-#define AFE_CONN_24BIT_1                  (0x0994)
-#define AFE_CONN_REG                      (0x0998)
-#define AFE_CONN35_0                      (0x09a0)
-#define AFE_CONN36_0                      (0x09a4)
-#define AFE_CONN37_0                      (0x09a8)
-#define AFE_CONN38_0                      (0x09ac)
-#define AFE_CONN35_1                      (0x09b0)
-#define AFE_CONN36_1                      (0x09b4)
-#define AFE_CONN37_1                      (0x09b8)
-#define AFE_CONN38_1                      (0x09bc)
-#define AFE_CONN39_0                      (0x09c0)
-#define AFE_CONN40_0                      (0x09c4)
-#define AFE_CONN41_0                      (0x09c8)
-#define AFE_CONN42_0                      (0x09cc)
-#define AFE_CONN39_1                      (0x09e0)
-#define AFE_CONN40_1                      (0x09e4)
-#define AFE_CONN41_1                      (0x09e8)
-#define AFE_CONN42_1                      (0x09ec)
-#define AFE_CONN60_0                      (0x0a64)
-#define AFE_CONN61_0                      (0x0a68)
-#define AFE_CONN62_0                      (0x0a6c)
-#define AFE_CONN63_0                      (0x0a70)
-#define AFE_CONN64_0                      (0x0a74)
-#define AFE_CONN65_0                      (0x0a78)
-#define AFE_CONN66_0                      (0x0a7c)
-#define AFE_ADDA6_TOP_CON0                (0x0a80)
-#define AFE_ADDA6_UL_SRC_CON0             (0x0a84)
-#define AFE_ADDA6_UL_SRC_CON1             (0x0a88)
-#define AFE_ADDA6_SRC_DEBUG               (0x0a8c)
-#define AFE_ADDA6_SRC_DEBUG_MON0          (0x0a90)
-#define AFE_ADDA6_ULCF_CFG_02_01          (0x0aa0)
-#define AFE_ADDA6_ULCF_CFG_04_03          (0x0aa4)
-#define AFE_ADDA6_ULCF_CFG_06_05          (0x0aa8)
-#define AFE_ADDA6_ULCF_CFG_08_07          (0x0aac)
-#define AFE_ADDA6_ULCF_CFG_10_09          (0x0ab0)
-#define AFE_ADDA6_ULCF_CFG_12_11          (0x0ab4)
-#define AFE_ADDA6_ULCF_CFG_14_13          (0x0ab8)
-#define AFE_ADDA6_ULCF_CFG_16_15          (0x0abc)
-#define AFE_ADDA6_ULCF_CFG_18_17          (0x0ac0)
-#define AFE_ADDA6_ULCF_CFG_20_19          (0x0ac4)
-#define AFE_ADDA6_ULCF_CFG_22_21          (0x0ac8)
-#define AFE_ADDA6_ULCF_CFG_24_23          (0x0acc)
-#define AFE_ADDA6_ULCF_CFG_26_25          (0x0ad0)
-#define AFE_ADDA6_ULCF_CFG_28_27          (0x0ad4)
-#define AFE_ADDA6_ULCF_CFG_30_29          (0x0ad8)
-#define AFE_ADD6A_UL_SRC_MON0             (0x0ae4)
-#define AFE_ADDA6_UL_SRC_MON1             (0x0ae8)
-#define AFE_CONN43_0                      (0x0af8)
-#define AFE_CONN43_1                      (0x0afc)
-#define AFE_MOD_DAI_CON0                  (0x0b00)
-#define AFE_MOD_DAI_BASE_MSB              (0x0b04)
-#define AFE_MOD_DAI_BASE                  (0x0b08)
-#define AFE_MOD_DAI_CUR_MSB               (0x0b0c)
-#define AFE_MOD_DAI_CUR                   (0x0b10)
-#define AFE_MOD_DAI_END_MSB               (0x0b14)
-#define AFE_MOD_DAI_END                   (0x0b18)
-#define AFE_AWB_RCH_MON                   (0x0b70)
-#define AFE_AWB_LCH_MON                   (0x0b74)
-#define AFE_VUL_RCH_MON                   (0x0b78)
-#define AFE_VUL_LCH_MON                   (0x0b7c)
-#define AFE_VUL12_RCH_MON                 (0x0b80)
-#define AFE_VUL12_LCH_MON                 (0x0b84)
-#define AFE_VUL2_RCH_MON                  (0x0b88)
-#define AFE_VUL2_LCH_MON                  (0x0b8c)
-#define AFE_DAI_DATA_MON                  (0x0b90)
-#define AFE_MOD_DAI_DATA_MON              (0x0b94)
-#define AFE_DAI2_DATA_MON                 (0x0b98)
-#define AFE_AWB2_RCH_MON                  (0x0b9c)
-#define AFE_AWB2_LCH_MON                  (0x0ba0)
-#define AFE_VUL3_RCH_MON                  (0x0ba4)
-#define AFE_VUL3_LCH_MON                  (0x0ba8)
-#define AFE_VUL4_RCH_MON                  (0x0bac)
-#define AFE_VUL4_LCH_MON                  (0x0bb0)
-#define AFE_VUL5_RCH_MON                  (0x0bb4)
-#define AFE_VUL5_LCH_MON                  (0x0bb8)
-#define AFE_VUL6_RCH_MON                  (0x0bbc)
-#define AFE_VUL6_LCH_MON                  (0x0bc0)
-#define AFE_DL1_RCH_MON                   (0x0bc4)
-#define AFE_DL1_LCH_MON                   (0x0bc8)
-#define AFE_DL2_RCH_MON                   (0x0bcc)
-#define AFE_DL2_LCH_MON                   (0x0bd0)
-#define AFE_DL12_RCH1_MON                 (0x0bd4)
-#define AFE_DL12_LCH1_MON                 (0x0bd8)
-#define AFE_DL12_RCH2_MON                 (0x0bdc)
-#define AFE_DL12_LCH2_MON                 (0x0be0)
-#define AFE_DL3_RCH_MON                   (0x0be4)
-#define AFE_DL3_LCH_MON                   (0x0be8)
-#define AFE_DL4_RCH_MON                   (0x0bec)
-#define AFE_DL4_LCH_MON                   (0x0bf0)
-#define AFE_DL5_RCH_MON                   (0x0bf4)
-#define AFE_DL5_LCH_MON                   (0x0bf8)
-#define AFE_DL6_RCH_MON                   (0x0bfc)
-#define AFE_DL6_LCH_MON                   (0x0c00)
-#define AFE_DL7_RCH_MON                   (0x0c04)
-#define AFE_DL7_LCH_MON                   (0x0c08)
-#define AFE_DL8_RCH_MON                   (0x0c0c)
-#define AFE_DL8_LCH_MON                   (0x0c10)
-#define AFE_VUL5_CON0                     (0x0c14)
-#define AFE_VUL5_BASE_MSB                 (0x0c18)
-#define AFE_VUL5_BASE                     (0x0c1c)
-#define AFE_VUL5_CUR_MSB                  (0x0c20)
-#define AFE_VUL5_CUR                      (0x0c24)
-#define AFE_VUL5_END_MSB                  (0x0c28)
-#define AFE_VUL5_END                      (0x0c2c)
-#define AFE_VUL6_CON0                     (0x0c30)
-#define AFE_VUL6_BASE_MSB                 (0x0c34)
-#define AFE_VUL6_BASE                     (0x0c38)
-#define AFE_VUL6_CUR_MSB                  (0x0c3c)
-#define AFE_VUL6_CUR                      (0x0c40)
-#define AFE_VUL6_END_MSB                  (0x0c44)
-#define AFE_VUL6_END                      (0x0c48)
-#define AFE_ADDA_DL_SDM_DCCOMP_CON        (0x0c50)
-#define AFE_ADDA_DL_SDM_TEST              (0x0c54)
-#define AFE_ADDA_DL_DC_COMP_CFG0          (0x0c58)
-#define AFE_ADDA_DL_DC_COMP_CFG1          (0x0c5c)
-#define AFE_ADDA_DL_SDM_FIFO_MON          (0x0c60)
-#define AFE_ADDA_DL_SRC_LCH_MON           (0x0c64)
-#define AFE_ADDA_DL_SRC_RCH_MON           (0x0c68)
-#define AFE_ADDA_DL_SDM_OUT_MON           (0x0c6c)
-#define AFE_ADDA_DL_SDM_DITHER_CON        (0x0c70)
-#define AFE_ADDA_DL_SDM_AUTO_RESET_CON    (0x0c74)
-#define AFE_CONNSYS_I2S_CON               (0x0c78)
-#define AFE_CONNSYS_I2S_MON               (0x0c7c)
-#define AFE_ASRC_2CH_CON0                 (0x0c80)
-#define AFE_ASRC_2CH_CON1                 (0x0c84)
-#define AFE_ASRC_2CH_CON2                 (0x0c88)
-#define AFE_ASRC_2CH_CON3                 (0x0c8c)
-#define AFE_ASRC_2CH_CON4                 (0x0c90)
-#define AFE_ASRC_2CH_CON5                 (0x0c94)
-#define AFE_ASRC_2CH_CON6                 (0x0c98)
-#define AFE_ASRC_2CH_CON7                 (0x0c9c)
-#define AFE_ASRC_2CH_CON8                 (0x0ca0)
-#define AFE_ASRC_2CH_CON9                 (0x0ca4)
-#define AFE_ASRC_2CH_CON10                (0x0ca8)
-#define AFE_ASRC_2CH_CON12                (0x0cb0)
-#define AFE_ASRC_2CH_CON13                (0x0cb4)
-#define AFE_ADDA6_IIR_COEF_02_01          (0x0ce0)
-#define AFE_ADDA6_IIR_COEF_04_03          (0x0ce4)
-#define AFE_ADDA6_IIR_COEF_06_05          (0x0ce8)
-#define AFE_ADDA6_IIR_COEF_08_07          (0x0cec)
-#define AFE_ADDA6_IIR_COEF_10_09          (0x0cf0)
-#define AFE_CONN67_0                      (0x0cf4)
-#define AFE_CONN68_0                      (0x0cf8)
-#define AFE_CONN69_0                      (0x0cfc)
-#define AFE_ADDA_PREDIS_CON2              (0x0d40)
-#define AFE_ADDA_PREDIS_CON3              (0x0d44)
-#define AFE_CONN44_0                      (0x0d70)
-#define AFE_CONN45_0                      (0x0d74)
-#define AFE_CONN46_0                      (0x0d78)
-#define AFE_CONN47_0                      (0x0d7c)
-#define AFE_CONN44_1                      (0x0d80)
-#define AFE_CONN45_1                      (0x0d84)
-#define AFE_CONN46_1                      (0x0d88)
-#define AFE_CONN47_1                      (0x0d8c)
-#define AFE_DL1_MON0                      (0x0d90)
-#define AFE_DL2_MON0                      (0x0d94)
-#define AFE_DL3_MON0                      (0x0d98)
-#define AFE_DL4_MON0                      (0x0d9c)
-#define AFE_DL5_MON0                      (0x0da0)
-#define AFE_DL6_MON0                      (0x0da4)
-#define AFE_DL7_MON0                      (0x0da8)
-#define AFE_DL8_MON0                      (0x0dac)
-#define AFE_DL12_MON0                     (0x0db0)
-#define AFE_HD_ENGEN_ENABLE               (0x0dd0)
-#define AFE_ADDA_DL_NLE_FIFO_MON          (0x0dfc)
-#define AFE_ADDA_MTKAIF_CFG0              (0x0e00)
-#define AFE_CONN67_1                      (0x0e04)
-#define AFE_CONN68_1                      (0x0e08)
-#define AFE_CONN69_1                      (0x0e0c)
-#define AFE_ADDA_MTKAIF_SYNCWORD_CFG      (0x0e14)
-#define AFE_ADDA_MTKAIF_RX_CFG0           (0x0e20)
-#define AFE_ADDA_MTKAIF_RX_CFG1           (0x0e24)
-#define AFE_ADDA_MTKAIF_RX_CFG2           (0x0e28)
-#define AFE_ADDA_MTKAIF_MON0              (0x0e34)
-#define AFE_ADDA_MTKAIF_MON1              (0x0e38)
-#define AFE_AUD_PAD_TOP                   (0x0e40)
-#define AFE_DL_NLE_R_CFG0                 (0x0e44)
-#define AFE_DL_NLE_R_CFG1                 (0x0e48)
-#define AFE_DL_NLE_L_CFG0                 (0x0e4c)
-#define AFE_DL_NLE_L_CFG1                 (0x0e50)
-#define AFE_DL_NLE_R_MON0                 (0x0e54)
-#define AFE_DL_NLE_R_MON1                 (0x0e58)
-#define AFE_DL_NLE_R_MON2                 (0x0e5c)
-#define AFE_DL_NLE_L_MON0                 (0x0e60)
-#define AFE_DL_NLE_L_MON1                 (0x0e64)
-#define AFE_DL_NLE_L_MON2                 (0x0e68)
-#define AFE_DL_NLE_GAIN_CFG0              (0x0e6c)
-#define AFE_ADDA6_MTKAIF_CFG0             (0x0e70)
-#define AFE_ADDA6_MTKAIF_RX_CFG0          (0x0e74)
-#define AFE_ADDA6_MTKAIF_RX_CFG1          (0x0e78)
-#define AFE_ADDA6_MTKAIF_RX_CFG2          (0x0e7c)
-#define AFE_GENERAL1_ASRC_2CH_CON0        (0x0e80)
-#define AFE_GENERAL1_ASRC_2CH_CON1        (0x0e84)
-#define AFE_GENERAL1_ASRC_2CH_CON2        (0x0e88)
-#define AFE_GENERAL1_ASRC_2CH_CON3        (0x0e8c)
-#define AFE_GENERAL1_ASRC_2CH_CON4        (0x0e90)
-#define AFE_GENERAL1_ASRC_2CH_CON5        (0x0e94)
-#define AFE_GENERAL1_ASRC_2CH_CON6        (0x0e98)
-#define AFE_GENERAL1_ASRC_2CH_CON7        (0x0e9c)
-#define AFE_GENERAL1_ASRC_2CH_CON8        (0x0ea0)
-#define AFE_GENERAL1_ASRC_2CH_CON9        (0x0ea4)
-#define AFE_GENERAL1_ASRC_2CH_CON10       (0x0ea8)
-#define AFE_GENERAL1_ASRC_2CH_CON12       (0x0eb0)
-#define AFE_GENERAL1_ASRC_2CH_CON13       (0x0eb4)
-#define GENERAL_ASRC_MODE                 (0x0eb8)
-#define GENERAL_ASRC_EN_ON                (0x0ebc)
-#define AFE_CONN48_0                      (0x0ec0)
-#define AFE_CONN49_0                      (0x0ec4)
-#define AFE_CONN50_0                      (0x0ec8)
-#define AFE_CONN51_0                      (0x0ecc)
-#define AFE_CONN52_0                      (0x0ed0)
-#define AFE_CONN53_0                      (0x0ed4)
-#define AFE_CONN54_0                      (0x0ed8)
-#define AFE_CONN55_0                      (0x0edc)
-#define AFE_CONN48_1                      (0x0ee0)
-#define AFE_CONN49_1                      (0x0ee4)
-#define AFE_CONN50_1                      (0x0ee8)
-#define AFE_CONN51_1                      (0x0eec)
-#define AFE_CONN52_1                      (0x0ef0)
-#define AFE_CONN53_1                      (0x0ef4)
-#define AFE_CONN54_1                      (0x0ef8)
-#define AFE_CONN55_1                      (0x0efc)
-#define AFE_GENERAL2_ASRC_2CH_CON0        (0x0f00)
-#define AFE_GENERAL2_ASRC_2CH_CON1        (0x0f04)
-#define AFE_GENERAL2_ASRC_2CH_CON2        (0x0f08)
-#define AFE_GENERAL2_ASRC_2CH_CON3        (0x0f0c)
-#define AFE_GENERAL2_ASRC_2CH_CON4        (0x0f10)
-#define AFE_GENERAL2_ASRC_2CH_CON5        (0x0f14)
-#define AFE_GENERAL2_ASRC_2CH_CON6        (0x0f18)
-#define AFE_GENERAL2_ASRC_2CH_CON7        (0x0f1c)
-#define AFE_GENERAL2_ASRC_2CH_CON8        (0x0f20)
-#define AFE_GENERAL2_ASRC_2CH_CON9        (0x0f24)
-#define AFE_GENERAL2_ASRC_2CH_CON10       (0x0f28)
-#define AFE_GENERAL2_ASRC_2CH_CON12       (0x0f30)
-#define AFE_GENERAL2_ASRC_2CH_CON13       (0x0f34)
-#define AFE_DL5_CON0                      (0x0f4c)
-#define AFE_DL5_BASE_MSB                  (0x0f50)
-#define AFE_DL5_BASE                      (0x0f54)
-#define AFE_DL5_CUR_MSB                   (0x0f58)
-#define AFE_DL5_CUR                       (0x0f5c)
-#define AFE_DL5_END_MSB                   (0x0f60)
-#define AFE_DL5_END                       (0x0f64)
-#define AFE_DL6_CON0                      (0x0f68)
-#define AFE_DL6_BASE_MSB                  (0x0f6c)
-#define AFE_DL6_BASE                      (0x0f70)
-#define AFE_DL6_CUR_MSB                   (0x0f74)
-#define AFE_DL6_CUR                       (0x0f78)
-#define AFE_DL6_END_MSB                   (0x0f7c)
-#define AFE_DL6_END                       (0x0f80)
-#define AFE_DL7_CON0                      (0x0f84)
-#define AFE_DL7_BASE_MSB                  (0x0f88)
-#define AFE_DL7_BASE                      (0x0f8c)
-#define AFE_DL7_CUR_MSB                   (0x0f90)
-#define AFE_DL7_CUR                       (0x0f94)
-#define AFE_DL7_END_MSB                   (0x0f98)
-#define AFE_DL7_END                       (0x0f9c)
-#define AFE_DL8_CON0                      (0x0fa0)
-#define AFE_DL8_BASE_MSB                  (0x0fa4)
-#define AFE_DL8_BASE                      (0x0fa8)
-#define AFE_DL8_CUR_MSB                   (0x0fac)
-#define AFE_DL8_CUR                       (0x0fb0)
-#define AFE_DL8_END_MSB                   (0x0fb4)
-#define AFE_DL8_END                       (0x0fb8)
-#define AFE_VUL_MON0                      (0x0fc8)
-#define AFE_VUL2_MON0                     (0x0fcc)
-#define AFE_VUL3_MON0                     (0x0fd0)
-#define AFE_VUL4_MON0                     (0x0fd4)
-#define AFE_VUL5_MON0                     (0x0fd8)
-#define AFE_VUL6_MON0                     (0x0fdc)
-#define AFE_VUL12_MON0                    (0x0fe0)
-#define AFE_AWB_MON0                      (0x0fe4)
-#define AFE_AWB2_MON0                     (0x0fe8)
-#define AFE_MOD_DAI_MON0                  (0x0fec)
-#define AFE_DAI_MON0                      (0x0ff0)
-#define AFE_DAI2_MON0                     (0x0ff4)
-#define AFE_CONN_RS_2                     (0x0ff8)
-#define AFE_CONN_DI_2                     (0x0ffc)
-#define AFE_CONN_24BIT_2                  (0x1000)
-#define AFE_CONN60_1                      (0x11f0)
-#define AFE_CONN61_1                      (0x11f4)
-#define AFE_CONN62_1                      (0x11f8)
-#define AFE_CONN63_1                      (0x11fc)
-#define AFE_CONN64_1                      (0x1220)
-#define AFE_CONN65_1                      (0x1224)
-#define AFE_CONN66_1                      (0x1228)
-#define FPGA_CFG4                         (0x1230)
-#define FPGA_CFG5                         (0x1234)
-#define FPGA_CFG6                         (0x1238)
-#define FPGA_CFG7                         (0x123c)
-#define FPGA_CFG8                         (0x1240)
-#define FPGA_CFG9                         (0x1244)
-#define FPGA_CFG10                        (0x1248)
-#define FPGA_CFG11                        (0x124c)
-#define FPGA_CFG12                        (0x1250)
-#define FPGA_CFG13                        (0x1254)
-#define ETDM_IN1_CON0                     (0x1430)
-#define ETDM_IN1_CON1                     (0x1434)
-#define ETDM_IN1_CON2                     (0x1438)
-#define ETDM_IN1_CON3                     (0x143c)
-#define ETDM_IN1_CON4                     (0x1440)
-#define ETDM_IN1_CON5                     (0x1444)
-#define ETDM_IN1_CON6                     (0x1448)
-#define ETDM_IN1_CON7                     (0x144c)
-#define ETDM_IN1_CON8                     (0x1450)
-#define ETDM_OUT1_CON0                    (0x1454)
-#define ETDM_OUT1_CON1                    (0x1458)
-#define ETDM_OUT1_CON2                    (0x145c)
-#define ETDM_OUT1_CON3                    (0x1460)
-#define ETDM_OUT1_CON4                    (0x1464)
-#define ETDM_OUT1_CON5                    (0x1468)
-#define ETDM_OUT1_CON6                    (0x146c)
-#define ETDM_OUT1_CON7                    (0x1470)
-#define ETDM_OUT1_CON8                    (0x1474)
-#define ETDM_IN1_MON                      (0x1478)
-#define ETDM_OUT1_MON                     (0x147c)
-#define ETDM_0_3_COWORK_CON0              (0x18b0)
-#define ETDM_0_3_COWORK_CON1              (0x18b4)
-#define ETDM_0_3_COWORK_CON3              (0x18bc)
-
-/* AFE_DAC_CON0 */
-#define VUL12_ON_SFT                                   31
-#define VUL12_ON_MASK                                  0x1
-#define VUL12_ON_MASK_SFT                              (0x1 << 31)
-#define MOD_DAI_ON_SFT                                 30
-#define MOD_DAI_ON_MASK                                0x1
-#define MOD_DAI_ON_MASK_SFT                            (0x1 << 30)
-#define DAI_ON_SFT                                     29
-#define DAI_ON_MASK                                    0x1
-#define DAI_ON_MASK_SFT                                (0x1 << 29)
-#define DAI2_ON_SFT                                    28
-#define DAI2_ON_MASK                                   0x1
-#define DAI2_ON_MASK_SFT                               (0x1 << 28)
-#define VUL6_ON_SFT                                    23
-#define VUL6_ON_MASK                                   0x1
-#define VUL6_ON_MASK_SFT                               (0x1 << 23)
-#define VUL5_ON_SFT                                    22
-#define VUL5_ON_MASK                                   0x1
-#define VUL5_ON_MASK_SFT                               (0x1 << 22)
-#define VUL4_ON_SFT                                    21
-#define VUL4_ON_MASK                                   0x1
-#define VUL4_ON_MASK_SFT                               (0x1 << 21)
-#define VUL3_ON_SFT                                    20
-#define VUL3_ON_MASK                                   0x1
-#define VUL3_ON_MASK_SFT                               (0x1 << 20)
-#define VUL2_ON_SFT                                    19
-#define VUL2_ON_MASK                                   0x1
-#define VUL2_ON_MASK_SFT                               (0x1 << 19)
-#define VUL_ON_SFT                                     18
-#define VUL_ON_MASK                                    0x1
-#define VUL_ON_MASK_SFT                                (0x1 << 18)
-#define AWB2_ON_SFT                                    17
-#define AWB2_ON_MASK                                   0x1
-#define AWB2_ON_MASK_SFT                               (0x1 << 17)
-#define AWB_ON_SFT                                     16
-#define AWB_ON_MASK                                    0x1
-#define AWB_ON_MASK_SFT                                (0x1 << 16)
-#define DL12_ON_SFT                                    15
-#define DL12_ON_MASK                                   0x1
-#define DL12_ON_MASK_SFT                               (0x1 << 15)
-#define DL8_ON_SFT                                     11
-#define DL8_ON_MASK                                    0x1
-#define DL8_ON_MASK_SFT                                (0x1 << 11)
-#define DL7_ON_SFT                                     10
-#define DL7_ON_MASK                                    0x1
-#define DL7_ON_MASK_SFT                                (0x1 << 10)
-#define DL6_ON_SFT                                     9
-#define DL6_ON_MASK                                    0x1
-#define DL6_ON_MASK_SFT                                (0x1 << 9)
-#define DL5_ON_SFT                                     8
-#define DL5_ON_MASK                                    0x1
-#define DL5_ON_MASK_SFT                                (0x1 << 8)
-#define DL4_ON_SFT                                     7
-#define DL4_ON_MASK                                    0x1
-#define DL4_ON_MASK_SFT                                (0x1 << 7)
-#define DL3_ON_SFT                                     6
-#define DL3_ON_MASK                                    0x1
-#define DL3_ON_MASK_SFT                                (0x1 << 6)
-#define DL2_ON_SFT                                     5
-#define DL2_ON_MASK                                    0x1
-#define DL2_ON_MASK_SFT                                (0x1 << 5)
-#define DL1_ON_SFT                                     4
-#define DL1_ON_MASK                                    0x1
-#define DL1_ON_MASK_SFT                                (0x1 << 4)
-#define AFE_ON_SFT                                     0
-#define AFE_ON_MASK                                    0x1
-#define AFE_ON_MASK_SFT                                (0x1 << 0)
-
-// AFE_CM1_CON
-#define CHANNEL_MERGE0_DEBUG_MODE_SFT                   (31)
-#define CHANNEL_MERGE0_DEBUG_MODE_MASK                  (0x1)
-#define CHANNEL_MERGE0_DEBUG_MODE_MASK_SFT              (0x1 << 31)
-#define VUL3_BYPASS_CM_SFT                              (30)
-#define VUL3_BYPASS_CM_MASK                             (0x1)
-#define VUL3_BYPASS_CM_MASK_SFT                         (0x1 << 30)
-#define CM1_DEBUG_MODE_SEL_SFT                          (29)
-#define CM1_DEBUG_MODE_SEL_MASK                         (0x1)
-#define CM1_DEBUG_MODE_SEL_MASK_SFT                     (0x1 << 29)
-#define CHANNEL_MERGE0_UPDATE_CNT_SFT                   (16)
-#define CHANNEL_MERGE0_UPDATE_CNT_MASK                  (0x1fff)
-#define CHANNEL_MERGE0_UPDATE_CNT_MASK_SFT              (0x1fff << 16)
-#define CM1_FS_SELECT_SFT                               (8)
-#define CM1_FS_SELECT_MASK                              (0x1f)
-#define CM1_FS_SELECT_MASK_SFT                          (0x1f << 8)
-#define CHANNEL_MERGE0_CHNUM_SFT                        (3)
-#define CHANNEL_MERGE0_CHNUM_MASK                       (0x1f)
-#define CHANNEL_MERGE0_CHNUM_MASK_SFT                   (0x1f << 3)
-#define CHANNEL_MERGE0_BYTE_SWAP_SFT                    (1)
-#define CHANNEL_MERGE0_BYTE_SWAP_MASK                   (0x1)
-#define CHANNEL_MERGE0_BYTE_SWAP_MASK_SFT               (0x1 << 1)
-#define CHANNEL_MERGE0_EN_SFT                           (0)
-#define CHANNEL_MERGE0_EN_MASK                          (0x1)
-#define CHANNEL_MERGE0_EN_MASK_SFT                      (0x1 << 0)
-
-// AFE_CM1_MON
-#define AFE_CM0_OUTPUT_CNT_POS				(16)
-#define AFE_CM0_OUTPUT_CNT_LEN				(13)
-#define AFE_CM0_CUR_CHSET_POS				(5)
-#define AFE_CM0_CUR_CHSET_LEN				(4)
-#define AFE_CM0_ODD_FLAG_POS				(4)
-#define AFE_CM0_ODD_FLAG_LEN				(1)
-#define AFE_CM0_BYTE_SWAP_MON_POS			(1)
-#define AFE_CM0_BYTE_SWAP_MON_LEN			(1)
-#define AFE_CM0_ON_MON_POS				(0)
-#define AFE_CM0_ON_MON_LEN				(1)
-
-/* AFE_DL1_CON0 */
-#define DL1_MODE_SFT                                   24
-#define DL1_MODE_MASK                                  0xf
-#define DL1_MODE_MASK_SFT                              (0xf << 24)
-#define DL1_MINLEN_SFT                                 20
-#define DL1_MINLEN_MASK                                0xf
-#define DL1_MINLEN_MASK_SFT                            (0xf << 20)
-#define DL1_MAXLEN_SFT                                 16
-#define DL1_MAXLEN_MASK                                0xf
-#define DL1_MAXLEN_MASK_SFT                            (0xf << 16)
-#define DL1_SW_CLEAR_BUF_EMPTY_SFT                     15
-#define DL1_SW_CLEAR_BUF_EMPTY_MASK                    0x1
-#define DL1_SW_CLEAR_BUF_EMPTY_MASK_SFT                (0x1 << 15)
-#define DL1_PBUF_SIZE_SFT                              12
-#define DL1_PBUF_SIZE_MASK                             0x3
-#define DL1_PBUF_SIZE_MASK_SFT                         (0x3 << 12)
-#define DL1_MONO_SFT                                   8
-#define DL1_MONO_MASK                                  0x1
-#define DL1_MONO_MASK_SFT                              (0x1 << 8)
-#define DL1_NORMAL_MODE_SFT                            5
-#define DL1_NORMAL_MODE_MASK                           0x1
-#define DL1_NORMAL_MODE_MASK_SFT                       (0x1 << 5)
-#define DL1_HALIGN_SFT                                 4
-#define DL1_HALIGN_MASK                                0x1
-#define DL1_HALIGN_MASK_SFT                            (0x1 << 4)
-#define DL1_HD_MODE_SFT                                0
-#define DL1_HD_MODE_MASK                               0x3
-#define DL1_HD_MODE_MASK_SFT                           (0x3 << 0)
-
-/* AFE_DL2_CON0 */
-#define DL2_MODE_SFT                                   24
-#define DL2_MODE_MASK                                  0xf
-#define DL2_MODE_MASK_SFT                              (0xf << 24)
-#define DL2_MINLEN_SFT                                 20
-#define DL2_MINLEN_MASK                                0xf
-#define DL2_MINLEN_MASK_SFT                            (0xf << 20)
-#define DL2_MAXLEN_SFT                                 16
-#define DL2_MAXLEN_MASK                                0xf
-#define DL2_MAXLEN_MASK_SFT                            (0xf << 16)
-#define DL2_SW_CLEAR_BUF_EMPTY_SFT                     15
-#define DL2_SW_CLEAR_BUF_EMPTY_MASK                    0x1
-#define DL2_SW_CLEAR_BUF_EMPTY_MASK_SFT                (0x1 << 15)
-#define DL2_PBUF_SIZE_SFT                              12
-#define DL2_PBUF_SIZE_MASK                             0x3
-#define DL2_PBUF_SIZE_MASK_SFT                         (0x3 << 12)
-#define DL2_MONO_SFT                                   8
-#define DL2_MONO_MASK                                  0x1
-#define DL2_MONO_MASK_SFT                              (0x1 << 8)
-#define DL2_NORMAL_MODE_SFT                            5
-#define DL2_NORMAL_MODE_MASK                           0x1
-#define DL2_NORMAL_MODE_MASK_SFT                       (0x1 << 5)
-#define DL2_HALIGN_SFT                                 4
-#define DL2_HALIGN_MASK                                0x1
-#define DL2_HALIGN_MASK_SFT                            (0x1 << 4)
-#define DL2_HD_MODE_SFT                                0
-#define DL2_HD_MODE_MASK                               0x3
-#define DL2_HD_MODE_MASK_SFT                           (0x3 << 0)
-
-/* AFE_DL3_CON0 */
-#define DL3_MODE_SFT                                   24
-#define DL3_MODE_MASK                                  0xf
-#define DL3_MODE_MASK_SFT                              (0xf << 24)
-#define DL3_MINLEN_SFT                                 20
-#define DL3_MINLEN_MASK                                0xf
-#define DL3_MINLEN_MASK_SFT                            (0xf << 20)
-#define DL3_MAXLEN_SFT                                 16
-#define DL3_MAXLEN_MASK                                0xf
-#define DL3_MAXLEN_MASK_SFT                            (0xf << 16)
-#define DL3_SW_CLEAR_BUF_EMPTY_SFT                     15
-#define DL3_SW_CLEAR_BUF_EMPTY_MASK                    0x1
-#define DL3_SW_CLEAR_BUF_EMPTY_MASK_SFT                (0x1 << 15)
-#define DL3_PBUF_SIZE_SFT                              12
-#define DL3_PBUF_SIZE_MASK                             0x3
-#define DL3_PBUF_SIZE_MASK_SFT                         (0x3 << 12)
-#define DL3_MONO_SFT                                   8
-#define DL3_MONO_MASK                                  0x1
-#define DL3_MONO_MASK_SFT                              (0x1 << 8)
-#define DL3_NORMAL_MODE_SFT                            5
-#define DL3_NORMAL_MODE_MASK                           0x1
-#define DL3_NORMAL_MODE_MASK_SFT                       (0x1 << 5)
-#define DL3_HALIGN_SFT                                 4
-#define DL3_HALIGN_MASK                                0x1
-#define DL3_HALIGN_MASK_SFT                            (0x1 << 4)
-#define DL3_HD_MODE_SFT                                0
-#define DL3_HD_MODE_MASK                               0x3
-#define DL3_HD_MODE_MASK_SFT                           (0x3 << 0)
-
-/* AFE_DL4_CON0 */
-#define DL4_MODE_SFT                                   24
-#define DL4_MODE_MASK                                  0xf
-#define DL4_MODE_MASK_SFT                              (0xf << 24)
-#define DL4_MINLEN_SFT                                 20
-#define DL4_MINLEN_MASK                                0xf
-#define DL4_MINLEN_MASK_SFT                            (0xf << 20)
-#define DL4_MAXLEN_SFT                                 16
-#define DL4_MAXLEN_MASK                                0xf
-#define DL4_MAXLEN_MASK_SFT                            (0xf << 16)
-#define DL4_SW_CLEAR_BUF_EMPTY_SFT                     15
-#define DL4_SW_CLEAR_BUF_EMPTY_MASK                    0x1
-#define DL4_SW_CLEAR_BUF_EMPTY_MASK_SFT                (0x1 << 15)
-#define DL4_PBUF_SIZE_SFT                              12
-#define DL4_PBUF_SIZE_MASK                             0x3
-#define DL4_PBUF_SIZE_MASK_SFT                         (0x3 << 12)
-#define DL4_MONO_SFT                                   8
-#define DL4_MONO_MASK                                  0x1
-#define DL4_MONO_MASK_SFT                              (0x1 << 8)
-#define DL4_NORMAL_MODE_SFT                            5
-#define DL4_NORMAL_MODE_MASK                           0x1
-#define DL4_NORMAL_MODE_MASK_SFT                       (0x1 << 5)
-#define DL4_HALIGN_SFT                                 4
-#define DL4_HALIGN_MASK                                0x1
-#define DL4_HALIGN_MASK_SFT                            (0x1 << 4)
-#define DL4_HD_MODE_SFT                                0
-#define DL4_HD_MODE_MASK                               0x3
-#define DL4_HD_MODE_MASK_SFT                           (0x3 << 0)
-
-/* AFE_DL5_CON0 */
-#define DL5_MODE_SFT                                   24
-#define DL5_MODE_MASK                                  0xf
-#define DL5_MODE_MASK_SFT                              (0xf << 24)
-#define DL5_MINLEN_SFT                                 20
-#define DL5_MINLEN_MASK                                0xf
-#define DL5_MINLEN_MASK_SFT                            (0xf << 20)
-#define DL5_MAXLEN_SFT                                 16
-#define DL5_MAXLEN_MASK                                0xf
-#define DL5_MAXLEN_MASK_SFT                            (0xf << 16)
-#define DL5_SW_CLEAR_BUF_EMPTY_SFT                     15
-#define DL5_SW_CLEAR_BUF_EMPTY_MASK                    0x1
-#define DL5_SW_CLEAR_BUF_EMPTY_MASK_SFT                (0x1 << 15)
-#define DL5_PBUF_SIZE_SFT                              12
-#define DL5_PBUF_SIZE_MASK                             0x3
-#define DL5_PBUF_SIZE_MASK_SFT                         (0x3 << 12)
-#define DL5_MONO_SFT                                   8
-#define DL5_MONO_MASK                                  0x1
-#define DL5_MONO_MASK_SFT                              (0x1 << 8)
-#define DL5_NORMAL_MODE_SFT                            5
-#define DL5_NORMAL_MODE_MASK                           0x1
-#define DL5_NORMAL_MODE_MASK_SFT                       (0x1 << 5)
-#define DL5_HALIGN_SFT                                 4
-#define DL5_HALIGN_MASK                                0x1
-#define DL5_HALIGN_MASK_SFT                            (0x1 << 4)
-#define DL5_HD_MODE_SFT                                0
-#define DL5_HD_MODE_MASK                               0x3
-#define DL5_HD_MODE_MASK_SFT                           (0x3 << 0)
-
-/* AFE_DL6_CON0 */
-#define DL6_MODE_SFT                                   24
-#define DL6_MODE_MASK                                  0xf
-#define DL6_MODE_MASK_SFT                              (0xf << 24)
-#define DL6_MINLEN_SFT                                 20
-#define DL6_MINLEN_MASK                                0xf
-#define DL6_MINLEN_MASK_SFT                            (0xf << 20)
-#define DL6_MAXLEN_SFT                                 16
-#define DL6_MAXLEN_MASK                                0xf
-#define DL6_MAXLEN_MASK_SFT                            (0xf << 16)
-#define DL6_SW_CLEAR_BUF_EMPTY_SFT                     15
-#define DL6_SW_CLEAR_BUF_EMPTY_MASK                    0x1
-#define DL6_SW_CLEAR_BUF_EMPTY_MASK_SFT                (0x1 << 15)
-#define DL6_PBUF_SIZE_SFT                              12
-#define DL6_PBUF_SIZE_MASK                             0x3
-#define DL6_PBUF_SIZE_MASK_SFT                         (0x3 << 12)
-#define DL6_MONO_SFT                                   8
-#define DL6_MONO_MASK                                  0x1
-#define DL6_MONO_MASK_SFT                              (0x1 << 8)
-#define DL6_NORMAL_MODE_SFT                            5
-#define DL6_NORMAL_MODE_MASK                           0x1
-#define DL6_NORMAL_MODE_MASK_SFT                       (0x1 << 5)
-#define DL6_HALIGN_SFT                                 4
-#define DL6_HALIGN_MASK                                0x1
-#define DL6_HALIGN_MASK_SFT                            (0x1 << 4)
-#define DL6_HD_MODE_SFT                                0
-#define DL6_HD_MODE_MASK                               0x3
-#define DL6_HD_MODE_MASK_SFT                           (0x3 << 0)
-
-/* AFE_DL7_CON0 */
-#define DL7_MODE_SFT                                   24
-#define DL7_MODE_MASK                                  0xf
-#define DL7_MODE_MASK_SFT                              (0xf << 24)
-#define DL7_MINLEN_SFT                                 20
-#define DL7_MINLEN_MASK                                0xf
-#define DL7_MINLEN_MASK_SFT                            (0xf << 20)
-#define DL7_MAXLEN_SFT                                 16
-#define DL7_MAXLEN_MASK                                0xf
-#define DL7_MAXLEN_MASK_SFT                            (0xf << 16)
-#define DL7_SW_CLEAR_BUF_EMPTY_SFT                     15
-#define DL7_SW_CLEAR_BUF_EMPTY_MASK                    0x1
-#define DL7_SW_CLEAR_BUF_EMPTY_MASK_SFT                (0x1 << 15)
-#define DL7_PBUF_SIZE_SFT                              12
-#define DL7_PBUF_SIZE_MASK                             0x3
-#define DL7_PBUF_SIZE_MASK_SFT                         (0x3 << 12)
-#define DL7_MONO_SFT                                   8
-#define DL7_MONO_MASK                                  0x1
-#define DL7_MONO_MASK_SFT                              (0x1 << 8)
-#define DL7_NORMAL_MODE_SFT                            5
-#define DL7_NORMAL_MODE_MASK                           0x1
-#define DL7_NORMAL_MODE_MASK_SFT                       (0x1 << 5)
-#define DL7_HALIGN_SFT                                 4
-#define DL7_HALIGN_MASK                                0x1
-#define DL7_HALIGN_MASK_SFT                            (0x1 << 4)
-#define DL7_HD_MODE_SFT                                0
-#define DL7_HD_MODE_MASK                               0x3
-#define DL7_HD_MODE_MASK_SFT                           (0x3 << 0)
-
-/* AFE_DL8_CON0 */
-#define DL8_MODE_SFT                                   24
-#define DL8_MODE_MASK                                  0xf
-#define DL8_MODE_MASK_SFT                              (0xf << 24)
-#define DL8_MINLEN_SFT                                 20
-#define DL8_MINLEN_MASK                                0xf
-#define DL8_MINLEN_MASK_SFT                            (0xf << 20)
-#define DL8_MAXLEN_SFT                                 16
-#define DL8_MAXLEN_MASK                                0xf
-#define DL8_MAXLEN_MASK_SFT                            (0xf << 16)
-#define DL8_SW_CLEAR_BUF_EMPTY_SFT                     15
-#define DL8_SW_CLEAR_BUF_EMPTY_MASK                    0x1
-#define DL8_SW_CLEAR_BUF_EMPTY_MASK_SFT                (0x1 << 15)
-#define DL8_PBUF_SIZE_SFT                              12
-#define DL8_PBUF_SIZE_MASK                             0x3
-#define DL8_PBUF_SIZE_MASK_SFT                         (0x3 << 12)
-#define DL8_MONO_SFT                                   8
-#define DL8_MONO_MASK                                  0x1
-#define DL8_MONO_MASK_SFT                              (0x1 << 8)
-#define DL8_NORMAL_MODE_SFT                            5
-#define DL8_NORMAL_MODE_MASK                           0x1
-#define DL8_NORMAL_MODE_MASK_SFT                       (0x1 << 5)
-#define DL8_HALIGN_SFT                                 4
-#define DL8_HALIGN_MASK                                0x1
-#define DL8_HALIGN_MASK_SFT                            (0x1 << 4)
-#define DL8_HD_MODE_SFT                                0
-#define DL8_HD_MODE_MASK                               0x3
-#define DL8_HD_MODE_MASK_SFT                           (0x3 << 0)
-
-/* AFE_DL12_CON0 */
-#define DL12_MODE_SFT                                  24
-#define DL12_MODE_MASK                                 0xf
-#define DL12_MODE_MASK_SFT                             (0xf << 24)
-#define DL12_MINLEN_SFT                                20
-#define DL12_MINLEN_MASK                               0xf
-#define DL12_MINLEN_MASK_SFT                           (0xf << 20)
-#define DL12_MAXLEN_SFT                                16
-#define DL12_MAXLEN_MASK                               0xf
-#define DL12_MAXLEN_MASK_SFT                           (0xf << 16)
-#define DL12_SW_CLEAR_BUF_EMPTY_SFT                    15
-#define DL12_SW_CLEAR_BUF_EMPTY_MASK                   0x1
-#define DL12_SW_CLEAR_BUF_EMPTY_MASK_SFT               (0x1 << 15)
-#define DL12_PBUF_SIZE_SFT                             12
-#define DL12_PBUF_SIZE_MASK                            0x3
-#define DL12_PBUF_SIZE_MASK_SFT                        (0x3 << 12)
-#define DL12_4CH_EN_SFT                                11
-#define DL12_4CH_EN_MASK                               0x1
-#define DL12_4CH_EN_MASK_SFT                           (0x1 << 11)
-#define DL12_MONO_SFT                                  8
-#define DL12_MONO_MASK                                 0x1
-#define DL12_MONO_MASK_SFT                             (0x1 << 8)
-#define DL12_NORMAL_MODE_SFT                           5
-#define DL12_NORMAL_MODE_MASK                          0x1
-#define DL12_NORMAL_MODE_MASK_SFT                      (0x1 << 5)
-#define DL12_HALIGN_SFT                                4
-#define DL12_HALIGN_MASK                               0x1
-#define DL12_HALIGN_MASK_SFT                           (0x1 << 4)
-#define DL12_HD_MODE_SFT                               0
-#define DL12_HD_MODE_MASK                              0x3
-#define DL12_HD_MODE_MASK_SFT                          (0x3 << 0)
-
-/* AFE_AWB_CON0 */
-#define AWB_MODE_SFT                                   24
-#define AWB_MODE_MASK                                  0xf
-#define AWB_MODE_MASK_SFT                              (0xf << 24)
-#define AWB_SW_CLEAR_BUF_FULL_SFT                      15
-#define AWB_SW_CLEAR_BUF_FULL_MASK                     0x1
-#define AWB_SW_CLEAR_BUF_FULL_MASK_SFT                 (0x1 << 15)
-#define AWB_R_MONO_SFT                                 9
-#define AWB_R_MONO_MASK                                0x1
-#define AWB_R_MONO_MASK_SFT                            (0x1 << 9)
-#define AWB_MONO_SFT                                   8
-#define AWB_MONO_MASK                                  0x1
-#define AWB_MONO_MASK_SFT                              (0x1 << 8)
-#define AWB_WR_SIGN_SFT                                6
-#define AWB_WR_SIGN_MASK                               0x1
-#define AWB_WR_SIGN_MASK_SFT                           (0x1 << 6)
-#define AWB_NORMAL_MODE_SFT                            5
-#define AWB_NORMAL_MODE_MASK                           0x1
-#define AWB_NORMAL_MODE_MASK_SFT                       (0x1 << 5)
-#define AWB_HALIGN_SFT                                 4
-#define AWB_HALIGN_MASK                                0x1
-#define AWB_HALIGN_MASK_SFT                            (0x1 << 4)
-#define AWB_HD_MODE_SFT                                0
-#define AWB_HD_MODE_MASK                               0x3
-#define AWB_HD_MODE_MASK_SFT                           (0x3 << 0)
-
-/* AFE_AWB2_CON0 */
-#define AWB2_MODE_SFT                                  24
-#define AWB2_MODE_MASK                                 0xf
-#define AWB2_MODE_MASK_SFT                             (0xf << 24)
-#define AWB2_SW_CLEAR_BUF_FULL_SFT                     15
-#define AWB2_SW_CLEAR_BUF_FULL_MASK                    0x1
-#define AWB2_SW_CLEAR_BUF_FULL_MASK_SFT                (0x1 << 15)
-#define AWB2_R_MONO_SFT                                9
-#define AWB2_R_MONO_MASK                               0x1
-#define AWB2_R_MONO_MASK_SFT                           (0x1 << 9)
-#define AWB2_MONO_SFT                                  8
-#define AWB2_MONO_MASK                                 0x1
-#define AWB2_MONO_MASK_SFT                             (0x1 << 8)
-#define AWB2_WR_SIGN_SFT                               6
-#define AWB2_WR_SIGN_MASK                              0x1
-#define AWB2_WR_SIGN_MASK_SFT                          (0x1 << 6)
-#define AWB2_NORMAL_MODE_SFT                           5
-#define AWB2_NORMAL_MODE_MASK                          0x1
-#define AWB2_NORMAL_MODE_MASK_SFT                      (0x1 << 5)
-#define AWB2_HALIGN_SFT                                4
-#define AWB2_HALIGN_MASK                               0x1
-#define AWB2_HALIGN_MASK_SFT                           (0x1 << 4)
-#define AWB2_HD_MODE_SFT                               0
-#define AWB2_HD_MODE_MASK                              0x3
-#define AWB2_HD_MODE_MASK_SFT                          (0x3 << 0)
-
-/* AFE_VUL_CON0 */
-#define VUL_MODE_SFT                                   24
-#define VUL_MODE_MASK                                  0xf
-#define VUL_MODE_MASK_SFT                              (0xf << 24)
-#define VUL_SW_CLEAR_BUF_FULL_SFT                      15
-#define VUL_SW_CLEAR_BUF_FULL_MASK                     0x1
-#define VUL_SW_CLEAR_BUF_FULL_MASK_SFT                 (0x1 << 15)
-#define VUL_R_MONO_SFT                                 9
-#define VUL_R_MONO_MASK                                0x1
-#define VUL_R_MONO_MASK_SFT                            (0x1 << 9)
-#define VUL_MONO_SFT                                   8
-#define VUL_MONO_MASK                                  0x1
-#define VUL_MONO_MASK_SFT                              (0x1 << 8)
-#define VUL_WR_SIGN_SFT                                6
-#define VUL_WR_SIGN_MASK                               0x1
-#define VUL_WR_SIGN_MASK_SFT                           (0x1 << 6)
-#define VUL_NORMAL_MODE_SFT                            5
-#define VUL_NORMAL_MODE_MASK                           0x1
-#define VUL_NORMAL_MODE_MASK_SFT                       (0x1 << 5)
-#define VUL_HALIGN_SFT                                 4
-#define VUL_HALIGN_MASK                                0x1
-#define VUL_HALIGN_MASK_SFT                            (0x1 << 4)
-#define VUL_HD_MODE_SFT                                0
-#define VUL_HD_MODE_MASK                               0x3
-#define VUL_HD_MODE_MASK_SFT                           (0x3 << 0)
-
-/* AFE_VUL12_CON0 */
-#define VUL12_MODE_SFT                                 24
-#define VUL12_MODE_MASK                                0xf
-#define VUL12_MODE_MASK_SFT                            (0xf << 24)
-#define VUL12_SW_CLEAR_BUF_FULL_SFT                    15
-#define VUL12_SW_CLEAR_BUF_FULL_MASK                   0x1
-#define VUL12_SW_CLEAR_BUF_FULL_MASK_SFT               (0x1 << 15)
-#define VUL12_4CH_EN_SFT                               11
-#define VUL12_4CH_EN_MASK                              0x1
-#define VUL12_4CH_EN_MASK_SFT                          (0x1 << 11)
-#define VUL12_R_MONO_SFT                               9
-#define VUL12_R_MONO_MASK                              0x1
-#define VUL12_R_MONO_MASK_SFT                          (0x1 << 9)
-#define VUL12_MONO_SFT                                 8
-#define VUL12_MONO_MASK                                0x1
-#define VUL12_MONO_MASK_SFT                            (0x1 << 8)
-#define VUL12_WR_SIGN_SFT                              6
-#define VUL12_WR_SIGN_MASK                             0x1
-#define VUL12_WR_SIGN_MASK_SFT                         (0x1 << 6)
-#define VUL12_NORMAL_MODE_SFT                          5
-#define VUL12_NORMAL_MODE_MASK                         0x1
-#define VUL12_NORMAL_MODE_MASK_SFT                     (0x1 << 5)
-#define VUL12_HALIGN_SFT                               4
-#define VUL12_HALIGN_MASK                              0x1
-#define VUL12_HALIGN_MASK_SFT                          (0x1 << 4)
-#define VUL12_HD_MODE_SFT                              0
-#define VUL12_HD_MODE_MASK                             0x3
-#define VUL12_HD_MODE_MASK_SFT                         (0x3 << 0)
-
-/* AFE_VUL2_CON0 */
-#define VUL2_MODE_SFT                                  24
-#define VUL2_MODE_MASK                                 0xf
-#define VUL2_MODE_MASK_SFT                             (0xf << 24)
-#define VUL2_SW_CLEAR_BUF_FULL_SFT                     15
-#define VUL2_SW_CLEAR_BUF_FULL_MASK                    0x1
-#define VUL2_SW_CLEAR_BUF_FULL_MASK_SFT                (0x1 << 15)
-#define VUL2_R_MONO_SFT                                9
-#define VUL2_R_MONO_MASK                               0x1
-#define VUL2_R_MONO_MASK_SFT                           (0x1 << 9)
-#define VUL2_MONO_SFT                                  8
-#define VUL2_MONO_MASK                                 0x1
-#define VUL2_MONO_MASK_SFT                             (0x1 << 8)
-#define VUL2_WR_SIGN_SFT                               6
-#define VUL2_WR_SIGN_MASK                              0x1
-#define VUL2_WR_SIGN_MASK_SFT                          (0x1 << 6)
-#define VUL2_NORMAL_MODE_SFT                           5
-#define VUL2_NORMAL_MODE_MASK                          0x1
-#define VUL2_NORMAL_MODE_MASK_SFT                      (0x1 << 5)
-#define VUL2_HALIGN_SFT                                4
-#define VUL2_HALIGN_MASK                               0x1
-#define VUL2_HALIGN_MASK_SFT                           (0x1 << 4)
-#define VUL2_HD_MODE_SFT                               0
-#define VUL2_HD_MODE_MASK                              0x3
-#define VUL2_HD_MODE_MASK_SFT                          (0x3 << 0)
-
-/* AFE_VUL3_CON0 */
-#define VUL3_MODE_SFT                                  24
-#define VUL3_MODE_MASK                                 0xf
-#define VUL3_MODE_MASK_SFT                             (0xf << 24)
-#define VUL3_SW_CLEAR_BUF_FULL_SFT                     15
-#define VUL3_SW_CLEAR_BUF_FULL_MASK                    0x1
-#define VUL3_SW_CLEAR_BUF_FULL_MASK_SFT                (0x1 << 15)
-#define VUL3_R_MONO_SFT                                9
-#define VUL3_R_MONO_MASK                               0x1
-#define VUL3_R_MONO_MASK_SFT                           (0x1 << 9)
-#define VUL3_MONO_SFT                                  8
-#define VUL3_MONO_MASK                                 0x1
-#define VUL3_MONO_MASK_SFT                             (0x1 << 8)
-#define VUL3_WR_SIGN_SFT                               6
-#define VUL3_WR_SIGN_MASK                              0x1
-#define VUL3_WR_SIGN_MASK_SFT                          (0x1 << 6)
-#define VUL3_NORMAL_MODE_SFT                           5
-#define VUL3_NORMAL_MODE_MASK                          0x1
-#define VUL3_NORMAL_MODE_MASK_SFT                      (0x1 << 5)
-#define VUL3_HALIGN_SFT                                4
-#define VUL3_HALIGN_MASK                               0x1
-#define VUL3_HALIGN_MASK_SFT                           (0x1 << 4)
-#define VUL3_HD_MODE_SFT                               0
-#define VUL3_HD_MODE_MASK                              0x3
-#define VUL3_HD_MODE_MASK_SFT                          (0x3 << 0)
-
-/* AFE_VUL4_CON0 */
-#define VUL4_MODE_SFT                                  24
-#define VUL4_MODE_MASK                                 0xf
-#define VUL4_MODE_MASK_SFT                             (0xf << 24)
-#define VUL4_SW_CLEAR_BUF_FULL_SFT                     15
-#define VUL4_SW_CLEAR_BUF_FULL_MASK                    0x1
-#define VUL4_SW_CLEAR_BUF_FULL_MASK_SFT                (0x1 << 15)
-#define VUL4_R_MONO_SFT                                9
-#define VUL4_R_MONO_MASK                               0x1
-#define VUL4_R_MONO_MASK_SFT                           (0x1 << 9)
-#define VUL4_MONO_SFT                                  8
-#define VUL4_MONO_MASK                                 0x1
-#define VUL4_MONO_MASK_SFT                             (0x1 << 8)
-#define VUL4_WR_SIGN_SFT                               6
-#define VUL4_WR_SIGN_MASK                              0x1
-#define VUL4_WR_SIGN_MASK_SFT                          (0x1 << 6)
-#define VUL4_NORMAL_MODE_SFT                           5
-#define VUL4_NORMAL_MODE_MASK                          0x1
-#define VUL4_NORMAL_MODE_MASK_SFT                      (0x1 << 5)
-#define VUL4_HALIGN_SFT                                4
-#define VUL4_HALIGN_MASK                               0x1
-#define VUL4_HALIGN_MASK_SFT                           (0x1 << 4)
-#define VUL4_HD_MODE_SFT                               0
-#define VUL4_HD_MODE_MASK                              0x3
-#define VUL4_HD_MODE_MASK_SFT                          (0x3 << 0)
-
-/* AFE_VUL5_CON0 */
-#define VUL5_MODE_SFT                                  24
-#define VUL5_MODE_MASK                                 0xf
-#define VUL5_MODE_MASK_SFT                             (0xf << 24)
-#define VUL5_SW_CLEAR_BUF_FULL_SFT                     15
-#define VUL5_SW_CLEAR_BUF_FULL_MASK                    0x1
-#define VUL5_SW_CLEAR_BUF_FULL_MASK_SFT                (0x1 << 15)
-#define VUL5_R_MONO_SFT                                9
-#define VUL5_R_MONO_MASK                               0x1
-#define VUL5_R_MONO_MASK_SFT                           (0x1 << 9)
-#define VUL5_MONO_SFT                                  8
-#define VUL5_MONO_MASK                                 0x1
-#define VUL5_MONO_MASK_SFT                             (0x1 << 8)
-#define VUL5_WR_SIGN_SFT                               6
-#define VUL5_WR_SIGN_MASK                              0x1
-#define VUL5_WR_SIGN_MASK_SFT                          (0x1 << 6)
-#define VUL5_NORMAL_MODE_SFT                           5
-#define VUL5_NORMAL_MODE_MASK                          0x1
-#define VUL5_NORMAL_MODE_MASK_SFT                      (0x1 << 5)
-#define VUL5_HALIGN_SFT                                4
-#define VUL5_HALIGN_MASK                               0x1
-#define VUL5_HALIGN_MASK_SFT                           (0x1 << 4)
-#define VUL5_HD_MODE_SFT                               0
-#define VUL5_HD_MODE_MASK                              0x3
-#define VUL5_HD_MODE_MASK_SFT                          (0x3 << 0)
-
-/* AFE_VUL6_CON0 */
-#define VUL6_MODE_SFT                                  24
-#define VUL6_MODE_MASK                                 0xf
-#define VUL6_MODE_MASK_SFT                             (0xf << 24)
-#define VUL6_SW_CLEAR_BUF_FULL_SFT                     15
-#define VUL6_SW_CLEAR_BUF_FULL_MASK                    0x1
-#define VUL6_SW_CLEAR_BUF_FULL_MASK_SFT                (0x1 << 15)
-#define VUL6_R_MONO_SFT                                9
-#define VUL6_R_MONO_MASK                               0x1
-#define VUL6_R_MONO_MASK_SFT                           (0x1 << 9)
-#define VUL6_MONO_SFT                                  8
-#define VUL6_MONO_MASK                                 0x1
-#define VUL6_MONO_MASK_SFT                             (0x1 << 8)
-#define VUL6_WR_SIGN_SFT                               6
-#define VUL6_WR_SIGN_MASK                              0x1
-#define VUL6_WR_SIGN_MASK_SFT                          (0x1 << 6)
-#define VUL6_NORMAL_MODE_SFT                           5
-#define VUL6_NORMAL_MODE_MASK                          0x1
-#define VUL6_NORMAL_MODE_MASK_SFT                      (0x1 << 5)
-#define VUL6_HALIGN_SFT                                4
-#define VUL6_HALIGN_MASK                               0x1
-#define VUL6_HALIGN_MASK_SFT                           (0x1 << 4)
-#define VUL6_HD_MODE_SFT                               0
-#define VUL6_HD_MODE_MASK                              0x3
-#define VUL6_HD_MODE_MASK_SFT                          (0x3 << 0)
-
-/* AFE_DAI_CON0 */
-#define DAI_MODE_SFT                                   24
-#define DAI_MODE_MASK                                  0x3
-#define DAI_MODE_MASK_SFT                              (0x3 << 24)
-#define DAI_SW_CLEAR_BUF_FULL_SFT                      15
-#define DAI_SW_CLEAR_BUF_FULL_MASK                     0x1
-#define DAI_SW_CLEAR_BUF_FULL_MASK_SFT                 (0x1 << 15)
-#define DAI_DUPLICATE_WR_SFT                           10
-#define DAI_DUPLICATE_WR_MASK                          0x1
-#define DAI_DUPLICATE_WR_MASK_SFT                      (0x1 << 10)
-#define DAI_MONO_SFT                                   8
-#define DAI_MONO_MASK                                  0x1
-#define DAI_MONO_MASK_SFT                              (0x1 << 8)
-#define DAI_WR_SIGN_SFT                                6
-#define DAI_WR_SIGN_MASK                               0x1
-#define DAI_WR_SIGN_MASK_SFT                           (0x1 << 6)
-#define DAI_NORMAL_MODE_SFT                            5
-#define DAI_NORMAL_MODE_MASK                           0x1
-#define DAI_NORMAL_MODE_MASK_SFT                       (0x1 << 5)
-#define DAI_HALIGN_SFT                                 4
-#define DAI_HALIGN_MASK                                0x1
-#define DAI_HALIGN_MASK_SFT                            (0x1 << 4)
-#define DAI_HD_MODE_SFT                                0
-#define DAI_HD_MODE_MASK                               0x3
-#define DAI_HD_MODE_MASK_SFT                           (0x3 << 0)
-
-/* AFE_MOD_DAI_CON0 */
-#define MOD_DAI_MODE_SFT                               24
-#define MOD_DAI_MODE_MASK                              0x3
-#define MOD_DAI_MODE_MASK_SFT                          (0x3 << 24)
-#define MOD_DAI_SW_CLEAR_BUF_FULL_SFT                  15
-#define MOD_DAI_SW_CLEAR_BUF_FULL_MASK                 0x1
-#define MOD_DAI_SW_CLEAR_BUF_FULL_MASK_SFT             (0x1 << 15)
-#define MOD_DAI_DUPLICATE_WR_SFT                       10
-#define MOD_DAI_DUPLICATE_WR_MASK                      0x1
-#define MOD_DAI_DUPLICATE_WR_MASK_SFT                  (0x1 << 10)
-#define MOD_DAI_MONO_SFT                               8
-#define MOD_DAI_MONO_MASK                              0x1
-#define MOD_DAI_MONO_MASK_SFT                          (0x1 << 8)
-#define MOD_DAI_WR_SIGN_SFT                            6
-#define MOD_DAI_WR_SIGN_MASK                           0x1
-#define MOD_DAI_WR_SIGN_MASK_SFT                       (0x1 << 6)
-#define MOD_DAI_NORMAL_MODE_SFT                        5
-#define MOD_DAI_NORMAL_MODE_MASK                       0x1
-#define MOD_DAI_NORMAL_MODE_MASK_SFT                   (0x1 << 5)
-#define MOD_DAI_HALIGN_SFT                             4
-#define MOD_DAI_HALIGN_MASK                            0x1
-#define MOD_DAI_HALIGN_MASK_SFT                        (0x1 << 4)
-#define MOD_DAI_HD_MODE_SFT                            0
-#define MOD_DAI_HD_MODE_MASK                           0x3
-#define MOD_DAI_HD_MODE_MASK_SFT                       (0x3 << 0)
-
-/* AFE_DAI2_CON0 */
-#define DAI2_MODE_SFT                                  24
-#define DAI2_MODE_MASK                                 0xf
-#define DAI2_MODE_MASK_SFT                             (0xf << 24)
-#define DAI2_SW_CLEAR_BUF_FULL_SFT                     15
-#define DAI2_SW_CLEAR_BUF_FULL_MASK                    0x1
-#define DAI2_SW_CLEAR_BUF_FULL_MASK_SFT                (0x1 << 15)
-#define DAI2_DUPLICATE_WR_SFT                          10
-#define DAI2_DUPLICATE_WR_MASK                         0x1
-#define DAI2_DUPLICATE_WR_MASK_SFT                     (0x1 << 10)
-#define DAI2_MONO_SFT                                  8
-#define DAI2_MONO_MASK                                 0x1
-#define DAI2_MONO_MASK_SFT                             (0x1 << 8)
-#define DAI2_WR_SIGN_SFT                               6
-#define DAI2_WR_SIGN_MASK                              0x1
-#define DAI2_WR_SIGN_MASK_SFT                          (0x1 << 6)
-#define DAI2_NORMAL_MODE_SFT                           5
-#define DAI2_NORMAL_MODE_MASK                          0x1
-#define DAI2_NORMAL_MODE_MASK_SFT                      (0x1 << 5)
-#define DAI2_HALIGN_SFT                                4
-#define DAI2_HALIGN_MASK                               0x1
-#define DAI2_HALIGN_MASK_SFT                           (0x1 << 4)
-#define DAI2_HD_MODE_SFT                               0
-#define DAI2_HD_MODE_MASK                              0x3
-#define DAI2_HD_MODE_MASK_SFT                          (0x3 << 0)
-
-/* AFE_MEMIF_CON0 */
-#define CPU_COMPACT_MODE_SFT                           2
-#define CPU_COMPACT_MODE_MASK                          0x1
-#define CPU_COMPACT_MODE_MASK_SFT                      (0x1 << 2)
-#define CPU_HD_ALIGN_SFT                               1
-#define CPU_HD_ALIGN_MASK                              0x1
-#define CPU_HD_ALIGN_MASK_SFT                          (0x1 << 1)
-#define SYSRAM_SIGN_SFT                                0
-#define SYSRAM_SIGN_MASK                               0x1
-#define SYSRAM_SIGN_MASK_SFT                           (0x1 << 0)
-
-/* AFE_IRQ_MCU_CON0 */
-#define IRQ31_MCU_ON_SFT                               31
-#define IRQ31_MCU_ON_MASK                              0x1
-#define IRQ31_MCU_ON_MASK_SFT                          (0x1 << 31)
-#define IRQ26_MCU_ON_SFT                               26
-#define IRQ26_MCU_ON_MASK                              0x1
-#define IRQ26_MCU_ON_MASK_SFT                          (0x1 << 26)
-#define IRQ25_MCU_ON_SFT                               25
-#define IRQ25_MCU_ON_MASK                              0x1
-#define IRQ25_MCU_ON_MASK_SFT                          (0x1 << 25)
-#define IRQ24_MCU_ON_SFT                               24
-#define IRQ24_MCU_ON_MASK                              0x1
-#define IRQ24_MCU_ON_MASK_SFT                          (0x1 << 24)
-#define IRQ23_MCU_ON_SFT                               23
-#define IRQ23_MCU_ON_MASK                              0x1
-#define IRQ23_MCU_ON_MASK_SFT                          (0x1 << 23)
-#define IRQ22_MCU_ON_SFT                               22
-#define IRQ22_MCU_ON_MASK                              0x1
-#define IRQ22_MCU_ON_MASK_SFT                          (0x1 << 22)
-#define IRQ21_MCU_ON_SFT                               21
-#define IRQ21_MCU_ON_MASK                              0x1
-#define IRQ21_MCU_ON_MASK_SFT                          (0x1 << 21)
-#define IRQ20_MCU_ON_SFT                               20
-#define IRQ20_MCU_ON_MASK                              0x1
-#define IRQ20_MCU_ON_MASK_SFT                          (0x1 << 20)
-#define IRQ19_MCU_ON_SFT                               19
-#define IRQ19_MCU_ON_MASK                              0x1
-#define IRQ19_MCU_ON_MASK_SFT                          (0x1 << 19)
-#define IRQ18_MCU_ON_SFT                               18
-#define IRQ18_MCU_ON_MASK                              0x1
-#define IRQ18_MCU_ON_MASK_SFT                          (0x1 << 18)
-#define IRQ17_MCU_ON_SFT                               17
-#define IRQ17_MCU_ON_MASK                              0x1
-#define IRQ17_MCU_ON_MASK_SFT                          (0x1 << 17)
-#define IRQ16_MCU_ON_SFT                               16
-#define IRQ16_MCU_ON_MASK                              0x1
-#define IRQ16_MCU_ON_MASK_SFT                          (0x1 << 16)
-#define IRQ15_MCU_ON_SFT                               15
-#define IRQ15_MCU_ON_MASK                              0x1
-#define IRQ15_MCU_ON_MASK_SFT                          (0x1 << 15)
-#define IRQ14_MCU_ON_SFT                               14
-#define IRQ14_MCU_ON_MASK                              0x1
-#define IRQ14_MCU_ON_MASK_SFT                          (0x1 << 14)
-#define IRQ13_MCU_ON_SFT                               13
-#define IRQ13_MCU_ON_MASK                              0x1
-#define IRQ13_MCU_ON_MASK_SFT                          (0x1 << 13)
-#define IRQ12_MCU_ON_SFT                               12
-#define IRQ12_MCU_ON_MASK                              0x1
-#define IRQ12_MCU_ON_MASK_SFT                          (0x1 << 12)
-#define IRQ11_MCU_ON_SFT                               11
-#define IRQ11_MCU_ON_MASK                              0x1
-#define IRQ11_MCU_ON_MASK_SFT                          (0x1 << 11)
-#define IRQ10_MCU_ON_SFT                               10
-#define IRQ10_MCU_ON_MASK                              0x1
-#define IRQ10_MCU_ON_MASK_SFT                          (0x1 << 10)
-#define IRQ9_MCU_ON_SFT                                9
-#define IRQ9_MCU_ON_MASK                               0x1
-#define IRQ9_MCU_ON_MASK_SFT                           (0x1 << 9)
-#define IRQ8_MCU_ON_SFT                                8
-#define IRQ8_MCU_ON_MASK                               0x1
-#define IRQ8_MCU_ON_MASK_SFT                           (0x1 << 8)
-#define IRQ7_MCU_ON_SFT                                7
-#define IRQ7_MCU_ON_MASK                               0x1
-#define IRQ7_MCU_ON_MASK_SFT                           (0x1 << 7)
-#define IRQ6_MCU_ON_SFT                                6
-#define IRQ6_MCU_ON_MASK                               0x1
-#define IRQ6_MCU_ON_MASK_SFT                           (0x1 << 6)
-#define IRQ5_MCU_ON_SFT                                5
-#define IRQ5_MCU_ON_MASK                               0x1
-#define IRQ5_MCU_ON_MASK_SFT                           (0x1 << 5)
-#define IRQ4_MCU_ON_SFT                                4
-#define IRQ4_MCU_ON_MASK                               0x1
-#define IRQ4_MCU_ON_MASK_SFT                           (0x1 << 4)
-#define IRQ3_MCU_ON_SFT                                3
-#define IRQ3_MCU_ON_MASK                               0x1
-#define IRQ3_MCU_ON_MASK_SFT                           (0x1 << 3)
-#define IRQ2_MCU_ON_SFT                                2
-#define IRQ2_MCU_ON_MASK                               0x1
-#define IRQ2_MCU_ON_MASK_SFT                           (0x1 << 2)
-#define IRQ1_MCU_ON_SFT                                1
-#define IRQ1_MCU_ON_MASK                               0x1
-#define IRQ1_MCU_ON_MASK_SFT                           (0x1 << 1)
-#define IRQ0_MCU_ON_SFT                                0
-#define IRQ0_MCU_ON_MASK                               0x1
-#define IRQ0_MCU_ON_MASK_SFT                           (0x1 << 0)
-
-/* AFE_IRQ_MCU_CON1 */
-#define IRQ7_MCU_MODE_SFT                              28
-#define IRQ7_MCU_MODE_MASK                             0xf
-#define IRQ7_MCU_MODE_MASK_SFT                         (0xf << 28)
-#define IRQ6_MCU_MODE_SFT                              24
-#define IRQ6_MCU_MODE_MASK                             0xf
-#define IRQ6_MCU_MODE_MASK_SFT                         (0xf << 24)
-#define IRQ5_MCU_MODE_SFT                              20
-#define IRQ5_MCU_MODE_MASK                             0xf
-#define IRQ5_MCU_MODE_MASK_SFT                         (0xf << 20)
-#define IRQ4_MCU_MODE_SFT                              16
-#define IRQ4_MCU_MODE_MASK                             0xf
-#define IRQ4_MCU_MODE_MASK_SFT                         (0xf << 16)
-#define IRQ3_MCU_MODE_SFT                              12
-#define IRQ3_MCU_MODE_MASK                             0xf
-#define IRQ3_MCU_MODE_MASK_SFT                         (0xf << 12)
-#define IRQ2_MCU_MODE_SFT                              8
-#define IRQ2_MCU_MODE_MASK                             0xf
-#define IRQ2_MCU_MODE_MASK_SFT                         (0xf << 8)
-#define IRQ1_MCU_MODE_SFT                              4
-#define IRQ1_MCU_MODE_MASK                             0xf
-#define IRQ1_MCU_MODE_MASK_SFT                         (0xf << 4)
-#define IRQ0_MCU_MODE_SFT                              0
-#define IRQ0_MCU_MODE_MASK                             0xf
-#define IRQ0_MCU_MODE_MASK_SFT                         (0xf << 0)
-
-/* AFE_IRQ_MCU_CON2 */
-#define IRQ15_MCU_MODE_SFT                             28
-#define IRQ15_MCU_MODE_MASK                            0xf
-#define IRQ15_MCU_MODE_MASK_SFT                        (0xf << 28)
-#define IRQ14_MCU_MODE_SFT                             24
-#define IRQ14_MCU_MODE_MASK                            0xf
-#define IRQ14_MCU_MODE_MASK_SFT                        (0xf << 24)
-#define IRQ13_MCU_MODE_SFT                             20
-#define IRQ13_MCU_MODE_MASK                            0xf
-#define IRQ13_MCU_MODE_MASK_SFT                        (0xf << 20)
-#define IRQ12_MCU_MODE_SFT                             16
-#define IRQ12_MCU_MODE_MASK                            0xf
-#define IRQ12_MCU_MODE_MASK_SFT                        (0xf << 16)
-#define IRQ11_MCU_MODE_SFT                             12
-#define IRQ11_MCU_MODE_MASK                            0xf
-#define IRQ11_MCU_MODE_MASK_SFT                        (0xf << 12)
-#define IRQ10_MCU_MODE_SFT                             8
-#define IRQ10_MCU_MODE_MASK                            0xf
-#define IRQ10_MCU_MODE_MASK_SFT                        (0xf << 8)
-#define IRQ9_MCU_MODE_SFT                              4
-#define IRQ9_MCU_MODE_MASK                             0xf
-#define IRQ9_MCU_MODE_MASK_SFT                         (0xf << 4)
-#define IRQ8_MCU_MODE_SFT                              0
-#define IRQ8_MCU_MODE_MASK                             0xf
-#define IRQ8_MCU_MODE_MASK_SFT                         (0xf << 0)
-
-/* AFE_IRQ_MCU_CON3 */
-#define IRQ23_MCU_MODE_SFT                             28
-#define IRQ23_MCU_MODE_MASK                            0xf
-#define IRQ23_MCU_MODE_MASK_SFT                        (0xf << 28)
-#define IRQ22_MCU_MODE_SFT                             24
-#define IRQ22_MCU_MODE_MASK                            0xf
-#define IRQ22_MCU_MODE_MASK_SFT                        (0xf << 24)
-#define IRQ21_MCU_MODE_SFT                             20
-#define IRQ21_MCU_MODE_MASK                            0xf
-#define IRQ21_MCU_MODE_MASK_SFT                        (0xf << 20)
-#define IRQ20_MCU_MODE_SFT                             16
-#define IRQ20_MCU_MODE_MASK                            0xf
-#define IRQ20_MCU_MODE_MASK_SFT                        (0xf << 16)
-#define IRQ19_MCU_MODE_SFT                             12
-#define IRQ19_MCU_MODE_MASK                            0xf
-#define IRQ19_MCU_MODE_MASK_SFT                        (0xf << 12)
-#define IRQ18_MCU_MODE_SFT                             8
-#define IRQ18_MCU_MODE_MASK                            0xf
-#define IRQ18_MCU_MODE_MASK_SFT                        (0xf << 8)
-#define IRQ17_MCU_MODE_SFT                             4
-#define IRQ17_MCU_MODE_MASK                            0xf
-#define IRQ17_MCU_MODE_MASK_SFT                        (0xf << 4)
-#define IRQ16_MCU_MODE_SFT                             0
-#define IRQ16_MCU_MODE_MASK                            0xf
-#define IRQ16_MCU_MODE_MASK_SFT                        (0xf << 0)
-
-/* AFE_IRQ_MCU_CON4 */
-#define IRQ26_MCU_MODE_SFT                             8
-#define IRQ26_MCU_MODE_MASK                            0xf
-#define IRQ26_MCU_MODE_MASK_SFT                        (0xf << 8)
-#define IRQ25_MCU_MODE_SFT                             4
-#define IRQ25_MCU_MODE_MASK                            0xf
-#define IRQ25_MCU_MODE_MASK_SFT                        (0xf << 4)
-#define IRQ24_MCU_MODE_SFT                             0
-#define IRQ24_MCU_MODE_MASK                            0xf
-#define IRQ24_MCU_MODE_MASK_SFT                        (0xf << 0)
-
-/* AFE_IRQ_MCU_CLR */
-#define IRQ31_MCU_CLR_SFT                              31
-#define IRQ31_MCU_CLR_MASK                             0x1
-#define IRQ31_MCU_CLR_MASK_SFT                         (0x1 << 31)
-#define IRQ26_MCU_CLR_SFT                              26
-#define IRQ26_MCU_CLR_MASK                             0x1
-#define IRQ26_MCU_CLR_MASK_SFT                         (0x1 << 26)
-#define IRQ25_MCU_CLR_SFT                              25
-#define IRQ25_MCU_CLR_MASK                             0x1
-#define IRQ25_MCU_CLR_MASK_SFT                         (0x1 << 25)
-#define IRQ24_MCU_CLR_SFT                              24
-#define IRQ24_MCU_CLR_MASK                             0x1
-#define IRQ24_MCU_CLR_MASK_SFT                         (0x1 << 24)
-#define IRQ23_MCU_CLR_SFT                              23
-#define IRQ23_MCU_CLR_MASK                             0x1
-#define IRQ23_MCU_CLR_MASK_SFT                         (0x1 << 23)
-#define IRQ22_MCU_CLR_SFT                              22
-#define IRQ22_MCU_CLR_MASK                             0x1
-#define IRQ22_MCU_CLR_MASK_SFT                         (0x1 << 22)
-#define IRQ21_MCU_CLR_SFT                              21
-#define IRQ21_MCU_CLR_MASK                             0x1
-#define IRQ21_MCU_CLR_MASK_SFT                         (0x1 << 21)
-#define IRQ20_MCU_CLR_SFT                              20
-#define IRQ20_MCU_CLR_MASK                             0x1
-#define IRQ20_MCU_CLR_MASK_SFT                         (0x1 << 20)
-#define IRQ19_MCU_CLR_SFT                              19
-#define IRQ19_MCU_CLR_MASK                             0x1
-#define IRQ19_MCU_CLR_MASK_SFT                         (0x1 << 19)
-#define IRQ18_MCU_CLR_SFT                              18
-#define IRQ18_MCU_CLR_MASK                             0x1
-#define IRQ18_MCU_CLR_MASK_SFT                         (0x1 << 18)
-#define IRQ17_MCU_CLR_SFT                              17
-#define IRQ17_MCU_CLR_MASK                             0x1
-#define IRQ17_MCU_CLR_MASK_SFT                         (0x1 << 17)
-#define IRQ16_MCU_CLR_SFT                              16
-#define IRQ16_MCU_CLR_MASK                             0x1
-#define IRQ16_MCU_CLR_MASK_SFT                         (0x1 << 16)
-#define IRQ15_MCU_CLR_SFT                              15
-#define IRQ15_MCU_CLR_MASK                             0x1
-#define IRQ15_MCU_CLR_MASK_SFT                         (0x1 << 15)
-#define IRQ14_MCU_CLR_SFT                              14
-#define IRQ14_MCU_CLR_MASK                             0x1
-#define IRQ14_MCU_CLR_MASK_SFT                         (0x1 << 14)
-#define IRQ13_MCU_CLR_SFT                              13
-#define IRQ13_MCU_CLR_MASK                             0x1
-#define IRQ13_MCU_CLR_MASK_SFT                         (0x1 << 13)
-#define IRQ12_MCU_CLR_SFT                              12
-#define IRQ12_MCU_CLR_MASK                             0x1
-#define IRQ12_MCU_CLR_MASK_SFT                         (0x1 << 12)
-#define IRQ11_MCU_CLR_SFT                              11
-#define IRQ11_MCU_CLR_MASK                             0x1
-#define IRQ11_MCU_CLR_MASK_SFT                         (0x1 << 11)
-#define IRQ10_MCU_CLR_SFT                              10
-#define IRQ10_MCU_CLR_MASK                             0x1
-#define IRQ10_MCU_CLR_MASK_SFT                         (0x1 << 10)
-#define IRQ9_MCU_CLR_SFT                               9
-#define IRQ9_MCU_CLR_MASK                              0x1
-#define IRQ9_MCU_CLR_MASK_SFT                          (0x1 << 9)
-#define IRQ8_MCU_CLR_SFT                               8
-#define IRQ8_MCU_CLR_MASK                              0x1
-#define IRQ8_MCU_CLR_MASK_SFT                          (0x1 << 8)
-#define IRQ7_MCU_CLR_SFT                               7
-#define IRQ7_MCU_CLR_MASK                              0x1
-#define IRQ7_MCU_CLR_MASK_SFT                          (0x1 << 7)
-#define IRQ6_MCU_CLR_SFT                               6
-#define IRQ6_MCU_CLR_MASK                              0x1
-#define IRQ6_MCU_CLR_MASK_SFT                          (0x1 << 6)
-#define IRQ5_MCU_CLR_SFT                               5
-#define IRQ5_MCU_CLR_MASK                              0x1
-#define IRQ5_MCU_CLR_MASK_SFT                          (0x1 << 5)
-#define IRQ4_MCU_CLR_SFT                               4
-#define IRQ4_MCU_CLR_MASK                              0x1
-#define IRQ4_MCU_CLR_MASK_SFT                          (0x1 << 4)
-#define IRQ3_MCU_CLR_SFT                               3
-#define IRQ3_MCU_CLR_MASK                              0x1
-#define IRQ3_MCU_CLR_MASK_SFT                          (0x1 << 3)
-#define IRQ2_MCU_CLR_SFT                               2
-#define IRQ2_MCU_CLR_MASK                              0x1
-#define IRQ2_MCU_CLR_MASK_SFT                          (0x1 << 2)
-#define IRQ1_MCU_CLR_SFT                               1
-#define IRQ1_MCU_CLR_MASK                              0x1
-#define IRQ1_MCU_CLR_MASK_SFT                          (0x1 << 1)
-#define IRQ0_MCU_CLR_SFT                               0
-#define IRQ0_MCU_CLR_MASK                              0x1
-#define IRQ0_MCU_CLR_MASK_SFT                          (0x1 << 0)
-
-/* AFE_IRQ_MCU_EN */
-#define IRQ31_MCU_EN_SFT                               31
-#define IRQ30_MCU_EN_SFT                               30
-#define IRQ29_MCU_EN_SFT                               29
-#define IRQ28_MCU_EN_SFT                               28
-#define IRQ27_MCU_EN_SFT                               27
-#define IRQ26_MCU_EN_SFT                               26
-#define IRQ25_MCU_EN_SFT                               25
-#define IRQ24_MCU_EN_SFT                               24
-#define IRQ23_MCU_EN_SFT                               23
-#define IRQ22_MCU_EN_SFT                               22
-#define IRQ21_MCU_EN_SFT                               21
-#define IRQ20_MCU_EN_SFT                               20
-#define IRQ19_MCU_EN_SFT                               19
-#define IRQ18_MCU_EN_SFT                               18
-#define IRQ17_MCU_EN_SFT                               17
-#define IRQ16_MCU_EN_SFT                               16
-#define IRQ15_MCU_EN_SFT                               15
-#define IRQ14_MCU_EN_SFT                               14
-#define IRQ13_MCU_EN_SFT                               13
-#define IRQ12_MCU_EN_SFT                               12
-#define IRQ11_MCU_EN_SFT                               11
-#define IRQ10_MCU_EN_SFT                               10
-#define IRQ9_MCU_EN_SFT                                9
-#define IRQ8_MCU_EN_SFT                                8
-#define IRQ7_MCU_EN_SFT                                7
-#define IRQ6_MCU_EN_SFT                                6
-#define IRQ5_MCU_EN_SFT                                5
-#define IRQ4_MCU_EN_SFT                                4
-#define IRQ3_MCU_EN_SFT                                3
-#define IRQ2_MCU_EN_SFT                                2
-#define IRQ1_MCU_EN_SFT                                1
-#define IRQ0_MCU_EN_SFT                                0
-
-/* AFE_IRQ_MCU_SCP_EN */
-#define IRQ31_MCU_SCP_EN_SFT                           31
-#define IRQ30_MCU_SCP_EN_SFT                           30
-#define IRQ29_MCU_SCP_EN_SFT                           29
-#define IRQ28_MCU_SCP_EN_SFT                           28
-#define IRQ27_MCU_SCP_EN_SFT                           27
-#define IRQ26_MCU_SCP_EN_SFT                           26
-#define IRQ25_MCU_SCP_EN_SFT                           25
-#define IRQ24_MCU_SCP_EN_SFT                           24
-#define IRQ23_MCU_SCP_EN_SFT                           23
-#define IRQ22_MCU_SCP_EN_SFT                           22
-#define IRQ21_MCU_SCP_EN_SFT                           21
-#define IRQ20_MCU_SCP_EN_SFT                           20
-#define IRQ19_MCU_SCP_EN_SFT                           19
-#define IRQ18_MCU_SCP_EN_SFT                           18
-#define IRQ17_MCU_SCP_EN_SFT                           17
-#define IRQ16_MCU_SCP_EN_SFT                           16
-#define IRQ15_MCU_SCP_EN_SFT                           15
-#define IRQ14_MCU_SCP_EN_SFT                           14
-#define IRQ13_MCU_SCP_EN_SFT                           13
-#define IRQ12_MCU_SCP_EN_SFT                           12
-#define IRQ11_MCU_SCP_EN_SFT                           11
-#define IRQ10_MCU_SCP_EN_SFT                           10
-#define IRQ9_MCU_SCP_EN_SFT                            9
-#define IRQ8_MCU_SCP_EN_SFT                            8
-#define IRQ7_MCU_SCP_EN_SFT                            7
-#define IRQ6_MCU_SCP_EN_SFT                            6
-#define IRQ5_MCU_SCP_EN_SFT                            5
-#define IRQ4_MCU_SCP_EN_SFT                            4
-#define IRQ3_MCU_SCP_EN_SFT                            3
-#define IRQ2_MCU_SCP_EN_SFT                            2
-#define IRQ1_MCU_SCP_EN_SFT                            1
-#define IRQ0_MCU_SCP_EN_SFT                            0
-
-/* AFE_IRQ_MCU_DSP_EN */
-#define IRQ31_MCU_DSP_EN_SFT                           31
-#define IRQ30_MCU_DSP_EN_SFT                           30
-#define IRQ29_MCU_DSP_EN_SFT                           29
-#define IRQ28_MCU_DSP_EN_SFT                           28
-#define IRQ27_MCU_DSP_EN_SFT                           27
-#define IRQ26_MCU_DSP_EN_SFT                           26
-#define IRQ25_MCU_DSP_EN_SFT                           25
-#define IRQ24_MCU_DSP_EN_SFT                           24
-#define IRQ23_MCU_DSP_EN_SFT                           23
-#define IRQ22_MCU_DSP_EN_SFT                           22
-#define IRQ21_MCU_DSP_EN_SFT                           21
-#define IRQ20_MCU_DSP_EN_SFT                           20
-#define IRQ19_MCU_DSP_EN_SFT                           19
-#define IRQ18_MCU_DSP_EN_SFT                           18
-#define IRQ17_MCU_DSP_EN_SFT                           17
-#define IRQ16_MCU_DSP_EN_SFT                           16
-#define IRQ15_MCU_DSP_EN_SFT                           15
-#define IRQ14_MCU_DSP_EN_SFT                           14
-#define IRQ13_MCU_DSP_EN_SFT                           13
-#define IRQ12_MCU_DSP_EN_SFT                           12
-#define IRQ11_MCU_DSP_EN_SFT                           11
-#define IRQ10_MCU_DSP_EN_SFT                           10
-#define IRQ9_MCU_DSP_EN_SFT                            9
-#define IRQ8_MCU_DSP_EN_SFT                            8
-#define IRQ7_MCU_DSP_EN_SFT                            7
-#define IRQ6_MCU_DSP_EN_SFT                            6
-#define IRQ5_MCU_DSP_EN_SFT                            5
-#define IRQ4_MCU_DSP_EN_SFT                            4
-#define IRQ3_MCU_DSP_EN_SFT                            3
-#define IRQ2_MCU_DSP_EN_SFT                            2
-#define IRQ1_MCU_DSP_EN_SFT                            1
-#define IRQ0_MCU_DSP_EN_SFT                            0
-
-#define AFE_IRQ_STATUS_BITS 0x87FFFFFF
-#define AFE_IRQ_CNT_SHIFT 0
-#define AFE_IRQ_CNT_MASK 0x3ffff
-
-#endif
diff --git a/src/platform/mt8186/include/platform/platform.h b/src/platform/mt8186/include/platform/platform.h
deleted file mode 100644
index 187f0fa5e6a2..000000000000
--- a/src/platform/mt8186/include/platform/platform.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2022 MediaTek. All rights reserved.
- *
- * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
- *         Tinghan Shen <tinghan.shen@mediatek.com>
- */
-
-#ifdef __SOF_PLATFORM_H__
-
-#ifndef __PLATFORM_PLATFORM_H__
-#define __PLATFORM_PLATFORM_H__
-
-#if !defined(__ASSEMBLER__) && !defined(LINKER)
-
-#include <sof/lib/mailbox.h>
-#include <stddef.h>
-#include <stdint.h>
-
-struct ll_schedule_domain;
-struct timer;
-
-#define PLATFORM_DEFAULT_CLOCK CLK_CPU(0)
-#define LPSRAM_SIZE 16384
-
-/* IPC Interrupt */
-#define PLATFORM_IPC_INTERRUPT MTK_DSP_IRQ_MAILBOX
-#define PLATFORM_IPC_INTERRUPT_NAME NULL
-
-/* Host page size */
-#define HOST_PAGE_SIZE 4096
-#define PLATFORM_PAGE_TABLE_SIZE 256
-
-/* pipeline IRQ */
-#define PLATFORM_SCHEDULE_IRQ MTK_DSP_IRQ_SW
-#define PLATFORM_SCHEDULE_IRQ_NAME NULL
-
-/* Platform stream capabilities */
-#define PLATFORM_MAX_CHANNELS 4
-#define PLATFORM_MAX_STREAMS 5
-
-/* local buffer size of DMA tracing */
-#define DMA_TRACE_LOCAL_SIZE HOST_PAGE_SIZE
-
-/* trace bytes flushed during panic */
-#define DMA_FLUSH_TRACE_SIZE (MAILBOX_TRACE_SIZE >> 2)
-
-/* the interval of DMA trace copying */
-#define DMA_TRACE_PERIOD 500000
-
-/*
- * the interval of reschedule DMA trace copying in special case like half
- * fullness of local DMA trace buffer
- */
-#define DMA_TRACE_RESCHEDULE_TIME 100
-
-/* DSP default delay in cycles */
-#define PLATFORM_DEFAULT_DELAY 12
-
-#define SRAM_REG_FW_STATUS 0x4
-
-/* Platform defined panic code */
-static inline void platform_panic(uint32_t p)
-{
-	/* Store the error code in the debug box so the
-	 * application processor can pick it up. Takes up 4 bytes
-	 * from the debug box.
-	 */
-	mailbox_sw_reg_write(SRAM_REG_FW_STATUS, p);
-
-	/* Notify application processor */
-	trigger_irq_to_host_req();
-}
-
-/**
- * \brief Platform specific CPU entering idle.
- * May be power-optimized using platform specific capabilities.
- * @param level Interrupt level.
- */
-void platform_wait_for_interrupt(int level);
-
-extern intptr_t _module_init_start;
-extern intptr_t _module_init_end;
-#endif
-
-#endif /* __PLATFORM_PLATFORM_H__ */
-
-#else
-
-#error "This file shouldn't be included from outside of sof/platform.h"
-
-#endif /* __SOF_PLATFORM_H__ */
diff --git a/src/platform/mt8186/include/platform/trace/trace.h b/src/platform/mt8186/include/platform/trace/trace.h
deleted file mode 100644
index 393530083efb..000000000000
--- a/src/platform/mt8186/include/platform/trace/trace.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2022 MediaTek. All rights reserved.
- *
- * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
- *         Tinghan Shen <tinghan.shen@mediatek.com>
- */
-
-#ifdef __SOF_TRACE_TRACE_H__
-
-#ifndef __PLATFORM_TRACE_TRACE_H__
-#define __PLATFORM_TRACE_TRACE_H__
-
-#include <sof/lib/mailbox.h>
-#include <sof/lib/memory.h>
-#include <sof/lib/io.h>
-#include <platform/drivers/mt_reg_base.h>
-
-#define platform_trace_point(__x)
-
-#endif /* __PLATFORM_TRACE_TRACE_H__ */
-
-#else
-
-#error "This file shouldn't be included from outside of sof/trace/trace.h"
-
-#endif /* __SOF_TRACE_TRACE_H__ */
diff --git a/src/platform/mt8186/lib/CMakeLists.txt b/src/platform/mt8186/lib/CMakeLists.txt
deleted file mode 100644
index ef71f8eea6cd..000000000000
--- a/src/platform/mt8186/lib/CMakeLists.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-
-add_local_sources(sof
-	clk.c
-	dma.c
-	memory.c
-	dai.c
-)
diff --git a/src/platform/mt8186/lib/clk.c b/src/platform/mt8186/lib/clk.c
deleted file mode 100644
index 21bf786963ac..000000000000
--- a/src/platform/mt8186/lib/clk.c
+++ /dev/null
@@ -1,154 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-/*
- * Copyright(c) 2022 MediaTek. All rights reserved.
- *
- * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
- *         Tinghan Shen <tinghan.shen@mediatek.com>
- */
-
-#include <platform/drivers/mt_reg_base.h>
-#include <rtos/clk.h>
-#include <rtos/wait.h>
-#include <sof/common.h>
-#include <sof/lib/cpu.h>
-#include <sof/lib/io.h>
-#include <sof/lib/memory.h>
-#include <sof/lib/notifier.h>
-#include <sof/lib/uuid.h>
-#include <rtos/sof.h>
-#include <sof/trace/trace.h>
-
-SOF_DEFINE_REG_UUID(clkdrv_mt8186);
-
-/* unused with Zephyr, generates no output */
-DECLARE_TR_CTX(clkdrv_tr, SOF_UUID(clkdrv_mt8186_uuid), LOG_LEVEL_INFO);
-
-/* default voltage is 0.8V */
-const struct freq_table platform_cpu_freq[] = {
-	{  26000000, 26000},
-	{ 300000000, 26000},
-	{ 400000000, 26000},
-};
-
-STATIC_ASSERT(ARRAY_SIZE(platform_cpu_freq) == NUM_CPU_FREQ,
-	      invalid_number_of_cpu_frequencies);
-
-static struct clock_info platform_clocks_info[NUM_CLOCKS];
-
-static void clk_dsppll_enable(uint32_t value)
-{
-	tr_dbg(&clkdrv_tr, "%d\n", value);
-
-	switch (value) {
-	case ADSP_CLK_PLL_300M:
-		io_reg_write(MTK_ADSPPLL_CON1, MTK_PLL_DIV_RATIO_300M);
-		break;
-	case ADSP_CLK_PLL_400M:
-		io_reg_write(MTK_ADSPPLL_CON1, MTK_PLL_DIV_RATIO_400M);
-		break;
-	default:
-		tr_err(&clkdrv_tr, "invalid dsppll: %d\n", value);
-		return;
-	}
-
-	io_reg_update_bits(MTK_ADSPPLL_CON3, MTK_PLL_PWR_ON, MTK_PLL_PWR_ON);
-	wait_delay_us(20);
-	io_reg_update_bits(MTK_ADSPPLL_CON3, MTK_PLL_ISO_EN, 0);
-	wait_delay_us(1);
-	io_reg_update_bits(MTK_ADSPPLL_CON0, MTK_PLL_BASE_EN, MTK_PLL_BASE_EN);
-	wait_delay_us(20);
-}
-
-static void clk_dsppll_disable(void)
-{
-	tr_dbg(&clkdrv_tr, "entry");
-
-	io_reg_update_bits(MTK_ADSPPLL_CON0, MTK_PLL_BASE_EN, 0);
-	wait_delay_us(1);
-	io_reg_update_bits(MTK_ADSPPLL_CON3, MTK_PLL_ISO_EN, MTK_PLL_ISO_EN);
-	wait_delay_us(1);
-	io_reg_update_bits(MTK_ADSPPLL_CON3, MTK_PLL_PWR_ON, 0);
-}
-
-static void set_mux_adsp_sel(uint32_t value)
-{
-	io_reg_write(MTK_CLK_CFG_11_CLR, MTK_CLK_ADSP_MASK << MTK_CLK_ADSP_OFFSET);
-	io_reg_write(MTK_CLK_CFG_11_SET, value << MTK_CLK_ADSP_OFFSET);
-	io_reg_write(MTK_CLK_CFG_UPDATE, MTK_CLK_CFG_ADSP_UPDATE);
-
-	tr_dbg(&clkdrv_tr, "adsp_clk_mux=%x, CLK_CFG_11=0x%08x\n",
-	       value, io_reg_read(MTK_CLK_CFG_11));
-}
-
-static void set_mux_adsp_bus_src_sel(uint32_t value)
-{
-	io_reg_write(MTK_ADSP_BUS_SRC, value);
-	io_reg_write(MTK_ADSP_CLK_BUS_UPDATE, MTK_ADSP_CLK_BUS_UPDATE_BIT);
-	wait_delay_us(1);
-
-	tr_dbg(&clkdrv_tr, "adsp_bus_mux=%x, MTK_ADSP_BUS_SRC=0x%08x\n",
-	       value, io_reg_read(MTK_ADSP_BUS_SRC));
-}
-
-static void set_mux_adsp_bus_sel(uint32_t value)
-{
-	io_reg_write(MTK_CLK_CFG_15_CLR, MTK_CLK_ADSP_BUS_MASK << MTK_CLK_ADSP_BUS_OFFSET);
-	io_reg_write(MTK_CLK_CFG_15_SET, value << MTK_CLK_ADSP_BUS_OFFSET);
-	io_reg_write(MTK_CLK_CFG_UPDATE, MTK_CLK_CFG_ADSP_BUS_UPDATE);
-
-	tr_dbg(&clkdrv_tr, "adsp_bus_clk_mux=%x, CLK_CFG_15=0x%08x\n",
-	       value, io_reg_read(MTK_CLK_CFG_15));
-}
-
-static int clock_platform_set_dsp_freq(int clock, int freq_idx)
-{
-	switch (freq_idx) {
-	case ADSP_CLK_26M:
-		set_mux_adsp_bus_sel(MTK_CLK_ADSP_BUS_26M);
-		set_mux_adsp_bus_src_sel(MTK_ADSP_CLK_BUS_SRC_LOCAL);
-		set_mux_adsp_sel(MTK_CLK_ADSP_26M);
-		clk_dsppll_disable();
-		break;
-	case ADSP_CLK_PLL_300M:
-		clock_platform_set_dsp_freq(clock, ADSP_CLK_26M);
-		clk_dsppll_enable(ADSP_CLK_PLL_300M);
-		set_mux_adsp_sel(MTK_CLK_ADSP_DSPPLL);
-		set_mux_adsp_bus_src_sel(MTK_ADSP_CLK_BUS_SRC_EMI);
-		set_mux_adsp_bus_sel(MTK_CLK_ADSP_BUS_26M);
-		break;
-	case ADSP_CLK_PLL_400M:
-		clock_platform_set_dsp_freq(clock, ADSP_CLK_26M);
-		clk_dsppll_enable(ADSP_CLK_PLL_400M);
-		set_mux_adsp_sel(MTK_CLK_ADSP_DSPPLL);
-		set_mux_adsp_bus_src_sel(MTK_ADSP_CLK_BUS_SRC_EMI);
-		set_mux_adsp_bus_sel(MTK_CLK_ADSP_BUS_26M);
-		break;
-	default:
-		clock_platform_set_dsp_freq(clock, ADSP_CLK_26M);
-		tr_err(&clkdrv_tr, "unknown freq index %x\n", freq_idx);
-		break;
-	}
-
-	return 0;
-}
-
-void platform_clock_init(struct sof *sof)
-{
-	int i;
-
-	sof->clocks = platform_clocks_info;
-
-	for (i = 0; i < CONFIG_CORE_COUNT; i++) {
-		sof->clocks[i] = (struct clock_info){
-			.freqs_num = NUM_CPU_FREQ,
-			.freqs = platform_cpu_freq,
-			.default_freq_idx = CPU_DEFAULT_IDX,
-			.current_freq_idx = CPU_DEFAULT_IDX,
-			.notification_id = NOTIFIER_ID_CPU_FREQ,
-			.notification_mask = NOTIFIER_TARGET_CORE_MASK(i),
-			.set_freq = clock_platform_set_dsp_freq,
-		};
-	}
-
-	clock_set_freq(CLK_CPU(cpu_get_id()), CLK_MAX_CPU_HZ);
-}
diff --git a/src/platform/mt8186/lib/dai.c b/src/platform/mt8186/lib/dai.c
deleted file mode 100644
index a45056846a2e..000000000000
--- a/src/platform/mt8186/lib/dai.c
+++ /dev/null
@@ -1,57 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-/*
- * Copyright(c) 2022 MediaTek. All rights reserved.
- *
- * Author: Chunxu Li <chunxu.li@mediatek.com>
- */
-
-#include <sof/common.h>
-#include <sof/lib/dai.h>
-#include <sof/lib/memory.h>
-#include <rtos/sof.h>
-#include <rtos/spinlock.h>
-#include <ipc/dai.h>
-#include <ipc/stream.h>
-
-#include <sof/drivers/afe-dai.h>
-#include <mt8186-afe-common.h>
-
-static int afe_dai_handshake[MT8186_DAI_NUM] = {
-	AFE_HANDSHAKE(MT8186_AFE_IO_I2S1, MT8186_IRQ_0, MT8186_MEMIF_DL1),
-	AFE_HANDSHAKE(MT8186_AFE_IO_I2S3, MT8186_IRQ_1, MT8186_MEMIF_DL2),
-	AFE_HANDSHAKE(MT8186_AFE_IO_UL_SRC1, MT8186_IRQ_10, MT8186_MEMIF_UL1),
-	AFE_HANDSHAKE(MT8186_AFE_IO_I2S0, MT8186_IRQ_12, MT8186_MEMIF_UL2),
-};
-
-static struct dai afe_dai[MT8186_DAI_NUM];
-
-const struct dai_type_info dti[] = {
-	{
-		.type = SOF_DAI_MEDIATEK_AFE,
-		.dai_array = afe_dai,
-		.num_dais = ARRAY_SIZE(afe_dai),
-	},
-};
-
-const struct dai_info lib_dai = {
-	.dai_type_array = dti,
-	.num_dai_types = ARRAY_SIZE(dti),
-};
-
-int dai_init(struct sof *sof)
-{
-	int i;
-
-	/* initialize spin locks early to enable ref counting */
-	for (i = 0; i < ARRAY_SIZE(afe_dai); i++) {
-		k_spinlock_init(&afe_dai[i].lock);
-		afe_dai[i].index = AFE_HS_GET_DAI(afe_dai_handshake[i]);
-		afe_dai[i].drv = &afe_dai_driver;
-		/* TODO, fifo[0] change to target playback or capture */
-		afe_dai[i].plat_data.fifo[0].handshake = afe_dai_handshake[i];
-	}
-
-	sof->dai_info = &lib_dai;
-
-	return 0;
-}
diff --git a/src/platform/mt8186/lib/dma.c b/src/platform/mt8186/lib/dma.c
deleted file mode 100644
index a8e3308367fc..000000000000
--- a/src/platform/mt8186/lib/dma.c
+++ /dev/null
@@ -1,60 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-/*
- * Copyright(c) 2022 MediaTek. All rights reserved.
- *
- * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
- *         Tinghan Shen <tinghan.shen@mediatek.com>
- */
-
-#include <sof/common.h>
-#include <sof/drivers/afe-memif.h>
-#include <rtos/interrupt.h>
-#include <sof/lib/dma.h>
-#include <sof/lib/memory.h>
-#include <rtos/sof.h>
-#include <rtos/spinlock.h>
-
-#include <mt8186-afe-regs.h>
-#include <mt8186-afe-common.h>
-
-extern const struct dma_ops dummy_dma_ops;
-
-static struct dma dma[PLATFORM_NUM_DMACS] = {
-{
-	.plat_data = {
-		.id		= DMA_ID_HOST,
-		.dir		= DMA_DIR_HMEM_TO_LMEM | DMA_DIR_LMEM_TO_HMEM,
-		.devs		= DMA_DEV_HOST,
-		.channels	= 16,
-	},
-	.ops	= &dummy_dma_ops,
-},
-{
-	.plat_data = {
-		.id		= DMA_ID_AFE_MEMIF,
-		.dir		= DMA_DIR_MEM_TO_DEV | DMA_DIR_DEV_TO_MEM,
-		.devs		= DMA_DEV_AFE_MEMIF,
-		.base		= AFE_BASE_ADDR,
-		.channels	= MT8186_MEMIF_NUM,
-	},
-	.ops	= &memif_ops,
-},
-};
-
-static const struct dma_info lib_dma = {
-	.dma_array = cache_to_uncache_init((struct dma *)dma),
-	.num_dmas = ARRAY_SIZE(dma)
-};
-
-int dmac_init(struct sof *sof)
-{
-	int i;
-
-	/* early lock initialization for ref counting */
-	for (i = 0; i < ARRAY_SIZE(dma); i++)
-		k_spinlock_init(&dma[i].lock);
-
-	sof->dma_info = &lib_dma;
-
-	return 0;
-}
diff --git a/src/platform/mt8186/lib/memory.c b/src/platform/mt8186/lib/memory.c
deleted file mode 100644
index beae268b7f6f..000000000000
--- a/src/platform/mt8186/lib/memory.c
+++ /dev/null
@@ -1,102 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-/*
- * Copyright(c) 2022 MediaTek. All rights reserved.
- *
- * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
- *         Tinghan Shen <tinghan.shen@mediatek.com>
- */
-
-#include <sof/common.h>
-#include <sof/lib/mm_heap.h>
-#include <sof/lib/memory.h>
-#include <rtos/sof.h>
-#include <ipc/topology.h>
-
-/* Heap blocks for system runtime */
-static struct block_hdr sys_rt_block64[HEAP_SYS_RT_COUNT64];
-static struct block_hdr sys_rt_block512[HEAP_SYS_RT_COUNT512];
-static struct block_hdr sys_rt_block1024[HEAP_SYS_RT_COUNT1024];
-
-/* Heap memory for system runtime */
-static struct block_map sys_rt_heap_map[] = {
-	BLOCK_DEF(64, HEAP_SYS_RT_COUNT64, sys_rt_block64),
-	BLOCK_DEF(512, HEAP_SYS_RT_COUNT512, sys_rt_block512),
-	BLOCK_DEF(1024, HEAP_SYS_RT_COUNT1024, sys_rt_block1024),
-};
-
-/* Heap blocks for modules */
-static struct block_hdr mod_block16[HEAP_RT_COUNT16];
-static struct block_hdr mod_block32[HEAP_RT_COUNT32];
-static struct block_hdr mod_block64[HEAP_RT_COUNT64];
-static struct block_hdr mod_block128[HEAP_RT_COUNT128];
-static struct block_hdr mod_block256[HEAP_RT_COUNT256];
-static struct block_hdr mod_block512[HEAP_RT_COUNT512];
-static struct block_hdr mod_block1024[HEAP_RT_COUNT1024];
-static struct block_hdr mod_block2048[HEAP_RT_COUNT2048];
-static struct block_hdr mod_block4096[HEAP_RT_COUNT4096];
-
-/* Heap memory map for modules */
-static struct block_map rt_heap_map[] = {
-	BLOCK_DEF(16, HEAP_RT_COUNT16, mod_block16),
-	BLOCK_DEF(32, HEAP_RT_COUNT32, mod_block32),
-	BLOCK_DEF(64, HEAP_RT_COUNT64, mod_block64),
-	BLOCK_DEF(128, HEAP_RT_COUNT128, mod_block128),
-	BLOCK_DEF(256, HEAP_RT_COUNT256, mod_block256),
-	BLOCK_DEF(512, HEAP_RT_COUNT512, mod_block512),
-	BLOCK_DEF(1024, HEAP_RT_COUNT1024, mod_block1024),
-	BLOCK_DEF(2048, HEAP_RT_COUNT2048, mod_block2048),
-	BLOCK_DEF(4096, HEAP_RT_COUNT4096, mod_block4096),
-};
-
-/* Heap blocks for buffers */
-static struct block_hdr buf_block[HEAP_BUFFER_COUNT];
-
-/* Heap memory map for buffers */
-static struct block_map buf_heap_map[] = {
-	BLOCK_DEF(HEAP_BUFFER_BLOCK_SIZE, HEAP_BUFFER_COUNT, buf_block),
-};
-
-static struct mm memmap = {
-	.system[0] = {
-		.heap = HEAP_SYSTEM_BASE,
-		.size = HEAP_SYSTEM_SIZE,
-		.info = {.free = HEAP_SYSTEM_SIZE,},
-		.caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_CACHE |
-			SOF_MEM_CAPS_DMA,
-	},
-	.system_runtime[0] = {
-		.blocks = ARRAY_SIZE(sys_rt_heap_map),
-		.map = sys_rt_heap_map,
-		.heap = HEAP_SYS_RUNTIME_BASE,
-		.size = HEAP_SYS_RUNTIME_SIZE,
-		.info = {.free = HEAP_SYS_RUNTIME_SIZE,},
-		.caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_CACHE |
-			SOF_MEM_CAPS_DMA,
-	},
-	.runtime[0] = {
-		.blocks = ARRAY_SIZE(rt_heap_map),
-		.map = rt_heap_map,
-		.heap = HEAP_RUNTIME_BASE,
-		.size = HEAP_RUNTIME_SIZE,
-		.info = {.free = HEAP_RUNTIME_SIZE,},
-		.caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_CACHE |
-			SOF_MEM_CAPS_DMA,
-	},
-	.buffer[0] = {
-		.blocks = ARRAY_SIZE(buf_heap_map),
-		.map = buf_heap_map,
-		.heap = HEAP_BUFFER_BASE,
-		.size = HEAP_BUFFER_SIZE,
-		.info = {.free = HEAP_BUFFER_SIZE,},
-		.caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_CACHE |
-			SOF_MEM_CAPS_DMA,
-	},
-	.total = {.free = HEAP_SYSTEM_SIZE + HEAP_SYS_RUNTIME_SIZE +
-			HEAP_RUNTIME_SIZE + HEAP_BUFFER_SIZE,},
-};
-
-void platform_init_memmap(struct sof *sof)
-{
-	/* memmap has been initialized statically as a part of .data */
-	sof->memory_map = &memmap;
-}
diff --git a/src/platform/mt8186/mt8186.x.in b/src/platform/mt8186/mt8186.x.in
deleted file mode 100644
index 2aa7c480c06e..000000000000
--- a/src/platform/mt8186/mt8186.x.in
+++ /dev/null
@@ -1,538 +0,0 @@
-/*
- * Linker Script for mt8186 MediaTek
- *
- * This script is run through the GNU C preprocessor to align the memory
- * offsets with headers.
- *
- * Use spaces for formatting as cpp ignore tab sizes.
- */
-
-
-#include <sof/lib/memory.h>
-#include <xtensa/config/core-isa.h>
-
-#if CONFIG_MEDIATEK_DRAM_IMAGE
-#define IMAGE_LOC sof_dram
-#else
-#define IMAGE_LOC sof_sram
-#endif
-
-OUTPUT_ARCH(xtensa)
-
-MEMORY
-{
-  vector_reset_text :
-        org = XCHAL_RESET_VECTOR0_PADDR,
-        len = SOF_MEM_RESET_TEXT_SIZE
-  vector_reset_lit :
-        org = XCHAL_RESET_VECTOR0_PADDR + SOF_MEM_RESET_TEXT_SIZE,
-        len = SOF_MEM_RESET_LIT_SIZE
-  vector_base_text :
-        org = XCHAL_VECBASE_RESET_PADDR,
-        len = SOF_MEM_VECBASE_LIT_SIZE
-  vector_int2_lit :
-        org = XCHAL_INTLEVEL2_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
-        len = SOF_MEM_VECT_LIT_SIZE
-  vector_int2_text :
-        org = XCHAL_INTLEVEL2_VECTOR_PADDR,
-        len = SOF_MEM_VECT_TEXT_SIZE
-  vector_int3_lit :
-        org = XCHAL_INTLEVEL3_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
-        len = SOF_MEM_VECT_LIT_SIZE
-  vector_int3_text :
-        org = XCHAL_INTLEVEL3_VECTOR_PADDR,
-        len = SOF_MEM_VECT_TEXT_SIZE
-  vector_int4_lit :
-        org = XCHAL_INTLEVEL4_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
-        len = SOF_MEM_VECT_LIT_SIZE
-  vector_int4_text :
-        org = XCHAL_INTLEVEL4_VECTOR_PADDR,
-        len = SOF_MEM_VECT_TEXT_SIZE
-  vector_int5_lit :
-        org = XCHAL_INTLEVEL5_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
-        len = SOF_MEM_VECT_LIT_SIZE
-  vector_int5_text :
-        org = XCHAL_INTLEVEL5_VECTOR_PADDR,
-        len = SOF_MEM_VECT_TEXT_SIZE
-  vector_kernel_lit :
-        org = XCHAL_KERNEL_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
-        len = SOF_MEM_VECT_LIT_SIZE
-  vector_kernel_text :
-        org = XCHAL_KERNEL_VECTOR_PADDR,
-        len = SOF_MEM_VECT_TEXT_SIZE
-  vector_user_lit :
-        org = XCHAL_USER_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
-        len = SOF_MEM_VECT_LIT_SIZE
-  vector_user_text :
-        org = XCHAL_USER_VECTOR_PADDR,
-        len = SOF_MEM_VECT_TEXT_SIZE
-  vector_double_lit :
-        org = XCHAL_DOUBLEEXC_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
-        len = SOF_MEM_VECT_LIT_SIZE
-  vector_double_text :
-        org = XCHAL_DOUBLEEXC_VECTOR_PADDR,
-        len = SOF_MEM_VECT_TEXT_SIZE
-  sof_sram :
-        org = SRAM_START,
-        len = SRAM_SIZE
-  sof_dram :
-        org = SOF_DRAM_BASE,
-        len = SOF_DRAM_SIZE
-  system_heap :
-        org = HEAP_SYSTEM_BASE,
-        len = HEAP_SYSTEM_SIZE
-  system_runtime_heap :
-        org = HEAP_SYS_RUNTIME_BASE,
-        len = HEAP_SYS_RUNTIME_SIZE
-  runtime_heap :
-        org = HEAP_RUNTIME_BASE,
-        len = HEAP_RUNTIME_SIZE
-  buffer_heap :
-        org = HEAP_BUFFER_BASE,
-        len = HEAP_BUFFER_SIZE
-  sof_stack :
-        org = SOF_STACK_END,
-        len = SOF_STACK_BASE - SOF_STACK_END
-  static_uuid_entries_seg (!ari) :
-        org = UUID_ENTRY_ELF_BASE,
-        len = UUID_ENTRY_ELF_SIZE
-  static_log_entries_seg (!ari) :
-        org = LOG_ENTRY_ELF_BASE,
-        len = LOG_ENTRY_ELF_SIZE
-  fw_metadata_seg (!ari) :
-        org = EXT_MANIFEST_ELF_BASE,
-        len = EXT_MANIFEST_ELF_SIZE
-}
-
-PHDRS
-{
-  vector_reset_text_phdr PT_LOAD;
-  vector_reset_lit_phdr PT_LOAD;
-  vector_base_text_phdr PT_LOAD;
-  vector_base_lit_phdr PT_LOAD;
-  vector_int2_text_phdr PT_LOAD;
-  vector_int2_lit_phdr PT_LOAD;
-  vector_int3_text_phdr PT_LOAD;
-  vector_int3_lit_phdr PT_LOAD;
-  vector_int4_text_phdr PT_LOAD;
-  vector_int4_lit_phdr PT_LOAD;
-  vector_int5_text_phdr PT_LOAD;
-  vector_int5_lit_phdr PT_LOAD;
-  vector_kernel_text_phdr PT_LOAD;
-  vector_kernel_lit_phdr PT_LOAD;
-  vector_user_text_phdr PT_LOAD;
-  vector_user_lit_phdr PT_LOAD;
-  vector_double_text_phdr PT_LOAD;
-  vector_double_lit_phdr PT_LOAD;
-  sof_sram_phdr PT_LOAD;
-  system_heap_phdr PT_LOAD;
-  system_runtime_heap_phdr PT_LOAD;
-  runtime_heap_phdr PT_LOAD;
-  buffer_heap_phdr PT_LOAD;
-  sof_stack_phdr PT_LOAD;
-  static_uuid_entries_phdr PT_NOTE;
-  static_log_entries_phdr PT_NOTE;
-  metadata_entries_phdr PT_NOTE;
-}
-
-/*  Default entry point:  */
-ENTRY(_ResetVector)
-_rom_store_table = 0;
-
-/* ABI0 does not use Window base */
-PROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR);
-
-/* Various memory-map dependent cache attribute settings: */
-_memmap_cacheattr_wb_base = 0x00000100;
-_memmap_cacheattr_wt_base = 0x00000300;
-_memmap_cacheattr_bp_base = 0x00000400;
-_memmap_cacheattr_unused_mask = 0xFFFFF0FF;
-_memmap_cacheattr_wb_trapnull = 0x44444140;
-_memmap_cacheattr_wba_trapnull = 0x44444140;
-_memmap_cacheattr_wbna_trapnull = 0x44444240;
-_memmap_cacheattr_wt_trapnull = 0x44444340;
-_memmap_cacheattr_bp_trapnull = 0x44444440;
-_memmap_cacheattr_wb_strict = 0x00000100;
-_memmap_cacheattr_wt_strict = 0x00000300;
-_memmap_cacheattr_bp_strict = 0x00000400;
-_memmap_cacheattr_wb_allvalid = 0x44444144;
-_memmap_cacheattr_wt_allvalid = 0x44444344;
-_memmap_cacheattr_bp_allvalid = 0x44444444;
-PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);
-
-_EXT_MAN_ALIGN_ = 16;
-EXTERN(ext_man_fw_ver)
-
-SECTIONS
-{
-  .ResetVector.text : ALIGN(4)
-  {
-    _ResetVector_text_start = ABSOLUTE(.);
-    KEEP (*(.ResetVector.text))
-    _ResetVector_text_end = ABSOLUTE(.);
-  } >vector_reset_text :vector_reset_text_phdr
-
-  .ResetVector.literal : ALIGN(4)
-  {
-    _ResetVector_literal_start = ABSOLUTE(.);
-    *(.ResetVector.literal)
-    _ResetVector_literal_end = ABSOLUTE(.);
-  } >vector_reset_lit :vector_reset_lit_phdr
-
-  .WindowVectors.text : ALIGN(4)
-  {
-    _WindowVectors_text_start = ABSOLUTE(.);
-    KEEP (*(.WindowVectors.text))
-    _WindowVectors_text_end = ABSOLUTE(.);
-  } >vector_base_text :vector_base_text_phdr
-
-  .Level2InterruptVector.literal : ALIGN(4)
-  {
-    _Level2InterruptVector_literal_start = ABSOLUTE(.);
-    *(.Level2InterruptVector.literal)
-    _Level2InterruptVector_literal_end = ABSOLUTE(.);
-  } >vector_int2_lit :vector_int2_lit_phdr
-
-  .Level2InterruptVector.text : ALIGN(4)
-  {
-    _Level2InterruptVector_text_start = ABSOLUTE(.);
-    KEEP (*(.Level2InterruptVector.text))
-    _Level2InterruptVector_text_end = ABSOLUTE(.);
-  } >vector_int2_text :vector_int2_text_phdr
-
-  .Level3InterruptVector.literal : ALIGN(4)
-  {
-    _Level3InterruptVector_literal_start = ABSOLUTE(.);
-    *(.Level3InterruptVector.literal)
-    _Level3InterruptVector_literal_end = ABSOLUTE(.);
-  } >vector_int3_lit :vector_int3_lit_phdr
-
-  .Level3InterruptVector.text : ALIGN(4)
-  {
-    _Level3InterruptVector_text_start = ABSOLUTE(.);
-    KEEP (*(.Level3InterruptVector.text))
-    _Level3InterruptVector_text_end = ABSOLUTE(.);
-  } >vector_int3_text :vector_int3_text_phdr
-
-  .Level4InterruptVector.literal : ALIGN(4)
-  {
-    _Level4InterruptVector_literal_start = ABSOLUTE(.);
-    *(.Level4InterruptVector.literal)
-    _Level4InterruptVector_literal_end = ABSOLUTE(.);
-  } >vector_int4_lit :vector_int4_lit_phdr
-
-  .Level4InterruptVector.text : ALIGN(4)
-  {
-    _Level4InterruptVector_text_start = ABSOLUTE(.);
-    KEEP (*(.Level4InterruptVector.text))
-    _Level4InterruptVector_text_end = ABSOLUTE(.);
-  } >vector_int4_text :vector_int4_text_phdr
-
-  .DebugExceptionVector.literal : ALIGN(4)
-  {
-    _DebugExceptionVector_literal_start = ABSOLUTE(.);
-    *(.DebugExceptionVector.literal)
-    _DebugExceptionVector_literal_end = ABSOLUTE(.);
-  } >vector_int5_lit :vector_int5_lit_phdr
-
-  .DebugExceptionVector.text : ALIGN(4)
-  {
-    _DebugExceptionVector_text_start = ABSOLUTE(.);
-    KEEP (*(.DebugExceptionVector.text))
-    _DebugExceptionVector_text_end = ABSOLUTE(.);
-  } >vector_int5_text :vector_int5_text_phdr
-
-  .NMIExceptionVector.literal : ALIGN(4)
-  {
-    _NMIExceptionVector_literal_start = ABSOLUTE(.);
-    *(.NMIExceptionVector.literal)
-    _NMIExceptionVector_literal_end = ABSOLUTE(.);
-  } >vector_int5_lit :vector_int5_lit_phdr
-
-  .NMIExceptionVector.text : ALIGN(4)
-  {
-    _NMIExceptionVector_text_start = ABSOLUTE(.);
-    KEEP (*(.NMIExceptionVector.text))
-    _NMIExceptionVector_text_end = ABSOLUTE(.);
-  } >vector_int5_text :vector_int5_text_phdr
-
-  .KernelExceptionVector.literal : ALIGN(4)
-  {
-    _KernelExceptionVector_literal_start = ABSOLUTE(.);
-    *(.KernelExceptionVector.literal)
-    _KernelExceptionVector_literal_end = ABSOLUTE(.);
-  } >vector_kernel_lit :vector_kernel_lit_phdr
-
-  .KernelExceptionVector.text : ALIGN(4)
-  {
-    _KernelExceptionVector_text_start = ABSOLUTE(.);
-    KEEP (*(.KernelExceptionVector.text))
-    _KernelExceptionVector_text_end = ABSOLUTE(.);
-  } >vector_kernel_text :vector_kernel_text_phdr
-
-  .UserExceptionVector.literal : ALIGN(4)
-  {
-    _UserExceptionVector_literal_start = ABSOLUTE(.);
-    *(.UserExceptionVector.literal)
-    _UserExceptionVector_literal_end = ABSOLUTE(.);
-  } >vector_user_lit :vector_user_lit_phdr
-
-  .UserExceptionVector.text : ALIGN(4)
-  {
-    _UserExceptionVector_text_start = ABSOLUTE(.);
-    KEEP (*(.UserExceptionVector.text))
-    _UserExceptionVector_text_end = ABSOLUTE(.);
-  } >vector_user_text :vector_user_text_phdr
-
-  .DoubleExceptionVector.literal : ALIGN(4)
-  {
-    _DoubleExceptionVector_literal_start = ABSOLUTE(.);
-    *(.DoubleExceptionVector.literal)
-    _DoubleExceptionVector_literal_end = ABSOLUTE(.);
-  } >vector_double_lit :vector_double_lit_phdr
-
-  .DoubleExceptionVector.text : ALIGN(4)
-  {
-    _DoubleExceptionVector_text_start = ABSOLUTE(.);
-    KEEP (*(.DoubleExceptionVector.text))
-    _DoubleExceptionVector_text_end = ABSOLUTE(.);
-  } >vector_double_text :vector_double_text_phdr
-
-  .fw_ready : ALIGN(4)
-  {
-    KEEP (*(.fw_ready))
-    KEEP (*(.fw_ready_metadata))
-  } >IMAGE_LOC :sof_sram_phdr
-
-  .rodata : ALIGN(4)
-  {
-    _rodata_start = ABSOLUTE(.);
-    *(.rodata)
-    *(.rodata.*)
-    *(.gnu.linkonce.r.*)
-    *(.rodata1)
-    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);
-    KEEP (*(.xt_except_table))
-    KEEP (*(.gcc_except_table))
-    *(.gnu.linkonce.e.*)
-    *(.gnu.version_r)
-    KEEP (*(.eh_frame))
-    /*  C++ constructor and destructor tables, properly ordered:  */
-    KEEP (*crtbegin.o(.ctors))
-    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
-    KEEP (*(SORT(.ctors.*)))
-    KEEP (*(.ctors))
-    KEEP (*crtbegin.o(.dtors))
-    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
-    KEEP (*(SORT(.dtors.*)))
-    KEEP (*(.dtors))
-    /*  C++ exception handlers table:  */
-    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);
-    *(.xt_except_desc)
-    *(.gnu.linkonce.h.*)
-    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
-    *(.xt_except_desc_end)
-    *(.dynamic)
-    *(.gnu.version_d)
-    . = ALIGN(4);		/* this table MUST be 4-byte aligned */
-    _bss_table_start = ABSOLUTE(.);
-    LONG(_bss_start)
-    LONG(_bss_end)
-    _bss_table_end = ABSOLUTE(.);
-    _rodata_end = ABSOLUTE(.);
-  } >IMAGE_LOC :sof_sram_phdr
-
-  .module_init : ALIGN(4)
-  {
-   _module_init_start = ABSOLUTE(.);
-    *(*.initcall)
-    _module_init_end = ABSOLUTE(.);
-  } >IMAGE_LOC :sof_sram_phdr
-
-  .text : ALIGN(4)
-  {
-    _stext = .;
-    _text_start = ABSOLUTE(.);
-    *(.entry.text)
-    *(.init.literal)
-    KEEP(*(.init))
-    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
-    *(.fini.literal)
-    KEEP(*(.fini))
-    *(.gnu.version)
-    _text_end = ABSOLUTE(.);
-    _etext = .;
-  } >IMAGE_LOC :sof_sram_phdr
-
-  .reset.rodata : ALIGN(4)
-  {
-    _reset_rodata_start = ABSOLUTE(.);
-    *(.reset.rodata)
-    _reset_rodata_end = ABSOLUTE(.);
-  } >IMAGE_LOC :sof_sram_phdr
-
-
-  .data : ALIGN(4)
-  {
-    _data_start = ABSOLUTE(.);
-    *(.data)
-    *(.data.*)
-    *(.gnu.linkonce.d.*)
-    KEEP(*(.gnu.linkonce.d.*personality*))
-    *(.data1)
-    *(.sdata)
-    *(.sdata.*)
-    *(.gnu.linkonce.s.*)
-    *(.sdata2)
-    *(.sdata2.*)
-    *(.gnu.linkonce.s2.*)
-    KEEP(*(.jcr))
-    _trace_ctx_start = ABSOLUTE(.);
-    *(.trace_ctx)
-    _trace_ctx_end = ABSOLUTE(.);
-    _data_end = ABSOLUTE(.);
-  } >IMAGE_LOC :sof_sram_phdr
-
-  .lit4 : ALIGN(4)
-  {
-    _lit4_start = ABSOLUTE(.);
-    *(*.lit4)
-    *(.lit4.*)
-    *(.gnu.linkonce.lit4.*)
-    _lit4_end = ABSOLUTE(.);
-  } >IMAGE_LOC :sof_sram_phdr
-
-  .bss (NOLOAD) : ALIGN(8)
-  {
-    . = ALIGN (8);
-    _bss_start = ABSOLUTE(.);
-    *(.dynsbss)
-    *(.sbss)
-    *(.sbss.*)
-    *(.gnu.linkonce.sb.*)
-    *(.scommon)
-    *(.sbss2)
-    *(.sbss2.*)
-    *(.gnu.linkonce.sb2.*)
-    *(.dynbss)
-    *(.bss)
-    *(.bss.*)
-    *(.gnu.linkonce.b.*)
-    *(COMMON)
-    . = ALIGN (8);
-    _bss_end = ABSOLUTE(.);
-  } >IMAGE_LOC :sof_sram_phdr
-
-  /* stack */
-  _end = SOF_STACK_END;
-  PROVIDE(end = SOF_STACK_END);
-  _stack_sentry = SOF_STACK_END;
-  __stack = SOF_STACK_BASE;
-
-  .debug  0 :  { *(.debug) }
-  .line  0 :  { *(.line) }
-  .debug_srcinfo  0 :  { *(.debug_srcinfo) }
-  .debug_sfnames  0 :  { *(.debug_sfnames) }
-  .debug_aranges  0 :  { *(.debug_aranges) }
-  .debug_pubnames  0 :  { *(.debug_pubnames) }
-  .debug_info  0 :  { *(.debug_info) }
-  .debug_abbrev  0 :  { *(.debug_abbrev) }
-  .debug_line  0 :  { *(.debug_line) }
-  .debug_frame  0 :  { *(.debug_frame) }
-  .debug_str  0 :  { *(.debug_str) }
-  .debug_loc  0 :  { *(.debug_loc) }
-  .debug_macinfo  0 :  { *(.debug_macinfo) }
-  .debug_weaknames  0 :  { *(.debug_weaknames) }
-  .debug_funcnames  0 :  { *(.debug_funcnames) }
-  .debug_typenames  0 :  { *(.debug_typenames) }
-  .debug_varnames  0 :  { *(.debug_varnames) }
-
-  .xt.insn 0 :
-  {
-    KEEP (*(.xt.insn))
-    KEEP (*(.gnu.linkonce.x.*))
-  }
-  .xt.prop 0 :
-  {
-    KEEP (*(.xt.prop))
-    KEEP (*(.xt.prop.*))
-    KEEP (*(.gnu.linkonce.prop.*))
-  }
-  .xt.lit 0 :
-  {
-    KEEP (*(.xt.lit))
-    KEEP (*(.xt.lit.*))
-    KEEP (*(.gnu.linkonce.p.*))
-  }
-  .xt.profile_range 0 :
-  {
-    KEEP (*(.xt.profile_range))
-    KEEP (*(.gnu.linkonce.profile_range.*))
-  }
-  .xt.profile_ranges 0 :
-  {
-    KEEP (*(.xt.profile_ranges))
-    KEEP (*(.gnu.linkonce.xt.profile_ranges.*))
-  }
-  .xt.profile_files 0 :
-  {
-    KEEP (*(.xt.profile_files))
-    KEEP (*(.gnu.linkonce.xt.profile_files.*))
-  }
-
-  .system_heap (NOLOAD) : ALIGN(8)
-  {
-    . = ALIGN (32);
-    _system_heap_start = ABSOLUTE(.);
-    . = . + HEAP_SYSTEM_SIZE;
-    _system_heap_end = ABSOLUTE(.);
-  } >system_heap :system_heap_phdr
-
-  .system_runtime_heap (NOLOAD) : ALIGN(8)
-  {
-    . = ALIGN (HEAP_BUF_ALIGNMENT);
-    _system_runtime_heap_start = ABSOLUTE(.);
-    . = . + HEAP_SYS_RUNTIME_SIZE;
-    _system_runtime_heap_end = ABSOLUTE(.);
-  } >system_runtime_heap :system_runtime_heap_phdr
-
-  .runtime_heap (NOLOAD) : ALIGN(8)
-  {
-    . = ALIGN (32);
-    _runtime_heap_start = ABSOLUTE(.);
-    . = . + HEAP_RUNTIME_SIZE;
-    _runtime_heap_end = ABSOLUTE(.);
-  } >runtime_heap :runtime_heap_phdr
-
-  .buffer_heap (NOLOAD) : ALIGN(8)
-  {
-    . = ALIGN (HEAP_BUF_ALIGNMENT);
-    _buffer_heap_start = ABSOLUTE(.);
-    . = . + HEAP_BUFFER_SIZE;
-    _buffer_heap_end = ABSOLUTE(.);
-  } >buffer_heap :buffer_heap_phdr
-
-  .sof_stack (NOLOAD) : ALIGN(8)
-  {
-    . = ALIGN (4096);
-    _sof_stack_start = ABSOLUTE(.);
-    . = . + SOF_STACK_TOTAL_SIZE;
-    _sof_stack_end = ABSOLUTE(.);
-  } >sof_stack :sof_stack_phdr
-
-  .static_uuid_entries (COPY) : ALIGN(1024)
-  {
-    *(*.static_uuids)
-  } > static_uuid_entries_seg :static_uuid_entries_phdr
-
-  .static_log_entries (COPY) : ALIGN(1024)
-  {
-    *(*.static_log*)
-  } > static_log_entries_seg :static_log_entries_phdr
-
-  .fw_metadata (COPY) : ALIGN(1024)
-  {
-    KEEP (*(.fw_metadata))
-    . = ALIGN(_EXT_MAN_ALIGN_);
-  } >fw_metadata_seg :metadata_entries_phdr
-}
diff --git a/src/platform/mt8186/platform.c b/src/platform/mt8186/platform.c
deleted file mode 100644
index 7d708750f8f0..000000000000
--- a/src/platform/mt8186/platform.c
+++ /dev/null
@@ -1,220 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-/*
- * Copyright(c) 2022 MediaTek. All rights reserved.
- *
- * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
- *         Tinghan Shen <tinghan.shen@mediatek.com>
- */
-
-#include <sof/compiler_info.h>
-#include <sof/debug/debug.h>
-#include <sof/drivers/edma.h>
-#include <rtos/interrupt.h>
-#include <sof/ipc/msg.h>
-#include <rtos/timer.h>
-#include <sof/fw-ready-metadata.h>
-#include <sof/lib/agent.h>
-#include <rtos/clk.h>
-#include <sof/lib/cpu.h>
-#include <sof/lib/dai.h>
-#include <sof/lib/dma.h>
-#include <sof/lib/mailbox.h>
-#include <sof/lib/memory.h>
-#include <sof/lib/mm_heap.h>
-#include <sof/platform.h>
-#include <sof/schedule/edf_schedule.h>
-#include <sof/schedule/ll_schedule.h>
-#include <sof/schedule/ll_schedule_domain.h>
-#include <rtos/sof.h>
-#include <sof/trace/dma-trace.h>
-#include <ipc/dai.h>
-#include <ipc/header.h>
-#include <ipc/info.h>
-#include <kernel/abi.h>
-#include <kernel/ext_manifest.h>
-#include <sof_versions.h>
-#include <errno.h>
-#include <stdint.h>
-#include <xtensa/hal.h>
-#include <platform/drivers/timer.h>
-
-struct sof;
-
-static const struct sof_ipc_fw_ready ready
-	__section(".fw_ready") = {
-	.hdr = {
-		.cmd = SOF_IPC_FW_READY,
-		.size = sizeof(struct sof_ipc_fw_ready),
-	},
-	/* dspbox is for DSP initiated IPC, hostbox is for host initiated IPC */
-	.version = {
-		.hdr.size = sizeof(struct sof_ipc_fw_version),
-		.micro = SOF_MICRO,
-		.minor = SOF_MINOR,
-		.major = SOF_MAJOR,
-		.tag = SOF_TAG,
-		.abi_version = SOF_ABI_VERSION,
-		.src_hash = SOF_SRC_HASH,
-	},
-	.flags = DEBUG_SET_FW_READY_FLAGS,
-};
-
-#define NUM_MTK_WINDOWS 6
-
-const struct ext_man_windows xsram_window
-		__aligned(EXT_MAN_ALIGN) __section(".fw_metadata") __unused = {
-	.hdr = {
-		.type = EXT_MAN_ELEM_WINDOW,
-		.elem_size = ALIGN_UP_COMPILE(sizeof(struct ext_man_windows), EXT_MAN_ALIGN),
-	},
-	.window = {
-		.ext_hdr	= {
-			.hdr.cmd = SOF_IPC_FW_READY,
-			.hdr.size = sizeof(struct sof_ipc_window),
-			.type	= SOF_IPC_EXT_WINDOW,
-		},
-		.num_windows	= NUM_MTK_WINDOWS,
-		.window	= {
-			{
-				.type	= SOF_IPC_REGION_UPBOX,
-				.id	= 0,	/* map to host window 0 */
-				.flags	= 0,
-				.size	= MAILBOX_DSPBOX_SIZE,
-				.offset	= MAILBOX_DSPBOX_OFFSET,
-			},
-			{
-				.type	= SOF_IPC_REGION_DOWNBOX,
-				.id	= 0,	/* map to host window 0 */
-				.flags	= 0,
-				.size	= MAILBOX_HOSTBOX_SIZE,
-				.offset	= MAILBOX_HOSTBOX_OFFSET,
-			},
-			{
-				.type	= SOF_IPC_REGION_DEBUG,
-				.id	= 0,	/* map to host window 0 */
-				.flags	= 0,
-				.size	= MAILBOX_DEBUG_SIZE,
-				.offset	= MAILBOX_DEBUG_OFFSET,
-			},
-			{
-				.type	= SOF_IPC_REGION_TRACE,
-				.id	= 0,	/* map to host window 0 */
-				.flags	= 0,
-				.size	= MAILBOX_TRACE_SIZE,
-				.offset	= MAILBOX_TRACE_OFFSET,
-			},
-			{
-				.type	= SOF_IPC_REGION_STREAM,
-				.id	= 0,	/* map to host window 0 */
-				.flags	= 0,
-				.size	= MAILBOX_STREAM_SIZE,
-				.offset	= MAILBOX_STREAM_OFFSET,
-			},
-			{
-				.type	= SOF_IPC_REGION_EXCEPTION,
-				.id	= 0,	/* map to host window 0 */
-				.flags	= 0,
-				.size	= MAILBOX_EXCEPTION_SIZE,
-				.offset	= MAILBOX_EXCEPTION_OFFSET,
-			},
-		},
-	}
-};
-
-static struct timer timer_shared = {
-	.id = OSTIMER0,
-	.irq = MTK_DSP_IRQ_OSTIMER32,
-};
-
-/* Override the default MPU setup. This table matches the memory map
- * of the 'sample_controller' core and will need to be modified for
- * other cores.
- * NOTE: This table sets up all of external memory as shared uncached.
- * For best results, edit the LSP memory map to create a separate
- * section in shared memory, place all sections that need to be uncached
- * into that section, and only map that section uncached. See README
- * for more details.
- */
-const struct xthal_MPU_entry __xt_mpu_init_table[] __section(".ResetVector.text") = {
-	XTHAL_MPU_ENTRY(0x00000000, 1, XTHAL_AR_RWXrwx, XTHAL_MEM_DEVICE),		// unused
-	XTHAL_MPU_ENTRY(0x4e100000, 1, XTHAL_AR_RWXrwx, XTHAL_MEM_WRITEBACK),		// sram
-	XTHAL_MPU_ENTRY(0x4e180000, 1, XTHAL_AR_NONE, XTHAL_MEM_DEVICE),		// unused
-	XTHAL_MPU_ENTRY(0x60000000, 1, XTHAL_AR_RWXrwx, XTHAL_MEM_WRITEBACK),		// dram
-	XTHAL_MPU_ENTRY(0x60500000, 1, XTHAL_AR_RWXrwx, XTHAL_MEM_NON_CACHEABLE),	// dram
-	XTHAL_MPU_ENTRY(0x61100000, 1, XTHAL_AR_NONE, XTHAL_MEM_DEVICE),		// unused
-};
-
-const unsigned int __xt_mpu_init_table_size __section(".ResetVector.text") =
-	ARRAY_SIZE(__xt_mpu_init_table);
-
-int platform_boot_complete(uint32_t boot_message)
-{
-	mailbox_dspbox_write(0, &ready, sizeof(ready));
-
-	/* now interrupt host to tell it we are done booting */
-	trigger_irq_to_host_req();
-
-	return 0;
-}
-
-extern void dump_adsppll(int line);
-
-int platform_init(struct sof *sof)
-{
-	int ret;
-
-	sof->platform_timer = &timer_shared;
-	sof->cpu_timers = sof->platform_timer;
-
-	platform_interrupt_init();
-	platform_clock_init(sof);
-
-	scheduler_init_edf();
-
-	/* init low latency domains and schedulers */
-	sof->platform_timer_domain = timer_domain_init(sof->platform_timer, PLATFORM_DEFAULT_CLOCK);
-	scheduler_init_ll(sof->platform_timer_domain);
-	platform_timer_start(sof->platform_timer);
-
-	sa_init(sof, CONFIG_SYSTICK_PERIOD);
-
-	/* init DMA */
-	ret = dmac_init(sof);
-	if (ret < 0)
-		return -ENODEV;
-
-	/* Init platform domain */
-	sof->platform_dma_domain = dma_multi_chan_domain_init(&sof->dma_info->dma_array[0], 1,
-							      PLATFORM_DEFAULT_CLOCK, false);
-	scheduler_init_ll(sof->platform_dma_domain);
-
-	/* initialize the host IPC mechanims */
-	ipc_init(sof);
-
-	ret = dai_init(sof);
-	if (ret < 0)
-		return ret;
-
-#if CONFIG_TRACE
-	/* Initialize DMA for Trace*/
-	trace_point(TRACE_BOOT_PLATFORM_DMA_TRACE);
-	dma_trace_init_complete(sof->dmat);
-#endif
-
-	/* show heap status */
-	heap_trace_all(1);
-
-	return 0;
-}
-
-int platform_context_save(struct sof *sof)
-{
-	clock_set_freq(CLK_CPU(cpu_get_id()), CLK_DEFAULT_CPU_HZ);
-	return 0;
-}
-
-void platform_wait_for_interrupt(int level)
-{
-	arch_wait_for_interrupt(level);
-}
-
diff --git a/src/platform/mt8188/CMakeLists.txt b/src/platform/mt8188/CMakeLists.txt
deleted file mode 100644
index 0965341701b5..000000000000
--- a/src/platform/mt8188/CMakeLists.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-
-add_subdirectory(lib)
-
-add_local_sources(sof platform.c afe-platform.c)
-target_include_directories(sof_options INTERFACE ${PROJECT_SOURCE_DIR}/src/platform/mt8188/include/arch)
-target_include_directories(sof_options INTERFACE ${PROJECT_SOURCE_DIR}/src/platform/mt8188/include/platform)
diff --git a/src/platform/mt8188/afe-platform.c b/src/platform/mt8188/afe-platform.c
deleted file mode 100644
index 4e0e2db4db35..000000000000
--- a/src/platform/mt8188/afe-platform.c
+++ /dev/null
@@ -1,252 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-/*
- * Copyright(c) 2023 MediaTek. All rights reserved.
- *
- * Author: Trevor Wu <trevor.wu@mediatek.com>
- */
-
-#include <sof/common.h>
-#include <errno.h>
-#include <sof/drivers/afe-drv.h>
-#include <mt8188-afe-reg.h>
-#include <mt8188-afe-common.h>
-
-/*
- * AFE: Audio Front-End
- *
- * frontend (memif):
- *   memory interface
- *   UL (uplink for capture)
- *   DL (downlink for playback)
- * backend:
- *   TDM In
- *   TDM Out
- *   DMIC
- *   GASRC
- *   I2S Out
- *   I2S In
- *   etc.
- * interconn:
- *   inter-connection,
- *   connect frontends and backends as DSP path
- */
-
-static const struct mtk_base_memif_data memif_data[MT8188_MEMIF_NUM] = {
-	[MT8188_MEMIF_DL2] = {
-		.name = "DL2",
-		.id = MT8188_MEMIF_DL2,
-		.reg_ofs_base = AFE_DL2_BASE,
-		.reg_ofs_cur = AFE_DL2_CUR,
-		.reg_ofs_end = AFE_DL2_END,
-		.fs_reg = AFE_MEMIF_AGENT_FS_CON0,
-		.fs_shift = 10,
-		.fs_maskbit = 0x1f,
-		.mono_reg = -1,
-		.mono_shift = 0,
-		.int_odd_flag_reg = -1,
-		.int_odd_flag_shift = 0,
-		.enable_reg = AFE_DAC_CON0,
-		.enable_shift = 18,
-		.hd_reg = AFE_DL2_CON0,
-		.hd_shift = 5,
-		.agent_disable_reg = AUDIO_TOP_CON5,
-		.agent_disable_shift = 18,
-		.ch_num_reg = AFE_DL2_CON0,
-		.ch_num_shift = 0,
-		.ch_num_maskbit = 0x1f,
-		.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
-		.msb_shift = 18,
-		.msb2_reg = AFE_NORMAL_END_ADR_MSB,
-		.msb2_shift = 18,
-	},
-	[MT8188_MEMIF_DL3] = {
-		.name = "DL3",
-		.id = MT8188_MEMIF_DL3,
-		.reg_ofs_base = AFE_DL3_BASE,
-		.reg_ofs_cur = AFE_DL3_CUR,
-		.reg_ofs_end = AFE_DL3_END,
-		.fs_reg = AFE_MEMIF_AGENT_FS_CON0,
-		.fs_shift = 15,
-		.fs_maskbit = 0x1f,
-		.mono_reg = -1,
-		.mono_shift = 0,
-		.int_odd_flag_reg = -1,
-		.int_odd_flag_shift = 0,
-		.enable_reg = AFE_DAC_CON0,
-		.enable_shift = 19,
-		.hd_reg = AFE_DL3_CON0,
-		.hd_shift = 5,
-		.agent_disable_reg = AUDIO_TOP_CON5,
-		.agent_disable_shift = 19,
-		.ch_num_reg = AFE_DL3_CON0,
-		.ch_num_shift = 0,
-		.ch_num_maskbit = 0x1f,
-		.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
-		.msb_shift = 19,
-		.msb2_reg = AFE_NORMAL_END_ADR_MSB,
-		.msb2_shift = 19,
-	},
-	[MT8188_MEMIF_UL4] = {
-		.name = "UL4",
-		.id = MT8188_MEMIF_UL4,
-		.reg_ofs_base = AFE_UL4_BASE,
-		.reg_ofs_cur = AFE_UL4_CUR,
-		.reg_ofs_end = AFE_UL4_END,
-		.fs_reg = AFE_MEMIF_AGENT_FS_CON2,
-		.fs_shift = 15,
-		.fs_maskbit = 0x1f,
-		.mono_reg = AFE_UL4_CON0,
-		.mono_shift = 1,
-		.int_odd_flag_reg = AFE_UL4_CON0,
-		.int_odd_flag_shift = 0,
-		.enable_reg = AFE_DAC_CON0,
-		.enable_shift = 4,
-		.hd_reg = AFE_UL4_CON0,
-		.hd_shift = 5,
-		.agent_disable_reg = AUDIO_TOP_CON5,
-		.agent_disable_shift = 3,
-		.ch_num_reg = -1,
-		.ch_num_shift = 0,
-		.ch_num_maskbit = 0,
-		.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
-		.msb_shift = 3,
-		.msb2_reg = AFE_NORMAL_END_ADR_MSB,
-		.msb2_shift = 3,
-	},
-	[MT8188_MEMIF_UL5] = {
-		.name = "UL5",
-		.id = MT8188_MEMIF_UL5,
-		.reg_ofs_base = AFE_UL5_BASE,
-		.reg_ofs_cur = AFE_UL5_CUR,
-		.reg_ofs_end = AFE_UL5_END,
-		.fs_reg = AFE_MEMIF_AGENT_FS_CON2,
-		.fs_shift = 20,
-		.fs_maskbit = 0x1f,
-		.mono_reg = AFE_UL5_CON0,
-		.mono_shift = 1,
-		.int_odd_flag_reg = AFE_UL5_CON0,
-		.int_odd_flag_shift = 0,
-		.enable_reg = AFE_DAC_CON0,
-		.enable_shift = 5,
-		.hd_reg = AFE_UL5_CON0,
-		.hd_shift = 5,
-		.agent_disable_reg = AUDIO_TOP_CON5,
-		.agent_disable_shift = 4,
-		.ch_num_reg = -1,
-		.ch_num_shift = 0,
-		.ch_num_maskbit = 0,
-		.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
-		.msb_shift = 4,
-		.msb2_reg = AFE_NORMAL_END_ADR_MSB,
-		.msb2_shift = 4,
-	},
-};
-
-struct mt8188_afe_rate {
-	unsigned int rate;
-	unsigned int reg_value;
-};
-
-static const struct mt8188_afe_rate mt8188_afe_rates[] = {
-	{
-		.rate = 8000,
-		.reg_value = 0,
-	},
-	{
-		.rate = 12000,
-		.reg_value = 1,
-	},
-	{
-		.rate = 16000,
-		.reg_value = 2,
-	},
-	{
-		.rate = 24000,
-		.reg_value = 3,
-	},
-	{
-		.rate = 32000,
-		.reg_value = 4,
-	},
-	{
-		.rate = 48000,
-		.reg_value = 5,
-	},
-	{
-		.rate = 96000,
-		.reg_value = 6,
-	},
-	{
-		.rate = 192000,
-		.reg_value = 7,
-	},
-	{
-		.rate = 384000,
-		.reg_value = 8,
-	},
-	{
-		.rate = 7350,
-		.reg_value = 16,
-	},
-	{
-		.rate = 11025,
-		.reg_value = 17,
-	},
-	{
-		.rate = 14700,
-		.reg_value = 18,
-	},
-	{
-		.rate = 22050,
-		.reg_value = 19,
-	},
-	{
-		.rate = 29400,
-		.reg_value = 20,
-	},
-	{
-		.rate = 44100,
-		.reg_value = 21,
-	},
-	{
-		.rate = 88200,
-		.reg_value = 22,
-	},
-	{
-		.rate = 176400,
-		.reg_value = 23,
-	},
-	{
-		.rate = 352800,
-		.reg_value = 24,
-	},
-};
-
-static unsigned int mt8188_afe_fs_timing(unsigned int rate)
-{
-	int i;
-
-	for (i = 0; i < ARRAY_SIZE(mt8188_afe_rates); i++)
-		if (mt8188_afe_rates[i].rate == rate)
-			return mt8188_afe_rates[i].reg_value;
-
-	return -EINVAL;
-}
-
-static unsigned int mt8188_afe_fs(unsigned int rate, int aud_blk)
-{
-	return mt8188_afe_fs_timing(rate);
-}
-
-struct mtk_base_afe_platform mtk_afe_platform = {
-	.base_addr = AFE_BASE_ADDR,
-	.memif_datas = memif_data,
-	.memif_size = MT8188_MEMIF_NUM,
-	.memif_dl_num = MT8188_MEMIF_DL_NUM,
-	.memif_32bit_supported = 0,
-	.irq_datas = NULL,
-	.irqs_size = 0,
-	.dais_size = MT8188_DAI_NUM,
-	.afe_fs = mt8188_afe_fs,
-	.irq_fs = mt8188_afe_fs_timing,
-};
diff --git a/src/platform/mt8188/include/arch/xtensa/config/core-isa.h b/src/platform/mt8188/include/arch/xtensa/config/core-isa.h
deleted file mode 100644
index 79bee81a1ff1..000000000000
--- a/src/platform/mt8188/include/arch/xtensa/config/core-isa.h
+++ /dev/null
@@ -1,805 +0,0 @@
-/* 
- * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
- *				processor CORE configuration
- *
- *  See <xtensa/config/core.h>, which includes this file, for more details.
- */
-
-/* Xtensa processor core configuration information.
-
-   Customer ID=16990; Build=0x904d8; Copyright (c) 1999-2020 Tensilica Inc.
-
-   Permission is hereby granted, free of charge, to any person obtaining
-   a copy of this software and associated documentation files (the
-   "Software"), to deal in the Software without restriction, including
-   without limitation the rights to use, copy, modify, merge, publish,
-   distribute, sublicense, and/or sell copies of the Software, and to
-   permit persons to whom the Software is furnished to do so, subject to
-   the following conditions:
-
-   The above copyright notice and this permission notice shall be included
-   in all copies or substantial portions of the Software.
-
-   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
-
-#ifndef XTENSA_CORE_CONFIGURATION_H_
-#define XTENSA_CORE_CONFIGURATION_H_
-
-
-/****************************************************************************
-	    Parameters Useful for Any Code, USER or PRIVILEGED
- ****************************************************************************/
-
-/*
- *  Note:  Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
- *  configured, and a value of 0 otherwise.  These macros are always defined.
- */
-
-
-/*----------------------------------------------------------------------
-				ISA
-  ----------------------------------------------------------------------*/
-
-#define XCHAL_HAVE_BE			0	/* big-endian byte ordering */
-#define XCHAL_HAVE_WINDOWED		1	/* windowed registers option */
-#define XCHAL_NUM_AREGS			64	/* num of physical addr regs */
-#define XCHAL_NUM_AREGS_LOG2		6	/* log2(XCHAL_NUM_AREGS) */
-#define XCHAL_MAX_INSTRUCTION_SIZE	16	/* max instr bytes (3..8) */
-#define XCHAL_HAVE_DEBUG		1	/* debug option */
-#define XCHAL_HAVE_DENSITY		1	/* 16-bit instructions */
-#define XCHAL_HAVE_LOOPS		1	/* zero-overhead loops */
-#define XCHAL_LOOP_BUFFER_SIZE		256	/* zero-ov. loop instr buffer size */
-#define XCHAL_HAVE_NSA			1	/* NSA/NSAU instructions */
-#define XCHAL_HAVE_MINMAX		1	/* MIN/MAX instructions */
-#define XCHAL_HAVE_SEXT			1	/* SEXT instruction */
-#define XCHAL_HAVE_DEPBITS		0	/* DEPBITS instruction */
-#define XCHAL_HAVE_CLAMPS		1	/* CLAMPS instruction */
-#define XCHAL_HAVE_MUL16		1	/* MUL16S/MUL16U instructions */
-#define XCHAL_HAVE_MUL32		1	/* MULL instruction */
-#define XCHAL_HAVE_MUL32_HIGH		0	/* MULUH/MULSH instructions */
-#define XCHAL_HAVE_DIV32		1	/* QUOS/QUOU/REMS/REMU instructions */
-#define XCHAL_HAVE_L32R			1	/* L32R instruction */
-#define XCHAL_HAVE_ABSOLUTE_LITERALS	0	/* non-PC-rel (extended) L32R */
-#define XCHAL_HAVE_CONST16		0	/* CONST16 instruction */
-#define XCHAL_HAVE_ADDX			1	/* ADDX#/SUBX# instructions */
-#define XCHAL_HAVE_EXCLUSIVE            1	/* L32EX/S32EX instructions */
-#define XCHAL_HAVE_WIDE_BRANCHES	0	/* B*.W18 or B*.W15 instr's */
-#define XCHAL_HAVE_PREDICTED_BRANCHES	0	/* B[EQ/EQZ/NE/NEZ]T instr's */
-#define XCHAL_HAVE_CALL4AND12		1	/* (obsolete option) */
-#define XCHAL_HAVE_ABS			1	/* ABS instruction */
-#define XCHAL_HAVE_RELEASE_SYNC		1	/* L32AI/S32RI instructions */
-#define XCHAL_HAVE_S32C1I		0	/* S32C1I instruction */
-#define XCHAL_HAVE_SPECULATION		0	/* speculation */
-#define XCHAL_HAVE_FULL_RESET		1	/* all regs/state reset */
-#define XCHAL_NUM_CONTEXTS		1	/* */
-#define XCHAL_NUM_MISC_REGS		4	/* num of scratch regs (0..4) */
-#define XCHAL_HAVE_TAP_MASTER		0	/* JTAG TAP control instr's */
-#define XCHAL_HAVE_PRID			1	/* processor ID register */
-#define XCHAL_HAVE_EXTERN_REGS		1	/* WER/RER instructions */
-#define XCHAL_HAVE_MX			0	/* MX core (Tensilica internal) */
-#define XCHAL_HAVE_MP_INTERRUPTS	0	/* interrupt distributor port */
-#define XCHAL_HAVE_MP_RUNSTALL		0	/* core RunStall control port */
-#define XCHAL_HAVE_PSO			0	/* Power Shut-Off */
-#define XCHAL_HAVE_PSO_CDM		0	/* core/debug/mem pwr domains */
-#define XCHAL_HAVE_PSO_FULL_RETENTION	0	/* all regs preserved on PSO */
-#define XCHAL_HAVE_THREADPTR		1	/* THREADPTR register */
-#define XCHAL_HAVE_BOOLEANS		1	/* boolean registers */
-#define XCHAL_HAVE_CP			1	/* CPENABLE reg (coprocessor) */
-#define XCHAL_CP_MAXCFG			2	/* max allowed cp id plus one */
-#define XCHAL_HAVE_MAC16		0	/* MAC16 package */
-#define XCHAL_HAVE_LX			1	/* LX core */
-#define XCHAL_HAVE_NX			0	/* NX core (starting RH) */
-
-#define XCHAL_HAVE_SUPERGATHER		0	/* SuperGather */
-
-#define XCHAL_HAVE_FUSION		0	/* Fusion*/
-#define XCHAL_HAVE_FUSION_FP		0	/* Fusion FP option */
-#define XCHAL_HAVE_FUSION_LOW_POWER	0	/* Fusion Low Power option */
-#define XCHAL_HAVE_FUSION_AES		0	/* Fusion BLE/Wifi AES-128 CCM option */
-#define XCHAL_HAVE_FUSION_CONVENC	0	/* Fusion Conv Encode option */
-#define XCHAL_HAVE_FUSION_LFSR_CRC	0	/* Fusion LFSR-CRC option */
-#define XCHAL_HAVE_FUSION_BITOPS	0	/* Fusion Bit Operations Support option */
-#define XCHAL_HAVE_FUSION_AVS		0	/* Fusion AVS option */
-#define XCHAL_HAVE_FUSION_16BIT_BASEBAND 0	/* Fusion 16-bit Baseband option */
-#define XCHAL_HAVE_FUSION_VITERBI	0	/* Fusion Viterbi option */
-#define XCHAL_HAVE_FUSION_SOFTDEMAP	0	/* Fusion Soft Bit Demap option */
-#define XCHAL_HAVE_HIFIPRO		0	/* HiFiPro Audio Engine pkg */
-#define XCHAL_HAVE_HIFI5		1	/* HiFi5 Audio Engine pkg */
-#define XCHAL_HAVE_HIFI5_NN_MAC		1	/* HiFi5 Audio Engine NN-MAC option */
-#define XCHAL_HAVE_HIFI5_VFPU		1	/* HiFi5 Audio Engine Single-Precision VFPU option */
-#define XCHAL_HAVE_HIFI5_HP_VFPU	1	/* HiFi5 Audio Engine Half-Precision VFPU option */
-#define XCHAL_HAVE_HIFI4		0	/* HiFi4 Audio Engine pkg */
-#define XCHAL_HAVE_HIFI4_VFPU		1	/* HiFi4 Audio Engine VFPU option */
-#define XCHAL_HAVE_HIFI3		1	/* HiFi3 Audio Engine pkg */
-#define XCHAL_HAVE_HIFI3_VFPU		1	/* HiFi3 Audio Engine VFPU option */
-#define XCHAL_HAVE_HIFI3Z		0	/* HiFi3Z Audio Engine pkg */
-#define XCHAL_HAVE_HIFI3Z_VFPU	0	/* HiFi3Z Audio Engine VFPU option */
-#define XCHAL_HAVE_HIFI2		0	/* HiFi2 Audio Engine pkg */
-#define XCHAL_HAVE_HIFI2EP		0	/* HiFi2EP */
-#define XCHAL_HAVE_HIFI_MINI		0	
-
-
-
-#define XCHAL_HAVE_VECTORFPU2005	0	/* vector floating-point pkg */
-#define XCHAL_HAVE_USER_DPFPU		0       /* user DP floating-point pkg */
-#define XCHAL_HAVE_USER_SPFPU		1       /* user SP floating-point pkg */
-#define XCHAL_HAVE_FP			1	/* single prec floating point */
-#define XCHAL_HAVE_FP_DIV		1	/* FP with DIV instructions */
-#define XCHAL_HAVE_FP_RECIP		1	/* FP with RECIP instructions */
-#define XCHAL_HAVE_FP_SQRT		1	/* FP with SQRT instructions */
-#define XCHAL_HAVE_FP_RSQRT		1	/* FP with RSQRT instructions */
-#define XCHAL_HAVE_DFP			0	/* double precision FP pkg */
-#define XCHAL_HAVE_DFP_DIV		0	/* DFP with DIV instructions */
-#define XCHAL_HAVE_DFP_RECIP		0	/* DFP with RECIP instructions*/
-#define XCHAL_HAVE_DFP_SQRT		0	/* DFP with SQRT instructions */
-#define XCHAL_HAVE_DFP_RSQRT		0	/* DFP with RSQRT instructions*/
-#define XCHAL_HAVE_DFP_ACCEL		0	/* double precision FP acceleration pkg */
-#define XCHAL_HAVE_DFP_accel		XCHAL_HAVE_DFP_ACCEL	/* for backward compatibility */
-
-#define XCHAL_HAVE_DFPU_SINGLE_ONLY	0	/* DFPU Coprocessor, single precision only */
-#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE	0	/* DFPU Coprocessor, single and double precision */
-#define XCHAL_HAVE_VECTRA1		0	/* Vectra I  pkg */
-#define XCHAL_HAVE_VECTRALX		0	/* Vectra LX pkg */
-
-#define XCHAL_HAVE_FUSIONG		0    /* FusionG */
-#define XCHAL_HAVE_FUSIONG3		0    /* FusionG3 */
-#define XCHAL_HAVE_FUSIONG6		0    /* FusionG6 */
-#define XCHAL_HAVE_FUSIONG_SP_VFPU	0    /* sp_vfpu option on FusionG */
-#define XCHAL_HAVE_FUSIONG_DP_VFPU	0    /* dp_vfpu option on FusionG */
-#define XCHAL_FUSIONG_SIMD32		0    /* simd32 for FusionG */
-
-#define XCHAL_HAVE_FUSIONJ		0    /* FusionJ */
-#define XCHAL_HAVE_FUSIONJ6		0    /* FusionJ6 */
-#define XCHAL_HAVE_FUSIONJ_SP_VFPU	0    /* sp_vfpu option on FusionJ */
-#define XCHAL_HAVE_FUSIONJ_DP_VFPU	0    /* dp_vfpu option on FusionJ */
-#define XCHAL_FUSIONJ_SIMD32		0    /* simd32 for FusionJ */
-
-#define XCHAL_HAVE_PDX			0    /* PDX-LX */
-#define XCHAL_PDX_SIMD32		0    /* simd32 for PDX */
-#define XCHAL_HAVE_PDX4			0    /* PDX4-LX */
-#define XCHAL_HAVE_PDX8			0    /* PDX8-LX */
-#define XCHAL_HAVE_PDX16		0    /* PDX16-LX */
-#define XCHAL_HAVE_PDXNX 		0    /* PDX-NX */
-
-#define XCHAL_HAVE_CONNXD2		0	/* ConnX D2 pkg */
-#define XCHAL_HAVE_CONNXD2_DUALLSFLIX   0	/* ConnX D2 & Dual LoadStore Flix */
-#define XCHAL_HAVE_BALL			0
-#define XCHAL_HAVE_BALLAP		0
-#define XCHAL_HAVE_BBE16		0	/* ConnX BBE16 pkg */
-#define XCHAL_HAVE_BBE16_RSQRT		0	/* BBE16 & vector recip sqrt */
-#define XCHAL_HAVE_BBE16_VECDIV		0	/* BBE16 & vector divide */
-#define XCHAL_HAVE_BBE16_DESPREAD	0	/* BBE16 & despread */
-#define XCHAL_HAVE_CONNX_B10            0    /* ConnX B10 pkg*/
-#define XCHAL_HAVE_CONNX_B20            0    /* ConnX B20 pkg*/
-#define XCHAL_HAVE_CONNX_B_DP_VFPU      0    /* Double-precision Vector Floating-point option on ConnX B10 & B20 */
-#define XCHAL_HAVE_CONNX_B_SP_VFPU      0    /* Single-precision Vector Floating-point option on ConnX B10 & B20 */
-#define XCHAL_HAVE_CONNX_B_SPX_VFPU     0    /* Single-precision Extended Vector Floating-point option on ConnX B10 & B20 */
-#define XCHAL_HAVE_CONNX_B_HPX_VFPU     0    /* Half-precision Extended Vector Floating-point option on ConnX B10 & B20 */
-#define XCHAL_HAVE_CONNX_B_32B_MAC      0    /* 32-bit vector MAC (real and complex), FIR & FFT option on ConnX B10 & B20 */
-#define XCHAL_HAVE_CONNX_B_VITERBI      0    /* Viterbi option on ConnX B10 & B20 */
-#define XCHAL_HAVE_CONNX_B_TURBO        0    /* Turbo option on ConnX B10 & B20 */
-#define XCHAL_HAVE_CONNX_B_LDPC         0    /* LDPC option on ConnX B10 & B20 */
-#define XCHAL_HAVE_BBENEP		0	/* ConnX BBENEP pkgs */
-#define XCHAL_HAVE_BBENEP_SP_VFPU	0       /* sp_vfpu option on BBE-EP */
-#define XCHAL_HAVE_BSP3			0	/* ConnX BSP3 pkg */
-#define XCHAL_HAVE_BSP3_TRANSPOSE	0	/* BSP3 & transpose32x32 */
-#define XCHAL_HAVE_SSP16		0	/* ConnX SSP16 pkg */
-#define XCHAL_HAVE_SSP16_VITERBI	0	/* SSP16 & viterbi */
-#define XCHAL_HAVE_TURBO16		0	/* ConnX Turbo16 pkg */
-#define XCHAL_HAVE_BBP16		0	/* ConnX BBP16 pkg */
-#define XCHAL_HAVE_FLIX3		0	/* basic 3-way FLIX option */
-#define XCHAL_HAVE_GRIVPEP		0	/* General Release of IVPEP */
-#define XCHAL_HAVE_GRIVPEP_HISTOGRAM	0       /* Histogram option on GRIVPEP */
-
-#define XCHAL_HAVE_VISION	        0     /* Vision P5/P6 */
-#define XCHAL_VISION_SIMD16             0     /* simd16 for Vision P5/P6 */
-#define XCHAL_VISION_TYPE               0     /* Vision P5, P6, Q6, Q7 or Q8 */
-#define XCHAL_VISION_QUAD_MAC_TYPE      0     /* quad_mac option on Vision P6 */
-#define XCHAL_HAVE_VISION_HISTOGRAM     0     /* histogram option on Vision P5/P6 */
-#define XCHAL_HAVE_VISION_DP_VFPU       0     /* dp_vfpu option on Vision Q7/Q8 */
-#define XCHAL_HAVE_VISION_SP_VFPU       0     /* sp_vfpu option on Vision P5/P6/Q6/Q7 */
-#define XCHAL_HAVE_VISION_SP_VFPU_2XFMAC 0     /* sp_vfpu_2xfma option on Vision Q7 */
-#define XCHAL_HAVE_VISION_HP_VFPU       0     /* hp_vfpu option on Vision P6/Q6 */
-#define XCHAL_HAVE_VISION_HP_VFPU_2XFMAC 0     /* hp_vfpu_2xfma option on Vision Q7 */
-
-#define XCHAL_HAVE_VISIONC	        0     /* Vision C */
-
-#define XCHAL_HAVE_XNNE			0		/* XNNE */
-
-/*----------------------------------------------------------------------
-				MISC
-  ----------------------------------------------------------------------*/
-
-#define XCHAL_NUM_LOADSTORE_UNITS	2	/* load/store units */
-#define XCHAL_NUM_WRITEBUFFER_ENTRIES	32	/* size of write buffer */
-#define XCHAL_INST_FETCH_WIDTH		16	/* instr-fetch width in bytes */
-#define XCHAL_DATA_WIDTH		16	/* data width in bytes */
-#define XCHAL_DATA_PIPE_DELAY		2	/* d-side pipeline delay
-						   (1 = 5-stage, 2 = 7-stage) */
-#define XCHAL_CLOCK_GATING_GLOBAL	1	/* global clock gating */
-#define XCHAL_CLOCK_GATING_FUNCUNIT	1	/* funct. unit clock gating */
-/*  In T1050, applies to selected core load and store instructions (see ISA): */
-#define XCHAL_UNALIGNED_LOAD_EXCEPTION	1	/* unaligned loads cause exc. */
-#define XCHAL_UNALIGNED_STORE_EXCEPTION	1	/* unaligned stores cause exc.*/
-#define XCHAL_UNALIGNED_LOAD_HW		0	/* unaligned loads work in hw */
-#define XCHAL_UNALIGNED_STORE_HW	0	/* unaligned stores work in hw*/
-
-#define XCHAL_UNIFIED_LOADSTORE         0
-
-#define XCHAL_SW_VERSION		1405000	/* sw version of this header */
-#define XCHAL_SW_VERSION_MAJOR		14000	/* major ver# of sw          */
-#define XCHAL_SW_VERSION_MINOR		5	/* minor ver# of sw          */
-#define XCHAL_SW_VERSION_MICRO		0	/* micro ver# of sw          */
-#define XCHAL_SW_MINOR_VERSION		1405000	/* with zeroed micro */
-#define XCHAL_SW_MICRO_VERSION		1405000
-
-#define XCHAL_CORE_ID			"hifi5_7stg_I64D128"	/* alphanum core name
-						   (CoreID) set in the Xtensa
-						   Processor Generator */
-
-#define XCHAL_BUILD_UNIQUE_ID		0x000904D8	/* 22-bit sw build ID */
-
-/*
- *  These definitions describe the hardware targeted by this software.
- */
-#define XCHAL_HW_CONFIGID0		0xC003B286	/* ConfigID hi 32 bits*/
-#define XCHAL_HW_CONFIGID1		0x294904D8	/* ConfigID lo 32 bits*/
-#define XCHAL_HW_VERSION_NAME		"LX7.1.5"	/* full version name */
-#define XCHAL_HW_VERSION_MAJOR		2810	/* major ver# of targeted hw */
-#define XCHAL_HW_VERSION_MINOR		5	/* minor ver# of targeted hw */
-#define XCHAL_HW_VERSION_MICRO		0	/* subdot ver# of targeted hw */
-#define XCHAL_HW_VERSION		281050	/* major*100+(major<2810 ? minor : minor*10+micro) */
-#define XCHAL_HW_REL_LX7		1
-#define XCHAL_HW_REL_LX7_1		1
-#define XCHAL_HW_REL_LX7_1_5		1
-#define XCHAL_HW_CONFIGID_RELIABLE	1
-/*  If software targets a *range* of hardware versions, these are the bounds: */
-#define XCHAL_HW_MIN_VERSION_MAJOR	2810	/* major v of earliest tgt hw */
-#define XCHAL_HW_MIN_VERSION_MINOR	5	/* minor v of earliest tgt hw */
-#define XCHAL_HW_MIN_VERSION_MICRO	0	/* micro v of earliest tgt hw */
-#define XCHAL_HW_MIN_VERSION		281050	/* earliest targeted hw */
-#define XCHAL_HW_MAX_VERSION_MAJOR	2810	/* major v of latest tgt hw */
-#define XCHAL_HW_MAX_VERSION_MINOR	5	/* minor v of latest tgt hw */
-#define XCHAL_HW_MAX_VERSION_MICRO	0	/* micro v of latest tgt hw */
-#define XCHAL_HW_MAX_VERSION		281050	/* latest targeted hw */
-
-/*  Config is enabled for functional safety: */
-#define XCHAL_HAVE_FUNC_SAFETY		0
-
-/*  Config is enabled for secure operation: */
-#define XCHAL_HAVE_SECURE     		0
-
-#define XCHAL_HAVE_APB			0 
-
-/*----------------------------------------------------------------------
-				CACHE
-  ----------------------------------------------------------------------*/
-
-#define XCHAL_ICACHE_LINESIZE		128	/* I-cache line size in bytes */
-#define XCHAL_DCACHE_LINESIZE		128	/* D-cache line size in bytes */
-#define XCHAL_ICACHE_LINEWIDTH		7	/* log2(I line size in bytes) */
-#define XCHAL_DCACHE_LINEWIDTH		7	/* log2(D line size in bytes) */
-
-#define XCHAL_ICACHE_SIZE		65536	/* I-cache size in bytes or 0 */
-#define XCHAL_ICACHE_SIZE_LOG2		16
-#define XCHAL_DCACHE_SIZE		131072	/* D-cache size in bytes or 0 */
-#define XCHAL_DCACHE_SIZE_LOG2		17
-
-#define XCHAL_DCACHE_IS_WRITEBACK	1	/* writeback feature */
-#define XCHAL_DCACHE_IS_COHERENT	0	/* MP coherence feature */
-
-#define XCHAL_HAVE_PREFETCH		1	/* PREFCTL register */
-#define XCHAL_HAVE_PREFETCH_L1		1	/* prefetch to L1 cache */
-#define XCHAL_PREFETCH_CASTOUT_LINES	2	/* dcache pref. castout bufsz */
-#define XCHAL_PREFETCH_ENTRIES		16	/* cache prefetch entries */
-#define XCHAL_PREFETCH_BLOCK_ENTRIES	8	/* prefetch block streams */
-#define XCHAL_HAVE_CACHE_BLOCKOPS	1	/* block prefetch for caches */
-#define XCHAL_HAVE_CME_DOWNGRADES	0
-#define XCHAL_HAVE_ICACHE_TEST		1	/* Icache test instructions */
-#define XCHAL_HAVE_DCACHE_TEST		1	/* Dcache test instructions */
-#define XCHAL_HAVE_ICACHE_DYN_WAYS	1	/* Icache dynamic way support */
-#define XCHAL_HAVE_DCACHE_DYN_WAYS	1	/* Dcache dynamic way support */
-#define XCHAL_HAVE_ICACHE_DYN_ENABLE	1	/* Icache enabled via MEMCTL */
-#define XCHAL_HAVE_DCACHE_DYN_ENABLE	1	/* Dcache enabled via MEMCTL */
-
-#define XCHAL_L1SCACHE_SIZE		         0
-#define XCHAL_L1SCACHE_SIZE_LOG2		 0
-#define XCHAL_L1SCACHE_WAYS              1
-#define XCHAL_L1SCACHE_WAYS_LOG2         0
-#define XCHAL_L1SCACHE_ACCESS_SIZE       0
-#define XCHAL_L1SCACHE_BANKS             1
-
-#define XCHAL_HAVE_L2			0	/* NX L2 cache controller */
-#define XCHAL_HAVE_L2_CACHE		0
-#define XCHAL_NUM_CORES_IN_CLUSTER	0
-
-/* PRID_ID macros are for internal use only ... subject to removal */
-#define PRID_ID_SHIFT           0
-#define PRID_ID_BITS            4
-#define PRID_ID_MASK            0x0000000F
-
-/*  This one is a form of caching, though not architecturally visible:  */
-#define XCHAL_HAVE_BRANCH_PREDICTION	0	/* branch [target] prediction */
-
-
-
-
-/****************************************************************************
-    Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
- ****************************************************************************/
-
-
-#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
-
-/*----------------------------------------------------------------------
-				CACHE
-  ----------------------------------------------------------------------*/
-
-#define XCHAL_HAVE_PIF			1	/* any outbound bus present */
-
-#define XCHAL_HAVE_AXI			1	/* AXI bus */
-#define XCHAL_HAVE_AXI_ECC		1	/* ECC on AXI bus */
-#define XCHAL_HAVE_ACELITE		0	/* ACELite bus */
-
-#define XCHAL_HAVE_PIF_WR_RESP			1	/* pif write response */
-#define XCHAL_HAVE_PIF_REQ_ATTR			1	/* pif attribute */
-
-/*  If present, cache size in bytes == (ways * 2^(linewidth + setwidth)).  */
-
-/*  Number of cache sets in log2(lines per way):  */
-#define XCHAL_ICACHE_SETWIDTH		7
-#define XCHAL_DCACHE_SETWIDTH		8
-
-/*  Cache set associativity (number of ways):  */
-#define XCHAL_ICACHE_WAYS		4
-#define XCHAL_ICACHE_WAYS_LOG2		2
-#define XCHAL_DCACHE_WAYS		4
-#define XCHAL_DCACHE_WAYS_LOG2		2
-
-/*  Cache features:  */
-#define XCHAL_ICACHE_LINE_LOCKABLE	1
-#define XCHAL_DCACHE_LINE_LOCKABLE	1
-#define XCHAL_ICACHE_ECC_PARITY		0
-#define XCHAL_DCACHE_ECC_PARITY		0
-#define XCHAL_ICACHE_ECC_WIDTH		4
-#define XCHAL_DCACHE_ECC_WIDTH		1
-
-/*  Cache access size in bytes (affects operation of SICW instruction):  */
-#define XCHAL_ICACHE_ACCESS_SIZE	16
-#define XCHAL_DCACHE_ACCESS_SIZE	16
-
-#define XCHAL_DCACHE_BANKS		2	/* number of banks */
-
-/* The number of Cache lines associated with a single cache tag */
-#define XCHAL_DCACHE_LINES_PER_TAG_LOG2	0
-
-/*  Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits):  */
-
-
-/*----------------------------------------------------------------------
-			INTERNAL I/D RAM/ROMs and XLMI
-  ----------------------------------------------------------------------*/
-#define XCHAL_NUM_INSTROM		0	/* number of core instr. ROMs */
-#define XCHAL_NUM_INSTRAM		2	/* number of core instr. RAMs */
-#define XCHAL_NUM_DATAROM		0	/* number of core data ROMs */
-#define XCHAL_NUM_DATARAM		1	/* number of core data RAMs */
-#define XCHAL_NUM_URAM			0	/* number of core unified RAMs*/
-#define XCHAL_NUM_XLMI			0	/* number of core XLMI ports */
-#define	XCHAL_HAVE_IRAMCFG		0	/* IRAMxCFG register present */
-#define	XCHAL_HAVE_DRAMCFG		0	/* DRAMxCFG register present */
-
-/*  Instruction RAM 0:  */
-#define XCHAL_INSTRAM0_VADDR		0x3FFF0000	/* virtual address */
-#define XCHAL_INSTRAM0_PADDR		0x3FFF0000	/* physical address */
-#define XCHAL_INSTRAM0_SIZE		32768	/* size in bytes */
-#define XCHAL_INSTRAM0_ECC_PARITY	0	/* ECC/parity type, 0=none */
-#define XCHAL_HAVE_INSTRAM0		1
-#define XCHAL_INSTRAM0_HAVE_IDMA	0	/* idma supported by this local memory */
-
-/*  Instruction RAM 1:  */
-#define XCHAL_INSTRAM1_VADDR		0x3FFF8000	/* virtual address */
-#define XCHAL_INSTRAM1_PADDR		0x3FFF8000	/* physical address */
-#define XCHAL_INSTRAM1_SIZE		4096	/* size in bytes */
-#define XCHAL_INSTRAM1_ECC_PARITY	0	/* ECC/parity type, 0=none */
-#define XCHAL_HAVE_INSTRAM1		1
-#define XCHAL_INSTRAM1_HAVE_IDMA	0	/* idma supported by this local memory */
-
-/*  Data RAM 0:  */
-#define XCHAL_DATARAM0_VADDR		0x3FFE8000	/* virtual address */
-#define XCHAL_DATARAM0_PADDR		0x3FFE8000	/* physical address */
-#define XCHAL_DATARAM0_SIZE		32768	/* size in bytes */
-#define XCHAL_DATARAM0_ECC_PARITY	0	/* ECC/parity type, 0=none */
-#define XCHAL_DATARAM0_BANKS		2	/* number of banks */
-#define XCHAL_HAVE_DATARAM0		1
-#define XCHAL_DATARAM0_HAVE_IDMA	0	/* idma supported by this local memory */
-
-#define XCHAL_HAVE_IMEM_LOADSTORE	1	/* can load/store to IROM/IRAM*/
-
-
-/*----------------------------------------------------------------------
-			IDMA
-  ----------------------------------------------------------------------*/
-
-#define XCHAL_HAVE_IDMA			0
-
-
-
-/*----------------------------------------------------------------------
-			INTERRUPTS and TIMERS
-  ----------------------------------------------------------------------*/
-
-#define XCHAL_HAVE_INTERRUPTS		1	/* interrupt option */
-#define XCHAL_HAVE_NMI			1	/* non-maskable interrupt */
-#define XCHAL_HAVE_CCOUNT		1	/* CCOUNT reg. (timer option) */
-#define XCHAL_NUM_TIMERS		3	/* number of CCOMPAREn regs */
-#define XCHAL_NUM_INTERRUPTS		32	/* number of interrupts */
-#define XCHAL_NUM_INTERRUPTS_LOG2	5	/* ceil(log2(NUM_INTERRUPTS)) */
-#define XCHAL_NUM_EXTINTERRUPTS		26	/* num of external interrupts */
-#define XCHAL_NUM_INTLEVELS		5	/* number of interrupt levels
-						   (not including level zero) */
-
-
-#define XCHAL_HAVE_HIGHPRI_INTERRUPTS	1   /* med/high-pri. interrupts */
-#define XCHAL_EXCM_LEVEL		3	/* level masked by PS.EXCM */
-	/* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
-
-/*  Masks of interrupts at each interrupt level:  */
-#define XCHAL_INTLEVEL1_MASK		0x040000FF
-#define XCHAL_INTLEVEL2_MASK		0xA800FF00
-#define XCHAL_INTLEVEL3_MASK		0x518F0000
-#define XCHAL_INTLEVEL4_MASK		0x00700000
-#define XCHAL_INTLEVEL5_MASK		0x00000000
-#define XCHAL_INTLEVEL6_MASK		0x02000000
-#define XCHAL_INTLEVEL7_MASK		0x00000000
-
-/*  Masks of interrupts at each range 1..n of interrupt levels:  */
-#define XCHAL_INTLEVEL1_ANDBELOW_MASK	0x040000FF
-#define XCHAL_INTLEVEL2_ANDBELOW_MASK	0xAC00FFFF
-#define XCHAL_INTLEVEL3_ANDBELOW_MASK	0xFD8FFFFF
-#define XCHAL_INTLEVEL4_ANDBELOW_MASK	0xFDFFFFFF
-#define XCHAL_INTLEVEL5_ANDBELOW_MASK	0xFDFFFFFF
-#define XCHAL_INTLEVEL6_ANDBELOW_MASK	0xFFFFFFFF
-#define XCHAL_INTLEVEL7_ANDBELOW_MASK	0xFFFFFFFF
-
-/*  Level of each interrupt:  */
-#define XCHAL_INT0_LEVEL		1
-#define XCHAL_INT1_LEVEL		1
-#define XCHAL_INT2_LEVEL		1
-#define XCHAL_INT3_LEVEL		1
-#define XCHAL_INT4_LEVEL		1
-#define XCHAL_INT5_LEVEL		1
-#define XCHAL_INT6_LEVEL		1
-#define XCHAL_INT7_LEVEL		1
-#define XCHAL_INT8_LEVEL		2
-#define XCHAL_INT9_LEVEL		2
-#define XCHAL_INT10_LEVEL		2
-#define XCHAL_INT11_LEVEL		2
-#define XCHAL_INT12_LEVEL		2
-#define XCHAL_INT13_LEVEL		2
-#define XCHAL_INT14_LEVEL		2
-#define XCHAL_INT15_LEVEL		2
-#define XCHAL_INT16_LEVEL		3
-#define XCHAL_INT17_LEVEL		3
-#define XCHAL_INT18_LEVEL		3
-#define XCHAL_INT19_LEVEL		3
-#define XCHAL_INT20_LEVEL		4
-#define XCHAL_INT21_LEVEL		4
-#define XCHAL_INT22_LEVEL		4
-#define XCHAL_INT23_LEVEL		3
-#define XCHAL_INT24_LEVEL		3
-#define XCHAL_INT25_LEVEL		6
-#define XCHAL_INT26_LEVEL		1
-#define XCHAL_INT27_LEVEL		2
-#define XCHAL_INT28_LEVEL		3
-#define XCHAL_INT29_LEVEL		2
-#define XCHAL_INT30_LEVEL		3
-#define XCHAL_INT31_LEVEL		2
-#define XCHAL_DEBUGLEVEL		5	/* debug interrupt level */
-#define XCHAL_HAVE_DEBUG_EXTERN_INT	1	/* OCD external db interrupt */
-#define XCHAL_NMILEVEL			6	/* NMI "level" (for use with
-						   EXCSAVE/EPS/EPC_n, RFI n) */
-
-/*  Type of each interrupt:  */
-#define XCHAL_INT0_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT1_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT2_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT3_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT4_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT5_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT6_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT7_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT8_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT9_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT10_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT11_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT12_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT13_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT14_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT15_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT16_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT17_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT18_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT19_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT20_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT21_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT22_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT23_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
-#define XCHAL_INT24_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
-#define XCHAL_INT25_TYPE 	XTHAL_INTTYPE_NMI
-#define XCHAL_INT26_TYPE 	XTHAL_INTTYPE_TIMER
-#define XCHAL_INT27_TYPE 	XTHAL_INTTYPE_TIMER
-#define XCHAL_INT28_TYPE 	XTHAL_INTTYPE_TIMER
-#define XCHAL_INT29_TYPE 	XTHAL_INTTYPE_PROFILING
-#define XCHAL_INT30_TYPE 	XTHAL_INTTYPE_WRITE_ERROR
-#define XCHAL_INT31_TYPE 	XTHAL_INTTYPE_SOFTWARE
-
-/*  Masks of interrupts for each type of interrupt:  */
-#define XCHAL_INTTYPE_MASK_UNCONFIGURED	0x00000000
-#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL	0x007FFFFF
-#define XCHAL_INTTYPE_MASK_EXTERN_EDGE	0x01800000
-#define XCHAL_INTTYPE_MASK_NMI		0x02000000
-#define XCHAL_INTTYPE_MASK_SOFTWARE	0x80000000
-#define XCHAL_INTTYPE_MASK_TIMER	0x1C000000
-#define XCHAL_INTTYPE_MASK_ETIE		0x00000000
-#define XCHAL_INTTYPE_MASK_WRITE_ERROR	0x40000000
-#define XCHAL_INTTYPE_MASK_DBG_REQUEST	0x00000000
-#define XCHAL_INTTYPE_MASK_BREAKIN	0x00000000
-#define XCHAL_INTTYPE_MASK_TRAX		0x00000000
-#define XCHAL_INTTYPE_MASK_PROFILING	0x20000000
-#define XCHAL_INTTYPE_MASK_IDMA_DONE	0x00000000
-#define XCHAL_INTTYPE_MASK_IDMA_ERR	0x00000000
-#define XCHAL_INTTYPE_MASK_GS_ERR	0x00000000
-#define XCHAL_INTTYPE_MASK_L2_ERR	0x00000000
-#define XCHAL_INTTYPE_MASK_L2_STATUS	0x00000000
-#define XCHAL_INTTYPE_MASK_COR_ECC_ERR	0x00000000
-#define XCHAL_INTTYPE_MASK_WWDT		0x00000000
-
-/*  Interrupt numbers assigned to specific interrupt sources:  */
-#define XCHAL_TIMER0_INTERRUPT		26	/* CCOMPARE0 */
-#define XCHAL_TIMER1_INTERRUPT		27	/* CCOMPARE1 */
-#define XCHAL_TIMER2_INTERRUPT		28	/* CCOMPARE2 */
-#define XCHAL_TIMER3_INTERRUPT		XTHAL_TIMER_UNCONFIGURED
-#define XCHAL_NMI_INTERRUPT		25	/* non-maskable interrupt */
-#define XCHAL_WRITE_ERROR_INTERRUPT	30
-#define XCHAL_PROFILING_INTERRUPT	29
-
-/*  Interrupt numbers for levels at which only one interrupt is configured:  */
-#define XCHAL_INTLEVEL6_NUM		25
-/*  (There are many interrupts each at level(s) 1, 2, 3, 4.)  */
-
-
-/*
- *  External interrupt mapping.
- *  These macros describe how Xtensa processor interrupt numbers
- *  (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
- *  map to external BInterrupt<n> pins, for those interrupts
- *  configured as external (level-triggered, edge-triggered, or NMI).
- *  See the Xtensa processor databook for more details.
- */
-
-/*  Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number:  */
-#define XCHAL_EXTINT0_NUM		0	/* (intlevel 1) */
-#define XCHAL_EXTINT1_NUM		1	/* (intlevel 1) */
-#define XCHAL_EXTINT2_NUM		2	/* (intlevel 1) */
-#define XCHAL_EXTINT3_NUM		3	/* (intlevel 1) */
-#define XCHAL_EXTINT4_NUM		4	/* (intlevel 1) */
-#define XCHAL_EXTINT5_NUM		5	/* (intlevel 1) */
-#define XCHAL_EXTINT6_NUM		6	/* (intlevel 1) */
-#define XCHAL_EXTINT7_NUM		7	/* (intlevel 1) */
-#define XCHAL_EXTINT8_NUM		8	/* (intlevel 2) */
-#define XCHAL_EXTINT9_NUM		9	/* (intlevel 2) */
-#define XCHAL_EXTINT10_NUM		10	/* (intlevel 2) */
-#define XCHAL_EXTINT11_NUM		11	/* (intlevel 2) */
-#define XCHAL_EXTINT12_NUM		12	/* (intlevel 2) */
-#define XCHAL_EXTINT13_NUM		13	/* (intlevel 2) */
-#define XCHAL_EXTINT14_NUM		14	/* (intlevel 2) */
-#define XCHAL_EXTINT15_NUM		15	/* (intlevel 2) */
-#define XCHAL_EXTINT16_NUM		16	/* (intlevel 3) */
-#define XCHAL_EXTINT17_NUM		17	/* (intlevel 3) */
-#define XCHAL_EXTINT18_NUM		18	/* (intlevel 3) */
-#define XCHAL_EXTINT19_NUM		19	/* (intlevel 3) */
-#define XCHAL_EXTINT20_NUM		20	/* (intlevel 4) */
-#define XCHAL_EXTINT21_NUM		21	/* (intlevel 4) */
-#define XCHAL_EXTINT22_NUM		22	/* (intlevel 4) */
-#define XCHAL_EXTINT23_NUM		23	/* (intlevel 3) */
-#define XCHAL_EXTINT24_NUM		24	/* (intlevel 3) */
-#define XCHAL_EXTINT25_NUM		25	/* (intlevel 6) */
-/*  EXTERNAL BInterrupt pin numbers mapped to each core interrupt number:  */
-#define XCHAL_INT0_EXTNUM		0	/* (intlevel 1) */
-#define XCHAL_INT1_EXTNUM		1	/* (intlevel 1) */
-#define XCHAL_INT2_EXTNUM		2	/* (intlevel 1) */
-#define XCHAL_INT3_EXTNUM		3	/* (intlevel 1) */
-#define XCHAL_INT4_EXTNUM		4	/* (intlevel 1) */
-#define XCHAL_INT5_EXTNUM		5	/* (intlevel 1) */
-#define XCHAL_INT6_EXTNUM		6	/* (intlevel 1) */
-#define XCHAL_INT7_EXTNUM		7	/* (intlevel 1) */
-#define XCHAL_INT8_EXTNUM		8	/* (intlevel 2) */
-#define XCHAL_INT9_EXTNUM		9	/* (intlevel 2) */
-#define XCHAL_INT10_EXTNUM		10	/* (intlevel 2) */
-#define XCHAL_INT11_EXTNUM		11	/* (intlevel 2) */
-#define XCHAL_INT12_EXTNUM		12	/* (intlevel 2) */
-#define XCHAL_INT13_EXTNUM		13	/* (intlevel 2) */
-#define XCHAL_INT14_EXTNUM		14	/* (intlevel 2) */
-#define XCHAL_INT15_EXTNUM		15	/* (intlevel 2) */
-#define XCHAL_INT16_EXTNUM		16	/* (intlevel 3) */
-#define XCHAL_INT17_EXTNUM		17	/* (intlevel 3) */
-#define XCHAL_INT18_EXTNUM		18	/* (intlevel 3) */
-#define XCHAL_INT19_EXTNUM		19	/* (intlevel 3) */
-#define XCHAL_INT20_EXTNUM		20	/* (intlevel 4) */
-#define XCHAL_INT21_EXTNUM		21	/* (intlevel 4) */
-#define XCHAL_INT22_EXTNUM		22	/* (intlevel 4) */
-#define XCHAL_INT23_EXTNUM		23	/* (intlevel 3) */
-#define XCHAL_INT24_EXTNUM		24	/* (intlevel 3) */
-#define XCHAL_INT25_EXTNUM		25	/* (intlevel 6) */
-
-#define	XCHAL_HAVE_ISB			0	/* No ISB */
-#define	XCHAL_ISB_VADDR			0	/* N/A    */
-#define	XCHAL_HAVE_ITB			0	/* No ITB */
-#define	XCHAL_ITB_VADDR			0	/* N/A    */
-
-#define	XCHAL_HAVE_KSL			0	/* Kernel Stack Limit */
-#define	XCHAL_HAVE_ISL			0	/* Interrupt Stack Limit */
-#define	XCHAL_HAVE_PSL			0	/* Pageable Stack Limit */
-
-
-/*----------------------------------------------------------------------
-			EXCEPTIONS and VECTORS
-  ----------------------------------------------------------------------*/
-
-#define XCHAL_XEA_VERSION		2	/* Xtensa Exception Architecture
-						   number: 1 == XEA1 (until T1050)
-							   2 == XEA2 (T1040 onwards)
-							   3 == XEA3 (LX8/NX/SX onwards)
-							   0 == XEAX (extern) or TX */
-#define XCHAL_HAVE_XEA1			0	/* Exception Architecture 1 */
-#define XCHAL_HAVE_XEA2			1	/* Exception Architecture 2 */
-#define XCHAL_HAVE_XEA3			0	/* Exception Architecture 3 */
-#define XCHAL_HAVE_XEAX			0	/* External Exception Arch. */
-#define XCHAL_HAVE_EXCEPTIONS		1	/* exception option */
-#define XCHAL_HAVE_IMPRECISE_EXCEPTIONS	0	/* imprecise exception option */
-#define	XCHAL_EXCCAUSE_NUM		64	/* Number of exceptions */
-#define XCHAL_HAVE_HALT			0	/* halt architecture option */
-#define XCHAL_HAVE_BOOTLOADER		0	/* boot loader (for TX) */
-#define XCHAL_HAVE_MEM_ECC_PARITY	0	/* local memory ECC/parity */
-#define XCHAL_HAVE_VECTOR_SELECT	1	/* relocatable vectors */
-#define XCHAL_HAVE_VECBASE		1	/* relocatable vectors */
-#define XCHAL_VECBASE_RESET_VADDR	0x4e100400  /* VECBASE reset value */
-#define XCHAL_VECBASE_RESET_PADDR	0x4e100400
-#define XCHAL_RESET_VECBASE_OVERLAP	0	/* UNUSED */
-
-#define XCHAL_RESET_VECTOR0_VADDR	0x4e100000
-#define XCHAL_RESET_VECTOR0_PADDR	0x4e100000
-#define XCHAL_RESET_VECTOR1_VADDR	0x4e100800
-#define XCHAL_RESET_VECTOR1_PADDR	0x4e100800
-#define XCHAL_RESET_VECTOR_VADDR	XCHAL_RESET_VECTOR1_VADDR
-#define XCHAL_RESET_VECTOR_PADDR	XCHAL_RESET_VECTOR1_PADDR
-#define XCHAL_USER_VECOFS		0x00000250
-#define XCHAL_USER_VECTOR_VADDR		0x4e100650
-#define XCHAL_USER_VECTOR_PADDR		0x4e100650
-#define XCHAL_KERNEL_VECOFS		0x00000230
-#define XCHAL_KERNEL_VECTOR_VADDR	0x4e100630
-#define XCHAL_KERNEL_VECTOR_PADDR	0x4e100630
-#define XCHAL_DOUBLEEXC_VECOFS		0x00000270
-#define XCHAL_DOUBLEEXC_VECTOR_VADDR	0x4e100670
-#define XCHAL_DOUBLEEXC_VECTOR_PADDR	0x4e100670
-#define XCHAL_WINDOW_OF4_VECOFS		0x00000000
-#define XCHAL_WINDOW_UF4_VECOFS		0x00000040
-#define XCHAL_WINDOW_OF8_VECOFS		0x00000080
-#define XCHAL_WINDOW_UF8_VECOFS		0x000000C0
-#define XCHAL_WINDOW_OF12_VECOFS	0x00000100
-#define XCHAL_WINDOW_UF12_VECOFS	0x00000140
-#define XCHAL_WINDOW_VECTORS_VADDR	0x4e100400
-#define XCHAL_WINDOW_VECTORS_PADDR	0x4e100400
-#define XCHAL_INTLEVEL2_VECOFS		0x00000180
-#define XCHAL_INTLEVEL2_VECTOR_VADDR	0x4e100580
-#define XCHAL_INTLEVEL2_VECTOR_PADDR	0x4e100580
-#define XCHAL_INTLEVEL3_VECOFS		0x000001A4
-#define XCHAL_INTLEVEL3_VECTOR_VADDR	0x4e1005A4
-#define XCHAL_INTLEVEL3_VECTOR_PADDR	0x4e1005A4
-#define XCHAL_INTLEVEL4_VECOFS		0x000001C8
-#define XCHAL_INTLEVEL4_VECTOR_VADDR	0x4e1005C8
-#define XCHAL_INTLEVEL4_VECTOR_PADDR	0x4e1005C8
-#define XCHAL_INTLEVEL5_VECOFS		0x000001EC
-#define XCHAL_INTLEVEL5_VECTOR_VADDR	0x4e1005EC
-#define XCHAL_INTLEVEL5_VECTOR_PADDR	0x4e1005EC
-#define XCHAL_DEBUG_VECOFS		XCHAL_INTLEVEL5_VECOFS
-#define XCHAL_DEBUG_VECTOR_VADDR	XCHAL_INTLEVEL5_VECTOR_VADDR
-#define XCHAL_DEBUG_VECTOR_PADDR	XCHAL_INTLEVEL5_VECTOR_PADDR
-#define XCHAL_NMI_VECOFS		0x00000210
-#define XCHAL_NMI_VECTOR_VADDR		0x4e100610
-#define XCHAL_NMI_VECTOR_PADDR		0x4e100610
-#define XCHAL_INTLEVEL6_VECOFS		XCHAL_NMI_VECOFS
-#define XCHAL_INTLEVEL6_VECTOR_VADDR	XCHAL_NMI_VECTOR_VADDR
-#define XCHAL_INTLEVEL6_VECTOR_PADDR	XCHAL_NMI_VECTOR_PADDR
-
-
-/*----------------------------------------------------------------------
-				DEBUG MODULE
-  ----------------------------------------------------------------------*/
-
-/*  Misc  */
-#define XCHAL_HAVE_DEBUG_ERI		1	/* ERI to debug module */
-#define XCHAL_HAVE_DEBUG_APB		1	/* APB to debug module */
-#define XCHAL_HAVE_DEBUG_JTAG		1	/* JTAG to debug module */
-
-/*  On-Chip Debug (OCD)  */
-#define XCHAL_HAVE_OCD			1	/* OnChipDebug option */
-#define XCHAL_NUM_IBREAK		2	/* number of IBREAKn regs */
-#define XCHAL_NUM_DBREAK		2	/* number of DBREAKn regs */
-#define XCHAL_HAVE_OCD_DIR_ARRAY	0	/* faster OCD option (to LX4) */
-#define XCHAL_HAVE_OCD_LS32DDR		1	/* L32DDR/S32DDR (faster OCD) */
-
-/*  TRAX (in core)  */
-#define XCHAL_HAVE_TRAX			1	/* TRAX in debug module */
-#define XCHAL_TRAX_MEM_SIZE		4096	/* TRAX memory size in bytes */
-#define XCHAL_TRAX_MEM_SHAREABLE	1	/* start/end regs; ready sig. */
-#define XCHAL_TRAX_ATB_WIDTH		32	/* ATB width (bits), 0=no ATB */
-#define XCHAL_TRAX_TIME_WIDTH		64	/* timestamp bitwidth, 0=none */
-
-/*  Perf counters  */
-#define XCHAL_NUM_PERF_COUNTERS		8	/* performance counters */
-
-
-/*----------------------------------------------------------------------
-				MMU
-  ----------------------------------------------------------------------*/
-
-/*  See core-matmap.h header file for more details.  */
-
-#define XCHAL_HAVE_TLBS			0	/* inverse of HAVE_CACHEATTR */
-#define XCHAL_HAVE_SPANNING_WAY		0	/* one way maps I+D 4GB vaddr */
-#define XCHAL_HAVE_IDENTITY_MAP		1	/* vaddr == paddr always */
-#define XCHAL_HAVE_CACHEATTR		0	/* CACHEATTR register present */
-#define XCHAL_HAVE_MIMIC_CACHEATTR	0	/* region protection */
-#define XCHAL_HAVE_XLT_CACHEATTR	0	/* region prot. w/translation */
-#define XCHAL_HAVE_PTP_MMU		0	/* full MMU (with page table
-						   [autorefill] and protection)
-						   usable for an MMU-based OS */
-
-/*  If none of the above last 5 are set, it's a custom TLB configuration.  */
-
-#define XCHAL_MMU_ASID_BITS		0	/* number of bits in ASIDs */
-#define XCHAL_MMU_RINGS			1	/* number of rings (1..4) */
-#define XCHAL_MMU_RING_BITS		0	/* num of bits in RING field */
-
-/*----------------------------------------------------------------------
-				MPU
-  ----------------------------------------------------------------------*/
-#define XCHAL_HAVE_MPU			1 
-#define XCHAL_MPU_ENTRIES		32
-#define XCHAL_MPU_LOCK			0
-
-#define XCHAL_MPU_ALIGN_REQ		1	/* MPU requires alignment of entries to background map */
-#define XCHAL_MPU_BACKGROUND_ENTRIES	2	/* number of entries in bg map*/
-#define XCHAL_MPU_BG_CACHEADRDIS	0xFF	/* default CACHEADRDIS for bg */
- 
-#define XCHAL_MPU_ALIGN_BITS		12
-#define XCHAL_MPU_ALIGN			4096
-
-/*-----------------------------------------------------------------------
-				CSR Parity
-------------------------------------------------------------------------*/
-#define XCHAL_HAVE_CSR_PARITY		0
-
-
-/*----------------------------------------------------------------------
-				FLEX-LOCK
-------------------------------------------------------------------------*/
-
-#define XCHAL_HAVE_FXLK			0
-
-/*----------------------------------------------------------------------
-				WWDT (Windowed Watchdog Timer)
-------------------------------------------------------------------------*/
-#define XCHAL_HAVE_WWDT			0
-#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
-
-
-#endif /* XTENSA_CORE_CONFIGURATION_H_ */
-
diff --git a/src/platform/mt8188/include/arch/xtensa/config/core-matmap.h b/src/platform/mt8188/include/arch/xtensa/config/core-matmap.h
deleted file mode 100644
index 8a0056ca9c21..000000000000
--- a/src/platform/mt8188/include/arch/xtensa/config/core-matmap.h
+++ /dev/null
@@ -1,106 +0,0 @@
-/* 
- * xtensa/config/core-matmap.h -- Memory access and translation mapping
- *	parameters (CHAL) of the Xtensa processor core configuration.
- *
- *  If you are using Xtensa Tools, see <xtensa/config/core.h> (which includes
- *  this file) for more details.
- *
- *  In the Xtensa processor products released to date, all parameters
- *  defined in this file are derivable (at least in theory) from
- *  information contained in the core-isa.h header file.
- *  In particular, the following core configuration parameters are relevant:
- *	XCHAL_HAVE_CACHEATTR
- *	XCHAL_HAVE_MIMIC_CACHEATTR
- *	XCHAL_HAVE_XLT_CACHEATTR
- *	XCHAL_HAVE_PTP_MMU
- *	XCHAL_ITLB_ARF_ENTRIES_LOG2
- *	XCHAL_DTLB_ARF_ENTRIES_LOG2
- *	XCHAL_DCACHE_IS_WRITEBACK
- *	XCHAL_ICACHE_SIZE		(presence of I-cache)
- *	XCHAL_DCACHE_SIZE		(presence of D-cache)
- *	XCHAL_HW_VERSION_MAJOR
- *	XCHAL_HW_VERSION_MINOR
- */
-
-/* Customer ID=16990; Build=0x904d8; Copyright (c) 1999-2020 Tensilica Inc.
-
-   Permission is hereby granted, free of charge, to any person obtaining
-   a copy of this software and associated documentation files (the
-   "Software"), to deal in the Software without restriction, including
-   without limitation the rights to use, copy, modify, merge, publish,
-   distribute, sublicense, and/or sell copies of the Software, and to
-   permit persons to whom the Software is furnished to do so, subject to
-   the following conditions:
-
-   The above copyright notice and this permission notice shall be included
-   in all copies or substantial portions of the Software.
-
-   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
-
-
-#ifndef XTENSA_CONFIG_CORE_MATMAP_H
-#define XTENSA_CONFIG_CORE_MATMAP_H
-
-
-/*----------------------------------------------------------------------
-			CACHE (MEMORY ACCESS) ATTRIBUTES
-  ----------------------------------------------------------------------*/
-/*----------------------------------------------------------------------
-				MPU
-  ----------------------------------------------------------------------*/
-
-/* Mappings for legacy constants where appropriate */
-
-#define XCHAL_CA_WRITEBACK (XTHAL_MEM_WRITEBACK | XTHAL_AR_RWXrwx)
-
-#define XCHAL_CA_WRITEBACK_NOALLOC (XTHAL_MEM_WRITEBACK_NOALLOC| XTHAL_AR_RWXrwx )
-
-#define XCHAL_CA_WRITETHRU (XTHAL_MEM_WRITETHRU | XTHAL_AR_RWXrwx)
-
-#define XCHAL_CA_ILLEGAL   (XTHAL_AR_NONE   | XTHAL_MEM_DEVICE)
-#define XCHAL_CA_BYPASS    (XTHAL_AR_RWXrwx | XTHAL_MEM_DEVICE)
-#define XCHAL_CA_BYPASSBUF    (XTHAL_AR_RWXrwx | XTHAL_MEM_DEVICE |\
-        XTHAL_MEM_BUFFERABLE)
-#define XCHAL_CA_BYPASS_RX (XTHAL_AR_RX     | XTHAL_MEM_DEVICE)
-#define XCHAL_CA_BYPASS_RW (XTHAL_AR_RW     | XTHAL_MEM_DEVICE)
-#define XCHAL_CA_BYPASS_R  (XTHAL_AR_R      | XTHAL_MEM_DEVICE)
-#define XCHAL_HAVE_CA_WRITEBACK_NOALLOC 1
-
-#define XCHAL_CA_R  (XTHAL_AR_R)
-#define XCHAL_CA_RX (XTHAL_AR_RX) 
-#define XCHAL_CA_RW (XTHAL_AR_RW) 
-#define XCHAL_CA_RWX (XTHAL_AR_RWX)
-
-
-/* 
- * Contents of MPU background map.
- * NOTE:  caller must define the XCHAL_MPU_BGMAP() macro (not defined here
- * but specified below) before expanding the XCHAL_MPU_BACKGROUND_MAP(s) macro.
- *
- * XCHAL_MPU_BGMAP(s, vaddr_start, vaddr_last, rights, memtype, x...)
- *
- *	s = passed from XCHAL_MPU_BACKGROUND_MAP(s), eg. to select how to expand
- *	vaddr_start = first byte of region (always 0 for first entry)
- *	vaddr_end = last byte of region (always 0xFFFFFFFF for last entry)
- *	rights = access rights
- *	memtype = memory type
- *	x = reserved for future use (0 until then)
- */
-/* parasoft-begin-suppress MISRA2012-RULE-20_7 "Macro use model requires s to not be in ()" */
-#define XCHAL_MPU_BACKGROUND_MAP(s) \
-	XCHAL_MPU_BGMAP(s, 0x00000000, 0x7fffffff,  7,   6, 0) \
-	XCHAL_MPU_BGMAP(s, 0x80000000, 0xffffffff,  7,   6, 0) \
-/* parasoft-end-suppress MISRA2012-RULE-20_7 "Macro use model requires s to not be in ()" */
-
-	/* end */
-
-
-
-#endif /*XTENSA_CONFIG_CORE_MATMAP_H*/
-
diff --git a/src/platform/mt8188/include/arch/xtensa/config/defs.h b/src/platform/mt8188/include/arch/xtensa/config/defs.h
deleted file mode 100644
index be3cf59f6756..000000000000
--- a/src/platform/mt8188/include/arch/xtensa/config/defs.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/* Definitions for Xtensa instructions, types, and protos. */
-
-/* Customer ID=16990; Build=0x904d8; Copyright (c) 2003-2004 Tensilica Inc.
-
-   Permission is hereby granted, free of charge, to any person obtaining
-   a copy of this software and associated documentation files (the
-   "Software"), to deal in the Software without restriction, including
-   without limitation the rights to use, copy, modify, merge, publish,
-   distribute, sublicense, and/or sell copies of the Software, and to
-   permit persons to whom the Software is furnished to do so, subject to
-   the following conditions:
-
-   The above copyright notice and this permission notice shall be included
-   in all copies or substantial portions of the Software.
-
-   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
-
-/* NOTE: This file exists only for backward compatibility with T1050
-   and earlier Xtensa releases.  It includes only a subset of the
-   available header files.  */
-
-#ifndef _XTENSA_BASE_HEADER
-#define _XTENSA_BASE_HEADER
-
-#ifdef __XTENSA__
-
-#include <xtensa/tie/xt_core.h>
-#include <xtensa/tie/xt_misc.h>
-#include <xtensa/tie/xt_booleans.h>
-
-#endif /* __XTENSA__ */
-#endif /* !_XTENSA_BASE_HEADER */
diff --git a/src/platform/mt8188/include/arch/xtensa/config/key.h b/src/platform/mt8188/include/arch/xtensa/config/key.h
deleted file mode 100644
index 8b137891791f..000000000000
--- a/src/platform/mt8188/include/arch/xtensa/config/key.h
+++ /dev/null
@@ -1 +0,0 @@
-
diff --git a/src/platform/mt8188/include/arch/xtensa/config/secure.h b/src/platform/mt8188/include/arch/xtensa/config/secure.h
deleted file mode 100644
index 561b2133c98e..000000000000
--- a/src/platform/mt8188/include/arch/xtensa/config/secure.h
+++ /dev/null
@@ -1,48 +0,0 @@
-
-/* Secure Mode defines. */
-
-/* Customer ID=16990; Build=0x904d8; Copyright (c) 2020 Cadence Design Systems, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef XTENSA_SECURE_H
-#define XTENSA_SECURE_H
-
-
-/* SRAM */
-#define XCHAL_HAVE_SECURE_SRAM	0
-
-/* INSTRAM0 */
-#define XCHAL_HAVE_SECURE_INSTRAM0	0
-
-/* INSTRAM1 */
-#define XCHAL_HAVE_SECURE_INSTRAM1	0
-
-/* DATARAM0 */
-#define XCHAL_HAVE_SECURE_DATARAM0	0
-
-/* Array of all secure regions' start/size */
-#define XCHAL_SECURE_MEM_LIST \
-{ \
-}
-
-#endif /* XTENSA_SECURE_H */
-
diff --git a/src/platform/mt8188/include/arch/xtensa/config/specreg.h b/src/platform/mt8188/include/arch/xtensa/config/specreg.h
deleted file mode 100644
index 7e4ed373ecc1..000000000000
--- a/src/platform/mt8188/include/arch/xtensa/config/specreg.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * Xtensa Special Register symbolic names
- */
-
-/* $Id: //depot/rel/Homewood/ib.5/Xtensa/SWConfig/hal/specreg.h.tpp#1 $ */
-
-/* Customer ID=16990; Build=0x904d8; Copyright (c) 1998-2002 Tensilica Inc.
-
-   Permission is hereby granted, free of charge, to any person obtaining
-   a copy of this software and associated documentation files (the
-   "Software"), to deal in the Software without restriction, including
-   without limitation the rights to use, copy, modify, merge, publish,
-   distribute, sublicense, and/or sell copies of the Software, and to
-   permit persons to whom the Software is furnished to do so, subject to
-   the following conditions:
-
-   The above copyright notice and this permission notice shall be included
-   in all copies or substantial portions of the Software.
-
-   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
-
-#ifndef XTENSA_SPECREG_H
-#define XTENSA_SPECREG_H
-
-/*  Include these special register bitfield definitions, for historical reasons:  */
-#include <xtensa/corebits.h>
-
-
-/*  Special registers:  */
-#define LBEG		0
-#define LEND		1
-#define LCOUNT		2
-#define SAR		3
-#define BR		4
-#define PREFCTL		40
-#define WINDOWBASE	72
-#define WINDOWSTART	73
-#define MPUENB		90
-#define ERACCESS	95
-#define IBREAKENABLE	96
-#define MEMCTL		97
-#define CACHEADRDIS	98
-#define DDR		104
-#define IBREAKA_0	128
-#define IBREAKA_1	129
-#define DBREAKA_0	144
-#define DBREAKA_1	145
-#define DBREAKC_0	160
-#define DBREAKC_1	161
-#define EPC_1		177
-#define EPC_2		178
-#define EPC_3		179
-#define EPC_4		180
-#define EPC_5		181
-#define EPC_6		182
-#define DEPC		192
-#define EPS_2		194
-#define EPS_3		195
-#define EPS_4		196
-#define EPS_5		197
-#define EPS_6		198
-#define EXCSAVE_1	209
-#define EXCSAVE_2	210
-#define EXCSAVE_3	211
-#define EXCSAVE_4	212
-#define EXCSAVE_5	213
-#define EXCSAVE_6	214
-#define CPENABLE	224
-#define INTERRUPT	226
-#define INTENABLE	228
-#define PS		230
-#define VECBASE		231
-#define EXCCAUSE	232
-#define DEBUGCAUSE	233
-#define CCOUNT		234
-#define PRID		235
-#define ICOUNT		236
-#define ICOUNTLEVEL	237
-#define EXCVADDR	238
-#define CCOMPARE_0	240
-#define CCOMPARE_1	241
-#define CCOMPARE_2	242
-#define MISC_REG_0	244
-#define MISC_REG_1	245
-#define MISC_REG_2	246
-#define MISC_REG_3	247
-
-
-/*  Special cases (bases of special register series):  */
-#define IBREAKA		128
-#define DBREAKA		144
-#define DBREAKC		160
-#define EPC		176
-#define EPS		192
-#define EXCSAVE		208
-#define CCOMPARE	240
-
-/*  Special names for read-only and write-only interrupt registers:  */
-#define INTREAD		226
-#define INTSET		226
-#define INTCLEAR	227
-
-#endif /* XTENSA_SPECREG_H */
-
diff --git a/src/platform/mt8188/include/arch/xtensa/config/system.h b/src/platform/mt8188/include/arch/xtensa/config/system.h
deleted file mode 100644
index e92cc4ad0433..000000000000
--- a/src/platform/mt8188/include/arch/xtensa/config/system.h
+++ /dev/null
@@ -1,254 +0,0 @@
-/* 
- * xtensa/config/system.h -- HAL definitions that are dependent on SYSTEM configuration
- *
- *  NOTE: The location and contents of this file are highly subject to change.
- *
- *  Source for configuration-independent binaries (which link in a
- *  configuration-specific HAL library) must NEVER include this file.
- *  The HAL itself has historically included this file in some instances,
- *  but this is not appropriate either, because the HAL is meant to be
- *  core-specific but system independent.
- */
-
-/* Customer ID=16990; Build=0x904d8; Copyright (c) 2000-2010 Tensilica Inc.
-
-   Permission is hereby granted, free of charge, to any person obtaining
-   a copy of this software and associated documentation files (the
-   "Software"), to deal in the Software without restriction, including
-   without limitation the rights to use, copy, modify, merge, publish,
-   distribute, sublicense, and/or sell copies of the Software, and to
-   permit persons to whom the Software is furnished to do so, subject to
-   the following conditions:
-
-   The above copyright notice and this permission notice shall be included
-   in all copies or substantial portions of the Software.
-
-   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
-
-
-#ifndef XTENSA_CONFIG_SYSTEM_H
-#define XTENSA_CONFIG_SYSTEM_H
-
-
-/*----------------------------------------------------------------------
-				CONFIGURED SOFTWARE OPTIONS
-  ----------------------------------------------------------------------*/
-
-#define XSHAL_USE_ABSOLUTE_LITERALS	0	/* (sw-only option, whether software uses absolute literals) */
-#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals.  */
-
-#define XSHAL_ABI			XTHAL_ABI_WINDOWED	/* (sw-only option, selected ABI) */
-/*  The above maps to one of the following constants:  */
-#define XTHAL_ABI_WINDOWED		0
-#define XTHAL_ABI_CALL0			1
-
-#define XSHAL_CLIB			XTHAL_CLIB_XCLIB	/* (sw-only option, selected C library) */
-/*  The above maps to one of the following constants:  */
-#define XTHAL_CLIB_NEWLIB		0
-#define XTHAL_CLIB_UCLIBC		1
-#define XTHAL_CLIB_XCLIB		2
-
-#define XSHAL_USE_FLOATING_POINT	1
-
-#define XSHAL_FLOATING_POINT_ABI        1
-
-/*  SW workarounds enabled for HW errata:  */
-
-/*----------------------------------------------------------------------
-				DEVICE ADDRESSES
-  ----------------------------------------------------------------------*/
-
-/*
- *  Strange place to find these, but the configuration GUI
- *  allows moving these around to account for various core
- *  configurations.  Specific boards (and their BSP software)
- *  will have specific meanings for these components.
- */
-
-/*  I/O Block areas:  */
-#define XSHAL_IOBLOCK_CACHED_VADDR	0x70000000
-#define XSHAL_IOBLOCK_CACHED_PADDR	0x70000000
-#define XSHAL_IOBLOCK_CACHED_SIZE	0x0E000000
-
-#define XSHAL_IOBLOCK_BYPASS_VADDR	0x90000000
-#define XSHAL_IOBLOCK_BYPASS_PADDR	0x90000000
-#define XSHAL_IOBLOCK_BYPASS_SIZE	0x0E000000
-
-/*  System ROM:  */
-
-/*  System RAM:  */
-#define XSHAL_RAM_VADDR		0x40000000
-#define XSHAL_RAM_PADDR		0x40000000
-#define XSHAL_RAM_VSIZE		0x80000000
-#define XSHAL_RAM_PSIZE		0x80000000
-#define XSHAL_RAM_SIZE		XSHAL_RAM_PSIZE
-/*  Largest available area (free of vectors):  */
-#define XSHAL_RAM_AVAIL_VADDR	0x40000AE0
-#define XSHAL_RAM_AVAIL_VSIZE	0x7FFFF520
-
-/*
- *  Shadow system RAM (same device as system RAM, at different address).
- *  (Emulation boards need this for the SONIC Ethernet driver
- *   when data caches are configured for writeback mode.)
- *  NOTE: on full MMU configs, this points to the BYPASS virtual address
- *  of system RAM, ie. is the same as XSHAL_RAM_* except that virtual
- *  addresses are viewed through the BYPASS static map rather than
- *  the CACHED static map.
- */
-#define XSHAL_RAM_BYPASS_VADDR		0xC0000000
-#define XSHAL_RAM_BYPASS_PADDR		0xC0000000
-#define XSHAL_RAM_BYPASS_PSIZE		0x20000000
-
-/*  Alternate system RAM (different device than system RAM):  */
-
-/*  Some available location in which to place devices in a simulation (eg. XTMP):  */
-#define XSHAL_SIMIO_CACHED_VADDR	0xC0000000
-#define XSHAL_SIMIO_BYPASS_VADDR	0xC0000000
-#define XSHAL_SIMIO_PADDR		0xC0000000
-#define XSHAL_SIMIO_SIZE		0x20000000
-
-
-/*----------------------------------------------------------------------
- *  For use by reference testbench exit and diagnostic routines.
- */
-#define XSHAL_MAGIC_EXIT		0xdeed2000
-#define XSHAL_STL_INFO_LOCATION		0xfffffffc
-
-/*----------------------------------------------------------------------
- *			DEVICE-ADDRESS DEPENDENT...
- *
- *  Values written to CACHEATTR special register (or its equivalent)
- *  to enable and disable caches in various modes.
- *----------------------------------------------------------------------*/
-
-/*----------------------------------------------------------------------
-			BACKWARD COMPATIBILITY ...
-  ----------------------------------------------------------------------*/
-
-/*
- *  NOTE:  the following two macros are DEPRECATED.  Use the latter
- *  board-specific macros instead, which are specially tuned for the
- *  particular target environments' memory maps.
- */
-#define XSHAL_CACHEATTR_BYPASS		XSHAL_XT2000_CACHEATTR_BYPASS	/* disable caches in bypass mode */
-#define XSHAL_CACHEATTR_DEFAULT		XSHAL_XT2000_CACHEATTR_DEFAULT	/* default setting to enable caches (no writeback!) */
-
-/*----------------------------------------------------------------------
-				GENERIC
-  ----------------------------------------------------------------------*/
-
-/*  For the following, a 512MB region is used if it contains a system (PIF) RAM,
- *  system (PIF) ROM, local memory, or XLMI.  */
-
-/*  These set any unused 512MB region to cache-BYPASS attribute:  */
-#define XSHAL_ALLVALID_CACHEATTR_WRITEBACK	0x22444442	/* enable caches in write-back mode */
-#define XSHAL_ALLVALID_CACHEATTR_WRITEALLOC	0x22111112	/* enable caches in write-allocate mode */
-#define XSHAL_ALLVALID_CACHEATTR_WRITETHRU	0x22111112	/* enable caches in write-through mode */
-#define XSHAL_ALLVALID_CACHEATTR_BYPASS		0x22222222	/* disable caches in bypass mode */
-#define XSHAL_ALLVALID_CACHEATTR_DEFAULT	XSHAL_ALLVALID_CACHEATTR_WRITEBACK	/* default setting to enable caches */
-
-/*  These set any unused 512MB region to ILLEGAL attribute:  */
-#define XSHAL_STRICT_CACHEATTR_WRITEBACK	0xFF44444F	/* enable caches in write-back mode */
-#define XSHAL_STRICT_CACHEATTR_WRITEALLOC	0xFF11111F	/* enable caches in write-allocate mode */
-#define XSHAL_STRICT_CACHEATTR_WRITETHRU	0xFF11111F	/* enable caches in write-through mode */
-#define XSHAL_STRICT_CACHEATTR_BYPASS		0xFF22222F	/* disable caches in bypass mode */
-#define XSHAL_STRICT_CACHEATTR_DEFAULT		XSHAL_STRICT_CACHEATTR_WRITEBACK	/* default setting to enable caches */
-
-/*  These set the first 512MB, if unused, to ILLEGAL attribute to help catch
- *  NULL-pointer dereference bugs; all other unused 512MB regions are set
- *  to cache-BYPASS attribute:  */
-#define XSHAL_TRAPNULL_CACHEATTR_WRITEBACK	0x2244444F	/* enable caches in write-back mode */
-#define XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC	0x2211111F	/* enable caches in write-allocate mode */
-#define XSHAL_TRAPNULL_CACHEATTR_WRITETHRU	0x2211111F	/* enable caches in write-through mode */
-#define XSHAL_TRAPNULL_CACHEATTR_BYPASS		0x2222222F	/* disable caches in bypass mode */
-#define XSHAL_TRAPNULL_CACHEATTR_DEFAULT	XSHAL_TRAPNULL_CACHEATTR_WRITEBACK	/* default setting to enable caches */
-
-/*----------------------------------------------------------------------
-			ISS (Instruction Set Simulator) SPECIFIC ...
-  ----------------------------------------------------------------------*/
-
-/*  For now, ISS defaults to the TRAPNULL settings:  */
-#define XSHAL_ISS_CACHEATTR_WRITEBACK	XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
-#define XSHAL_ISS_CACHEATTR_WRITEALLOC	XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC
-#define XSHAL_ISS_CACHEATTR_WRITETHRU	XSHAL_TRAPNULL_CACHEATTR_WRITETHRU
-#define XSHAL_ISS_CACHEATTR_BYPASS	XSHAL_TRAPNULL_CACHEATTR_BYPASS
-#define XSHAL_ISS_CACHEATTR_DEFAULT	XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
-
-#define XSHAL_ISS_PIPE_REGIONS	0
-#define XSHAL_ISS_SDRAM_REGIONS	0
-
-
-/*----------------------------------------------------------------------
-			XT2000 BOARD SPECIFIC ...
-  ----------------------------------------------------------------------*/
-
-/*  For the following, a 512MB region is used if it contains any system RAM,
- *  system ROM, local memory, XLMI, or other XT2000 board device or memory.
- *  Regions containing devices are forced to cache-BYPASS mode regardless
- *  of whether the macro is _WRITEBACK vs. _BYPASS etc.  */
-
-/*  These set any 512MB region unused on the XT2000 to ILLEGAL attribute:  */
-#define XSHAL_XT2000_CACHEATTR_WRITEBACK	0xF242444F	/* enable caches in write-back mode */
-#define XSHAL_XT2000_CACHEATTR_WRITEALLOC	0xF212111F	/* enable caches in write-allocate mode */
-#define XSHAL_XT2000_CACHEATTR_WRITETHRU	0xF212111F	/* enable caches in write-through mode */
-#define XSHAL_XT2000_CACHEATTR_BYPASS		0xF222222F	/* disable caches in bypass mode */
-#define XSHAL_XT2000_CACHEATTR_DEFAULT		XSHAL_XT2000_CACHEATTR_WRITEBACK	/* default setting to enable caches */
-
-#define XSHAL_XT2000_PIPE_REGIONS	0x00000000	/* BusInt pipeline regions */
-#define XSHAL_XT2000_SDRAM_REGIONS	0x00001010	/* BusInt SDRAM regions */
-
-
-/*----------------------------------------------------------------------
-				VECTOR INFO AND SIZES
-  ----------------------------------------------------------------------*/
-
-#define XSHAL_VECTORS_PACKED		0	/* UNUSED */
-#define XSHAL_STATIC_VECTOR_SELECT	1
-#define XSHAL_RESET_VECTOR_VADDR	0x40000800
-#define XSHAL_RESET_VECTOR_PADDR	0x40000800
-
-/*
- *  Sizes allocated to vectors by the system (memory map) configuration.
- *  These sizes are constrained by core configuration (eg. one vector's
- *  code cannot overflow into another vector) but are dependent on the
- *  system or board (or LSP) memory map configuration.
- *
- *  Whether or not each vector happens to be in a system ROM is also
- *  a system configuration matter, sometimes useful, included here also:
- */
-#define XSHAL_RESET_VECTOR_SIZE	0x000002E0
-#define XSHAL_RESET_VECTOR_ISROM	0
-#define XSHAL_USER_VECTOR_SIZE	0x0000001C
-#define XSHAL_USER_VECTOR_ISROM	0
-#define XSHAL_PROGRAMEXC_VECTOR_SIZE	XSHAL_USER_VECTOR_SIZE	/* for backward compatibility */
-#define XSHAL_USEREXC_VECTOR_SIZE	XSHAL_USER_VECTOR_SIZE	/* for backward compatibility */
-#define XSHAL_KERNEL_VECTOR_SIZE	0x0000001C
-#define XSHAL_KERNEL_VECTOR_ISROM	0
-#define XSHAL_STACKEDEXC_VECTOR_SIZE	XSHAL_KERNEL_VECTOR_SIZE	/* for backward compatibility */
-#define XSHAL_KERNELEXC_VECTOR_SIZE	XSHAL_KERNEL_VECTOR_SIZE	/* for backward compatibility */
-#define XSHAL_DOUBLEEXC_VECTOR_SIZE	0x0000001C
-#define XSHAL_DOUBLEEXC_VECTOR_ISROM	0
-#define XSHAL_WINDOW_VECTORS_SIZE	0x00000178
-#define XSHAL_WINDOW_VECTORS_ISROM	0
-#define XSHAL_INTLEVEL2_VECTOR_SIZE	0x0000001C
-#define XSHAL_INTLEVEL2_VECTOR_ISROM	0
-#define XSHAL_INTLEVEL3_VECTOR_SIZE	0x0000001C
-#define XSHAL_INTLEVEL3_VECTOR_ISROM	0
-#define XSHAL_INTLEVEL4_VECTOR_SIZE	0x0000001C
-#define XSHAL_INTLEVEL4_VECTOR_ISROM	0
-#define XSHAL_INTLEVEL5_VECTOR_SIZE	0x0000001C
-#define XSHAL_INTLEVEL5_VECTOR_ISROM	0
-#define XSHAL_DEBUG_VECTOR_SIZE		XSHAL_INTLEVEL5_VECTOR_SIZE
-#define XSHAL_DEBUG_VECTOR_ISROM	XSHAL_INTLEVEL5_VECTOR_ISROM
-#define XSHAL_NMI_VECTOR_SIZE	0x0000001C
-#define XSHAL_NMI_VECTOR_ISROM	0
-#define XSHAL_INTLEVEL6_VECTOR_SIZE	XSHAL_NMI_VECTOR_SIZE
-
-#endif /*XTENSA_CONFIG_SYSTEM_H*/
-
diff --git a/src/platform/mt8188/include/arch/xtensa/config/tie-asm.h b/src/platform/mt8188/include/arch/xtensa/config/tie-asm.h
deleted file mode 100644
index 1dd05a4d23b9..000000000000
--- a/src/platform/mt8188/include/arch/xtensa/config/tie-asm.h
+++ /dev/null
@@ -1,362 +0,0 @@
-/* 
- * tie-asm.h -- compile-time HAL assembler definitions dependent on CORE & TIE
- *
- *  NOTE:  This header file is not meant to be included directly.
- */
-
-/* This header file contains assembly-language definitions (assembly
-   macros, etc.) for this specific Xtensa processor's TIE extensions
-   and options.  It is customized to this Xtensa processor configuration.
-
-   Customer ID=16990; Build=0x904d8; Copyright (c) 1999-2020 Cadence Design Systems Inc.
-
-   Permission is hereby granted, free of charge, to any person obtaining
-   a copy of this software and associated documentation files (the
-   "Software"), to deal in the Software without restriction, including
-   without limitation the rights to use, copy, modify, merge, publish,
-   distribute, sublicense, and/or sell copies of the Software, and to
-   permit persons to whom the Software is furnished to do so, subject to
-   the following conditions:
-
-   The above copyright notice and this permission notice shall be included
-   in all copies or substantial portions of the Software.
-
-   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
-
-#ifndef _XTENSA_CORE_TIE_ASM_H
-#define _XTENSA_CORE_TIE_ASM_H
-
-#include <xtensa/coreasm.h>
-
-/*  Selection parameter values for save-area save/restore macros:  */
-/*  Option vs. TIE:  */
-#define XTHAL_SAS_TIE	0x0001	/* custom extension or coprocessor */
-#define XTHAL_SAS_OPT	0x0002	/* optional (and not a coprocessor) */
-#define XTHAL_SAS_ANYOT	0x0003	/* both of the above */
-/*  Whether used automatically by compiler:  */
-#define XTHAL_SAS_NOCC	0x0004	/* not used by compiler w/o special opts/code */
-#define XTHAL_SAS_CC	0x0008	/* used by compiler without special opts/code */
-#define XTHAL_SAS_ANYCC	0x000C	/* both of the above */
-/*  ABI handling across function calls:  */
-#define XTHAL_SAS_CALR	0x0010	/* caller-saved */
-#define XTHAL_SAS_CALE	0x0020	/* callee-saved */
-#define XTHAL_SAS_GLOB	0x0040	/* global across function calls (in thread) */
-#define XTHAL_SAS_ANYABI	0x0070	/* all of the above three */
-/*  Misc  */
-#define XTHAL_SAS_ALL	0xFFFF	/* include all default NCP contents */
-#define XTHAL_SAS3(optie,ccuse,abi)	( ((optie) & XTHAL_SAS_ANYOT)  \
-					| ((ccuse) & XTHAL_SAS_ANYCC)  \
-					| ((abi)   & XTHAL_SAS_ANYABI) )
-
-
-    /*
-      *  Macro to store all non-coprocessor (extra) custom TIE and optional state
-      *  (not including zero-overhead loop registers).
-      *  Required parameters:
-      *      ptr         Save area pointer address register (clobbered)
-      *                  (register must contain a 4 byte aligned address).
-      *      at1..at4    Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
-      *                  registers are clobbered, the remaining are unused).
-      *  Optional parameters:
-      *      continue    If macro invoked as part of a larger store sequence, set to 1
-      *                  if this is not the first in the sequence.  Defaults to 0.
-      *      ofs         Offset from start of larger sequence (from value of first ptr
-      *                  in sequence) at which to store.  Defaults to next available space
-      *                  (or 0 if <continue> is 0).
-      *      select      Select what category(ies) of registers to store, as a bitmask
-      *                  (see XTHAL_SAS_xxx constants).  Defaults to all registers.
-      *      alloc       Select what category(ies) of registers to allocate; if any
-      *                  category is selected here that is not in <select>, space for
-      *                  the corresponding registers is skipped without doing any store.
-      */
-    .macro xchal_ncp_store  ptr at1 at2 at3 at4  continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
-	xchal_sa_start	\continue, \ofs
-	// Optional global registers used by default by the compiler:
-	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
-	xchal_sa_align	\ptr, 0, 1016, 4, 4
-	rur.threadptr	\at1		// threadptr option
-	s32i	\at1, \ptr, .Lxchal_ofs_+0
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
-	.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
-	xchal_sa_align	\ptr, 0, 1016, 4, 4
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
-	.endif
-	// Optional caller-saved registers not used by default by the compiler:
-	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
-	xchal_sa_align	\ptr, 0, 1016, 4, 4
-	rsr.br	\at1		// boolean option
-	s32i	\at1, \ptr, .Lxchal_ofs_+0
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
-	.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
-	xchal_sa_align	\ptr, 0, 1016, 4, 4
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
-	.endif
-    .endm	// xchal_ncp_store
-
-    /*
-      *  Macro to load all non-coprocessor (extra) custom TIE and optional state
-      *  (not including zero-overhead loop registers).
-      *  Required parameters:
-      *      ptr         Save area pointer address register (clobbered)
-      *                  (register must contain a 4 byte aligned address).
-      *      at1..at4    Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
-      *                  registers are clobbered, the remaining are unused).
-      *  Optional parameters:
-      *      continue    If macro invoked as part of a larger load sequence, set to 1
-      *                  if this is not the first in the sequence.  Defaults to 0.
-      *      ofs         Offset from start of larger sequence (from value of first ptr
-      *                  in sequence) at which to load.  Defaults to next available space
-      *                  (or 0 if <continue> is 0).
-      *      select      Select what category(ies) of registers to load, as a bitmask
-      *                  (see XTHAL_SAS_xxx constants).  Defaults to all registers.
-      *      alloc       Select what category(ies) of registers to allocate; if any
-      *                  category is selected here that is not in <select>, space for
-      *                  the corresponding registers is skipped without doing any load.
-      */
-    .macro xchal_ncp_load  ptr at1 at2 at3 at4  continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
-	xchal_sa_start	\continue, \ofs
-	// Optional global registers used by default by the compiler:
-	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
-	xchal_sa_align	\ptr, 0, 1016, 4, 4
-	l32i	\at1, \ptr, .Lxchal_ofs_+0
-	wur.threadptr	\at1		// threadptr option
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
-	.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
-	xchal_sa_align	\ptr, 0, 1016, 4, 4
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
-	.endif
-	// Optional caller-saved registers not used by default by the compiler:
-	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
-	xchal_sa_align	\ptr, 0, 1016, 4, 4
-	l32i	\at1, \ptr, .Lxchal_ofs_+0
-	wsr.br	\at1		// boolean option
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
-	.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
-	xchal_sa_align	\ptr, 0, 1016, 4, 4
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
-	.endif
-    .endm	// xchal_ncp_load
-
-
-#define XCHAL_NCP_NUM_ATMPS	1
-
-    /* 
-     *  Macro to store the state of TIE coprocessor AudioEngineLX.
-     *  Required parameters:
-     *      ptr         Save area pointer address register (clobbered)
-     *                  (register must contain a 16 byte aligned address).
-     *      at1..at4    Four temporary address registers (first XCHAL_CP1_NUM_ATMPS
-     *                  registers are clobbered, the remaining are unused).
-     *  Optional parameters are the same as for xchal_ncp_store.
-     */
-#define xchal_cp_AudioEngineLX_store	xchal_cp1_store
-    .macro	xchal_cp1_store  ptr at1 at2 at3 at4  continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
-	xchal_sa_start \continue, \ofs
-	// Custom caller-saved registers not used by default by the compiler:
-	.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
-	xchal_sa_align	\ptr, 0, 0, 16, 16
-	ae_s64.i	aed0, \ptr, .Lxchal_ofs_+56
-	addi.a	\ptr, \ptr, 64
-	ae_s64.i	aed1, \ptr, .Lxchal_ofs_+0
-	ae_s64.i	aed2, \ptr, .Lxchal_ofs_+8
-	ae_s64.i	aed3, \ptr, .Lxchal_ofs_+16
-	ae_s64.i	aed4, \ptr, .Lxchal_ofs_+24
-	ae_s64.i	aed5, \ptr, .Lxchal_ofs_+32
-	ae_s64.i	aed6, \ptr, .Lxchal_ofs_+40
-	ae_s64.i	aed7, \ptr, .Lxchal_ofs_+48
-	ae_s64.i	aed8, \ptr, .Lxchal_ofs_+56
-	addi.a	\ptr, \ptr, 64
-	ae_s64.i	aed9, \ptr, .Lxchal_ofs_+0
-	ae_s64.i	aed10, \ptr, .Lxchal_ofs_+8
-	ae_s64.i	aed11, \ptr, .Lxchal_ofs_+16
-	ae_s64.i	aed12, \ptr, .Lxchal_ofs_+24
-	ae_s64.i	aed13, \ptr, .Lxchal_ofs_+32
-	ae_s64.i	aed14, \ptr, .Lxchal_ofs_+40
-	ae_s64.i	aed15, \ptr, .Lxchal_ofs_+48
-	ae_s64.i	aed16, \ptr, .Lxchal_ofs_+56
-	addi.a	\ptr, \ptr, 64
-	ae_s64.i	aed17, \ptr, .Lxchal_ofs_+0
-	ae_s64.i	aed18, \ptr, .Lxchal_ofs_+8
-	ae_s64.i	aed19, \ptr, .Lxchal_ofs_+16
-	ae_s64.i	aed20, \ptr, .Lxchal_ofs_+24
-	ae_s64.i	aed21, \ptr, .Lxchal_ofs_+32
-	ae_s64.i	aed22, \ptr, .Lxchal_ofs_+40
-	ae_s64.i	aed23, \ptr, .Lxchal_ofs_+48
-	ae_s64.i	aed24, \ptr, .Lxchal_ofs_+56
-	addi.a	\ptr, \ptr, 64
-	ae_s64.i	aed25, \ptr, .Lxchal_ofs_+0
-	ae_s64.i	aed26, \ptr, .Lxchal_ofs_+8
-	ae_s64.i	aed27, \ptr, .Lxchal_ofs_+16
-	ae_s64.i	aed28, \ptr, .Lxchal_ofs_+24
-	ae_s64.i	aed29, \ptr, .Lxchal_ofs_+32
-	ae_s64.i	aed30, \ptr, .Lxchal_ofs_+40
-	ae_s64.i	aed31, \ptr, .Lxchal_ofs_+48
-	ae_movae	\at1, aep0
-	s8i	\at1, \ptr, .Lxchal_ofs_+56
-	ae_movae	\at1, aep1
-	s8i	\at1, \ptr, .Lxchal_ofs_+57
-	ae_movae	\at1, aep2
-	s8i	\at1, \ptr, .Lxchal_ofs_+58
-	ae_movae	\at1, aep3
-	s8i	\at1, \ptr, .Lxchal_ofs_+59
-	addi.a	\ptr, \ptr, 64
-	ae_salign128.i	u0, \ptr, .Lxchal_ofs_+0
-	ae_salign128.i	u1, \ptr, .Lxchal_ofs_+16
-	ae_salign128.i	u2, \ptr, .Lxchal_ofs_+32
-	ae_salign128.i	u3, \ptr, .Lxchal_ofs_+48
-	addi.a	\ptr, \ptr, -320
-	ae_movdrzbvc	aed0		// ureg AE_ZBIASV8C
-	ae_s64.i	aed0, \ptr, .Lxchal_ofs_+0 + 0
-	ae_movvfcrfsr	aed0		// ureg FCR_FSR
-	ae_s64.i	aed0, \ptr, .Lxchal_ofs_+8 + 0
-	rur.ae_ovf_sar	\at1		// ureg 240
-	s32i	\at1, \ptr, .Lxchal_ofs_+16
-	rur.ae_bithead	\at1		// ureg 241
-	s32i	\at1, \ptr, .Lxchal_ofs_+20
-	rur.ae_ts_fts_bu_bp	\at1		// ureg 242
-	s32i	\at1, \ptr, .Lxchal_ofs_+24
-	rur.ae_cw_sd_no	\at1		// ureg 243
-	s32i	\at1, \ptr, .Lxchal_ofs_+28
-	rur.ae_cbegin0	\at1		// ureg 246
-	s32i	\at1, \ptr, .Lxchal_ofs_+32
-	rur.ae_cend0	\at1		// ureg 247
-	s32i	\at1, \ptr, .Lxchal_ofs_+36
-	rur.ae_cbegin1	\at1		// ureg 248
-	s32i	\at1, \ptr, .Lxchal_ofs_+40
-	rur.ae_cend1	\at1		// ureg 249
-	s32i	\at1, \ptr, .Lxchal_ofs_+44
-	rur.ae_cbegin2	\at1		// ureg 250
-	s32i	\at1, \ptr, .Lxchal_ofs_+48
-	rur.ae_cend2	\at1		// ureg 251
-	s32i	\at1, \ptr, .Lxchal_ofs_+52
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 384
-	.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
-	xchal_sa_align	\ptr, 0, 0, 16, 16
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 384
-	.endif
-    .endm	// xchal_cp1_store
-
-    /* 
-     *  Macro to load the state of TIE coprocessor AudioEngineLX.
-     *  Required parameters:
-     *      ptr         Save area pointer address register (clobbered)
-     *                  (register must contain a 16 byte aligned address).
-     *      at1..at4    Four temporary address registers (first XCHAL_CP1_NUM_ATMPS
-     *                  registers are clobbered, the remaining are unused).
-     *  Optional parameters are the same as for xchal_ncp_load.
-     */
-#define xchal_cp_AudioEngineLX_load	xchal_cp1_load
-    .macro	xchal_cp1_load  ptr at1 at2 at3 at4  continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
-	xchal_sa_start \continue, \ofs
-	// Custom caller-saved registers not used by default by the compiler:
-	.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
-	xchal_sa_align	\ptr, 0, 0, 16, 16
-	ae_l64.i	aed0, \ptr, .Lxchal_ofs_+0 + 0		// ureg AE_ZBIASV8C
-	ae_movzbvcdr	aed0
-	ae_l64.i	aed0, \ptr, .Lxchal_ofs_+8 + 0		// ureg FCR_FSR
-	ae_movfcrfsrv	aed0
-	l32i	\at1, \ptr, .Lxchal_ofs_+16
-	wur.ae_ovf_sar	\at1		// ureg 240
-	l32i	\at1, \ptr, .Lxchal_ofs_+20
-	wur.ae_bithead	\at1		// ureg 241
-	l32i	\at1, \ptr, .Lxchal_ofs_+24
-	wur.ae_ts_fts_bu_bp	\at1		// ureg 242
-	l32i	\at1, \ptr, .Lxchal_ofs_+28
-	wur.ae_cw_sd_no	\at1		// ureg 243
-	l32i	\at1, \ptr, .Lxchal_ofs_+32
-	wur.ae_cbegin0	\at1		// ureg 246
-	l32i	\at1, \ptr, .Lxchal_ofs_+36
-	wur.ae_cend0	\at1		// ureg 247
-	l32i	\at1, \ptr, .Lxchal_ofs_+40
-	wur.ae_cbegin1	\at1		// ureg 248
-	l32i	\at1, \ptr, .Lxchal_ofs_+44
-	wur.ae_cend1	\at1		// ureg 249
-	l32i	\at1, \ptr, .Lxchal_ofs_+48
-	wur.ae_cbegin2	\at1		// ureg 250
-	l32i	\at1, \ptr, .Lxchal_ofs_+52
-	wur.ae_cend2	\at1		// ureg 251
-	ae_l64.i	aed0, \ptr, .Lxchal_ofs_+56
-	addi.a	\ptr, \ptr, 64
-	ae_l64.i	aed1, \ptr, .Lxchal_ofs_+0
-	ae_l64.i	aed2, \ptr, .Lxchal_ofs_+8
-	ae_l64.i	aed3, \ptr, .Lxchal_ofs_+16
-	ae_l64.i	aed4, \ptr, .Lxchal_ofs_+24
-	ae_l64.i	aed5, \ptr, .Lxchal_ofs_+32
-	ae_l64.i	aed6, \ptr, .Lxchal_ofs_+40
-	ae_l64.i	aed7, \ptr, .Lxchal_ofs_+48
-	ae_l64.i	aed8, \ptr, .Lxchal_ofs_+56
-	addi.a	\ptr, \ptr, 64
-	ae_l64.i	aed9, \ptr, .Lxchal_ofs_+0
-	ae_l64.i	aed10, \ptr, .Lxchal_ofs_+8
-	ae_l64.i	aed11, \ptr, .Lxchal_ofs_+16
-	ae_l64.i	aed12, \ptr, .Lxchal_ofs_+24
-	ae_l64.i	aed13, \ptr, .Lxchal_ofs_+32
-	ae_l64.i	aed14, \ptr, .Lxchal_ofs_+40
-	ae_l64.i	aed15, \ptr, .Lxchal_ofs_+48
-	ae_l64.i	aed16, \ptr, .Lxchal_ofs_+56
-	addi.a	\ptr, \ptr, 64
-	ae_l64.i	aed17, \ptr, .Lxchal_ofs_+0
-	ae_l64.i	aed18, \ptr, .Lxchal_ofs_+8
-	ae_l64.i	aed19, \ptr, .Lxchal_ofs_+16
-	ae_l64.i	aed20, \ptr, .Lxchal_ofs_+24
-	ae_l64.i	aed21, \ptr, .Lxchal_ofs_+32
-	ae_l64.i	aed22, \ptr, .Lxchal_ofs_+40
-	ae_l64.i	aed23, \ptr, .Lxchal_ofs_+48
-	ae_l64.i	aed24, \ptr, .Lxchal_ofs_+56
-	addi.a	\ptr, \ptr, 64
-	ae_l64.i	aed25, \ptr, .Lxchal_ofs_+0
-	ae_l64.i	aed26, \ptr, .Lxchal_ofs_+8
-	ae_l64.i	aed27, \ptr, .Lxchal_ofs_+16
-	ae_l64.i	aed28, \ptr, .Lxchal_ofs_+24
-	ae_l64.i	aed29, \ptr, .Lxchal_ofs_+32
-	ae_l64.i	aed30, \ptr, .Lxchal_ofs_+40
-	ae_l64.i	aed31, \ptr, .Lxchal_ofs_+48
-	addi.a	\ptr, \ptr, 56
-	l8ui	\at1, \ptr, .Lxchal_ofs_+0
-	ae_movea	aep0, \at1
-	l8ui	\at1, \ptr, .Lxchal_ofs_+1
-	ae_movea	aep1, \at1
-	l8ui	\at1, \ptr, .Lxchal_ofs_+2
-	ae_movea	aep2, \at1
-	l8ui	\at1, \ptr, .Lxchal_ofs_+3
-	ae_movea	aep3, \at1
-	addi.a	\ptr, \ptr, 8
-	ae_lalign128.i	u0, \ptr, .Lxchal_ofs_+0
-	ae_lalign128.i	u1, \ptr, .Lxchal_ofs_+16
-	ae_lalign128.i	u2, \ptr, .Lxchal_ofs_+32
-	ae_lalign128.i	u3, \ptr, .Lxchal_ofs_+48
-	.set	.Lxchal_pofs_, .Lxchal_pofs_ + 320
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 64
-	.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
-	xchal_sa_align	\ptr, 0, 0, 16, 16
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 384
-	.endif
-    .endm	// xchal_cp1_load
-
-#define XCHAL_CP1_NUM_ATMPS	1
-#define XCHAL_SA_NUM_ATMPS	1
-
-	/*  Empty macros for unconfigured coprocessors:  */
-	.macro xchal_cp0_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp0_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp2_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp2_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp3_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp3_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp4_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp4_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp5_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp5_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp6_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp6_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp7_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp7_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-
-#endif /*_XTENSA_CORE_TIE_ASM_H*/
-
diff --git a/src/platform/mt8188/include/arch/xtensa/config/tie.h b/src/platform/mt8188/include/arch/xtensa/config/tie.h
deleted file mode 100644
index 8ff7910d17ab..000000000000
--- a/src/platform/mt8188/include/arch/xtensa/config/tie.h
+++ /dev/null
@@ -1,210 +0,0 @@
-/* 
- * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
- *
- *  NOTE:  This header file is not meant to be included directly.
- */
-
-/* This header file describes this specific Xtensa processor's TIE extensions
-   that extend basic Xtensa core functionality.  It is customized to this
-   Xtensa processor configuration.
-
-   Customer ID=16990; Build=0x904d8; Copyright (c) 1999-2020 Cadence Design Systems Inc.
-
-   Permission is hereby granted, free of charge, to any person obtaining
-   a copy of this software and associated documentation files (the
-   "Software"), to deal in the Software without restriction, including
-   without limitation the rights to use, copy, modify, merge, publish,
-   distribute, sublicense, and/or sell copies of the Software, and to
-   permit persons to whom the Software is furnished to do so, subject to
-   the following conditions:
-
-   The above copyright notice and this permission notice shall be included
-   in all copies or substantial portions of the Software.
-
-   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
-
-#ifndef XTENSA_CORE_TIE_H
-#define XTENSA_CORE_TIE_H
-
-/* parasoft-begin-suppress ALL "This file not MISRA checked." */
-
-#define XCHAL_CP_NUM			1	/* number of coprocessors */
-#define XCHAL_CP_MAX			2	/* max CP ID + 1 (0 if none) */
-#define XCHAL_CP_MASK			0x02	/* bitmask of all CPs by ID */
-#define XCHAL_CP_PORT_MASK		0x00	/* bitmask of only port CPs */
-
-/*  Basic parameters of each coprocessor:  */
-#define XCHAL_CP1_NAME			"AudioEngineLX"
-#define XCHAL_CP1_IDENT			AudioEngineLX
-#define XCHAL_CP1_SA_SIZE		384	/* size of state save area */
-#define XCHAL_CP1_SA_ALIGN		16	/* min alignment of save area */
-#define XCHAL_CP_ID_AUDIOENGINELX   	1	/* coprocessor ID (0..7) */
-
-/*  Filler info for unassigned coprocessors, to simplify arrays etc:  */
-#define XCHAL_CP0_SA_SIZE		0
-#define XCHAL_CP0_SA_ALIGN		1
-#define XCHAL_CP2_SA_SIZE		0
-#define XCHAL_CP2_SA_ALIGN		1
-#define XCHAL_CP3_SA_SIZE		0
-#define XCHAL_CP3_SA_ALIGN		1
-#define XCHAL_CP4_SA_SIZE		0
-#define XCHAL_CP4_SA_ALIGN		1
-#define XCHAL_CP5_SA_SIZE		0
-#define XCHAL_CP5_SA_ALIGN		1
-#define XCHAL_CP6_SA_SIZE		0
-#define XCHAL_CP6_SA_ALIGN		1
-#define XCHAL_CP7_SA_SIZE		0
-#define XCHAL_CP7_SA_ALIGN		1
-
-/*  Save area for non-coprocessor optional and custom (TIE) state:  */
-#define XCHAL_NCP_SA_SIZE		8
-#define XCHAL_NCP_SA_ALIGN		4
-
-/*  Total save area for optional and custom state (NCP + CPn):  */
-#define XCHAL_TOTAL_SA_SIZE		400	/* with 16-byte align padding */
-#define XCHAL_TOTAL_SA_ALIGN		16	/* actual minimum alignment */
-
-/*
- * Detailed contents of save areas.
- * NOTE:  caller must define the XCHAL_SA_REG macro (not defined here)
- * before expanding the XCHAL_xxx_SA_LIST() macros.
- *
- * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
- *		dbnum,base,regnum,bitsz,gapsz,reset,x...)
- *
- *	s = passed from XCHAL_*_LIST(s), eg. to select how to expand
- *	ccused = set if used by compiler without special options or code
- *	abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
- *	kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
- *	opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg)
- *	name = lowercase reg name (no quotes)
- *	galign = group byte alignment (power of 2) (galign >= align)
- *	align = register byte alignment (power of 2)
- *	asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz)
- *	  (not including any pad bytes required to galign this or next reg)
- *	dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>)
- *	base = reg shortname w/o index (or sr=special, ur=TIE user reg)
- *	regnum = reg index in regfile, or special/TIE-user reg number
- *	bitsz = number of significant bits (regfile width, or ur/sr mask bits)
- *	gapsz = intervening bits, if bitsz bits not stored contiguously
- *	(padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize)
- *	reset = register reset value (or 0 if undefined at reset)
- *	x = reserved for future use (0 until then)
- *
- *  To filter out certain registers, e.g. to expand only the non-global
- *  registers used by the compiler, you can do something like this:
- *
- *  #define XCHAL_SA_REG(s,ccused,p...)	SELCC##ccused(p)
- *  #define SELCC0(p...)
- *  #define SELCC1(abikind,p...)	SELAK##abikind(p)
- *  #define SELAK0(p...)		REG(p)
- *  #define SELAK1(p...)		REG(p)
- *  #define SELAK2(p...)
- *  #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \
- *		...what you want to expand...
- */
-
-#define XCHAL_NCP_SA_NUM	2
-#define XCHAL_NCP_SA_LIST(s)	\
- XCHAL_SA_REG(s,1,2,1,1,      threadptr, 4, 4, 4,0x03E7,  ur,231, 32,0,0,0) \
- XCHAL_SA_REG(s,0,0,0,1,             br, 4, 4, 4,0x0204,  sr,4  , 16,0,0,0)
-
-#define XCHAL_CP0_SA_NUM	0
-#define XCHAL_CP0_SA_LIST(s)	/* empty */
-
-#define XCHAL_CP1_SA_NUM	52
-#define XCHAL_CP1_SA_LIST(s)	\
- XCHAL_SA_REG(s,0,0,1,0,    ae_zbiasv8c,16, 8, 8,0x1029,  ur,-1 , 16,0,0,0) \
- XCHAL_SA_REG(s,0,0,1,0,        fcr_fsr, 8, 8, 8,0x102A,  ur,-1 ,  7,0,0,0) \
- XCHAL_SA_REG(s,0,0,1,0,     ae_ovf_sar, 4, 4, 4,0x03F0,  ur,240, 15,0,0,0) \
- XCHAL_SA_REG(s,0,0,1,0,     ae_bithead, 4, 4, 4,0x03F1,  ur,241, 32,0,0,0) \
- XCHAL_SA_REG(s,0,0,1,0,ae_ts_fts_bu_bp, 4, 4, 4,0x03F2,  ur,242, 16,0,0,0) \
- XCHAL_SA_REG(s,0,0,1,0,    ae_cw_sd_no, 4, 4, 4,0x03F3,  ur,243, 29,0,0,0) \
- XCHAL_SA_REG(s,0,0,1,0,     ae_cbegin0, 4, 4, 4,0x03F6,  ur,246, 32,0,0,0) \
- XCHAL_SA_REG(s,0,0,1,0,       ae_cend0, 4, 4, 4,0x03F7,  ur,247, 32,0,0,0) \
- XCHAL_SA_REG(s,0,0,1,0,     ae_cbegin1, 4, 4, 4,0x03F8,  ur,248, 32,0,0,0) \
- XCHAL_SA_REG(s,0,0,1,0,       ae_cend1, 4, 4, 4,0x03F9,  ur,249, 32,0,0,0) \
- XCHAL_SA_REG(s,0,0,1,0,     ae_cbegin2, 4, 4, 4,0x03FA,  ur,250, 32,0,0,0) \
- XCHAL_SA_REG(s,0,0,1,0,       ae_cend2, 4, 4, 4,0x03FB,  ur,251, 32,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aed0, 8, 8, 8,0x1000, aed,0  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aed1, 8, 8, 8,0x1001, aed,1  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aed2, 8, 8, 8,0x1002, aed,2  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aed3, 8, 8, 8,0x1003, aed,3  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aed4, 8, 8, 8,0x1004, aed,4  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aed5, 8, 8, 8,0x1005, aed,5  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aed6, 8, 8, 8,0x1006, aed,6  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aed7, 8, 8, 8,0x1007, aed,7  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aed8, 8, 8, 8,0x1008, aed,8  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aed9, 8, 8, 8,0x1009, aed,9  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed10, 8, 8, 8,0x100A, aed,10 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed11, 8, 8, 8,0x100B, aed,11 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed12, 8, 8, 8,0x100C, aed,12 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed13, 8, 8, 8,0x100D, aed,13 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed14, 8, 8, 8,0x100E, aed,14 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed15, 8, 8, 8,0x100F, aed,15 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed16, 8, 8, 8,0x1010, aed,16 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed17, 8, 8, 8,0x1011, aed,17 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed18, 8, 8, 8,0x1012, aed,18 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed19, 8, 8, 8,0x1013, aed,19 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed20, 8, 8, 8,0x1014, aed,20 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed21, 8, 8, 8,0x1015, aed,21 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed22, 8, 8, 8,0x1016, aed,22 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed23, 8, 8, 8,0x1017, aed,23 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed24, 8, 8, 8,0x1018, aed,24 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed25, 8, 8, 8,0x1019, aed,25 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed26, 8, 8, 8,0x101A, aed,26 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed27, 8, 8, 8,0x101B, aed,27 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed28, 8, 8, 8,0x101C, aed,28 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed29, 8, 8, 8,0x101D, aed,29 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed30, 8, 8, 8,0x101E, aed,30 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed31, 8, 8, 8,0x101F, aed,31 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aep0, 1, 1, 1,0x1024, aep,0  ,  8,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aep1, 1, 1, 1,0x1025, aep,1  ,  8,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aep2, 1, 1, 1,0x1026, aep,2  ,  8,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aep3, 1, 1, 1,0x1027, aep,3  ,  8,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,             u0,16,16,16,0x1020,   u,0  ,128,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,             u1,16,16,16,0x1021,   u,1  ,128,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,             u2,16,16,16,0x1022,   u,2  ,128,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,             u3,16,16,16,0x1023,   u,3  ,128,0,0,0)
-
-#define XCHAL_CP2_SA_NUM	0
-#define XCHAL_CP2_SA_LIST(s)	/* empty */
-
-#define XCHAL_CP3_SA_NUM	0
-#define XCHAL_CP3_SA_LIST(s)	/* empty */
-
-#define XCHAL_CP4_SA_NUM	0
-#define XCHAL_CP4_SA_LIST(s)	/* empty */
-
-#define XCHAL_CP5_SA_NUM	0
-#define XCHAL_CP5_SA_LIST(s)	/* empty */
-
-#define XCHAL_CP6_SA_NUM	0
-#define XCHAL_CP6_SA_LIST(s)	/* empty */
-
-#define XCHAL_CP7_SA_NUM	0
-#define XCHAL_CP7_SA_LIST(s)	/* empty */
-
-/* Byte length of instruction from its first nibble (op0 field), per FLIX.  */
-#define XCHAL_OP0_FORMAT_LENGTHS	3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,16
-/* Byte length of instruction from its first byte, per FLIX.  */
-#define XCHAL_BYTE0_FORMAT_LENGTHS	\
-	3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,16, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,16,\
-	3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,16, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,16,\
-	3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,16, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,16,\
-	3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,16, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,16,\
-	3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,16, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,16,\
-	3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,16, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,16,\
-	3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,16, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,16,\
-	3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,16, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,16
-
-/* parasoft-end-suppress ALL "This file not MISRA checked." */
-
-#endif /* XTENSA_CORE_TIE_H */
-
diff --git a/src/platform/mt8188/include/platform/drivers/idc.h b/src/platform/mt8188/include/platform/drivers/idc.h
deleted file mode 100644
index e77600345b55..000000000000
--- a/src/platform/mt8188/include/platform/drivers/idc.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2022 MediaTek. All rights reserved.
- *
- * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
- *         Tinghan Shen <tinghan.shen@mediatek.com>
- */
-
-#if defined(__XTOS_RTOS_IDC_H__) || defined(__ZEPHYR_RTOS_IDC_H__)
-
-#ifndef __PLATFORM_DRIVERS_IDC_H__
-#define __PLATFORM_DRIVERS_IDC_H__
-
-#include <stdint.h>
-
-struct idc_msg;
-
-static inline int idc_send_msg(struct idc_msg *msg, uint32_t mode)
-{
-	return 0;
-}
-
-static inline int idc_init(void)
-{
-	return 0;
-}
-
-#endif /* __PLATFORM_DRIVERS_IDC_H__ */
-
-#else
-
-#error "This file shouldn't be included from outside of Zephyr/XTOS's rtos/idc.h"
-
-#endif
diff --git a/src/platform/mt8188/include/platform/drivers/interrupt.h b/src/platform/mt8188/include/platform/drivers/interrupt.h
deleted file mode 100644
index d9a5b367d1fb..000000000000
--- a/src/platform/mt8188/include/platform/drivers/interrupt.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2022 MediaTek. All rights reserved.
- *
- * Author: Zhengnan Chen <zhengnan.chen@mediatek.com>
- *         Allen-KH Cheng <allen-kh.cheng@mediatek.com>
- *         Tinghan Shen <tinghan.shen@mediatek.com>
- */
-
-#ifdef __SOF_DRIVERS_INTERRUPT_H__
-
-#ifndef __PLATFORM_DRIVERS_INTERRUPT_H__
-#define __PLATFORM_DRIVERS_INTERRUPT_H__
-
-#include <stdint.h>
-#include <platform/drivers/mt_reg_base.h>
-
-#define PLATFORM_IRQ_HW_NUM		XCHAL_NUM_INTERRUPTS
-#define PLATFORM_IRQ_FIRST_CHILD	PLATFORM_IRQ_HW_NUM
-#define PLATFORM_IRQ_CHILDREN		32
-
-/* MTK_ADSP_IRQ_MASK */
-#define MTK_DSP_OUT_IRQ_MASK		0x3FF
-
-/* interrupt table */
-#define MTK_DSP_IRQ_UART		0
-#define MTK_DSP_IRQ_SPM			1
-#define MTK_DSP_IRQ_MAILBOX		2
-#define MTK_DSP_IRQ_DSP_TIMER0		3
-#define MTK_DSP_IRQ_DSP_TIMER1		4
-#define MTK_DSP_IRQ_CORE0		5
-#define MTK_DSP_IRQ_RSV0		6
-#define MTK_DSP_IRQ_CORE0_32A		7
-#define MTK_DSP_IRQ_I2C4		8
-#define MTK_DSP_IRQ_ASRC0		9
-#define MTK_DSP_IRQ_ASRC1		10
-#define MTK_DSP_IRQ_ASRC2		11
-#define MTK_DSP_IRQ_ASRC3		12
-#define MTK_DSP_IRQ_OSTIMER64		13
-#define MTK_DSP_IRQ_DMA			14
-#define MTK_DSP_IRQ_AUDIOSYS		15
-#define MTK_DSP_IRQ_WDT			16
-#define MTK_DSP_IRQ_RSV1		17
-#define MTK_DSP_IRQ_OSTIMER32		18
-#define MTK_DSP_IRQ_SCP			19
-#define MTK_DSP_IRQ_RSV2		20
-#define MTK_DSP_IRQ_LATENCT_MON		21
-#define MTK_DSP_IRQ_BUS_TRACKER		22
-#define MTK_DSP_IRQ_WAKEUP_SRC		23
-#define MTK_DSP_IRQ_INFRA_HANG		24
-/* following interrupts are HiFi internal interrupts */
-#define MTK_DSP_IRQ_NMI			25
-#define MTK_DSP_IRQ_TIMER0		26
-#define MTK_DSP_IRQ_TIMER1		27
-#define MTK_DSP_IRQ_TIMER2		28
-#define MTK_DSP_IRQ_PROFILING		29
-#define MTK_DSP_IRQ_WERR		30
-#define MTK_DSP_IRQ_SW			31
-
-#define MTK_MAX_IRQ_NUM			32
-
-/* grouped mailbox IRQ */
-#define MTK_DSP_IRQ_MBOX0		32
-#define MTK_DSP_IRQ_MBOX1		33
-#define MTK_DSP_IRQ_MBOX2		34
-#define MTK_DSP_IRQ_MBOX3		35
-#define MTK_DSP_IRQ_MBOX4		36
-
-#define	MTK_DSP_MBOX_MASK		0xF
-
-int mtk_irq_group_id(uint32_t irq);
-
-#endif /* __PLATFORM_DRIVERS_INTERRUPT_H__ */
-
-#else
-
-#error "This file shouldn't be included from outside of sof/drivers/interrupt.h"
-
-#endif /* __SOF_DRIVERS_INTERRUPT_H__ */
diff --git a/src/platform/mt8188/include/platform/drivers/mt_reg_base.h b/src/platform/mt8188/include/platform/drivers/mt_reg_base.h
deleted file mode 100644
index 5fae02c0cec9..000000000000
--- a/src/platform/mt8188/include/platform/drivers/mt_reg_base.h
+++ /dev/null
@@ -1,108 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2022 MediaTek. All rights reserved.
- *
- * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
- *         Tinghan Shen <tinghan.shen@mediatek.com>
- */
-
-#ifndef MT_REG_BASE_H
-#define MT_REG_BASE_H
-
-#define MTK_REG_TOPCKGEN_BASE		0x10000000
-#define MTK_REG_TOPCKGEN_SIZE		0x1000
-#define MTK_REG_APMIXDSYS_BASE		0x1000C000
-#define MTK_REG_APMIXDSYS_SIZE		0x1000
-
-#define MTK_DSP_REG_BASE		0x10b80000 /* DSP Register base */
-#define MTK_DSP_CFGREG_BASE		0x10b80000
-#define MTK_DSP_CFGREG_SIZE		0x1000
-#define MTK_DSP_CKCTRL_BASE		0x10b81000
-#define MTK_DSP_CKCTRL_SIZE		0x1000
-#define MTK_DSP_OS_TIMER_BASE		0x10b83000
-#define MTK_DSP_OS_TIMER_SIZE		0x1000
-#define MTK_DSP_UART0_BASE		0x10b84000
-#define MTK_DSP_UART0_SIZE		0x1000
-#define MTK_DSP_TIMER_BASE		0x10b92000
-#define MTK_DSP_TIMER_SIZE		0x1000
-#define MTK_DSP_BUS_BASE		0x10b8F000
-#define MTK_DSP_BUS_SIZE		0x1000
-
-#define MTK_ADSP_CFGREG_SW_RSTN		(MTK_DSP_REG_BASE + 0x0000)
-#define MTK_ADSP_HIFI_IO_CONFIG		(MTK_DSP_REG_BASE + 0x000c)
-#define MTK_ADSP_IRQ_STATUS		(MTK_DSP_REG_BASE + 0x0010)
-#define MTK_ADSP_SW_INT_SET		(MTK_DSP_REG_BASE + 0x0018)
-#define MTK_ADSP_SW_INT_CLR		(MTK_DSP_REG_BASE + 0x001c)
-#define MTK_ADSP_SW_INT_32A		(MTK_DSP_REG_BASE + 0x0020)
-#define MTK_ADSP_IRQ_MASK		(MTK_DSP_REG_BASE + 0x0030)
-#define MTK_ADSP_GENERAL_IRQ_SET	(MTK_DSP_REG_BASE + 0x0034)
-#define MTK_ADSP_GENERAL_IRQ_CLR	(MTK_DSP_REG_BASE + 0x0038)
-#define MTK_ADSP_DVFSRC_STATE		(MTK_DSP_REG_BASE + 0x003c)
-#define MTK_ADSP_DVFSRC_REQ		(MTK_DSP_REG_BASE + 0x0040)
-#define MTK_ADSP_DDREN_REQ_0		(MTK_DSP_REG_BASE + 0x0044)
-#define MTK_ADSP_SPM_ACK		(MTK_DSP_REG_BASE + 0x004c)
-#define MTK_ADSP_IRQ_EN			(MTK_DSP_REG_BASE + 0x0050)
-#define MTK_ADSP_IRQ_POL_FIX		(MTK_DSP_REG_BASE + 0x0054)
-#define MTK_ADSP_SPM_WAKEUPSRC_CORE0	(MTK_DSP_REG_BASE + 0x005c)
-#define MTK_ADSP_SEMAPHORE		(MTK_DSP_REG_BASE + 0x0064)
-#define MTK_ADSP_DBG_SEL		(MTK_DSP_REG_BASE + 0x0074)
-#define MTK_ADSP_DBG_INFO		(MTK_DSP_REG_BASE + 0x0078)
-#define MTK_ADSP_WDT_CON_C0		(MTK_DSP_REG_BASE + 0x007c)
-#define MTK_ADSP_WDT_INIT_VALUE_C0	(MTK_DSP_REG_BASE + 0x0080)
-#define MTK_ADSP_WDT_CNT_C0		(MTK_DSP_REG_BASE + 0x0084)
-#define MTK_ADSP_WAKEUPSRC_MASK_C0	(MTK_DSP_REG_BASE + 0x00a0)
-#define MTK_ADSP_WAKEUPSRC_IRQ_C0	(MTK_DSP_REG_BASE + 0x00a4)
-#define MTK_ADSP2SPM_MBOX		(MTK_DSP_REG_BASE + 0x00bc)
-#define MTK_SPM2ADSP_MBOX		(MTK_DSP_REG_BASE + 0x00c0)
-#define MTK_GPR_RW_REG0			(MTK_DSP_REG_BASE + 0x0440)
-#define MTK_GPR_RW_REG1			(MTK_DSP_REG_BASE + 0x0444)
-#define MTK_GPR_RW_REG2			(MTK_DSP_REG_BASE + 0x0448)
-#define MTK_GPR_RW_REG3			(MTK_DSP_REG_BASE + 0x044c)
-#define MTK_GPR_RW_REG4			(MTK_DSP_REG_BASE + 0x0450)
-#define MTK_GPR_RW_REG5			(MTK_DSP_REG_BASE + 0x0454)
-#define MTK_GPR_RW_REG6			(MTK_DSP_REG_BASE + 0x0458)
-#define MTK_GPR_RW_REG7			(MTK_DSP_REG_BASE + 0x045c)
-#define MTK_GPR_RW_REG8			(MTK_DSP_REG_BASE + 0x0460)
-#define MTK_GPR_RW_REG9			(MTK_DSP_REG_BASE + 0x0464)
-#define MTK_GPR_RW_REG10		(MTK_DSP_REG_BASE + 0x0468)
-#define MTK_GPR_RW_REG11		(MTK_DSP_REG_BASE + 0x046c)
-#define MTK_GPR_RW_REG12		(MTK_DSP_REG_BASE + 0x0470)
-#define MTK_GPR_RW_REG13		(MTK_DSP_REG_BASE + 0x0474)
-#define MTK_GPR_RW_REG14		(MTK_DSP_REG_BASE + 0x0478)
-#define MTK_GPR_RW_REG15		(MTK_DSP_REG_BASE + 0x047c)
-#define MTK_GPR_RW_REG16		(MTK_DSP_REG_BASE + 0x0480)
-#define MTK_GPR_RW_REG17		(MTK_DSP_REG_BASE + 0x0484)
-#define MTK_GPR_RW_REG18		(MTK_DSP_REG_BASE + 0x0488)
-#define MTK_GPR_RW_REG19		(MTK_DSP_REG_BASE + 0x048c)
-#define MTK_GPR_RW_REG20		(MTK_DSP_REG_BASE + 0x0490)
-#define MTK_GPR_RW_REG21		(MTK_DSP_REG_BASE + 0x0494)
-#define MTK_GPR_RW_REG22		(MTK_DSP_REG_BASE + 0x0498)
-#define MTK_GPR_RW_REG23		(MTK_DSP_REG_BASE + 0x049c)
-#define MTK_GPR_RW_REG24		(MTK_DSP_REG_BASE + 0x04a0)
-#define MTK_GPR_RW_REG25		(MTK_DSP_REG_BASE + 0x04a4)
-#define MTK_GPR_RW_REG26		(MTK_DSP_REG_BASE + 0x04a8)
-#define MTK_GPR_RW_REG27		(MTK_DSP_REG_BASE + 0x04ac)
-#define MTK_GPR_RW_REG28		(MTK_DSP_REG_BASE + 0x04b0)  /* use for tickless status */
-#define MTK_GPR_RW_REG29		(MTK_DSP_REG_BASE + 0x04b4)
-#define MTK_ADSP_IRQ_OUT_MASK		(MTK_DSP_REG_BASE + 0x0500)
-#define MTK_MBOX_IRQ_IN			(MTK_DSP_REG_BASE + 0xB070)
-
-#define MTK_ADSPPLL_CON0		(MTK_REG_APMIXDSYS_BASE + 0x42C)
-#define MTK_ADSPPLL_CON1		(MTK_REG_APMIXDSYS_BASE + 0x430)
-#define MTK_ADSPPLL_CON2		(MTK_REG_APMIXDSYS_BASE + 0x434)
-#define MTK_ADSPPLL_CON3		(MTK_REG_APMIXDSYS_BASE + 0x438)
-
-#define MTK_CLK_CFG_UPDATE2		(MTK_REG_TOPCKGEN_BASE + 0xC)
-#define MTK_CLK_CFG_17			(MTK_REG_TOPCKGEN_BASE + 0x0EC)
-#define MTK_CLK_CFG_17_SET		(MTK_REG_TOPCKGEN_BASE + 0x0F0)
-#define MTK_CLK_CFG_17_CLR		(MTK_REG_TOPCKGEN_BASE + 0x0F4)
-
-/* MBOX registers */
-#define MTK_ADSP_MBOX_REG_BASE(x)	(0x10b86000 + (0x1000 * (x)))
-#define MTK_ADSP_MBOX_REG_SIZE		(0x5000)
-#define MTK_ADSP_MBOX_IN_CMD(x)		(MTK_ADSP_MBOX_REG_BASE(x) + 0x100)
-#define MTK_ADSP_MBOX_IN_CMD_CLR(x)	(MTK_ADSP_MBOX_REG_BASE(x) + 0x108)
-#define MTK_ADSP_MBOX_OUT_CMD(x)	(MTK_ADSP_MBOX_REG_BASE(x) + 0x104)
-#define MTK_ADSP_MBOX_OUT_CMD_CLR(x)	(MTK_ADSP_MBOX_REG_BASE(x) + 0x10c)
-
-#endif /* MT_REG_BASE_H */
diff --git a/src/platform/mt8188/include/platform/drivers/timer.h b/src/platform/mt8188/include/platform/drivers/timer.h
deleted file mode 100644
index 4f0e68f1928d..000000000000
--- a/src/platform/mt8188/include/platform/drivers/timer.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2022 MediaTek. All rights reserved.
- *
- * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
- *         Tinghan Shen <tinghan.shen@mediatek.com>
- */
-
-#ifndef __PLATFORM_DRIVERS_TIMER_H__
-#define __PLATFORM_DRIVERS_TIMER_H__
-
-#include <rtos/bit.h>
-#include <platform/drivers/mt_reg_base.h>
-
-/*-------timer:ostimer0-------*/
-enum ostimer {
-	OSTIMER0 = 0,
-	OSTIMER1,
-	OSTIMER2,
-	OSTIMER3,
-	NR_TMRS
-};
-
-#define MTK_TIMER_CON(n)		(MTK_DSP_OS_TIMER_BASE + 0x0 + 0x10 * (n))
-#define MTK_TIMER_RST_VAL(n)		(MTK_DSP_OS_TIMER_BASE + 0x4 + 0x10 * (n))
-#define MTK_TIMER_CUR_VAL(n)		(MTK_DSP_OS_TIMER_BASE + 0x8 + 0x10 * (n))
-#define MTK_TIMER_IRQ_ACK(n)		(MTK_DSP_OS_TIMER_BASE + 0xC + 0x10 * (n))
-
-#define MTK_TIMER_ENABLE_BIT		BIT(0)
-#define MTK_TIMER_IRQ_ENABLE		BIT(0)
-#define MTK_TIMER_IRQ_STA		BIT(4)
-#define MTK_TIMER_IRQ_CLEAR		BIT(5)
-#define MTK_TIMER_CLKSRC_BIT		(BIT(4) | BIT(5))
-
-#define MTK_TIMER_CLK_SRC_OFFSET	4
-#define MTK_TIMER_CLK_SRC_CLK_26M	0
-#define MTK_TIMER_CLK_SRC_BCLK		BIT(4)
-#define MTK_TIMER_CLK_SRC_PCLK		BIT(5)
-
-/*-------platform_timer: 64 bit systimer-------*/
-#define MTK_OSTIMER_CON			(MTK_DSP_OS_TIMER_BASE + 0x80)
-#define MTK_OSTIMER_CUR_L		(MTK_DSP_OS_TIMER_BASE + 0x8C)
-#define MTK_OSTIMER_CUR_H		(MTK_DSP_OS_TIMER_BASE + 0x90)
-#define MTK_OSTIMER_TVAL		(MTK_DSP_OS_TIMER_BASE + 0x94)
-#define MTK_OSTIMER_IRQ_ACK		(MTK_DSP_OS_TIMER_BASE + 0x98)
-
-#define MTK_OSTIMER_EN_BIT			BIT(0)
-
-#endif /* __PLATFORM_DRIVERS_TIMER_H__ */
diff --git a/src/platform/mt8188/include/platform/lib/clk.h b/src/platform/mt8188/include/platform/lib/clk.h
deleted file mode 100644
index d9f76609384a..000000000000
--- a/src/platform/mt8188/include/platform/lib/clk.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2022 MediaTek. All rights reserved.
- *
- * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
- *         Tinghan Shen <tinghan.shen@mediatek.com>
- */
-
-#ifdef __SOF_LIB_CLK_H__
-
-#ifndef __PLATFORM_LIB_CLK_H__
-#define __PLATFORM_LIB_CLK_H__
-
-#include <stdint.h>
-
-struct sof;
-
-#define CPU_DEFAULT_IDX				0
-
-#define CLK_CPU(x)				(x)
-#define CLK_DEFAULT_CPU_HZ			26000000
-#define CLK_MAX_CPU_HZ				800000000
-#define NUM_CLOCKS				1
-#define NUM_CPU_FREQ				3
-
-/* MTK_ADSPPLL_CON1 */
-#define MTK_PLL_DIV_RATIO_800M			0x810F6276
-#define MTK_PLL_DIV_RATIO_400M			0x831EC4ED
-
-/* MTK_ADSPPLL_CON3 */
-#define MTK_PLL_EN				BIT(9)
-#define MTK_PLL_PWR_ON				BIT(0)
-#define MTK_PLL_ISO_EN				BIT(1)
-
-/* MTK_CLK_CFG_UPDATE2 */
-#define MTK_CLK_UPDATE_ADSK_CLK			BIT(4)
-#define MTK_CLK_UPDATE_AUDIO_LOCAL_BUS_CLK	BIT(5)
-
-/* MTK_CLK_CFG_17[3:0] */
-#define MTK_CLK_ADSP_OFFSET			0
-#define MTK_CLK_ADSP_MASK			0xF
-#define MTK_CLK_ADSP_26M			0
-#define MTK_CLK_ADSP_ADSPPLL			8 /* 800M */
-#define MTK_CLK_ADSP_ADSPPLL_D_2		9 /* 400M */
-
-/* MTK_CLK_CFG_17[11:8] */
-#define MTK_CLK_AUDIO_LOCAL_BUS_OFFSET		8
-#define MTK_CLK_AUDIO_LOCAL_BUS_MASK		0xF
-#define MTK_CLK_AUDIO_LOCAL_BUS_26M		0
-#define MTK_CLK_AUDIO_LOCAL_BUS_MAINPLL_D_7	6 /* 312M */
-#define MTK_CLK_AUDIO_LOCAL_BUS_MAINPLL_D_4	7 /* 546M */
-
-/* List resource from low to high request */
-/* 0 is the lowest request */
-enum ADSP_HW_DSP_CLK {
-	ADSP_CLK_26M = 0,
-	ADSP_CLK_PLL_400M,
-	ADSP_CLK_PLL_800M,
-};
-
-void platform_clock_init(struct sof *sof);
-
-#endif /* __PLATFORM_LIB_CLK_H__ */
-
-#else
-
-#error "This file shouldn't be included from outside of sof/lib/clk.h"
-
-#endif /* __SOF_LIB_CLK_H__ */
diff --git a/src/platform/mt8188/include/platform/lib/cpu.h b/src/platform/mt8188/include/platform/lib/cpu.h
deleted file mode 100644
index ecbb220d5f02..000000000000
--- a/src/platform/mt8188/include/platform/lib/cpu.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2022 MediaTek. All rights reserved.
- *
- * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
- *         Tinghan Shen <tinghan.shen@mediatek.com>
- */
-
-#ifdef __SOF_LIB_CPU_H__
-
-#ifndef __PLATFORM_LIB_CPU_H__
-#define __PLATFORM_LIB_CPU_H__
-
-/** \brief Id of primary DSP core */
-#define PLATFORM_PRIMARY_CORE_ID	0
-
-#endif /* __PLATFORM_LIB_CPU_H__ */
-
-#else
-
-#error "This file shouldn't be included from outside of sof/lib/cpu.h"
-
-#endif /* __SOF_LIB_CPU_H__ */
diff --git a/src/platform/mt8188/include/platform/lib/dai.h b/src/platform/mt8188/include/platform/lib/dai.h
deleted file mode 100644
index 8d367ed32cdd..000000000000
--- a/src/platform/mt8188/include/platform/lib/dai.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2022 MediaTek. All rights reserved.
- *
- * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
- *         Tinghan Shen <tinghan.shen@mediatek.com>
- */
-
-#ifdef __SOF_LIB_DAI_H__
-
-#ifndef __PLATFORM_LIB_DAI_H__
-#define __PLATFORM_LIB_DAI_H__
-
-#endif /* __PLATFORM_LIB_DAI_H__ */
-
-#else
-
-#error "This file shouldn't be included from outside of sof/lib/dai.h"
-
-#endif /* __SOF_LIB_DAI_H__ */
diff --git a/src/platform/mt8188/include/platform/lib/dma.h b/src/platform/mt8188/include/platform/lib/dma.h
deleted file mode 100644
index a7080012ffd9..000000000000
--- a/src/platform/mt8188/include/platform/lib/dma.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2022 MediaTek. All rights reserved.
- *
- * Author: Bo Pan <bo.pan@mediatek.com>
- *         Allen-KH Cheng <allen-kh.cheng@mediatek.com>
- *         Tinghan Shen <tinghan.shen@mediatek.com>
- */
-
-#ifdef __SOF_LIB_DMA_H__
-
-#ifndef __PLATFORM_LIB_DMA_H__
-#define __PLATFORM_LIB_DMA_H__
-
-#define PLATFORM_NUM_DMACS		2
-
-/* max number of supported DMA channels */
-#define PLATFORM_MAX_DMA_CHAN		32
-
-#define DMA_ID_AFE_MEMIF		0
-#define DMA_ID_HOST			1
-
-#define dma_chan_irq(dma, chan)		dma_irq(dma)
-#define dma_chan_irq_name(dma, chan)	dma_irq_name(dma)
-
-#endif /* __PLATFORM_LIB_DMA_H__ */
-
-#else
-
-#error "This file shouldn't be included from outside of sof/lib/dma.h"
-
-#endif /* __SOF_LIB_DMA_H__ */
diff --git a/src/platform/mt8188/include/platform/lib/mailbox.h b/src/platform/mt8188/include/platform/lib/mailbox.h
deleted file mode 100644
index 2473f542ceee..000000000000
--- a/src/platform/mt8188/include/platform/lib/mailbox.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2022 MediaTek. All rights reserved.
- *
- * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
- *         Tinghan Shen <tinghan.shen@mediatek.com>
- */
-
-#ifdef __SOF_LIB_MAILBOX_H__
-
-#ifndef __PLATFORM_LIB_MAILBOX_H__
-#define __PLATFORM_LIB_MAILBOX_H__
-
-#include <sof/lib/memory.h>
-#include <stddef.h>
-#include <stdint.h>
-
-/*
- * The Window Region on MT8186 SRAM is organised like this :-
- * +--------------------------------------------------------------------------+
- * | Offset              | Region         |  Size                             |
- * +---------------------+----------------+-----------------------------------+
- * | SRAM_OUTBOX_BASE    | Outbox         |  SRAM_MAILBOX_SIZE                |
- * +---------------------+----------------+-----------------------------------+
- * | SRAM_INBOX_BASE     | Inbox          |  SRAM_INBOX_SIZE                  |
- * +---------------------+----------------+-----------------------------------+
- * | SRAM_DEBUG_BASE     | Debug data     |  SRAM_DEBUG_SIZE                  |
- * +---------------------+----------------+-----------------------------------+
- * | SRAM_EXCEPT_BASE    | Except         |  SRAM_EXCEPT_SIZE                 |
- * +---------------------+----------------+-----------------------------------+
- * | SRAM_STREAM_BASE    | Stream         |  SRAM_STREAM_SIZE                 |
- * +---------------------+----------------+-----------------------------------+
- * | SRAM_TRACE_BASE     | Trace Buffer   |  SRAM_TRACE_SIZE                  |
- * +---------------------+----------------+-----------------------------------+
- */
-
-#define MAILBOX_DSPBOX_SIZE		SRAM_OUTBOX_SIZE
-#define MAILBOX_DSPBOX_BASE		SRAM_OUTBOX_BASE
-#define MAILBOX_DSPBOX_OFFSET		SRAM_OUTBOX_OFFSET
-
-#define MAILBOX_HOSTBOX_SIZE		SRAM_INBOX_SIZE
-#define MAILBOX_HOSTBOX_BASE		SRAM_INBOX_BASE
-#define MAILBOX_HOSTBOX_OFFSET		SRAM_INBOX_OFFSET
-
-#define MAILBOX_DEBUG_SIZE		SRAM_DEBUG_SIZE
-#define MAILBOX_DEBUG_BASE		SRAM_DEBUG_BASE
-#define MAILBOX_DEBUG_OFFSET		SRAM_DEBUG_OFFSET
-
-#define MAILBOX_EXCEPTION_SIZE		SRAM_EXCEPT_SIZE
-#define MAILBOX_EXCEPTION_BASE		SRAM_EXCEPT_BASE
-#define MAILBOX_EXCEPTION_OFFSET	SRAM_EXCEPT_OFFSET
-
-#define MAILBOX_STREAM_SIZE		SRAM_STREAM_SIZE
-#define MAILBOX_STREAM_BASE		SRAM_STREAM_BASE
-#define MAILBOX_STREAM_OFFSET		SRAM_STREAM_OFFSET
-
-#define MAILBOX_TRACE_SIZE		SRAM_TRACE_SIZE
-#define MAILBOX_TRACE_BASE		SRAM_TRACE_BASE
-#define MAILBOX_TRACE_OFFSET		SRAM_TRACE_OFFSET
-
-#define ADSP_IPI_OP_REQ	0x1
-#define ADSP_IPI_OP_RSP	0x2
-void trigger_irq_to_host_req(void);
-void trigger_irq_to_host_rsp(void);
-
-static inline void mailbox_sw_reg_write(size_t offset, uint32_t src)
-{
-	volatile uint32_t *ptr;
-
-	ptr = (volatile uint32_t *)(MAILBOX_DEBUG_BASE + offset);
-	*ptr = src;
-}
-
-#endif /* __PLATFORM_LIB_MAILBOX_H__ */
-
-#else
-
-#error "This file shouldn't be included from outside of sof/lib/mailbox.h"
-
-#endif /* __SOF_LIB_MAILBOX_H__ */
diff --git a/src/platform/mt8188/include/platform/lib/memory.h b/src/platform/mt8188/include/platform/lib/memory.h
deleted file mode 100644
index 17343e78ef76..000000000000
--- a/src/platform/mt8188/include/platform/lib/memory.h
+++ /dev/null
@@ -1,217 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2022 MediaTek. All rights reserved.
- *
- * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
- *         Tinghan Shen <tinghan.shen@mediatek.com>
- */
-
-#ifdef __SOF_LIB_MEMORY_H__
-
-#ifndef __PLATFORM_LIB_MEMORY_H__
-#define __PLATFORM_LIB_MEMORY_H__
-
-#include <rtos/cache.h>
-
-/* data cache line alignment */
-#define PLATFORM_DCACHE_ALIGN sizeof(void *)
-
-/* physical DSP addresses */
-#define SRAM_BASE			0x4e100000
-#define SRAM_SIZE			0x80000
-
-/* reset vector + rodata + module_init + text + data + bss */
-#define SOF_DATA_SIZE			0x80000
-#define VECTOR_SIZE			0x700
-#define SRAM_START			(SRAM_BASE + VECTOR_SIZE)
-
-#define DRAM_BASE			0x60000000
-#define DRAM0_SIZE			0x500000
-#define MAILBOX_BASE			(DRAM_BASE + DRAM0_SIZE)
-#define DSP_SYS_SIZE			0xA00000
-
-#define UUID_ENTRY_ELF_BASE		(SRAM_BASE + SOF_DATA_SIZE)
-#define UUID_ENTRY_ELF_SIZE		0x6000
-
-#define LOG_ENTRY_ELF_BASE		(UUID_ENTRY_ELF_BASE + UUID_ENTRY_ELF_SIZE)
-#define LOG_ENTRY_ELF_SIZE		0x20000
-#define EXT_MANIFEST_ELF_BASE		(LOG_ENTRY_ELF_BASE + LOG_ENTRY_ELF_SIZE)
-#define EXT_MANIFEST_ELF_SIZE		(SRAM_BASE + SRAM_SIZE - EXT_MANIFEST_ELF_BASE)
-
-/*
- * The Memory Layout on MT8188 are organised like this :-
- *
- * +--------------------------------------------------------------------------+
- * | Offset              | Region         |  Size                             |
- * +---------------------+----------------+-----------------------------------+
- * | SRAM_START          | RO Data        |  SOF_DATA_SIZE                    |
- * |                     | text           |                                   |
- * |                     | Data           |                                   |
- * |                     | BSS            |                                   |
- * +---------------------+----------------+-----------------------------------+
- * | fw_ready                                                                 |
- * +---------------------+----------------+-----------------------------------+
- * | static_uuid                                                              |
- * +---------------------+----------------+-----------------------------------+
- * | static_log                                                               |
- * +---------------------+----------------+-----------------------------------+
- * | fw_metadata                                                              |
- * +---------------------+----------------+-----------------------------------+
- *
- * +---------------------+----------------+-----------------------------------+
- * | SOF_DRAM_BASE       |                |  SOF_DRAM_SIZE                    |
- * +---------------------+----------------+-----------------------------------+
- * | HEAP_SYSTEM_BASE    | System Heap    |  HEAP_SYSTEM_SIZE                 |
- * +---------------------+----------------+-----------------------------------+
- * | HEAP_RUNTIME_BASE   | Runtime Heap   |  HEAP_RUNTIME_SIZE                |
- * +---------------------+----------------+-----------------------------------+
- * | HEAP_BUFFER_BASE    | Module Buffers |  HEAP_BUFFER_SIZE                 |
- * +---------------------+----------------+-----------------------------------+
- * | SOF_STACK_END       | Stack          |  SOF_STACK_SIZE                   |
- * +---------------------+----------------+-----------------------------------+
- * | SOF_STACK_BASE      |                |                                   |
- * +---------------------+----------------+-----------------------------------+
- * | MAILBOX_BASE        |                |  SOF_MAILBOX_SIZE                 |
- * +---------------------+----------------+-----------------------------------+
- */
-
-#define SRAM_OUTBOX_BASE	MAILBOX_BASE
-#define SRAM_OUTBOX_SIZE	0x1000
-#define SRAM_OUTBOX_OFFSET	0
-
-#define SRAM_INBOX_BASE		(SRAM_OUTBOX_BASE + SRAM_OUTBOX_SIZE)
-#define SRAM_INBOX_SIZE		0x1000
-#define SRAM_INBOX_OFFSET	SRAM_OUTBOX_SIZE
-
-#define SRAM_DEBUG_BASE		(SRAM_INBOX_BASE + SRAM_INBOX_SIZE)
-#define SRAM_DEBUG_SIZE		0x800
-#define SRAM_DEBUG_OFFSET	(SRAM_INBOX_OFFSET + SRAM_INBOX_SIZE)
-
-#define SRAM_EXCEPT_BASE	(SRAM_DEBUG_BASE + SRAM_DEBUG_SIZE)
-#define SRAM_EXCEPT_SIZE	0x800
-#define SRAM_EXCEPT_OFFSET	(SRAM_DEBUG_OFFSET + SRAM_DEBUG_SIZE)
-
-#define SRAM_STREAM_BASE	(SRAM_EXCEPT_BASE + SRAM_EXCEPT_SIZE)
-#define SRAM_STREAM_SIZE	0x1000
-#define SRAM_STREAM_OFFSET	(SRAM_EXCEPT_OFFSET + SRAM_EXCEPT_SIZE)
-
-#define SRAM_TRACE_BASE		(SRAM_STREAM_BASE + SRAM_STREAM_SIZE)
-#define SRAM_TRACE_SIZE		0x1000
-#define SRAM_TRACE_OFFSET	(SRAM_STREAM_OFFSET + SRAM_STREAM_SIZE)
-
-/*4K + 4K +2K + 2K + 4K + 4K = 20KB*/
-#define SOF_MAILBOX_SIZE                                        \
-	(SRAM_INBOX_SIZE + SRAM_OUTBOX_SIZE + SRAM_DEBUG_SIZE + \
-	 SRAM_EXCEPT_SIZE + SRAM_STREAM_SIZE + SRAM_TRACE_SIZE)
-
-/* SOF image on DRAM */
-#define SOF_DRAM_BASE	DRAM_BASE
-#define SOF_DRAM_SIZE	0x100000
-
-/* Heap section sizes for module pool */
-#define HEAP_RT_COUNT8		0
-#define HEAP_RT_COUNT16		48
-#define HEAP_RT_COUNT32		48
-#define HEAP_RT_COUNT64		32
-#define HEAP_RT_COUNT128	32
-#define HEAP_RT_COUNT256	32
-#define HEAP_RT_COUNT512	32
-#define HEAP_RT_COUNT1024	4
-#define HEAP_RT_COUNT2048	2
-#define HEAP_RT_COUNT4096	2
-
-/* Heap section sizes for system runtime heap */
-#define HEAP_SYS_RT_COUNT64	128
-#define HEAP_SYS_RT_COUNT512	16
-#define HEAP_SYS_RT_COUNT1024	8
-
-/* Heap configuration */
-
-#define HEAP_SYSTEM_BASE	(SOF_DRAM_BASE + SOF_DRAM_SIZE)
-#define HEAP_SYSTEM_SIZE	0x6000
-
-#define HEAP_SYS_RUNTIME_BASE	(HEAP_SYSTEM_BASE + HEAP_SYSTEM_SIZE)
-/*24KB*/
-#define HEAP_SYS_RUNTIME_SIZE                                    \
-	(HEAP_SYS_RT_COUNT64 * 64 + HEAP_SYS_RT_COUNT512 * 512 + \
-	 HEAP_SYS_RT_COUNT1024 * 1024)
-
-#define HEAP_RUNTIME_BASE (HEAP_SYS_RUNTIME_BASE + HEAP_SYS_RUNTIME_SIZE)
-/*48*(16 +32) + 32*(64 128+256) + 4*(512+1024) + 1*2048 = 24832 = 24.25KB*/
-#define HEAP_RUNTIME_SIZE                                        \
-	(HEAP_RT_COUNT8 * 8 + HEAP_RT_COUNT16 * 16 +             \
-	 HEAP_RT_COUNT32 * 32 + HEAP_RT_COUNT64 * 64 +           \
-	 HEAP_RT_COUNT128 * 128 + HEAP_RT_COUNT256 * 256 +       \
-	 HEAP_RT_COUNT512 * 512 + HEAP_RT_COUNT1024 * 1024 +     \
-	 HEAP_RT_COUNT2048 * 2048 + HEAP_RT_COUNT4096 * 4096)
-
-#define HEAP_BUFFER_BASE (HEAP_RUNTIME_BASE + HEAP_RUNTIME_SIZE)
-#define HEAP_BUFFER_SIZE                                           \
-	(DRAM0_SIZE - SOF_DRAM_SIZE - HEAP_RUNTIME_SIZE - SOF_STACK_TOTAL_SIZE -   \
-	 HEAP_SYS_RUNTIME_SIZE - HEAP_SYSTEM_SIZE)
-
-#define HEAP_BUFFER_BLOCK_SIZE		0x100
-#define HEAP_BUFFER_COUNT		(HEAP_BUFFER_SIZE / HEAP_BUFFER_BLOCK_SIZE)
-
-#define PLATFORM_HEAP_SYSTEM		1 /* one per core */
-#define PLATFORM_HEAP_SYSTEM_RUNTIME	1 /* one per core */
-#define PLATFORM_HEAP_RUNTIME		1
-#define PLATFORM_HEAP_BUFFER		1
-
-/* Stack configuration */
-#define SOF_STACK_SIZE			(CONFIG_SOF_STACK_SIZE)
-#define SOF_STACK_TOTAL_SIZE		SOF_STACK_SIZE /*4KB*/
-#define SOF_STACK_BASE			(DRAM_BASE + DRAM0_SIZE)
-#define SOF_STACK_END			(SOF_STACK_BASE - SOF_STACK_TOTAL_SIZE)
-
-/* Vector and literal sizes - not in core-isa.h */
-#define SOF_MEM_VECT_LIT_SIZE		0x4
-#define SOF_MEM_VECT_TEXT_SIZE		0x1c
-#define SOF_MEM_VECT_SIZE		(SOF_MEM_VECT_TEXT_SIZE + SOF_MEM_VECT_LIT_SIZE)
-
-#define SOF_MEM_RESET_TEXT_SIZE		0x2e0
-#define SOF_MEM_RESET_LIT_SIZE		0x120
-#define SOF_MEM_VECBASE_LIT_SIZE	0x178
-
-#define SOF_MEM_RO_SIZE			0x8
-
-#define HEAP_BUF_ALIGNMENT		DCACHE_LINE_SIZE
-
-/** \brief EDF task's default stack size in bytes. */
-#define PLATFORM_TASK_DEFAULT_STACK_SIZE	3072
-
-#if !defined(__ASSEMBLER__) && !defined(LINKER)
-
-struct sof;
-
-void platform_init_memmap(struct sof *sof);
-
-#define uncache_to_cache(address)	address
-#define cache_to_uncache(address)	address
-#define cache_to_uncache_init(address)	address
-#define is_uncached(address)		0
-
-/**
- * \brief Function for keeping shared data synchronized.
- * It's used after usage of data shared by different cores.
- * Such data is dynamically allocated with SOF_MEM_FLAG_SHARED
- * flag. Does nothing, since mt8188 doesn't support SMP.
- */
-
-static inline void *platform_rfree_prepare(void *ptr)
-{
-	return ptr;
-}
-
-#endif
-
-#define host_to_local(addr)	(addr)
-#define local_to_host(addr)	(addr)
-
-#endif /* __PLATFORM_LIB_MEMORY_H__ */
-
-#else
-
-#error "This file shouldn't be included from outside of sof/lib/memory.h"
-
-#endif /* __SOF_LIB_MEMORY_H__ */
diff --git a/src/platform/mt8188/include/platform/lib/pm_runtime.h b/src/platform/mt8188/include/platform/lib/pm_runtime.h
deleted file mode 100644
index 9831aadb4447..000000000000
--- a/src/platform/mt8188/include/platform/lib/pm_runtime.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2022 MediaTek. All rights reserved.
- *
- * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
- *         Tinghan Shen <tinghan.shen@mediatek.com>
- */
-
-#ifdef __SOF_LIB_PM_RUNTIME_H__
-
-#ifndef __PLATFORM_LIB_PM_RUNTIME_H__
-#define __PLATFORM_LIB_PM_RUNTIME_H__
-
-#include <stdint.h>
-
-struct pm_runtime_data;
-
-/**
- * \brief Initializes platform specific runtime power management.
- * \param[in,out] prd Runtime power management data.
- */
-static inline void platform_pm_runtime_init(struct pm_runtime_data *prd)
-{
-}
-
-/**
- * \brief Retrieves platform specific power management resource.
- *
- * \param[in] context Type of power management context.
- * \param[in] index The index of the device.
- * \param[in] flags The flags, set of RPM_...
- */
-static inline void platform_pm_runtime_get(uint32_t context, uint32_t index, uint32_t flags)
-{
-}
-
-/**
- * \brief Releases platform specific power management resource.
- *
- * \param[in] context Type of power management context.
- * \param[in] index The index of the device.
- * \param[in] flags The flags, set of RPM_...
- */
-static inline void platform_pm_runtime_put(uint32_t context, uint32_t index, uint32_t flags)
-{
-}
-
-static inline void platform_pm_runtime_enable(uint32_t context, uint32_t index)
-{
-}
-
-static inline void platform_pm_runtime_disable(uint32_t context, uint32_t index)
-{
-}
-
-static inline bool platform_pm_runtime_is_active(uint32_t context, uint32_t index)
-{
-	return false;
-}
-
-#endif /* __PLATFORM_LIB_PM_RUNTIME_H__ */
-
-#else
-
-#error "This file shouldn't be included from outside of sof/lib/pm_runtime.h"
-
-#endif /* __SOF_LIB_PM_RUNTIME_H__ */
diff --git a/src/platform/mt8188/include/platform/mt8188-afe-common.h b/src/platform/mt8188/include/platform/mt8188-afe-common.h
deleted file mode 100644
index 2336c1491363..000000000000
--- a/src/platform/mt8188/include/platform/mt8188-afe-common.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2023 MediaTek. All rights reserved.
- *
- * Author: Trevor Wu <trevor.wu@mediatek.com>
- */
-
-#ifndef _MT_8188_AFE_COMMON_H_
-#define _MT_8188_AFE_COMMON_H_
-
-enum {
-	MT8188_MEMIF_START,
-	MT8188_MEMIF_DL_START = MT8188_MEMIF_START,
-	MT8188_MEMIF_DL2 = MT8188_MEMIF_DL_START,
-	MT8188_MEMIF_DL3,
-	MT8188_MEMIF_DL_END,
-	MT8188_MEMIF_UL_START = MT8188_MEMIF_DL_END,
-	MT8188_MEMIF_UL4 = MT8188_MEMIF_UL_START,
-	MT8188_MEMIF_UL5,
-	MT8188_MEMIF_UL_END,
-	MT8188_MEMIF_END = MT8188_MEMIF_UL_END,
-	MT8188_MEMIF_DL_NUM = (MT8188_MEMIF_DL_END - MT8188_MEMIF_DL_START),
-	MT8188_MEMIF_UL_NUM = (MT8188_MEMIF_UL_END - MT8188_MEMIF_UL_START),
-	MT8188_MEMIF_NUM = (MT8188_MEMIF_END - MT8188_MEMIF_START),
-};
-
-enum {
-	MT8188_IRQ_1,
-	MT8188_IRQ_2,
-	MT8188_IRQ_3,
-	MT8188_IRQ_8,
-	MT8188_IRQ_9,
-	MT8188_IRQ_10,
-	MT8188_IRQ_13,
-	MT8188_IRQ_14,
-	MT8188_IRQ_15,
-	MT8188_IRQ_16,
-	MT8188_IRQ_17,
-	MT8188_IRQ_18,
-	MT8188_IRQ_19,
-	MT8188_IRQ_20,
-	MT8188_IRQ_21,
-	MT8188_IRQ_22,
-	MT8188_IRQ_23,
-	MT8188_IRQ_24,
-	MT8188_IRQ_25,
-	MT8188_IRQ_26,
-	MT8188_IRQ_27,
-	MT8188_IRQ_28,
-	MT8188_IRQ_NUM,
-};
-
-enum {
-	MT8188_AFE_IO_ETDM2_OUT, /* speaker */
-	MT8188_AFE_IO_ETDM1_OUT, /* headset out */
-	MT8188_AFE_IO_ADDA, /* DMIC */
-	MT8188_AFE_IO_ETDM2_IN, /* headset mic */
-	MT8188_DAI_NUM,
-};
-
-#endif
diff --git a/src/platform/mt8188/include/platform/mt8188-afe-reg.h b/src/platform/mt8188/include/platform/mt8188-afe-reg.h
deleted file mode 100644
index 277f43f7e8a7..000000000000
--- a/src/platform/mt8188/include/platform/mt8188-afe-reg.h
+++ /dev/null
@@ -1,2725 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2023 MediaTek. All rights reserved.
- *
- * Author: Trevor Wu <trevor.wu@mediatek.com>
- */
-
-#ifndef _MT8188_AFE_REG_H_
-#define _MT8188_AFE_REG_H_
-
-#define AFE_BASE_ADDR 0x10B10000
-
-#define AUDIO_TOP_CON0                    0x0000
-#define AUDIO_TOP_CON1                    0x0004
-#define AUDIO_TOP_CON2                    0x0008
-#define AUDIO_TOP_CON3                    0x000c
-#define AUDIO_TOP_CON4                    0x0010
-#define AUDIO_TOP_CON5                    0x0014
-#define AUDIO_TOP_CON6                    0x0018
-#define AFE_MAS_HADDR_MSB                 0x0020
-#define AFE_MEMIF_ONE_HEART               0x0024
-#define AFE_MUX_SEL_CFG                   0x0044
-#define PWR1_ASM_CON1                     0x0108
-#define ASYS_IRQ_CONFIG                   0x0110
-#define ASYS_IRQ1_CON                     0x0114
-#define ASYS_IRQ2_CON                     0x0118
-#define ASYS_IRQ3_CON                     0x011c
-#define ASYS_IRQ4_CON                     0x0120
-#define ASYS_IRQ5_CON                     0x0124
-#define ASYS_IRQ6_CON                     0x0128
-#define ASYS_IRQ7_CON                     0x012c
-#define ASYS_IRQ8_CON                     0x0130
-#define ASYS_IRQ9_CON                     0x0134
-#define ASYS_IRQ10_CON                    0x0138
-#define ASYS_IRQ11_CON                    0x013c
-#define ASYS_IRQ12_CON                    0x0140
-#define ASYS_IRQ13_CON                    0x0144
-#define ASYS_IRQ14_CON                    0x0148
-#define ASYS_IRQ15_CON                    0x014c
-#define ASYS_IRQ16_CON                    0x0150
-#define ASYS_IRQ_CLR                      0x0154
-#define ASYS_IRQ_STATUS                   0x0158
-#define ASYS_IRQ_MON1                     0x015c
-#define ASYS_IRQ_MON2                     0x0160
-#define AFE_IRQ1_CON                      0x0164
-#define AFE_IRQ2_CON                      0x0168
-#define AFE_IRQ3_CON                      0x016c
-#define AFE_IRQ_MCU_CLR                   0x0170
-#define AFE_IRQ_STATUS                    0x0174
-#define AFE_IRQ_MASK                      0x0178
-#define ASYS_IRQ_MASK                     0x017c
-#define AFE_IRQ3_CON_MON                  0x01b0
-#define AFE_IRQ_MCU_MON2                  0x01b4
-#define AFE_IRQ8_CON                      0x01b8
-#define AFE_IRQ9_CON                      0x01bc
-#define AFE_IRQ10_CON                     0x01c0
-#define AFE_IRQ9_CON_MON                  0x01c4
-#define ADSP_IRQ_MASK                     0x01c8
-#define ADSP_IRQ_STATUS                   0x01cc
-#define AFE_SINEGEN_CON0                  0x01f0
-#define AFE_SINEGEN_CON1                  0x01f4
-#define AFE_SINEGEN_CON2                  0x01f8
-#define AFE_SINEGEN_CON3                  0x01fc
-#define AFE_SPDIF_OUT_CON0                0x0380
-#define AFE_TDMOUT_CONN0                  0x0390
-#define PWR1_ASM_CON2                     0x03b0
-#define PWR1_ASM_CON3                     0x03b4
-#define AFE_APLL_TUNER_CFG                0x03f8
-#define AFE_APLL_TUNER_CFG1               0x03fc
-#define AUDIO_TOP_STA0                    0x0400
-#define AUDIO_TOP_STA1                    0x0404
-#define AFE_GAIN1_CON0                    0x0410
-#define AFE_GAIN1_CON1                    0x0414
-#define AFE_GAIN1_CON2                    0x0418
-#define AFE_GAIN1_CON3                    0x041c
-#define AFE_GAIN1_CUR                     0x0424
-#define AFE_GAIN2_CON0                    0x0428
-#define AFE_GAIN2_CON1                    0x042c
-#define AFE_GAIN2_CON2                    0x0430
-#define AFE_GAIN2_CON3                    0x0434
-#define AFE_GAIN2_CUR                     0x043c
-#define AFE_IEC_CFG                       0x0480
-#define AFE_IEC_NSNUM                     0x0484
-#define AFE_IEC_BURST_INFO                0x0488
-#define AFE_IEC_BURST_LEN                 0x048c
-#define AFE_IEC_NSADR                     0x0490
-#define AFE_IEC_CHL_STAT0                 0x04a0
-#define AFE_IEC_CHL_STAT1                 0x04a4
-#define AFE_IEC_CHR_STAT0                 0x04a8
-#define AFE_IEC_CHR_STAT1                 0x04ac
-#define AFE_SPDIFIN_CFG0                  0x0500
-#define AFE_SPDIFIN_CFG1                  0x0504
-#define AFE_SPDIFIN_CHSTS1                0x0508
-#define AFE_SPDIFIN_CHSTS2                0x050c
-#define AFE_SPDIFIN_CHSTS3                0x0510
-#define AFE_SPDIFIN_CHSTS4                0x0514
-#define AFE_SPDIFIN_CHSTS5                0x0518
-#define AFE_SPDIFIN_CHSTS6                0x051c
-#define AFE_SPDIFIN_DEBUG1                0x0520
-#define AFE_SPDIFIN_DEBUG2                0x0524
-#define AFE_SPDIFIN_DEBUG3                0x0528
-#define AFE_SPDIFIN_DEBUG4                0x052c
-#define AFE_SPDIFIN_EC                    0x0530
-#define AFE_SPDIFIN_CKLOCK_CFG            0x0534
-#define AFE_SPDIFIN_BR                    0x053c
-#define AFE_SPDIFIN_BR_DBG1               0x0540
-#define AFE_SPDIFIN_CKFBDIV               0x0544
-#define AFE_SPDIFIN_INT_EXT               0x0548
-#define AFE_SPDIFIN_INT_EXT2              0x054c
-#define SPDIFIN_FREQ_INFO                 0x0550
-#define SPDIFIN_FREQ_INFO_2               0x0554
-#define SPDIFIN_FREQ_INFO_3               0x0558
-#define SPDIFIN_FREQ_STATUS               0x055c
-#define SPDIFIN_USERCODE1                 0x0560
-#define SPDIFIN_USERCODE2                 0x0564
-#define SPDIFIN_USERCODE3                 0x0568
-#define SPDIFIN_USERCODE4                 0x056c
-#define SPDIFIN_USERCODE5                 0x0570
-#define SPDIFIN_USERCODE6                 0x0574
-#define SPDIFIN_USERCODE7                 0x0578
-#define SPDIFIN_USERCODE8                 0x057c
-#define SPDIFIN_USERCODE9                 0x0580
-#define SPDIFIN_USERCODE10                0x0584
-#define SPDIFIN_USERCODE11                0x0588
-#define SPDIFIN_USERCODE12                0x058c
-#define AFE_SPDIFIN_APLL_TUNER_CFG        0x0594
-#define AFE_SPDIFIN_APLL_TUNER_CFG1       0x0598
-#define ASYS_TOP_CON                      0x0600
-#define AFE_LINEIN_APLL_TUNER_CFG         0x0610
-#define AFE_LINEIN_APLL_TUNER_MON         0x0614
-#define AFE_EARC_APLL_TUNER_CFG           0x0618
-#define AFE_EARC_APLL_TUNER_MON           0x061c
-#define PWR2_TOP_CON0                     0x0634
-#define PWR2_TOP_CON1                     0x0638
-#define PCM_INTF_CON1                     0x063c
-#define PCM_INTF_CON2                     0x0640
-#define AFE_CM0_CON                       0x0660
-#define AFE_CM1_CON                       0x0664
-#define AFE_CM2_CON                       0x0668
-#define AFE_CM0_MON                       0x0670
-#define AFE_CM1_MON                       0x0674
-#define AFE_CM2_MON                       0x0678
-#define AFE_MPHONE_MULTI_CON0             0x06a4
-#define AFE_MPHONE_MULTI_CON1             0x06a8
-#define AFE_MPHONE_MULTI_CON2             0x06ac
-#define AFE_MPHONE_MULTI_MON              0x06b0
-#define AFE_MPHONE_MULTI_DET_REG_CON0     0x06b4
-#define AFE_MPHONE_MULTI_DET_REG_CON1     0x06b8
-#define AFE_MPHONE_MULTI_DET_REG_CON2     0x06bc
-#define AFE_MPHONE_MULTI_DET_REG_CON3     0x06c0
-#define AFE_MPHONE_MULTI_DET_MON0         0x06c4
-#define AFE_MPHONE_MULTI_DET_MON1         0x06c8
-#define AFE_MPHONE_MULTI_DET_MON2         0x06d0
-#define AFE_MPHONE_MULTI2_CON0            0x06d4
-#define AFE_MPHONE_MULTI2_CON1            0x06d8
-#define AFE_MPHONE_MULTI2_CON2            0x06dc
-#define AFE_MPHONE_MULTI2_MON             0x06e0
-#define AFE_MPHONE_MULTI2_DET_REG_CON0    0x06e4
-#define AFE_MPHONE_MULTI2_DET_REG_CON1    0x06e8
-#define AFE_MPHONE_MULTI2_DET_REG_CON2    0x06ec
-#define AFE_MPHONE_MULTI2_DET_REG_CON3    0x06f0
-#define AFE_MPHONE_MULTI2_DET_MON0        0x06f4
-#define AFE_MPHONE_MULTI2_DET_MON1        0x06f8
-#define AFE_MPHONE_MULTI2_DET_MON2        0x06fc
-#define AFE_ADDA_IIR_COEF_02_01           0x0700
-#define AFE_ADDA_IIR_COEF_04_03           0x0704
-#define AFE_ADDA_IIR_COEF_06_05           0x0708
-#define AFE_ADDA_IIR_COEF_08_07           0x070c
-#define AFE_ADDA_IIR_COEF_10_09           0x0710
-#define AFE_ADDA_ULCF_CFG_02_01           0x0714
-#define AFE_ADDA_ULCF_CFG_04_03           0x0718
-#define AFE_ADDA_ULCF_CFG_06_05           0x071c
-#define AFE_ADDA_ULCF_CFG_08_07           0x0720
-#define AFE_ADDA_ULCF_CFG_10_09           0x0724
-#define AFE_ADDA_ULCF_CFG_12_11           0x0728
-#define AFE_ADDA_ULCF_CFG_14_13           0x072c
-#define AFE_ADDA_ULCF_CFG_16_15           0x0730
-#define AFE_ADDA_ULCF_CFG_18_17           0x0734
-#define AFE_ADDA_ULCF_CFG_20_19           0x0738
-#define AFE_ADDA_ULCF_CFG_22_21           0x073c
-#define AFE_ADDA_ULCF_CFG_24_23           0x0740
-#define AFE_ADDA_ULCF_CFG_26_25           0x0744
-#define AFE_ADDA_ULCF_CFG_28_27           0x0748
-#define AFE_ADDA_ULCF_CFG_30_29           0x074c
-#define AFE_ADDA6_IIR_COEF_02_01          0x0750
-#define AFE_ADDA6_IIR_COEF_04_03          0x0754
-#define AFE_ADDA6_IIR_COEF_06_05          0x0758
-#define AFE_ADDA6_IIR_COEF_08_07          0x075c
-#define AFE_ADDA6_IIR_COEF_10_09          0x0760
-#define AFE_ADDA6_ULCF_CFG_02_01          0x0764
-#define AFE_ADDA6_ULCF_CFG_04_03          0x0768
-#define AFE_ADDA6_ULCF_CFG_06_05          0x076c
-#define AFE_ADDA6_ULCF_CFG_08_07          0x0770
-#define AFE_ADDA6_ULCF_CFG_10_09          0x0774
-#define AFE_ADDA6_ULCF_CFG_12_11          0x0778
-#define AFE_ADDA6_ULCF_CFG_14_13          0x077c
-#define AFE_ADDA6_ULCF_CFG_16_15          0x0780
-#define AFE_ADDA6_ULCF_CFG_18_17          0x0784
-#define AFE_ADDA6_ULCF_CFG_20_19          0x0788
-#define AFE_ADDA6_ULCF_CFG_22_21          0x078c
-#define AFE_ADDA6_ULCF_CFG_24_23          0x0790
-#define AFE_ADDA6_ULCF_CFG_26_25          0x0794
-#define AFE_ADDA6_ULCF_CFG_28_27          0x0798
-#define AFE_ADDA6_ULCF_CFG_30_29          0x079c
-#define AFE_ADDA_MTKAIF_CFG0              0x07a0
-#define AFE_ADDA_MTKAIF_SYNCWORD_CFG      0x07a8
-#define AFE_ADDA_MTKAIF_RX_CFG0           0x07b4
-#define AFE_ADDA_MTKAIF_RX_CFG1           0x07b8
-#define AFE_ADDA_MTKAIF_RX_CFG2           0x07bc
-#define AFE_ADDA_MTKAIF_MON0              0x07c8
-#define AFE_ADDA_MTKAIF_MON1              0x07cc
-#define AFE_AUD_PAD_TOP                   0x07d4
-#define AFE_ADDA6_MTKAIF_MON0             0x07d8
-#define AFE_ADDA6_MTKAIF_MON1             0x07dc
-#define AFE_ADDA6_MTKAIF_CFG0             0x07e0
-#define AFE_ADDA6_MTKAIF_RX_CFG0          0x07e4
-#define AFE_ADDA6_MTKAIF_RX_CFG1          0x07e8
-#define AFE_ADDA6_MTKAIF_RX_CFG2          0x07ec
-#define AFE_ADDA6_TOP_CON0                0x07f0
-#define AFE_ADDA6_UL_SRC_CON0             0x07f4
-#define AFE_ADDA6_UL_SRC_CON1             0x07f8
-#define AFE_ADDA6_SRC_DEBUG               0x0800
-#define AFE_ADDA6_SRC_DEBUG_MON0          0x0804
-#define AFE_ADDA6_UL_SRC_MON0             0x0818
-#define AFE_ADDA6_UL_SRC_MON1             0x081c
-#define AFE_CONN0_5                       0x0830
-#define AFE_CONN1_5                       0x0834
-#define AFE_CONN2_5                       0x0838
-#define AFE_CONN3_5                       0x083c
-#define AFE_CONN4_5                       0x0840
-#define AFE_CONN5_5                       0x0844
-#define AFE_CONN6_5                       0x0848
-#define AFE_CONN7_5                       0x084c
-#define AFE_CONN8_5                       0x0850
-#define AFE_CONN9_5                       0x0854
-#define AFE_CONN10_5                      0x0858
-#define AFE_CONN11_5                      0x085c
-#define AFE_CONN12_5                      0x0860
-#define AFE_CONN13_5                      0x0864
-#define AFE_CONN14_5                      0x0868
-#define AFE_CONN15_5                      0x086c
-#define AFE_CONN16_5                      0x0870
-#define AFE_CONN17_5                      0x0874
-#define AFE_CONN18_5                      0x0878
-#define AFE_CONN19_5                      0x087c
-#define AFE_CONN20_5                      0x0880
-#define AFE_CONN21_5                      0x0884
-#define AFE_CONN22_5                      0x0888
-#define AFE_CONN23_5                      0x088c
-#define AFE_CONN24_5                      0x0890
-#define AFE_CONN25_5                      0x0894
-#define AFE_CONN26_5                      0x0898
-#define AFE_CONN27_5                      0x089c
-#define AFE_CONN28_5                      0x08a0
-#define AFE_CONN29_5                      0x08a4
-#define AFE_CONN30_5                      0x08a8
-#define AFE_CONN31_5                      0x08ac
-#define AFE_CONN32_5                      0x08b0
-#define AFE_CONN33_5                      0x08b4
-#define AFE_CONN34_5                      0x08b8
-#define AFE_CONN35_5                      0x08bc
-#define AFE_CONN36_5                      0x08c0
-#define AFE_CONN37_5                      0x08c4
-#define AFE_CONN38_5                      0x08c8
-#define AFE_CONN39_5                      0x08cc
-#define AFE_CONN40_5                      0x08d0
-#define AFE_CONN41_5                      0x08d4
-#define AFE_CONN42_5                      0x08d8
-#define AFE_CONN43_5                      0x08dc
-#define AFE_CONN44_5                      0x08e0
-#define AFE_CONN45_5                      0x08e4
-#define AFE_CONN46_5                      0x08e8
-#define AFE_CONN47_5                      0x08ec
-#define AFE_CONN48_5                      0x08f0
-#define AFE_CONN49_5                      0x08f4
-#define AFE_CONN50_5                      0x08f8
-#define AFE_CONN51_5                      0x08fc
-#define AFE_CONN52_5                      0x0900
-#define AFE_CONN53_5                      0x0904
-#define AFE_CONN54_5                      0x0908
-#define AFE_CONN55_5                      0x090c
-#define AFE_CONN56_5                      0x0910
-#define AFE_CONN57_5                      0x0914
-#define AFE_CONN58_5                      0x0918
-#define AFE_CONN59_5                      0x091c
-#define AFE_CONN60_5                      0x0920
-#define AFE_CONN61_5                      0x0924
-#define AFE_CONN62_5                      0x0928
-#define AFE_CONN63_5                      0x092c
-#define AFE_CONN64_5                      0x0930
-#define AFE_CONN65_5                      0x0934
-#define AFE_CONN66_5                      0x0938
-#define AFE_CONN67_5                      0x093c
-#define AFE_CONN68_5                      0x0940
-#define AFE_CONN69_5                      0x0944
-#define AFE_CONN70_5                      0x0948
-#define AFE_CONN71_5                      0x094c
-#define AFE_CONN72_5                      0x0950
-#define AFE_CONN73_5                      0x0954
-#define AFE_CONN74_5                      0x0958
-#define AFE_CONN75_5                      0x095c
-#define AFE_CONN76_5                      0x0960
-#define AFE_CONN77_5                      0x0964
-#define AFE_CONN78_5                      0x0968
-#define AFE_CONN79_5                      0x096c
-#define AFE_CONN80_5                      0x0970
-#define AFE_CONN81_5                      0x0974
-#define AFE_CONN82_5                      0x0978
-#define AFE_CONN83_5                      0x097c
-#define AFE_CONN84_5                      0x0980
-#define AFE_CONN85_5                      0x0984
-#define AFE_CONN86_5                      0x0988
-#define AFE_CONN87_5                      0x098c
-#define AFE_CONN88_5                      0x0990
-#define AFE_CONN89_5                      0x0994
-#define AFE_CONN90_5                      0x0998
-#define AFE_CONN91_5                      0x099c
-#define AFE_CONN92_5                      0x09a0
-#define AFE_CONN93_5                      0x09a4
-#define AFE_CONN94_5                      0x09a8
-#define AFE_CONN95_5                      0x09ac
-#define AFE_CONN96_5                      0x09b0
-#define AFE_CONN97_5                      0x09b4
-#define AFE_CONN98_5                      0x09b8
-#define AFE_CONN99_5                      0x09bc
-#define AFE_CONN100_5                     0x09c0
-#define AFE_CONN101_5                     0x09c4
-#define AFE_CONN102_5                     0x09c8
-#define AFE_CONN103_5                     0x09cc
-#define AFE_CONN104_5                     0x09d0
-#define AFE_CONN105_5                     0x09d4
-#define AFE_CONN106_5                     0x09d8
-#define AFE_CONN107_5                     0x09dc
-#define AFE_CONN108_5                     0x09e0
-#define AFE_CONN109_5                     0x09e4
-#define AFE_CONN110_5                     0x09e8
-#define AFE_CONN111_5                     0x09ec
-#define AFE_CONN112_5                     0x09f0
-#define AFE_CONN113_5                     0x09f4
-#define AFE_CONN114_5                     0x09f8
-#define AFE_CONN115_5                     0x09fc
-#define AFE_CONN116_5                     0x0a00
-#define AFE_CONN117_5                     0x0a04
-#define AFE_CONN118_5                     0x0a08
-#define AFE_CONN119_5                     0x0a0c
-#define AFE_CONN120_5                     0x0a10
-#define AFE_CONN121_5                     0x0a14
-#define AFE_CONN122_5                     0x0a18
-#define AFE_CONN123_5                     0x0a1c
-#define AFE_CONN124_5                     0x0a20
-#define AFE_CONN125_5                     0x0a24
-#define AFE_CONN126_5                     0x0a28
-#define AFE_CONN127_5                     0x0a2c
-#define AFE_CONN128_5                     0x0a30
-#define AFE_CONN129_5                     0x0a34
-#define AFE_CONN130_5                     0x0a38
-#define AFE_CONN131_5                     0x0a3c
-#define AFE_CONN132_5                     0x0a40
-#define AFE_CONN133_5                     0x0a44
-#define AFE_CONN134_5                     0x0a48
-#define AFE_CONN135_5                     0x0a4c
-#define AFE_CONN136_5                     0x0a50
-#define AFE_CONN137_5                     0x0a54
-#define AFE_CONN138_5                     0x0a58
-#define AFE_CONN139_5                     0x0a5c
-#define AFE_CONN_RS_5                     0x0a60
-#define AFE_CONN_DI_5                     0x0a64
-#define AFE_CONN_16BIT_5                  0x0a68
-#define AFE_CONN_24BIT_5                  0x0a6c
-#define AFE_SECURE_MASK_CONN53_5          0x0a70
-#define AFE_SECURE_MASK_CONN54_5          0x0a74
-#define AFE_SECURE_MASK_CONN55_5          0x0a78
-#define AFE_SECURE_MASK_CONN56_5          0x0a7c
-#define AFE_SECURE_MASK_CONN57_5          0x0a80
-#define AFE_SECURE_MASK_CONN58_5          0x0a84
-#define AFE_SECURE_MASK_CONN59_5          0x0a88
-#define AFE_SECURE_MASK_CONN60_5          0x0a8c
-#define AFE_SECURE_MASK_CONN61_5          0x0a90
-#define AFE_SECURE_MASK_CONN62_5          0x0a94
-#define AFE_SECURE_MASK_CONN63_5          0x0a98
-#define AFE_SECURE_MASK_CONN64_5          0x0a9c
-#define AFE_SECURE_MASK_CONN65_5          0x0aa0
-#define AFE_SECURE_MASK_CONN66_5          0x0aa4
-#define AFE_SECURE_MASK_CONN67_5          0x0aa8
-#define AFE_SECURE_MASK_CONN68_5          0x0aac
-#define AFE_SECURE_MASK_CONN69_5          0x0ab0
-#define AFE_SECURE_MASK_CONN70_5          0x0ab4
-#define AFE_SECURE_MASK_CONN71_5          0x0ab8
-#define AFE_SECURE_MASK_CONN72_5          0x0abc
-#define AFE_SECURE_MASK_CONN73_5          0x0ac0
-#define AFE_SECURE_MASK_CONN74_5          0x0ac4
-#define AFE_SECURE_MASK_CONN75_5          0x0ac8
-#define AFE_SECURE_MASK_CONN76_5          0x0acc
-#define AFE_SECURE_MASK_CONN77_5          0x0ad0
-#define AFE_SECURE_MASK_CONN78_5          0x0ad4
-#define AFE_SECURE_MASK_CONN79_5          0x0ad8
-#define AFE_SECURE_MASK_CONN80_5          0x0adc
-#define AFE_SECURE_MASK_CONN81_5          0x0ae0
-#define AFE_SECURE_MASK_CONN82_5          0x0ae4
-#define AFE_SECURE_MASK_CONN83_5          0x0ae8
-#define AFE_SECURE_MASK_CONN84_5          0x0aec
-#define AFE_SECURE_MASK_CONN85_5          0x0af0
-#define AFE_SECURE_MASK_CONN86_5          0x0af4
-#define AFE_SECURE_MASK_CONN87_5          0x0af8
-#define AFE_SECURE_MASK_CONN88_5          0x0afc
-#define AFE_SECURE_MASK_CONN89_5          0x0b00
-#define AFE_SECURE_MASK_CONN90_5          0x0b04
-#define AFE_SECURE_MASK_CONN91_5          0x0b08
-#define AFE_SECURE_MASK_CONN92_5          0x0b0c
-#define AFE_SECURE_MASK_CONN93_5          0x0b10
-#define AFE_SECURE_MASK_CONN94_5          0x0b14
-#define AFE_SECURE_MASK_CONN95_5          0x0b18
-#define AFE_SECURE_MASK_CONN96_5          0x0b1c
-#define AFE_SECURE_MASK_CONN97_5          0x0b20
-#define AFE_SECURE_MASK_CONN98_5          0x0b24
-#define AFE_SECURE_MASK_CONN99_5          0x0b28
-#define AFE_SECURE_MASK_CONN100_5         0x0b2c
-#define AFE_SECURE_MASK_CONN101_5         0x0b30
-#define AFE_SECURE_MASK_CONN102_5         0x0b34
-#define AFE_SECURE_MASK_CONN103_5         0x0b38
-#define AFE_SECURE_MASK_CONN104_5         0x0b3c
-#define AFE_SECURE_MASK_CONN105_5         0x0b40
-#define AFE_SECURE_MASK_CONN106_5         0x0b44
-#define AFE_SECURE_MASK_CONN107_5         0x0b48
-#define AFE_SECURE_MASK_CONN108_5         0x0b4c
-#define AFE_SECURE_MASK_CONN109_5         0x0b50
-#define AFE_SECURE_MASK_CONN110_5         0x0b54
-#define AFE_SECURE_MASK_CONN111_5         0x0b58
-#define AFE_SECURE_MASK_CONN112_5         0x0b5c
-#define AFE_SECURE_MASK_CONN113_5         0x0b60
-#define AFE_SECURE_MASK_CONN114_5         0x0b64
-#define AFE_SECURE_MASK_CONN115_5         0x0b68
-#define AFE_SECURE_MASK_CONN116_5         0x0b6c
-#define AFE_SECURE_MASK_CONN117_5         0x0b70
-#define AFE_SECURE_MASK_CONN118_5         0x0b74
-#define AFE_SECURE_MASK_CONN119_5         0x0b78
-#define AFE_SECURE_MASK_CONN120_5         0x0b7c
-#define AFE_SECURE_MASK_CONN121_5         0x0b80
-#define AFE_SECURE_MASK_CONN122_5         0x0b84
-#define AFE_SECURE_MASK_CONN123_5         0x0b88
-#define AFE_SECURE_MASK_CONN124_5         0x0b8c
-#define AFE_SECURE_MASK_CONN125_5         0x0b90
-#define AFE_SECURE_MASK_CONN126_5         0x0b94
-#define AFE_SECURE_MASK_CONN127_5         0x0b98
-#define AFE_SECURE_MASK_CONN128_5         0x0b9c
-#define AFE_SECURE_MASK_CONN129_5         0x0ba0
-#define AFE_SECURE_MASK_CONN130_5         0x0ba4
-#define AFE_SECURE_MASK_CONN131_5         0x0ba8
-#define AFE_SECURE_MASK_CONN132_5         0x0bac
-#define AFE_SECURE_MASK_CONN133_5         0x0bb0
-#define AFE_SECURE_MASK_CONN134_5         0x0bb4
-#define AFE_SECURE_MASK_CONN135_5         0x0bb8
-#define AFE_SECURE_MASK_CONN136_5         0x0bbc
-#define AFE_SECURE_MASK_CONN137_5         0x0bc0
-#define AFE_SECURE_MASK_CONN138_5         0x0bc4
-#define AFE_SECURE_MASK_CONN139_5         0x0bc8
-#define AFE_SECURE_MASK_CONN_RS_5         0x0bcc
-#define AFE_SECURE_MASK_CONN_16BIT_5      0x0bd0
-#define AFE_SECURE_MASK_CONN_24BIT_5      0x0bd4
-#define AFE_ASRC11_NEW_CON0               0x0d80
-#define AFE_ASRC11_NEW_CON1               0x0d84
-#define AFE_ASRC11_NEW_CON2               0x0d88
-#define AFE_ASRC11_NEW_CON3               0x0d8c
-#define AFE_ASRC11_NEW_CON4               0x0d90
-#define AFE_ASRC11_NEW_CON5               0x0d94
-#define AFE_ASRC11_NEW_CON6               0x0d98
-#define AFE_ASRC11_NEW_CON7               0x0d9c
-#define AFE_ASRC11_NEW_CON8               0x0da0
-#define AFE_ASRC11_NEW_CON9               0x0da4
-#define AFE_ASRC11_NEW_CON10              0x0da8
-#define AFE_ASRC11_NEW_CON11              0x0dac
-#define AFE_ASRC11_NEW_CON13              0x0db4
-#define AFE_ASRC11_NEW_CON14              0x0db8
-#define AFE_ASRC12_NEW_CON0               0x0dc0
-#define AFE_ASRC12_NEW_CON1               0x0dc4
-#define AFE_ASRC12_NEW_CON2               0x0dc8
-#define AFE_ASRC12_NEW_CON3               0x0dcc
-#define AFE_ASRC12_NEW_CON4               0x0dd0
-#define AFE_ASRC12_NEW_CON5               0x0dd4
-#define AFE_ASRC12_NEW_CON6               0x0dd8
-#define AFE_ASRC12_NEW_CON7               0x0ddc
-#define AFE_ASRC12_NEW_CON8               0x0de0
-#define AFE_ASRC12_NEW_CON9               0x0de4
-#define AFE_ASRC12_NEW_CON10              0x0de8
-#define AFE_ASRC12_NEW_CON11              0x0dec
-#define AFE_ASRC12_NEW_CON13              0x0df4
-#define AFE_ASRC12_NEW_CON14              0x0df8
-#define AFE_SECURE_MASK_CONN176           0x0fe0
-#define AFE_SECURE_MASK_CONN176_1         0x0fe4
-#define AFE_SECURE_MASK_CONN176_2         0x0fe8
-#define AFE_SECURE_MASK_CONN176_3         0x0fec
-#define AFE_SECURE_MASK_CONN176_4         0x0ff0
-#define AFE_SECURE_MASK_CONN176_5         0x0ff4
-#define AFE_SECURE_MASK_CONN177           0x0ff8
-#define AFE_SECURE_MASK_CONN177_1         0x0ffc
-#define AFE_LRCK_CNT                      0x1018
-#define AFE_SECURE_MASK_CONN177_2         0x1020
-#define AFE_SECURE_MASK_CONN177_3         0x1024
-#define AFE_SECURE_MASK_CONN177_4         0x1028
-#define AFE_SECURE_MASK_CONN177_5         0x102c
-#define AFE_SECURE_MASK_CONN182           0x1090
-#define AFE_SECURE_MASK_CONN182_1         0x1094
-#define AFE_SECURE_MASK_CONN182_2         0x1098
-#define AFE_SECURE_MASK_CONN182_3         0x109c
-#define AFE_SECURE_MASK_CONN182_4         0x10a0
-#define AFE_SECURE_MASK_CONN182_5         0x10a4
-#define AFE_SECURE_MASK_CONN183           0x10a8
-#define AFE_SECURE_MASK_CONN183_1         0x10ac
-#define AFE_SECURE_MASK_CONN183_2         0x10b0
-#define AFE_SECURE_MASK_CONN183_3         0x10b4
-#define AFE_SECURE_MASK_CONN183_4         0x10b8
-#define AFE_SECURE_MASK_CONN183_5         0x10bc
-#define AFE_DAC_CON0                      0x1200
-#define AFE_DAC_CON1                      0x1204
-#define AFE_DAC_CON2                      0x1208
-#define AFE_DAC_MON0                      0x1218
-#define AFE_DL1_BASE                      0x1240
-#define AFE_DL1_CUR                       0x1244
-#define AFE_DL1_END                       0x1248
-#define AFE_DL1_CON0                      0x124c
-#define AFE_DL2_BASE                      0x1250
-#define AFE_DL2_CUR                       0x1254
-#define AFE_DL2_END                       0x1258
-#define AFE_DL2_CON0                      0x125c
-#define AFE_DL3_BASE                      0x1260
-#define AFE_DL3_CUR                       0x1264
-#define AFE_DL3_END                       0x1268
-#define AFE_DL3_CON0                      0x126c
-#define AFE_DL6_BASE                      0x1290
-#define AFE_DL6_CUR                       0x1294
-#define AFE_DL6_END                       0x1298
-#define AFE_DL6_CON0                      0x129c
-#define AFE_DL7_BASE                      0x12a0
-#define AFE_DL7_CUR                       0x12a4
-#define AFE_DL7_END                       0x12a8
-#define AFE_DL7_CON0                      0x12ac
-#define AFE_DL8_BASE                      0x12b0
-#define AFE_DL8_CUR                       0x12b4
-#define AFE_DL8_END                       0x12b8
-#define AFE_DL8_CON0                      0x12bc
-#define AFE_DL10_BASE                     0x12d0
-#define AFE_DL10_CUR                      0x12d4
-#define AFE_DL10_END                      0x12d8
-#define AFE_DL10_CON0                     0x12dc
-#define AFE_DL11_BASE                     0x12e0
-#define AFE_DL11_CUR                      0x12e4
-#define AFE_DL11_END                      0x12e8
-#define AFE_DL11_CON0                     0x12ec
-#define AFE_UL1_BASE                      0x1300
-#define AFE_UL1_CUR                       0x1304
-#define AFE_UL1_END                       0x1308
-#define AFE_UL1_CON0                      0x130c
-#define AFE_UL2_BASE                      0x1310
-#define AFE_UL2_CUR                       0x1314
-#define AFE_UL2_END                       0x1318
-#define AFE_UL2_CON0                      0x131c
-#define AFE_UL3_BASE                      0x1320
-#define AFE_UL3_CUR                       0x1324
-#define AFE_UL3_END                       0x1328
-#define AFE_UL3_CON0                      0x132c
-#define AFE_UL4_BASE                      0x1330
-#define AFE_UL4_CUR                       0x1334
-#define AFE_UL4_END                       0x1338
-#define AFE_UL4_CON0                      0x133c
-#define AFE_UL5_BASE                      0x1340
-#define AFE_UL5_CUR                       0x1344
-#define AFE_UL5_END                       0x1348
-#define AFE_UL5_CON0                      0x134c
-#define AFE_UL6_BASE                      0x1350
-#define AFE_UL6_CUR                       0x1354
-#define AFE_UL6_END                       0x1358
-#define AFE_UL6_CON0                      0x135c
-#define AFE_UL8_BASE                      0x1370
-#define AFE_UL8_CUR                       0x1374
-#define AFE_UL8_END                       0x1378
-#define AFE_UL8_CON0                      0x137c
-#define AFE_UL9_BASE                      0x1380
-#define AFE_UL9_CUR                       0x1384
-#define AFE_UL9_END                       0x1388
-#define AFE_UL9_CON0                      0x138c
-#define AFE_UL10_BASE                     0x13d0
-#define AFE_UL10_CUR                      0x13d4
-#define AFE_UL10_END                      0x13d8
-#define AFE_UL10_CON0                     0x13dc
-#define AFE_DL8_CHK_SUM1                  0x1400
-#define AFE_DL8_CHK_SUM2                  0x1404
-#define AFE_DL8_CHK_SUM3                  0x1408
-#define AFE_DL8_CHK_SUM4                  0x140c
-#define AFE_DL8_CHK_SUM5                  0x1410
-#define AFE_DL8_CHK_SUM6                  0x1414
-#define AFE_DL10_CHK_SUM1                 0x1418
-#define AFE_DL10_CHK_SUM2                 0x141c
-#define AFE_DL10_CHK_SUM3                 0x1420
-#define AFE_DL10_CHK_SUM4                 0x1424
-#define AFE_DL10_CHK_SUM5                 0x1428
-#define AFE_DL10_CHK_SUM6                 0x142c
-#define AFE_DL11_CHK_SUM1                 0x1430
-#define AFE_DL11_CHK_SUM2                 0x1434
-#define AFE_DL11_CHK_SUM3                 0x1438
-#define AFE_DL11_CHK_SUM4                 0x143c
-#define AFE_DL11_CHK_SUM5                 0x1440
-#define AFE_DL11_CHK_SUM6                 0x1444
-#define AFE_UL1_CHK_SUM1                  0x1450
-#define AFE_UL1_CHK_SUM2                  0x1454
-#define AFE_UL2_CHK_SUM1                  0x1458
-#define AFE_UL2_CHK_SUM2                  0x145c
-#define AFE_UL3_CHK_SUM1                  0x1460
-#define AFE_UL3_CHK_SUM2                  0x1464
-#define AFE_UL4_CHK_SUM1                  0x1468
-#define AFE_UL4_CHK_SUM2                  0x146c
-#define AFE_UL5_CHK_SUM1                  0x1470
-#define AFE_UL5_CHK_SUM2                  0x1474
-#define AFE_UL6_CHK_SUM1                  0x1478
-#define AFE_UL6_CHK_SUM2                  0x147c
-#define AFE_UL8_CHK_SUM1                  0x1488
-#define AFE_UL8_CHK_SUM2                  0x148c
-#define AFE_DL1_CHK_SUM1                  0x1490
-#define AFE_DL1_CHK_SUM2                  0x1494
-#define AFE_DL2_CHK_SUM1                  0x14a0
-#define AFE_DL2_CHK_SUM2                  0x14a4
-#define AFE_DL3_CHK_SUM1                  0x14b0
-#define AFE_DL3_CHK_SUM2                  0x14b4
-#define AFE_DL6_CHK_SUM1                  0x14e0
-#define AFE_DL6_CHK_SUM2                  0x14e4
-#define AFE_DL7_CHK_SUM1                  0x14f0
-#define AFE_DL7_CHK_SUM2                  0x14f4
-#define AFE_UL9_CHK_SUM1                  0x1528
-#define AFE_UL9_CHK_SUM2                  0x152c
-#define AFE_BUS_MON1                      0x1540
-#define AFE_UL10_CHK_SUM1                 0x1550
-#define AFE_UL10_CHK_SUM2                 0x1554
-#define UL1_MOD2AGT_CNT_LAT               0x1568
-#define UL2_MOD2AGT_CNT_LAT               0x156c
-#define UL3_MOD2AGT_CNT_LAT               0x1570
-#define UL4_MOD2AGT_CNT_LAT               0x1574
-#define UL5_MOD2AGT_CNT_LAT               0x1578
-#define UL6_MOD2AGT_CNT_LAT               0x157c
-#define UL8_MOD2AGT_CNT_LAT               0x1588
-#define UL9_MOD2AGT_CNT_LAT               0x158c
-#define UL10_MOD2AGT_CNT_LAT              0x1590
-#define AFE_MEMIF_AGENT_FS_CON0           0x15a0
-#define AFE_MEMIF_AGENT_FS_CON1           0x15a4
-#define AFE_MEMIF_AGENT_FS_CON2           0x15a8
-#define AFE_MEMIF_AGENT_FS_CON3           0x15ac
-#define AFE_MEMIF_BURST_CFG               0x1600
-#define AFE_MEMIF_BUF_FULL_MON            0x1610
-#define AFE_MEMIF_BUF_MON0                0x1618
-#define AFE_MEMIF_BUF_MON1                0x161c
-#define AFE_MEMIF_BUF_MON3                0x1624
-#define AFE_MEMIF_BUF_MON4                0x1628
-#define AFE_MEMIF_BUF_MON5                0x162c
-#define AFE_MEMIF_BUF_MON6                0x1630
-#define AFE_MEMIF_BUF_MON7                0x1634
-#define AFE_MEMIF_BUF_MON8                0x1638
-#define AFE_MEMIF_BUF_MON9                0x163c
-#define AFE_MEMIF_BUF_MON10               0x1640
-#define DL1_AGENT2MODULE_CNT              0x1674
-#define DL2_AGENT2MODULE_CNT              0x1678
-#define DL3_AGENT2MODULE_CNT              0x167c
-#define DL6_AGENT2MODULE_CNT              0x1688
-#define DL7_AGENT2MODULE_CNT              0x168c
-#define DL8_AGENT2MODULE_CNT              0x1690
-#define DL10_AGENT2MODULE_CNT             0x1698
-#define DL11_AGENT2MODULE_CNT             0x169c
-#define UL1_MODULE2AGENT_CNT              0x16a0
-#define UL2_MODULE2AGENT_CNT              0x16a4
-#define UL3_MODULE2AGENT_CNT              0x16a8
-#define UL4_MODULE2AGENT_CNT              0x16ac
-#define UL5_MODULE2AGENT_CNT              0x16b0
-#define UL6_MODULE2AGENT_CNT              0x16b4
-#define UL8_MODULE2AGENT_CNT              0x16bc
-#define UL9_MODULE2AGENT_CNT              0x16c0
-#define UL10_MODULE2AGENT_CNT             0x16c4
-#define AFE_SECURE_CON2                   0x1798
-#define AFE_SECURE_CON1                   0x179c
-#define AFE_SECURE_CON                    0x17a0
-#define AFE_SRAM_BOUND                    0x17a4
-#define AFE_SE_SECURE_CON                 0x17a8
-#define AFE_SECURE_MASK_LOOPBACK          0x17bc
-#define AFE_SRAM_SECURE_CON               0x1800
-#define AFE_SRAM_SECURE_CON1              0x1804
-#define AFE_SRAM_SECURE_CON2              0x1808
-#define AFE_SECURE_SIDEBAND0              0x1908
-#define AFE_SECURE_SIDEBAND1              0x190c
-#define AFE_SECURE_SIDEBAND2              0x1910
-#define AFE_SECURE_SIDEBAND3              0x1914
-#define AFE_SECURE_MASK_BASE_ADR_MSB      0x1920
-#define AFE_SECURE_MASK_END_ADR_MSB       0x1924
-#define AFE_NORMAL_BASE_ADR_MSB           0x192c
-#define AFE_NORMAL_END_ADR_MSB            0x1930
-#define AFE_SECURE_MASK_LOOPBACK0         0x1940
-#define AFE_SECURE_MASK_LOOPBACK1         0x1944
-#define AFE_SECURE_MASK_LOOPBACK2         0x1948
-#define AFE_LOOPBACK_CFG0                 0x1950
-#define AFE_LOOPBACK_CFG1                 0x1954
-#define AFE_LOOPBACK_CFG2                 0x1958
-#define AFE_DMIC0_UL_SRC_CON0             0x1a00
-#define AFE_DMIC0_UL_SRC_CON1             0x1a04
-#define AFE_DMIC0_SRC_DEBUG               0x1a08
-#define AFE_DMIC0_SRC_DEBUG_MON0          0x1a0c
-#define AFE_DMIC0_UL_SRC_MON0             0x1a10
-#define AFE_DMIC0_UL_SRC_MON1             0x1a14
-#define AFE_DMIC0_IIR_COEF_02_01          0x1a18
-#define AFE_DMIC0_IIR_COEF_04_03          0x1a1c
-#define AFE_DMIC0_IIR_COEF_06_05          0x1a20
-#define AFE_DMIC0_IIR_COEF_08_07          0x1a24
-#define AFE_DMIC0_IIR_COEF_10_09          0x1a28
-#define AFE_DMIC1_UL_SRC_CON0             0x1a68
-#define AFE_DMIC1_UL_SRC_CON1             0x1a6c
-#define AFE_DMIC1_SRC_DEBUG               0x1a70
-#define AFE_DMIC1_SRC_DEBUG_MON0          0x1a74
-#define AFE_DMIC1_UL_SRC_MON0             0x1a78
-#define AFE_DMIC1_UL_SRC_MON1             0x1a7c
-#define AFE_DMIC1_IIR_COEF_02_01          0x1a80
-#define AFE_DMIC1_IIR_COEF_04_03          0x1a84
-#define AFE_DMIC1_IIR_COEF_06_05          0x1a88
-#define AFE_DMIC1_IIR_COEF_08_07          0x1a8c
-#define AFE_DMIC1_IIR_COEF_10_09          0x1a90
-#define AFE_DMIC2_UL_SRC_CON0             0x1ad0
-#define AFE_DMIC2_UL_SRC_CON1             0x1ad4
-#define AFE_DMIC2_SRC_DEBUG               0x1ad8
-#define AFE_DMIC2_SRC_DEBUG_MON0          0x1adc
-#define AFE_DMIC2_UL_SRC_MON0             0x1ae0
-#define AFE_DMIC2_UL_SRC_MON1             0x1ae4
-#define AFE_DMIC2_IIR_COEF_02_01          0x1ae8
-#define AFE_DMIC2_IIR_COEF_04_03          0x1aec
-#define AFE_DMIC2_IIR_COEF_06_05          0x1af0
-#define AFE_DMIC2_IIR_COEF_08_07          0x1af4
-#define AFE_DMIC2_IIR_COEF_10_09          0x1af8
-#define AFE_DMIC3_UL_SRC_CON0             0x1b38
-#define AFE_DMIC3_UL_SRC_CON1             0x1b3c
-#define AFE_DMIC3_SRC_DEBUG               0x1b40
-#define AFE_DMIC3_SRC_DEBUG_MON0          0x1b44
-#define AFE_DMIC3_UL_SRC_MON0             0x1b48
-#define AFE_DMIC3_UL_SRC_MON1             0x1b4c
-#define AFE_DMIC3_IIR_COEF_02_01          0x1b50
-#define AFE_DMIC3_IIR_COEF_04_03          0x1b54
-#define AFE_DMIC3_IIR_COEF_06_05          0x1b58
-#define AFE_DMIC3_IIR_COEF_08_07          0x1b5c
-#define AFE_DMIC3_IIR_COEF_10_09          0x1b60
-#define DMIC_BYPASS_HW_GAIN               0x1bf0
-#define DMIC_GAIN1_CON0                   0x1c00
-#define DMIC_GAIN1_CON1                   0x1c04
-#define DMIC_GAIN1_CON2                   0x1c08
-#define DMIC_GAIN1_CON3                   0x1c0c
-#define DMIC_GAIN1_CUR                    0x1c10
-#define DMIC_GAIN2_CON0                   0x1c20
-#define DMIC_GAIN2_CON1                   0x1c24
-#define DMIC_GAIN2_CON2                   0x1c28
-#define DMIC_GAIN2_CON3                   0x1c2c
-#define DMIC_GAIN2_CUR                    0x1c30
-#define DMIC_GAIN3_CON0                   0x1c40
-#define DMIC_GAIN3_CON1                   0x1c44
-#define DMIC_GAIN3_CON2                   0x1c48
-#define DMIC_GAIN3_CON3                   0x1c4c
-#define DMIC_GAIN3_CUR                    0x1c50
-#define DMIC_GAIN4_CON0                   0x1c60
-#define DMIC_GAIN4_CON1                   0x1c64
-#define DMIC_GAIN4_CON2                   0x1c68
-#define DMIC_GAIN4_CON3                   0x1c6c
-#define DMIC_GAIN4_CUR                    0x1c70
-#define ETDM_OUT1_DSD_FADE_CON            0x2260
-#define ETDM_OUT1_DSD_FADE_CON1           0x2264
-#define ETDM_OUT3_DSD_FADE_CON            0x2280
-#define ETDM_OUT3_DSD_FADE_CON1           0x2284
-#define ETDM_IN1_AFIFO_CON                0x2294
-#define ETDM_IN2_AFIFO_CON                0x2298
-#define ETDM_IN1_MONITOR                  0x22c0
-#define ETDM_IN2_MONITOR                  0x22c4
-#define ETDM_OUT1_MONITOR                 0x22d0
-#define ETDM_OUT2_MONITOR                 0x22d4
-#define ETDM_OUT3_MONITOR                 0x22d8
-#define ETDM_COWORK_SEC_CON0              0x22e0
-#define ETDM_COWORK_SEC_CON1              0x22e4
-#define ETDM_COWORK_SEC_CON2              0x22e8
-#define ETDM_COWORK_SEC_CON3              0x22ec
-#define ETDM_COWORK_CON0                  0x22f0
-#define ETDM_COWORK_CON1                  0x22f4
-#define ETDM_COWORK_CON2                  0x22f8
-#define ETDM_COWORK_CON3                  0x22fc
-#define ETDM_IN1_CON0                     0x2300
-#define ETDM_IN1_CON1                     0x2304
-#define ETDM_IN1_CON2                     0x2308
-#define ETDM_IN1_CON3                     0x230c
-#define ETDM_IN1_CON4                     0x2310
-#define ETDM_IN1_CON5                     0x2314
-#define ETDM_IN1_CON6                     0x2318
-#define ETDM_IN1_CON7                     0x231c
-#define ETDM_IN2_CON0                     0x2320
-#define ETDM_IN2_CON1                     0x2324
-#define ETDM_IN2_CON2                     0x2328
-#define ETDM_IN2_CON3                     0x232c
-#define ETDM_IN2_CON4                     0x2330
-#define ETDM_IN2_CON5                     0x2334
-#define ETDM_IN2_CON6                     0x2338
-#define ETDM_IN2_CON7                     0x233c
-#define ETDM_OUT1_CON0                    0x2380
-#define ETDM_OUT1_CON1                    0x2384
-#define ETDM_OUT1_CON2                    0x2388
-#define ETDM_OUT1_CON3                    0x238c
-#define ETDM_OUT1_CON4                    0x2390
-#define ETDM_OUT1_CON5                    0x2394
-#define ETDM_OUT1_CON6                    0x2398
-#define ETDM_OUT1_CON7                    0x239c
-#define ETDM_OUT2_CON0                    0x23a0
-#define ETDM_OUT2_CON1                    0x23a4
-#define ETDM_OUT2_CON2                    0x23a8
-#define ETDM_OUT2_CON3                    0x23ac
-#define ETDM_OUT2_CON4                    0x23b0
-#define ETDM_OUT2_CON5                    0x23b4
-#define ETDM_OUT2_CON6                    0x23b8
-#define ETDM_OUT2_CON7                    0x23bc
-#define ETDM_OUT3_CON0                    0x23c0
-#define ETDM_OUT3_CON1                    0x23c4
-#define ETDM_OUT3_CON2                    0x23c8
-#define ETDM_OUT3_CON3                    0x23cc
-#define ETDM_OUT3_CON4                    0x23d0
-#define ETDM_OUT3_CON5                    0x23d4
-#define ETDM_OUT3_CON6                    0x23d8
-#define ETDM_OUT3_CON7                    0x23dc
-#define ETDM_OUT3_CON8                    0x23e0
-#define ETDM_OUT1_CON8                    0x23e4
-#define ETDM_OUT2_CON8                    0x23e8
-#define GASRC_TIMING_CON0                 0x2414
-#define GASRC_TIMING_CON1                 0x2418
-#define GASRC_TIMING_CON2                 0x241c
-#define GASRC_TIMING_CON3                 0x2420
-#define GASRC_TIMING_CON4                 0x2424
-#define GASRC_TIMING_CON5                 0x2428
-#define A3_A4_TIMING_SEL0                 0x2440
-#define A3_A4_TIMING_SEL1                 0x2444
-#define A3_A4_TIMING_SEL2                 0x2448
-#define A3_A4_TIMING_SEL3                 0x244c
-#define A3_A4_TIMING_SEL4                 0x2450
-#define A3_A4_TIMING_SEL5                 0x2454
-#define A3_A4_TIMING_SEL6                 0x2458
-#define ASYS_TOP_DEBUG                    0x2500
-#define AFE_DPTX_CON                      0x2558
-#define AFE_DPTX_MON                      0x255c
-#define AFE_ADDA_DL_SRC2_CON0             0x2d00
-#define AFE_ADDA_DL_SRC2_CON1             0x2d04
-#define AFE_ADDA_TOP_CON0                 0x2d0c
-#define AFE_ADDA_UL_DL_CON0               0x2d10
-#define AFE_ADDA_SRC_DEBUG                0x2d14
-#define AFE_ADDA_SRC_DEBUG_MON0           0x2d18
-#define AFE_ADDA_SRC_DEBUG_MON1           0x2d20
-#define AFE_ADDA_PREDIS_CON0              0x2d24
-#define AFE_ADDA_PREDIS_CON1              0x2d28
-#define AFE_ADDA_PREDIS_CON2              0x2d2c
-#define AFE_ADDA_PREDIS_CON3              0x2d30
-#define AFE_ADDA_DL_SDM_DCCOMP_CON        0x2d34
-#define AFE_ADDA_DL_SDM_TEST              0x2d38
-#define AFE_ADDA_DL_DC_COMP_CFG0          0x2d3c
-#define AFE_ADDA_DL_DC_COMP_CFG1          0x2d40
-#define AFE_ADDA_DL_SDM_FIFO_MON          0x2d44
-#define AFE_ADDA_DL_SRC_LCH_MON           0x2d50
-#define AFE_ADDA_DL_SRC_RCH_MON           0x2d54
-#define AFE_ADDA_DL_SDM_OUT_MON           0x2d58
-#define AFE_ADDA_DL_SDM_DITHER_CON        0x2d5c
-#define AFE_ADDA_DL_SDM_AUTO_RESET_CON    0x2d60
-#define AFE_ADDA_UL_SRC_CON0              0x2e3c
-#define AFE_ADDA_UL_SRC_CON1              0x2e40
-#define AFE_CONN0                         0x3000
-#define AFE_CONN0_1                       0x3004
-#define AFE_CONN0_2                       0x3008
-#define AFE_CONN0_3                       0x300c
-#define AFE_CONN0_4                       0x3010
-#define AFE_CONN1                         0x3014
-#define AFE_CONN1_1                       0x3018
-#define AFE_CONN1_2                       0x301c
-#define AFE_CONN1_3                       0x3020
-#define AFE_CONN1_4                       0x3024
-#define AFE_CONN2                         0x3028
-#define AFE_CONN2_1                       0x302c
-#define AFE_CONN2_2                       0x3030
-#define AFE_CONN2_3                       0x3034
-#define AFE_CONN2_4                       0x3038
-#define AFE_CONN3                         0x303c
-#define AFE_CONN3_1                       0x3040
-#define AFE_CONN3_2                       0x3044
-#define AFE_CONN3_3                       0x3048
-#define AFE_CONN3_4                       0x304c
-#define AFE_CONN4                         0x3050
-#define AFE_CONN4_1                       0x3054
-#define AFE_CONN4_2                       0x3058
-#define AFE_CONN4_3                       0x305c
-#define AFE_CONN4_4                       0x3060
-#define AFE_CONN5                         0x3064
-#define AFE_CONN5_1                       0x3068
-#define AFE_CONN5_2                       0x306c
-#define AFE_CONN5_3                       0x3070
-#define AFE_CONN5_4                       0x3074
-#define AFE_CONN6                         0x3078
-#define AFE_CONN6_1                       0x307c
-#define AFE_CONN6_2                       0x3080
-#define AFE_CONN6_3                       0x3084
-#define AFE_CONN6_4                       0x3088
-#define AFE_CONN7                         0x308c
-#define AFE_CONN7_1                       0x3090
-#define AFE_CONN7_2                       0x3094
-#define AFE_CONN7_3                       0x3098
-#define AFE_CONN7_4                       0x309c
-#define AFE_CONN8                         0x30a0
-#define AFE_CONN8_1                       0x30a4
-#define AFE_CONN8_2                       0x30a8
-#define AFE_CONN8_3                       0x30ac
-#define AFE_CONN8_4                       0x30b0
-#define AFE_CONN9                         0x30b4
-#define AFE_CONN9_1                       0x30b8
-#define AFE_CONN9_2                       0x30bc
-#define AFE_CONN9_3                       0x30c0
-#define AFE_CONN9_4                       0x30c4
-#define AFE_CONN10                        0x30c8
-#define AFE_CONN10_1                      0x30cc
-#define AFE_CONN10_2                      0x30d0
-#define AFE_CONN10_3                      0x30d4
-#define AFE_CONN10_4                      0x30d8
-#define AFE_CONN11                        0x30dc
-#define AFE_CONN11_1                      0x30e0
-#define AFE_CONN11_2                      0x30e4
-#define AFE_CONN11_3                      0x30e8
-#define AFE_CONN11_4                      0x30ec
-#define AFE_CONN12                        0x30f0
-#define AFE_CONN12_1                      0x30f4
-#define AFE_CONN12_2                      0x30f8
-#define AFE_CONN12_3                      0x30fc
-#define AFE_CONN12_4                      0x3100
-#define AFE_CONN13                        0x3104
-#define AFE_CONN13_1                      0x3108
-#define AFE_CONN13_2                      0x310c
-#define AFE_CONN13_3                      0x3110
-#define AFE_CONN13_4                      0x3114
-#define AFE_CONN14                        0x3118
-#define AFE_CONN14_1                      0x311c
-#define AFE_CONN14_2                      0x3120
-#define AFE_CONN14_3                      0x3124
-#define AFE_CONN14_4                      0x3128
-#define AFE_CONN15                        0x312c
-#define AFE_CONN15_1                      0x3130
-#define AFE_CONN15_2                      0x3134
-#define AFE_CONN15_3                      0x3138
-#define AFE_CONN15_4                      0x313c
-#define AFE_CONN16                        0x3140
-#define AFE_CONN16_1                      0x3144
-#define AFE_CONN16_2                      0x3148
-#define AFE_CONN16_3                      0x314c
-#define AFE_CONN16_4                      0x3150
-#define AFE_CONN17                        0x3154
-#define AFE_CONN17_1                      0x3158
-#define AFE_CONN17_2                      0x315c
-#define AFE_CONN17_3                      0x3160
-#define AFE_CONN17_4                      0x3164
-#define AFE_CONN18                        0x3168
-#define AFE_CONN18_1                      0x316c
-#define AFE_CONN18_2                      0x3170
-#define AFE_CONN18_3                      0x3174
-#define AFE_CONN18_4                      0x3178
-#define AFE_CONN19                        0x317c
-#define AFE_CONN19_1                      0x3180
-#define AFE_CONN19_2                      0x3184
-#define AFE_CONN19_3                      0x3188
-#define AFE_CONN19_4                      0x318c
-#define AFE_CONN20                        0x3190
-#define AFE_CONN20_1                      0x3194
-#define AFE_CONN20_2                      0x3198
-#define AFE_CONN20_3                      0x319c
-#define AFE_CONN20_4                      0x31a0
-#define AFE_CONN21                        0x31a4
-#define AFE_CONN21_1                      0x31a8
-#define AFE_CONN21_2                      0x31ac
-#define AFE_CONN21_3                      0x31b0
-#define AFE_CONN21_4                      0x31b4
-#define AFE_CONN22                        0x31b8
-#define AFE_CONN22_1                      0x31bc
-#define AFE_CONN22_2                      0x31c0
-#define AFE_CONN22_3                      0x31c4
-#define AFE_CONN22_4                      0x31c8
-#define AFE_CONN23                        0x31cc
-#define AFE_CONN23_1                      0x31d0
-#define AFE_CONN23_2                      0x31d4
-#define AFE_CONN23_3                      0x31d8
-#define AFE_CONN23_4                      0x31dc
-#define AFE_CONN24                        0x31e0
-#define AFE_CONN24_1                      0x31e4
-#define AFE_CONN24_2                      0x31e8
-#define AFE_CONN24_3                      0x31ec
-#define AFE_CONN24_4                      0x31f0
-#define AFE_CONN25                        0x31f4
-#define AFE_CONN25_1                      0x31f8
-#define AFE_CONN25_2                      0x31fc
-#define AFE_CONN25_3                      0x3200
-#define AFE_CONN25_4                      0x3204
-#define AFE_CONN26                        0x3208
-#define AFE_CONN26_1                      0x320c
-#define AFE_CONN26_2                      0x3210
-#define AFE_CONN26_3                      0x3214
-#define AFE_CONN26_4                      0x3218
-#define AFE_CONN27                        0x321c
-#define AFE_CONN27_1                      0x3220
-#define AFE_CONN27_2                      0x3224
-#define AFE_CONN27_3                      0x3228
-#define AFE_CONN27_4                      0x322c
-#define AFE_CONN28                        0x3230
-#define AFE_CONN28_1                      0x3234
-#define AFE_CONN28_2                      0x3238
-#define AFE_CONN28_3                      0x323c
-#define AFE_CONN28_4                      0x3240
-#define AFE_CONN29                        0x3244
-#define AFE_CONN29_1                      0x3248
-#define AFE_CONN29_2                      0x324c
-#define AFE_CONN29_3                      0x3250
-#define AFE_CONN29_4                      0x3254
-#define AFE_CONN30                        0x3258
-#define AFE_CONN30_1                      0x325c
-#define AFE_CONN30_2                      0x3260
-#define AFE_CONN30_3                      0x3264
-#define AFE_CONN30_4                      0x3268
-#define AFE_CONN31                        0x326c
-#define AFE_CONN31_1                      0x3270
-#define AFE_CONN31_2                      0x3274
-#define AFE_CONN31_3                      0x3278
-#define AFE_CONN31_4                      0x327c
-#define AFE_CONN32                        0x3280
-#define AFE_CONN32_1                      0x3284
-#define AFE_CONN32_2                      0x3288
-#define AFE_CONN32_3                      0x328c
-#define AFE_CONN32_4                      0x3290
-#define AFE_CONN33                        0x3294
-#define AFE_CONN33_1                      0x3298
-#define AFE_CONN33_2                      0x329c
-#define AFE_CONN33_3                      0x32a0
-#define AFE_CONN33_4                      0x32a4
-#define AFE_CONN34                        0x32a8
-#define AFE_CONN34_1                      0x32ac
-#define AFE_CONN34_2                      0x32b0
-#define AFE_CONN34_3                      0x32b4
-#define AFE_CONN34_4                      0x32b8
-#define AFE_CONN35                        0x32bc
-#define AFE_CONN35_1                      0x32c0
-#define AFE_CONN35_2                      0x32c4
-#define AFE_CONN35_3                      0x32c8
-#define AFE_CONN35_4                      0x32cc
-#define AFE_CONN36                        0x32d0
-#define AFE_CONN36_1                      0x32d4
-#define AFE_CONN36_2                      0x32d8
-#define AFE_CONN36_3                      0x32dc
-#define AFE_CONN36_4                      0x32e0
-#define AFE_CONN37                        0x32e4
-#define AFE_CONN37_1                      0x32e8
-#define AFE_CONN37_2                      0x32ec
-#define AFE_CONN37_3                      0x32f0
-#define AFE_CONN37_4                      0x32f4
-#define AFE_CONN38                        0x32f8
-#define AFE_CONN38_1                      0x32fc
-#define AFE_CONN38_2                      0x3300
-#define AFE_CONN38_3                      0x3304
-#define AFE_CONN38_4                      0x3308
-#define AFE_CONN39                        0x330c
-#define AFE_CONN39_1                      0x3310
-#define AFE_CONN39_2                      0x3314
-#define AFE_CONN39_3                      0x3318
-#define AFE_CONN39_4                      0x331c
-#define AFE_CONN40                        0x3320
-#define AFE_CONN40_1                      0x3324
-#define AFE_CONN40_2                      0x3328
-#define AFE_CONN40_3                      0x332c
-#define AFE_CONN40_4                      0x3330
-#define AFE_CONN41                        0x3334
-#define AFE_CONN41_1                      0x3338
-#define AFE_CONN41_2                      0x333c
-#define AFE_CONN41_3                      0x3340
-#define AFE_CONN41_4                      0x3344
-#define AFE_CONN42                        0x3348
-#define AFE_CONN42_1                      0x334c
-#define AFE_CONN42_2                      0x3350
-#define AFE_CONN42_3                      0x3354
-#define AFE_CONN42_4                      0x3358
-#define AFE_CONN43                        0x335c
-#define AFE_CONN43_1                      0x3360
-#define AFE_CONN43_2                      0x3364
-#define AFE_CONN43_3                      0x3368
-#define AFE_CONN43_4                      0x336c
-#define AFE_CONN44                        0x3370
-#define AFE_CONN44_1                      0x3374
-#define AFE_CONN44_2                      0x3378
-#define AFE_CONN44_3                      0x337c
-#define AFE_CONN44_4                      0x3380
-#define AFE_CONN45                        0x3384
-#define AFE_CONN45_1                      0x3388
-#define AFE_CONN45_2                      0x338c
-#define AFE_CONN45_3                      0x3390
-#define AFE_CONN45_4                      0x3394
-#define AFE_CONN46                        0x3398
-#define AFE_CONN46_1                      0x339c
-#define AFE_CONN46_2                      0x33a0
-#define AFE_CONN46_3                      0x33a4
-#define AFE_CONN46_4                      0x33a8
-#define AFE_CONN47                        0x33ac
-#define AFE_CONN47_1                      0x33b0
-#define AFE_CONN47_2                      0x33b4
-#define AFE_CONN47_3                      0x33b8
-#define AFE_CONN47_4                      0x33bc
-#define AFE_CONN48                        0x33c0
-#define AFE_CONN48_1                      0x33c4
-#define AFE_CONN48_2                      0x33c8
-#define AFE_CONN48_3                      0x33cc
-#define AFE_CONN48_4                      0x33d0
-#define AFE_CONN49                        0x33d4
-#define AFE_CONN49_1                      0x33d8
-#define AFE_CONN49_2                      0x33dc
-#define AFE_CONN49_3                      0x33e0
-#define AFE_CONN49_4                      0x33e4
-#define AFE_CONN50                        0x33e8
-#define AFE_CONN50_1                      0x33ec
-#define AFE_CONN50_2                      0x33f0
-#define AFE_CONN50_3                      0x33f4
-#define AFE_CONN50_4                      0x33f8
-#define AFE_CONN51                        0x33fc
-#define AFE_CONN51_1                      0x3400
-#define AFE_CONN51_2                      0x3404
-#define AFE_CONN51_3                      0x3408
-#define AFE_CONN51_4                      0x340c
-#define AFE_CONN52                        0x3410
-#define AFE_CONN52_1                      0x3414
-#define AFE_CONN52_2                      0x3418
-#define AFE_CONN52_3                      0x341c
-#define AFE_CONN52_4                      0x3420
-#define AFE_CONN53                        0x3424
-#define AFE_CONN53_1                      0x3428
-#define AFE_CONN53_2                      0x342c
-#define AFE_CONN53_3                      0x3430
-#define AFE_CONN53_4                      0x3434
-#define AFE_CONN54                        0x3438
-#define AFE_CONN54_1                      0x343c
-#define AFE_CONN54_2                      0x3440
-#define AFE_CONN54_3                      0x3444
-#define AFE_CONN54_4                      0x3448
-#define AFE_CONN55                        0x344c
-#define AFE_CONN55_1                      0x3450
-#define AFE_CONN55_2                      0x3454
-#define AFE_CONN55_3                      0x3458
-#define AFE_CONN55_4                      0x345c
-#define AFE_CONN56                        0x3460
-#define AFE_CONN56_1                      0x3464
-#define AFE_CONN56_2                      0x3468
-#define AFE_CONN56_3                      0x346c
-#define AFE_CONN56_4                      0x3470
-#define AFE_CONN57                        0x3474
-#define AFE_CONN57_1                      0x3478
-#define AFE_CONN57_2                      0x347c
-#define AFE_CONN57_3                      0x3480
-#define AFE_CONN57_4                      0x3484
-#define AFE_CONN58                        0x3488
-#define AFE_CONN58_1                      0x348c
-#define AFE_CONN58_2                      0x3490
-#define AFE_CONN58_3                      0x3494
-#define AFE_CONN58_4                      0x3498
-#define AFE_CONN59                        0x349c
-#define AFE_CONN59_1                      0x34a0
-#define AFE_CONN59_2                      0x34a4
-#define AFE_CONN59_3                      0x34a8
-#define AFE_CONN59_4                      0x34ac
-#define AFE_CONN60                        0x34b0
-#define AFE_CONN60_1                      0x34b4
-#define AFE_CONN60_2                      0x34b8
-#define AFE_CONN60_3                      0x34bc
-#define AFE_CONN60_4                      0x34c0
-#define AFE_CONN61                        0x34c4
-#define AFE_CONN61_1                      0x34c8
-#define AFE_CONN61_2                      0x34cc
-#define AFE_CONN61_3                      0x34d0
-#define AFE_CONN61_4                      0x34d4
-#define AFE_CONN62                        0x34d8
-#define AFE_CONN62_1                      0x34dc
-#define AFE_CONN62_2                      0x34e0
-#define AFE_CONN62_3                      0x34e4
-#define AFE_CONN62_4                      0x34e8
-#define AFE_CONN63                        0x34ec
-#define AFE_CONN63_1                      0x34f0
-#define AFE_CONN63_2                      0x34f4
-#define AFE_CONN63_3                      0x34f8
-#define AFE_CONN63_4                      0x34fc
-#define AFE_CONN64                        0x3500
-#define AFE_CONN64_1                      0x3504
-#define AFE_CONN64_2                      0x3508
-#define AFE_CONN64_3                      0x350c
-#define AFE_CONN64_4                      0x3510
-#define AFE_CONN65                        0x3514
-#define AFE_CONN65_1                      0x3518
-#define AFE_CONN65_2                      0x351c
-#define AFE_CONN65_3                      0x3520
-#define AFE_CONN65_4                      0x3524
-#define AFE_CONN66                        0x3528
-#define AFE_CONN66_1                      0x352c
-#define AFE_CONN66_2                      0x3530
-#define AFE_CONN66_3                      0x3534
-#define AFE_CONN66_4                      0x3538
-#define AFE_CONN67                        0x353c
-#define AFE_CONN67_1                      0x3540
-#define AFE_CONN67_2                      0x3544
-#define AFE_CONN67_3                      0x3548
-#define AFE_CONN67_4                      0x354c
-#define AFE_CONN68                        0x3550
-#define AFE_CONN68_1                      0x3554
-#define AFE_CONN68_2                      0x3558
-#define AFE_CONN68_3                      0x355c
-#define AFE_CONN68_4                      0x3560
-#define AFE_CONN69                        0x3564
-#define AFE_CONN69_1                      0x3568
-#define AFE_CONN69_2                      0x356c
-#define AFE_CONN69_3                      0x3570
-#define AFE_CONN69_4                      0x3574
-#define AFE_CONN70                        0x3578
-#define AFE_CONN70_1                      0x357c
-#define AFE_CONN70_2                      0x3580
-#define AFE_CONN70_3                      0x3584
-#define AFE_CONN70_4                      0x3588
-#define AFE_CONN71                        0x358c
-#define AFE_CONN71_1                      0x3590
-#define AFE_CONN71_2                      0x3594
-#define AFE_CONN71_3                      0x3598
-#define AFE_CONN71_4                      0x359c
-#define AFE_CONN72                        0x35a0
-#define AFE_CONN72_1                      0x35a4
-#define AFE_CONN72_2                      0x35a8
-#define AFE_CONN72_3                      0x35ac
-#define AFE_CONN72_4                      0x35b0
-#define AFE_CONN73                        0x35b4
-#define AFE_CONN73_1                      0x35b8
-#define AFE_CONN73_2                      0x35bc
-#define AFE_CONN73_3                      0x35c0
-#define AFE_CONN73_4                      0x35c4
-#define AFE_CONN74                        0x35c8
-#define AFE_CONN74_1                      0x35cc
-#define AFE_CONN74_2                      0x35d0
-#define AFE_CONN74_3                      0x35d4
-#define AFE_CONN74_4                      0x35d8
-#define AFE_CONN75                        0x35dc
-#define AFE_CONN75_1                      0x35e0
-#define AFE_CONN75_2                      0x35e4
-#define AFE_CONN75_3                      0x35e8
-#define AFE_CONN75_4                      0x35ec
-#define AFE_CONN76                        0x35f0
-#define AFE_CONN76_1                      0x35f4
-#define AFE_CONN76_2                      0x35f8
-#define AFE_CONN76_3                      0x35fc
-#define AFE_CONN76_4                      0x3600
-#define AFE_CONN77                        0x3604
-#define AFE_CONN77_1                      0x3608
-#define AFE_CONN77_2                      0x360c
-#define AFE_CONN77_3                      0x3610
-#define AFE_CONN77_4                      0x3614
-#define AFE_CONN78                        0x3618
-#define AFE_CONN78_1                      0x361c
-#define AFE_CONN78_2                      0x3620
-#define AFE_CONN78_3                      0x3624
-#define AFE_CONN78_4                      0x3628
-#define AFE_CONN79                        0x362c
-#define AFE_CONN79_1                      0x3630
-#define AFE_CONN79_2                      0x3634
-#define AFE_CONN79_3                      0x3638
-#define AFE_CONN79_4                      0x363c
-#define AFE_CONN80                        0x3640
-#define AFE_CONN80_1                      0x3644
-#define AFE_CONN80_2                      0x3648
-#define AFE_CONN80_3                      0x364c
-#define AFE_CONN80_4                      0x3650
-#define AFE_CONN81                        0x3654
-#define AFE_CONN81_1                      0x3658
-#define AFE_CONN81_2                      0x365c
-#define AFE_CONN81_3                      0x3660
-#define AFE_CONN81_4                      0x3664
-#define AFE_CONN82                        0x3668
-#define AFE_CONN82_1                      0x366c
-#define AFE_CONN82_2                      0x3670
-#define AFE_CONN82_3                      0x3674
-#define AFE_CONN82_4                      0x3678
-#define AFE_CONN83                        0x367c
-#define AFE_CONN83_1                      0x3680
-#define AFE_CONN83_2                      0x3684
-#define AFE_CONN83_3                      0x3688
-#define AFE_CONN83_4                      0x368c
-#define AFE_CONN84                        0x3690
-#define AFE_CONN84_1                      0x3694
-#define AFE_CONN84_2                      0x3698
-#define AFE_CONN84_3                      0x369c
-#define AFE_CONN84_4                      0x36a0
-#define AFE_CONN85                        0x36a4
-#define AFE_CONN85_1                      0x36a8
-#define AFE_CONN85_2                      0x36ac
-#define AFE_CONN85_3                      0x36b0
-#define AFE_CONN85_4                      0x36b4
-#define AFE_CONN86                        0x36b8
-#define AFE_CONN86_1                      0x36bc
-#define AFE_CONN86_2                      0x36c0
-#define AFE_CONN86_3                      0x36c4
-#define AFE_CONN86_4                      0x36c8
-#define AFE_CONN87                        0x36cc
-#define AFE_CONN87_1                      0x36d0
-#define AFE_CONN87_2                      0x36d4
-#define AFE_CONN87_3                      0x36d8
-#define AFE_CONN87_4                      0x36dc
-#define AFE_CONN88                        0x36e0
-#define AFE_CONN88_1                      0x36e4
-#define AFE_CONN88_2                      0x36e8
-#define AFE_CONN88_3                      0x36ec
-#define AFE_CONN88_4                      0x36f0
-#define AFE_CONN89                        0x36f4
-#define AFE_CONN89_1                      0x36f8
-#define AFE_CONN89_2                      0x36fc
-#define AFE_CONN89_3                      0x3700
-#define AFE_CONN89_4                      0x3704
-#define AFE_CONN90                        0x3708
-#define AFE_CONN90_1                      0x370c
-#define AFE_CONN90_2                      0x3710
-#define AFE_CONN90_3                      0x3714
-#define AFE_CONN90_4                      0x3718
-#define AFE_CONN91                        0x371c
-#define AFE_CONN91_1                      0x3720
-#define AFE_CONN91_2                      0x3724
-#define AFE_CONN91_3                      0x3728
-#define AFE_CONN91_4                      0x372c
-#define AFE_CONN92                        0x3730
-#define AFE_CONN92_1                      0x3734
-#define AFE_CONN92_2                      0x3738
-#define AFE_CONN92_3                      0x373c
-#define AFE_CONN92_4                      0x3740
-#define AFE_CONN93                        0x3744
-#define AFE_CONN93_1                      0x3748
-#define AFE_CONN93_2                      0x374c
-#define AFE_CONN93_3                      0x3750
-#define AFE_CONN93_4                      0x3754
-#define AFE_CONN94                        0x3758
-#define AFE_CONN94_1                      0x375c
-#define AFE_CONN94_2                      0x3760
-#define AFE_CONN94_3                      0x3764
-#define AFE_CONN94_4                      0x3768
-#define AFE_CONN95                        0x376c
-#define AFE_CONN95_1                      0x3770
-#define AFE_CONN95_2                      0x3774
-#define AFE_CONN95_3                      0x3778
-#define AFE_CONN95_4                      0x377c
-#define AFE_CONN96                        0x3780
-#define AFE_CONN96_1                      0x3784
-#define AFE_CONN96_2                      0x3788
-#define AFE_CONN96_3                      0x378c
-#define AFE_CONN96_4                      0x3790
-#define AFE_CONN97                        0x3794
-#define AFE_CONN97_1                      0x3798
-#define AFE_CONN97_2                      0x379c
-#define AFE_CONN97_3                      0x37a0
-#define AFE_CONN97_4                      0x37a4
-#define AFE_CONN98                        0x37a8
-#define AFE_CONN98_1                      0x37ac
-#define AFE_CONN98_2                      0x37b0
-#define AFE_CONN98_3                      0x37b4
-#define AFE_CONN98_4                      0x37b8
-#define AFE_CONN99                        0x37bc
-#define AFE_CONN99_1                      0x37c0
-#define AFE_CONN99_2                      0x37c4
-#define AFE_CONN99_3                      0x37c8
-#define AFE_CONN99_4                      0x37cc
-#define AFE_CONN100                       0x37d0
-#define AFE_CONN100_1                     0x37d4
-#define AFE_CONN100_2                     0x37d8
-#define AFE_CONN100_3                     0x37dc
-#define AFE_CONN100_4                     0x37e0
-#define AFE_CONN101                       0x37e4
-#define AFE_CONN101_1                     0x37e8
-#define AFE_CONN101_2                     0x37ec
-#define AFE_CONN101_3                     0x37f0
-#define AFE_CONN101_4                     0x37f4
-#define AFE_CONN102                       0x37f8
-#define AFE_CONN102_1                     0x37fc
-#define AFE_CONN102_2                     0x3800
-#define AFE_CONN102_3                     0x3804
-#define AFE_CONN102_4                     0x3808
-#define AFE_CONN103                       0x380c
-#define AFE_CONN103_1                     0x3810
-#define AFE_CONN103_2                     0x3814
-#define AFE_CONN103_3                     0x3818
-#define AFE_CONN103_4                     0x381c
-#define AFE_CONN104                       0x3820
-#define AFE_CONN104_1                     0x3824
-#define AFE_CONN104_2                     0x3828
-#define AFE_CONN104_3                     0x382c
-#define AFE_CONN104_4                     0x3830
-#define AFE_CONN105                       0x3834
-#define AFE_CONN105_1                     0x3838
-#define AFE_CONN105_2                     0x383c
-#define AFE_CONN105_3                     0x3840
-#define AFE_CONN105_4                     0x3844
-#define AFE_CONN106                       0x3848
-#define AFE_CONN106_1                     0x384c
-#define AFE_CONN106_2                     0x3850
-#define AFE_CONN106_3                     0x3854
-#define AFE_CONN106_4                     0x3858
-#define AFE_CONN107                       0x385c
-#define AFE_CONN107_1                     0x3860
-#define AFE_CONN107_2                     0x3864
-#define AFE_CONN107_3                     0x3868
-#define AFE_CONN107_4                     0x386c
-#define AFE_CONN108                       0x3870
-#define AFE_CONN108_1                     0x3874
-#define AFE_CONN108_2                     0x3878
-#define AFE_CONN108_3                     0x387c
-#define AFE_CONN108_4                     0x3880
-#define AFE_CONN109                       0x3884
-#define AFE_CONN109_1                     0x3888
-#define AFE_CONN109_2                     0x388c
-#define AFE_CONN109_3                     0x3890
-#define AFE_CONN109_4                     0x3894
-#define AFE_CONN110                       0x3898
-#define AFE_CONN110_1                     0x389c
-#define AFE_CONN110_2                     0x38a0
-#define AFE_CONN110_3                     0x38a4
-#define AFE_CONN110_4                     0x38a8
-#define AFE_CONN111                       0x38ac
-#define AFE_CONN111_1                     0x38b0
-#define AFE_CONN111_2                     0x38b4
-#define AFE_CONN111_3                     0x38b8
-#define AFE_CONN111_4                     0x38bc
-#define AFE_CONN112                       0x38c0
-#define AFE_CONN112_1                     0x38c4
-#define AFE_CONN112_2                     0x38c8
-#define AFE_CONN112_3                     0x38cc
-#define AFE_CONN112_4                     0x38d0
-#define AFE_CONN113                       0x38d4
-#define AFE_CONN113_1                     0x38d8
-#define AFE_CONN113_2                     0x38dc
-#define AFE_CONN113_3                     0x38e0
-#define AFE_CONN113_4                     0x38e4
-#define AFE_CONN114                       0x38e8
-#define AFE_CONN114_1                     0x38ec
-#define AFE_CONN114_2                     0x38f0
-#define AFE_CONN114_3                     0x38f4
-#define AFE_CONN114_4                     0x38f8
-#define AFE_CONN115                       0x38fc
-#define AFE_CONN115_1                     0x3900
-#define AFE_CONN115_2                     0x3904
-#define AFE_CONN115_3                     0x3908
-#define AFE_CONN115_4                     0x390c
-#define AFE_CONN116                       0x3910
-#define AFE_CONN116_1                     0x3914
-#define AFE_CONN116_2                     0x3918
-#define AFE_CONN116_3                     0x391c
-#define AFE_CONN116_4                     0x3920
-#define AFE_CONN117                       0x3924
-#define AFE_CONN117_1                     0x3928
-#define AFE_CONN117_2                     0x392c
-#define AFE_CONN117_3                     0x3930
-#define AFE_CONN117_4                     0x3934
-#define AFE_CONN118                       0x3938
-#define AFE_CONN118_1                     0x393c
-#define AFE_CONN118_2                     0x3940
-#define AFE_CONN118_3                     0x3944
-#define AFE_CONN118_4                     0x3948
-#define AFE_CONN119                       0x394c
-#define AFE_CONN119_1                     0x3950
-#define AFE_CONN119_2                     0x3954
-#define AFE_CONN119_3                     0x3958
-#define AFE_CONN119_4                     0x395c
-#define AFE_CONN120                       0x3960
-#define AFE_CONN120_1                     0x3964
-#define AFE_CONN120_2                     0x3968
-#define AFE_CONN120_3                     0x396c
-#define AFE_CONN120_4                     0x3970
-#define AFE_CONN121                       0x3974
-#define AFE_CONN121_1                     0x3978
-#define AFE_CONN121_2                     0x397c
-#define AFE_CONN121_3                     0x3980
-#define AFE_CONN121_4                     0x3984
-#define AFE_CONN122                       0x3988
-#define AFE_CONN122_1                     0x398c
-#define AFE_CONN122_2                     0x3990
-#define AFE_CONN122_3                     0x3994
-#define AFE_CONN122_4                     0x3998
-#define AFE_CONN123                       0x399c
-#define AFE_CONN123_1                     0x39a0
-#define AFE_CONN123_2                     0x39a4
-#define AFE_CONN123_3                     0x39a8
-#define AFE_CONN123_4                     0x39ac
-#define AFE_CONN124                       0x39b0
-#define AFE_CONN124_1                     0x39b4
-#define AFE_CONN124_2                     0x39b8
-#define AFE_CONN124_3                     0x39bc
-#define AFE_CONN124_4                     0x39c0
-#define AFE_CONN125                       0x39c4
-#define AFE_CONN125_1                     0x39c8
-#define AFE_CONN125_2                     0x39cc
-#define AFE_CONN125_3                     0x39d0
-#define AFE_CONN125_4                     0x39d4
-#define AFE_CONN126                       0x39d8
-#define AFE_CONN126_1                     0x39dc
-#define AFE_CONN126_2                     0x39e0
-#define AFE_CONN126_3                     0x39e4
-#define AFE_CONN126_4                     0x39e8
-#define AFE_CONN127                       0x39ec
-#define AFE_CONN127_1                     0x39f0
-#define AFE_CONN127_2                     0x39f4
-#define AFE_CONN127_3                     0x39f8
-#define AFE_CONN127_4                     0x39fc
-#define AFE_CONN128                       0x3a00
-#define AFE_CONN128_1                     0x3a04
-#define AFE_CONN128_2                     0x3a08
-#define AFE_CONN128_3                     0x3a0c
-#define AFE_CONN128_4                     0x3a10
-#define AFE_CONN129                       0x3a14
-#define AFE_CONN129_1                     0x3a18
-#define AFE_CONN129_2                     0x3a1c
-#define AFE_CONN129_3                     0x3a20
-#define AFE_CONN129_4                     0x3a24
-#define AFE_CONN130                       0x3a28
-#define AFE_CONN130_1                     0x3a2c
-#define AFE_CONN130_2                     0x3a30
-#define AFE_CONN130_3                     0x3a34
-#define AFE_CONN130_4                     0x3a38
-#define AFE_CONN131                       0x3a3c
-#define AFE_CONN131_1                     0x3a40
-#define AFE_CONN131_2                     0x3a44
-#define AFE_CONN131_3                     0x3a48
-#define AFE_CONN131_4                     0x3a4c
-#define AFE_CONN132                       0x3a50
-#define AFE_CONN132_1                     0x3a54
-#define AFE_CONN132_2                     0x3a58
-#define AFE_CONN132_3                     0x3a5c
-#define AFE_CONN132_4                     0x3a60
-#define AFE_CONN133                       0x3a64
-#define AFE_CONN133_1                     0x3a68
-#define AFE_CONN133_2                     0x3a6c
-#define AFE_CONN133_3                     0x3a70
-#define AFE_CONN133_4                     0x3a74
-#define AFE_CONN134                       0x3a78
-#define AFE_CONN134_1                     0x3a7c
-#define AFE_CONN134_2                     0x3a80
-#define AFE_CONN134_3                     0x3a84
-#define AFE_CONN134_4                     0x3a88
-#define AFE_CONN135                       0x3a8c
-#define AFE_CONN135_1                     0x3a90
-#define AFE_CONN135_2                     0x3a94
-#define AFE_CONN135_3                     0x3a98
-#define AFE_CONN135_4                     0x3a9c
-#define AFE_CONN136                       0x3aa0
-#define AFE_CONN136_1                     0x3aa4
-#define AFE_CONN136_2                     0x3aa8
-#define AFE_CONN136_3                     0x3aac
-#define AFE_CONN136_4                     0x3ab0
-#define AFE_CONN137                       0x3ab4
-#define AFE_CONN137_1                     0x3ab8
-#define AFE_CONN137_2                     0x3abc
-#define AFE_CONN137_3                     0x3ac0
-#define AFE_CONN137_4                     0x3ac4
-#define AFE_CONN138                       0x3ac8
-#define AFE_CONN138_1                     0x3acc
-#define AFE_CONN138_2                     0x3ad0
-#define AFE_CONN138_3                     0x3ad4
-#define AFE_CONN138_4                     0x3ad8
-#define AFE_CONN139                       0x3adc
-#define AFE_CONN139_1                     0x3ae0
-#define AFE_CONN139_2                     0x3ae4
-#define AFE_CONN139_3                     0x3ae8
-#define AFE_CONN139_4                     0x3aec
-#define AFE_CONN_RS                       0x3af0
-#define AFE_CONN_RS_1                     0x3af4
-#define AFE_CONN_RS_2                     0x3af8
-#define AFE_CONN_RS_3                     0x3afc
-#define AFE_CONN_RS_4                     0x3b00
-#define AFE_CONN_16BIT                    0x3b04
-#define AFE_CONN_16BIT_1                  0x3b08
-#define AFE_CONN_16BIT_2                  0x3b0c
-#define AFE_CONN_16BIT_3                  0x3b10
-#define AFE_CONN_16BIT_4                  0x3b14
-#define AFE_CONN_24BIT                    0x3b18
-#define AFE_CONN_24BIT_1                  0x3b1c
-#define AFE_CONN_24BIT_2                  0x3b20
-#define AFE_CONN_24BIT_3                  0x3b24
-#define AFE_CONN_24BIT_4                  0x3b28
-#define AFE_CONN_DI                       0x3b2c
-#define AFE_CONN_DI_1                     0x3b30
-#define AFE_CONN_DI_2                     0x3b34
-#define AFE_CONN_DI_3                     0x3b38
-#define AFE_CONN_DI_4                     0x3b3c
-#define AFE_CONN176                       0x3ea0
-#define AFE_CONN176_1                     0x3ea4
-#define AFE_CONN176_2                     0x3ea8
-#define AFE_CONN176_3                     0x3eac
-#define AFE_CONN176_4                     0x3eb0
-#define AFE_CONN176_5                     0x3eb4
-#define AFE_CONN177                       0x3eb8
-#define AFE_CONN177_1                     0x3ebc
-#define AFE_CONN177_2                     0x3ec0
-#define AFE_CONN177_3                     0x3ec4
-#define AFE_CONN177_4                     0x3ec8
-#define AFE_CONN177_5                     0x3ecc
-#define AFE_CONN182                       0x3f30
-#define AFE_CONN182_1                     0x3f34
-#define AFE_CONN182_2                     0x3f38
-#define AFE_CONN182_3                     0x3f3c
-#define AFE_CONN182_4                     0x3f40
-#define AFE_CONN182_5                     0x3f44
-#define AFE_CONN183                       0x3f48
-#define AFE_CONN183_1                     0x3f4c
-#define AFE_CONN183_2                     0x3f50
-#define AFE_CONN183_3                     0x3f54
-#define AFE_CONN183_4                     0x3f58
-#define AFE_CONN183_5                     0x3f5c
-#define AFE_SECURE_MASK_CONN0             0x4000
-#define AFE_SECURE_MASK_CONN0_1           0x4004
-#define AFE_SECURE_MASK_CONN0_2           0x4008
-#define AFE_SECURE_MASK_CONN0_3           0x400c
-#define AFE_SECURE_MASK_CONN0_4           0x4010
-#define AFE_SECURE_MASK_CONN1             0x4014
-#define AFE_SECURE_MASK_CONN1_1           0x4018
-#define AFE_SECURE_MASK_CONN1_2           0x401c
-#define AFE_SECURE_MASK_CONN1_3           0x4020
-#define AFE_SECURE_MASK_CONN1_4           0x4024
-#define AFE_SECURE_MASK_CONN2             0x4028
-#define AFE_SECURE_MASK_CONN2_1           0x402c
-#define AFE_SECURE_MASK_CONN2_2           0x4030
-#define AFE_SECURE_MASK_CONN2_3           0x4034
-#define AFE_SECURE_MASK_CONN2_4           0x4038
-#define AFE_SECURE_MASK_CONN3             0x403c
-#define AFE_SECURE_MASK_CONN3_1           0x4040
-#define AFE_SECURE_MASK_CONN3_2           0x4044
-#define AFE_SECURE_MASK_CONN3_3           0x4048
-#define AFE_SECURE_MASK_CONN3_4           0x404c
-#define AFE_SECURE_MASK_CONN4             0x4050
-#define AFE_SECURE_MASK_CONN4_1           0x4054
-#define AFE_SECURE_MASK_CONN4_2           0x4058
-#define AFE_SECURE_MASK_CONN4_3           0x405c
-#define AFE_SECURE_MASK_CONN4_4           0x4060
-#define AFE_SECURE_MASK_CONN5             0x4064
-#define AFE_SECURE_MASK_CONN5_1           0x4068
-#define AFE_SECURE_MASK_CONN5_2           0x406c
-#define AFE_SECURE_MASK_CONN5_3           0x4070
-#define AFE_SECURE_MASK_CONN5_4           0x4074
-#define AFE_SECURE_MASK_CONN6             0x4078
-#define AFE_SECURE_MASK_CONN6_1           0x407c
-#define AFE_SECURE_MASK_CONN6_2           0x4080
-#define AFE_SECURE_MASK_CONN6_3           0x4084
-#define AFE_SECURE_MASK_CONN6_4           0x4088
-#define AFE_SECURE_MASK_CONN7             0x408c
-#define AFE_SECURE_MASK_CONN7_1           0x4090
-#define AFE_SECURE_MASK_CONN7_2           0x4094
-#define AFE_SECURE_MASK_CONN7_3           0x4098
-#define AFE_SECURE_MASK_CONN7_4           0x409c
-#define AFE_SECURE_MASK_CONN8             0x40a0
-#define AFE_SECURE_MASK_CONN8_1           0x40a4
-#define AFE_SECURE_MASK_CONN8_2           0x40a8
-#define AFE_SECURE_MASK_CONN8_3           0x40ac
-#define AFE_SECURE_MASK_CONN8_4           0x40b0
-#define AFE_SECURE_MASK_CONN9             0x40b4
-#define AFE_SECURE_MASK_CONN9_1           0x40b8
-#define AFE_SECURE_MASK_CONN9_2           0x40bc
-#define AFE_SECURE_MASK_CONN9_3           0x40c0
-#define AFE_SECURE_MASK_CONN9_4           0x40c4
-#define AFE_SECURE_MASK_CONN10            0x40c8
-#define AFE_SECURE_MASK_CONN10_1          0x40cc
-#define AFE_SECURE_MASK_CONN10_2          0x40d0
-#define AFE_SECURE_MASK_CONN10_3          0x40d4
-#define AFE_SECURE_MASK_CONN10_4          0x40d8
-#define AFE_SECURE_MASK_CONN11            0x40dc
-#define AFE_SECURE_MASK_CONN11_1          0x40e0
-#define AFE_SECURE_MASK_CONN11_2          0x40e4
-#define AFE_SECURE_MASK_CONN11_3          0x40e8
-#define AFE_SECURE_MASK_CONN11_4          0x40ec
-#define AFE_SECURE_MASK_CONN12            0x40f0
-#define AFE_SECURE_MASK_CONN12_1          0x40f4
-#define AFE_SECURE_MASK_CONN12_2          0x40f8
-#define AFE_SECURE_MASK_CONN12_3          0x40fc
-#define AFE_SECURE_MASK_CONN12_4          0x4100
-#define AFE_SECURE_MASK_CONN13            0x4104
-#define AFE_SECURE_MASK_CONN13_1          0x4108
-#define AFE_SECURE_MASK_CONN13_2          0x410c
-#define AFE_SECURE_MASK_CONN13_3          0x4110
-#define AFE_SECURE_MASK_CONN13_4          0x4114
-#define AFE_SECURE_MASK_CONN14            0x4118
-#define AFE_SECURE_MASK_CONN14_1          0x411c
-#define AFE_SECURE_MASK_CONN14_2          0x4120
-#define AFE_SECURE_MASK_CONN14_3          0x4124
-#define AFE_SECURE_MASK_CONN14_4          0x4128
-#define AFE_SECURE_MASK_CONN15            0x412c
-#define AFE_SECURE_MASK_CONN15_1          0x4130
-#define AFE_SECURE_MASK_CONN15_2          0x4134
-#define AFE_SECURE_MASK_CONN15_3          0x4138
-#define AFE_SECURE_MASK_CONN15_4          0x413c
-#define AFE_SECURE_MASK_CONN16            0x4140
-#define AFE_SECURE_MASK_CONN16_1          0x4144
-#define AFE_SECURE_MASK_CONN16_2          0x4148
-#define AFE_SECURE_MASK_CONN16_3          0x414c
-#define AFE_SECURE_MASK_CONN16_4          0x4150
-#define AFE_SECURE_MASK_CONN17            0x4154
-#define AFE_SECURE_MASK_CONN17_1          0x4158
-#define AFE_SECURE_MASK_CONN17_2          0x415c
-#define AFE_SECURE_MASK_CONN17_3          0x4160
-#define AFE_SECURE_MASK_CONN17_4          0x4164
-#define AFE_SECURE_MASK_CONN18            0x4168
-#define AFE_SECURE_MASK_CONN18_1          0x416c
-#define AFE_SECURE_MASK_CONN18_2          0x4170
-#define AFE_SECURE_MASK_CONN18_3          0x4174
-#define AFE_SECURE_MASK_CONN18_4          0x4178
-#define AFE_SECURE_MASK_CONN19            0x417c
-#define AFE_SECURE_MASK_CONN19_1          0x4180
-#define AFE_SECURE_MASK_CONN19_2          0x4184
-#define AFE_SECURE_MASK_CONN19_3          0x4188
-#define AFE_SECURE_MASK_CONN19_4          0x418c
-#define AFE_SECURE_MASK_CONN20            0x4190
-#define AFE_SECURE_MASK_CONN20_1          0x4194
-#define AFE_SECURE_MASK_CONN20_2          0x4198
-#define AFE_SECURE_MASK_CONN20_3          0x419c
-#define AFE_SECURE_MASK_CONN20_4          0x41a0
-#define AFE_SECURE_MASK_CONN21            0x41a4
-#define AFE_SECURE_MASK_CONN21_1          0x41a8
-#define AFE_SECURE_MASK_CONN21_2          0x41ac
-#define AFE_SECURE_MASK_CONN21_3          0x41b0
-#define AFE_SECURE_MASK_CONN21_4          0x41b4
-#define AFE_SECURE_MASK_CONN22            0x41b8
-#define AFE_SECURE_MASK_CONN22_1          0x41bc
-#define AFE_SECURE_MASK_CONN22_2          0x41c0
-#define AFE_SECURE_MASK_CONN22_3          0x41c4
-#define AFE_SECURE_MASK_CONN22_4          0x41c8
-#define AFE_SECURE_MASK_CONN23            0x41cc
-#define AFE_SECURE_MASK_CONN23_1          0x41d0
-#define AFE_SECURE_MASK_CONN23_2          0x41d4
-#define AFE_SECURE_MASK_CONN23_3          0x41d8
-#define AFE_SECURE_MASK_CONN23_4          0x41dc
-#define AFE_SECURE_MASK_CONN24            0x41e0
-#define AFE_SECURE_MASK_CONN24_1          0x41e4
-#define AFE_SECURE_MASK_CONN24_2          0x41e8
-#define AFE_SECURE_MASK_CONN24_3          0x41ec
-#define AFE_SECURE_MASK_CONN24_4          0x41f0
-#define AFE_SECURE_MASK_CONN25            0x41f4
-#define AFE_SECURE_MASK_CONN25_1          0x41f8
-#define AFE_SECURE_MASK_CONN25_2          0x41fc
-#define AFE_SECURE_MASK_CONN25_3          0x4200
-#define AFE_SECURE_MASK_CONN25_4          0x4204
-#define AFE_SECURE_MASK_CONN26            0x4208
-#define AFE_SECURE_MASK_CONN26_1          0x420c
-#define AFE_SECURE_MASK_CONN26_2          0x4210
-#define AFE_SECURE_MASK_CONN26_3          0x4214
-#define AFE_SECURE_MASK_CONN26_4          0x4218
-#define AFE_SECURE_MASK_CONN27            0x421c
-#define AFE_SECURE_MASK_CONN27_1          0x4220
-#define AFE_SECURE_MASK_CONN27_2          0x4224
-#define AFE_SECURE_MASK_CONN27_3          0x4228
-#define AFE_SECURE_MASK_CONN27_4          0x422c
-#define AFE_SECURE_MASK_CONN28            0x4230
-#define AFE_SECURE_MASK_CONN28_1          0x4234
-#define AFE_SECURE_MASK_CONN28_2          0x4238
-#define AFE_SECURE_MASK_CONN28_3          0x423c
-#define AFE_SECURE_MASK_CONN28_4          0x4240
-#define AFE_SECURE_MASK_CONN29            0x4244
-#define AFE_SECURE_MASK_CONN29_1          0x4248
-#define AFE_SECURE_MASK_CONN29_2          0x424c
-#define AFE_SECURE_MASK_CONN29_3          0x4250
-#define AFE_SECURE_MASK_CONN29_4          0x4254
-#define AFE_SECURE_MASK_CONN30            0x4258
-#define AFE_SECURE_MASK_CONN30_1          0x425c
-#define AFE_SECURE_MASK_CONN30_2          0x4260
-#define AFE_SECURE_MASK_CONN30_3          0x4264
-#define AFE_SECURE_MASK_CONN30_4          0x4268
-#define AFE_SECURE_MASK_CONN31            0x426c
-#define AFE_SECURE_MASK_CONN31_1          0x4270
-#define AFE_SECURE_MASK_CONN31_2          0x4274
-#define AFE_SECURE_MASK_CONN31_3          0x4278
-#define AFE_SECURE_MASK_CONN31_4          0x427c
-#define AFE_SECURE_MASK_CONN32            0x4280
-#define AFE_SECURE_MASK_CONN32_1          0x4284
-#define AFE_SECURE_MASK_CONN32_2          0x4288
-#define AFE_SECURE_MASK_CONN32_3          0x428c
-#define AFE_SECURE_MASK_CONN32_4          0x4290
-#define AFE_SECURE_MASK_CONN33            0x4294
-#define AFE_SECURE_MASK_CONN33_1          0x4298
-#define AFE_SECURE_MASK_CONN33_2          0x429c
-#define AFE_SECURE_MASK_CONN33_3          0x42a0
-#define AFE_SECURE_MASK_CONN33_4          0x42a4
-#define AFE_SECURE_MASK_CONN34            0x42a8
-#define AFE_SECURE_MASK_CONN34_1          0x42ac
-#define AFE_SECURE_MASK_CONN34_2          0x42b0
-#define AFE_SECURE_MASK_CONN34_3          0x42b4
-#define AFE_SECURE_MASK_CONN34_4          0x42b8
-#define AFE_SECURE_MASK_CONN35            0x42bc
-#define AFE_SECURE_MASK_CONN35_1          0x42c0
-#define AFE_SECURE_MASK_CONN35_2          0x42c4
-#define AFE_SECURE_MASK_CONN35_3          0x42c8
-#define AFE_SECURE_MASK_CONN35_4          0x42cc
-#define AFE_SECURE_MASK_CONN36            0x42d0
-#define AFE_SECURE_MASK_CONN36_1          0x42d4
-#define AFE_SECURE_MASK_CONN36_2          0x42d8
-#define AFE_SECURE_MASK_CONN36_3          0x42dc
-#define AFE_SECURE_MASK_CONN36_4          0x42e0
-#define AFE_SECURE_MASK_CONN37            0x42e4
-#define AFE_SECURE_MASK_CONN37_1          0x42e8
-#define AFE_SECURE_MASK_CONN37_2          0x42ec
-#define AFE_SECURE_MASK_CONN37_3          0x42f0
-#define AFE_SECURE_MASK_CONN37_4          0x42f4
-#define AFE_SECURE_MASK_CONN38            0x42f8
-#define AFE_SECURE_MASK_CONN38_1          0x42fc
-#define AFE_SECURE_MASK_CONN38_2          0x4300
-#define AFE_SECURE_MASK_CONN38_3          0x4304
-#define AFE_SECURE_MASK_CONN38_4          0x4308
-#define AFE_SECURE_MASK_CONN39            0x430c
-#define AFE_SECURE_MASK_CONN39_1          0x4310
-#define AFE_SECURE_MASK_CONN39_2          0x4314
-#define AFE_SECURE_MASK_CONN39_3          0x4318
-#define AFE_SECURE_MASK_CONN39_4          0x431c
-#define AFE_SECURE_MASK_CONN40            0x4320
-#define AFE_SECURE_MASK_CONN40_1          0x4324
-#define AFE_SECURE_MASK_CONN40_2          0x4328
-#define AFE_SECURE_MASK_CONN40_3          0x432c
-#define AFE_SECURE_MASK_CONN40_4          0x4330
-#define AFE_SECURE_MASK_CONN41            0x4334
-#define AFE_SECURE_MASK_CONN41_1          0x4338
-#define AFE_SECURE_MASK_CONN41_2          0x433c
-#define AFE_SECURE_MASK_CONN41_3          0x4340
-#define AFE_SECURE_MASK_CONN41_4          0x4344
-#define AFE_SECURE_MASK_CONN42            0x4348
-#define AFE_SECURE_MASK_CONN42_1          0x434c
-#define AFE_SECURE_MASK_CONN42_2          0x4350
-#define AFE_SECURE_MASK_CONN42_3          0x4354
-#define AFE_SECURE_MASK_CONN42_4          0x4358
-#define AFE_SECURE_MASK_CONN43            0x435c
-#define AFE_SECURE_MASK_CONN43_1          0x4360
-#define AFE_SECURE_MASK_CONN43_2          0x4364
-#define AFE_SECURE_MASK_CONN43_3          0x4368
-#define AFE_SECURE_MASK_CONN43_4          0x436c
-#define AFE_SECURE_MASK_CONN44            0x4370
-#define AFE_SECURE_MASK_CONN44_1          0x4374
-#define AFE_SECURE_MASK_CONN44_2          0x4378
-#define AFE_SECURE_MASK_CONN44_3          0x437c
-#define AFE_SECURE_MASK_CONN44_4          0x4380
-#define AFE_SECURE_MASK_CONN45            0x4384
-#define AFE_SECURE_MASK_CONN45_1          0x4388
-#define AFE_SECURE_MASK_CONN45_2          0x438c
-#define AFE_SECURE_MASK_CONN45_3          0x4390
-#define AFE_SECURE_MASK_CONN45_4          0x4394
-#define AFE_SECURE_MASK_CONN46            0x4398
-#define AFE_SECURE_MASK_CONN46_1          0x439c
-#define AFE_SECURE_MASK_CONN46_2          0x43a0
-#define AFE_SECURE_MASK_CONN46_3          0x43a4
-#define AFE_SECURE_MASK_CONN46_4          0x43a8
-#define AFE_SECURE_MASK_CONN47            0x43ac
-#define AFE_SECURE_MASK_CONN47_1          0x43b0
-#define AFE_SECURE_MASK_CONN47_2          0x43b4
-#define AFE_SECURE_MASK_CONN47_3          0x43b8
-#define AFE_SECURE_MASK_CONN47_4          0x43bc
-#define AFE_SECURE_MASK_CONN48            0x43c0
-#define AFE_SECURE_MASK_CONN48_1          0x43c4
-#define AFE_SECURE_MASK_CONN48_2          0x43c8
-#define AFE_SECURE_MASK_CONN48_3          0x43cc
-#define AFE_SECURE_MASK_CONN48_4          0x43d0
-#define AFE_SECURE_MASK_CONN49            0x43d4
-#define AFE_SECURE_MASK_CONN49_1          0x43d8
-#define AFE_SECURE_MASK_CONN49_2          0x43dc
-#define AFE_SECURE_MASK_CONN49_3          0x43e0
-#define AFE_SECURE_MASK_CONN49_4          0x43e4
-#define AFE_SECURE_MASK_CONN50            0x43e8
-#define AFE_SECURE_MASK_CONN50_1          0x43ec
-#define AFE_SECURE_MASK_CONN50_2          0x43f0
-#define AFE_SECURE_MASK_CONN50_3          0x43f4
-#define AFE_SECURE_MASK_CONN50_4          0x43f8
-#define AFE_SECURE_MASK_CONN51            0x43fc
-#define AFE_SECURE_MASK_CONN51_1          0x4400
-#define AFE_SECURE_MASK_CONN51_2          0x4404
-#define AFE_SECURE_MASK_CONN51_3          0x4408
-#define AFE_SECURE_MASK_CONN51_4          0x440c
-#define AFE_SECURE_MASK_CONN52            0x4410
-#define AFE_SECURE_MASK_CONN52_1          0x4414
-#define AFE_SECURE_MASK_CONN52_2          0x4418
-#define AFE_SECURE_MASK_CONN52_3          0x441c
-#define AFE_SECURE_MASK_CONN52_4          0x4420
-#define AFE_SECURE_MASK_CONN53            0x4424
-#define AFE_SECURE_MASK_CONN53_1          0x4428
-#define AFE_SECURE_MASK_CONN53_2          0x442c
-#define AFE_SECURE_MASK_CONN53_3          0x4430
-#define AFE_SECURE_MASK_CONN53_4          0x4434
-#define AFE_SECURE_MASK_CONN54            0x4438
-#define AFE_SECURE_MASK_CONN54_1          0x443c
-#define AFE_SECURE_MASK_CONN54_2          0x4440
-#define AFE_SECURE_MASK_CONN54_3          0x4444
-#define AFE_SECURE_MASK_CONN54_4          0x4448
-#define AFE_SECURE_MASK_CONN55            0x444c
-#define AFE_SECURE_MASK_CONN55_1          0x4450
-#define AFE_SECURE_MASK_CONN55_2          0x4454
-#define AFE_SECURE_MASK_CONN55_3          0x4458
-#define AFE_SECURE_MASK_CONN55_4          0x445c
-#define AFE_SECURE_MASK_CONN56            0x4460
-#define AFE_SECURE_MASK_CONN56_1          0x4464
-#define AFE_SECURE_MASK_CONN56_2          0x4468
-#define AFE_SECURE_MASK_CONN56_3          0x446c
-#define AFE_SECURE_MASK_CONN56_4          0x4470
-#define AFE_SECURE_MASK_CONN57            0x4474
-#define AFE_SECURE_MASK_CONN57_1          0x4478
-#define AFE_SECURE_MASK_CONN57_2          0x447c
-#define AFE_SECURE_MASK_CONN57_3          0x4480
-#define AFE_SECURE_MASK_CONN57_4          0x4484
-#define AFE_SECURE_MASK_CONN58            0x4488
-#define AFE_SECURE_MASK_CONN58_1          0x448c
-#define AFE_SECURE_MASK_CONN58_2          0x4490
-#define AFE_SECURE_MASK_CONN58_3          0x4494
-#define AFE_SECURE_MASK_CONN58_4          0x4498
-#define AFE_SECURE_MASK_CONN59            0x449c
-#define AFE_SECURE_MASK_CONN59_1          0x44a0
-#define AFE_SECURE_MASK_CONN59_2          0x44a4
-#define AFE_SECURE_MASK_CONN59_3          0x44a8
-#define AFE_SECURE_MASK_CONN59_4          0x44ac
-#define AFE_SECURE_MASK_CONN60            0x44b0
-#define AFE_SECURE_MASK_CONN60_1          0x44b4
-#define AFE_SECURE_MASK_CONN60_2          0x44b8
-#define AFE_SECURE_MASK_CONN60_3          0x44bc
-#define AFE_SECURE_MASK_CONN60_4          0x44c0
-#define AFE_SECURE_MASK_CONN61            0x44c4
-#define AFE_SECURE_MASK_CONN61_1          0x44c8
-#define AFE_SECURE_MASK_CONN61_2          0x44cc
-#define AFE_SECURE_MASK_CONN61_3          0x44d0
-#define AFE_SECURE_MASK_CONN61_4          0x44d4
-#define AFE_SECURE_MASK_CONN62            0x44d8
-#define AFE_SECURE_MASK_CONN62_1          0x44dc
-#define AFE_SECURE_MASK_CONN62_2          0x44e0
-#define AFE_SECURE_MASK_CONN62_3          0x44e4
-#define AFE_SECURE_MASK_CONN62_4          0x44e8
-#define AFE_SECURE_MASK_CONN63            0x44ec
-#define AFE_SECURE_MASK_CONN63_1          0x44f0
-#define AFE_SECURE_MASK_CONN63_2          0x44f4
-#define AFE_SECURE_MASK_CONN63_3          0x44f8
-#define AFE_SECURE_MASK_CONN63_4          0x44fc
-#define AFE_SECURE_MASK_CONN64            0x4500
-#define AFE_SECURE_MASK_CONN64_1          0x4504
-#define AFE_SECURE_MASK_CONN64_2          0x4508
-#define AFE_SECURE_MASK_CONN64_3          0x450c
-#define AFE_SECURE_MASK_CONN64_4          0x4510
-#define AFE_SECURE_MASK_CONN65            0x4514
-#define AFE_SECURE_MASK_CONN65_1          0x4518
-#define AFE_SECURE_MASK_CONN65_2          0x451c
-#define AFE_SECURE_MASK_CONN65_3          0x4520
-#define AFE_SECURE_MASK_CONN65_4          0x4524
-#define AFE_SECURE_MASK_CONN66            0x4528
-#define AFE_SECURE_MASK_CONN66_1          0x452c
-#define AFE_SECURE_MASK_CONN66_2          0x4530
-#define AFE_SECURE_MASK_CONN66_3          0x4534
-#define AFE_SECURE_MASK_CONN66_4          0x4538
-#define AFE_SECURE_MASK_CONN67            0x453c
-#define AFE_SECURE_MASK_CONN67_1          0x4540
-#define AFE_SECURE_MASK_CONN67_2          0x4544
-#define AFE_SECURE_MASK_CONN67_3          0x4548
-#define AFE_SECURE_MASK_CONN67_4          0x454c
-#define AFE_SECURE_MASK_CONN68            0x4550
-#define AFE_SECURE_MASK_CONN68_1          0x4554
-#define AFE_SECURE_MASK_CONN68_2          0x4558
-#define AFE_SECURE_MASK_CONN68_3          0x455c
-#define AFE_SECURE_MASK_CONN68_4          0x4560
-#define AFE_SECURE_MASK_CONN69            0x4564
-#define AFE_SECURE_MASK_CONN69_1          0x4568
-#define AFE_SECURE_MASK_CONN69_2          0x456c
-#define AFE_SECURE_MASK_CONN69_3          0x4570
-#define AFE_SECURE_MASK_CONN69_4          0x4574
-#define AFE_SECURE_MASK_CONN70            0x4578
-#define AFE_SECURE_MASK_CONN70_1          0x457c
-#define AFE_SECURE_MASK_CONN70_2          0x4580
-#define AFE_SECURE_MASK_CONN70_3          0x4584
-#define AFE_SECURE_MASK_CONN70_4          0x4588
-#define AFE_SECURE_MASK_CONN71            0x458c
-#define AFE_SECURE_MASK_CONN71_1          0x4590
-#define AFE_SECURE_MASK_CONN71_2          0x4594
-#define AFE_SECURE_MASK_CONN71_3          0x4598
-#define AFE_SECURE_MASK_CONN71_4          0x459c
-#define AFE_SECURE_MASK_CONN72            0x45a0
-#define AFE_SECURE_MASK_CONN72_1          0x45a4
-#define AFE_SECURE_MASK_CONN72_2          0x45a8
-#define AFE_SECURE_MASK_CONN72_3          0x45ac
-#define AFE_SECURE_MASK_CONN72_4          0x45b0
-#define AFE_SECURE_MASK_CONN73            0x45b4
-#define AFE_SECURE_MASK_CONN73_1          0x45b8
-#define AFE_SECURE_MASK_CONN73_2          0x45bc
-#define AFE_SECURE_MASK_CONN73_3          0x45c0
-#define AFE_SECURE_MASK_CONN73_4          0x45c4
-#define AFE_SECURE_MASK_CONN74            0x45c8
-#define AFE_SECURE_MASK_CONN74_1          0x45cc
-#define AFE_SECURE_MASK_CONN74_2          0x45d0
-#define AFE_SECURE_MASK_CONN74_3          0x45d4
-#define AFE_SECURE_MASK_CONN74_4          0x45d8
-#define AFE_SECURE_MASK_CONN75            0x45dc
-#define AFE_SECURE_MASK_CONN75_1          0x45e0
-#define AFE_SECURE_MASK_CONN75_2          0x45e4
-#define AFE_SECURE_MASK_CONN75_3          0x45e8
-#define AFE_SECURE_MASK_CONN75_4          0x45ec
-#define AFE_SECURE_MASK_CONN76            0x45f0
-#define AFE_SECURE_MASK_CONN76_1          0x45f4
-#define AFE_SECURE_MASK_CONN76_2          0x45f8
-#define AFE_SECURE_MASK_CONN76_3          0x45fc
-#define AFE_SECURE_MASK_CONN76_4          0x4600
-#define AFE_SECURE_MASK_CONN77            0x4604
-#define AFE_SECURE_MASK_CONN77_1          0x4608
-#define AFE_SECURE_MASK_CONN77_2          0x460c
-#define AFE_SECURE_MASK_CONN77_3          0x4610
-#define AFE_SECURE_MASK_CONN77_4          0x4614
-#define AFE_SECURE_MASK_CONN78            0x4618
-#define AFE_SECURE_MASK_CONN78_1          0x461c
-#define AFE_SECURE_MASK_CONN78_2          0x4620
-#define AFE_SECURE_MASK_CONN78_3          0x4624
-#define AFE_SECURE_MASK_CONN78_4          0x4628
-#define AFE_SECURE_MASK_CONN79            0x462c
-#define AFE_SECURE_MASK_CONN79_1          0x4630
-#define AFE_SECURE_MASK_CONN79_2          0x4634
-#define AFE_SECURE_MASK_CONN79_3          0x4638
-#define AFE_SECURE_MASK_CONN79_4          0x463c
-#define AFE_SECURE_MASK_CONN80            0x4640
-#define AFE_SECURE_MASK_CONN80_1          0x4644
-#define AFE_SECURE_MASK_CONN80_2          0x4648
-#define AFE_SECURE_MASK_CONN80_3          0x464c
-#define AFE_SECURE_MASK_CONN80_4          0x4650
-#define AFE_SECURE_MASK_CONN81            0x4654
-#define AFE_SECURE_MASK_CONN81_1          0x4658
-#define AFE_SECURE_MASK_CONN81_2          0x465c
-#define AFE_SECURE_MASK_CONN81_3          0x4660
-#define AFE_SECURE_MASK_CONN81_4          0x4664
-#define AFE_SECURE_MASK_CONN82            0x4668
-#define AFE_SECURE_MASK_CONN82_1          0x466c
-#define AFE_SECURE_MASK_CONN82_2          0x4670
-#define AFE_SECURE_MASK_CONN82_3          0x4674
-#define AFE_SECURE_MASK_CONN82_4          0x4678
-#define AFE_SECURE_MASK_CONN83            0x467c
-#define AFE_SECURE_MASK_CONN83_1          0x4680
-#define AFE_SECURE_MASK_CONN83_2          0x4684
-#define AFE_SECURE_MASK_CONN83_3          0x4688
-#define AFE_SECURE_MASK_CONN83_4          0x468c
-#define AFE_SECURE_MASK_CONN84            0x4690
-#define AFE_SECURE_MASK_CONN84_1          0x4694
-#define AFE_SECURE_MASK_CONN84_2          0x4698
-#define AFE_SECURE_MASK_CONN84_3          0x469c
-#define AFE_SECURE_MASK_CONN84_4          0x46a0
-#define AFE_SECURE_MASK_CONN85            0x46a4
-#define AFE_SECURE_MASK_CONN85_1          0x46a8
-#define AFE_SECURE_MASK_CONN85_2          0x46ac
-#define AFE_SECURE_MASK_CONN85_3          0x46b0
-#define AFE_SECURE_MASK_CONN85_4          0x46b4
-#define AFE_SECURE_MASK_CONN86            0x46b8
-#define AFE_SECURE_MASK_CONN86_1          0x46bc
-#define AFE_SECURE_MASK_CONN86_2          0x46c0
-#define AFE_SECURE_MASK_CONN86_3          0x46c4
-#define AFE_SECURE_MASK_CONN86_4          0x46c8
-#define AFE_SECURE_MASK_CONN87            0x46cc
-#define AFE_SECURE_MASK_CONN87_1          0x46d0
-#define AFE_SECURE_MASK_CONN87_2          0x46d4
-#define AFE_SECURE_MASK_CONN87_3          0x46d8
-#define AFE_SECURE_MASK_CONN87_4          0x46dc
-#define AFE_SECURE_MASK_CONN88            0x46e0
-#define AFE_SECURE_MASK_CONN88_1          0x46e4
-#define AFE_SECURE_MASK_CONN88_2          0x46e8
-#define AFE_SECURE_MASK_CONN88_3          0x46ec
-#define AFE_SECURE_MASK_CONN88_4          0x46f0
-#define AFE_SECURE_MASK_CONN89            0x46f4
-#define AFE_SECURE_MASK_CONN89_1          0x46f8
-#define AFE_SECURE_MASK_CONN89_2          0x46fc
-#define AFE_SECURE_MASK_CONN89_3          0x4700
-#define AFE_SECURE_MASK_CONN89_4          0x4704
-#define AFE_SECURE_MASK_CONN90            0x4708
-#define AFE_SECURE_MASK_CONN90_1          0x470c
-#define AFE_SECURE_MASK_CONN90_2          0x4710
-#define AFE_SECURE_MASK_CONN90_3          0x4714
-#define AFE_SECURE_MASK_CONN90_4          0x4718
-#define AFE_SECURE_MASK_CONN91            0x471c
-#define AFE_SECURE_MASK_CONN91_1          0x4720
-#define AFE_SECURE_MASK_CONN91_2          0x4724
-#define AFE_SECURE_MASK_CONN91_3          0x4728
-#define AFE_SECURE_MASK_CONN91_4          0x472c
-#define AFE_SECURE_MASK_CONN92            0x4730
-#define AFE_SECURE_MASK_CONN92_1          0x4734
-#define AFE_SECURE_MASK_CONN92_2          0x4738
-#define AFE_SECURE_MASK_CONN92_3          0x473c
-#define AFE_SECURE_MASK_CONN92_4          0x4740
-#define AFE_SECURE_MASK_CONN93            0x4744
-#define AFE_SECURE_MASK_CONN93_1          0x4748
-#define AFE_SECURE_MASK_CONN93_2          0x474c
-#define AFE_SECURE_MASK_CONN93_3          0x4750
-#define AFE_SECURE_MASK_CONN93_4          0x4754
-#define AFE_SECURE_MASK_CONN94            0x4758
-#define AFE_SECURE_MASK_CONN94_1          0x475c
-#define AFE_SECURE_MASK_CONN94_2          0x4760
-#define AFE_SECURE_MASK_CONN94_3          0x4764
-#define AFE_SECURE_MASK_CONN94_4          0x4768
-#define AFE_SECURE_MASK_CONN95            0x476c
-#define AFE_SECURE_MASK_CONN95_1          0x4770
-#define AFE_SECURE_MASK_CONN95_2          0x4774
-#define AFE_SECURE_MASK_CONN95_3          0x4778
-#define AFE_SECURE_MASK_CONN95_4          0x477c
-#define AFE_SECURE_MASK_CONN96            0x4780
-#define AFE_SECURE_MASK_CONN96_1          0x4784
-#define AFE_SECURE_MASK_CONN96_2          0x4788
-#define AFE_SECURE_MASK_CONN96_3          0x478c
-#define AFE_SECURE_MASK_CONN96_4          0x4790
-#define AFE_SECURE_MASK_CONN97            0x4794
-#define AFE_SECURE_MASK_CONN97_1          0x4798
-#define AFE_SECURE_MASK_CONN97_2          0x479c
-#define AFE_SECURE_MASK_CONN97_3          0x47a0
-#define AFE_SECURE_MASK_CONN97_4          0x47a4
-#define AFE_SECURE_MASK_CONN98            0x47a8
-#define AFE_SECURE_MASK_CONN98_1          0x47ac
-#define AFE_SECURE_MASK_CONN98_2          0x47b0
-#define AFE_SECURE_MASK_CONN98_3          0x47b4
-#define AFE_SECURE_MASK_CONN98_4          0x47b8
-#define AFE_SECURE_MASK_CONN99            0x47bc
-#define AFE_SECURE_MASK_CONN99_1          0x47c0
-#define AFE_SECURE_MASK_CONN99_2          0x47c4
-#define AFE_SECURE_MASK_CONN99_3          0x47c8
-#define AFE_SECURE_MASK_CONN99_4          0x47cc
-#define AFE_SECURE_MASK_CONN100           0x47d0
-#define AFE_SECURE_MASK_CONN100_1         0x47d4
-#define AFE_SECURE_MASK_CONN100_2         0x47d8
-#define AFE_SECURE_MASK_CONN100_3         0x47dc
-#define AFE_SECURE_MASK_CONN100_4         0x47e0
-#define AFE_SECURE_MASK_CONN101           0x47e4
-#define AFE_SECURE_MASK_CONN101_1         0x47e8
-#define AFE_SECURE_MASK_CONN101_2         0x47ec
-#define AFE_SECURE_MASK_CONN101_3         0x47f0
-#define AFE_SECURE_MASK_CONN101_4         0x47f4
-#define AFE_SECURE_MASK_CONN102           0x47f8
-#define AFE_SECURE_MASK_CONN102_1         0x47fc
-#define AFE_SECURE_MASK_CONN102_2         0x4800
-#define AFE_SECURE_MASK_CONN102_3         0x4804
-#define AFE_SECURE_MASK_CONN102_4         0x4808
-#define AFE_SECURE_MASK_CONN103           0x480c
-#define AFE_SECURE_MASK_CONN103_1         0x4810
-#define AFE_SECURE_MASK_CONN103_2         0x4814
-#define AFE_SECURE_MASK_CONN103_3         0x4818
-#define AFE_SECURE_MASK_CONN103_4         0x481c
-#define AFE_SECURE_MASK_CONN104           0x4820
-#define AFE_SECURE_MASK_CONN104_1         0x4824
-#define AFE_SECURE_MASK_CONN104_2         0x4828
-#define AFE_SECURE_MASK_CONN104_3         0x482c
-#define AFE_SECURE_MASK_CONN104_4         0x4830
-#define AFE_SECURE_MASK_CONN105           0x4834
-#define AFE_SECURE_MASK_CONN105_1         0x4838
-#define AFE_SECURE_MASK_CONN105_2         0x483c
-#define AFE_SECURE_MASK_CONN105_3         0x4840
-#define AFE_SECURE_MASK_CONN105_4         0x4844
-#define AFE_SECURE_MASK_CONN106           0x4848
-#define AFE_SECURE_MASK_CONN106_1         0x484c
-#define AFE_SECURE_MASK_CONN106_2         0x4850
-#define AFE_SECURE_MASK_CONN106_3         0x4854
-#define AFE_SECURE_MASK_CONN106_4         0x4858
-#define AFE_SECURE_MASK_CONN107           0x485c
-#define AFE_SECURE_MASK_CONN107_1         0x4860
-#define AFE_SECURE_MASK_CONN107_2         0x4864
-#define AFE_SECURE_MASK_CONN107_3         0x4868
-#define AFE_SECURE_MASK_CONN107_4         0x486c
-#define AFE_SECURE_MASK_CONN108           0x4870
-#define AFE_SECURE_MASK_CONN108_1         0x4874
-#define AFE_SECURE_MASK_CONN108_2         0x4878
-#define AFE_SECURE_MASK_CONN108_3         0x487c
-#define AFE_SECURE_MASK_CONN108_4         0x4880
-#define AFE_SECURE_MASK_CONN109           0x4884
-#define AFE_SECURE_MASK_CONN109_1         0x4888
-#define AFE_SECURE_MASK_CONN109_2         0x488c
-#define AFE_SECURE_MASK_CONN109_3         0x4890
-#define AFE_SECURE_MASK_CONN109_4         0x4894
-#define AFE_SECURE_MASK_CONN110           0x4898
-#define AFE_SECURE_MASK_CONN110_1         0x489c
-#define AFE_SECURE_MASK_CONN110_2         0x48a0
-#define AFE_SECURE_MASK_CONN110_3         0x48a4
-#define AFE_SECURE_MASK_CONN110_4         0x48a8
-#define AFE_SECURE_MASK_CONN111           0x48ac
-#define AFE_SECURE_MASK_CONN111_1         0x48b0
-#define AFE_SECURE_MASK_CONN111_2         0x48b4
-#define AFE_SECURE_MASK_CONN111_3         0x48b8
-#define AFE_SECURE_MASK_CONN111_4         0x48bc
-#define AFE_SECURE_MASK_CONN112           0x48c0
-#define AFE_SECURE_MASK_CONN112_1         0x48c4
-#define AFE_SECURE_MASK_CONN112_2         0x48c8
-#define AFE_SECURE_MASK_CONN112_3         0x48cc
-#define AFE_SECURE_MASK_CONN112_4         0x48d0
-#define AFE_SECURE_MASK_CONN113           0x48d4
-#define AFE_SECURE_MASK_CONN113_1         0x48d8
-#define AFE_SECURE_MASK_CONN113_2         0x48dc
-#define AFE_SECURE_MASK_CONN113_3         0x48e0
-#define AFE_SECURE_MASK_CONN113_4         0x48e4
-#define AFE_SECURE_MASK_CONN114           0x48e8
-#define AFE_SECURE_MASK_CONN114_1         0x48ec
-#define AFE_SECURE_MASK_CONN114_2         0x48f0
-#define AFE_SECURE_MASK_CONN114_3         0x48f4
-#define AFE_SECURE_MASK_CONN114_4         0x48f8
-#define AFE_SECURE_MASK_CONN115           0x48fc
-#define AFE_SECURE_MASK_CONN115_1         0x4900
-#define AFE_SECURE_MASK_CONN115_2         0x4904
-#define AFE_SECURE_MASK_CONN115_3         0x4908
-#define AFE_SECURE_MASK_CONN115_4         0x490c
-#define AFE_SECURE_MASK_CONN116           0x4910
-#define AFE_SECURE_MASK_CONN116_1         0x4914
-#define AFE_SECURE_MASK_CONN116_2         0x4918
-#define AFE_SECURE_MASK_CONN116_3         0x491c
-#define AFE_SECURE_MASK_CONN116_4         0x4920
-#define AFE_SECURE_MASK_CONN117           0x4924
-#define AFE_SECURE_MASK_CONN117_1         0x4928
-#define AFE_SECURE_MASK_CONN117_2         0x492c
-#define AFE_SECURE_MASK_CONN117_3         0x4930
-#define AFE_SECURE_MASK_CONN117_4         0x4934
-#define AFE_SECURE_MASK_CONN118           0x4938
-#define AFE_SECURE_MASK_CONN118_1         0x493c
-#define AFE_SECURE_MASK_CONN118_2         0x4940
-#define AFE_SECURE_MASK_CONN118_3         0x4944
-#define AFE_SECURE_MASK_CONN118_4         0x4948
-#define AFE_SECURE_MASK_CONN119           0x494c
-#define AFE_SECURE_MASK_CONN119_1         0x4950
-#define AFE_SECURE_MASK_CONN119_2         0x4954
-#define AFE_SECURE_MASK_CONN119_3         0x4958
-#define AFE_SECURE_MASK_CONN119_4         0x495c
-#define AFE_SECURE_MASK_CONN120           0x4960
-#define AFE_SECURE_MASK_CONN120_1         0x4964
-#define AFE_SECURE_MASK_CONN120_2         0x4968
-#define AFE_SECURE_MASK_CONN120_3         0x496c
-#define AFE_SECURE_MASK_CONN120_4         0x4970
-#define AFE_SECURE_MASK_CONN121           0x4974
-#define AFE_SECURE_MASK_CONN121_1         0x4978
-#define AFE_SECURE_MASK_CONN121_2         0x497c
-#define AFE_SECURE_MASK_CONN121_3         0x4980
-#define AFE_SECURE_MASK_CONN121_4         0x4984
-#define AFE_SECURE_MASK_CONN122           0x4988
-#define AFE_SECURE_MASK_CONN122_1         0x498c
-#define AFE_SECURE_MASK_CONN122_2         0x4990
-#define AFE_SECURE_MASK_CONN122_3         0x4994
-#define AFE_SECURE_MASK_CONN122_4         0x4998
-#define AFE_SECURE_MASK_CONN123           0x499c
-#define AFE_SECURE_MASK_CONN123_1         0x49a0
-#define AFE_SECURE_MASK_CONN123_2         0x49a4
-#define AFE_SECURE_MASK_CONN123_3         0x49a8
-#define AFE_SECURE_MASK_CONN123_4         0x49ac
-#define AFE_SECURE_MASK_CONN124           0x49b0
-#define AFE_SECURE_MASK_CONN124_1         0x49b4
-#define AFE_SECURE_MASK_CONN124_2         0x49b8
-#define AFE_SECURE_MASK_CONN124_3         0x49bc
-#define AFE_SECURE_MASK_CONN124_4         0x49c0
-#define AFE_SECURE_MASK_CONN125           0x49c4
-#define AFE_SECURE_MASK_CONN125_1         0x49c8
-#define AFE_SECURE_MASK_CONN125_2         0x49cc
-#define AFE_SECURE_MASK_CONN125_3         0x49d0
-#define AFE_SECURE_MASK_CONN125_4         0x49d4
-#define AFE_SECURE_MASK_CONN126           0x49d8
-#define AFE_SECURE_MASK_CONN126_1         0x49dc
-#define AFE_SECURE_MASK_CONN126_2         0x49e0
-#define AFE_SECURE_MASK_CONN126_3         0x49e4
-#define AFE_SECURE_MASK_CONN126_4         0x49e8
-#define AFE_SECURE_MASK_CONN127           0x49ec
-#define AFE_SECURE_MASK_CONN127_1         0x49f0
-#define AFE_SECURE_MASK_CONN127_2         0x49f4
-#define AFE_SECURE_MASK_CONN127_3         0x49f8
-#define AFE_SECURE_MASK_CONN127_4         0x49fc
-#define AFE_SECURE_MASK_CONN128           0x4a00
-#define AFE_SECURE_MASK_CONN128_1         0x4a04
-#define AFE_SECURE_MASK_CONN128_2         0x4a08
-#define AFE_SECURE_MASK_CONN128_3         0x4a0c
-#define AFE_SECURE_MASK_CONN128_4         0x4a10
-#define AFE_SECURE_MASK_CONN129           0x4a14
-#define AFE_SECURE_MASK_CONN129_1         0x4a18
-#define AFE_SECURE_MASK_CONN129_2         0x4a1c
-#define AFE_SECURE_MASK_CONN129_3         0x4a20
-#define AFE_SECURE_MASK_CONN129_4         0x4a24
-#define AFE_SECURE_MASK_CONN130           0x4a28
-#define AFE_SECURE_MASK_CONN130_1         0x4a2c
-#define AFE_SECURE_MASK_CONN130_2         0x4a30
-#define AFE_SECURE_MASK_CONN130_3         0x4a34
-#define AFE_SECURE_MASK_CONN130_4         0x4a38
-#define AFE_SECURE_MASK_CONN131           0x4a3c
-#define AFE_SECURE_MASK_CONN131_1         0x4a40
-#define AFE_SECURE_MASK_CONN131_2         0x4a44
-#define AFE_SECURE_MASK_CONN131_3         0x4a48
-#define AFE_SECURE_MASK_CONN131_4         0x4a4c
-#define AFE_SECURE_MASK_CONN132           0x4a50
-#define AFE_SECURE_MASK_CONN132_1         0x4a54
-#define AFE_SECURE_MASK_CONN132_2         0x4a58
-#define AFE_SECURE_MASK_CONN132_3         0x4a5c
-#define AFE_SECURE_MASK_CONN132_4         0x4a60
-#define AFE_SECURE_MASK_CONN133           0x4a64
-#define AFE_SECURE_MASK_CONN133_1         0x4a68
-#define AFE_SECURE_MASK_CONN133_2         0x4a6c
-#define AFE_SECURE_MASK_CONN133_3         0x4a70
-#define AFE_SECURE_MASK_CONN133_4         0x4a74
-#define AFE_SECURE_MASK_CONN134           0x4a78
-#define AFE_SECURE_MASK_CONN134_1         0x4a7c
-#define AFE_SECURE_MASK_CONN134_2         0x4a80
-#define AFE_SECURE_MASK_CONN134_3         0x4a84
-#define AFE_SECURE_MASK_CONN134_4         0x4a88
-#define AFE_SECURE_MASK_CONN135           0x4a8c
-#define AFE_SECURE_MASK_CONN135_1         0x4a90
-#define AFE_SECURE_MASK_CONN135_2         0x4a94
-#define AFE_SECURE_MASK_CONN135_3         0x4a98
-#define AFE_SECURE_MASK_CONN135_4         0x4a9c
-#define AFE_SECURE_MASK_CONN136           0x4aa0
-#define AFE_SECURE_MASK_CONN136_1         0x4aa4
-#define AFE_SECURE_MASK_CONN136_2         0x4aa8
-#define AFE_SECURE_MASK_CONN136_3         0x4aac
-#define AFE_SECURE_MASK_CONN136_4         0x4ab0
-#define AFE_SECURE_MASK_CONN137           0x4ab4
-#define AFE_SECURE_MASK_CONN137_1         0x4ab8
-#define AFE_SECURE_MASK_CONN137_2         0x4abc
-#define AFE_SECURE_MASK_CONN137_3         0x4ac0
-#define AFE_SECURE_MASK_CONN137_4         0x4ac4
-#define AFE_SECURE_MASK_CONN138           0x4ac8
-#define AFE_SECURE_MASK_CONN138_1         0x4acc
-#define AFE_SECURE_MASK_CONN138_2         0x4ad0
-#define AFE_SECURE_MASK_CONN138_3         0x4ad4
-#define AFE_SECURE_MASK_CONN138_4         0x4ad8
-#define AFE_SECURE_MASK_CONN139           0x4adc
-#define AFE_SECURE_MASK_CONN139_1         0x4ae0
-#define AFE_SECURE_MASK_CONN139_2         0x4ae4
-#define AFE_SECURE_MASK_CONN139_3         0x4ae8
-#define AFE_SECURE_MASK_CONN139_4         0x4aec
-#define AFE_SECURE_MASK_CONN_RS           0x4af0
-#define AFE_SECURE_MASK_CONN_RS_1         0x4af4
-#define AFE_SECURE_MASK_CONN_RS_2         0x4af8
-#define AFE_SECURE_MASK_CONN_RS_3         0x4afc
-#define AFE_SECURE_MASK_CONN_RS_4         0x4b00
-#define AFE_SECURE_MASK_CONN_16BIT        0x4b04
-#define AFE_SECURE_MASK_CONN_16BIT_1      0x4b08
-#define AFE_SECURE_MASK_CONN_16BIT_2      0x4b0c
-#define AFE_SECURE_MASK_CONN_16BIT_3      0x4b10
-#define AFE_SECURE_MASK_CONN_16BIT_4      0x4b14
-#define AFE_SECURE_MASK_CONN_24BIT        0x4b18
-#define AFE_SECURE_MASK_CONN_24BIT_1      0x4b1c
-#define AFE_SECURE_MASK_CONN_24BIT_2      0x4b20
-#define AFE_SECURE_MASK_CONN_24BIT_3      0x4b24
-#define AFE_SECURE_MASK_CONN_24BIT_4      0x4b28
-#define AFE_SECURE_MASK_CONN0_5           0x4b2c
-#define AFE_SECURE_MASK_CONN1_5           0x4b30
-#define AFE_SECURE_MASK_CONN2_5           0x4b34
-#define AFE_SECURE_MASK_CONN3_5           0x4b38
-#define AFE_SECURE_MASK_CONN4_5           0x4b3c
-#define AFE_SECURE_MASK_CONN5_5           0x4b40
-#define AFE_SECURE_MASK_CONN6_5           0x4b44
-#define AFE_SECURE_MASK_CONN7_5           0x4b48
-#define AFE_SECURE_MASK_CONN8_5           0x4b4c
-#define AFE_SECURE_MASK_CONN9_5           0x4b50
-#define AFE_SECURE_MASK_CONN10_5          0x4b54
-#define AFE_SECURE_MASK_CONN11_5          0x4b58
-#define AFE_SECURE_MASK_CONN12_5          0x4b5c
-#define AFE_SECURE_MASK_CONN13_5          0x4b60
-#define AFE_SECURE_MASK_CONN14_5          0x4b64
-#define AFE_SECURE_MASK_CONN15_5          0x4b68
-#define AFE_SECURE_MASK_CONN16_5          0x4b6c
-#define AFE_SECURE_MASK_CONN17_5          0x4b70
-#define AFE_SECURE_MASK_CONN18_5          0x4b74
-#define AFE_SECURE_MASK_CONN19_5          0x4b78
-#define AFE_SECURE_MASK_CONN20_5          0x4b7c
-#define AFE_SECURE_MASK_CONN21_5          0x4b80
-#define AFE_SECURE_MASK_CONN22_5          0x4b84
-#define AFE_SECURE_MASK_CONN23_5          0x4b88
-#define AFE_SECURE_MASK_CONN24_5          0x4b8c
-#define AFE_SECURE_MASK_CONN25_5          0x4b90
-#define AFE_SECURE_MASK_CONN26_5          0x4b94
-#define AFE_SECURE_MASK_CONN27_5          0x4b98
-#define AFE_SECURE_MASK_CONN28_5          0x4b9c
-#define AFE_SECURE_MASK_CONN29_5          0x4ba0
-#define AFE_SECURE_MASK_CONN30_5          0x4ba4
-#define AFE_SECURE_MASK_CONN31_5          0x4ba8
-#define AFE_SECURE_MASK_CONN32_5          0x4bac
-#define AFE_SECURE_MASK_CONN33_5          0x4bb0
-#define AFE_SECURE_MASK_CONN34_5          0x4bb4
-#define AFE_SECURE_MASK_CONN35_5          0x4bb8
-#define AFE_SECURE_MASK_CONN36_5          0x4bbc
-#define AFE_SECURE_MASK_CONN37_5          0x4bc0
-#define AFE_SECURE_MASK_CONN38_5          0x4bc4
-#define AFE_SECURE_MASK_CONN39_5          0x4bc8
-#define AFE_SECURE_MASK_CONN40_5          0x4bcc
-#define AFE_SECURE_MASK_CONN41_5          0x4bd0
-#define AFE_SECURE_MASK_CONN42_5          0x4bd4
-#define AFE_SECURE_MASK_CONN43_5          0x4bd8
-#define AFE_SECURE_MASK_CONN44_5          0x4bdc
-#define AFE_SECURE_MASK_CONN45_5          0x4be0
-#define AFE_SECURE_MASK_CONN46_5          0x4be4
-#define AFE_SECURE_MASK_CONN47_5          0x4be8
-#define AFE_SECURE_MASK_CONN48_5          0x4bec
-#define AFE_SECURE_MASK_CONN49_5          0x4bf0
-#define AFE_SECURE_MASK_CONN50_5          0x4bf4
-#define AFE_SECURE_MASK_CONN51_5          0x4bf8
-#define AFE_SECURE_MASK_CONN52_5          0x4bfc
-#define AFE_GASRC0_NEW_CON0               0x4c40
-#define AFE_GASRC0_NEW_CON1               0x4c44
-#define AFE_GASRC0_NEW_CON2               0x4c48
-#define AFE_GASRC0_NEW_CON3               0x4c4c
-#define AFE_GASRC0_NEW_CON4               0x4c50
-#define AFE_GASRC0_NEW_CON5               0x4c54
-#define AFE_GASRC0_NEW_CON6               0x4c58
-#define AFE_GASRC0_NEW_CON7               0x4c5c
-#define AFE_GASRC0_NEW_CON8               0x4c60
-#define AFE_GASRC0_NEW_CON9               0x4c64
-#define AFE_GASRC0_NEW_CON10              0x4c68
-#define AFE_GASRC0_NEW_CON11              0x4c6c
-#define AFE_GASRC0_NEW_CON12              0x4c70
-#define AFE_GASRC0_NEW_CON13              0x4c74
-#define AFE_GASRC0_NEW_CON14              0x4c78
-#define AFE_GASRC1_NEW_CON0               0x4c80
-#define AFE_GASRC1_NEW_CON1               0x4c84
-#define AFE_GASRC1_NEW_CON2               0x4c88
-#define AFE_GASRC1_NEW_CON3               0x4c8c
-#define AFE_GASRC1_NEW_CON4               0x4c90
-#define AFE_GASRC1_NEW_CON5               0x4c94
-#define AFE_GASRC1_NEW_CON6               0x4c98
-#define AFE_GASRC1_NEW_CON7               0x4c9c
-#define AFE_GASRC1_NEW_CON8               0x4ca0
-#define AFE_GASRC1_NEW_CON9               0x4ca4
-#define AFE_GASRC1_NEW_CON10              0x4ca8
-#define AFE_GASRC1_NEW_CON11              0x4cac
-#define AFE_GASRC1_NEW_CON12              0x4cb0
-#define AFE_GASRC1_NEW_CON13              0x4cb4
-#define AFE_GASRC1_NEW_CON14              0x4cb8
-#define AFE_GASRC2_NEW_CON0               0x4cc0
-#define AFE_GASRC2_NEW_CON1               0x4cc4
-#define AFE_GASRC2_NEW_CON2               0x4cc8
-#define AFE_GASRC2_NEW_CON3               0x4ccc
-#define AFE_GASRC2_NEW_CON4               0x4cd0
-#define AFE_GASRC2_NEW_CON5               0x4cd4
-#define AFE_GASRC2_NEW_CON6               0x4cd8
-#define AFE_GASRC2_NEW_CON7               0x4cdc
-#define AFE_GASRC2_NEW_CON8               0x4ce0
-#define AFE_GASRC2_NEW_CON9               0x4ce4
-#define AFE_GASRC2_NEW_CON10              0x4ce8
-#define AFE_GASRC2_NEW_CON11              0x4cec
-#define AFE_GASRC2_NEW_CON12              0x4cf0
-#define AFE_GASRC2_NEW_CON13              0x4cf4
-#define AFE_GASRC2_NEW_CON14              0x4cf8
-#define AFE_GASRC3_NEW_CON0               0x4d00
-#define AFE_GASRC3_NEW_CON1               0x4d04
-#define AFE_GASRC3_NEW_CON2               0x4d08
-#define AFE_GASRC3_NEW_CON3               0x4d0c
-#define AFE_GASRC3_NEW_CON4               0x4d10
-#define AFE_GASRC3_NEW_CON5               0x4d14
-#define AFE_GASRC3_NEW_CON6               0x4d18
-#define AFE_GASRC3_NEW_CON7               0x4d1c
-#define AFE_GASRC3_NEW_CON8               0x4d20
-#define AFE_GASRC3_NEW_CON9               0x4d24
-#define AFE_GASRC3_NEW_CON10              0x4d28
-#define AFE_GASRC3_NEW_CON11              0x4d2c
-#define AFE_GASRC3_NEW_CON12              0x4d30
-#define AFE_GASRC3_NEW_CON13              0x4d34
-#define AFE_GASRC3_NEW_CON14              0x4d38
-#define AFE_GASRC4_NEW_CON0               0x4d40
-#define AFE_GASRC4_NEW_CON1               0x4d44
-#define AFE_GASRC4_NEW_CON2               0x4d48
-#define AFE_GASRC4_NEW_CON3               0x4d4c
-#define AFE_GASRC4_NEW_CON4               0x4d50
-#define AFE_GASRC4_NEW_CON5               0x4d54
-#define AFE_GASRC4_NEW_CON6               0x4d58
-#define AFE_GASRC4_NEW_CON7               0x4d5c
-#define AFE_GASRC4_NEW_CON8               0x4d60
-#define AFE_GASRC4_NEW_CON9               0x4d64
-#define AFE_GASRC4_NEW_CON10              0x4d68
-#define AFE_GASRC4_NEW_CON11              0x4d6c
-#define AFE_GASRC4_NEW_CON12              0x4d70
-#define AFE_GASRC4_NEW_CON13              0x4d74
-#define AFE_GASRC4_NEW_CON14              0x4d78
-#define AFE_GASRC5_NEW_CON0               0x4d80
-#define AFE_GASRC5_NEW_CON1               0x4d84
-#define AFE_GASRC5_NEW_CON2               0x4d88
-#define AFE_GASRC5_NEW_CON3               0x4d8c
-#define AFE_GASRC5_NEW_CON4               0x4d90
-#define AFE_GASRC5_NEW_CON5               0x4d94
-#define AFE_GASRC5_NEW_CON6               0x4d98
-#define AFE_GASRC5_NEW_CON7               0x4d9c
-#define AFE_GASRC5_NEW_CON8               0x4da0
-#define AFE_GASRC5_NEW_CON9               0x4da4
-#define AFE_GASRC5_NEW_CON10              0x4da8
-#define AFE_GASRC5_NEW_CON11              0x4dac
-#define AFE_GASRC5_NEW_CON12              0x4db0
-#define AFE_GASRC5_NEW_CON13              0x4db4
-#define AFE_GASRC5_NEW_CON14              0x4db8
-#define AFE_GASRC6_NEW_CON0               0x4dc0
-#define AFE_GASRC6_NEW_CON1               0x4dc4
-#define AFE_GASRC6_NEW_CON2               0x4dc8
-#define AFE_GASRC6_NEW_CON3               0x4dcc
-#define AFE_GASRC6_NEW_CON4               0x4dd0
-#define AFE_GASRC6_NEW_CON5               0x4dd4
-#define AFE_GASRC6_NEW_CON6               0x4dd8
-#define AFE_GASRC6_NEW_CON7               0x4ddc
-#define AFE_GASRC6_NEW_CON8               0x4de0
-#define AFE_GASRC6_NEW_CON9               0x4de4
-#define AFE_GASRC6_NEW_CON10              0x4de8
-#define AFE_GASRC6_NEW_CON11              0x4dec
-#define AFE_GASRC6_NEW_CON12              0x4df0
-#define AFE_GASRC6_NEW_CON13              0x4df4
-#define AFE_GASRC6_NEW_CON14              0x4df8
-#define AFE_GASRC7_NEW_CON0               0x4e00
-#define AFE_GASRC7_NEW_CON1               0x4e04
-#define AFE_GASRC7_NEW_CON2               0x4e08
-#define AFE_GASRC7_NEW_CON3               0x4e0c
-#define AFE_GASRC7_NEW_CON4               0x4e10
-#define AFE_GASRC7_NEW_CON5               0x4e14
-#define AFE_GASRC7_NEW_CON6               0x4e18
-#define AFE_GASRC7_NEW_CON7               0x4e1c
-#define AFE_GASRC7_NEW_CON8               0x4e20
-#define AFE_GASRC7_NEW_CON9               0x4e24
-#define AFE_GASRC7_NEW_CON10              0x4e28
-#define AFE_GASRC7_NEW_CON11              0x4e2c
-#define AFE_GASRC7_NEW_CON12              0x4e30
-#define AFE_GASRC7_NEW_CON13              0x4e34
-#define AFE_GASRC7_NEW_CON14              0x4e38
-#define AFE_GASRC8_NEW_CON0               0x4e40
-#define AFE_GASRC8_NEW_CON1               0x4e44
-#define AFE_GASRC8_NEW_CON2               0x4e48
-#define AFE_GASRC8_NEW_CON3               0x4e4c
-#define AFE_GASRC8_NEW_CON4               0x4e50
-#define AFE_GASRC8_NEW_CON5               0x4e54
-#define AFE_GASRC8_NEW_CON6               0x4e58
-#define AFE_GASRC8_NEW_CON7               0x4e5c
-#define AFE_GASRC8_NEW_CON8               0x4e60
-#define AFE_GASRC8_NEW_CON9               0x4e64
-#define AFE_GASRC8_NEW_CON10              0x4e68
-#define AFE_GASRC8_NEW_CON11              0x4e6c
-#define AFE_GASRC8_NEW_CON12              0x4e70
-#define AFE_GASRC8_NEW_CON13              0x4e74
-#define AFE_GASRC8_NEW_CON14              0x4e78
-#define AFE_GASRC9_NEW_CON0               0x4e80
-#define AFE_GASRC9_NEW_CON1               0x4e84
-#define AFE_GASRC9_NEW_CON2               0x4e88
-#define AFE_GASRC9_NEW_CON3               0x4e8c
-#define AFE_GASRC9_NEW_CON4               0x4e90
-#define AFE_GASRC9_NEW_CON5               0x4e94
-#define AFE_GASRC9_NEW_CON6               0x4e98
-#define AFE_GASRC9_NEW_CON7               0x4e9c
-#define AFE_GASRC9_NEW_CON8               0x4ea0
-#define AFE_GASRC9_NEW_CON9               0x4ea4
-#define AFE_GASRC9_NEW_CON10              0x4ea8
-#define AFE_GASRC9_NEW_CON11              0x4eac
-#define AFE_GASRC9_NEW_CON12              0x4eb0
-#define AFE_GASRC9_NEW_CON13              0x4eb4
-#define AFE_GASRC9_NEW_CON14              0x4eb8
-#define AFE_GASRC10_NEW_CON0              0x4ec0
-#define AFE_GASRC10_NEW_CON1              0x4ec4
-#define AFE_GASRC10_NEW_CON2              0x4ec8
-#define AFE_GASRC10_NEW_CON3              0x4ecc
-#define AFE_GASRC10_NEW_CON4              0x4ed0
-#define AFE_GASRC10_NEW_CON5              0x4ed4
-#define AFE_GASRC10_NEW_CON6              0x4ed8
-#define AFE_GASRC10_NEW_CON7              0x4edc
-#define AFE_GASRC10_NEW_CON8              0x4ee0
-#define AFE_GASRC10_NEW_CON9              0x4ee4
-#define AFE_GASRC10_NEW_CON10             0x4ee8
-#define AFE_GASRC10_NEW_CON11             0x4eec
-#define AFE_GASRC10_NEW_CON12             0x4ef0
-#define AFE_GASRC10_NEW_CON13             0x4ef4
-#define AFE_GASRC10_NEW_CON14             0x4ef8
-#define AFE_GASRC11_NEW_CON0              0x4f00
-#define AFE_GASRC11_NEW_CON1              0x4f04
-#define AFE_GASRC11_NEW_CON2              0x4f08
-#define AFE_GASRC11_NEW_CON3              0x4f0c
-#define AFE_GASRC11_NEW_CON4              0x4f10
-#define AFE_GASRC11_NEW_CON5              0x4f14
-#define AFE_GASRC11_NEW_CON6              0x4f18
-#define AFE_GASRC11_NEW_CON7              0x4f1c
-#define AFE_GASRC11_NEW_CON8              0x4f20
-#define AFE_GASRC11_NEW_CON9              0x4f24
-#define AFE_GASRC11_NEW_CON10             0x4f28
-#define AFE_GASRC11_NEW_CON11             0x4f2c
-#define AFE_GASRC11_NEW_CON12             0x4f30
-#define AFE_GASRC11_NEW_CON13             0x4f34
-#define AFE_GASRC11_NEW_CON14             0x4f38
-
-#define AFE_IEC_BURST_INFO_MON            0x64b0
-#define AFE_SPDIFOUT_IP_VERSION           0x64b4
-#define AFE_SPDIF_OUT_CFG0                0x64b8
-#define AFE_SPDIF_OUT_CFG1                0x64bc
-#define AFE_SPDIF_OUT_CHSTS1              0x64c0
-#define AFE_SPDIF_OUT_CHSTS2              0x64c4
-#define AFE_SPDIF_OUT_CHSTS3              0x64c8
-#define AFE_SPDIF_OUT_CHSTS4              0x64cc
-#define AFE_SPDIF_OUT_CHSTS5              0x64d0
-#define AFE_SPDIF_OUT_CHSTS6              0x64d4
-#define AFE_SPDIF_OUT_USERCODE1           0x64d8
-#define AFE_SPDIF_OUT_USERCODE2           0x64dc
-#define AFE_SPDIF_OUT_USERCODE3           0x64e0
-#define AFE_SPDIF_OUT_USERCODE4           0x64e4
-#define AFE_SPDIF_OUT_USERCODE5           0x64e8
-#define AFE_SPDIF_OUT_USERCODE6           0x64ec
-#define AFE_SPDIF_OUT_BURST_PRE0          0x64f0
-#define AFE_SPDIF_OUT_BURST_PRE1          0x64f4
-#define AFE_SPDIF_OUT_MON0                0x64f8
-#define AFE_SPDIF_OUT_MON1                0x64fc
-#define AFE_SPDIF_OUT_MON2                0x6500
-#define AFE_SPDIF_OUT_MON3                0x6504
-#define AFE_SPDIF_OUT_MON4                0x6508
-#define AFE_SPDIF_OUT_MON5                0x650c
-#define AFE_CONN0_6                       0x7000
-#define AFE_CONN1_6                       0x7004
-#define AFE_CONN2_6                       0x7008
-#define AFE_CONN3_6                       0x700c
-#define AFE_CONN4_6                       0x7010
-#define AFE_CONN5_6                       0x7014
-#define AFE_CONN6_6                       0x7018
-#define AFE_CONN7_6                       0x701c
-#define AFE_CONN8_6                       0x7020
-#define AFE_CONN9_6                       0x7024
-#define AFE_CONN10_6                      0x7028
-#define AFE_CONN11_6                      0x702c
-#define AFE_CONN12_6                      0x7030
-#define AFE_CONN13_6                      0x7034
-#define AFE_CONN14_6                      0x7038
-#define AFE_CONN15_6                      0x703c
-#define AFE_CONN16_6                      0x7040
-#define AFE_CONN17_6                      0x7044
-#define AFE_CONN18_6                      0x7048
-#define AFE_CONN19_6                      0x704c
-#define AFE_CONN20_6                      0x7050
-#define AFE_CONN21_6                      0x7054
-#define AFE_CONN22_6                      0x7058
-#define AFE_CONN23_6                      0x705c
-#define AFE_CONN24_6                      0x7060
-#define AFE_CONN25_6                      0x7064
-#define AFE_CONN26_6                      0x7068
-#define AFE_CONN27_6                      0x706c
-#define AFE_CONN28_6                      0x7070
-#define AFE_CONN29_6                      0x7074
-#define AFE_CONN30_6                      0x7078
-#define AFE_CONN31_6                      0x707c
-#define AFE_CONN32_6                      0x7080
-#define AFE_CONN33_6                      0x7084
-#define AFE_CONN34_6                      0x7088
-#define AFE_CONN35_6                      0x708c
-#define AFE_CONN36_6                      0x7090
-#define AFE_CONN37_6                      0x7094
-#define AFE_CONN38_6                      0x7098
-#define AFE_CONN39_6                      0x709c
-#define AFE_CONN40_6                      0x70a0
-#define AFE_CONN41_6                      0x70a4
-#define AFE_CONN42_6                      0x70a8
-#define AFE_CONN43_6                      0x70ac
-#define AFE_CONN44_6                      0x70b0
-#define AFE_CONN45_6                      0x70b4
-#define AFE_CONN46_6                      0x70b8
-#define AFE_CONN47_6                      0x70bc
-#define AFE_CONN48_6                      0x70c0
-#define AFE_CONN49_6                      0x70c4
-#define AFE_CONN50_6                      0x70c8
-#define AFE_CONN51_6                      0x70cc
-#define AFE_CONN52_6                      0x70d0
-#define AFE_CONN53_6                      0x70d4
-#define AFE_CONN54_6                      0x70d8
-#define AFE_CONN55_6                      0x70dc
-#define AFE_CONN56_6                      0x70e0
-#define AFE_CONN57_6                      0x70e4
-#define AFE_CONN58_6                      0x70e8
-#define AFE_CONN59_6                      0x70ec
-#define AFE_CONN60_6                      0x70f0
-#define AFE_CONN61_6                      0x70f4
-#define AFE_CONN62_6                      0x70f8
-#define AFE_CONN63_6                      0x70fc
-#define AFE_CONN64_6                      0x7100
-#define AFE_CONN65_6                      0x7104
-#define AFE_CONN66_6                      0x7108
-#define AFE_CONN67_6                      0x710c
-#define AFE_CONN68_6                      0x7110
-#define AFE_CONN69_6                      0x7114
-#define AFE_CONN70_6                      0x7118
-#define AFE_CONN71_6                      0x711c
-#define AFE_CONN72_6                      0x7120
-#define AFE_CONN73_6                      0x7124
-#define AFE_CONN74_6                      0x7128
-#define AFE_CONN75_6                      0x712c
-#define AFE_CONN76_6                      0x7130
-#define AFE_CONN77_6                      0x7134
-#define AFE_CONN78_6                      0x7138
-#define AFE_CONN79_6                      0x713c
-#define AFE_CONN80_6                      0x7140
-#define AFE_CONN81_6                      0x7144
-#define AFE_CONN82_6                      0x7148
-#define AFE_CONN83_6                      0x714c
-#define AFE_CONN84_6                      0x7150
-#define AFE_CONN85_6                      0x7154
-#define AFE_CONN86_6                      0x7158
-#define AFE_CONN87_6                      0x715c
-#define AFE_CONN88_6                      0x7160
-#define AFE_CONN89_6                      0x7164
-#define AFE_CONN90_6                      0x7168
-#define AFE_CONN91_6                      0x716c
-#define AFE_CONN92_6                      0x7170
-#define AFE_CONN93_6                      0x7174
-#define AFE_CONN94_6                      0x7178
-#define AFE_CONN95_6                      0x717c
-#define AFE_CONN96_6                      0x7180
-#define AFE_CONN97_6                      0x7184
-#define AFE_CONN98_6                      0x7188
-#define AFE_CONN99_6                      0x718c
-#define AFE_CONN100_6                     0x7190
-#define AFE_CONN101_6                     0x7194
-#define AFE_CONN102_6                     0x7198
-#define AFE_CONN103_6                     0x719c
-#define AFE_CONN104_6                     0x71a0
-#define AFE_CONN105_6                     0x71a4
-#define AFE_CONN106_6                     0x71a8
-#define AFE_CONN107_6                     0x71ac
-#define AFE_CONN108_6                     0x71b0
-#define AFE_CONN109_6                     0x71b4
-#define AFE_CONN110_6                     0x71b8
-#define AFE_CONN111_6                     0x71bc
-#define AFE_CONN112_6                     0x71c0
-#define AFE_CONN113_6                     0x71c4
-#define AFE_CONN114_6                     0x71c8
-#define AFE_CONN115_6                     0x71cc
-#define AFE_CONN116_6                     0x71d0
-#define AFE_CONN117_6                     0x71d4
-#define AFE_CONN118_6                     0x71d8
-#define AFE_CONN119_6                     0x71dc
-#define AFE_CONN120_6                     0x71e0
-#define AFE_CONN121_6                     0x71e4
-#define AFE_CONN122_6                     0x71e8
-#define AFE_CONN123_6                     0x71ec
-#define AFE_CONN124_6                     0x71f0
-#define AFE_CONN125_6                     0x71f4
-#define AFE_CONN126_6                     0x71f8
-#define AFE_CONN127_6                     0x71fc
-#define AFE_CONN128_6                     0x7200
-#define AFE_CONN129_6                     0x7204
-#define AFE_CONN130_6                     0x7208
-#define AFE_CONN131_6                     0x720c
-#define AFE_CONN132_6                     0x7210
-#define AFE_CONN133_6                     0x7214
-#define AFE_CONN134_6                     0x7218
-#define AFE_CONN135_6                     0x721c
-#define AFE_CONN136_6                     0x7220
-#define AFE_CONN137_6                     0x7224
-#define AFE_CONN138_6                     0x7228
-#define AFE_CONN139_6                     0x722c
-#define AFE_CONN176_6                     0x72c0
-#define AFE_CONN177_6                     0x72c4
-#define AFE_CONN182_6                     0x72d8
-#define AFE_CONN183_6                     0x72dc
-
-#endif
diff --git a/src/platform/mt8188/include/platform/platform.h b/src/platform/mt8188/include/platform/platform.h
deleted file mode 100644
index 187f0fa5e6a2..000000000000
--- a/src/platform/mt8188/include/platform/platform.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2022 MediaTek. All rights reserved.
- *
- * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
- *         Tinghan Shen <tinghan.shen@mediatek.com>
- */
-
-#ifdef __SOF_PLATFORM_H__
-
-#ifndef __PLATFORM_PLATFORM_H__
-#define __PLATFORM_PLATFORM_H__
-
-#if !defined(__ASSEMBLER__) && !defined(LINKER)
-
-#include <sof/lib/mailbox.h>
-#include <stddef.h>
-#include <stdint.h>
-
-struct ll_schedule_domain;
-struct timer;
-
-#define PLATFORM_DEFAULT_CLOCK CLK_CPU(0)
-#define LPSRAM_SIZE 16384
-
-/* IPC Interrupt */
-#define PLATFORM_IPC_INTERRUPT MTK_DSP_IRQ_MAILBOX
-#define PLATFORM_IPC_INTERRUPT_NAME NULL
-
-/* Host page size */
-#define HOST_PAGE_SIZE 4096
-#define PLATFORM_PAGE_TABLE_SIZE 256
-
-/* pipeline IRQ */
-#define PLATFORM_SCHEDULE_IRQ MTK_DSP_IRQ_SW
-#define PLATFORM_SCHEDULE_IRQ_NAME NULL
-
-/* Platform stream capabilities */
-#define PLATFORM_MAX_CHANNELS 4
-#define PLATFORM_MAX_STREAMS 5
-
-/* local buffer size of DMA tracing */
-#define DMA_TRACE_LOCAL_SIZE HOST_PAGE_SIZE
-
-/* trace bytes flushed during panic */
-#define DMA_FLUSH_TRACE_SIZE (MAILBOX_TRACE_SIZE >> 2)
-
-/* the interval of DMA trace copying */
-#define DMA_TRACE_PERIOD 500000
-
-/*
- * the interval of reschedule DMA trace copying in special case like half
- * fullness of local DMA trace buffer
- */
-#define DMA_TRACE_RESCHEDULE_TIME 100
-
-/* DSP default delay in cycles */
-#define PLATFORM_DEFAULT_DELAY 12
-
-#define SRAM_REG_FW_STATUS 0x4
-
-/* Platform defined panic code */
-static inline void platform_panic(uint32_t p)
-{
-	/* Store the error code in the debug box so the
-	 * application processor can pick it up. Takes up 4 bytes
-	 * from the debug box.
-	 */
-	mailbox_sw_reg_write(SRAM_REG_FW_STATUS, p);
-
-	/* Notify application processor */
-	trigger_irq_to_host_req();
-}
-
-/**
- * \brief Platform specific CPU entering idle.
- * May be power-optimized using platform specific capabilities.
- * @param level Interrupt level.
- */
-void platform_wait_for_interrupt(int level);
-
-extern intptr_t _module_init_start;
-extern intptr_t _module_init_end;
-#endif
-
-#endif /* __PLATFORM_PLATFORM_H__ */
-
-#else
-
-#error "This file shouldn't be included from outside of sof/platform.h"
-
-#endif /* __SOF_PLATFORM_H__ */
diff --git a/src/platform/mt8188/include/platform/trace/trace.h b/src/platform/mt8188/include/platform/trace/trace.h
deleted file mode 100644
index 393530083efb..000000000000
--- a/src/platform/mt8188/include/platform/trace/trace.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2022 MediaTek. All rights reserved.
- *
- * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
- *         Tinghan Shen <tinghan.shen@mediatek.com>
- */
-
-#ifdef __SOF_TRACE_TRACE_H__
-
-#ifndef __PLATFORM_TRACE_TRACE_H__
-#define __PLATFORM_TRACE_TRACE_H__
-
-#include <sof/lib/mailbox.h>
-#include <sof/lib/memory.h>
-#include <sof/lib/io.h>
-#include <platform/drivers/mt_reg_base.h>
-
-#define platform_trace_point(__x)
-
-#endif /* __PLATFORM_TRACE_TRACE_H__ */
-
-#else
-
-#error "This file shouldn't be included from outside of sof/trace/trace.h"
-
-#endif /* __SOF_TRACE_TRACE_H__ */
diff --git a/src/platform/mt8188/lib/CMakeLists.txt b/src/platform/mt8188/lib/CMakeLists.txt
deleted file mode 100644
index ef71f8eea6cd..000000000000
--- a/src/platform/mt8188/lib/CMakeLists.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-
-add_local_sources(sof
-	clk.c
-	dma.c
-	memory.c
-	dai.c
-)
diff --git a/src/platform/mt8188/lib/clk.c b/src/platform/mt8188/lib/clk.c
deleted file mode 100644
index 125cc8623c0a..000000000000
--- a/src/platform/mt8188/lib/clk.c
+++ /dev/null
@@ -1,142 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-/*
- * Copyright(c) 2022 MediaTek. All rights reserved.
- *
- * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
- *         Tinghan Shen <tinghan.shen@mediatek.com>
- */
-
-#include <platform/drivers/mt_reg_base.h>
-#include <rtos/clk.h>
-#include <rtos/wait.h>
-#include <sof/common.h>
-#include <sof/lib/cpu.h>
-#include <sof/lib/io.h>
-#include <sof/lib/memory.h>
-#include <sof/lib/notifier.h>
-#include <sof/lib/uuid.h>
-#include <rtos/sof.h>
-#include <sof/trace/trace.h>
-
-SOF_DEFINE_REG_UUID(clkdrv_mt8188);
-
-/* unused with Zephyr, generates no output */
-DECLARE_TR_CTX(clkdrv_tr, SOF_UUID(clkdrv_mt8188_uuid), LOG_LEVEL_INFO);
-
-/* default voltage is 0.75V */
-const struct freq_table platform_cpu_freq[] = {
-	{  26000000, 26000},
-	{ 400000000, 26000},
-	{ 800000000, 26000},
-};
-
-STATIC_ASSERT(ARRAY_SIZE(platform_cpu_freq) == NUM_CPU_FREQ,
-	      invalid_number_of_cpu_frequencies);
-
-static struct clock_info platform_clocks_info[NUM_CLOCKS];
-
-static void clk_dsppll_enable(uint32_t value)
-{
-	tr_dbg(&clkdrv_tr, "%d\n", value);
-
-	switch (value) {
-	case ADSP_CLK_PLL_400M:
-		io_reg_write(MTK_ADSPPLL_CON1, MTK_PLL_DIV_RATIO_400M);
-		break;
-	case ADSP_CLK_PLL_800M:
-		io_reg_write(MTK_ADSPPLL_CON1, MTK_PLL_DIV_RATIO_800M);
-		break;
-	default:
-		tr_err(&clkdrv_tr, "invalid dsppll: %d\n", value);
-		return;
-	}
-
-	io_reg_update_bits(MTK_ADSPPLL_CON3, MTK_PLL_PWR_ON, MTK_PLL_PWR_ON);
-	wait_delay_us(1);
-	io_reg_update_bits(MTK_ADSPPLL_CON3, MTK_PLL_ISO_EN, 0);
-	wait_delay_us(1);
-	io_reg_update_bits(MTK_ADSPPLL_CON0, MTK_PLL_EN, MTK_PLL_EN);
-	wait_delay_us(20);
-}
-
-static void clk_dsppll_disable(void)
-{
-	tr_dbg(&clkdrv_tr, "entry");
-
-	io_reg_update_bits(MTK_ADSPPLL_CON0, MTK_PLL_EN, 0);
-	wait_delay_us(1);
-	io_reg_update_bits(MTK_ADSPPLL_CON3, MTK_PLL_ISO_EN, MTK_PLL_ISO_EN);
-	wait_delay_us(1);
-	io_reg_update_bits(MTK_ADSPPLL_CON3, MTK_PLL_PWR_ON, 0);
-}
-
-static void set_mux_adsp_sel(uint32_t value)
-{
-	io_reg_write(MTK_CLK_CFG_17_CLR, MTK_CLK_ADSP_MASK << MTK_CLK_ADSP_OFFSET);
-	io_reg_write(MTK_CLK_CFG_17_SET, value << MTK_CLK_ADSP_OFFSET);
-	io_reg_write(MTK_CLK_CFG_UPDATE2, MTK_CLK_UPDATE_ADSK_CLK);
-
-	tr_dbg(&clkdrv_tr, "adsp_clk_mux=%x, CLK_CFG_17=0x%08x\n",
-	       value, io_reg_read(MTK_CLK_CFG_17));
-}
-
-static void set_mux_adsp_bus_sel(uint32_t value)
-{
-	io_reg_write(MTK_CLK_CFG_17_CLR,
-		     MTK_CLK_AUDIO_LOCAL_BUS_MASK << MTK_CLK_AUDIO_LOCAL_BUS_OFFSET);
-	io_reg_write(MTK_CLK_CFG_17_SET, value << MTK_CLK_AUDIO_LOCAL_BUS_OFFSET);
-	io_reg_write(MTK_CLK_CFG_UPDATE2, MTK_CLK_UPDATE_AUDIO_LOCAL_BUS_CLK);
-
-	tr_dbg(&clkdrv_tr, "audio_local_bus_mux=%x, CLK_CFG_17=0x%08x\n",
-	       value, io_reg_read(MTK_CLK_CFG_17));
-}
-
-static int clock_platform_set_dsp_freq(int clock, int freq_idx)
-{
-	int freq = platform_cpu_freq[freq_idx].freq;
-
-	tr_info(&clkdrv_tr, "clock_platform_set_cpu_freq %d\n", freq);
-
-	switch (freq_idx) {
-	case ADSP_CLK_26M:
-		set_mux_adsp_sel(MTK_CLK_ADSP_26M);
-		set_mux_adsp_bus_sel(MTK_CLK_AUDIO_LOCAL_BUS_26M);
-		clk_dsppll_disable();
-		break;
-	case ADSP_CLK_PLL_400M:
-		clock_platform_set_dsp_freq(clock, ADSP_CLK_26M);
-		clk_dsppll_enable(ADSP_CLK_PLL_400M);
-		set_mux_adsp_sel(MTK_CLK_ADSP_ADSPPLL);
-		set_mux_adsp_bus_sel(MTK_CLK_AUDIO_LOCAL_BUS_MAINPLL_D_7);
-		break;
-	case ADSP_CLK_PLL_800M:
-		clock_platform_set_dsp_freq(clock, ADSP_CLK_26M);
-		clk_dsppll_enable(ADSP_CLK_PLL_800M);
-		set_mux_adsp_sel(MTK_CLK_ADSP_ADSPPLL);
-		set_mux_adsp_bus_sel(MTK_CLK_AUDIO_LOCAL_BUS_MAINPLL_D_4);
-		break;
-	}
-
-	return 0;
-}
-
-void platform_clock_init(struct sof *sof)
-{
-	int i;
-
-	sof->clocks = platform_clocks_info;
-
-	for (i = 0; i < CONFIG_CORE_COUNT; i++) {
-		sof->clocks[i] = (struct clock_info){
-			.freqs_num = NUM_CPU_FREQ,
-			.freqs = platform_cpu_freq,
-			.default_freq_idx = CPU_DEFAULT_IDX,
-			.current_freq_idx = CPU_DEFAULT_IDX,
-			.notification_id = NOTIFIER_ID_CPU_FREQ,
-			.notification_mask = NOTIFIER_TARGET_CORE_MASK(i),
-			.set_freq = clock_platform_set_dsp_freq,
-		};
-	}
-
-	clock_set_freq(CLK_CPU(cpu_get_id()), CLK_MAX_CPU_HZ);
-}
diff --git a/src/platform/mt8188/lib/dai.c b/src/platform/mt8188/lib/dai.c
deleted file mode 100644
index 53b30146a2fd..000000000000
--- a/src/platform/mt8188/lib/dai.c
+++ /dev/null
@@ -1,57 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-/*
- * Copyright(c) 2023 MediaTek. All rights reserved.
- *
- * Author: Trevor Wu <trevor.wu@mediatek.com>
- */
-
-#include <sof/common.h>
-#include <sof/lib/dai.h>
-#include <sof/lib/memory.h>
-#include <rtos/sof.h>
-#include <rtos/spinlock.h>
-#include <ipc/dai.h>
-#include <ipc/stream.h>
-
-#include <sof/drivers/afe-dai.h>
-#include <mt8188-afe-common.h>
-
-static int afe_dai_handshake[MT8188_DAI_NUM] = {
-	AFE_HANDSHAKE(MT8188_AFE_IO_ETDM2_OUT, MT8188_IRQ_13, MT8188_MEMIF_DL2),
-	AFE_HANDSHAKE(MT8188_AFE_IO_ETDM1_OUT, MT8188_IRQ_14, MT8188_MEMIF_DL3),
-	AFE_HANDSHAKE(MT8188_AFE_IO_ADDA, MT8188_IRQ_21, MT8188_MEMIF_UL4),
-	AFE_HANDSHAKE(MT8188_AFE_IO_ETDM2_IN, MT8188_IRQ_22, MT8188_MEMIF_UL5),
-};
-
-static struct dai afe_dai[MT8188_DAI_NUM];
-
-const struct dai_type_info dti[] = {
-	{
-		.type = SOF_DAI_MEDIATEK_AFE,
-		.dai_array = afe_dai,
-		.num_dais = ARRAY_SIZE(afe_dai),
-	},
-};
-
-const struct dai_info lib_dai = {
-	.dai_type_array = dti,
-	.num_dai_types = ARRAY_SIZE(dti),
-};
-
-int dai_init(struct sof *sof)
-{
-	int i;
-
-	/* initialize spin locks early to enable ref counting */
-	for (i = 0; i < ARRAY_SIZE(afe_dai); i++) {
-		k_spinlock_init(&afe_dai[i].lock);
-		afe_dai[i].index = AFE_HS_GET_DAI(afe_dai_handshake[i]);
-		afe_dai[i].drv = &afe_dai_driver;
-		/* TODO, fifo[0] change to target playback or capture */
-		afe_dai[i].plat_data.fifo[0].handshake = afe_dai_handshake[i];
-	}
-
-	sof->dai_info = &lib_dai;
-
-	return 0;
-}
diff --git a/src/platform/mt8188/lib/dma.c b/src/platform/mt8188/lib/dma.c
deleted file mode 100644
index 51bcb18a16ef..000000000000
--- a/src/platform/mt8188/lib/dma.c
+++ /dev/null
@@ -1,61 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-/*
- * Copyright(c) 2022 MediaTek. All rights reserved.
- *
- * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
- *         Tinghan Shen <tinghan.shen@mediatek.com>
- */
-
-#include <rtos/interrupt.h>
-#include <rtos/spinlock.h>
-#include <sof/common.h>
-#include <sof/drivers/afe-memif.h>
-#include <sof/lib/dma.h>
-#include <sof/lib/memory.h>
-#include <rtos/sof.h>
-
-#include <mt8188-afe-reg.h>
-#include <mt8188-afe-common.h>
-
-extern const struct dma_ops dummy_dma_ops;
-
-static struct dma dma[PLATFORM_NUM_DMACS] = {
-{
-	.plat_data = {
-		.id		= DMA_ID_HOST,
-		.dir		= DMA_DIR_HMEM_TO_LMEM | DMA_DIR_LMEM_TO_HMEM,
-		.devs		= DMA_DEV_HOST,
-		.channels	= 16,
-	},
-	.ops	= &dummy_dma_ops,
-},
-{
-	.plat_data = {
-		.id		= DMA_ID_AFE_MEMIF,
-		.dir		= DMA_DIR_MEM_TO_DEV | DMA_DIR_DEV_TO_MEM,
-		.devs		= DMA_DEV_AFE_MEMIF,
-		.base		= AFE_BASE_ADDR,
-		.channels	= MT8188_MEMIF_NUM,
-	},
-	.ops	= &memif_ops,
-},
-
-};
-
-static const struct dma_info lib_dma = {
-	.dma_array = cache_to_uncache_init((struct dma *)dma),
-	.num_dmas = ARRAY_SIZE(dma)
-};
-
-int dmac_init(struct sof *sof)
-{
-	int i;
-
-	/* early lock initialization for ref counting */
-	for (i = 0; i < ARRAY_SIZE(dma); i++)
-		k_spinlock_init(&dma[i].lock);
-
-	sof->dma_info = &lib_dma;
-
-	return 0;
-}
diff --git a/src/platform/mt8188/lib/memory.c b/src/platform/mt8188/lib/memory.c
deleted file mode 100644
index 6475b01e48ad..000000000000
--- a/src/platform/mt8188/lib/memory.c
+++ /dev/null
@@ -1,102 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-/*
- * Copyright(c) 2022 MediaTek. All rights reserved.
- *
- * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
- *         Tinghan Shen <tinghan.shen@mediatek.com>
- */
-
-#include <ipc/topology.h>
-#include <sof/common.h>
-#include <sof/lib/mm_heap.h>
-#include <sof/lib/memory.h>
-#include <rtos/sof.h>
-
-/* Heap blocks for system runtime */
-static struct block_hdr sys_rt_block64[HEAP_SYS_RT_COUNT64];
-static struct block_hdr sys_rt_block512[HEAP_SYS_RT_COUNT512];
-static struct block_hdr sys_rt_block1024[HEAP_SYS_RT_COUNT1024];
-
-/* Heap memory for system runtime */
-static struct block_map sys_rt_heap_map[] = {
-	BLOCK_DEF(64, HEAP_SYS_RT_COUNT64, sys_rt_block64),
-	BLOCK_DEF(512, HEAP_SYS_RT_COUNT512, sys_rt_block512),
-	BLOCK_DEF(1024, HEAP_SYS_RT_COUNT1024, sys_rt_block1024),
-};
-
-/* Heap blocks for modules */
-static struct block_hdr mod_block16[HEAP_RT_COUNT16];
-static struct block_hdr mod_block32[HEAP_RT_COUNT32];
-static struct block_hdr mod_block64[HEAP_RT_COUNT64];
-static struct block_hdr mod_block128[HEAP_RT_COUNT128];
-static struct block_hdr mod_block256[HEAP_RT_COUNT256];
-static struct block_hdr mod_block512[HEAP_RT_COUNT512];
-static struct block_hdr mod_block1024[HEAP_RT_COUNT1024];
-static struct block_hdr mod_block2048[HEAP_RT_COUNT2048];
-static struct block_hdr mod_block4096[HEAP_RT_COUNT4096];
-
-/* Heap memory map for modules */
-static struct block_map rt_heap_map[] = {
-	BLOCK_DEF(16, HEAP_RT_COUNT16, mod_block16),
-	BLOCK_DEF(32, HEAP_RT_COUNT32, mod_block32),
-	BLOCK_DEF(64, HEAP_RT_COUNT64, mod_block64),
-	BLOCK_DEF(128, HEAP_RT_COUNT128, mod_block128),
-	BLOCK_DEF(256, HEAP_RT_COUNT256, mod_block256),
-	BLOCK_DEF(512, HEAP_RT_COUNT512, mod_block512),
-	BLOCK_DEF(1024, HEAP_RT_COUNT1024, mod_block1024),
-	BLOCK_DEF(2048, HEAP_RT_COUNT2048, mod_block2048),
-	BLOCK_DEF(4096, HEAP_RT_COUNT4096, mod_block4096),
-};
-
-/* Heap blocks for buffers */
-static struct block_hdr buf_block[HEAP_BUFFER_COUNT];
-
-/* Heap memory map for buffers */
-static struct block_map buf_heap_map[] = {
-	BLOCK_DEF(HEAP_BUFFER_BLOCK_SIZE, HEAP_BUFFER_COUNT, buf_block),
-};
-
-static struct mm memmap = {
-	.system[0] = {
-		.heap = HEAP_SYSTEM_BASE,
-		.size = HEAP_SYSTEM_SIZE,
-		.info = {.free = HEAP_SYSTEM_SIZE,},
-		.caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_CACHE |
-			SOF_MEM_CAPS_DMA,
-	},
-	.system_runtime[0] = {
-		.blocks = ARRAY_SIZE(sys_rt_heap_map),
-		.map = sys_rt_heap_map,
-		.heap = HEAP_SYS_RUNTIME_BASE,
-		.size = HEAP_SYS_RUNTIME_SIZE,
-		.info = {.free = HEAP_SYS_RUNTIME_SIZE,},
-		.caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_CACHE |
-			SOF_MEM_CAPS_DMA,
-	},
-	.runtime[0] = {
-		.blocks = ARRAY_SIZE(rt_heap_map),
-		.map = rt_heap_map,
-		.heap = HEAP_RUNTIME_BASE,
-		.size = HEAP_RUNTIME_SIZE,
-		.info = {.free = HEAP_RUNTIME_SIZE,},
-		.caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_CACHE |
-			SOF_MEM_CAPS_DMA,
-	},
-	.buffer[0] = {
-		.blocks = ARRAY_SIZE(buf_heap_map),
-		.map = buf_heap_map,
-		.heap = HEAP_BUFFER_BASE,
-		.size = HEAP_BUFFER_SIZE,
-		.info = {.free = HEAP_BUFFER_SIZE,},
-		.caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_CACHE |
-			SOF_MEM_CAPS_DMA,
-	},
-	.total = {.free = HEAP_SYSTEM_SIZE + HEAP_SYS_RUNTIME_SIZE +
-			HEAP_RUNTIME_SIZE + HEAP_BUFFER_SIZE,},
-};
-
-void platform_init_memmap(struct sof *sof)
-{
-	/* memmap has been initialized statically as a part of .data */
-	sof->memory_map = &memmap;
-}
diff --git a/src/platform/mt8188/mt8188.x.in b/src/platform/mt8188/mt8188.x.in
deleted file mode 100644
index 99120a0b225c..000000000000
--- a/src/platform/mt8188/mt8188.x.in
+++ /dev/null
@@ -1,538 +0,0 @@
-/*
- * Linker Script for mt8188 MediaTek
- *
- * This script is run through the GNU C preprocessor to align the memory
- * offsets with headers.
- *
- * Use spaces for formatting as cpp ignore tab sizes.
- */
-
-
-#include <sof/lib/memory.h>
-#include <xtensa/config/core-isa.h>
-
-#if CONFIG_MEDIATEK_DRAM_IMAGE
-#define IMAGE_LOC sof_dram
-#else
-#define IMAGE_LOC sof_sram
-#endif
-
-OUTPUT_ARCH(xtensa)
-
-MEMORY
-{
-  vector_reset_text :
-        org = XCHAL_RESET_VECTOR0_PADDR,
-        len = SOF_MEM_RESET_TEXT_SIZE
-  vector_reset_lit :
-        org = XCHAL_RESET_VECTOR0_PADDR + SOF_MEM_RESET_TEXT_SIZE,
-        len = SOF_MEM_RESET_LIT_SIZE
-  vector_base_text :
-        org = XCHAL_VECBASE_RESET_PADDR,
-        len = SOF_MEM_VECBASE_LIT_SIZE
-  vector_int2_lit :
-        org = XCHAL_INTLEVEL2_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
-        len = SOF_MEM_VECT_LIT_SIZE
-  vector_int2_text :
-        org = XCHAL_INTLEVEL2_VECTOR_PADDR,
-        len = SOF_MEM_VECT_TEXT_SIZE
-  vector_int3_lit :
-        org = XCHAL_INTLEVEL3_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
-        len = SOF_MEM_VECT_LIT_SIZE
-  vector_int3_text :
-        org = XCHAL_INTLEVEL3_VECTOR_PADDR,
-        len = SOF_MEM_VECT_TEXT_SIZE
-  vector_int4_lit :
-        org = XCHAL_INTLEVEL4_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
-        len = SOF_MEM_VECT_LIT_SIZE
-  vector_int4_text :
-        org = XCHAL_INTLEVEL4_VECTOR_PADDR,
-        len = SOF_MEM_VECT_TEXT_SIZE
-  vector_int5_lit :
-        org = XCHAL_INTLEVEL5_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
-        len = SOF_MEM_VECT_LIT_SIZE
-  vector_int5_text :
-        org = XCHAL_INTLEVEL5_VECTOR_PADDR,
-        len = SOF_MEM_VECT_TEXT_SIZE
-  vector_kernel_lit :
-        org = XCHAL_KERNEL_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
-        len = SOF_MEM_VECT_LIT_SIZE
-  vector_kernel_text :
-        org = XCHAL_KERNEL_VECTOR_PADDR,
-        len = SOF_MEM_VECT_TEXT_SIZE
-  vector_user_lit :
-        org = XCHAL_USER_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
-        len = SOF_MEM_VECT_LIT_SIZE
-  vector_user_text :
-        org = XCHAL_USER_VECTOR_PADDR,
-        len = SOF_MEM_VECT_TEXT_SIZE
-  vector_double_lit :
-        org = XCHAL_DOUBLEEXC_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
-        len = SOF_MEM_VECT_LIT_SIZE
-  vector_double_text :
-        org = XCHAL_DOUBLEEXC_VECTOR_PADDR,
-        len = SOF_MEM_VECT_TEXT_SIZE
-  sof_sram :
-        org = SRAM_START,
-        len = SRAM_SIZE
-  sof_dram :
-        org = SOF_DRAM_BASE,
-        len = SOF_DRAM_SIZE
-  system_heap :
-        org = HEAP_SYSTEM_BASE,
-        len = HEAP_SYSTEM_SIZE
-  system_runtime_heap :
-        org = HEAP_SYS_RUNTIME_BASE,
-        len = HEAP_SYS_RUNTIME_SIZE
-  runtime_heap :
-        org = HEAP_RUNTIME_BASE,
-        len = HEAP_RUNTIME_SIZE
-  buffer_heap :
-        org = HEAP_BUFFER_BASE,
-        len = HEAP_BUFFER_SIZE
-  sof_stack :
-        org = SOF_STACK_END,
-        len = SOF_STACK_BASE - SOF_STACK_END
-  static_uuid_entries_seg (!ari) :
-        org = UUID_ENTRY_ELF_BASE,
-        len = UUID_ENTRY_ELF_SIZE
-  static_log_entries_seg (!ari) :
-        org = LOG_ENTRY_ELF_BASE,
-        len = LOG_ENTRY_ELF_SIZE
-  fw_metadata_seg (!ari) :
-        org = EXT_MANIFEST_ELF_BASE,
-        len = EXT_MANIFEST_ELF_SIZE
-}
-
-PHDRS
-{
-  vector_reset_text_phdr PT_LOAD;
-  vector_reset_lit_phdr PT_LOAD;
-  vector_base_text_phdr PT_LOAD;
-  vector_base_lit_phdr PT_LOAD;
-  vector_int2_text_phdr PT_LOAD;
-  vector_int2_lit_phdr PT_LOAD;
-  vector_int3_text_phdr PT_LOAD;
-  vector_int3_lit_phdr PT_LOAD;
-  vector_int4_text_phdr PT_LOAD;
-  vector_int4_lit_phdr PT_LOAD;
-  vector_int5_text_phdr PT_LOAD;
-  vector_int5_lit_phdr PT_LOAD;
-  vector_kernel_text_phdr PT_LOAD;
-  vector_kernel_lit_phdr PT_LOAD;
-  vector_user_text_phdr PT_LOAD;
-  vector_user_lit_phdr PT_LOAD;
-  vector_double_text_phdr PT_LOAD;
-  vector_double_lit_phdr PT_LOAD;
-  sof_sram_phdr PT_LOAD;
-  system_heap_phdr PT_LOAD;
-  system_runtime_heap_phdr PT_LOAD;
-  runtime_heap_phdr PT_LOAD;
-  buffer_heap_phdr PT_LOAD;
-  sof_stack_phdr PT_LOAD;
-  static_uuid_entries_phdr PT_NOTE;
-  static_log_entries_phdr PT_NOTE;
-  metadata_entries_phdr PT_NOTE;
-}
-
-/*  Default entry point:  */
-ENTRY(_ResetVector)
-_rom_store_table = 0;
-
-/* ABI0 does not use Window base */
-PROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR);
-
-/* Various memory-map dependent cache attribute settings: */
-_memmap_cacheattr_wb_base = 0x00000100;
-_memmap_cacheattr_wt_base = 0x00000300;
-_memmap_cacheattr_bp_base = 0x00000400;
-_memmap_cacheattr_unused_mask = 0xFFFFF0FF;
-_memmap_cacheattr_wb_trapnull = 0x44444140;
-_memmap_cacheattr_wba_trapnull = 0x44444140;
-_memmap_cacheattr_wbna_trapnull = 0x44444240;
-_memmap_cacheattr_wt_trapnull = 0x44444340;
-_memmap_cacheattr_bp_trapnull = 0x44444440;
-_memmap_cacheattr_wb_strict = 0x00000100;
-_memmap_cacheattr_wt_strict = 0x00000300;
-_memmap_cacheattr_bp_strict = 0x00000400;
-_memmap_cacheattr_wb_allvalid = 0x44444144;
-_memmap_cacheattr_wt_allvalid = 0x44444344;
-_memmap_cacheattr_bp_allvalid = 0x44444444;
-PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);
-
-_EXT_MAN_ALIGN_ = 16;
-EXTERN(ext_man_fw_ver)
-
-SECTIONS
-{
-  .ResetVector.text : ALIGN(4)
-  {
-    _ResetVector_text_start = ABSOLUTE(.);
-    KEEP (*(.ResetVector.text))
-    _ResetVector_text_end = ABSOLUTE(.);
-  } >vector_reset_text :vector_reset_text_phdr
-
-  .ResetVector.literal : ALIGN(4)
-  {
-    _ResetVector_literal_start = ABSOLUTE(.);
-    *(.ResetVector.literal)
-    _ResetVector_literal_end = ABSOLUTE(.);
-  } >vector_reset_lit :vector_reset_lit_phdr
-
-  .WindowVectors.text : ALIGN(4)
-  {
-    _WindowVectors_text_start = ABSOLUTE(.);
-    KEEP (*(.WindowVectors.text))
-    _WindowVectors_text_end = ABSOLUTE(.);
-  } >vector_base_text :vector_base_text_phdr
-
-  .Level2InterruptVector.literal : ALIGN(4)
-  {
-    _Level2InterruptVector_literal_start = ABSOLUTE(.);
-    *(.Level2InterruptVector.literal)
-    _Level2InterruptVector_literal_end = ABSOLUTE(.);
-  } >vector_int2_lit :vector_int2_lit_phdr
-
-  .Level2InterruptVector.text : ALIGN(4)
-  {
-    _Level2InterruptVector_text_start = ABSOLUTE(.);
-    KEEP (*(.Level2InterruptVector.text))
-    _Level2InterruptVector_text_end = ABSOLUTE(.);
-  } >vector_int2_text :vector_int2_text_phdr
-
-  .Level3InterruptVector.literal : ALIGN(4)
-  {
-    _Level3InterruptVector_literal_start = ABSOLUTE(.);
-    *(.Level3InterruptVector.literal)
-    _Level3InterruptVector_literal_end = ABSOLUTE(.);
-  } >vector_int3_lit :vector_int3_lit_phdr
-
-  .Level3InterruptVector.text : ALIGN(4)
-  {
-    _Level3InterruptVector_text_start = ABSOLUTE(.);
-    KEEP (*(.Level3InterruptVector.text))
-    _Level3InterruptVector_text_end = ABSOLUTE(.);
-  } >vector_int3_text :vector_int3_text_phdr
-
-  .Level4InterruptVector.literal : ALIGN(4)
-  {
-    _Level4InterruptVector_literal_start = ABSOLUTE(.);
-    *(.Level4InterruptVector.literal)
-    _Level4InterruptVector_literal_end = ABSOLUTE(.);
-  } >vector_int4_lit :vector_int4_lit_phdr
-
-  .Level4InterruptVector.text : ALIGN(4)
-  {
-    _Level4InterruptVector_text_start = ABSOLUTE(.);
-    KEEP (*(.Level4InterruptVector.text))
-    _Level4InterruptVector_text_end = ABSOLUTE(.);
-  } >vector_int4_text :vector_int4_text_phdr
-
-  .DebugExceptionVector.literal : ALIGN(4)
-  {
-    _DebugExceptionVector_literal_start = ABSOLUTE(.);
-    *(.DebugExceptionVector.literal)
-    _DebugExceptionVector_literal_end = ABSOLUTE(.);
-  } >vector_int5_lit :vector_int5_lit_phdr
-
-  .DebugExceptionVector.text : ALIGN(4)
-  {
-    _DebugExceptionVector_text_start = ABSOLUTE(.);
-    KEEP (*(.DebugExceptionVector.text))
-    _DebugExceptionVector_text_end = ABSOLUTE(.);
-  } >vector_int5_text :vector_int5_text_phdr
-
-  .NMIExceptionVector.literal : ALIGN(4)
-  {
-    _NMIExceptionVector_literal_start = ABSOLUTE(.);
-    *(.NMIExceptionVector.literal)
-    _NMIExceptionVector_literal_end = ABSOLUTE(.);
-  } >vector_int5_lit :vector_int5_lit_phdr
-
-  .NMIExceptionVector.text : ALIGN(4)
-  {
-    _NMIExceptionVector_text_start = ABSOLUTE(.);
-    KEEP (*(.NMIExceptionVector.text))
-    _NMIExceptionVector_text_end = ABSOLUTE(.);
-  } >vector_int5_text :vector_int5_text_phdr
-
-  .KernelExceptionVector.literal : ALIGN(4)
-  {
-    _KernelExceptionVector_literal_start = ABSOLUTE(.);
-    *(.KernelExceptionVector.literal)
-    _KernelExceptionVector_literal_end = ABSOLUTE(.);
-  } >vector_kernel_lit :vector_kernel_lit_phdr
-
-  .KernelExceptionVector.text : ALIGN(4)
-  {
-    _KernelExceptionVector_text_start = ABSOLUTE(.);
-    KEEP (*(.KernelExceptionVector.text))
-    _KernelExceptionVector_text_end = ABSOLUTE(.);
-  } >vector_kernel_text :vector_kernel_text_phdr
-
-  .UserExceptionVector.literal : ALIGN(4)
-  {
-    _UserExceptionVector_literal_start = ABSOLUTE(.);
-    *(.UserExceptionVector.literal)
-    _UserExceptionVector_literal_end = ABSOLUTE(.);
-  } >vector_user_lit :vector_user_lit_phdr
-
-  .UserExceptionVector.text : ALIGN(4)
-  {
-    _UserExceptionVector_text_start = ABSOLUTE(.);
-    KEEP (*(.UserExceptionVector.text))
-    _UserExceptionVector_text_end = ABSOLUTE(.);
-  } >vector_user_text :vector_user_text_phdr
-
-  .DoubleExceptionVector.literal : ALIGN(4)
-  {
-    _DoubleExceptionVector_literal_start = ABSOLUTE(.);
-    *(.DoubleExceptionVector.literal)
-    _DoubleExceptionVector_literal_end = ABSOLUTE(.);
-  } >vector_double_lit :vector_double_lit_phdr
-
-  .DoubleExceptionVector.text : ALIGN(4)
-  {
-    _DoubleExceptionVector_text_start = ABSOLUTE(.);
-    KEEP (*(.DoubleExceptionVector.text))
-    _DoubleExceptionVector_text_end = ABSOLUTE(.);
-  } >vector_double_text :vector_double_text_phdr
-
-  .fw_ready : ALIGN(4)
-  {
-    KEEP (*(.fw_ready))
-    KEEP (*(.fw_ready_metadata))
-  } >IMAGE_LOC :sof_sram_phdr
-
-  .rodata : ALIGN(4)
-  {
-    _rodata_start = ABSOLUTE(.);
-    *(.rodata)
-    *(.rodata.*)
-    *(.gnu.linkonce.r.*)
-    *(.rodata1)
-    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);
-    KEEP (*(.xt_except_table))
-    KEEP (*(.gcc_except_table))
-    *(.gnu.linkonce.e.*)
-    *(.gnu.version_r)
-    KEEP (*(.eh_frame))
-    /*  C++ constructor and destructor tables, properly ordered:  */
-    KEEP (*crtbegin.o(.ctors))
-    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
-    KEEP (*(SORT(.ctors.*)))
-    KEEP (*(.ctors))
-    KEEP (*crtbegin.o(.dtors))
-    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
-    KEEP (*(SORT(.dtors.*)))
-    KEEP (*(.dtors))
-    /*  C++ exception handlers table:  */
-    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);
-    *(.xt_except_desc)
-    *(.gnu.linkonce.h.*)
-    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
-    *(.xt_except_desc_end)
-    *(.dynamic)
-    *(.gnu.version_d)
-    . = ALIGN(4);		/* this table MUST be 4-byte aligned */
-    _bss_table_start = ABSOLUTE(.);
-    LONG(_bss_start)
-    LONG(_bss_end)
-    _bss_table_end = ABSOLUTE(.);
-    _rodata_end = ABSOLUTE(.);
-  } >IMAGE_LOC :sof_sram_phdr
-
-  .module_init : ALIGN(4)
-  {
-   _module_init_start = ABSOLUTE(.);
-    *(*.initcall)
-    _module_init_end = ABSOLUTE(.);
-  } >IMAGE_LOC :sof_sram_phdr
-
-  .text : ALIGN(4)
-  {
-    _stext = .;
-    _text_start = ABSOLUTE(.);
-    *(.entry.text)
-    *(.init.literal)
-    KEEP(*(.init))
-    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
-    *(.fini.literal)
-    KEEP(*(.fini))
-    *(.gnu.version)
-    _text_end = ABSOLUTE(.);
-    _etext = .;
-  } >IMAGE_LOC :sof_sram_phdr
-
-  .reset.rodata : ALIGN(4)
-  {
-    _reset_rodata_start = ABSOLUTE(.);
-    *(.reset.rodata)
-    _reset_rodata_end = ABSOLUTE(.);
-  } >IMAGE_LOC :sof_sram_phdr
-
-
-  .data : ALIGN(4)
-  {
-    _data_start = ABSOLUTE(.);
-    *(.data)
-    *(.data.*)
-    *(.gnu.linkonce.d.*)
-    KEEP(*(.gnu.linkonce.d.*personality*))
-    *(.data1)
-    *(.sdata)
-    *(.sdata.*)
-    *(.gnu.linkonce.s.*)
-    *(.sdata2)
-    *(.sdata2.*)
-    *(.gnu.linkonce.s2.*)
-    KEEP(*(.jcr))
-    _trace_ctx_start = ABSOLUTE(.);
-    *(.trace_ctx)
-    _trace_ctx_end = ABSOLUTE(.);
-    _data_end = ABSOLUTE(.);
-  } >IMAGE_LOC :sof_sram_phdr
-
-  .lit4 : ALIGN(4)
-  {
-    _lit4_start = ABSOLUTE(.);
-    *(*.lit4)
-    *(.lit4.*)
-    *(.gnu.linkonce.lit4.*)
-    _lit4_end = ABSOLUTE(.);
-  } >IMAGE_LOC :sof_sram_phdr
-
-  .bss (NOLOAD) : ALIGN(8)
-  {
-    . = ALIGN (8);
-    _bss_start = ABSOLUTE(.);
-    *(.dynsbss)
-    *(.sbss)
-    *(.sbss.*)
-    *(.gnu.linkonce.sb.*)
-    *(.scommon)
-    *(.sbss2)
-    *(.sbss2.*)
-    *(.gnu.linkonce.sb2.*)
-    *(.dynbss)
-    *(.bss)
-    *(.bss.*)
-    *(.gnu.linkonce.b.*)
-    *(COMMON)
-    . = ALIGN (8);
-    _bss_end = ABSOLUTE(.);
-  } >IMAGE_LOC :sof_sram_phdr
-
-  /* stack */
-  _end = SOF_STACK_END;
-  PROVIDE(end = SOF_STACK_END);
-  _stack_sentry = SOF_STACK_END;
-  __stack = SOF_STACK_BASE;
-
-  .debug  0 :  { *(.debug) }
-  .line  0 :  { *(.line) }
-  .debug_srcinfo  0 :  { *(.debug_srcinfo) }
-  .debug_sfnames  0 :  { *(.debug_sfnames) }
-  .debug_aranges  0 :  { *(.debug_aranges) }
-  .debug_pubnames  0 :  { *(.debug_pubnames) }
-  .debug_info  0 :  { *(.debug_info) }
-  .debug_abbrev  0 :  { *(.debug_abbrev) }
-  .debug_line  0 :  { *(.debug_line) }
-  .debug_frame  0 :  { *(.debug_frame) }
-  .debug_str  0 :  { *(.debug_str) }
-  .debug_loc  0 :  { *(.debug_loc) }
-  .debug_macinfo  0 :  { *(.debug_macinfo) }
-  .debug_weaknames  0 :  { *(.debug_weaknames) }
-  .debug_funcnames  0 :  { *(.debug_funcnames) }
-  .debug_typenames  0 :  { *(.debug_typenames) }
-  .debug_varnames  0 :  { *(.debug_varnames) }
-
-  .xt.insn 0 :
-  {
-    KEEP (*(.xt.insn))
-    KEEP (*(.gnu.linkonce.x.*))
-  }
-  .xt.prop 0 :
-  {
-    KEEP (*(.xt.prop))
-    KEEP (*(.xt.prop.*))
-    KEEP (*(.gnu.linkonce.prop.*))
-  }
-  .xt.lit 0 :
-  {
-    KEEP (*(.xt.lit))
-    KEEP (*(.xt.lit.*))
-    KEEP (*(.gnu.linkonce.p.*))
-  }
-  .xt.profile_range 0 :
-  {
-    KEEP (*(.xt.profile_range))
-    KEEP (*(.gnu.linkonce.profile_range.*))
-  }
-  .xt.profile_ranges 0 :
-  {
-    KEEP (*(.xt.profile_ranges))
-    KEEP (*(.gnu.linkonce.xt.profile_ranges.*))
-  }
-  .xt.profile_files 0 :
-  {
-    KEEP (*(.xt.profile_files))
-    KEEP (*(.gnu.linkonce.xt.profile_files.*))
-  }
-
-  .system_heap (NOLOAD) : ALIGN(8)
-  {
-    . = ALIGN (32);
-    _system_heap_start = ABSOLUTE(.);
-    . = . + HEAP_SYSTEM_SIZE;
-    _system_heap_end = ABSOLUTE(.);
-  } >system_heap :system_heap_phdr
-
-  .system_runtime_heap (NOLOAD) : ALIGN(8)
-  {
-    . = ALIGN (HEAP_BUF_ALIGNMENT);
-    _system_runtime_heap_start = ABSOLUTE(.);
-    . = . + HEAP_SYS_RUNTIME_SIZE;
-    _system_runtime_heap_end = ABSOLUTE(.);
-  } >system_runtime_heap :system_runtime_heap_phdr
-
-  .runtime_heap (NOLOAD) : ALIGN(8)
-  {
-    . = ALIGN (32);
-    _runtime_heap_start = ABSOLUTE(.);
-    . = . + HEAP_RUNTIME_SIZE;
-    _runtime_heap_end = ABSOLUTE(.);
-  } >runtime_heap :runtime_heap_phdr
-
-  .buffer_heap (NOLOAD) : ALIGN(8)
-  {
-    . = ALIGN (HEAP_BUF_ALIGNMENT);
-    _buffer_heap_start = ABSOLUTE(.);
-    . = . + HEAP_BUFFER_SIZE;
-    _buffer_heap_end = ABSOLUTE(.);
-  } >buffer_heap :buffer_heap_phdr
-
-  .sof_stack (NOLOAD) : ALIGN(8)
-  {
-    . = ALIGN (4096);
-    _sof_stack_start = ABSOLUTE(.);
-    . = . + SOF_STACK_TOTAL_SIZE;
-    _sof_stack_end = ABSOLUTE(.);
-  } >sof_stack :sof_stack_phdr
-
-  .static_uuid_entries (COPY) : ALIGN(1024)
-  {
-    *(*.static_uuids)
-  } > static_uuid_entries_seg :static_uuid_entries_phdr
-
-  .static_log_entries (COPY) : ALIGN(1024)
-  {
-    *(*.static_log*)
-  } > static_log_entries_seg :static_log_entries_phdr
-
-  .fw_metadata (COPY) : ALIGN(1024)
-  {
-    KEEP (*(.fw_metadata))
-    . = ALIGN(_EXT_MAN_ALIGN_);
-  } >fw_metadata_seg :metadata_entries_phdr
-}
diff --git a/src/platform/mt8188/platform.c b/src/platform/mt8188/platform.c
deleted file mode 100644
index babedcba3ac6..000000000000
--- a/src/platform/mt8188/platform.c
+++ /dev/null
@@ -1,218 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-/*
- * Copyright(c) 2022 MediaTek. All rights reserved.
- *
- * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
- *         Tinghan Shen <tinghan.shen@mediatek.com>
- */
-
-#include <errno.h>
-#include <ipc/dai.h>
-#include <ipc/header.h>
-#include <ipc/info.h>
-#include <kernel/abi.h>
-#include <kernel/ext_manifest.h>
-#include <platform/drivers/timer.h>
-#include <rtos/clk.h>
-#include <rtos/timer.h>
-#include <rtos/interrupt.h>
-#include <sof/compiler_info.h>
-#include <sof/debug/debug.h>
-#include <sof/drivers/edma.h>
-#include <sof/ipc/msg.h>
-#include <sof/fw-ready-metadata.h>
-#include <sof/lib/agent.h>
-#include <sof/lib/cpu.h>
-#include <sof/lib/dai.h>
-#include <sof/lib/dma.h>
-#include <sof/lib/mailbox.h>
-#include <sof/lib/memory.h>
-#include <sof/lib/mm_heap.h>
-#include <sof/platform.h>
-#include <sof/schedule/edf_schedule.h>
-#include <sof/schedule/ll_schedule.h>
-#include <sof/schedule/ll_schedule_domain.h>
-#include <rtos/sof.h>
-#include <sof/trace/dma-trace.h>
-#include <sof_versions.h>
-#include <stdint.h>
-#include <xtensa/hal.h>
-
-struct sof;
-
-static const struct sof_ipc_fw_ready ready
-	__section(".fw_ready") = {
-	.hdr = {
-		.cmd = SOF_IPC_FW_READY,
-		.size = sizeof(struct sof_ipc_fw_ready),
-	},
-	/* dspbox is for DSP initiated IPC, hostbox is for host initiated IPC */
-	.version = {
-		.hdr.size = sizeof(struct sof_ipc_fw_version),
-		.micro = SOF_MICRO,
-		.minor = SOF_MINOR,
-		.major = SOF_MAJOR,
-		.tag = SOF_TAG,
-		.abi_version = SOF_ABI_VERSION,
-		.src_hash = SOF_SRC_HASH,
-	},
-	.flags = DEBUG_SET_FW_READY_FLAGS,
-};
-
-#define NUM_MTK_WINDOWS 6
-
-const struct ext_man_windows xsram_window
-		__aligned(EXT_MAN_ALIGN) __section(".fw_metadata") __unused = {
-	.hdr = {
-		.type = EXT_MAN_ELEM_WINDOW,
-		.elem_size = ALIGN_UP_COMPILE(sizeof(struct ext_man_windows), EXT_MAN_ALIGN),
-	},
-	.window = {
-		.ext_hdr	= {
-			.hdr.cmd = SOF_IPC_FW_READY,
-			.hdr.size = sizeof(struct sof_ipc_window),
-			.type	= SOF_IPC_EXT_WINDOW,
-		},
-		.num_windows	= NUM_MTK_WINDOWS,
-		.window	= {
-			{
-				.type	= SOF_IPC_REGION_UPBOX,
-				.id	= 0,	/* map to host window 0 */
-				.flags	= 0,
-				.size	= MAILBOX_DSPBOX_SIZE,
-				.offset	= MAILBOX_DSPBOX_OFFSET,
-			},
-			{
-				.type	= SOF_IPC_REGION_DOWNBOX,
-				.id	= 0,	/* map to host window 0 */
-				.flags	= 0,
-				.size	= MAILBOX_HOSTBOX_SIZE,
-				.offset	= MAILBOX_HOSTBOX_OFFSET,
-			},
-			{
-				.type	= SOF_IPC_REGION_DEBUG,
-				.id	= 0,	/* map to host window 0 */
-				.flags	= 0,
-				.size	= MAILBOX_DEBUG_SIZE,
-				.offset	= MAILBOX_DEBUG_OFFSET,
-			},
-			{
-				.type	= SOF_IPC_REGION_TRACE,
-				.id	= 0,	/* map to host window 0 */
-				.flags	= 0,
-				.size	= MAILBOX_TRACE_SIZE,
-				.offset	= MAILBOX_TRACE_OFFSET,
-			},
-			{
-				.type	= SOF_IPC_REGION_STREAM,
-				.id	= 0,	/* map to host window 0 */
-				.flags	= 0,
-				.size	= MAILBOX_STREAM_SIZE,
-				.offset	= MAILBOX_STREAM_OFFSET,
-			},
-			{
-				.type	= SOF_IPC_REGION_EXCEPTION,
-				.id	= 0,	/* map to host window 0 */
-				.flags	= 0,
-				.size	= MAILBOX_EXCEPTION_SIZE,
-				.offset	= MAILBOX_EXCEPTION_OFFSET,
-			},
-		},
-	}
-};
-
-static struct timer timer_shared = {
-	.id = OSTIMER0,
-	.irq = MTK_DSP_IRQ_OSTIMER32,
-};
-
-/* Override the default MPU setup. This table matches the memory map
- * of the 'sample_controller' core and will need to be modified for
- * other cores.
- * NOTE: This table sets up all of external memory as shared uncached.
- * For best results, edit the LSP memory map to create a separate
- * section in shared memory, place all sections that need to be uncached
- * into that section, and only map that section uncached. See README
- * for more details.
- */
-const struct xthal_MPU_entry __xt_mpu_init_table[] __section(".ResetVector.text") = {
-	XTHAL_MPU_ENTRY(0x00000000, 1, XTHAL_AR_RWXrwx, XTHAL_MEM_DEVICE),		// infra
-	XTHAL_MPU_ENTRY(0x4e100000, 1, XTHAL_AR_RWXrwx, XTHAL_MEM_WRITEBACK),		// sram
-	XTHAL_MPU_ENTRY(0x4e180000, 1, XTHAL_AR_NONE, XTHAL_MEM_DEVICE),		// unused
-	XTHAL_MPU_ENTRY(0x60000000, 1, XTHAL_AR_RWXrwx, XTHAL_MEM_WRITEBACK),		// dram
-	XTHAL_MPU_ENTRY(0x60500000, 1, XTHAL_AR_RWXrwx, XTHAL_MEM_NON_CACHEABLE),	// dram
-	XTHAL_MPU_ENTRY(0x61100000, 1, XTHAL_AR_NONE, XTHAL_MEM_DEVICE),		// unused
-};
-
-const unsigned int __xt_mpu_init_table_size __section(".ResetVector.text") =
-	ARRAY_SIZE(__xt_mpu_init_table);
-
-int platform_boot_complete(uint32_t boot_message)
-{
-	mailbox_dspbox_write(0, &ready, sizeof(ready));
-
-	/* now interrupt host to tell it we are done booting */
-	trigger_irq_to_host_req();
-
-	return 0;
-}
-
-int platform_init(struct sof *sof)
-{
-	int ret;
-
-	sof->platform_timer = &timer_shared;
-	sof->cpu_timers = sof->platform_timer;
-
-	platform_interrupt_init();
-	platform_clock_init(sof);
-
-	scheduler_init_edf();
-
-	/* init low latency domains and schedulers */
-	sof->platform_timer_domain = timer_domain_init(sof->platform_timer, PLATFORM_DEFAULT_CLOCK);
-	scheduler_init_ll(sof->platform_timer_domain);
-	platform_timer_start(sof->platform_timer);
-
-	sa_init(sof, CONFIG_SYSTICK_PERIOD);
-
-	/* init DMA */
-	ret = dmac_init(sof);
-	if (ret < 0)
-		return -ENODEV;
-
-	/* Init platform domain */
-	sof->platform_dma_domain = dma_multi_chan_domain_init(&sof->dma_info->dma_array[0], 1,
-							      PLATFORM_DEFAULT_CLOCK, false);
-	scheduler_init_ll(sof->platform_dma_domain);
-
-	/* initialize the host IPC mechanims */
-	ipc_init(sof);
-
-	ret = dai_init(sof);
-	if (ret < 0)
-		return ret;
-
-#if CONFIG_TRACE
-	/* Initialize DMA for Trace*/
-	trace_point(TRACE_BOOT_PLATFORM_DMA_TRACE);
-	dma_trace_init_complete(sof->dmat);
-#endif
-
-	/* show heap status */
-	heap_trace_all(1);
-
-	return 0;
-}
-
-int platform_context_save(struct sof *sof)
-{
-	clock_set_freq(CLK_CPU(cpu_get_id()), CLK_DEFAULT_CPU_HZ);
-	return 0;
-}
-
-void platform_wait_for_interrupt(int level)
-{
-	arch_wait_for_interrupt(level);
-}
-
diff --git a/src/platform/mt8195/CMakeLists.txt b/src/platform/mt8195/CMakeLists.txt
deleted file mode 100644
index b5b1e06e9e10..000000000000
--- a/src/platform/mt8195/CMakeLists.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-
-add_subdirectory(lib)
-
-add_local_sources(sof platform.c afe-platform.c)
-target_include_directories(sof_options INTERFACE ${PROJECT_SOURCE_DIR}/src/platform/mt8195/include/platform)
diff --git a/src/platform/mt8195/afe-platform.c b/src/platform/mt8195/afe-platform.c
deleted file mode 100644
index f879b2dcfeaf..000000000000
--- a/src/platform/mt8195/afe-platform.c
+++ /dev/null
@@ -1,256 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-/*
- * Copyright(c) 2021 MediaTek. All rights reserved.
- *
- * Author: YC Hung <yc.hung@mediatek.com>
- */
-
-#include <sof/common.h>
-#include <errno.h>
-#include <sof/drivers/afe-drv.h>
-#include <mt8195-afe-regs.h>
-#include <mt8195-afe-common.h>
-
-/*
- * AFE: Audio Front-End
- *
- * frontend (memif):
- *   memory interface
- *   UL (uplink for capture)
- *   DL (downlink for playback)
- * backend:
- *   TDM In
- *   TMD out
- *   DMIC
- *   GASRC
- *   etc.
- * interconn:
- *   inter-connection,
- *   connect frontends and backends as DSP path
- */
-
-static const struct mtk_base_memif_data memif_data[MT8195_MEMIF_NUM] = {
-	[MT8195_MEMIF_DL2] = {
-		.name = "DL2",
-		.id = MT8195_MEMIF_DL2,
-		.reg_ofs_base = AFE_DL2_BASE,
-		.reg_ofs_cur = AFE_DL2_CUR,
-		.reg_ofs_end = AFE_DL2_END,
-		.fs_reg = AFE_MEMIF_AGENT_FS_CON0,
-		.fs_shift = 10,
-		.fs_maskbit = 0x1f,
-		.mono_reg = -1,
-		.mono_shift = -1,
-		.enable_reg = AFE_DAC_CON0,
-		.enable_shift = 18,
-		.hd_reg = AFE_DL2_CON0,
-		.hd_shift = 5,
-		.agent_disable_reg = AUDIO_TOP_CON5,
-		.agent_disable_shift = 18,
-		.ch_num_reg = AFE_DL2_CON0,
-		.ch_num_shift = 0,
-		.ch_num_maskbit = 0x1f,
-		.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
-		.msb_shift = 18,
-		.msb2_reg = AFE_NORMAL_END_ADR_MSB,
-		.msb2_shift = 18,
-	},
-	[MT8195_MEMIF_DL3] = {
-		.name = "DL3",
-		.id = MT8195_MEMIF_DL3,
-		.reg_ofs_base = AFE_DL3_BASE,
-		.reg_ofs_cur = AFE_DL3_CUR,
-		.reg_ofs_end = AFE_DL3_END,
-		.fs_reg = AFE_MEMIF_AGENT_FS_CON0,
-		.fs_shift = 15,
-		.fs_maskbit = 0x1f,
-		.mono_reg = -1,
-		.mono_shift = -1,
-		.enable_reg = AFE_DAC_CON0,
-		.enable_shift = 19,
-		.hd_reg = AFE_DL3_CON0,
-		.hd_shift = 5,
-		.agent_disable_reg = AUDIO_TOP_CON5,
-		.agent_disable_shift = 19,
-		.ch_num_reg = AFE_DL3_CON0,
-		.ch_num_shift = 0,
-		.ch_num_maskbit = 0x1f,
-		.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
-		.msb_shift = 19,
-		.msb2_reg = AFE_NORMAL_END_ADR_MSB,
-		.msb2_shift = 19,
-	},
-	[MT8195_MEMIF_UL4] = {
-		.name = "UL4",
-		.id = MT8195_MEMIF_UL4,
-		.reg_ofs_base = AFE_UL4_BASE,
-		.reg_ofs_cur = AFE_UL4_CUR,
-		.reg_ofs_end = AFE_UL4_END,
-		.fs_reg = AFE_MEMIF_AGENT_FS_CON2,
-		.fs_shift = 15,
-		.fs_maskbit = 0x1f,
-		.mono_reg = AFE_UL4_CON0,
-		.mono_shift = 1,
-		.enable_reg = AFE_DAC_CON0,
-		.enable_shift = 4,
-		.hd_reg = AFE_UL4_CON0,
-		.hd_shift = 5,
-		.agent_disable_reg = AUDIO_TOP_CON5,
-		.agent_disable_shift = 3,
-		.ch_num_reg = -1,
-		.ch_num_shift = 0,
-		.ch_num_maskbit = 0,
-		.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
-		.msb_shift = 3,
-		.msb2_reg = AFE_NORMAL_END_ADR_MSB,
-		.msb2_shift = 3,
-	},
-	[MT8195_MEMIF_UL5] = {
-		.name = "UL5",
-		.id = MT8195_MEMIF_UL5,
-		.reg_ofs_base = AFE_UL5_BASE,
-		.reg_ofs_cur = AFE_UL5_CUR,
-		.reg_ofs_end = AFE_UL5_END,
-		.fs_reg = AFE_MEMIF_AGENT_FS_CON2,
-		.fs_shift = 20,
-		.fs_maskbit = 0x1f,
-		.mono_reg = AFE_UL5_CON0,
-		.mono_shift = 1,
-		.enable_reg = AFE_DAC_CON0,
-		.enable_shift = 5,
-		.hd_reg = AFE_UL5_CON0,
-		.hd_shift = 5,
-		.agent_disable_reg = AUDIO_TOP_CON5,
-		.agent_disable_shift = 4,
-		.ch_num_reg = -1,
-		.ch_num_shift = 0,
-		.ch_num_maskbit = 0,
-		.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
-		.msb_shift = 4,
-		.msb2_reg = AFE_NORMAL_END_ADR_MSB,
-		.msb2_shift = 4,
-	}
-};
-
-struct mt8195_afe_rate {
-	unsigned int rate;
-	unsigned int reg_value;
-};
-
-static const struct mt8195_afe_rate mt8195_afe_rates[] = {
-	{
-		.rate = 8000,
-		.reg_value = 0,
-	},
-	{
-		.rate = 12000,
-		.reg_value = 1,
-	},
-	{
-		.rate = 16000,
-		.reg_value = 2,
-	},
-	{
-		.rate = 24000,
-		.reg_value = 3,
-	},
-	{
-		.rate = 32000,
-		.reg_value = 4,
-	},
-	{
-		.rate = 48000,
-		.reg_value = 5,
-	},
-	{
-		.rate = 96000,
-		.reg_value = 6,
-	},
-	{
-		.rate = 192000,
-		.reg_value = 7,
-	},
-	{
-		.rate = 384000,
-		.reg_value = 8,
-	},
-	{
-		.rate = 7350,
-		.reg_value = 16,
-	},
-	{
-		.rate = 11025,
-		.reg_value = 17,
-	},
-	{
-		.rate = 14700,
-		.reg_value = 18,
-	},
-	{
-		.rate = 22050,
-		.reg_value = 19,
-	},
-	{
-		.rate = 29400,
-		.reg_value = 20,
-	},
-	{
-		.rate = 44100,
-		.reg_value = 21,
-	},
-	{
-		.rate = 88200,
-		.reg_value = 22,
-	},
-	{
-		.rate = 176400,
-		.reg_value = 23,
-	},
-	{
-		.rate = 352800,
-		.reg_value = 24,
-	},
-};
-
-static unsigned int mt8195_afe_fs_timing(unsigned int rate)
-{
-	int i;
-
-	for (i = 0; i < ARRAY_SIZE(mt8195_afe_rates); i++)
-		if (mt8195_afe_rates[i].rate == rate)
-			return mt8195_afe_rates[i].reg_value;
-
-	return -EINVAL;
-}
-
-static unsigned int mt8195_afe_fs(unsigned int rate, int aud_blk)
-{
-	return mt8195_afe_fs_timing(rate);
-}
-
-static unsigned int mt8195_afe2adsp_addr(unsigned int addr)
-{
-	/*TODO : Need apply the address remap */
-	return addr;
-}
-
-static unsigned int mt8195_adsp2afe_addr(unsigned int addr)
-{
-	/* TODO : Need apply the address remap */
-	return addr;
-}
-
-struct mtk_base_afe_platform mtk_afe_platform = {
-	.base_addr = AFE_BASE_ADDR,
-	.memif_datas = memif_data,
-	.memif_size = MT8195_MEMIF_NUM,
-	.memif_dl_num = MT8195_MEMIF_DL_NUM,
-	.memif_32bit_supported = 0,
-	.irq_datas = NULL,
-	.irqs_size = 0,
-	.dais_size = MT8195_DAI_NUM,
-	.afe2adsp_addr = mt8195_afe2adsp_addr,
-	.adsp2afe_addr = mt8195_adsp2afe_addr,
-	.afe_fs = mt8195_afe_fs,
-	.irq_fs = mt8195_afe_fs_timing,
-};
diff --git a/src/platform/mt8195/include/arch/xtensa/config/core-isa.h b/src/platform/mt8195/include/arch/xtensa/config/core-isa.h
deleted file mode 100644
index 0c5a5fd59fe5..000000000000
--- a/src/platform/mt8195/include/arch/xtensa/config/core-isa.h
+++ /dev/null
@@ -1,697 +0,0 @@
-/*
-* xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
-*				processor CORE configuration
-*
-* See <xtensa/config/core.h>, which includes this file, for more details.
-*/
-/* Xtensa processor core configuration information.
-
-   Customer ID=16233; Build=0x89932; Copyright (c) 1999-2020 Tensilica Inc.
-
-   Permission is hereby granted, free of charge, to any person obtaining
-   a copy of this software and associated documentation files (the
-   "Software"), to deal in the Software without restriction, including
-   without limitation the rights to use, copy, modify, merge, publish,
-   distribute, sublicense, and/or sell copies of the Software, and to
-   permit persons to whom the Software is furnished to do so, subject to
-   the following conditions:
-
-   The above copyright notice and this permission notice shall be included
-   in all copies or substantial portions of the Software.
-
-   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
-
-#ifndef _XTENSA_CORE_CONFIGURATION_H
-#define _XTENSA_CORE_CONFIGURATION_H
-
-/* depot/dev/Homewood/Xtensa/SWConfig/hal/core-common.h.tph#24 - edit change 444323 (text+ko) */
-
-/****************************************************************************
-	    Parameters Useful for Any Code, USER or PRIVILEGED
- ****************************************************************************/
-
-/*
- *  Note:  Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
- *  configured, and a value of 0 otherwise.  These macros are always defined.
- */
-
-
-/*----------------------------------------------------------------------
-				ISA
-  ----------------------------------------------------------------------*/
-
-#define XCHAL_HAVE_BE			0	/* big-endian byte ordering */
-#define XCHAL_HAVE_WINDOWED		1	/* windowed registers option */
-#define XCHAL_NUM_AREGS			64	/* num of physical addr regs */
-#define XCHAL_NUM_AREGS_LOG2		6	/* log2(XCHAL_NUM_AREGS) */
-#define XCHAL_MAX_INSTRUCTION_SIZE	11	/* max instr bytes (3..8) */
-#define XCHAL_HAVE_DEBUG		1	/* debug option */
-#define XCHAL_HAVE_DENSITY		1	/* 16-bit instructions */
-#define XCHAL_HAVE_LOOPS		1	/* zero-overhead loops */
-#define XCHAL_LOOP_BUFFER_SIZE		256	/* zero-ov. loop instr buffer size */
-#define XCHAL_HAVE_NSA			1	/* NSA/NSAU instructions */
-#define XCHAL_HAVE_MINMAX		1	/* MIN/MAX instructions */
-#define XCHAL_HAVE_SEXT			1	/* SEXT instruction */
-#define XCHAL_HAVE_DEPBITS		0	/* DEPBITS instruction */
-#define XCHAL_HAVE_CLAMPS		1	/* CLAMPS instruction */
-#define XCHAL_HAVE_MUL16		1	/* MUL16S/MUL16U instructions */
-#define XCHAL_HAVE_MUL32		1	/* MULL instruction */
-#define XCHAL_HAVE_MUL32_HIGH		0	/* MULUH/MULSH instructions */
-#define XCHAL_HAVE_DIV32		1	/* QUOS/QUOU/REMS/REMU instructions */
-#define XCHAL_HAVE_L32R			1	/* L32R instruction */
-#define XCHAL_HAVE_ABSOLUTE_LITERALS	0	/* non-PC-rel (extended) L32R */
-#define XCHAL_HAVE_CONST16		0	/* CONST16 instruction */
-#define XCHAL_HAVE_ADDX			1	/* ADDX#/SUBX# instructions */
-#define XCHAL_HAVE_EXCLUSIVE            1	/* L32EX/S32EX instructions */
-#define XCHAL_HAVE_WIDE_BRANCHES	0	/* B*.W18 or B*.W15 instr's */
-#define XCHAL_HAVE_PREDICTED_BRANCHES	0	/* B[EQ/EQZ/NE/NEZ]T instr's */
-#define XCHAL_HAVE_CALL4AND12		1	/* (obsolete option) */
-#define XCHAL_HAVE_ABS			1	/* ABS instruction */
-#define XCHAL_HAVE_RELEASE_SYNC		1	/* L32AI/S32RI instructions */
-#define XCHAL_HAVE_S32C1I		0	/* S32C1I instruction */
-#define XCHAL_HAVE_SPECULATION		0	/* speculation */
-#define XCHAL_HAVE_FULL_RESET		1	/* all regs/state reset */
-#define XCHAL_NUM_CONTEXTS		1	/* */
-#define XCHAL_NUM_MISC_REGS		4	/* num of scratch regs (0..4) */
-#define XCHAL_HAVE_TAP_MASTER		0	/* JTAG TAP control instr's */
-#define XCHAL_HAVE_PRID			1	/* processor ID register */
-#define XCHAL_HAVE_EXTERN_REGS		1	/* WER/RER instructions */
-#define XCHAL_HAVE_MX			0	/* MX core (Tensilica internal) */
-#define XCHAL_HAVE_MP_INTERRUPTS	0	/* interrupt distributor port */
-#define XCHAL_HAVE_MP_RUNSTALL		0	/* core RunStall control port */
-#define XCHAL_HAVE_PSO			0	/* Power Shut-Off */
-#define XCHAL_HAVE_PSO_CDM		0	/* core/debug/mem pwr domains */
-#define XCHAL_HAVE_PSO_FULL_RETENTION	0	/* all regs preserved on PSO */
-#define XCHAL_HAVE_THREADPTR		1	/* THREADPTR register */
-#define XCHAL_HAVE_BOOLEANS		1	/* boolean registers */
-#define XCHAL_HAVE_CP			1	/* CPENABLE reg (coprocessor) */
-#define XCHAL_CP_MAXCFG			2	/* max allowed cp id plus one */
-#define XCHAL_HAVE_MAC16		0	/* MAC16 package */
-#define XCHAL_HAVE_LX			1	/* LX core */
-#define XCHAL_HAVE_NX			0	/* NX core (starting RH) */
-
-#define XCHAL_HAVE_SUPERGATHER		0	/* SuperGather */
-
-#define XCHAL_HAVE_FUSION		0	/* Fusion*/
-#define XCHAL_HAVE_FUSION_FP		0	/* Fusion FP option */
-#define XCHAL_HAVE_FUSION_LOW_POWER	0	/* Fusion Low Power option */
-#define XCHAL_HAVE_FUSION_AES		0	/* Fusion BLE/Wifi AES-128 CCM option */
-#define XCHAL_HAVE_FUSION_CONVENC	0	/* Fusion Conv Encode option */
-#define XCHAL_HAVE_FUSION_LFSR_CRC	0	/* Fusion LFSR-CRC option */
-#define XCHAL_HAVE_FUSION_BITOPS	0	/* Fusion Bit Operations Support option */
-#define XCHAL_HAVE_FUSION_AVS		0	/* Fusion AVS option */
-#define XCHAL_HAVE_FUSION_16BIT_BASEBAND 0	/* Fusion 16-bit Baseband option */
-#define XCHAL_HAVE_FUSION_VITERBI	0	/* Fusion Viterbi option */
-#define XCHAL_HAVE_FUSION_SOFTDEMAP	0	/* Fusion Soft Bit Demap option */
-#define XCHAL_HAVE_HIFIPRO		0	/* HiFiPro Audio Engine pkg */
-#define XCHAL_HAVE_HIFI5		0	/* HiFi5 Audio Engine pkg */
-#define XCHAL_HAVE_HIFI5_NN_MAC		0	/* HiFi5 Audio Engine NN-MAC option */
-#define XCHAL_HAVE_HIFI5_VFPU		0	/* HiFi5 Audio Engine Single-Precision VFPU option */
-#define XCHAL_HAVE_HIFI5_HP_VFPU	0	/* HiFi5 Audio Engine Half-Precision VFPU option */
-#define XCHAL_HAVE_HIFI4		1	/* HiFi4 Audio Engine pkg */
-#define XCHAL_HAVE_HIFI4_VFPU		1	/* HiFi4 Audio Engine VFPU option */
-#define XCHAL_HAVE_HIFI3		1	/* HiFi3 Audio Engine pkg */
-#define XCHAL_HAVE_HIFI3_VFPU		0	/* HiFi3 Audio Engine VFPU option */
-#define XCHAL_HAVE_HIFI3Z		0	/* HiFi3Z Audio Engine pkg */
-#define XCHAL_HAVE_HIFI3Z_VFPU	0	/* HiFi3Z Audio Engine VFPU option */
-#define XCHAL_HAVE_HIFI2		0	/* HiFi2 Audio Engine pkg */
-#define XCHAL_HAVE_HIFI2EP		0	/* HiFi2EP */
-#define XCHAL_HAVE_HIFI_MINI		0
-
-
-#define XCHAL_HAVE_VECTORFPU2005	0	/* vector floating-point pkg */
-#define XCHAL_HAVE_USER_DPFPU		0       /* user DP floating-point pkg */
-#define XCHAL_HAVE_USER_SPFPU		1       /* user SP floating-point pkg */
-#define XCHAL_HAVE_FP			1	/* single prec floating point */
-#define XCHAL_HAVE_FP_DIV		1	/* FP with DIV instructions */
-#define XCHAL_HAVE_FP_RECIP		1	/* FP with RECIP instructions */
-#define XCHAL_HAVE_FP_SQRT		1	/* FP with SQRT instructions */
-#define XCHAL_HAVE_FP_RSQRT		1	/* FP with RSQRT instructions */
-#define XCHAL_HAVE_DFP			0	/* double precision FP pkg */
-#define XCHAL_HAVE_DFP_DIV		0	/* DFP with DIV instructions */
-#define XCHAL_HAVE_DFP_RECIP		0	/* DFP with RECIP instructions*/
-#define XCHAL_HAVE_DFP_SQRT		0	/* DFP with SQRT instructions */
-#define XCHAL_HAVE_DFP_RSQRT		0	/* DFP with RSQRT instructions*/
-#define XCHAL_HAVE_DFP_ACCEL		0	/* double precision FP acceleration pkg */
-#define XCHAL_HAVE_DFP_accel		XCHAL_HAVE_DFP_ACCEL	/* for backward compatibility */
-
-#define XCHAL_HAVE_DFPU_SINGLE_ONLY	0	/* DFPU Coprocessor, single precision only */
-#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE	0	/* DFPU Coprocessor, single and double precision */
-#define XCHAL_HAVE_VECTRA1		0	/* Vectra I  pkg */
-#define XCHAL_HAVE_VECTRALX		0	/* Vectra LX pkg */
-
-#define XCHAL_HAVE_FUSIONG		0    /* FusionG */
-#define XCHAL_HAVE_FUSIONG3		0    /* FusionG3 */
-#define XCHAL_HAVE_FUSIONG6		0    /* FusionG6 */
-#define XCHAL_HAVE_FUSIONG_SP_VFPU	0    /* sp_vfpu option on FusionG */
-#define XCHAL_HAVE_FUSIONG_DP_VFPU	0    /* dp_vfpu option on FusionG */
-#define XCHAL_FUSIONG_SIMD32		0    /* simd32 for FusionG */
-
-#define XCHAL_HAVE_FUSIONJ		0    /* FusionJ */
-#define XCHAL_HAVE_FUSIONJ6		0    /* FusionJ6 */
-#define XCHAL_HAVE_FUSIONJ_SP_VFPU	0    /* sp_vfpu option on FusionJ */
-#define XCHAL_HAVE_FUSIONJ_DP_VFPU	0    /* dp_vfpu option on FusionJ */
-#define XCHAL_FUSIONJ_SIMD32		0    /* simd32 for FusionJ */
-
-#define XCHAL_HAVE_PDX			0    /* PDX-LX */
-#define XCHAL_PDX_SIMD32		0    /* simd32 for PDX */
-#define XCHAL_HAVE_PDX4			0    /* PDX4-LX */
-#define XCHAL_HAVE_PDX8			0    /* PDX8-LX */
-#define XCHAL_HAVE_PDX16		0    /* PDX16-LX */
-#define XCHAL_HAVE_PDXNX 		0    /* PDX-NX */
-
-#define XCHAL_HAVE_CONNXD2		0	/* ConnX D2 pkg */
-#define XCHAL_HAVE_CONNXD2_DUALLSFLIX   0	/* ConnX D2 & Dual LoadStore Flix */
-#define XCHAL_HAVE_BALL			0
-#define XCHAL_HAVE_BALLAP		0
-#define XCHAL_HAVE_BBE16		0	/* ConnX BBE16 pkg */
-#define XCHAL_HAVE_BBE16_RSQRT		0	/* BBE16 & vector recip sqrt */
-#define XCHAL_HAVE_BBE16_VECDIV		0	/* BBE16 & vector divide */
-#define XCHAL_HAVE_BBE16_DESPREAD	0	/* BBE16 & despread */
-#define XCHAL_HAVE_CONNX_B10            0    /* ConnX B10 pkg*/
-#define XCHAL_HAVE_CONNX_B20            0    /* ConnX B20 pkg*/
-#define XCHAL_HAVE_CONNX_B_SP_VFPU      0    /* Single-precision Vector Floating-point option on ConnX B10 & B20 */
-#define XCHAL_HAVE_CONNX_B_SPX_VFPU     0    /* Single-precision Extended Vector Floating-point option on ConnX B10 & B20 */
-#define XCHAL_HAVE_CONNX_B_HPX_VFPU     0    /* Half-precision Extended Vector Floating-point option on ConnX B10 & B20 */
-#define XCHAL_HAVE_CONNX_B_32B_MAC      0    /* 32-bit vector MAC (real and complex), FIR & FFT option on ConnX B10 & B20 */
-#define XCHAL_HAVE_CONNX_B_VITERBI      0    /* Viterbi option on ConnX B10 & B20 */
-#define XCHAL_HAVE_CONNX_B_TURBO        0    /* Turbo option on ConnX B10 & B20 */
-#define XCHAL_HAVE_BBENEP		0	/* ConnX BBENEP pkgs */
-#define XCHAL_HAVE_BBENEP_SP_VFPU	0       /* sp_vfpu option on BBE-EP */
-#define XCHAL_HAVE_BSP3			0	/* ConnX BSP3 pkg */
-#define XCHAL_HAVE_BSP3_TRANSPOSE	0	/* BSP3 & transpose32x32 */
-#define XCHAL_HAVE_SSP16		0	/* ConnX SSP16 pkg */
-#define XCHAL_HAVE_SSP16_VITERBI	0	/* SSP16 & viterbi */
-#define XCHAL_HAVE_TURBO16		0	/* ConnX Turbo16 pkg */
-#define XCHAL_HAVE_BBP16		0	/* ConnX BBP16 pkg */
-#define XCHAL_HAVE_FLIX3		0	/* basic 3-way FLIX option */
-#define XCHAL_HAVE_GRIVPEP		0	/* General Release of IVPEP */
-#define XCHAL_HAVE_GRIVPEP_HISTOGRAM	0       /* Histogram option on GRIVPEP */
-
-#define XCHAL_HAVE_VISION	        0     /* Vision P5/P6 */
-#define XCHAL_VISION_SIMD16             0     /* simd16 for Vision P5/P6 */
-#define XCHAL_VISION_TYPE               0     /* Vision P5, P6, Q6 or Q7 */
-#define XCHAL_VISION_QUAD_MAC_TYPE      0     /* quad_mac option on Vision P6 */
-#define XCHAL_HAVE_VISION_HISTOGRAM     0     /* histogram option on Vision P5/P6 */
-#define XCHAL_HAVE_VISION_SP_VFPU       0     /* sp_vfpu option on Vision P5/P6/Q6/Q7 */
-#define XCHAL_HAVE_VISION_SP_VFPU_2XFMAC 0     /* sp_vfpu_2xfma option on Vision Q7 */
-#define XCHAL_HAVE_VISION_HP_VFPU       0     /* hp_vfpu option on Vision P6/Q6 */
-#define XCHAL_HAVE_VISION_HP_VFPU_2XFMAC 0     /* hp_vfpu_2xfma option on Vision Q7 */
-
-#define XCHAL_HAVE_VISIONC	        0     /* Vision C */
-
-#define XCHAL_HAVE_XNNE			0		/* XNNE */
-
-/*----------------------------------------------------------------------
-				MISC
-  ----------------------------------------------------------------------*/
-
-#define XCHAL_NUM_LOADSTORE_UNITS	2	/* load/store units */
-#define XCHAL_NUM_WRITEBUFFER_ENTRIES	32	/* size of write buffer */
-#define XCHAL_INST_FETCH_WIDTH		16	/* instr-fetch width in bytes */
-#define XCHAL_DATA_WIDTH		8	/* data width in bytes */
-#define XCHAL_DATA_PIPE_DELAY		2	/* d-side pipeline delay
-						   (1 = 5-stage, 2 = 7-stage) */
-#define XCHAL_CLOCK_GATING_GLOBAL	1	/* global clock gating */
-#define XCHAL_CLOCK_GATING_FUNCUNIT	1	/* funct. unit clock gating */
-/*  In T1050, applies to selected core load and store instructions (see ISA): */
-#define XCHAL_UNALIGNED_LOAD_EXCEPTION	1	/* unaligned loads cause exc. */
-#define XCHAL_UNALIGNED_STORE_EXCEPTION	1	/* unaligned stores cause exc.*/
-#define XCHAL_UNALIGNED_LOAD_HW		0	/* unaligned loads work in hw */
-#define XCHAL_UNALIGNED_STORE_HW	0	/* unaligned stores work in hw*/
-
-#define XCHAL_UNIFIED_LOADSTORE         0
-
-#define XCHAL_SW_VERSION		1401000	/* sw version of this header */
-#define XCHAL_SW_MINOR_VERSION		1401000	/* same, with zeroed micro and patch */
-#define XCHAL_SW_MICRO_VERSION		1401000	/* same, with zeroed patch */
-
-#define XCHAL_CORE_ID			"hifi4_8195_PROD"	/* alphanum core name
-						   (CoreID) set in the Xtensa
-						   Processor Generator */
-
-#define XCHAL_BUILD_UNIQUE_ID		0x00089932	/* 22-bit sw build ID */
-
-/*
- *  These definitions describe the hardware targeted by this software.
- */
-#define XCHAL_HW_CONFIGID0		0xC003B286	/* ConfigID hi 32 bits*/
-#define XCHAL_HW_CONFIGID1		0x28489932	/* ConfigID lo 32 bits*/
-#define XCHAL_HW_VERSION_NAME		"LX7.1.1"	/* full version name */
-#define XCHAL_HW_VERSION_MAJOR		2810	/* major ver# of targeted hw */
-#define XCHAL_HW_VERSION_MINOR		1	/* minor ver# of targeted hw */
-#define XCHAL_HW_VERSION_MICRO			/* subdot ver# of targeted hw */
-#define XCHAL_HW_VERSION		281010	/* major*100+(major<2810 ? minor : minor*10+micro) */
-#define XCHAL_HW_REL_LX7		1
-#define XCHAL_HW_REL_LX7_1		1
-#define XCHAL_HW_REL_LX7_1_1		1
-#define XCHAL_HW_CONFIGID_RELIABLE	1
-/*  If software targets a *range* of hardware versions, these are the bounds: */
-#define XCHAL_HW_MIN_VERSION_MAJOR	2810	/* major v of earliest tgt hw */
-#define XCHAL_HW_MIN_VERSION_MINOR	1	/* minor v of earliest tgt hw */
-#define XCHAL_HW_MIN_VERSION_MICRO	0	/* micro v of earliest tgt hw */
-#define XCHAL_HW_MIN_VERSION		281010	/* earliest targeted hw */
-#define XCHAL_HW_MAX_VERSION_MAJOR	2810	/* major v of latest tgt hw */
-#define XCHAL_HW_MAX_VERSION_MINOR	1	/* minor v of latest tgt hw */
-#define XCHAL_HW_MAX_VERSION_MICRO		/* micro v of latest tgt hw */
-#define XCHAL_HW_MAX_VERSION		281010	/* latest targeted hw */
-
-/*  Config is enabled for functional safety: */
-#define XCHAL_HAVE_FUNC_SAFETY		0
-
-#define XCHAL_HAVE_APB			0
-
-/*----------------------------------------------------------------------
-				CACHE
-  ----------------------------------------------------------------------*/
-
-#define XCHAL_ICACHE_LINESIZE		128	/* I-cache line size in bytes */
-#define XCHAL_DCACHE_LINESIZE		128	/* D-cache line size in bytes */
-#define XCHAL_ICACHE_LINEWIDTH		7	/* log2(I line size in bytes) */
-#define XCHAL_DCACHE_LINEWIDTH		7	/* log2(D line size in bytes) */
-
-#define XCHAL_ICACHE_SIZE		32768	/* I-cache size in bytes or 0 */
-#define XCHAL_ICACHE_SIZE_LOG2		15
-#define XCHAL_DCACHE_SIZE		131072	/* D-cache size in bytes or 0 */
-#define XCHAL_DCACHE_SIZE_LOG2		17
-
-#define XCHAL_DCACHE_IS_WRITEBACK	1	/* writeback feature */
-#define XCHAL_DCACHE_IS_COHERENT	0	/* MP coherence feature */
-
-#define XCHAL_HAVE_PREFETCH		1	/* PREFCTL register */
-#define XCHAL_HAVE_PREFETCH_L1		0	/* prefetch to L1 cache */
-#define XCHAL_PREFETCH_CASTOUT_LINES	1	/* dcache pref. castout bufsz */
-#define XCHAL_PREFETCH_ENTRIES		16	/* cache prefetch entries */
-#define XCHAL_PREFETCH_BLOCK_ENTRIES	0	/* prefetch block streams */
-#define XCHAL_HAVE_CACHE_BLOCKOPS	0	/* block prefetch for caches */
-#define XCHAL_HAVE_CME_DOWNGRADES	0
-#define XCHAL_HAVE_ICACHE_TEST		1	/* Icache test instructions */
-#define XCHAL_HAVE_DCACHE_TEST		1	/* Dcache test instructions */
-#define XCHAL_HAVE_ICACHE_DYN_WAYS	1	/* Icache dynamic way support */
-#define XCHAL_HAVE_DCACHE_DYN_WAYS	1	/* Dcache dynamic way support */
-#define XCHAL_HAVE_ICACHE_DYN_ENABLE	1	/* Icache enabled via MEMCTL */
-#define XCHAL_HAVE_DCACHE_DYN_ENABLE	1	/* Dcache enabled via MEMCTL */
-
-#define XCHAL_L1SCACHE_SIZE		         0
-#define XCHAL_L1SCACHE_SIZE_LOG2		 0
-#define XCHAL_L1SCACHE_WAYS              1
-#define XCHAL_L1SCACHE_WAYS_LOG2         0
-#define XCHAL_L1SCACHE_ACCESS_SIZE       0
-#define XCHAL_L1SCACHE_BANKS             1
-
-#define XCHAL_HAVE_L2			0	/* NX L2 cache controller */
-
-/*  This one is a form of caching, though not architecturally visible:  */
-#define XCHAL_HAVE_BRANCH_PREDICTION	0	/* branch [target] prediction */
-
-
-
-
-/****************************************************************************
-    Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
- ****************************************************************************/
-
-
-#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
-
-/*----------------------------------------------------------------------
-				CACHE
-  ----------------------------------------------------------------------*/
-
-#define XCHAL_HAVE_PIF			1	/* any outbound bus present */
-
-#define XCHAL_HAVE_AXI			1	/* AXI bus */
-#define XCHAL_HAVE_AXI_ECC		1	/* ECC on AXI bus */
-#define XCHAL_HAVE_ACELITE		0	/* ACELite bus */
-
-#define XCHAL_HAVE_PIF_WR_RESP			1	/* pif write response */
-#define XCHAL_HAVE_PIF_REQ_ATTR			1	/* pif attribute */
-
-/*  If present, cache size in bytes == (ways * 2^(linewidth + setwidth)).  */
-
-/*  Number of cache sets in log2(lines per way):  */
-#define XCHAL_ICACHE_SETWIDTH		6
-#define XCHAL_DCACHE_SETWIDTH		8
-
-/*  Cache set associativity (number of ways):  */
-#define XCHAL_ICACHE_WAYS		4
-#define XCHAL_ICACHE_WAYS_LOG2		2
-#define XCHAL_DCACHE_WAYS		4
-#define XCHAL_DCACHE_WAYS_LOG2		2
-
-/*  Cache features:  */
-#define XCHAL_ICACHE_LINE_LOCKABLE	1
-#define XCHAL_DCACHE_LINE_LOCKABLE	1
-#define XCHAL_ICACHE_ECC_PARITY		0
-#define XCHAL_DCACHE_ECC_PARITY		0
-#define XCHAL_ICACHE_ECC_WIDTH		4
-#define XCHAL_DCACHE_ECC_WIDTH		1
-
-/*  Cache access size in bytes (affects operation of SICW instruction):  */
-#define XCHAL_ICACHE_ACCESS_SIZE	16
-#define XCHAL_DCACHE_ACCESS_SIZE	8
-
-#define XCHAL_DCACHE_BANKS		2	/* number of banks */
-
-/* The number of Cache lines associated with a single cache tag */
-#define XCHAL_DCACHE_LINES_PER_TAG_LOG2	0
-
-/*  Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits):  */
-
-
-/*----------------------------------------------------------------------
-			INTERNAL I/D RAM/ROMs and XLMI
-  ----------------------------------------------------------------------*/
-#define XCHAL_NUM_INSTROM		0	/* number of core instr. ROMs */
-#define XCHAL_NUM_INSTRAM		0	/* number of core instr. RAMs */
-#define XCHAL_NUM_DATAROM		0	/* number of core data ROMs */
-#define XCHAL_NUM_DATARAM		0	/* number of core data RAMs */
-#define XCHAL_NUM_URAM			0	/* number of core unified RAMs*/
-#define XCHAL_NUM_XLMI			0	/* number of core XLMI ports */
-#define	XCHAL_HAVE_IRAMCFG		0	/* IRAMxCFG register present */
-#define	XCHAL_HAVE_DRAMCFG		0	/* DRAMxCFG register present */
-
-
-#define XCHAL_HAVE_IDMA			0
-
-
-#define XCHAL_HAVE_IMEM_LOADSTORE	1	/* can load/store to IROM/IRAM*/
-
-/*----------------------------------------------------------------------
-			INTERRUPTS and TIMERS
-  ----------------------------------------------------------------------*/
-
-#define XCHAL_HAVE_INTERRUPTS		1	/* interrupt option */
-#define XCHAL_HAVE_NMI			0	/* non-maskable interrupt */
-#define XCHAL_HAVE_CCOUNT		1	/* CCOUNT reg. (timer option) */
-#define XCHAL_NUM_TIMERS		3	/* number of CCOMPAREn regs */
-#define XCHAL_NUM_INTERRUPTS		25	/* number of interrupts */
-#define XCHAL_NUM_INTERRUPTS_LOG2	5	/* ceil(log2(NUM_INTERRUPTS)) */
-#define XCHAL_NUM_EXTINTERRUPTS		18	/* num of external interrupts */
-#define XCHAL_NUM_INTLEVELS		4	/* number of interrupt levels
-						   (not including level zero) */
-
-
-#define XCHAL_HAVE_HIGHPRI_INTERRUPTS	1   /* med/high-pri. interrupts */
-#define XCHAL_EXCM_LEVEL		2	/* level masked by PS.EXCM */
-	/* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
-
-/*  Masks of interrupts at each interrupt level:  */
-#define XCHAL_INTLEVEL1_MASK		0x00B900FF
-#define XCHAL_INTLEVEL2_MASK		0x0142FF00
-#define XCHAL_INTLEVEL3_MASK		0x00040000
-#define XCHAL_INTLEVEL4_MASK		0x00000000
-#define XCHAL_INTLEVEL5_MASK		0x00000000
-#define XCHAL_INTLEVEL6_MASK		0x00000000
-#define XCHAL_INTLEVEL7_MASK		0x00000000
-
-/*  Masks of interrupts at each range 1..n of interrupt levels:  */
-#define XCHAL_INTLEVEL1_ANDBELOW_MASK	0x00B900FF
-#define XCHAL_INTLEVEL2_ANDBELOW_MASK	0x01FBFFFF
-#define XCHAL_INTLEVEL3_ANDBELOW_MASK	0x01FFFFFF
-#define XCHAL_INTLEVEL4_ANDBELOW_MASK	0x01FFFFFF
-#define XCHAL_INTLEVEL5_ANDBELOW_MASK	0x01FFFFFF
-#define XCHAL_INTLEVEL6_ANDBELOW_MASK	0x01FFFFFF
-#define XCHAL_INTLEVEL7_ANDBELOW_MASK	0x01FFFFFF
-
-/*  Level of each interrupt:  */
-#define XCHAL_INT0_LEVEL		1
-#define XCHAL_INT1_LEVEL		1
-#define XCHAL_INT2_LEVEL		1
-#define XCHAL_INT3_LEVEL		1
-#define XCHAL_INT4_LEVEL		1
-#define XCHAL_INT5_LEVEL		1
-#define XCHAL_INT6_LEVEL		1
-#define XCHAL_INT7_LEVEL		1
-#define XCHAL_INT8_LEVEL		2
-#define XCHAL_INT9_LEVEL		2
-#define XCHAL_INT10_LEVEL		2
-#define XCHAL_INT11_LEVEL		2
-#define XCHAL_INT12_LEVEL		2
-#define XCHAL_INT13_LEVEL		2
-#define XCHAL_INT14_LEVEL		2
-#define XCHAL_INT15_LEVEL		2
-#define XCHAL_INT16_LEVEL		1
-#define XCHAL_INT17_LEVEL		2
-#define XCHAL_INT18_LEVEL		3
-#define XCHAL_INT19_LEVEL		1
-#define XCHAL_INT20_LEVEL		1
-#define XCHAL_INT21_LEVEL		1
-#define XCHAL_INT22_LEVEL		2
-#define XCHAL_INT23_LEVEL		1
-#define XCHAL_INT24_LEVEL		2
-#define XCHAL_DEBUGLEVEL		4	/* debug interrupt level */
-#define XCHAL_HAVE_DEBUG_EXTERN_INT	1	/* OCD external db interrupt */
-
-/*  Type of each interrupt:  */
-#define XCHAL_INT0_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT1_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT2_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT3_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT4_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT5_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT6_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
-#define XCHAL_INT7_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
-#define XCHAL_INT8_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT9_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT10_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT11_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT12_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT13_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT14_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
-#define XCHAL_INT15_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
-#define XCHAL_INT16_TYPE 	XTHAL_INTTYPE_TIMER
-#define XCHAL_INT17_TYPE 	XTHAL_INTTYPE_TIMER
-#define XCHAL_INT18_TYPE 	XTHAL_INTTYPE_TIMER
-#define XCHAL_INT19_TYPE 	XTHAL_INTTYPE_WRITE_ERROR
-#define XCHAL_INT20_TYPE 	XTHAL_INTTYPE_PROFILING
-#define XCHAL_INT21_TYPE 	XTHAL_INTTYPE_SOFTWARE
-#define XCHAL_INT22_TYPE 	XTHAL_INTTYPE_SOFTWARE
-#define XCHAL_INT23_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT24_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-
-/*  Masks of interrupts for each type of interrupt:  */
-#define XCHAL_INTTYPE_MASK_UNCONFIGURED	0xFE000000
-#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL	0x01803F3F
-#define XCHAL_INTTYPE_MASK_EXTERN_EDGE	0x0000C0C0
-#define XCHAL_INTTYPE_MASK_NMI		0x00000000
-#define XCHAL_INTTYPE_MASK_SOFTWARE	0x00600000
-#define XCHAL_INTTYPE_MASK_TIMER	0x00070000
-#define XCHAL_INTTYPE_MASK_WRITE_ERROR	0x00080000
-#define XCHAL_INTTYPE_MASK_DBG_REQUEST	0x00000000
-#define XCHAL_INTTYPE_MASK_BREAKIN	0x00000000
-#define XCHAL_INTTYPE_MASK_TRAX		0x00000000
-#define XCHAL_INTTYPE_MASK_PROFILING	0x00100000
-#define XCHAL_INTTYPE_MASK_IDMA_DONE	0x00000000
-#define XCHAL_INTTYPE_MASK_IDMA_ERR	0x00000000
-#define XCHAL_INTTYPE_MASK_GS_ERR	0x00000000
-#define XCHAL_INTTYPE_MASK_L2_ERR	0x00000000
-#define XCHAL_INTTYPE_MASK_L2_STATUS	0x00000000
-#define XCHAL_INTTYPE_MASK_COR_ECC_ERR	0x00000000
-
-/*  Interrupt numbers assigned to specific interrupt sources:  */
-#define XCHAL_TIMER0_INTERRUPT		16	/* CCOMPARE0 */
-#define XCHAL_TIMER1_INTERRUPT		17	/* CCOMPARE1 */
-#define XCHAL_TIMER2_INTERRUPT		18	/* CCOMPARE2 */
-#define XCHAL_TIMER3_INTERRUPT		XTHAL_TIMER_UNCONFIGURED
-#define XCHAL_WRITE_ERROR_INTERRUPT	19
-#define XCHAL_PROFILING_INTERRUPT	20
-
-/*  Interrupt numbers for levels at which only one interrupt is configured:  */
-#define XCHAL_INTLEVEL3_NUM		18
-/*  (There are many interrupts each at level(s) 1, 2.)  */
-
-
-/*
- *  External interrupt mapping.
- *  These macros describe how Xtensa processor interrupt numbers
- *  (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
- *  map to external BInterrupt<n> pins, for those interrupts
- *  configured as external (level-triggered, edge-triggered, or NMI).
- *  See the Xtensa processor databook for more details.
- */
-
-/*  Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number:  */
-#define XCHAL_EXTINT0_NUM		0	/* (intlevel 1) */
-#define XCHAL_EXTINT1_NUM		1	/* (intlevel 1) */
-#define XCHAL_EXTINT2_NUM		2	/* (intlevel 1) */
-#define XCHAL_EXTINT3_NUM		3	/* (intlevel 1) */
-#define XCHAL_EXTINT4_NUM		4	/* (intlevel 1) */
-#define XCHAL_EXTINT5_NUM		5	/* (intlevel 1) */
-#define XCHAL_EXTINT6_NUM		6	/* (intlevel 1) */
-#define XCHAL_EXTINT7_NUM		7	/* (intlevel 1) */
-#define XCHAL_EXTINT8_NUM		8	/* (intlevel 2) */
-#define XCHAL_EXTINT9_NUM		9	/* (intlevel 2) */
-#define XCHAL_EXTINT10_NUM		10	/* (intlevel 2) */
-#define XCHAL_EXTINT11_NUM		11	/* (intlevel 2) */
-#define XCHAL_EXTINT12_NUM		12	/* (intlevel 2) */
-#define XCHAL_EXTINT13_NUM		13	/* (intlevel 2) */
-#define XCHAL_EXTINT14_NUM		14	/* (intlevel 2) */
-#define XCHAL_EXTINT15_NUM		15	/* (intlevel 2) */
-#define XCHAL_EXTINT16_NUM		23	/* (intlevel 1) */
-#define XCHAL_EXTINT17_NUM		24	/* (intlevel 2) */
-/*  EXTERNAL BInterrupt pin numbers mapped to each core interrupt number:  */
-#define XCHAL_INT0_EXTNUM		0	/* (intlevel 1) */
-#define XCHAL_INT1_EXTNUM		1	/* (intlevel 1) */
-#define XCHAL_INT2_EXTNUM		2	/* (intlevel 1) */
-#define XCHAL_INT3_EXTNUM		3	/* (intlevel 1) */
-#define XCHAL_INT4_EXTNUM		4	/* (intlevel 1) */
-#define XCHAL_INT5_EXTNUM		5	/* (intlevel 1) */
-#define XCHAL_INT6_EXTNUM		6	/* (intlevel 1) */
-#define XCHAL_INT7_EXTNUM		7	/* (intlevel 1) */
-#define XCHAL_INT8_EXTNUM		8	/* (intlevel 2) */
-#define XCHAL_INT9_EXTNUM		9	/* (intlevel 2) */
-#define XCHAL_INT10_EXTNUM		10	/* (intlevel 2) */
-#define XCHAL_INT11_EXTNUM		11	/* (intlevel 2) */
-#define XCHAL_INT12_EXTNUM		12	/* (intlevel 2) */
-#define XCHAL_INT13_EXTNUM		13	/* (intlevel 2) */
-#define XCHAL_INT14_EXTNUM		14	/* (intlevel 2) */
-#define XCHAL_INT15_EXTNUM		15	/* (intlevel 2) */
-#define XCHAL_INT23_EXTNUM		16	/* (intlevel 1) */
-#define XCHAL_INT24_EXTNUM		17	/* (intlevel 2) */
-
-#define	XCHAL_HAVE_ISB			0	/* No ISB */
-#define	XCHAL_ISB_VADDR			0	/* N/A    */
-#define	XCHAL_HAVE_ITB			0	/* No ITB */
-#define	XCHAL_ITB_VADDR			0	/* N/A    */
-
-#define	XCHAL_HAVE_KSL			0	/* Kernel Stack Limit */
-#define	XCHAL_HAVE_ISL			0	/* Interrupt Stack Limit */
-#define	XCHAL_HAVE_PSL			0	/* Pageable Stack Limit */
-
-
-/*----------------------------------------------------------------------
-			EXCEPTIONS and VECTORS
-  ----------------------------------------------------------------------*/
-
-#define XCHAL_XEA_VERSION		2	/* Xtensa Exception Architecture
-						   number: 1 == XEA1 (until T1050)
-							   2 == XEA2 (T1040 onwards)
-							   3 == XEA3 (LX8/NX/SX onwards)
-							   0 == XEAX (extern) or TX */
-#define XCHAL_HAVE_XEA1			0	/* Exception Architecture 1 */
-#define XCHAL_HAVE_XEA2			1	/* Exception Architecture 2 */
-#define XCHAL_HAVE_XEA3			0	/* Exception Architecture 3 */
-#define XCHAL_HAVE_XEAX			0	/* External Exception Arch. */
-#define XCHAL_HAVE_EXCEPTIONS		1	/* exception option */
-#define XCHAL_HAVE_IMPRECISE_EXCEPTIONS	0	/* imprecise exception option */
-#define	XCHAL_EXCCAUSE_NUM		64	/* Number of exceptions */
-#define XCHAL_HAVE_HALT			0	/* halt architecture option */
-#define XCHAL_HAVE_BOOTLOADER		0	/* boot loader (for TX) */
-#define XCHAL_HAVE_MEM_ECC_PARITY	0	/* local memory ECC/parity */
-#define XCHAL_HAVE_VECTOR_SELECT	1	/* relocatable vectors */
-#define XCHAL_HAVE_VECBASE		1	/* relocatable vectors */
-#define XCHAL_VECBASE_RESET_VADDR	0x40000400  /* VECBASE reset value */
-#define XCHAL_VECBASE_RESET_PADDR	0x40000400
-#define XCHAL_RESET_VECBASE_OVERLAP	0	/* UNUSED */
-
-#define XCHAL_RESET_VECTOR0_VADDR	0x40000000
-#define XCHAL_RESET_VECTOR0_PADDR	0x40000000
-#define XCHAL_RESET_VECTOR1_VADDR	0x40000640
-#define XCHAL_RESET_VECTOR1_PADDR	0x40000640
-#define XCHAL_RESET_VECTOR_VADDR	XCHAL_RESET_VECTOR1_VADDR
-#define XCHAL_RESET_VECTOR_PADDR	XCHAL_RESET_VECTOR1_PADDR
-#define XCHAL_USER_VECOFS		0x000001FC
-#define XCHAL_USER_VECTOR_VADDR		0x400005FC
-#define XCHAL_USER_VECTOR_PADDR		0x400005FC
-#define XCHAL_KERNEL_VECOFS		0x000001DC
-#define XCHAL_KERNEL_VECTOR_VADDR	0x400005DC
-#define XCHAL_KERNEL_VECTOR_PADDR	0x400005DC
-#define XCHAL_DOUBLEEXC_VECOFS		0x0000021C
-#define XCHAL_DOUBLEEXC_VECTOR_VADDR	0x4000061C
-#define XCHAL_DOUBLEEXC_VECTOR_PADDR	0x4000061C
-#define XCHAL_WINDOW_OF4_VECOFS		0x00000000
-#define XCHAL_WINDOW_UF4_VECOFS		0x00000040
-#define XCHAL_WINDOW_OF8_VECOFS		0x00000080
-#define XCHAL_WINDOW_UF8_VECOFS		0x000000C0
-#define XCHAL_WINDOW_OF12_VECOFS	0x00000100
-#define XCHAL_WINDOW_UF12_VECOFS	0x00000140
-#define XCHAL_WINDOW_VECTORS_VADDR	0x40000400
-#define XCHAL_WINDOW_VECTORS_PADDR	0x40000400
-#define XCHAL_INTLEVEL2_VECOFS		0x0000017C
-#define XCHAL_INTLEVEL2_VECTOR_VADDR	0x4000057C
-#define XCHAL_INTLEVEL2_VECTOR_PADDR	0x4000057C
-#define XCHAL_INTLEVEL3_VECOFS		0x0000019C
-#define XCHAL_INTLEVEL3_VECTOR_VADDR	0x4000059C
-#define XCHAL_INTLEVEL3_VECTOR_PADDR	0x4000059C
-#define XCHAL_INTLEVEL4_VECOFS		0x000001BC
-#define XCHAL_INTLEVEL4_VECTOR_VADDR	0x400005BC
-#define XCHAL_INTLEVEL4_VECTOR_PADDR	0x400005BC
-#define XCHAL_DEBUG_VECOFS		XCHAL_INTLEVEL4_VECOFS
-#define XCHAL_DEBUG_VECTOR_VADDR	XCHAL_INTLEVEL4_VECTOR_VADDR
-#define XCHAL_DEBUG_VECTOR_PADDR	XCHAL_INTLEVEL4_VECTOR_PADDR
-
-
-/*----------------------------------------------------------------------
-				DEBUG MODULE
-  ----------------------------------------------------------------------*/
-
-/*  Misc  */
-#define XCHAL_HAVE_DEBUG_ERI		1	/* ERI to debug module */
-#define XCHAL_HAVE_DEBUG_APB		1	/* APB to debug module */
-#define XCHAL_HAVE_DEBUG_JTAG		1	/* JTAG to debug module */
-
-/*  On-Chip Debug (OCD)  */
-#define XCHAL_HAVE_OCD			1	/* OnChipDebug option */
-#define XCHAL_NUM_IBREAK		2	/* number of IBREAKn regs */
-#define XCHAL_NUM_DBREAK		2	/* number of DBREAKn regs */
-#define XCHAL_HAVE_OCD_DIR_ARRAY	0	/* faster OCD option (to LX4) */
-#define XCHAL_HAVE_OCD_LS32DDR		1	/* L32DDR/S32DDR (faster OCD) */
-
-/*  TRAX (in core)  */
-#define XCHAL_HAVE_TRAX			1	/* TRAX in debug module */
-#define XCHAL_TRAX_MEM_SIZE		4096	/* TRAX memory size in bytes */
-#define XCHAL_TRAX_MEM_SHAREABLE	1	/* start/end regs; ready sig. */
-#define XCHAL_TRAX_ATB_WIDTH		32	/* ATB width (bits), 0=no ATB */
-#define XCHAL_TRAX_TIME_WIDTH		0	/* timestamp bitwidth, 0=none */
-
-/*  Perf counters  */
-#define XCHAL_NUM_PERF_COUNTERS		8	/* performance counters */
-
-
-/*----------------------------------------------------------------------
-				MMU
-  ----------------------------------------------------------------------*/
-
-/*  See core-matmap.h header file for more details.  */
-
-#define XCHAL_HAVE_TLBS			0	/* inverse of HAVE_CACHEATTR */
-#define XCHAL_HAVE_SPANNING_WAY		0	/* one way maps I+D 4GB vaddr */
-#define XCHAL_HAVE_IDENTITY_MAP		1	/* vaddr == paddr always */
-#define XCHAL_HAVE_CACHEATTR		0	/* CACHEATTR register present */
-#define XCHAL_HAVE_MIMIC_CACHEATTR	0	/* region protection */
-#define XCHAL_HAVE_XLT_CACHEATTR	0	/* region prot. w/translation */
-#define XCHAL_HAVE_PTP_MMU		0	/* full MMU (with page table
-						   [autorefill] and protection)
-						   usable for an MMU-based OS */
-
-/*  If none of the above last 5 are set, it's a custom TLB configuration.  */
-
-#define XCHAL_MMU_ASID_BITS		0	/* number of bits in ASIDs */
-#define XCHAL_MMU_RINGS			1	/* number of rings (1..4) */
-#define XCHAL_MMU_RING_BITS		0	/* num of bits in RING field */
-
-/*----------------------------------------------------------------------
-				MPU
-  ----------------------------------------------------------------------*/
-#define XCHAL_HAVE_MPU			1
-#define XCHAL_MPU_ENTRIES		32
-
-#define XCHAL_MPU_ALIGN_REQ		1	/* MPU requires alignment of entries to background map */
-#define XCHAL_MPU_BACKGROUND_ENTRIES	2	/* number of entries in bg map*/
-#define XCHAL_MPU_BG_CACHEADRDIS	0xFF	/* default CACHEADRDIS for bg */
-
-#define XCHAL_MPU_ALIGN_BITS		12
-#define XCHAL_MPU_ALIGN			4096
-
-#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
-
-
-#endif /* _XTENSA_CORE_CONFIGURATION_H */
-
diff --git a/src/platform/mt8195/include/arch/xtensa/config/core-matmap.h b/src/platform/mt8195/include/arch/xtensa/config/core-matmap.h
deleted file mode 100644
index d6e9558c0eb4..000000000000
--- a/src/platform/mt8195/include/arch/xtensa/config/core-matmap.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
- * xtensa/config/core-matmap.h -- Memory access and translation mapping
- *	parameters (CHAL) of the Xtensa processor core configuration.
- *
- *  If you are using Xtensa Tools, see <xtensa/config/core.h> (which includes
- *  this file) for more details.
- *
- *  In the Xtensa processor products released to date, all parameters
- *  defined in this file are derivable (at least in theory) from
- *  information contained in the core-isa.h header file.
- *  In particular, the following core configuration parameters are relevant:
- *	XCHAL_HAVE_CACHEATTR
- *	XCHAL_HAVE_MIMIC_CACHEATTR
- *	XCHAL_HAVE_XLT_CACHEATTR
- *	XCHAL_HAVE_PTP_MMU
- *	XCHAL_ITLB_ARF_ENTRIES_LOG2
- *	XCHAL_DTLB_ARF_ENTRIES_LOG2
- *	XCHAL_DCACHE_IS_WRITEBACK
- *	XCHAL_ICACHE_SIZE		(presence of I-cache)
- *	XCHAL_DCACHE_SIZE		(presence of D-cache)
- *	XCHAL_HW_VERSION_MAJOR
- *	XCHAL_HW_VERSION_MINOR
- */
-
-/* Customer ID=16233; Build=0x89932; Copyright (c) 1999-2020 Tensilica Inc.
-
-   Permission is hereby granted, free of charge, to any person obtaining
-   a copy of this software and associated documentation files (the
-   "Software"), to deal in the Software without restriction, including
-   without limitation the rights to use, copy, modify, merge, publish,
-   distribute, sublicense, and/or sell copies of the Software, and to
-   permit persons to whom the Software is furnished to do so, subject to
-   the following conditions:
-
-   The above copyright notice and this permission notice shall be included
-   in all copies or substantial portions of the Software.
-
-   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
-
-
-#ifndef XTENSA_CONFIG_CORE_MATMAP_H
-#define XTENSA_CONFIG_CORE_MATMAP_H
-
-
-/*----------------------------------------------------------------------
-			CACHE (MEMORY ACCESS) ATTRIBUTES
-  ----------------------------------------------------------------------*/
-/*----------------------------------------------------------------------
-				MPU
-  ----------------------------------------------------------------------*/
-
-/* Mappings for legacy constants where appropriate */
-
-#define XCHAL_CA_WRITEBACK (XTHAL_MEM_WRITEBACK | XTHAL_AR_RWXrwx)
-
-#define XCHAL_CA_WRITEBACK_NOALLOC (XTHAL_MEM_WRITEBACK_NOALLOC | XTHAL_AR_RWXrwx)
-
-#define XCHAL_CA_WRITETHRU (XTHAL_MEM_WRITETHRU | XTHAL_AR_RWXrwx)
-
-#define XCHAL_CA_ILLEGAL   (XTHAL_AR_NONE   | XTHAL_MEM_DEVICE)
-#define XCHAL_CA_BYPASS    (XTHAL_AR_RWXrwx | XTHAL_MEM_DEVICE)
-#define XCHAL_CA_BYPASSBUF    (XTHAL_AR_RWXrwx | XTHAL_MEM_DEVICE | XTHAL_MEM_BUFFERABLE)
-#define XCHAL_CA_BYPASS_RX (XTHAL_AR_RX     | XTHAL_MEM_DEVICE)
-#define XCHAL_CA_BYPASS_RW (XTHAL_AR_RW     | XTHAL_MEM_DEVICE)
-#define XCHAL_CA_BYPASS_R  (XTHAL_AR_R      | XTHAL_MEM_DEVICE)
-#define XCHAL_HAVE_CA_WRITEBACK_NOALLOC 1
-
-#define XCHAL_CA_R  (XTHAL_AR_R)
-#define XCHAL_CA_RX (XTHAL_AR_RX)
-#define XCHAL_CA_RW (XTHAL_AR_RW)
-#define XCHAL_CA_RWX (XTHAL_AR_RWX)
-
-
-/*
- * Contents of MPU background map.
- * NOTE:  caller must define the XCHAL_MPU_BGMAP() macro (not defined here
- * but specified below) before expanding the XCHAL_MPU_BACKGROUND_MAP(s) macro.
- *
- * XCHAL_MPU_BGMAP(s, vaddr_start, vaddr_last, rights, memtype, x...)
- *
- *	s = passed from XCHAL_MPU_BACKGROUND_MAP(s), eg. to select how to expand
- *	vaddr_start = first byte of region (always 0 for first entry)
- *	vaddr_end = last byte of region (always 0xFFFFFFFF for last entry)
- *	rights = access rights
- *	memtype = memory type
- *	x = reserved for future use (0 until then)
- */
-/* parasoft-begin-suppress MISRA2012-RULE-20_7 "Macro use model requires s to not be in ()" */
-#define XCHAL_MPU_BACKGROUND_MAP(s) \
-	(XCHAL_MPU_BGMAP(s, 0x00000000, 0x7fffffff,  7,   6, 0) \
-	XCHAL_MPU_BGMAP(s, 0x80000000, 0xffffffff,  7,   6, 0))
-/* parasoft-end-suppress MISRA2012-RULE-20_7 "Macro use model requires s to not be in ()" */
-
-	/* end */
-
-
-
-#endif /*XTENSA_CONFIG_CORE_MATMAP_H*/
-
diff --git a/src/platform/mt8195/include/arch/xtensa/config/defs.h b/src/platform/mt8195/include/arch/xtensa/config/defs.h
deleted file mode 100644
index 23229428bb0b..000000000000
--- a/src/platform/mt8195/include/arch/xtensa/config/defs.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/* Definitions for Xtensa instructions, types, and protos. */
-
-/* Customer ID=16233; Build=0x89932; Copyright (c) 2003-2004 Tensilica Inc.
-
-   Permission is hereby granted, free of charge, to any person obtaining
-   a copy of this software and associated documentation files (the
-   "Software"), to deal in the Software without restriction, including
-   without limitation the rights to use, copy, modify, merge, publish,
-   distribute, sublicense, and/or sell copies of the Software, and to
-   permit persons to whom the Software is furnished to do so, subject to
-   the following conditions:
-
-   The above copyright notice and this permission notice shall be included
-   in all copies or substantial portions of the Software.
-
-   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
-
-/* NOTE: This file exists only for backward compatibility with T1050
-   and earlier Xtensa releases.  It includes only a subset of the
-   available header files.  */
-
-#ifndef _XTENSA_BASE_HEADER
-#define _XTENSA_BASE_HEADER
-
-#ifdef __XTENSA__
-
-#include <xtensa/tie/xt_core.h>
-#include <xtensa/tie/xt_misc.h>
-#include <xtensa/tie/xt_booleans.h>
-
-#endif /* __XTENSA__ */
-#endif /* !_XTENSA_BASE_HEADER */
diff --git a/src/platform/mt8195/include/arch/xtensa/config/specreg.h b/src/platform/mt8195/include/arch/xtensa/config/specreg.h
deleted file mode 100644
index 4961e38f895f..000000000000
--- a/src/platform/mt8195/include/arch/xtensa/config/specreg.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- * Xtensa Special Register symbolic names
- */
-
-/* $Id: /depot/rel/Homewood/ib.1/Xtensa/SWConfig/hal/specreg.h.tpp#1 $ */
-
-/* Customer ID=16233; Build=0x89932; Copyright (c) 1998-2002 Tensilica Inc.
-
-   Permission is hereby granted, free of charge, to any person obtaining
-   a copy of this software and associated documentation files (the
-   "Software"), to deal in the Software without restriction, including
-   without limitation the rights to use, copy, modify, merge, publish,
-   distribute, sublicense, and/or sell copies of the Software, and to
-   permit persons to whom the Software is furnished to do so, subject to
-   the following conditions:
-
-   The above copyright notice and this permission notice shall be included
-   in all copies or substantial portions of the Software.
-
-   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
-
-#ifndef XTENSA_SPECREG_H
-#define XTENSA_SPECREG_H
-
-/*  Include these special register bitfield definitions, for historical reasons:  */
-#include <xtensa/corebits.h>
-
-
-/*  Special registers:  */
-#define LBEG		0
-#define LEND		1
-#define LCOUNT		2
-#define SAR		3
-#define BR		4
-#define PREFCTL		40
-#define WINDOWBASE	72
-#define WINDOWSTART	73
-#define MPUENB		90
-#define ERACCESS	95
-#define IBREAKENABLE	96
-#define MEMCTL		97
-#define CACHEADRDIS	98
-#define DDR		104
-#define IBREAKA_0	128
-#define IBREAKA_1	129
-#define DBREAKA_0	144
-#define DBREAKA_1	145
-#define DBREAKC_0	160
-#define DBREAKC_1	161
-#define EPC_1		177
-#define EPC_2		178
-#define EPC_3		179
-#define EPC_4		180
-#define DEPC		192
-#define EPS_2		194
-#define EPS_3		195
-#define EPS_4		196
-#define EXCSAVE_1	209
-#define EXCSAVE_2	210
-#define EXCSAVE_3	211
-#define EXCSAVE_4	212
-#define CPENABLE	224
-#define INTERRUPT	226
-#define INTENABLE	228
-#define PS		230
-#define VECBASE		231
-#define EXCCAUSE	232
-#define DEBUGCAUSE	233
-#define CCOUNT		234
-#define PRID		235
-#define ICOUNT		236
-#define ICOUNTLEVEL	237
-#define EXCVADDR	238
-#define CCOMPARE_0	240
-#define CCOMPARE_1	241
-#define CCOMPARE_2	242
-#define MISC_REG_0	244
-#define MISC_REG_1	245
-#define MISC_REG_2	246
-#define MISC_REG_3	247
-
-
-/*  Special cases (bases of special register series):  */
-#define IBREAKA		128
-#define DBREAKA		144
-#define DBREAKC		160
-#define EPC		176
-#define EPS		192
-#define EXCSAVE		208
-#define CCOMPARE	240
-
-/*  Special names for read-only and write-only interrupt registers:  */
-#define INTREAD		226
-#define INTSET		226
-#define INTCLEAR	227
-
-#endif /* XTENSA_SPECREG_H */
-
diff --git a/src/platform/mt8195/include/arch/xtensa/config/system.h b/src/platform/mt8195/include/arch/xtensa/config/system.h
deleted file mode 100644
index aa462dbdd47b..000000000000
--- a/src/platform/mt8195/include/arch/xtensa/config/system.h
+++ /dev/null
@@ -1,249 +0,0 @@
-/*
- * xtensa/config/system.h -- HAL definitions that are dependent on SYSTEM configuration
- *
- *  NOTE: The location and contents of this file are highly subject to change.
- *
- *  Source for configuration-independent binaries (which link in a
- *  configuration-specific HAL library) must NEVER include this file.
- *  The HAL itself has historically included this file in some instances,
- *  but this is not appropriate either, because the HAL is meant to be
- *  core-specific but system independent.
- */
-
-/* Customer ID=16233; Build=0x89932; Copyright (c) 2000-2010 Tensilica Inc.
-
-   Permission is hereby granted, free of charge, to any person obtaining
-   a copy of this software and associated documentation files (the
-   "Software"), to deal in the Software without restriction, including
-   without limitation the rights to use, copy, modify, merge, publish,
-   distribute, sublicense, and/or sell copies of the Software, and to
-   permit persons to whom the Software is furnished to do so, subject to
-   the following conditions:
-
-   The above copyright notice and this permission notice shall be included
-   in all copies or substantial portions of the Software.
-
-   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
-
-
-#ifndef XTENSA_CONFIG_SYSTEM_H
-#define XTENSA_CONFIG_SYSTEM_H
-
-
-/*----------------------------------------------------------------------
-				CONFIGURED SOFTWARE OPTIONS
-  ----------------------------------------------------------------------*/
-
-#define XSHAL_USE_ABSOLUTE_LITERALS	0	/* (sw-only option, whether software uses absolute literals) */
-#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals.  */
-
-#define XSHAL_ABI			XTHAL_ABI_WINDOWED	/* (sw-only option, selected ABI) */
-/*  The above maps to one of the following constants:  */
-#define XTHAL_ABI_WINDOWED		0
-#define XTHAL_ABI_CALL0			1
-
-#define XSHAL_CLIB			XTHAL_CLIB_XCLIB	/* (sw-only option, selected C library) */
-/*  The above maps to one of the following constants:  */
-#define XTHAL_CLIB_NEWLIB		0
-#define XTHAL_CLIB_UCLIBC		1
-#define XTHAL_CLIB_XCLIB		2
-
-#define XSHAL_USE_FLOATING_POINT	1
-
-#define XSHAL_FLOATING_POINT_ABI        1
-
-/*  SW workarounds enabled for HW errata:  */
-
-/*----------------------------------------------------------------------
-				DEVICE ADDRESSES
-  ----------------------------------------------------------------------*/
-
-/*
- *  Strange place to find these, but the configuration GUI
- *  allows moving these around to account for various core
- *  configurations.  Specific boards (and their BSP software)
- *  will have specific meanings for these components.
- */
-
-/*  I/O Block areas:  */
-#define XSHAL_IOBLOCK_CACHED_VADDR	0x70000000
-#define XSHAL_IOBLOCK_CACHED_PADDR	0x70000000
-#define XSHAL_IOBLOCK_CACHED_SIZE	0x0E000000
-
-#define XSHAL_IOBLOCK_BYPASS_VADDR	0x90000000
-#define XSHAL_IOBLOCK_BYPASS_PADDR	0x90000000
-#define XSHAL_IOBLOCK_BYPASS_SIZE	0x0E000000
-
-/*  System ROM:  */
-
-/*  System RAM:  */
-#define XSHAL_RAM_VADDR		0x40000000
-#define XSHAL_RAM_PADDR		0x40000000
-#define XSHAL_RAM_VSIZE		0x80000000
-#define XSHAL_RAM_PSIZE		0x80000000
-#define XSHAL_RAM_SIZE		XSHAL_RAM_PSIZE
-/*  Largest available area (free of vectors):  */
-#define XSHAL_RAM_AVAIL_VADDR	0x40000640
-#define XSHAL_RAM_AVAIL_VSIZE	0x7FFFF9C0
-
-/*
- *  Shadow system RAM (same device as system RAM, at different address).
- *  (Emulation boards need this for the SONIC Ethernet driver
- *   when data caches are configured for writeback mode.)
- *  NOTE: on full MMU configs, this points to the BYPASS virtual address
- *  of system RAM, ie. is the same as XSHAL_RAM_* except that virtual
- *  addresses are viewed through the BYPASS static map rather than
- *  the CACHED static map.
- */
-#define XSHAL_RAM_BYPASS_VADDR		0x20000000
-#define XSHAL_RAM_BYPASS_PADDR		0x20000000
-#define XSHAL_RAM_BYPASS_PSIZE		0x20000000
-
-/*  Alternate system RAM (different device than system RAM):  */
-
-/*  Some available location in which to place devices in a simulation (eg. XTMP):  */
-#define XSHAL_SIMIO_CACHED_VADDR	0xC0000000
-#define XSHAL_SIMIO_BYPASS_VADDR	0xC0000000
-#define XSHAL_SIMIO_PADDR		0xC0000000
-#define XSHAL_SIMIO_SIZE		0x20000000
-
-
-/*----------------------------------------------------------------------
- *  For use by reference testbench exit and diagnostic routines.
- */
-#define XSHAL_MAGIC_EXIT		0xdeece000
-#define XSHAL_STL_INFO_LOCATION		0x6c
-
-/*----------------------------------------------------------------------
- *			DEVICE-ADDRESS DEPENDENT...
- *
- *  Values written to CACHEATTR special register (or its equivalent)
- *  to enable and disable caches in various modes.
- *----------------------------------------------------------------------*/
-
-/*----------------------------------------------------------------------
-			BACKWARD COMPATIBILITY ...
-  ----------------------------------------------------------------------*/
-
-/*
- *  NOTE:  the following two macros are DEPRECATED.  Use the latter
- *  board-specific macros instead, which are specially tuned for the
- *  particular target environments' memory maps.
- */
-#define XSHAL_CACHEATTR_BYPASS		XSHAL_XT2000_CACHEATTR_BYPASS	/* disable caches in bypass mode */
-#define XSHAL_CACHEATTR_DEFAULT		XSHAL_XT2000_CACHEATTR_DEFAULT	/* default setting to enable caches (no writeback!) */
-
-/*----------------------------------------------------------------------
-				GENERIC
-  ----------------------------------------------------------------------*/
-
-/*  For the following, a 512MB region is used if it contains a system (PIF) RAM,
- *  system (PIF) ROM, local memory, or XLMI.  */
-
-/*  These set any unused 512MB region to cache-BYPASS attribute:  */
-#define XSHAL_ALLVALID_CACHEATTR_WRITEBACK	0x22444422	/* enable caches in write-back mode */
-#define XSHAL_ALLVALID_CACHEATTR_WRITEALLOC	0x22111122	/* enable caches in write-allocate mode */
-#define XSHAL_ALLVALID_CACHEATTR_WRITETHRU	0x22111122	/* enable caches in write-through mode */
-#define XSHAL_ALLVALID_CACHEATTR_BYPASS		0x22222222	/* disable caches in bypass mode */
-#define XSHAL_ALLVALID_CACHEATTR_DEFAULT	XSHAL_ALLVALID_CACHEATTR_WRITEBACK	/* default setting to enable caches */
-
-/*  These set any unused 512MB region to ILLEGAL attribute:  */
-#define XSHAL_STRICT_CACHEATTR_WRITEBACK	0xFF4444FF	/* enable caches in write-back mode */
-#define XSHAL_STRICT_CACHEATTR_WRITEALLOC	0xFF1111FF	/* enable caches in write-allocate mode */
-#define XSHAL_STRICT_CACHEATTR_WRITETHRU	0xFF1111FF	/* enable caches in write-through mode */
-#define XSHAL_STRICT_CACHEATTR_BYPASS		0xFF2222FF	/* disable caches in bypass mode */
-#define XSHAL_STRICT_CACHEATTR_DEFAULT		XSHAL_STRICT_CACHEATTR_WRITEBACK	/* default setting to enable caches */
-
-/*  These set the first 512MB, if unused, to ILLEGAL attribute to help catch
- *  NULL-pointer dereference bugs; all other unused 512MB regions are set
- *  to cache-BYPASS attribute:  */
-#define XSHAL_TRAPNULL_CACHEATTR_WRITEBACK	0x2244442F	/* enable caches in write-back mode */
-#define XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC	0x2211112F	/* enable caches in write-allocate mode */
-#define XSHAL_TRAPNULL_CACHEATTR_WRITETHRU	0x2211112F	/* enable caches in write-through mode */
-#define XSHAL_TRAPNULL_CACHEATTR_BYPASS		0x2222222F	/* disable caches in bypass mode */
-#define XSHAL_TRAPNULL_CACHEATTR_DEFAULT	XSHAL_TRAPNULL_CACHEATTR_WRITEBACK	/* default setting to enable caches */
-
-/*----------------------------------------------------------------------
-			ISS (Instruction Set Simulator) SPECIFIC ...
-  ----------------------------------------------------------------------*/
-
-/*  For now, ISS defaults to the TRAPNULL settings:  */
-#define XSHAL_ISS_CACHEATTR_WRITEBACK	XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
-#define XSHAL_ISS_CACHEATTR_WRITEALLOC	XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC
-#define XSHAL_ISS_CACHEATTR_WRITETHRU	XSHAL_TRAPNULL_CACHEATTR_WRITETHRU
-#define XSHAL_ISS_CACHEATTR_BYPASS	XSHAL_TRAPNULL_CACHEATTR_BYPASS
-#define XSHAL_ISS_CACHEATTR_DEFAULT	XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
-
-#define XSHAL_ISS_PIPE_REGIONS	0
-#define XSHAL_ISS_SDRAM_REGIONS	0
-
-
-/*----------------------------------------------------------------------
-			XT2000 BOARD SPECIFIC ...
-  ----------------------------------------------------------------------*/
-
-/*  For the following, a 512MB region is used if it contains any system RAM,
- *  system ROM, local memory, XLMI, or other XT2000 board device or memory.
- *  Regions containing devices are forced to cache-BYPASS mode regardless
- *  of whether the macro is _WRITEBACK vs. _BYPASS etc.  */
-
-/*  These set any 512MB region unused on the XT2000 to ILLEGAL attribute:  */
-#define XSHAL_XT2000_CACHEATTR_WRITEBACK	0xFF42442F	/* enable caches in write-back mode */
-#define XSHAL_XT2000_CACHEATTR_WRITEALLOC	0xFF12112F	/* enable caches in write-allocate mode */
-#define XSHAL_XT2000_CACHEATTR_WRITETHRU	0xFF12112F	/* enable caches in write-through mode */
-#define XSHAL_XT2000_CACHEATTR_BYPASS		0xFF22222F	/* disable caches in bypass mode */
-#define XSHAL_XT2000_CACHEATTR_DEFAULT		XSHAL_XT2000_CACHEATTR_WRITEBACK	/* default setting to enable caches */
-
-#define XSHAL_XT2000_PIPE_REGIONS	0x00000000	/* BusInt pipeline regions */
-#define XSHAL_XT2000_SDRAM_REGIONS	0x00000014	/* BusInt SDRAM regions */
-
-
-/*----------------------------------------------------------------------
-				VECTOR INFO AND SIZES
-  ----------------------------------------------------------------------*/
-
-#define XSHAL_VECTORS_PACKED		0	/* UNUSED */
-#define XSHAL_STATIC_VECTOR_SELECT	1
-#define XSHAL_RESET_VECTOR_VADDR	0x40000640
-#define XSHAL_RESET_VECTOR_PADDR	0x40000640
-
-/*
- *  Sizes allocated to vectors by the system (memory map) configuration.
- *  These sizes are constrained by core configuration (eg. one vector's
- *  code cannot overflow into another vector) but are dependent on the
- *  system or board (or LSP) memory map configuration.
- *
- *  Whether or not each vector happens to be in a system ROM is also
- *  a system configuration matter, sometimes useful, included here also:
- */
-#define XSHAL_RESET_VECTOR_SIZE	0x000002E0
-#define XSHAL_RESET_VECTOR_ISROM	0
-#define XSHAL_USER_VECTOR_SIZE	0x0000001C
-#define XSHAL_USER_VECTOR_ISROM	0
-#define XSHAL_PROGRAMEXC_VECTOR_SIZE	XSHAL_USER_VECTOR_SIZE	/* for backward compatibility */
-#define XSHAL_USEREXC_VECTOR_SIZE	XSHAL_USER_VECTOR_SIZE	/* for backward compatibility */
-#define XSHAL_KERNEL_VECTOR_SIZE	0x0000001C
-#define XSHAL_KERNEL_VECTOR_ISROM	0
-#define XSHAL_STACKEDEXC_VECTOR_SIZE	XSHAL_KERNEL_VECTOR_SIZE	/* for backward compatibility */
-#define XSHAL_KERNELEXC_VECTOR_SIZE	XSHAL_KERNEL_VECTOR_SIZE	/* for backward compatibility */
-#define XSHAL_DOUBLEEXC_VECTOR_SIZE	0x0000001C
-#define XSHAL_DOUBLEEXC_VECTOR_ISROM	0
-#define XSHAL_WINDOW_VECTORS_SIZE	0x00000178
-#define XSHAL_WINDOW_VECTORS_ISROM	0
-#define XSHAL_INTLEVEL2_VECTOR_SIZE	0x0000001C
-#define XSHAL_INTLEVEL2_VECTOR_ISROM	0
-#define XSHAL_INTLEVEL3_VECTOR_SIZE	0x0000001C
-#define XSHAL_INTLEVEL3_VECTOR_ISROM	0
-#define XSHAL_INTLEVEL4_VECTOR_SIZE	0x0000001C
-#define XSHAL_INTLEVEL4_VECTOR_ISROM	0
-#define XSHAL_DEBUG_VECTOR_SIZE		XSHAL_INTLEVEL4_VECTOR_SIZE
-#define XSHAL_DEBUG_VECTOR_ISROM	XSHAL_INTLEVEL4_VECTOR_ISROM
-
-#endif /*XTENSA_CONFIG_SYSTEM_H*/
-
diff --git a/src/platform/mt8195/include/arch/xtensa/config/tie-asm.h b/src/platform/mt8195/include/arch/xtensa/config/tie-asm.h
deleted file mode 100644
index 5d3937e9e977..000000000000
--- a/src/platform/mt8195/include/arch/xtensa/config/tie-asm.h
+++ /dev/null
@@ -1,314 +0,0 @@
-/*
- * tie-asm.h -- compile-time HAL assembler definitions dependent on CORE & TIE
- *
- *  NOTE:  This header file is not meant to be included directly.
- */
-
-/* This header file contains assembly-language definitions (assembly
-   macros, etc.) for this specific Xtensa processor's TIE extensions
-   and options.  It is customized to this Xtensa processor configuration.
-
-   Customer ID=16233; Build=0x89932; Copyright (c) 1999-2020 Cadence Design Systems Inc.
-
-   Permission is hereby granted, free of charge, to any person obtaining
-   a copy of this software and associated documentation files (the
-   "Software"), to deal in the Software without restriction, including
-   without limitation the rights to use, copy, modify, merge, publish,
-   distribute, sublicense, and/or sell copies of the Software, and to
-   permit persons to whom the Software is furnished to do so, subject to
-   the following conditions:
-
-   The above copyright notice and this permission notice shall be included
-   in all copies or substantial portions of the Software.
-
-   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
-
-#ifndef _XTENSA_CORE_TIE_ASM_H
-#define _XTENSA_CORE_TIE_ASM_H
-
-#include <xtensa/coreasm.h>
-
-/*  Selection parameter values for save-area save/restore macros:  */
-/*  Option vs. TIE:  */
-#define XTHAL_SAS_TIE	0x0001	/* custom extension or coprocessor */
-#define XTHAL_SAS_OPT	0x0002	/* optional (and not a coprocessor) */
-#define XTHAL_SAS_ANYOT	0x0003	/* both of the above */
-/*  Whether used automatically by compiler:  */
-#define XTHAL_SAS_NOCC	0x0004	/* not used by compiler w/o special opts/code */
-#define XTHAL_SAS_CC	0x0008	/* used by compiler without special opts/code */
-#define XTHAL_SAS_ANYCC	0x000C	/* both of the above */
-/*  ABI handling across function calls:  */
-#define XTHAL_SAS_CALR	0x0010	/* caller-saved */
-#define XTHAL_SAS_CALE	0x0020	/* callee-saved */
-#define XTHAL_SAS_GLOB	0x0040	/* global across function calls (in thread) */
-#define XTHAL_SAS_ANYABI	0x0070	/* all of the above three */
-/*  Misc  */
-#define XTHAL_SAS_ALL	0xFFFF	/* include all default NCP contents */
-#define XTHAL_SAS3(optie, ccuse, abi)	(((optie) & XTHAL_SAS_ANYOT)  \
-					| ((ccuse) & XTHAL_SAS_ANYCC)  \
-					| ((abi)   & XTHAL_SAS_ANYABI))
-
-
-    /*
-      *  Macro to store all non-coprocessor (extra) custom TIE and optional state
-      *  (not including zero-overhead loop registers).
-      *  Required parameters:
-      *      ptr         Save area pointer address register (clobbered)
-      *                  (register must contain a 4 byte aligned address).
-      *      at1..at4    Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
-      *                  registers are clobbered, the remaining are unused).
-      *  Optional parameters:
-      *      continue    If macro invoked as part of a larger store sequence, set to 1
-      *                  if this is not the first in the sequence.  Defaults to 0.
-      *      ofs         Offset from start of larger sequence (from value of first ptr
-      *                  in sequence) at which to store.  Defaults to next available space
-      *                  (or 0 if <continue> is 0).
-      *      select      Select what category(ies) of registers to store, as a bitmask
-      *                  (see XTHAL_SAS_xxx constants).  Defaults to all registers.
-      *      alloc       Select what category(ies) of registers to allocate; if any
-      *                  category is selected here that is not in <select>, space for
-      *                  the corresponding registers is skipped without doing any store.
-      */
-    .macro xchal_ncp_store  ptr at1 at2 at3 at4  continue = 0 ofs = -1 select = XTHAL_SAS_ALL alloc = 0
-	xchal_sa_start	\continue, \ofs
-	/* Optional global registers used by default by the compiler: */
-	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
-	xchal_sa_align	\ptr, 0, 1016, 4, 4
-	rur.threadptr	\at1		/* threadptr option */
-	s32i	\at1, \ptr, .Lxchal_ofs_+0
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
-	.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
-	xchal_sa_align	\ptr, 0, 1016, 4, 4
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
-	.endif
-	/* Optional caller-saved registers not used by default by the compiler: */
-	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
-	xchal_sa_align	\ptr, 0, 1016, 4, 4
-	rsr.br	\at1		/* boolean option */
-	s32i	\at1, \ptr, .Lxchal_ofs_+0
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
-	.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
-	xchal_sa_align	\ptr, 0, 1016, 4, 4
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
-	.endif
-    .endm	/* xchal_ncp_store */
-
-    /*
-      *  Macro to load all non-coprocessor (extra) custom TIE and optional state
-      *  (not including zero-overhead loop registers).
-      *  Required parameters:
-      *      ptr         Save area pointer address register (clobbered)
-      *                  (register must contain a 4 byte aligned address).
-      *      at1..at4    Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
-      *                  registers are clobbered, the remaining are unused).
-      *  Optional parameters:
-      *      continue    If macro invoked as part of a larger load sequence, set to 1
-      *                  if this is not the first in the sequence.  Defaults to 0.
-      *      ofs         Offset from start of larger sequence (from value of first ptr
-      *                  in sequence) at which to load.  Defaults to next available space
-      *                  (or 0 if <continue> is 0).
-      *      select      Select what category(ies) of registers to load, as a bitmask
-      *                  (see XTHAL_SAS_xxx constants).  Defaults to all registers.
-      *      alloc       Select what category(ies) of registers to allocate; if any
-      *                  category is selected here that is not in <select>, space for
-      *                  the corresponding registers is skipped without doing any load.
-      */
-    .macro xchal_ncp_load  ptr at1 at2 at3 at4  continue = 0 ofs = -1 select = XTHAL_SAS_ALL alloc = 0
-	xchal_sa_start	\continue, \ofs
-	/* Optional global registers used by default by the compiler: */
-	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
-	xchal_sa_align	\ptr, 0, 1016, 4, 4
-	l32i	\at1, \ptr, .Lxchal_ofs_+0
-	wur.threadptr	\at1		/* threadptr option */
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
-	.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
-	xchal_sa_align	\ptr, 0, 1016, 4, 4
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
-	.endif
-	/* Optional caller-saved registers not used by default by the compiler: */
-	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
-	xchal_sa_align	\ptr, 0, 1016, 4, 4
-	l32i	\at1, \ptr, .Lxchal_ofs_+0
-	wsr.br	\at1		/* boolean option */
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
-	.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
-	xchal_sa_align	\ptr, 0, 1016, 4, 4
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
-	.endif
-    .endm	/* xchal_ncp_load */
-
-
-#define XCHAL_NCP_NUM_ATMPS	1
-
-    /*
-     *  Macro to store the state of TIE coprocessor AudioEngineLX.
-     *  Required parameters:
-     *      ptr         Save area pointer address register (clobbered)
-     *                  (register must contain a 8 byte aligned address).
-     *      at1..at4    Four temporary address registers (first XCHAL_CP1_NUM_ATMPS
-     *                  registers are clobbered, the remaining are unused).
-     *  Optional parameters are the same as for xchal_ncp_store.
-     */
-#define xchal_cp_AudioEngineLX_store	xchal_cp1_store
-    .macro	xchal_cp1_store  ptr at1 at2 at3 at4  continue = 0 ofs = -1 select = XTHAL_SAS_ALL alloc = 0
-	xchal_sa_start \continue, \ofs
-	/* Custom caller-saved registers not used by default by the compiler: */
-	.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
-	xchal_sa_align	\ptr, 0, 0, 8, 8
-	ae_s64.i	aed0, \ptr, .Lxchal_ofs_+40
-	ae_s64.i	aed1, \ptr, .Lxchal_ofs_+48
-	ae_s64.i	aed2, \ptr, .Lxchal_ofs_+56
-	addi.a	\ptr, \ptr, 64
-	ae_s64.i	aed3, \ptr, .Lxchal_ofs_+0
-	ae_s64.i	aed4, \ptr, .Lxchal_ofs_+8
-	ae_s64.i	aed5, \ptr, .Lxchal_ofs_+16
-	ae_s64.i	aed6, \ptr, .Lxchal_ofs_+24
-	ae_s64.i	aed7, \ptr, .Lxchal_ofs_+32
-	ae_s64.i	aed8, \ptr, .Lxchal_ofs_+40
-	ae_s64.i	aed9, \ptr, .Lxchal_ofs_+48
-	ae_s64.i	aed10, \ptr, .Lxchal_ofs_+56
-	addi.a	\ptr, \ptr, 64
-	ae_s64.i	aed11, \ptr, .Lxchal_ofs_+0
-	ae_s64.i	aed12, \ptr, .Lxchal_ofs_+8
-	ae_s64.i	aed13, \ptr, .Lxchal_ofs_+16
-	ae_s64.i	aed14, \ptr, .Lxchal_ofs_+24
-	ae_s64.i	aed15, \ptr, .Lxchal_ofs_+32
-	ae_movae	\at1, aep0
-	s8i	\at1, \ptr, .Lxchal_ofs_+40
-	ae_movae	\at1, aep1
-	s8i	\at1, \ptr, .Lxchal_ofs_+41
-	ae_movae	\at1, aep2
-	s8i	\at1, \ptr, .Lxchal_ofs_+42
-	ae_movae	\at1, aep3
-	s8i	\at1, \ptr, .Lxchal_ofs_+43
-	ae_salign64.i	u0, \ptr, .Lxchal_ofs_+48
-	ae_salign64.i	u1, \ptr, .Lxchal_ofs_+56
-	addi.a	\ptr, \ptr, 64
-	ae_salign64.i	u2, \ptr, .Lxchal_ofs_+0
-	ae_salign64.i	u3, \ptr, .Lxchal_ofs_+8
-	addi.a	\ptr, \ptr, -192
-	ae_movvfcrfsr	aed0		/* ureg FCR_FSR */
-	ae_s64.i	aed0, \ptr, .Lxchal_ofs_+0 + 0
-	rur.ae_ovf_sar	\at1		/* ureg 240 */
-	s32i	\at1, \ptr, .Lxchal_ofs_+8
-	rur.ae_bithead	\at1		/* ureg 241 */
-	s32i	\at1, \ptr, .Lxchal_ofs_+12
-	rur.ae_ts_fts_bu_bp	\at1		/* ureg 242 */
-	s32i	\at1, \ptr, .Lxchal_ofs_+16
-	rur.ae_cw_sd_no	\at1		/* ureg 243 */
-	s32i	\at1, \ptr, .Lxchal_ofs_+20
-	rur.ae_cbegin0	\at1		/* ureg 246 */
-	s32i	\at1, \ptr, .Lxchal_ofs_+24
-	rur.ae_cend0	\at1		/* ureg 247 */
-	s32i	\at1, \ptr, .Lxchal_ofs_+28
-	rur.ae_cbegin1	\at1		/* ureg 248 */
-	s32i	\at1, \ptr, .Lxchal_ofs_+32
-	rur.ae_cend1	\at1		/* ureg 249 */
-	s32i	\at1, \ptr, .Lxchal_ofs_+36
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 208
-	.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
-	xchal_sa_align	\ptr, 0, 0, 8, 8
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 208
-	.endif
-    .endm	/* xchal_cp1_store  */
-
-    /*
-     *  Macro to load the state of TIE coprocessor AudioEngineLX.
-     *  Required parameters:
-     *      ptr         Save area pointer address register (clobbered)
-     *                  (register must contain a 8 byte aligned address).
-     *      at1..at4    Four temporary address registers (first XCHAL_CP1_NUM_ATMPS
-     *                  registers are clobbered, the remaining are unused).
-     *  Optional parameters are the same as for xchal_ncp_load.
-     */
-#define xchal_cp_AudioEngineLX_load	xchal_cp1_load
-    .macro	xchal_cp1_load  ptr at1 at2 at3 at4  continue = 0 ofs = -1 select = XTHAL_SAS_ALL alloc = 0
-	xchal_sa_start \continue, \ofs
-	/* Custom caller-saved registers not used by default by the compiler: */
-	.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
-	xchal_sa_align	\ptr, 0, 0, 8, 8
-	ae_l64.i	aed0, \ptr, .Lxchal_ofs_+0 + 0		/* ureg FCR_FSR */
-	ae_movfcrfsrv	aed0
-	l32i	\at1, \ptr, .Lxchal_ofs_+8
-	wur.ae_ovf_sar	\at1		/* ureg 240 */
-	l32i	\at1, \ptr, .Lxchal_ofs_+12
-	wur.ae_bithead	\at1		/* ureg 241 */
-	l32i	\at1, \ptr, .Lxchal_ofs_+16
-	wur.ae_ts_fts_bu_bp	\at1		/* ureg 242 */
-	l32i	\at1, \ptr, .Lxchal_ofs_+20
-	wur.ae_cw_sd_no	\at1		/* ureg 243 */
-	l32i	\at1, \ptr, .Lxchal_ofs_+24
-	wur.ae_cbegin0	\at1		/* ureg 246 */
-	l32i	\at1, \ptr, .Lxchal_ofs_+28
-	wur.ae_cend0	\at1		/* ureg 247 */
-	l32i	\at1, \ptr, .Lxchal_ofs_+32
-	wur.ae_cbegin1	\at1		/* ureg 248 */
-	l32i	\at1, \ptr, .Lxchal_ofs_+36
-	wur.ae_cend1	\at1		/* ureg 249 */
-	ae_l64.i	aed0, \ptr, .Lxchal_ofs_+40
-	ae_l64.i	aed1, \ptr, .Lxchal_ofs_+48
-	ae_l64.i	aed2, \ptr, .Lxchal_ofs_+56
-	addi.a	\ptr, \ptr, 64
-	ae_l64.i	aed3, \ptr, .Lxchal_ofs_+0
-	ae_l64.i	aed4, \ptr, .Lxchal_ofs_+8
-	ae_l64.i	aed5, \ptr, .Lxchal_ofs_+16
-	ae_l64.i	aed6, \ptr, .Lxchal_ofs_+24
-	ae_l64.i	aed7, \ptr, .Lxchal_ofs_+32
-	ae_l64.i	aed8, \ptr, .Lxchal_ofs_+40
-	ae_l64.i	aed9, \ptr, .Lxchal_ofs_+48
-	ae_l64.i	aed10, \ptr, .Lxchal_ofs_+56
-	addi.a	\ptr, \ptr, 64
-	ae_l64.i	aed11, \ptr, .Lxchal_ofs_+0
-	ae_l64.i	aed12, \ptr, .Lxchal_ofs_+8
-	ae_l64.i	aed13, \ptr, .Lxchal_ofs_+16
-	ae_l64.i	aed14, \ptr, .Lxchal_ofs_+24
-	ae_l64.i	aed15, \ptr, .Lxchal_ofs_+32
-	addi.a	\ptr, \ptr, 40
-	l8ui	\at1, \ptr, .Lxchal_ofs_+0
-	ae_movea	aep0, \at1
-	l8ui	\at1, \ptr, .Lxchal_ofs_+1
-	ae_movea	aep1, \at1
-	l8ui	\at1, \ptr, .Lxchal_ofs_+2
-	ae_movea	aep2, \at1
-	l8ui	\at1, \ptr, .Lxchal_ofs_+3
-	ae_movea	aep3, \at1
-	addi.a	\ptr, \ptr, 8
-	ae_lalign64.i	u0, \ptr, .Lxchal_ofs_+0
-	ae_lalign64.i	u1, \ptr, .Lxchal_ofs_+8
-	ae_lalign64.i	u2, \ptr, .Lxchal_ofs_+16
-	ae_lalign64.i	u3, \ptr, .Lxchal_ofs_+24
-	.set	.Lxchal_pofs_, .Lxchal_pofs_ + 176
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 32
-	.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
-	xchal_sa_align	\ptr, 0, 0, 8, 8
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 208
-	.endif
-    .endm	/* xchal_cp1_load  */
-
-#define XCHAL_CP1_NUM_ATMPS	1
-#define XCHAL_SA_NUM_ATMPS	1
-
-	/*  Empty macros for unconfigured coprocessors:  */
-	.macro xchal_cp0_store	p a b c d continue = 0 ofs = -1 select = -1 ; .endm
-	.macro xchal_cp0_load	p a b c d continue = 0 ofs = -1 select = -1 ; .endm
-	.macro xchal_cp2_store	p a b c d continue = 0 ofs = -1 select = -1 ; .endm
-	.macro xchal_cp2_load	p a b c d continue = 0 ofs = -1 select = -1 ; .endm
-	.macro xchal_cp3_store	p a b c d continue = 0 ofs = -1 select = -1 ; .endm
-	.macro xchal_cp3_load	p a b c d continue = 0 ofs = -1 select = -1 ; .endm
-	.macro xchal_cp4_store	p a b c d continue = 0 ofs = -1 select = -1 ; .endm
-	.macro xchal_cp4_load	p a b c d continue = 0 ofs = -1 select = -1 ; .endm
-	.macro xchal_cp5_store	p a b c d continue = 0 ofs = -1 select = -1 ; .endm
-	.macro xchal_cp5_load	p a b c d continue = 0 ofs = -1 select = -1 ; .endm
-	.macro xchal_cp6_store	p a b c d continue = 0 ofs = -1 select = -1 ; .endm
-	.macro xchal_cp6_load	p a b c d continue = 0 ofs = -1 select = -1 ; .endm
-	.macro xchal_cp7_store	p a b c d continue = 0 ofs = -1 select = -1 ; .endm
-	.macro xchal_cp7_load	p a b c d continue = 0 ofs = -1 select = -1 ; .endm
-
-#endif /*_XTENSA_CORE_TIE_ASM_H*/
-
diff --git a/src/platform/mt8195/include/arch/xtensa/config/tie.h b/src/platform/mt8195/include/arch/xtensa/config/tie.h
deleted file mode 100644
index e7e8a6847e43..000000000000
--- a/src/platform/mt8195/include/arch/xtensa/config/tie.h
+++ /dev/null
@@ -1,191 +0,0 @@
-/*
- * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
- *
- *  NOTE:  This header file is not meant to be included directly.
- */
-
-/* This header file describes this specific Xtensa processor's TIE extensions
-   that extend basic Xtensa core functionality.  It is customized to this
-   Xtensa processor configuration.
-
-   Customer ID=16233; Build=0x89932; Copyright (c) 1999-2020 Cadence Design Systems Inc.
-
-   Permission is hereby granted, free of charge, to any person obtaining
-   a copy of this software and associated documentation files (the
-   "Software"), to deal in the Software without restriction, including
-   without limitation the rights to use, copy, modify, merge, publish,
-   distribute, sublicense, and/or sell copies of the Software, and to
-   permit persons to whom the Software is furnished to do so, subject to
-   the following conditions:
-
-   The above copyright notice and this permission notice shall be included
-   in all copies or substantial portions of the Software.
-
-   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
-
-#ifndef XTENSA_CORE_TIE_H
-#define XTENSA_CORE_TIE_H
-
-/* parasoft-begin-suppress ALL "This file not MISRA checked." */
-
-#define XCHAL_CP_NUM			1	/* number of coprocessors */
-#define XCHAL_CP_MAX			2	/* max CP ID + 1 (0 if none) */
-#define XCHAL_CP_MASK			0x02	/* bitmask of all CPs by ID */
-#define XCHAL_CP_PORT_MASK		0x00	/* bitmask of only port CPs */
-
-/*  Basic parameters of each coprocessor:  */
-#define XCHAL_CP1_NAME			"AudioEngineLX"
-#define XCHAL_CP1_IDENT			AudioEngineLX
-#define XCHAL_CP1_SA_SIZE		208	/* size of state save area */
-#define XCHAL_CP1_SA_ALIGN		8	/* min alignment of save area */
-#define XCHAL_CP_ID_AUDIOENGINELX   	1	/* coprocessor ID (0..7) */
-
-/*  Filler info for unassigned coprocessors, to simplify arrays etc:  */
-#define XCHAL_CP0_SA_SIZE		0
-#define XCHAL_CP0_SA_ALIGN		1
-#define XCHAL_CP2_SA_SIZE		0
-#define XCHAL_CP2_SA_ALIGN		1
-#define XCHAL_CP3_SA_SIZE		0
-#define XCHAL_CP3_SA_ALIGN		1
-#define XCHAL_CP4_SA_SIZE		0
-#define XCHAL_CP4_SA_ALIGN		1
-#define XCHAL_CP5_SA_SIZE		0
-#define XCHAL_CP5_SA_ALIGN		1
-#define XCHAL_CP6_SA_SIZE		0
-#define XCHAL_CP6_SA_ALIGN		1
-#define XCHAL_CP7_SA_SIZE		0
-#define XCHAL_CP7_SA_ALIGN		1
-
-/*  Save area for non-coprocessor optional and custom (TIE) state:  */
-#define XCHAL_NCP_SA_SIZE		8
-#define XCHAL_NCP_SA_ALIGN		4
-
-/*  Total save area for optional and custom state (NCP + CPn):  */
-#define XCHAL_TOTAL_SA_SIZE		224	/* with 16-byte align padding */
-#define XCHAL_TOTAL_SA_ALIGN		8	/* actual minimum alignment */
-
-/*
- * Detailed contents of save areas.
- * NOTE:  caller must define the XCHAL_SA_REG macro (not defined here)
- * before expanding the XCHAL_xxx_SA_LIST() macros.
- *
- * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
- *		dbnum,base,regnum,bitsz,gapsz,reset,x...)
- *
- *	s = passed from XCHAL_*_LIST(s), eg. to select how to expand
- *	ccused = set if used by compiler without special options or code
- *	abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
- *	kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
- *	opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg)
- *	name = lowercase reg name (no quotes)
- *	galign = group byte alignment (power of 2) (galign >= align)
- *	align = register byte alignment (power of 2)
- *	asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz)
- *	  (not including any pad bytes required to galign this or next reg)
- *	dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>)
- *	base = reg shortname w/o index (or sr=special, ur=TIE user reg)
- *	regnum = reg index in regfile, or special/TIE-user reg number
- *	bitsz = number of significant bits (regfile width, or ur/sr mask bits)
- *	gapsz = intervening bits, if bitsz bits not stored contiguously
- *	(padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize)
- *	reset = register reset value (or 0 if undefined at reset)
- *	x = reserved for future use (0 until then)
- *
- *  To filter out certain registers, e.g. to expand only the non-global
- *  registers used by the compiler, you can do something like this:
- *
- *  #define XCHAL_SA_REG(s,ccused,p...)	SELCC##ccused(p)
- *  #define SELCC0(p...)
- *  #define SELCC1(abikind,p...)	SELAK##abikind(p)
- *  #define SELAK0(p...)		REG(p)
- *  #define SELAK1(p...)		REG(p)
- *  #define SELAK2(p...)
- *  #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \
- *		...what you want to expand...
- */
-
-#define XCHAL_NCP_SA_NUM	2
-#define XCHAL_NCP_SA_LIST(s)	\
- (XCHAL_SA_REG(s, 1, 2, 1, 1,      threadptr, 4, 4, 4, 0x03E7,  ur, 231, 32, 0, 0, 0) \
- XCHAL_SA_REG(s, 0, 0, 0, 1,             br, 4, 4, 4, 0x0204,  sr, 4, 16, 0, 0, 0))
-
-#define XCHAL_CP0_SA_NUM	0
-#define XCHAL_CP0_SA_LIST(s)	/* empty */
-
-#define XCHAL_CP1_SA_NUM	33
-#define XCHAL_CP1_SA_LIST(s)	\
- (XCHAL_SA_REG(s, 0, 0, 1, 0,         fcr_fsr, 8, 8, 8, 0x1019,  ur, -1,  7, 0, 0, 0) \
- XCHAL_SA_REG(s, 0, 0, 1, 0,      ae_ovf_sar, 4, 4, 4, 0x03F0,  ur, 240, 15, 0, 0, 0) \
- XCHAL_SA_REG(s, 0, 0, 1, 0,      ae_bithead, 4, 4, 4, 0x03F1,  ur, 241, 32, 0, 0, 0) \
- XCHAL_SA_REG(s, 0, 0, 1, 0, ae_ts_fts_bu_bp, 4, 4, 4, 0x03F2,  ur, 242, 16, 0, 0, 0) \
- XCHAL_SA_REG(s, 0, 0, 1, 0,     ae_cw_sd_no, 4, 4, 4, 0x03F3,  ur, 243, 29, 0, 0, 0) \
- XCHAL_SA_REG(s, 0, 0, 1, 0,      ae_cbegin0, 4, 4, 4, 0x03F6,  ur, 246, 32, 0, 0, 0) \
- XCHAL_SA_REG(s, 0, 0, 1, 0,        ae_cend0, 4, 4, 4, 0x03F7,  ur, 247, 32, 0, 0, 0) \
- XCHAL_SA_REG(s, 0, 0, 1, 0,      ae_cbegin1, 4, 4, 4, 0x03F8,  ur, 248, 32, 0, 0, 0) \
- XCHAL_SA_REG(s, 0, 0, 1, 0,        ae_cend1, 4, 4, 4, 0x03F9,  ur, 249, 32, 0, 0, 0) \
- XCHAL_SA_REG(s, 0, 0, 2, 0,            aed0, 8, 8, 8, 0x1000, aed, 0, 64, 0, 0, 0) \
- XCHAL_SA_REG(s, 0, 0, 2, 0,            aed1, 8, 8, 8, 0x1001, aed, 1, 64, 0, 0, 0) \
- XCHAL_SA_REG(s, 0, 0, 2, 0,            aed2, 8, 8, 8, 0x1002, aed, 2, 64, 0, 0, 0) \
- XCHAL_SA_REG(s, 0, 0, 2, 0,            aed3, 8, 8, 8, 0x1003, aed, 3, 64, 0, 0, 0) \
- XCHAL_SA_REG(s, 0, 0, 2, 0,            aed4, 8, 8, 8, 0x1004, aed, 4, 64, 0, 0, 0) \
- XCHAL_SA_REG(s, 0, 0, 2, 0,            aed5, 8, 8, 8, 0x1005, aed, 5, 64, 0, 0, 0) \
- XCHAL_SA_REG(s, 0, 0, 2, 0,            aed6, 8, 8, 8, 0x1006, aed, 6, 64, 0, 0, 0) \
- XCHAL_SA_REG(s, 0, 0, 2, 0,            aed7, 8, 8, 8, 0x1007, aed, 7, 64, 0, 0, 0) \
- XCHAL_SA_REG(s, 0, 0, 2, 0,            aed8, 8, 8, 8, 0x1008, aed, 8, 64, 0, 0, 0) \
- XCHAL_SA_REG(s, 0, 0, 2, 0,            aed9, 8, 8, 8, 0x1009, aed, 9, 64, 0, 0, 0) \
- XCHAL_SA_REG(s, 0, 0, 2, 0,           aed10, 8, 8, 8, 0x100A, aed, 10, 64, 0, 0, 0) \
- XCHAL_SA_REG(s, 0, 0, 2, 0,           aed11, 8, 8, 8, 0x100B, aed, 11, 64, 0, 0, 0) \
- XCHAL_SA_REG(s, 0, 0, 2, 0,           aed12, 8, 8, 8, 0x100C, aed, 12, 64, 0, 0, 0) \
- XCHAL_SA_REG(s, 0, 0, 2, 0,           aed13, 8, 8, 8, 0x100D, aed, 13, 64, 0, 0, 0) \
- XCHAL_SA_REG(s, 0, 0, 2, 0,           aed14, 8, 8, 8, 0x100E, aed, 14, 64, 0, 0, 0) \
- XCHAL_SA_REG(s, 0, 0, 2, 0,           aed15, 8, 8, 8, 0x100F, aed, 15, 64, 0, 0, 0) \
- XCHAL_SA_REG(s, 0, 0, 2, 0,            aep0, 1, 1, 1, 0x1014, aep, 0,  8, 0, 0, 0) \
- XCHAL_SA_REG(s, 0, 0, 2, 0,            aep1, 1, 1, 1, 0x1015, aep, 1,  8, 0, 0, 0) \
- XCHAL_SA_REG(s, 0, 0, 2, 0,            aep2, 1, 1, 1, 0x1016, aep, 2,  8, 0, 0, 0) \
- XCHAL_SA_REG(s, 0, 0, 2, 0,            aep3, 1, 1, 1, 0x1017, aep, 3,  8, 0, 0, 0) \
- XCHAL_SA_REG(s, 0, 0, 2, 0,              u0, 8, 8, 8, 0x1010,   u, 0, 64, 0, 0, 0) \
- XCHAL_SA_REG(s, 0, 0, 2, 0,              u1, 8, 8, 8, 0x1011,   u, 1, 64, 0, 0, 0) \
- XCHAL_SA_REG(s, 0, 0, 2, 0,              u2, 8, 8, 8, 0x1012,   u, 2, 64, 0, 0, 0) \
- XCHAL_SA_REG(s, 0, 0, 2, 0,              u3, 8, 8, 8, 0x1013,   u, 3, 64, 0, 0, 0))
-
-#define XCHAL_CP2_SA_NUM	0
-#define XCHAL_CP2_SA_LIST(s)	/* empty */
-
-#define XCHAL_CP3_SA_NUM	0
-#define XCHAL_CP3_SA_LIST(s)	/* empty */
-
-#define XCHAL_CP4_SA_NUM	0
-#define XCHAL_CP4_SA_LIST(s)	/* empty */
-
-#define XCHAL_CP5_SA_NUM	0
-#define XCHAL_CP5_SA_LIST(s)	/* empty */
-
-#define XCHAL_CP6_SA_NUM	0
-#define XCHAL_CP6_SA_LIST(s)	/* empty */
-
-#define XCHAL_CP7_SA_NUM	0
-#define XCHAL_CP7_SA_LIST(s)	/* empty */
-
-/* Byte length of instruction from its first nibble (op0 field), per FLIX.  */
-/* (not available, must use XCHAL_BYTE0_FORMAT_LENGTHS for this processor) */
-/* Byte length of instruction from its first byte, per FLIX.  */
-#define XCHAL_BYTE0_FORMAT_LENGTHS	\
-	(3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 6, 11, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 6, 11,\
-	3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 6, 11,\
-	3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 6, 11, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 6, 11,\
-	3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 6, 11,\
-	3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 6, 11, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 6, 11,\
-	3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 6, 11,\
-	3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 6, 11, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 6, 11,\
-	3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 6, 11)
-
-/* parasoft-end-suppress ALL "This file not MISRA checked." */
-
-#endif /* XTENSA_CORE_TIE_H */
-
diff --git a/src/platform/mt8195/include/platform/drivers/idc.h b/src/platform/mt8195/include/platform/drivers/idc.h
deleted file mode 100644
index 7f3d5213aade..000000000000
--- a/src/platform/mt8195/include/platform/drivers/idc.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2021 MediaTek. All rights reserved.
- *
- * Author: YC Hung <yc.hung@mediatek.com>
- */
-
-#if defined(__XTOS_RTOS_IDC_H__) || defined(__ZEPHYR_RTOS_IDC_H__)
-
-#ifndef __PLATFORM_DRIVERS_IDC_H__
-#define __PLATFORM_DRIVERS_IDC_H__
-
-#include <stdint.h>
-
-struct idc_msg;
-
-static inline int idc_send_msg(struct idc_msg *msg, uint32_t mode)
-{
-	return 0;
-}
-
-static inline int idc_init(void)
-{
-	return 0;
-}
-
-#endif /* __PLATFORM_DRIVERS_IDC_H__ */
-
-#else
-
-#error "This file shouldn't be included from outside of Zephyr/XTOS's rtos/idc.h"
-
-#endif
diff --git a/src/platform/mt8195/include/platform/drivers/interrupt.h b/src/platform/mt8195/include/platform/drivers/interrupt.h
deleted file mode 100644
index 50a9ce207661..000000000000
--- a/src/platform/mt8195/include/platform/drivers/interrupt.h
+++ /dev/null
@@ -1,153 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2021 MediaTek. All rights reserved.
- *
- * Author: Hailong Fan <hailong.fan@mediatek.com>
- *         Allen-KH Cheng <allen-kh.cheng@mediatek.com>
- */
-
-#ifdef __SOF_DRIVERS_INTERRUPT_H__
-
-#ifndef __PLATFORM_DRIVERS_INTERRUPT_H__
-#define __PLATFORM_DRIVERS_INTERRUPT_H__
-
-#include <stdint.h>
-#include <platform/drivers/mt_reg_base.h>
-
-#define PLATFORM_IRQ_HW_NUM XCHAL_NUM_INTERRUPTS
-#define PLATFORM_IRQ_FIRST_CHILD PLATFORM_IRQ_HW_NUM
-#define PLATFORM_IRQ_CHILDREN 32
-
-/* IRQ numbers - wrt Tensilica DSP */
-#if CONFIG_XT_INTERRUPT_LEVEL_1
-#define IRQ_NUM_TIMER0 0
-#define IRQ_NUM_SOFTWARE0 21
-#define IRQ_NUM_EXT_LEVEL01 1
-#define IRQ_NUM_EXT_LEVEL23 23
-#define IRQ_EXT_DOMAIN0 IRQ_NUM_EXT_LEVEL01
-#define IRQ_EXT_DOMAIN1 IRQ_NUM_EXT_LEVEL23
-#define IRQ_EXT_DOMAIN0_OFFSET	4
-#define IRQ_MASK_SOFTWARE0 BIT(IRQ_NUM_SOFTWARE0)
-#define IRQ_MASK_TIMER0 BIT(IRQ_NUM_TIMER0)
-#define IRQ_MASK_GROUP16 BIT(IRQ_NUM_GROUP16)
-#endif
-
-#if CONFIG_XT_INTERRUPT_LEVEL_2
-#define IRQ_NUM_SOFTWARE1 22 /* level 2 */
-#define IRQ_NUM_EXT_LEVEL09 9 /* Level 2 */
-#define IRQ_NUM_EXT_LEVEL24 24 /* Level 2 */
-#define IRQ_MASK_SOFTWARE1 BIT(IRQ_NUM_SOFTWARE1)
-#define IRQ_MASK_GROUP17 BIT(IRQ_NUM_GROUP17)
-#endif
-
-/* platform irq information */
-#define IRQ_TYPE_EDGE_RISING 0x00000001
-#define IRQ_TYPE_EDGE_FALLING 0x00000002
-#define IRQ_TYPE_LEVEL_HIGH 0x00000004
-#define IRQ_TYPE_LEVEL_LOW 0x00000008
-
-/* int level */
-#define IRQ_INVALID 0xff
-#define IRQ_MASK 0xff
-#define IRQ_EXT_DOMAIN1_MASK 0x3FFFFFF0
-#define IRQ_EXT_DOMAIN2_MASK 0xFFFF
-#define GET_INTERRUPT_ID(n) ((n) & IRQ_MASK)
-#define LEVEL_SHFIT 8
-#define LEVEL_MASK 0xff
-#define INT_LEVEL(n) ((n) << LEVEL_SHFIT)
-#define GET_INTLEVEL(irq) (((irq) >> LEVEL_SHFIT) & LEVEL_MASK)
-#define IRQ_LEVEL0 0
-#define IRQ_LEVEL1 1
-
-/*
- * IRQ = 0xcc-dd
- * cc = int level
- * dd = irq
- * LX_MODULEX_IRQX_B	= ( (0xcc << 8 ) | 0xdd )
- * All irq dispatch to level0 default
- */
-#define INTERRUPT_ID(ID) (ID)
-
-#define L1_INT_IRQ_B (INT_LEVEL(1) | IRQ_INVALID)
-#define L23_INT_IRQ_B (INT_LEVEL(23) | IRQ_INVALID)
-#define L1_DSP_TIMER_IRQ0_B (INT_LEVEL(2) | INTERRUPT_ID(0))
-#define L1_DSP_TIMER_IRQ1_B (INT_LEVEL(3) | INTERRUPT_ID(1))
-#define L1_DSP_TIMER_IRQ2_B (INT_LEVEL(4) | INTERRUPT_ID(2))
-#define L1_DSP_TIMER_IRQ3_B (INT_LEVEL(5) | INTERRUPT_ID(3))
-
-#define LX_CQDMA_IRQ0_B (INT_LEVEL(1) | INTERRUPT_ID(4))
-#define LX_CQDMA_IRQ1_B (INT_LEVEL(1) | INTERRUPT_ID(5))
-#define LX_CQDMA_IRQ2_B (INT_LEVEL(1) | INTERRUPT_ID(6))
-#define LX_CQDMA_IRQ3_B (INT_LEVEL(1) | INTERRUPT_ID(7))
-#define LX_UART_IRQ_B (INT_LEVEL(1) | INTERRUPT_ID(8))
-#define LX_AFE_IRQ_B (INT_LEVEL(1) | INTERRUPT_ID(9))
-#define LX_MCU_IRQ_B (INT_LEVEL(1) | INTERRUPT_ID(10))
-#define LX_I2C_IRQ4_B (INT_LEVEL(1) | INTERRUPT_ID(11))
-#define LX_I2C_IRQ5_B (INT_LEVEL(1) | INTERRUPT_ID(12))
-#define LX_RSVD_IRQ1_B (INT_LEVEL(1) | INTERRUPT_ID(13))
-#define LX_RSVD_IRQ2_B (INT_LEVEL(1) | INTERRUPT_ID(14))
-#define LX_ASRC_IRQ0_B (INT_LEVEL(1) | INTERRUPT_ID(15))
-#define LX_ASRC_IRQ1_B (INT_LEVEL(1) | INTERRUPT_ID(16))
-#define LX_ASRC_IRQ2_B (INT_LEVEL(1) | INTERRUPT_ID(17))
-#define LX_ASRC_IRQ3_B (INT_LEVEL(1) | INTERRUPT_ID(18))
-#define LX_ASRC_IRQ4_B (INT_LEVEL(1) | INTERRUPT_ID(19))
-#define LX_ASRC_IRQ5_B (INT_LEVEL(1) | INTERRUPT_ID(20))
-#define LX_ASRC_IRQ6_B (INT_LEVEL(1) | INTERRUPT_ID(21))
-#define LX_ASRC_IRQ7_B (INT_LEVEL(1) | INTERRUPT_ID(22))
-#define LX_ASRC_IRQ8_B (INT_LEVEL(1) | INTERRUPT_ID(23))
-#define LX_ASRC_IRQ9_B (INT_LEVEL(1) | INTERRUPT_ID(24))
-#define LX_ASRC_IRQ10_B (INT_LEVEL(1) | INTERRUPT_ID(25))
-#define LX_ASRC_IRQ11_B (INT_LEVEL(1) | INTERRUPT_ID(26))
-#define LX_ASRC_IRQ15_IRQ12_B (INT_LEVEL(1) | INTERRUPT_ID(27))
-#define LX_SPM_IRQ_B (INT_LEVEL(1) | INTERRUPT_ID(28))
-#define LX_SCP_IRQ_B (INT_LEVEL(1) | INTERRUPT_ID(29))
-#define LX_MBOX_IRQ0_B (INT_LEVEL(23) | INTERRUPT_ID(32))
-#define LX_MBOX_IRQ1_B (INT_LEVEL(23) | INTERRUPT_ID(33))
-#define LX_MBOX_IRQ2_B (INT_LEVEL(23) | INTERRUPT_ID(34))
-#define LX_MBOX_IRQ3_B (INT_LEVEL(23) | INTERRUPT_ID(35))
-#define LX_MBOX_IRQ4_B (INT_LEVEL(23) | INTERRUPT_ID(36))
-#define LX_MISC_NNA0_IRQ0_B (INT_LEVEL(23) | INTERRUPT_ID(37))
-#define LX_MISC_NNA0_IRQ1_B (INT_LEVEL(23) | INTERRUPT_ID(38))
-#define LX_MISC_NNA0_IRQ2_B (INT_LEVEL(23) | INTERRUPT_ID(39))
-#define LX_MISC_NNA1_IRQ0_B (INT_LEVEL(23) | INTERRUPT_ID(40))
-#define LX_MISC_NNA1_IRQ1_B (INT_LEVEL(23) | INTERRUPT_ID(41))
-#define LX_MISC_NNA1_IRQ2_B (INT_LEVEL(23) | INTERRUPT_ID(42))
-#define LX_ADSP_TIMTER_IRQ0_B (INT_LEVEL(23) | INTERRUPT_ID(43))
-#define LX_ADSP_TIMTER_IRQ1_B (INT_LEVEL(23) | INTERRUPT_ID(44))
-#define LX_ADSP_TIMTER_IRQ2_B (INT_LEVEL(23) | INTERRUPT_ID(45))
-#define LX_ADSP_TIMTER_IRQ3_B (INT_LEVEL(23) | INTERRUPT_ID(46))
-#define LX_OS_TIMTER_IRQ_B (INT_LEVEL(23) | INTERRUPT_ID(47))
-
-#define MAX_IRQ_NUM 64
-#define DOMAIN1_MAX_IRQ_NUM 32
-#define MAX_INT_LEVEL 24
-#define AUDIO_IRQn LX_AFE_IRQ_B
-/*
- *      irq register information
- *      INT 23/24
- *
- */
-#define DSP_IRQ_POL MTK_DSP_RG_DSP_IRQ_POL
-#define DSP_IRQ_EN MTK_DSP_DSP_IRQ_EN
-#define DSP_IRQ_LEVEL MTK_DSP_DSP_IRQ_LEVEL
-#define DSP_IRQ_STATUS MTK_DSP_DSP_IRQ_STATUS
-
-/*
- *      irq register information
- *      INT 0~15
- *
- */
-#define RG_DSP_IRQ_POL MTK_DSP_RG_INT_POL_CTL0
-#define RG_DSP_IRQ_EN MTK_DSP_RG_INT_EN_CTL0
-#define RG_DSP_IRQ_LEVEL MTK_DSP_RG_INT_LV_CTL0
-#define RG_DSP_IRQ_STATUS MTK_DSP_RG_INT_STATUS0
-
-uint32_t mtk_get_irq_domain_id(int32_t irq);
-
-#endif /* __PLATFORM_DRIVERS_INTERRUPT_H__ */
-
-#else
-
-#error "This file shouldn't be included from outside of sof/drivers/interrupt.h"
-
-#endif /* __SOF_DRIVERS_INTERRUPT_H__ */
diff --git a/src/platform/mt8195/include/platform/drivers/mt_reg_base.h b/src/platform/mt8195/include/platform/drivers/mt_reg_base.h
deleted file mode 100644
index 0c94c06bc6e8..000000000000
--- a/src/platform/mt8195/include/platform/drivers/mt_reg_base.h
+++ /dev/null
@@ -1,141 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2021 MediaTek. All rights reserved.
- *
- * Author: YC Hung <yc.hung@mediatek.com>
- *         Allen-KH Cheng <allen-kh.cheng@mediatek.com>
- */
-
-#ifndef MT_REG_BASE_H
-#define MT_REG_BASE_H
-
-#define MTK_DSP_IRQ_BASE 0x10009000
-#define MTK_DSP_IRQ_SIZE 0x1000
-
-#define MTK_TOPCKGEN_REG_BASE 0x1001B000
-#define MTK_TOPCKGEN_REG_SIZE 0x00001000
-
-#define MTK_DSP_REG_REMAP_BASE 0x10800000
-#define MTK_DSP_REG_REMAP_SIZE 0xE000
-#define MTK_DSP_TIMER_BASE 0x10800000
-#define MTK_DSP_UART0_BASE 0x10801000
-#define MTK_DSP_REG_BASE 0x10803000 /* DSPCFG base */
-#define MTK_DSP_WDT_BASE 0x10803400
-#define MTK_DSP_OSTIMER_BASE 0x1080D000
-
-#define MTK_DSP_JTAGMUX (MTK_DSP_REG_BASE + 0x0000)
-#define MTK_DSP_ALTRESETVEC (MTK_DSP_REG_BASE + 0x0004)
-#define MTK_DSP_PDEBUGDATA (MTK_DSP_REG_BASE + 0x0008)
-#define MTK_DSP_PDEBUGBUS0 (MTK_DSP_REG_BASE + 0x000c)
-#define MTK_DSP_PDEBUGBUS1 (MTK_DSP_REG_BASE + 0x0010)
-#define MTK_DSP_PDEBUGINST (MTK_DSP_REG_BASE + 0x0014)
-#define MTK_DSP_PDEBUGLS0STAT (MTK_DSP_REG_BASE + 0x0018)
-#define MTK_DSP_PDEBUGLS1STAT (MTK_DSP_REG_BASE + 0x001c)
-#define MTK_DSP_PDEBUGPC (MTK_DSP_REG_BASE + 0x0020)
-#define MTK_DSP_RESET_SW (MTK_DSP_REG_BASE + 0x0024)
-#define MTK_DSP_PFAULTBUS (MTK_DSP_REG_BASE + 0x0028)
-#define MTK_DSP_PFAULTINFO (MTK_DSP_REG_BASE + 0x002c)
-#define MTK_DSP_GPR00 (MTK_DSP_REG_BASE + 0x0030)
-#define MTK_DSP_GPR01 (MTK_DSP_REG_BASE + 0x0034)
-#define MTK_DSP_GPR02 (MTK_DSP_REG_BASE + 0x0038)
-#define MTK_DSP_GPR03 (MTK_DSP_REG_BASE + 0x003c)
-#define MTK_DSP_GPR04 (MTK_DSP_REG_BASE + 0x0040)
-#define MTK_DSP_GPR05 (MTK_DSP_REG_BASE + 0x0044)
-#define MTK_DSP_GPR06 (MTK_DSP_REG_BASE + 0x0048)
-#define MTK_DSP_GPR07 (MTK_DSP_REG_BASE + 0x004c)
-#define MTK_DSP_GPR08 (MTK_DSP_REG_BASE + 0x0050)
-#define MTK_DSP_GPR09 (MTK_DSP_REG_BASE + 0x0054)
-#define MTK_DSP_GPR0A (MTK_DSP_REG_BASE + 0x0058)
-#define MTK_DSP_GPR0B (MTK_DSP_REG_BASE + 0x005c)
-#define MTK_DSP_GPR0C (MTK_DSP_REG_BASE + 0x0060)
-#define MTK_DSP_GPR0D (MTK_DSP_REG_BASE + 0x0064)
-#define MTK_DSP_GPR0E (MTK_DSP_REG_BASE + 0x0068)
-#define MTK_DSP_GPR0F (MTK_DSP_REG_BASE + 0x006c)
-#define MTK_DSP_GPR10 (MTK_DSP_REG_BASE + 0x0070)
-#define MTK_DSP_GPR11 (MTK_DSP_REG_BASE + 0x0074)
-#define MTK_DSP_GPR12 (MTK_DSP_REG_BASE + 0x0078)
-#define MTK_DSP_GPR13 (MTK_DSP_REG_BASE + 0x007c)
-#define MTK_DSP_GPR14 (MTK_DSP_REG_BASE + 0x0080)
-#define MTK_DSP_GPR15 (MTK_DSP_REG_BASE + 0x0084)
-#define MTK_DSP_GPR16 (MTK_DSP_REG_BASE + 0x0088)
-#define MTK_DSP_GPR17 (MTK_DSP_REG_BASE + 0x008c)
-#define MTK_DSP_GPR18 (MTK_DSP_REG_BASE + 0x0090)
-#define MTK_DSP_GPR19 (MTK_DSP_REG_BASE + 0x0094)
-#define MTK_DSP_GPR1A (MTK_DSP_REG_BASE + 0x0098)
-#define MTK_DSP_GPR1B (MTK_DSP_REG_BASE + 0x009c)
-#define MTK_DSP_GPR1C (MTK_DSP_REG_BASE + 0x00a0)
-#define MTK_DSP_GPR1D (MTK_DSP_REG_BASE + 0x00a4)
-#define MTK_DSP_GPR1E (MTK_DSP_REG_BASE + 0x00a8)
-#define MTK_DSP_GPR1F (MTK_DSP_REG_BASE + 0x00ac)
-#define MTK_DSP_TCM_OFFSET (MTK_DSP_REG_BASE + 0x00b0) /* not used */
-#define MTK_DSP_DDR_OFFSET (MTK_DSP_REG_BASE + 0x00b4) /* not used */
-#define MTK_DSP_INTFDSP (MTK_DSP_REG_BASE + 0x00d0)
-#define MTK_DSP_INTFDSP_CLR (MTK_DSP_REG_BASE + 0x00d4)
-#define MTK_DSP_SRAM_PD_SW1 (MTK_DSP_REG_BASE + 0x00d8)
-#define MTK_DSP_SRAM_PD_SW2 (MTK_DSP_REG_BASE + 0x00dc)
-#define MTK_DSP_OCD (MTK_DSP_REG_BASE + 0x00e0)
-#define MTK_DSP_RG_DSP_IRQ_POL (MTK_DSP_REG_BASE + 0x00f0)
-#define MTK_DSP_DSP_IRQ_EN (MTK_DSP_REG_BASE + 0x00f4)
-#define MTK_DSP_DSP_IRQ_LEVEL (MTK_DSP_REG_BASE + 0x00f8)
-#define MTK_DSP_DSP_IRQ_STATUS (MTK_DSP_REG_BASE + 0x00fc)
-#define MTK_DSP_RG_INT2CIRQ (MTK_DSP_REG_BASE + 0x0114)
-#define MTK_DSP_RG_INT_POL_CTL0 (MTK_DSP_REG_BASE + 0x0120)
-#define MTK_DSP_RG_INT_EN_CTL0 (MTK_DSP_REG_BASE + 0x0130)
-#define MTK_DSP_RG_INT_LV_CTL0 (MTK_DSP_REG_BASE + 0x0140)
-#define MTK_DSP_RG_INT_STATUS0 (MTK_DSP_REG_BASE + 0x0150)
-#define MTK_DSP_PDEBUGSTATUS0 (MTK_DSP_REG_BASE + 0x0200)
-#define MTK_DSP_PDEBUGSTATUS1 (MTK_DSP_REG_BASE + 0x0204)
-#define MTK_DSP_PDEBUGSTATUS2 (MTK_DSP_REG_BASE + 0x0208)
-#define MTK_DSP_PDEBUGSTATUS3 (MTK_DSP_REG_BASE + 0x020c)
-#define MTK_DSP_PDEBUGSTATUS4 (MTK_DSP_REG_BASE + 0x0210)
-#define MTK_DSP_PDEBUGSTATUS5 (MTK_DSP_REG_BASE + 0x0214)
-#define MTK_DSP_PDEBUGSTATUS6 (MTK_DSP_REG_BASE + 0x0218)
-#define MTK_DSP_PDEBUGSTATUS7 (MTK_DSP_REG_BASE + 0x021c)
-#define MTK_DSP_DSP2PSRAM_PRIORITY (MTK_DSP_REG_BASE + 0x0220) /* not used */
-#define MTK_DSP_AUDIO_DSP2SPM_INT (MTK_DSP_REG_BASE + 0x0224)
-#define MTK_DSP_AUDIO_DSP2SPM_INT_ACK (MTK_DSP_REG_BASE + 0x0228)
-#define MTK_DSP_AUDIO_DSP_DEBUG_SEL (MTK_DSP_REG_BASE + 0x022C)
-#define MTK_DSP_AUDIO_DSP_EMI_BASE_ADDR (MTK_DSP_REG_BASE + 0x02E0) /* not used */
-#define MTK_DSP_AUDIO_DSP_SHARED_IRAM (MTK_DSP_REG_BASE + 0x02E4)
-#define MTK_DSP_AUDIO_DSP_CKCTRL_P2P_CK_CON (MTK_DSP_REG_BASE + 0x02F0)
-#define MTK_DSP_RG_SEMAPHORE00 (MTK_DSP_REG_BASE + 0x0300)
-#define MTK_DSP_RG_SEMAPHORE01 (MTK_DSP_REG_BASE + 0x0304)
-#define MTK_DSP_RG_SEMAPHORE02 (MTK_DSP_REG_BASE + 0x0308)
-#define MTK_DSP_RG_SEMAPHORE03 (MTK_DSP_REG_BASE + 0x030C)
-#define MTK_DSP_RG_SEMAPHORE04 (MTK_DSP_REG_BASE + 0x0310)
-#define MTK_DSP_RG_SEMAPHORE05 (MTK_DSP_REG_BASE + 0x0314)
-#define MTK_DSP_RG_SEMAPHORE06 (MTK_DSP_REG_BASE + 0x0318)
-#define MTK_DSP_RG_SEMAPHORE07 (MTK_DSP_REG_BASE + 0x031C)
-#define MTK_DSP_RESERVED_0 (MTK_DSP_REG_BASE + 0x03F0)
-#define MTK_DSP_RESERVED_1 (MTK_DSP_REG_BASE + 0x03F4)
-
-/*MBOX registers*/
-#define MTK_DSP_MBOX_REG_BASE(x) (0x10816000 + (0x1000 * (x)))
-#define MTK_DSP_MBOX_REG_SIZE (0x5000)
-#define MTK_DSP_MBOX_IN_CMD(x) (MTK_DSP_MBOX_REG_BASE(x) + 0x0)
-#define MTK_DSP_MBOX_IN_CMD_CLR(x) (MTK_DSP_MBOX_REG_BASE(x) + 0x04)
-#define MTK_DSP_MBOX_OUT_CMD(x) (MTK_DSP_MBOX_REG_BASE(x) + 0x1c)
-#define MTK_DSP_MBOX_OUT_CMD_CLR(x) (MTK_DSP_MBOX_REG_BASE(x) + 0x20)
-#define MTK_DSP_MBOX_OUT_CMD_MSG0(x) (MTK_DSP_MBOX_REG_BASE(x) + 0x24)
-#define MTK_DSP_MBOX_OUT_CMD_MSG1(x) (MTK_DSP_MBOX_REG_BASE(x) + 0x28)
-#define MTK_DSP_MBOX_OUT_CMD_MSG2(x) (MTK_DSP_MBOX_REG_BASE(x) + 0x2c)
-#define MTK_DSP_MBOX_OUT_CMD_MSG3(x) (MTK_DSP_MBOX_REG_BASE(x) + 0x30)
-#define MTK_DSP_MBOX_OUT_CMD_MSG4(x) (MTK_DSP_MBOX_REG_BASE(x) + 0x34)
-
-/* Redefinition for using Special registers */
-#define MTK_TICKLESS_STATUS_REG (DSP_RESERVED_1)
-
-/* WDT CONFIGS */
-#define MTK_ADSP_WDT_MODE (MTK_DSP_WDT_BASE + 0x00)
-#define MTK_ADSP_WDT_LENGTH (MTK_DSP_WDT_BASE + 0x04)
-#define MTK_ADSP_WDT_RESTART (MTK_DSP_WDT_BASE + 0x08)
-#define MTK_ADSP_WDT_STA (MTK_DSP_WDT_BASE + 0x0C)
-#define MTK_ADSP_WDT_SWRST (MTK_DSP_WDT_BASE + 0x14)
-
-#define MTK_ADSP_WDT_SWRST_KEY 0x1209
-#define MTK_ADSP_WDT_RESTART_RELOAD 0x1971
-#define MTK_ADSP_WDT_LENGTH_KEY 0x8
-
-#define MTK_WDT_LENGTH_TIMEOUT(n) ((n) << 5)
-
-#endif /* MT_REG_BASE_H */
diff --git a/src/platform/mt8195/include/platform/drivers/timer.h b/src/platform/mt8195/include/platform/drivers/timer.h
deleted file mode 100644
index 025d9f138bef..000000000000
--- a/src/platform/mt8195/include/platform/drivers/timer.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- *
- * Copyright(c) 2021 MediaTek. All rights reserved.
- *
- * Author: Author: Fengquan Chen <fengquan.chen@mediatek.com>
- */
-
-#ifndef __PLATFORM_DRIVERS_TIMER_H__
-#define __PLATFORM_DRIVERS_TIMER_H__
-
-#include <rtos/bit.h>
-#include <platform/drivers/mt_reg_base.h>
-
-/*-------timer:ostimer0-------*/
-enum ostimer {
-	OSTIMER0 = 0,
-	OSTIMER1,
-	OSTIMER2,
-	OSTIMER3,
-	NR_TMRS
-};
-
-#define TIMER_CON(n) (MTK_DSP_OSTIMER_BASE + 0x0 + 0x10 * (n))
-#define TIMER_RST_VAL(n) (MTK_DSP_OSTIMER_BASE + 0x4 + 0x10 * (n))
-#define TIMER_CUR_VAL(n) (MTK_DSP_OSTIMER_BASE + 0x8 + 0x10 * (n))
-#define TIMER_IRQ_ACK(n) (MTK_DSP_OSTIMER_BASE + 0xC + 0x10 * (n))
-
-#define TIMER_ENABLE_BIT (0x1 << 0)
-#define TIMER_IRQ_ENABLE (0x1 << 0)
-#define TIMER_IRQ_STA (0x1 << 4)
-#define TIMER_IRQ_CLEAR (0x1 << 5)
-#define TIMER_CLKSRC_BIT (0x3 << 4)
-
-#define TIMER_CLK_SRC_CLK_32K 0x00
-#define TIMER_CLK_SRC_CLK_26M 0x01
-#define TIMER_CLK_SRC_BCLK 0x02
-#define TIMER_CLK_SRC_PCLK 0x03
-
-#define TIMER_CLK_SRC_SHIFT 4
-
-#define OSTIMER_CON (MTK_DSP_OSTIMER_BASE + 0x80)
-#define OSTIMER_INIT_L (MTK_DSP_OSTIMER_BASE + 0x84)
-#define OSTIMER_INIT_H (MTK_DSP_OSTIMER_BASE + 0x88)
-#define OSTIMER_CUR_L (MTK_DSP_OSTIMER_BASE + 0x8C)
-#define OSTIMER_CUR_H (MTK_DSP_OSTIMER_BASE + 0x90)
-#define OSTIMER_TVAL (MTK_DSP_OSTIMER_BASE + 0x94)
-#define OSTIMER_IRQ_ACK (MTK_DSP_OSTIMER_BASE + 0x98)
-
-/*-------platform_timer: 64 bit systimer-------*/
-#define CNTCR (MTK_DSP_TIMER_BASE + 0x00)
-#define CNTSR (MTK_DSP_TIMER_BASE + 0x04)
-#define CNTCV_L (MTK_DSP_TIMER_BASE + 0x08)
-#define CNTCV_H (MTK_DSP_TIMER_BASE + 0x0c)
-#define CNTWACR (MTK_DSP_TIMER_BASE + 0x10)
-#define CNTRACR (MTK_DSP_TIMER_BASE + 0x14)
-
-#define CNT_EN_BIT BIT(0)
-#define CLKSRC_BIT (BIT(8) | BIT(9))
-#define CLKSRC_13M_BIT BIT(8)
-#define COMP_BIT (BIT(10) | BIT(11) | BIT(12))
-#define COMP_20_25_EN_BIT (BIT(11) | BIT(12))
-
-#endif /* __PLATFORM_DRIVERS_TIMER_H__ */
diff --git a/src/platform/mt8195/include/platform/lib/clk.h b/src/platform/mt8195/include/platform/lib/clk.h
deleted file mode 100644
index 769363f4e228..000000000000
--- a/src/platform/mt8195/include/platform/lib/clk.h
+++ /dev/null
@@ -1,117 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2021 MediaTek. All rights reserved.
- *
- * Author: YC Hung <yc.hung@mediatek.com>
- */
-
-#ifdef __SOF_LIB_CLK_H__
-
-#ifndef __PLATFORM_LIB_CLK_H__
-#define __PLATFORM_LIB_CLK_H__
-
-#include <stdint.h>
-
-struct sof;
-
-#define CLK_CPU(x) (x)
-
-#define CPU_DEFAULT_IDX 4
-
-#define CLK_DEFAULT_CPU_HZ 720000000
-#define CLK_MAX_CPU_HZ 720000000
-#define CLK_SUSPEND_CPU_HZ 26000000
-
-#define NUM_CLOCKS 1
-
-#define NUM_CPU_FREQ 5
-
-void platform_clock_init(struct sof *sof);
-
-#define REG_TOPCKGEN_BASE		0x10000000
-#define REG_APMIXDSYS_BASE		0x1000C000
-#define REG_SCP_BASE			0x10700000
-
-/* dsp clock */
-#define DSPPLL_CON0		(REG_APMIXDSYS_BASE + 0x7E0)
-#define DSPPLL_CON1		(REG_APMIXDSYS_BASE + 0x7E4)
-#define DSPPLL_CON2		(REG_APMIXDSYS_BASE + 0x7E8)
-#define DSPPLL_CON3		(REG_APMIXDSYS_BASE + 0x7EC)
-#define DSPPLL_CON4		(REG_APMIXDSYS_BASE + 0x7F0)
-
-#define PLL_BASE_EN		BIT(0)
-#define PLL_PWR_ON		BIT(0)
-#define PLL_ISO_EN		BIT(1)
-#define PLL_EN			BIT(9)
-
-#define CLK_MODE		(REG_TOPCKGEN_BASE + 0x0)
-#define CLK_CFG_UPDATE0		(REG_TOPCKGEN_BASE + 0x4)
-#define CLK_CFG_UPDATE1		(REG_TOPCKGEN_BASE + 0x8)
-#define CLK_CFG_UPDATE2		(REG_TOPCKGEN_BASE + 0xC)
-#define CLK_CFG_UPDATE3		(REG_TOPCKGEN_BASE + 0x10)
-
-#define CLK_CFG_22		(REG_TOPCKGEN_BASE + 0x128)
-#define CLK_CFG_22_SET		(REG_TOPCKGEN_BASE + 0x12C)
-#define CLK_CFG_22_CLR		(REG_TOPCKGEN_BASE + 0x130)
-
-#define CLK_CFG_28		(REG_TOPCKGEN_BASE + 0x170)
-#define CLK_CFG_28_SET		(REG_TOPCKGEN_BASE + 0x174)
-#define CLK_CFG_28_CLR		(REG_TOPCKGEN_BASE + 0x178)
-
-/* CLK_CFG_UPDATE2 */
-#define CLK_UPDATE_ADSP_CK		24
-
-/* CLK_CFG_UPDATE3 */
-#define CLK_UPDATE_AUDIO_LOCAL_BUS_CK	18
-
-/* CLK_CFG_22[3:0] hf_fadsp_ck_sel clksrc. */
-#define CLK_ADSP_SEL_26M		0
-#define CLK_ADSP_SEL_26M_D_2		1
-#define CLK_ADSP_SEL_MAINPLL_D_6	2
-#define CLK_ADSP_SEL_MAINPLL_D_5_D_2	3
-#define CLK_ADSP_SEL_MAINPLL_D_4_D_4	4
-#define CLK_ADSP_SEL_UNIVPLL_D_4	5
-#define CLK_ADSP_SEL_UNIVPLL_D_6	6
-#define CLK_ADSP_SEL_ULPOSC		7
-#define CLK_ADSP_SEL_ADSPPLL		8
-#define CLK_ADSP_SEL_ADSPPLL_D_2	9
-#define CLK_ADSP_SEL_ADSPPLL_D_4	10
-#define CLK_ADSP_SEL_ADSPPLL_D_8	11
-
-/* CLK_CFG_28[19:16] hf_faudio_local_bus_ck_sel clksrc. */
-#define CLK_AUDIO_LOCAL_BUS_SEL_26M		0
-#define CLK_AUDIO_LOCAL_BUS_SEL_26M_D_2		1
-#define CLK_AUDIO_LOCAL_BUS_SEL_MAINPLL_D_4_D_4	2
-#define CLK_AUDIO_LOCAL_BUS_SEL_MAINPLL_D_7_D_2	3
-#define CLK_AUDIO_LOCAL_BUS_SEL_MAINPLL_D_4_D_2	4
-#define CLK_AUDIO_LOCAL_BUS_SEL_MAINPLL_D_5_D_2	5
-#define CLK_AUDIO_LOCAL_BUS_SEL_MAINPLL_D_6_D_2	6
-#define CLK_AUDIO_LOCAL_BUS_SEL_MAINPLL_D_7	7
-#define CLK_AUDIO_LOCAL_BUS_SEL_UNIVPLL_D_6	8
-#define CLK_AUDIO_LOCAL_BUS_SEL_ULPOSC		9
-#define CLK_AUDIO_LOCAL_BUS_SEL_ULPOSC_D_4	10
-#define CLK_AUDIO_LOCAL_BUS_SEL_ULPOSC_D_2	11
-
-#define AUDIODSP_CK_CG			(REG_SCP_BASE + 0x20180)
-#define RG_AUDIODSP_SW_CG		0
-
-enum mux_id_t {
-	MUX_CLK_ADSP_SEL = 0,
-	MUX_CLK_AUDIO_LOCAL_BUS_SEL,
-	HIFI4DSP_MUX_NUM,
-};
-
-enum DSP_HW_DSP_CLK {
-	DSP_CLK_13M = 0,
-	DSP_CLK_26M,
-	DSP_CLK_PLL_370M,
-	DSP_CLK_PLL_540M,
-	DSP_CLK_PLL_720M,
-};
-#endif /* __PLATFORM_LIB_CLK_H__ */
-
-#else
-
-#error "This file shouldn't be included from outside of sof/lib/clk.h"
-
-#endif /* __SOF_LIB_CLK_H__ */
diff --git a/src/platform/mt8195/include/platform/lib/cpu.h b/src/platform/mt8195/include/platform/lib/cpu.h
deleted file mode 100644
index e391c32a07b0..000000000000
--- a/src/platform/mt8195/include/platform/lib/cpu.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2021 MediaTek. All rights reserved.
- *
- * Author: YC Hung <yc.hung@mediatek.com>
- */
-
-#ifdef __SOF_LIB_CPU_H__
-
-#ifndef __PLATFORM_LIB_CPU_H__
-#define __PLATFORM_LIB_CPU_H__
-
-/** \brief Id of primary DSP core */
-#define PLATFORM_PRIMARY_CORE_ID 0
-
-#endif /* __PLATFORM_LIB_CPU_H__ */
-
-#else
-
-#error "This file shouldn't be included from outside of sof/lib/cpu.h"
-
-#endif /* __SOF_LIB_CPU_H__ */
diff --git a/src/platform/mt8195/include/platform/lib/dai.h b/src/platform/mt8195/include/platform/lib/dai.h
deleted file mode 100644
index 81dc98863314..000000000000
--- a/src/platform/mt8195/include/platform/lib/dai.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2021 MediaTek. All rights reserved.
- *
- * Author: YC Hung <yc.hung@mediatek.com>
- */
-
-#ifdef __SOF_LIB_DAI_H__
-
-#ifndef __PLATFORM_LIB_DAI_H__
-#define __PLATFORM_LIB_DAI_H__
-
-#endif /* __PLATFORM_LIB_DAI_H__ */
-
-#else
-
-#error "This file shouldn't be included from outside of sof/lib/dai.h"
-
-#endif /* __SOF_LIB_DAI_H__ */
diff --git a/src/platform/mt8195/include/platform/lib/dma.h b/src/platform/mt8195/include/platform/lib/dma.h
deleted file mode 100644
index 06c8ea9ef3bd..000000000000
--- a/src/platform/mt8195/include/platform/lib/dma.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2021 MediaTek. All rights reserved.
- *
- * Author: Bo Pan <bo.pan@mediatek.com>
- */
-
-#ifdef __SOF_LIB_DMA_H__
-
-#ifndef __PLATFORM_LIB_DMA_H__
-#define __PLATFORM_LIB_DMA_H__
-
-#define PLATFORM_NUM_DMACS 2
-
-/* max number of supported DMA channels */
-#define PLATFORM_MAX_DMA_CHAN 32
-
-#define DMA_ID_AFE_MEMIF 0
-#define DMA_ID_HOST 1
-
-#define dma_chan_irq(dma, chan) dma_irq(dma)
-#define dma_chan_irq_name(dma, chan) dma_irq_name(dma)
-
-#endif /* __PLATFORM_LIB_DMA_H__ */
-
-#else
-
-#error "This file shouldn't be included from outside of sof/lib/dma.h"
-
-#endif /* __SOF_LIB_DMA_H__ */
diff --git a/src/platform/mt8195/include/platform/lib/mailbox.h b/src/platform/mt8195/include/platform/lib/mailbox.h
deleted file mode 100644
index 8de30a1cb422..000000000000
--- a/src/platform/mt8195/include/platform/lib/mailbox.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2021 MediaTek. All rights reserved.
- *
- * Author: YC Hung <yc.hung@mediatek.com>
- */
-
-#ifdef __SOF_LIB_MAILBOX_H__
-
-#ifndef __PLATFORM_LIB_MAILBOX_H__
-#define __PLATFORM_LIB_MAILBOX_H__
-
-#include <sof/lib/memory.h>
-#include <stddef.h>
-#include <stdint.h>
-
-/*
- * The Window Region on MT8195 SRAM is organised like this :-
- * +--------------------------------------------------------------------------+
- * | Offset              | Region         |  Size                             |
- * +---------------------+----------------+-----------------------------------+
- * | SRAM_TRACE_BASE     | Trace Buffer   |  SRAM_TRACE_SIZE                  |
- * +---------------------+----------------+-----------------------------------+
- * | SRAM_DEBUG_BASE     | Debug data     |  SRAM_DEBUG_SIZE                  |
- * +---------------------+----------------+-----------------------------------+
- * | SRAM_INBOX_BASE     | Inbox          |  SRAM_INBOX_SIZE                  |
- * +---------------------+----------------+-----------------------------------+
- * | SRAM_OUTBOX_BASE    | Outbox         |  SRAM_MAILBOX_SIZE                |
- * +---------------------+----------------+-----------------------------------+
- */
-
-#define MAILBOX_DSPBOX_SIZE SRAM_OUTBOX_SIZE
-#define MAILBOX_DSPBOX_BASE SRAM_OUTBOX_BASE
-#define MAILBOX_DSPBOX_OFFSET SRAM_OUTBOX_OFFSET
-
-#define MAILBOX_HOSTBOX_SIZE SRAM_INBOX_SIZE
-#define MAILBOX_HOSTBOX_BASE SRAM_INBOX_BASE
-#define MAILBOX_HOSTBOX_OFFSET SRAM_INBOX_OFFSET
-
-#define MAILBOX_DEBUG_SIZE SRAM_DEBUG_SIZE
-#define MAILBOX_DEBUG_BASE SRAM_DEBUG_BASE
-#define MAILBOX_DEBUG_OFFSET SRAM_DEBUG_OFFSET
-
-#define MAILBOX_TRACE_SIZE SRAM_TRACE_SIZE
-#define MAILBOX_TRACE_BASE SRAM_TRACE_BASE
-#define MAILBOX_TRACE_OFFSET SRAM_TRACE_OFFSET
-
-#define MAILBOX_EXCEPTION_SIZE SRAM_EXCEPT_SIZE
-#define MAILBOX_EXCEPTION_BASE SRAM_EXCEPT_BASE
-#define MAILBOX_EXCEPTION_OFFSET SRAM_EXCEPT_OFFSET
-
-#define MAILBOX_STREAM_SIZE SRAM_STREAM_SIZE
-#define MAILBOX_STREAM_BASE SRAM_STREAM_BASE
-#define MAILBOX_STREAM_OFFSET SRAM_STREAM_OFFSET
-
-static inline void mailbox_sw_reg_write(size_t offset, uint32_t src)
-{
-	volatile uint32_t *ptr;
-
-	ptr = (volatile uint32_t *)(MAILBOX_DEBUG_BASE + offset);
-	*ptr = src;
-}
-
-#define ADSP_IPI_OP_REQ 0x1
-#define ADSP_IPI_OP_RSP 0x2
-void trigger_irq_to_host_req(void);
-void trigger_irq_to_host_rsp(void);
-
-#endif /* __PLATFORM_LIB_MAILBOX_H__ */
-
-#else
-
-#error "This file shouldn't be included from outside of sof/lib/mailbox.h"
-
-#endif /* __SOF_LIB_MAILBOX_H__ */
diff --git a/src/platform/mt8195/include/platform/lib/memory.h b/src/platform/mt8195/include/platform/lib/memory.h
deleted file mode 100644
index 75b8b3348e04..000000000000
--- a/src/platform/mt8195/include/platform/lib/memory.h
+++ /dev/null
@@ -1,208 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2021 MediaTek. All rights reserved.
- *
- * Author: YC Hung <yc.hung@mediatek.com>
- *         Allen-KH Cheng <allen-kh.cheng@mediatek.com>
- */
-
-#ifdef __SOF_LIB_MEMORY_H__
-
-#ifndef __PLATFORM_LIB_MEMORY_H__
-#define __PLATFORM_LIB_MEMORY_H__
-
-#include <rtos/cache.h>
-#include <xtensa/config/core-isa.h>
-
-#define BOOT_WITH_DRAM /*Use DRAM as SRAM1 for heap related*/
-/* data cache line alignment */
-#define PLATFORM_DCACHE_ALIGN sizeof(void *)
-
-/* BOOT_WITH_DRAM ONLY */
-/* physical DSP addresses */
-#define DRAM_BASE 0x60000000
-#define DRAM_AUDIO_SHARED_SIZE 0x280000
-#define DRAM_SIZE 0x1000000 /*DRAM Size : 16M , need to sync with Host side*/
-
-#define SRAM_TOTAL_SIZE 0x40000 /*256KB DSP SRAM*/
-#define VECTOR_SIZE 0x628
-
-#define SRAM0_BASE DRAM_BASE
-#define SRAM0_SIZE (DRAM_SIZE >> 1)
-#define SRAM1_BASE (DRAM_BASE + SRAM0_SIZE)
-#define SRAM1_SIZE                                                                                 \
-	(DRAM_SIZE - SRAM0_SIZE - DRAM_AUDIO_SHARED_SIZE - UUID_ENTRY_ELF_SIZE -                   \
-	 LOG_ENTRY_ELF_SIZE - EXT_MANIFEST_ELF_SIZE)
-
-#define DMA_SIZE 0x100000
-
-#define UUID_ENTRY_ELF_SIZE 0x6000
-#define LOG_ENTRY_ELF_SIZE 0x200000
-#define EXT_MANIFEST_ELF_SIZE 0x100000
-
-#define UUID_ENTRY_ELF_BASE (SRAM1_BASE + SRAM1_SIZE)
-#define LOG_ENTRY_ELF_BASE (UUID_ENTRY_ELF_BASE + UUID_ENTRY_ELF_SIZE)
-#define EXT_MANIFEST_ELF_BASE (LOG_ENTRY_ELF_BASE + LOG_ENTRY_ELF_SIZE)
-
-/*
- * The Heap and Stack on MT8195 are organised like this :-
- *
- * +--------------------------------------------------------------------------+
- * | Offset              | Region         |  Size                             |
- * +---------------------+----------------+-----------------------------------+
- * | SRAM1_BASE          | RO Data        |  SOF_DATA_SIZE                    |
- * |                     | Data           |                                   |
- * |                     | BSS            |                                   |
- * +---------------------+----------------+-----------------------------------+
- * | HEAP_SYSTEM_BASE    | System Heap    |  HEAP_SYSTEM_SIZE                 |
- * +---------------------+----------------+-----------------------------------+
- * | HEAP_RUNTIME_BASE   | Runtime Heap   |  HEAP_RUNTIME_SIZE                |
- * +---------------------+----------------+-----------------------------------+
- * | HEAP_BUFFER_BASE    | Module Buffers |  HEAP_BUFFER_SIZE                 |
- * +---------------------+----------------+-----------------------------------+
- * | SOF_STACK_END       | Stack          |  SOF_STACK_SIZE                   |
- * +---------------------+----------------+-----------------------------------+
- * | SOF_STACK_BASE      |                |                                   |
- * +---------------------+----------------+-----------------------------------+
- */
-
-/* Mailbox configuration */
-#define SRAM_OUTBOX_BASE SRAM1_BASE
-#define SRAM_OUTBOX_SIZE 0x1000
-#define SRAM_OUTBOX_OFFSET 0
-
-#define SRAM_INBOX_BASE (SRAM_OUTBOX_BASE + SRAM_OUTBOX_SIZE)
-#define SRAM_INBOX_SIZE 0x1000
-#define SRAM_INBOX_OFFSET SRAM_OUTBOX_SIZE
-
-#define SRAM_DEBUG_BASE (SRAM_INBOX_BASE + SRAM_INBOX_SIZE)
-#define SRAM_DEBUG_SIZE 0x800
-#define SRAM_DEBUG_OFFSET (SRAM_INBOX_OFFSET + SRAM_INBOX_SIZE)
-
-#define SRAM_EXCEPT_BASE (SRAM_DEBUG_BASE + SRAM_DEBUG_SIZE)
-#define SRAM_EXCEPT_SIZE 0x800
-#define SRAM_EXCEPT_OFFSET (SRAM_DEBUG_OFFSET + SRAM_DEBUG_SIZE)
-
-#define SRAM_STREAM_BASE (SRAM_EXCEPT_BASE + SRAM_EXCEPT_SIZE)
-#define SRAM_STREAM_SIZE 0x1000
-#define SRAM_STREAM_OFFSET (SRAM_EXCEPT_OFFSET + SRAM_EXCEPT_SIZE)
-
-#define SRAM_TRACE_BASE (SRAM_STREAM_BASE + SRAM_STREAM_SIZE)
-#define SRAM_TRACE_SIZE 0x1000
-#define SRAM_TRACE_OFFSET (SRAM_STREAM_OFFSET + SRAM_STREAM_SIZE)
-
-/*4K + 4K +2K + 2K + 4K + 4K = 20KB*/
-#define SOF_MAILBOX_SIZE                                                                           \
-	(SRAM_INBOX_SIZE + SRAM_OUTBOX_SIZE + SRAM_DEBUG_SIZE + SRAM_EXCEPT_SIZE +                 \
-	 SRAM_STREAM_SIZE + SRAM_TRACE_SIZE)
-
-/* Heap section sizes for module pool */
-#define HEAP_RT_COUNT8 0
-#define HEAP_RT_COUNT16 48
-#define HEAP_RT_COUNT32 48
-#define HEAP_RT_COUNT64 32
-#define HEAP_RT_COUNT128 32
-#define HEAP_RT_COUNT256 32
-#define HEAP_RT_COUNT512 32
-#define HEAP_RT_COUNT1024 4
-#define HEAP_RT_COUNT2048 2
-#define HEAP_RT_COUNT4096 2
-
-/* Heap section sizes for system runtime heap */
-#define HEAP_SYS_RT_COUNT64 128
-#define HEAP_SYS_RT_COUNT512 16
-#define HEAP_SYS_RT_COUNT1024 8
-
-/* Heap configuration */
-
-#define HEAP_SYSTEM_BASE (SRAM1_BASE + SOF_MAILBOX_SIZE)
-#define HEAP_SYSTEM_SIZE 0x6000
-
-#define HEAP_SYSTEM_0_BASE HEAP_SYSTEM_BASE
-
-#define HEAP_SYS_RUNTIME_BASE (HEAP_SYSTEM_BASE + HEAP_SYSTEM_SIZE)
-/*24KB*/
-#define HEAP_SYS_RUNTIME_SIZE                                                                      \
-	(HEAP_SYS_RT_COUNT64 * 64 + HEAP_SYS_RT_COUNT512 * 512 + HEAP_SYS_RT_COUNT1024 * 1024)
-
-#define HEAP_RUNTIME_BASE (HEAP_SYS_RUNTIME_BASE + HEAP_SYS_RUNTIME_SIZE)
-/*48*(16 +32) + 32*(64 128+256) + 4*(512+1024) + 1*2048 = 24832 = 24.25KB*/
-#define HEAP_RUNTIME_SIZE                                                                          \
-	(HEAP_RT_COUNT8 * 8 + HEAP_RT_COUNT16 * 16 + HEAP_RT_COUNT32 * 32 + HEAP_RT_COUNT64 * 64 + \
-	 HEAP_RT_COUNT128 * 128 + HEAP_RT_COUNT256 * 256 + HEAP_RT_COUNT512 * 512 +                \
-	 HEAP_RT_COUNT1024 * 1024 + HEAP_RT_COUNT2048 * 2048 + HEAP_RT_COUNT4096 * 4096)
-
-#define HEAP_BUFFER_BASE (HEAP_RUNTIME_BASE + HEAP_RUNTIME_SIZE)
-#define HEAP_BUFFER_SIZE                                                                           \
-	(SRAM1_SIZE - SOF_MAILBOX_SIZE - HEAP_RUNTIME_SIZE - SOF_STACK_TOTAL_SIZE -                \
-	 HEAP_SYS_RUNTIME_SIZE - HEAP_SYSTEM_SIZE)
-
-#define HEAP_BUFFER_BLOCK_SIZE 0x100
-#define HEAP_BUFFER_COUNT (HEAP_BUFFER_SIZE / HEAP_BUFFER_BLOCK_SIZE)
-
-#define PLATFORM_HEAP_SYSTEM 1 /* one per core */
-#define PLATFORM_HEAP_SYSTEM_RUNTIME 1 /* one per core */
-#define PLATFORM_HEAP_RUNTIME 1
-#define PLATFORM_HEAP_BUFFER 1
-
-/* Stack configuration */
-#define SOF_STACK_SIZE 0x8000
-#define SOF_STACK_TOTAL_SIZE SOF_STACK_SIZE /*4KB*/
-#define SOF_STACK_BASE (SRAM1_BASE + SRAM1_SIZE)
-#define SOF_STACK_END (SOF_STACK_BASE - SOF_STACK_TOTAL_SIZE)
-
-/* Vector and literal sizes - not in core-isa.h */
-#define SOF_MEM_VECT_LIT_SIZE 0x4
-#define SOF_MEM_VECT_TEXT_SIZE 0x1c
-#define SOF_MEM_VECT_SIZE (SOF_MEM_VECT_TEXT_SIZE + SOF_MEM_VECT_LIT_SIZE)
-
-#define SOF_MEM_RESET_TEXT_SIZE 0x2e0
-#define SOF_MEM_RESET_LIT_SIZE 0x120
-#define SOF_MEM_VECBASE_LIT_SIZE 0x178
-
-#define SOF_MEM_RO_SIZE 0x8
-
-#define HEAP_BUF_ALIGNMENT DCACHE_LINE_SIZE
-
-/** \brief EDF task's default stack size in bytes. */
-#ifdef CONFIG_COMP_GOOGLE_RTC_AUDIO_PROCESSING
-#define PLATFORM_TASK_DEFAULT_STACK_SIZE (12 * 1024)
-#else
-#define PLATFORM_TASK_DEFAULT_STACK_SIZE 3072
-#endif
-
-#if !defined(__ASSEMBLER__) && !defined(LINKER)
-
-struct sof;
-
-void platform_init_memmap(struct sof *sof);
-
-#define uncache_to_cache(address) address
-#define cache_to_uncache(address) address
-#define cache_to_uncache_init(address) address
-#define is_uncached(address) 0
-
-/**
- * \brief Function for keeping shared data synchronized.
- * It's used after usage of data shared by different cores.
- * Such data is dynamically allocated with SOF_MEM_FLAG_SHARED
- * flag. Does nothing, since mt8195 doesn't support SMP.
- */
-
-static inline void *platform_rfree_prepare(void *ptr)
-{
-	return ptr;
-}
-
-#endif
-
-#define host_to_local(addr) (addr)
-#define local_to_host(addr) (addr)
-
-#endif /* __PLATFORM_LIB_MEMORY_H__ */
-
-#else
-
-#error "This file shouldn't be included from outside of sof/lib/memory.h"
-
-#endif /* __SOF_LIB_MEMORY_H__ */
diff --git a/src/platform/mt8195/include/platform/lib/pm_runtime.h b/src/platform/mt8195/include/platform/lib/pm_runtime.h
deleted file mode 100644
index ee7f32e7a442..000000000000
--- a/src/platform/mt8195/include/platform/lib/pm_runtime.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2021 MediaTek. All rights reserved.
- *
- * Author: YC Hung <yc.hung@mediatek.com>
- */
-
-#ifdef __SOF_LIB_PM_RUNTIME_H__
-
-#ifndef __PLATFORM_LIB_PM_RUNTIME_H__
-#define __PLATFORM_LIB_PM_RUNTIME_H__
-
-#include <stdint.h>
-
-struct pm_runtime_data;
-
-/**
- * \brief Initializes platform specific runtime power management.
- * \param[in,out] prd Runtime power management data.
- */
-static inline void platform_pm_runtime_init(struct pm_runtime_data *prd)
-{
-}
-
-/**
- * \brief Retrieves platform specific power management resource.
- *
- * \param[in] context Type of power management context.
- * \param[in] index Index of the device.
- * \param[in] flags Flags, set of RPM_...
- */
-static inline void platform_pm_runtime_get(uint32_t context, uint32_t index, uint32_t flags)
-{
-}
-
-/**
- * \brief Releases platform specific power management resource.
- *
- * \param[in] context Type of power management context.
- * \param[in] index Index of the device.
- * \param[in] flags Flags, set of RPM_...
- */
-static inline void platform_pm_runtime_put(uint32_t context, uint32_t index, uint32_t flags)
-{
-}
-
-static inline void platform_pm_runtime_enable(uint32_t context, uint32_t index)
-{
-}
-
-static inline void platform_pm_runtime_disable(uint32_t context, uint32_t index)
-{
-}
-
-static inline bool platform_pm_runtime_is_active(uint32_t context, uint32_t index)
-{
-	return false;
-}
-
-#endif /* __PLATFORM_LIB_PM_RUNTIME_H__ */
-
-#else
-
-#error "This file shouldn't be included from outside of sof/lib/pm_runtime.h"
-
-#endif /* __SOF_LIB_PM_RUNTIME_H__ */
diff --git a/src/platform/mt8195/include/platform/mt8195-afe-common.h b/src/platform/mt8195/include/platform/mt8195-afe-common.h
deleted file mode 100644
index ffd699dce523..000000000000
--- a/src/platform/mt8195/include/platform/mt8195-afe-common.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2021 MediaTek. All rights reserved.
- *
- * Author: YC Hung <yc.hung@mediatek.com>
- */
-
-#ifndef _MT_8195_AFE_COMMON_H_
-#define _MT_8195_AFE_COMMON_H_
-
-/* AFE: the abbreviation for Audio Front End  */
-
-enum {
-	MT8195_MEMIF_START,
-	MT8195_MEMIF_DL_START = MT8195_MEMIF_START,
-	MT8195_MEMIF_DL2 = MT8195_MEMIF_DL_START,
-	MT8195_MEMIF_DL3,
-	MT8195_MEMIF_DL_END,
-	MT8195_MEMIF_UL_START = MT8195_MEMIF_DL_END,
-	MT8195_MEMIF_UL4 = MT8195_MEMIF_UL_START,
-	MT8195_MEMIF_UL5,
-	MT8195_MEMIF_UL_END,
-	MT8195_MEMIF_END = MT8195_MEMIF_UL_END,
-	MT8195_MEMIF_DL_NUM = (MT8195_MEMIF_DL_END - MT8195_MEMIF_DL_START),
-	MT8195_MEMIF_UL_NUM = (MT8195_MEMIF_UL_END - MT8195_MEMIF_UL_START),
-	MT8195_MEMIF_NUM = (MT8195_MEMIF_END - MT8195_MEMIF_START),
-};
-
-enum {
-	MT8195_IRQ_0,
-	MT8195_IRQ_1,
-	MT8195_IRQ_2,
-	MT8195_IRQ_3,
-	MT8195_IRQ_4,
-	MT8195_IRQ_5,
-	MT8195_IRQ_6,
-	MT8195_IRQ_7,
-	MT8195_IRQ_8,
-	MT8195_IRQ_9,
-	MT8195_IRQ_10,
-	MT8195_IRQ_11,
-	MT8195_IRQ_12,
-	MT8195_IRQ_13,
-	MT8195_IRQ_14,
-	MT8195_IRQ_15,
-	MT8195_IRQ_16,
-	MT8195_IRQ_17,
-	MT8195_IRQ_18,
-	MT8195_IRQ_19,
-	MT8195_IRQ_20,
-	MT8195_IRQ_21,
-	MT8195_IRQ_22,
-	MT8195_IRQ_23,
-	MT8195_IRQ_24,
-	MT8195_IRQ_25,
-	MT8195_IRQ_26,
-	MT8195_IRQ_31, /* used only for TDM */
-	MT8195_IRQ_NUM,
-};
-
-enum {
-	MT8195_AFE_IO_ETDM2_OUT,
-	MT8195_AFE_IO_ETDM1_OUT,
-	MT8195_AFE_IO_UL_SRC1,
-	MT8195_AFE_IO_ETDM2_IN,
-	MT8195_DAI_NUM,
-};
-
-#endif
diff --git a/src/platform/mt8195/include/platform/mt8195-afe-regs.h b/src/platform/mt8195/include/platform/mt8195-afe-regs.h
deleted file mode 100644
index 57d0d4637558..000000000000
--- a/src/platform/mt8195/include/platform/mt8195-afe-regs.h
+++ /dev/null
@@ -1,2790 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2021 MediaTek. All rights reserved.
- *
- * Author: YC Hung <yc.hung@mediatek.com>
- */
-
-#ifndef _MT8195_REG_H_
-#define _MT8195_REG_H_
-
-#define AFE_SRAM_BASE 0x10880000
-#define AFE_SRAM_SIZE 0x10000
-#define AFE_BASE_ADDR 0x10890000
-
-#define AUDIO_TOP_CON0 0x0000
-#define AUDIO_TOP_CON1 0x0004
-#define AUDIO_TOP_CON2 0x0008
-#define AUDIO_TOP_CON3 0x000c
-#define AUDIO_TOP_CON4 0x0010
-#define AUDIO_TOP_CON5 0x0014
-#define AUDIO_TOP_CON6 0x0018
-#define AFE_MAS_HADDR_MSB 0x0020
-#define PWR1_ASM_CON1 0x0108
-#define ASYS_IRQ_CONFIG 0x0110
-#define ASYS_IRQ1_CON 0x0114
-#define ASYS_IRQ2_CON 0x0118
-#define ASYS_IRQ3_CON 0x011c
-#define ASYS_IRQ4_CON 0x0120
-#define ASYS_IRQ5_CON 0x0124
-#define ASYS_IRQ6_CON 0x0128
-#define ASYS_IRQ7_CON 0x012c
-#define ASYS_IRQ8_CON 0x0130
-#define ASYS_IRQ9_CON 0x0134
-#define ASYS_IRQ10_CON 0x0138
-#define ASYS_IRQ11_CON 0x013c
-#define ASYS_IRQ12_CON 0x0140
-#define ASYS_IRQ13_CON 0x0144
-#define ASYS_IRQ14_CON 0x0148
-#define ASYS_IRQ15_CON 0x014c
-#define ASYS_IRQ16_CON 0x0150
-#define ASYS_IRQ_CLR 0x0154
-#define ASYS_IRQ_STATUS 0x0158
-#define ASYS_IRQ_MON1 0x015c
-#define ASYS_IRQ_MON2 0x0160
-#define AFE_IRQ1_CON 0x0164
-#define AFE_IRQ2_CON 0x0168
-#define AFE_IRQ3_CON 0x016c
-#define AFE_IRQ_MCU_CLR 0x0170
-#define AFE_IRQ_STATUS 0x0174
-#define AFE_IRQ_MASK 0x0178
-#define ASYS_IRQ_MASK 0x017c
-#define AFE_IRQ3_CON_MON 0x01b0
-#define AFE_IRQ_MCU_MON2 0x01b4
-#define AFE_IRQ8_CON 0x01b8
-#define AFE_IRQ9_CON 0x01bc
-#define AFE_IRQ10_CON 0x01c0
-#define AFE_IRQ9_CON_MON 0x01c4
-#define ADSP_IRQ_MASK 0x01c8
-#define ADSP_IRQ_STATUS 0x01cc
-#define AFE_SINEGEN_CON0 0x01f0
-#define AFE_SINEGEN_CON1 0x01f4
-#define AFE_SINEGEN_CON2 0x01f8
-#define AFE_SINEGEN_CON3 0x01fc
-#define AFE_SPDIF_OUT_CON0 0x0380
-#define AFE_TDMOUT_CONN0 0x0390
-#define PWR1_ASM_CON2 0x03b0
-#define PWR1_ASM_CON3 0x03b4
-#define PWR1_ASM_CON4 0x03b8
-#define AFE_APLL_TUNER_CFG 0x03f8
-#define AFE_APLL_TUNER_CFG1 0x03fc
-#define AUDIO_TOP_STA0 0x0400
-#define AUDIO_TOP_STA1 0x0404
-#define AFE_GAIN1_CON0 0x0410
-#define AFE_GAIN1_CON1 0x0414
-#define AFE_GAIN1_CON2 0x0418
-#define AFE_GAIN1_CON3 0x041c
-#define AFE_GAIN1_CUR 0x0424
-#define AFE_GAIN2_CON0 0x0428
-#define AFE_GAIN2_CON1 0x042c
-#define AFE_GAIN2_CON2 0x0430
-#define AFE_GAIN2_CON3 0x0434
-#define AFE_GAIN2_CUR 0x043c
-#define AFE_IEC_CFG 0x0480
-#define AFE_IEC_NSNUM 0x0484
-#define AFE_IEC_BURST_INFO 0x0488
-#define AFE_IEC_BURST_LEN 0x048c
-#define AFE_IEC_NSADR 0x0490
-#define AFE_IEC_CHL_STAT0 0x04a0
-#define AFE_IEC_CHL_STAT1 0x04a4
-#define AFE_IEC_CHR_STAT0 0x04a8
-#define AFE_IEC_CHR_STAT1 0x04ac
-#define AFE_SPDIFIN_CFG0 0x0500
-#define AFE_SPDIFIN_CFG1 0x0504
-#define AFE_SPDIFIN_CHSTS1 0x0508
-#define AFE_SPDIFIN_CHSTS2 0x050c
-#define AFE_SPDIFIN_CHSTS3 0x0510
-#define AFE_SPDIFIN_CHSTS4 0x0514
-#define AFE_SPDIFIN_CHSTS5 0x0518
-#define AFE_SPDIFIN_CHSTS6 0x051c
-#define AFE_SPDIFIN_DEBUG1 0x0520
-#define AFE_SPDIFIN_DEBUG2 0x0524
-#define AFE_SPDIFIN_DEBUG3 0x0528
-#define AFE_SPDIFIN_DEBUG4 0x052c
-#define AFE_SPDIFIN_EC 0x0530
-#define AFE_SPDIFIN_CKLOCK_CFG 0x0534
-#define AFE_SPDIFIN_BR 0x053c
-#define AFE_SPDIFIN_BR_DBG1 0x0540
-#define AFE_SPDIFIN_CKFBDIV 0x0544
-#define AFE_SPDIFIN_INT_EXT 0x0548
-#define AFE_SPDIFIN_INT_EXT2 0x054c
-#define SPDIFIN_FREQ_INFO 0x0550
-#define SPDIFIN_FREQ_INFO_2 0x0554
-#define SPDIFIN_FREQ_INFO_3 0x0558
-#define SPDIFIN_FREQ_STATUS 0x055c
-#define SPDIFIN_USERCODE1 0x0560
-#define SPDIFIN_USERCODE2 0x0564
-#define SPDIFIN_USERCODE3 0x0568
-#define SPDIFIN_USERCODE4 0x056c
-#define SPDIFIN_USERCODE5 0x0570
-#define SPDIFIN_USERCODE6 0x0574
-#define SPDIFIN_USERCODE7 0x0578
-#define SPDIFIN_USERCODE8 0x057c
-#define SPDIFIN_USERCODE9 0x0580
-#define SPDIFIN_USERCODE10 0x0584
-#define SPDIFIN_USERCODE11 0x0588
-#define SPDIFIN_USERCODE12 0x058c
-#define AFE_SPDIFIN_APLL_TUNER_CFG 0x0594
-#define AFE_SPDIFIN_APLL_TUNER_CFG1 0x0598
-#define ASYS_TOP_CON 0x0600
-#define AFE_LINEIN_APLL_TUNER_CFG 0x0610
-#define AFE_LINEIN_APLL_TUNER_MON 0x0614
-#define AFE_EARC_APLL_TUNER_CFG 0x0618
-#define AFE_EARC_APLL_TUNER_MON 0x061c
-#define PWR2_TOP_CON0 0x0634
-#define PWR2_TOP_CON1 0x0638
-#define PCM_INTF_CON1 0x063c
-#define PCM_INTF_CON2 0x0640
-#define AFE_CM0_CON 0x0660
-#define AFE_CM1_CON 0x0664
-#define AFE_CM2_CON 0x0668
-#define AFE_CM0_MON 0x0670
-#define AFE_CM1_MON 0x0674
-#define AFE_CM2_MON 0x0678
-#define AFE_MPHONE_MULTI_CON0 0x06a4
-#define AFE_MPHONE_MULTI_CON1 0x06a8
-#define AFE_MPHONE_MULTI_CON2 0x06ac
-#define AFE_MPHONE_MULTI_MON 0x06b0
-#define AFE_MPHONE_MULTI_DET_REG_CON0 0x06b4
-#define AFE_MPHONE_MULTI_DET_REG_CON1 0x06b8
-#define AFE_MPHONE_MULTI_DET_REG_CON2 0x06bc
-#define AFE_MPHONE_MULTI_DET_REG_CON3 0x06c0
-#define AFE_MPHONE_MULTI_DET_MON0 0x06c4
-#define AFE_MPHONE_MULTI_DET_MON1 0x06c8
-#define AFE_MPHONE_MULTI_DET_MON2 0x06d0
-#define AFE_MPHONE_MULTI2_CON0 0x06d4
-#define AFE_MPHONE_MULTI2_CON1 0x06d8
-#define AFE_MPHONE_MULTI2_CON2 0x06dc
-#define AFE_MPHONE_MULTI2_MON 0x06e0
-#define AFE_MPHONE_MULTI2_DET_REG_CON0 0x06e4
-#define AFE_MPHONE_MULTI2_DET_REG_CON1 0x06e8
-#define AFE_MPHONE_MULTI2_DET_REG_CON2 0x06ec
-#define AFE_MPHONE_MULTI2_DET_REG_CON3 0x06f0
-#define AFE_MPHONE_MULTI2_DET_MON0 0x06f4
-#define AFE_MPHONE_MULTI2_DET_MON1 0x06f8
-#define AFE_MPHONE_MULTI2_DET_MON2 0x06fc
-#define AFE_ADDA_IIR_COEF_02_01 0x0700
-#define AFE_ADDA_IIR_COEF_04_03 0x0704
-#define AFE_ADDA_IIR_COEF_06_05 0x0708
-#define AFE_ADDA_IIR_COEF_08_07 0x070c
-#define AFE_ADDA_IIR_COEF_10_09 0x0710
-#define AFE_ADDA_ULCF_CFG_02_01 0x0714
-#define AFE_ADDA_ULCF_CFG_04_03 0x0718
-#define AFE_ADDA_ULCF_CFG_06_05 0x071c
-#define AFE_ADDA_ULCF_CFG_08_07 0x0720
-#define AFE_ADDA_ULCF_CFG_10_09 0x0724
-#define AFE_ADDA_ULCF_CFG_12_11 0x0728
-#define AFE_ADDA_ULCF_CFG_14_13 0x072c
-#define AFE_ADDA_ULCF_CFG_16_15 0x0730
-#define AFE_ADDA_ULCF_CFG_18_17 0x0734
-#define AFE_ADDA_ULCF_CFG_20_19 0x0738
-#define AFE_ADDA_ULCF_CFG_22_21 0x073c
-#define AFE_ADDA_ULCF_CFG_24_23 0x0740
-#define AFE_ADDA_ULCF_CFG_26_25 0x0744
-#define AFE_ADDA_ULCF_CFG_28_27 0x0748
-#define AFE_ADDA_ULCF_CFG_30_29 0x074c
-#define AFE_ADDA6_IIR_COEF_02_01 0x0750
-#define AFE_ADDA6_IIR_COEF_04_03 0x0754
-#define AFE_ADDA6_IIR_COEF_06_05 0x0758
-#define AFE_ADDA6_IIR_COEF_08_07 0x075c
-#define AFE_ADDA6_IIR_COEF_10_09 0x0760
-#define AFE_ADDA6_ULCF_CFG_02_01 0x0764
-#define AFE_ADDA6_ULCF_CFG_04_03 0x0768
-#define AFE_ADDA6_ULCF_CFG_06_05 0x076c
-#define AFE_ADDA6_ULCF_CFG_08_07 0x0770
-#define AFE_ADDA6_ULCF_CFG_10_09 0x0774
-#define AFE_ADDA6_ULCF_CFG_12_11 0x0778
-#define AFE_ADDA6_ULCF_CFG_14_13 0x077c
-#define AFE_ADDA6_ULCF_CFG_16_15 0x0780
-#define AFE_ADDA6_ULCF_CFG_18_17 0x0784
-#define AFE_ADDA6_ULCF_CFG_20_19 0x0788
-#define AFE_ADDA6_ULCF_CFG_22_21 0x078c
-#define AFE_ADDA6_ULCF_CFG_24_23 0x0790
-#define AFE_ADDA6_ULCF_CFG_26_25 0x0794
-#define AFE_ADDA6_ULCF_CFG_28_27 0x0798
-#define AFE_ADDA6_ULCF_CFG_30_29 0x079c
-#define AFE_ADDA_MTKAIF_CFG0 0x07a0
-#define AFE_ADDA_MTKAIF_SYNCWORD_CFG 0x07a8
-#define AFE_ADDA_MTKAIF_RX_CFG0 0x07b4
-#define AFE_ADDA_MTKAIF_RX_CFG1 0x07b8
-#define AFE_ADDA_MTKAIF_RX_CFG2 0x07bc
-#define AFE_ADDA_MTKAIF_MON0 0x07c8
-#define AFE_ADDA_MTKAIF_MON1 0x07cc
-#define AFE_AUD_PAD_TOP 0x07d4
-#define AFE_ADDA6_MTKAIF_MON0 0x07d8
-#define AFE_ADDA6_MTKAIF_MON1 0x07dc
-#define AFE_ADDA6_MTKAIF_CFG0 0x07e0
-#define AFE_ADDA6_MTKAIF_RX_CFG0 0x07e4
-#define AFE_ADDA6_MTKAIF_RX_CFG1 0x07e8
-#define AFE_ADDA6_MTKAIF_RX_CFG2 0x07ec
-#define AFE_ADDA6_TOP_CON0 0x07f0
-#define AFE_ADDA6_UL_SRC_CON0 0x07f4
-#define AFE_ADDA6_UL_SRC_CON1 0x07f8
-#define AFE_ADDA6_SRC_DEBUG 0x0800
-#define AFE_ADDA6_SRC_DEBUG_MON0 0x0804
-#define AFE_ADDA6_UL_SRC_MON0 0x0818
-#define AFE_ADDA6_UL_SRC_MON1 0x081c
-#define AFE_CONN0_5 0x0830
-#define AFE_CONN1_5 0x0834
-#define AFE_CONN2_5 0x0838
-#define AFE_CONN3_5 0x083c
-#define AFE_CONN4_5 0x0840
-#define AFE_CONN5_5 0x0844
-#define AFE_CONN6_5 0x0848
-#define AFE_CONN7_5 0x084c
-#define AFE_CONN8_5 0x0850
-#define AFE_CONN9_5 0x0854
-#define AFE_CONN10_5 0x0858
-#define AFE_CONN11_5 0x085c
-#define AFE_CONN12_5 0x0860
-#define AFE_CONN13_5 0x0864
-#define AFE_CONN14_5 0x0868
-#define AFE_CONN15_5 0x086c
-#define AFE_CONN16_5 0x0870
-#define AFE_CONN17_5 0x0874
-#define AFE_CONN18_5 0x0878
-#define AFE_CONN19_5 0x087c
-#define AFE_CONN20_5 0x0880
-#define AFE_CONN21_5 0x0884
-#define AFE_CONN22_5 0x0888
-#define AFE_CONN23_5 0x088c
-#define AFE_CONN24_5 0x0890
-#define AFE_CONN25_5 0x0894
-#define AFE_CONN26_5 0x0898
-#define AFE_CONN27_5 0x089c
-#define AFE_CONN28_5 0x08a0
-#define AFE_CONN29_5 0x08a4
-#define AFE_CONN30_5 0x08a8
-#define AFE_CONN31_5 0x08ac
-#define AFE_CONN32_5 0x08b0
-#define AFE_CONN33_5 0x08b4
-#define AFE_CONN34_5 0x08b8
-#define AFE_CONN35_5 0x08bc
-#define AFE_CONN36_5 0x08c0
-#define AFE_CONN37_5 0x08c4
-#define AFE_CONN38_5 0x08c8
-#define AFE_CONN39_5 0x08cc
-#define AFE_CONN40_5 0x08d0
-#define AFE_CONN41_5 0x08d4
-#define AFE_CONN42_5 0x08d8
-#define AFE_CONN43_5 0x08dc
-#define AFE_CONN44_5 0x08e0
-#define AFE_CONN45_5 0x08e4
-#define AFE_CONN46_5 0x08e8
-#define AFE_CONN47_5 0x08ec
-#define AFE_CONN48_5 0x08f0
-#define AFE_CONN49_5 0x08f4
-#define AFE_CONN50_5 0x08f8
-#define AFE_CONN51_5 0x08fc
-#define AFE_CONN52_5 0x0900
-#define AFE_CONN53_5 0x0904
-#define AFE_CONN54_5 0x0908
-#define AFE_CONN55_5 0x090c
-#define AFE_CONN56_5 0x0910
-#define AFE_CONN57_5 0x0914
-#define AFE_CONN58_5 0x0918
-#define AFE_CONN59_5 0x091c
-#define AFE_CONN60_5 0x0920
-#define AFE_CONN61_5 0x0924
-#define AFE_CONN62_5 0x0928
-#define AFE_CONN63_5 0x092c
-#define AFE_CONN64_5 0x0930
-#define AFE_CONN65_5 0x0934
-#define AFE_CONN66_5 0x0938
-#define AFE_CONN67_5 0x093c
-#define AFE_CONN68_5 0x0940
-#define AFE_CONN69_5 0x0944
-#define AFE_CONN70_5 0x0948
-#define AFE_CONN71_5 0x094c
-#define AFE_CONN72_5 0x0950
-#define AFE_CONN73_5 0x0954
-#define AFE_CONN74_5 0x0958
-#define AFE_CONN75_5 0x095c
-#define AFE_CONN76_5 0x0960
-#define AFE_CONN77_5 0x0964
-#define AFE_CONN78_5 0x0968
-#define AFE_CONN79_5 0x096c
-#define AFE_CONN80_5 0x0970
-#define AFE_CONN81_5 0x0974
-#define AFE_CONN82_5 0x0978
-#define AFE_CONN83_5 0x097c
-#define AFE_CONN84_5 0x0980
-#define AFE_CONN85_5 0x0984
-#define AFE_CONN86_5 0x0988
-#define AFE_CONN87_5 0x098c
-#define AFE_CONN88_5 0x0990
-#define AFE_CONN89_5 0x0994
-#define AFE_CONN90_5 0x0998
-#define AFE_CONN91_5 0x099c
-#define AFE_CONN92_5 0x09a0
-#define AFE_CONN93_5 0x09a4
-#define AFE_CONN94_5 0x09a8
-#define AFE_CONN95_5 0x09ac
-#define AFE_CONN96_5 0x09b0
-#define AFE_CONN97_5 0x09b4
-#define AFE_CONN98_5 0x09b8
-#define AFE_CONN99_5 0x09bc
-#define AFE_CONN100_5 0x09c0
-#define AFE_CONN101_5 0x09c4
-#define AFE_CONN102_5 0x09c8
-#define AFE_CONN103_5 0x09cc
-#define AFE_CONN104_5 0x09d0
-#define AFE_CONN105_5 0x09d4
-#define AFE_CONN106_5 0x09d8
-#define AFE_CONN107_5 0x09dc
-#define AFE_CONN108_5 0x09e0
-#define AFE_CONN109_5 0x09e4
-#define AFE_CONN110_5 0x09e8
-#define AFE_CONN111_5 0x09ec
-#define AFE_CONN112_5 0x09f0
-#define AFE_CONN113_5 0x09f4
-#define AFE_CONN114_5 0x09f8
-#define AFE_CONN115_5 0x09fc
-#define AFE_CONN116_5 0x0a00
-#define AFE_CONN117_5 0x0a04
-#define AFE_CONN118_5 0x0a08
-#define AFE_CONN119_5 0x0a0c
-#define AFE_CONN120_5 0x0a10
-#define AFE_CONN121_5 0x0a14
-#define AFE_CONN122_5 0x0a18
-#define AFE_CONN123_5 0x0a1c
-#define AFE_CONN124_5 0x0a20
-#define AFE_CONN125_5 0x0a24
-#define AFE_CONN126_5 0x0a28
-#define AFE_CONN127_5 0x0a2c
-#define AFE_CONN128_5 0x0a30
-#define AFE_CONN129_5 0x0a34
-#define AFE_CONN130_5 0x0a38
-#define AFE_CONN131_5 0x0a3c
-#define AFE_CONN132_5 0x0a40
-#define AFE_CONN133_5 0x0a44
-#define AFE_CONN134_5 0x0a48
-#define AFE_CONN135_5 0x0a4c
-#define AFE_CONN136_5 0x0a50
-#define AFE_CONN137_5 0x0a54
-#define AFE_CONN138_5 0x0a58
-#define AFE_CONN139_5 0x0a5c
-#define AFE_CONN_RS_5 0x0a60
-#define AFE_CONN_DI_5 0x0a64
-#define AFE_CONN_16BIT_5 0x0a68
-#define AFE_CONN_24BIT_5 0x0a6c
-#define AFE_ASRC11_NEW_CON0 0x0d80
-#define AFE_ASRC11_NEW_CON1 0x0d84
-#define AFE_ASRC11_NEW_CON2 0x0d88
-#define AFE_ASRC11_NEW_CON3 0x0d8c
-#define AFE_ASRC11_NEW_CON4 0x0d90
-#define AFE_ASRC11_NEW_CON5 0x0d94
-#define AFE_ASRC11_NEW_CON6 0x0d98
-#define AFE_ASRC11_NEW_CON7 0x0d9c
-#define AFE_ASRC11_NEW_CON8 0x0da0
-#define AFE_ASRC11_NEW_CON9 0x0da4
-#define AFE_ASRC11_NEW_CON10 0x0da8
-#define AFE_ASRC11_NEW_CON11 0x0dac
-#define AFE_ASRC11_NEW_CON13 0x0db4
-#define AFE_ASRC11_NEW_CON14 0x0db8
-#define AFE_ASRC12_NEW_CON0 0x0dc0
-#define AFE_ASRC12_NEW_CON1 0x0dc4
-#define AFE_ASRC12_NEW_CON2 0x0dc8
-#define AFE_ASRC12_NEW_CON3 0x0dcc
-#define AFE_ASRC12_NEW_CON4 0x0dd0
-#define AFE_ASRC12_NEW_CON5 0x0dd4
-#define AFE_ASRC12_NEW_CON6 0x0dd8
-#define AFE_ASRC12_NEW_CON7 0x0ddc
-#define AFE_ASRC12_NEW_CON8 0x0de0
-#define AFE_ASRC12_NEW_CON9 0x0de4
-#define AFE_ASRC12_NEW_CON10 0x0de8
-#define AFE_ASRC12_NEW_CON11 0x0dec
-#define AFE_ASRC12_NEW_CON13 0x0df4
-#define AFE_ASRC12_NEW_CON14 0x0df8
-#define AFE_LRCK_CNT 0x1018
-#define AFE_DAC_CON0 0x1200
-#define AFE_DAC_CON1 0x1204
-#define AFE_DAC_CON2 0x1208
-#define AFE_DAC_MON0 0x1218
-#define AFE_DL2_BASE 0x1250
-#define AFE_DL2_CUR 0x1254
-#define AFE_DL2_END 0x1258
-#define AFE_DL2_CON0 0x125c
-#define AFE_DL3_BASE 0x1260
-#define AFE_DL3_CUR 0x1264
-#define AFE_DL3_END 0x1268
-#define AFE_DL3_CON0 0x126c
-#define AFE_DL6_BASE 0x1290
-#define AFE_DL6_CUR 0x1294
-#define AFE_DL6_END 0x1298
-#define AFE_DL6_CON0 0x129c
-#define AFE_DL7_BASE 0x12a0
-#define AFE_DL7_CUR 0x12a4
-#define AFE_DL7_END 0x12a8
-#define AFE_DL7_CON0 0x12ac
-#define AFE_DL8_BASE 0x12b0
-#define AFE_DL8_CUR 0x12b4
-#define AFE_DL8_END 0x12b8
-#define AFE_DL8_CON0 0x12bc
-#define AFE_DL10_BASE 0x12d0
-#define AFE_DL10_CUR 0x12d4
-#define AFE_DL10_END 0x12d8
-#define AFE_DL10_CON0 0x12dc
-#define AFE_DL11_BASE 0x12e0
-#define AFE_DL11_CUR 0x12e4
-#define AFE_DL11_END 0x12e8
-#define AFE_DL11_CON0 0x12ec
-#define AFE_UL1_BASE 0x1300
-#define AFE_UL1_CUR 0x1304
-#define AFE_UL1_END 0x1308
-#define AFE_UL1_CON0 0x130c
-#define AFE_UL2_BASE 0x1310
-#define AFE_UL2_CUR 0x1314
-#define AFE_UL2_END 0x1318
-#define AFE_UL2_CON0 0x131c
-#define AFE_UL3_BASE 0x1320
-#define AFE_UL3_CUR 0x1324
-#define AFE_UL3_END 0x1328
-#define AFE_UL3_CON0 0x132c
-#define AFE_UL4_BASE 0x1330
-#define AFE_UL4_CUR 0x1334
-#define AFE_UL4_END 0x1338
-#define AFE_UL4_CON0 0x133c
-#define AFE_UL5_BASE 0x1340
-#define AFE_UL5_CUR 0x1344
-#define AFE_UL5_END 0x1348
-#define AFE_UL5_CON0 0x134c
-#define AFE_UL6_BASE 0x1350
-#define AFE_UL6_CUR 0x1354
-#define AFE_UL6_END 0x1358
-#define AFE_UL6_CON0 0x135c
-#define AFE_UL8_BASE 0x1370
-#define AFE_UL8_CUR 0x1374
-#define AFE_UL8_END 0x1378
-#define AFE_UL8_CON0 0x137c
-#define AFE_UL9_BASE 0x1380
-#define AFE_UL9_CUR 0x1384
-#define AFE_UL9_END 0x1388
-#define AFE_UL9_CON0 0x138c
-#define AFE_UL10_BASE 0x13d0
-#define AFE_UL10_CUR 0x13d4
-#define AFE_UL10_END 0x13d8
-#define AFE_UL10_CON0 0x13dc
-#define AFE_DL8_CHK_SUM1 0x1400
-#define AFE_DL8_CHK_SUM2 0x1404
-#define AFE_DL8_CHK_SUM3 0x1408
-#define AFE_DL8_CHK_SUM4 0x140c
-#define AFE_DL8_CHK_SUM5 0x1410
-#define AFE_DL8_CHK_SUM6 0x1414
-#define AFE_DL10_CHK_SUM1 0x1418
-#define AFE_DL10_CHK_SUM2 0x141c
-#define AFE_DL10_CHK_SUM3 0x1420
-#define AFE_DL10_CHK_SUM4 0x1424
-#define AFE_DL10_CHK_SUM5 0x1428
-#define AFE_DL10_CHK_SUM6 0x142c
-#define AFE_DL11_CHK_SUM1 0x1430
-#define AFE_DL11_CHK_SUM2 0x1434
-#define AFE_DL11_CHK_SUM3 0x1438
-#define AFE_DL11_CHK_SUM4 0x143c
-#define AFE_DL11_CHK_SUM5 0x1440
-#define AFE_DL11_CHK_SUM6 0x1444
-#define AFE_UL1_CHK_SUM1 0x1450
-#define AFE_UL1_CHK_SUM2 0x1454
-#define AFE_UL2_CHK_SUM1 0x1458
-#define AFE_UL2_CHK_SUM2 0x145c
-#define AFE_UL3_CHK_SUM1 0x1460
-#define AFE_UL3_CHK_SUM2 0x1464
-#define AFE_UL4_CHK_SUM1 0x1468
-#define AFE_UL4_CHK_SUM2 0x146c
-#define AFE_UL5_CHK_SUM1 0x1470
-#define AFE_UL5_CHK_SUM2 0x1474
-#define AFE_UL6_CHK_SUM1 0x1478
-#define AFE_UL6_CHK_SUM2 0x147c
-#define AFE_UL8_CHK_SUM1 0x1488
-#define AFE_UL8_CHK_SUM2 0x148c
-#define AFE_DL2_CHK_SUM1 0x14a0
-#define AFE_DL2_CHK_SUM2 0x14a4
-#define AFE_DL3_CHK_SUM1 0x14b0
-#define AFE_DL3_CHK_SUM2 0x14b4
-#define AFE_DL6_CHK_SUM1 0x14e0
-#define AFE_DL6_CHK_SUM2 0x14e4
-#define AFE_DL7_CHK_SUM1 0x14f0
-#define AFE_DL7_CHK_SUM2 0x14f4
-#define AFE_UL9_CHK_SUM1 0x1528
-#define AFE_UL9_CHK_SUM2 0x152c
-#define AFE_BUS_MON1 0x1540
-#define UL1_MOD2AGT_CNT_LAT 0x1568
-#define UL2_MOD2AGT_CNT_LAT 0x156c
-#define UL3_MOD2AGT_CNT_LAT 0x1570
-#define UL4_MOD2AGT_CNT_LAT 0x1574
-#define UL5_MOD2AGT_CNT_LAT 0x1578
-#define UL6_MOD2AGT_CNT_LAT 0x157c
-#define UL8_MOD2AGT_CNT_LAT 0x1588
-#define UL9_MOD2AGT_CNT_LAT 0x158c
-#define UL10_MOD2AGT_CNT_LAT 0x1590
-#define AFE_MEMIF_AGENT_FS_CON0 0x15a0
-#define AFE_MEMIF_AGENT_FS_CON1 0x15a4
-#define AFE_MEMIF_AGENT_FS_CON2 0x15a8
-#define AFE_MEMIF_AGENT_FS_CON3 0x15ac
-#define AFE_MEMIF_BURST_CFG 0x1600
-#define AFE_MEMIF_BUF_FULL_MON 0x1610
-#define AFE_MEMIF_BUF_MON1 0x161c
-#define AFE_MEMIF_BUF_MON3 0x1624
-#define AFE_MEMIF_BUF_MON4 0x1628
-#define AFE_MEMIF_BUF_MON5 0x162c
-#define AFE_MEMIF_BUF_MON6 0x1630
-#define AFE_MEMIF_BUF_MON7 0x1634
-#define AFE_MEMIF_BUF_MON8 0x1638
-#define AFE_MEMIF_BUF_MON9 0x163c
-#define AFE_MEMIF_BUF_MON10 0x1640
-#define DL2_AGENT2MODULE_CNT 0x1678
-#define DL3_AGENT2MODULE_CNT 0x167c
-#define DL6_AGENT2MODULE_CNT 0x1688
-#define DL7_AGENT2MODULE_CNT 0x168c
-#define DL8_AGENT2MODULE_CNT 0x1690
-#define DL10_AGENT2MODULE_CNT 0x1698
-#define DL11_AGENT2MODULE_CNT 0x169c
-#define UL1_MODULE2AGENT_CNT 0x16a0
-#define UL2_MODULE2AGENT_CNT 0x16a4
-#define UL3_MODULE2AGENT_CNT 0x16a8
-#define UL4_MODULE2AGENT_CNT 0x16ac
-#define UL5_MODULE2AGENT_CNT 0x16b0
-#define UL6_MODULE2AGENT_CNT 0x16b4
-#define UL8_MODULE2AGENT_CNT 0x16bc
-#define UL9_MODULE2AGENT_CNT 0x16c0
-#define UL10_MODULE2AGENT_CNT 0x16c4
-#define AFE_SECURE_CON2 0x1798
-#define AFE_SECURE_CON1 0x179c
-#define AFE_SECURE_CON 0x17a0
-#define AFE_SRAM_BOUND 0x17a4
-#define AFE_SE_SECURE_CON 0x17a8
-#define AFE_SECURE_MASK_LOOPBACK 0x17bc
-#define AFE_SECURE_SIDEBAND0 0x1908
-#define AFE_SECURE_SIDEBAND1 0x190c
-#define AFE_SECURE_SIDEBAND2 0x1910
-#define AFE_SECURE_SIDEBAND3 0x1914
-#define AFE_SECURE_MASK_BASE_ADR_MSB 0x1920
-#define AFE_SECURE_MASK_END_ADR_MSB 0x1924
-#define AFE_NORMAL_BASE_ADR_MSB 0x192c
-#define AFE_NORMAL_END_ADR_MSB 0x1930
-#define AFE_SECURE_MASK_LOOPBACK0 0x1940
-#define AFE_SECURE_MASK_LOOPBACK1 0x1944
-#define AFE_SECURE_MASK_LOOPBACK2 0x1948
-#define AFE_LOOPBACK_CFG0 0x1950
-#define AFE_LOOPBACK_CFG1 0x1954
-#define AFE_LOOPBACK_CFG2 0x1958
-#define AFE_DMIC0_UL_SRC_CON0 0x1a00
-#define AFE_DMIC0_UL_SRC_CON1 0x1a04
-#define AFE_DMIC0_SRC_DEBUG 0x1a08
-#define AFE_DMIC0_SRC_DEBUG_MON0 0x1a0c
-#define AFE_DMIC0_UL_SRC_MON0 0x1a10
-#define AFE_DMIC0_UL_SRC_MON1 0x1a14
-#define AFE_DMIC0_IIR_COEF_02_01 0x1a18
-#define AFE_DMIC0_IIR_COEF_04_03 0x1a1c
-#define AFE_DMIC0_IIR_COEF_06_05 0x1a20
-#define AFE_DMIC0_IIR_COEF_08_07 0x1a24
-#define AFE_DMIC0_IIR_COEF_10_09 0x1a28
-#define AFE_DMIC1_UL_SRC_CON0 0x1a68
-#define AFE_DMIC1_UL_SRC_CON1 0x1a6c
-#define AFE_DMIC1_SRC_DEBUG 0x1a70
-#define AFE_DMIC1_SRC_DEBUG_MON0 0x1a74
-#define AFE_DMIC1_UL_SRC_MON0 0x1a78
-#define AFE_DMIC1_UL_SRC_MON1 0x1a7c
-#define AFE_DMIC1_IIR_COEF_02_01 0x1a80
-#define AFE_DMIC1_IIR_COEF_04_03 0x1a84
-#define AFE_DMIC1_IIR_COEF_06_05 0x1a88
-#define AFE_DMIC1_IIR_COEF_08_07 0x1a8c
-#define AFE_DMIC1_IIR_COEF_10_09 0x1a90
-#define AFE_DMIC2_UL_SRC_CON0 0x1ad0
-#define AFE_DMIC2_UL_SRC_CON1 0x1ad4
-#define AFE_DMIC2_SRC_DEBUG 0x1ad8
-#define AFE_DMIC2_SRC_DEBUG_MON0 0x1adc
-#define AFE_DMIC2_UL_SRC_MON0 0x1ae0
-#define AFE_DMIC2_UL_SRC_MON1 0x1ae4
-#define AFE_DMIC2_IIR_COEF_02_01 0x1ae8
-#define AFE_DMIC2_IIR_COEF_04_03 0x1aec
-#define AFE_DMIC2_IIR_COEF_06_05 0x1af0
-#define AFE_DMIC2_IIR_COEF_08_07 0x1af4
-#define AFE_DMIC2_IIR_COEF_10_09 0x1af8
-#define AFE_DMIC3_UL_SRC_CON0 0x1b38
-#define AFE_DMIC3_UL_SRC_CON1 0x1b3c
-#define AFE_DMIC3_SRC_DEBUG 0x1b40
-#define AFE_DMIC3_SRC_DEBUG_MON0 0x1b44
-#define AFE_DMIC3_UL_SRC_MON0 0x1b48
-#define AFE_DMIC3_UL_SRC_MON1 0x1b4c
-#define AFE_DMIC3_IIR_COEF_02_01 0x1b50
-#define AFE_DMIC3_IIR_COEF_04_03 0x1b54
-#define AFE_DMIC3_IIR_COEF_06_05 0x1b58
-#define AFE_DMIC3_IIR_COEF_08_07 0x1b5c
-#define AFE_DMIC3_IIR_COEF_10_09 0x1b60
-#define DMIC_BYPASS_HW_GAIN 0x1bf0
-#define DMIC_GAIN1_CON0 0x1c00
-#define DMIC_GAIN1_CON1 0x1c04
-#define DMIC_GAIN1_CON2 0x1c08
-#define DMIC_GAIN1_CON3 0x1c0c
-#define DMIC_GAIN1_CUR 0x1c10
-#define DMIC_GAIN2_CON0 0x1c20
-#define DMIC_GAIN2_CON1 0x1c24
-#define DMIC_GAIN2_CON2 0x1c28
-#define DMIC_GAIN2_CON3 0x1c2c
-#define DMIC_GAIN2_CUR 0x1c30
-#define DMIC_GAIN3_CON0 0x1c40
-#define DMIC_GAIN3_CON1 0x1c44
-#define DMIC_GAIN3_CON2 0x1c48
-#define DMIC_GAIN3_CON3 0x1c4c
-#define DMIC_GAIN3_CUR 0x1c50
-#define DMIC_GAIN4_CON0 0x1c60
-#define DMIC_GAIN4_CON1 0x1c64
-#define DMIC_GAIN4_CON2 0x1c68
-#define DMIC_GAIN4_CON3 0x1c6c
-#define DMIC_GAIN4_CUR 0x1c70
-#define ETDM_OUT1_DSD_FADE_CON 0x2260
-#define ETDM_OUT1_DSD_FADE_CON1 0x2264
-#define ETDM_OUT3_DSD_FADE_CON 0x2280
-#define ETDM_OUT3_DSD_FADE_CON1 0x2284
-#define ETDM_IN1_AFIFO_CON 0x2294
-#define ETDM_IN2_AFIFO_CON 0x2298
-#define ETDM_IN1_MONITOR 0x22c0
-#define ETDM_IN2_MONITOR 0x22c4
-#define ETDM_OUT1_MONITOR 0x22d0
-#define ETDM_OUT2_MONITOR 0x22d4
-#define ETDM_OUT3_MONITOR 0x22d8
-#define ETDM_COWORK_SEC_CON0 0x22e0
-#define ETDM_COWORK_SEC_CON1 0x22e4
-#define ETDM_COWORK_SEC_CON2 0x22e8
-#define ETDM_COWORK_SEC_CON3 0x22ec
-#define ETDM_COWORK_CON0 0x22f0
-#define ETDM_COWORK_CON1 0x22f4
-#define ETDM_COWORK_CON2 0x22f8
-#define ETDM_COWORK_CON3 0x22fc
-#define ETDM_IN1_CON0 0x2300
-#define ETDM_IN1_CON1 0x2304
-#define ETDM_IN1_CON2 0x2308
-#define ETDM_IN1_CON3 0x230c
-#define ETDM_IN1_CON4 0x2310
-#define ETDM_IN1_CON5 0x2314
-#define ETDM_IN1_CON6 0x2318
-#define ETDM_IN1_CON7 0x231c
-#define ETDM_IN2_CON0 0x2320
-#define ETDM_IN2_CON1 0x2324
-#define ETDM_IN2_CON2 0x2328
-#define ETDM_IN2_CON3 0x232c
-#define ETDM_IN2_CON4 0x2330
-#define ETDM_IN2_CON5 0x2334
-#define ETDM_IN2_CON6 0x2338
-#define ETDM_IN2_CON7 0x233c
-#define ETDM_OUT1_CON0 0x2380
-#define ETDM_OUT1_CON1 0x2384
-#define ETDM_OUT1_CON2 0x2388
-#define ETDM_OUT1_CON3 0x238c
-#define ETDM_OUT1_CON4 0x2390
-#define ETDM_OUT1_CON5 0x2394
-#define ETDM_OUT1_CON6 0x2398
-#define ETDM_OUT1_CON7 0x239c
-#define ETDM_OUT2_CON0 0x23a0
-#define ETDM_OUT2_CON1 0x23a4
-#define ETDM_OUT2_CON2 0x23a8
-#define ETDM_OUT2_CON3 0x23ac
-#define ETDM_OUT2_CON4 0x23b0
-#define ETDM_OUT2_CON5 0x23b4
-#define ETDM_OUT2_CON6 0x23b8
-#define ETDM_OUT2_CON7 0x23bc
-#define ETDM_OUT3_CON0 0x23c0
-#define ETDM_OUT3_CON1 0x23c4
-#define ETDM_OUT3_CON2 0x23c8
-#define ETDM_OUT3_CON3 0x23cc
-#define ETDM_OUT3_CON4 0x23d0
-#define ETDM_OUT3_CON5 0x23d4
-#define ETDM_OUT3_CON6 0x23d8
-#define ETDM_OUT3_CON7 0x23dc
-#define ETDM_OUT3_CON8 0x23e0
-#define ETDM_OUT1_CON8 0x23e4
-#define ETDM_OUT2_CON8 0x23e8
-#define GASRC_TIMING_CON0 0x2414
-#define GASRC_TIMING_CON1 0x2418
-#define GASRC_TIMING_CON2 0x241c
-#define GASRC_TIMING_CON3 0x2420
-#define GASRC_TIMING_CON4 0x2424
-#define GASRC_TIMING_CON5 0x2428
-#define GASRC_TIMING_CON6 0x242c
-#define GASRC_TIMING_CON7 0x2430
-#define A3_A4_TIMING_SEL0 0x2440
-#define A3_A4_TIMING_SEL1 0x2444
-#define A3_A4_TIMING_SEL2 0x2448
-#define A3_A4_TIMING_SEL3 0x244c
-#define A3_A4_TIMING_SEL4 0x2450
-#define A3_A4_TIMING_SEL5 0x2454
-#define A3_A4_TIMING_SEL6 0x2458
-#define ASYS_TOP_DEBUG 0x2500
-#define AFE_DPTX_CON 0x2558
-#define AFE_DPTX_MON 0x255c
-#define AFE_ADDA_DL_SRC2_CON0 0x2d00
-#define AFE_ADDA_DL_SRC2_CON1 0x2d04
-#define AFE_ADDA_TOP_CON0 0x2d0c
-#define AFE_ADDA_UL_DL_CON0 0x2d10
-#define AFE_ADDA_SRC_DEBUG 0x2d14
-#define AFE_ADDA_SRC_DEBUG_MON0 0x2d18
-#define AFE_ADDA_SRC_DEBUG_MON1 0x2d20
-#define AFE_ADDA_PREDIS_CON0 0x2d24
-#define AFE_ADDA_PREDIS_CON1 0x2d28
-#define AFE_ADDA_PREDIS_CON2 0x2d2c
-#define AFE_ADDA_PREDIS_CON3 0x2d30
-#define AFE_ADDA_DL_SDM_DCCOMP_CON 0x2d34
-#define AFE_ADDA_DL_SDM_TEST 0x2d38
-#define AFE_ADDA_DL_DC_COMP_CFG0 0x2d3c
-#define AFE_ADDA_DL_DC_COMP_CFG1 0x2d40
-#define AFE_ADDA_DL_SDM_FIFO_MON 0x2d44
-#define AFE_ADDA_DL_SRC_LCH_MON 0x2d50
-#define AFE_ADDA_DL_SRC_RCH_MON 0x2d54
-#define AFE_ADDA_DL_SDM_OUT_MON 0x2d58
-#define AFE_ADDA_DL_SDM_DITHER_CON 0x2d5c
-#define AFE_ADDA_DL_SDM_AUTO_RESET_CON 0x2d60
-#define AFE_ADDA_UL_SRC_CON0 0x2e3c
-#define AFE_ADDA_UL_SRC_CON1 0x2e40
-#define AFE_CONN0 0x3000
-#define AFE_CONN0_1 0x3004
-#define AFE_CONN0_2 0x3008
-#define AFE_CONN0_3 0x300c
-#define AFE_CONN0_4 0x3010
-#define AFE_CONN1 0x3014
-#define AFE_CONN1_1 0x3018
-#define AFE_CONN1_2 0x301c
-#define AFE_CONN1_3 0x3020
-#define AFE_CONN1_4 0x3024
-#define AFE_CONN2 0x3028
-#define AFE_CONN2_1 0x302c
-#define AFE_CONN2_2 0x3030
-#define AFE_CONN2_3 0x3034
-#define AFE_CONN2_4 0x3038
-#define AFE_CONN3 0x303c
-#define AFE_CONN3_1 0x3040
-#define AFE_CONN3_2 0x3044
-#define AFE_CONN3_3 0x3048
-#define AFE_CONN3_4 0x304c
-#define AFE_CONN4 0x3050
-#define AFE_CONN4_1 0x3054
-#define AFE_CONN4_2 0x3058
-#define AFE_CONN4_3 0x305c
-#define AFE_CONN4_4 0x3060
-#define AFE_CONN5 0x3064
-#define AFE_CONN5_1 0x3068
-#define AFE_CONN5_2 0x306c
-#define AFE_CONN5_3 0x3070
-#define AFE_CONN5_4 0x3074
-#define AFE_CONN6 0x3078
-#define AFE_CONN6_1 0x307c
-#define AFE_CONN6_2 0x3080
-#define AFE_CONN6_3 0x3084
-#define AFE_CONN6_4 0x3088
-#define AFE_CONN7 0x308c
-#define AFE_CONN7_1 0x3090
-#define AFE_CONN7_2 0x3094
-#define AFE_CONN7_3 0x3098
-#define AFE_CONN7_4 0x309c
-#define AFE_CONN8 0x30a0
-#define AFE_CONN8_1 0x30a4
-#define AFE_CONN8_2 0x30a8
-#define AFE_CONN8_3 0x30ac
-#define AFE_CONN8_4 0x30b0
-#define AFE_CONN9 0x30b4
-#define AFE_CONN9_1 0x30b8
-#define AFE_CONN9_2 0x30bc
-#define AFE_CONN9_3 0x30c0
-#define AFE_CONN9_4 0x30c4
-#define AFE_CONN10 0x30c8
-#define AFE_CONN10_1 0x30cc
-#define AFE_CONN10_2 0x30d0
-#define AFE_CONN10_3 0x30d4
-#define AFE_CONN10_4 0x30d8
-#define AFE_CONN11 0x30dc
-#define AFE_CONN11_1 0x30e0
-#define AFE_CONN11_2 0x30e4
-#define AFE_CONN11_3 0x30e8
-#define AFE_CONN11_4 0x30ec
-#define AFE_CONN12 0x30f0
-#define AFE_CONN12_1 0x30f4
-#define AFE_CONN12_2 0x30f8
-#define AFE_CONN12_3 0x30fc
-#define AFE_CONN12_4 0x3100
-#define AFE_CONN13 0x3104
-#define AFE_CONN13_1 0x3108
-#define AFE_CONN13_2 0x310c
-#define AFE_CONN13_3 0x3110
-#define AFE_CONN13_4 0x3114
-#define AFE_CONN14 0x3118
-#define AFE_CONN14_1 0x311c
-#define AFE_CONN14_2 0x3120
-#define AFE_CONN14_3 0x3124
-#define AFE_CONN14_4 0x3128
-#define AFE_CONN15 0x312c
-#define AFE_CONN15_1 0x3130
-#define AFE_CONN15_2 0x3134
-#define AFE_CONN15_3 0x3138
-#define AFE_CONN15_4 0x313c
-#define AFE_CONN16 0x3140
-#define AFE_CONN16_1 0x3144
-#define AFE_CONN16_2 0x3148
-#define AFE_CONN16_3 0x314c
-#define AFE_CONN16_4 0x3150
-#define AFE_CONN17 0x3154
-#define AFE_CONN17_1 0x3158
-#define AFE_CONN17_2 0x315c
-#define AFE_CONN17_3 0x3160
-#define AFE_CONN17_4 0x3164
-#define AFE_CONN18 0x3168
-#define AFE_CONN18_1 0x316c
-#define AFE_CONN18_2 0x3170
-#define AFE_CONN18_3 0x3174
-#define AFE_CONN18_4 0x3178
-#define AFE_CONN19 0x317c
-#define AFE_CONN19_1 0x3180
-#define AFE_CONN19_2 0x3184
-#define AFE_CONN19_3 0x3188
-#define AFE_CONN19_4 0x318c
-#define AFE_CONN20 0x3190
-#define AFE_CONN20_1 0x3194
-#define AFE_CONN20_2 0x3198
-#define AFE_CONN20_3 0x319c
-#define AFE_CONN20_4 0x31a0
-#define AFE_CONN21 0x31a4
-#define AFE_CONN21_1 0x31a8
-#define AFE_CONN21_2 0x31ac
-#define AFE_CONN21_3 0x31b0
-#define AFE_CONN21_4 0x31b4
-#define AFE_CONN22 0x31b8
-#define AFE_CONN22_1 0x31bc
-#define AFE_CONN22_2 0x31c0
-#define AFE_CONN22_3 0x31c4
-#define AFE_CONN22_4 0x31c8
-#define AFE_CONN23 0x31cc
-#define AFE_CONN23_1 0x31d0
-#define AFE_CONN23_2 0x31d4
-#define AFE_CONN23_3 0x31d8
-#define AFE_CONN23_4 0x31dc
-#define AFE_CONN24 0x31e0
-#define AFE_CONN24_1 0x31e4
-#define AFE_CONN24_2 0x31e8
-#define AFE_CONN24_3 0x31ec
-#define AFE_CONN24_4 0x31f0
-#define AFE_CONN25 0x31f4
-#define AFE_CONN25_1 0x31f8
-#define AFE_CONN25_2 0x31fc
-#define AFE_CONN25_3 0x3200
-#define AFE_CONN25_4 0x3204
-#define AFE_CONN26 0x3208
-#define AFE_CONN26_1 0x320c
-#define AFE_CONN26_2 0x3210
-#define AFE_CONN26_3 0x3214
-#define AFE_CONN26_4 0x3218
-#define AFE_CONN27 0x321c
-#define AFE_CONN27_1 0x3220
-#define AFE_CONN27_2 0x3224
-#define AFE_CONN27_3 0x3228
-#define AFE_CONN27_4 0x322c
-#define AFE_CONN28 0x3230
-#define AFE_CONN28_1 0x3234
-#define AFE_CONN28_2 0x3238
-#define AFE_CONN28_3 0x323c
-#define AFE_CONN28_4 0x3240
-#define AFE_CONN29 0x3244
-#define AFE_CONN29_1 0x3248
-#define AFE_CONN29_2 0x324c
-#define AFE_CONN29_3 0x3250
-#define AFE_CONN29_4 0x3254
-#define AFE_CONN30 0x3258
-#define AFE_CONN30_1 0x325c
-#define AFE_CONN30_2 0x3260
-#define AFE_CONN30_3 0x3264
-#define AFE_CONN30_4 0x3268
-#define AFE_CONN31 0x326c
-#define AFE_CONN31_1 0x3270
-#define AFE_CONN31_2 0x3274
-#define AFE_CONN31_3 0x3278
-#define AFE_CONN31_4 0x327c
-#define AFE_CONN32 0x3280
-#define AFE_CONN32_1 0x3284
-#define AFE_CONN32_2 0x3288
-#define AFE_CONN32_3 0x328c
-#define AFE_CONN32_4 0x3290
-#define AFE_CONN33 0x3294
-#define AFE_CONN33_1 0x3298
-#define AFE_CONN33_2 0x329c
-#define AFE_CONN33_3 0x32a0
-#define AFE_CONN33_4 0x32a4
-#define AFE_CONN34 0x32a8
-#define AFE_CONN34_1 0x32ac
-#define AFE_CONN34_2 0x32b0
-#define AFE_CONN34_3 0x32b4
-#define AFE_CONN34_4 0x32b8
-#define AFE_CONN35 0x32bc
-#define AFE_CONN35_1 0x32c0
-#define AFE_CONN35_2 0x32c4
-#define AFE_CONN35_3 0x32c8
-#define AFE_CONN35_4 0x32cc
-#define AFE_CONN36 0x32d0
-#define AFE_CONN36_1 0x32d4
-#define AFE_CONN36_2 0x32d8
-#define AFE_CONN36_3 0x32dc
-#define AFE_CONN36_4 0x32e0
-#define AFE_CONN37 0x32e4
-#define AFE_CONN37_1 0x32e8
-#define AFE_CONN37_2 0x32ec
-#define AFE_CONN37_3 0x32f0
-#define AFE_CONN37_4 0x32f4
-#define AFE_CONN38 0x32f8
-#define AFE_CONN38_1 0x32fc
-#define AFE_CONN38_2 0x3300
-#define AFE_CONN38_3 0x3304
-#define AFE_CONN38_4 0x3308
-#define AFE_CONN39 0x330c
-#define AFE_CONN39_1 0x3310
-#define AFE_CONN39_2 0x3314
-#define AFE_CONN39_3 0x3318
-#define AFE_CONN39_4 0x331c
-#define AFE_CONN40 0x3320
-#define AFE_CONN40_1 0x3324
-#define AFE_CONN40_2 0x3328
-#define AFE_CONN40_3 0x332c
-#define AFE_CONN40_4 0x3330
-#define AFE_CONN41 0x3334
-#define AFE_CONN41_1 0x3338
-#define AFE_CONN41_2 0x333c
-#define AFE_CONN41_3 0x3340
-#define AFE_CONN41_4 0x3344
-#define AFE_CONN42 0x3348
-#define AFE_CONN42_1 0x334c
-#define AFE_CONN42_2 0x3350
-#define AFE_CONN42_3 0x3354
-#define AFE_CONN42_4 0x3358
-#define AFE_CONN43 0x335c
-#define AFE_CONN43_1 0x3360
-#define AFE_CONN43_2 0x3364
-#define AFE_CONN43_3 0x3368
-#define AFE_CONN43_4 0x336c
-#define AFE_CONN44 0x3370
-#define AFE_CONN44_1 0x3374
-#define AFE_CONN44_2 0x3378
-#define AFE_CONN44_3 0x337c
-#define AFE_CONN44_4 0x3380
-#define AFE_CONN45 0x3384
-#define AFE_CONN45_1 0x3388
-#define AFE_CONN45_2 0x338c
-#define AFE_CONN45_3 0x3390
-#define AFE_CONN45_4 0x3394
-#define AFE_CONN46 0x3398
-#define AFE_CONN46_1 0x339c
-#define AFE_CONN46_2 0x33a0
-#define AFE_CONN46_3 0x33a4
-#define AFE_CONN46_4 0x33a8
-#define AFE_CONN47 0x33ac
-#define AFE_CONN47_1 0x33b0
-#define AFE_CONN47_2 0x33b4
-#define AFE_CONN47_3 0x33b8
-#define AFE_CONN47_4 0x33bc
-#define AFE_CONN48 0x33c0
-#define AFE_CONN48_1 0x33c4
-#define AFE_CONN48_2 0x33c8
-#define AFE_CONN48_3 0x33cc
-#define AFE_CONN48_4 0x33d0
-#define AFE_CONN49 0x33d4
-#define AFE_CONN49_1 0x33d8
-#define AFE_CONN49_2 0x33dc
-#define AFE_CONN49_3 0x33e0
-#define AFE_CONN49_4 0x33e4
-#define AFE_CONN50 0x33e8
-#define AFE_CONN50_1 0x33ec
-#define AFE_CONN50_2 0x33f0
-#define AFE_CONN50_3 0x33f4
-#define AFE_CONN50_4 0x33f8
-#define AFE_CONN51 0x33fc
-#define AFE_CONN51_1 0x3400
-#define AFE_CONN51_2 0x3404
-#define AFE_CONN51_3 0x3408
-#define AFE_CONN51_4 0x340c
-#define AFE_CONN52 0x3410
-#define AFE_CONN52_1 0x3414
-#define AFE_CONN52_2 0x3418
-#define AFE_CONN52_3 0x341c
-#define AFE_CONN52_4 0x3420
-#define AFE_CONN53 0x3424
-#define AFE_CONN53_1 0x3428
-#define AFE_CONN53_2 0x342c
-#define AFE_CONN53_3 0x3430
-#define AFE_CONN53_4 0x3434
-#define AFE_CONN54 0x3438
-#define AFE_CONN54_1 0x343c
-#define AFE_CONN54_2 0x3440
-#define AFE_CONN54_3 0x3444
-#define AFE_CONN54_4 0x3448
-#define AFE_CONN55 0x344c
-#define AFE_CONN55_1 0x3450
-#define AFE_CONN55_2 0x3454
-#define AFE_CONN55_3 0x3458
-#define AFE_CONN55_4 0x345c
-#define AFE_CONN56 0x3460
-#define AFE_CONN56_1 0x3464
-#define AFE_CONN56_2 0x3468
-#define AFE_CONN56_3 0x346c
-#define AFE_CONN56_4 0x3470
-#define AFE_CONN57 0x3474
-#define AFE_CONN57_1 0x3478
-#define AFE_CONN57_2 0x347c
-#define AFE_CONN57_3 0x3480
-#define AFE_CONN57_4 0x3484
-#define AFE_CONN58 0x3488
-#define AFE_CONN58_1 0x348c
-#define AFE_CONN58_2 0x3490
-#define AFE_CONN58_3 0x3494
-#define AFE_CONN58_4 0x3498
-#define AFE_CONN59 0x349c
-#define AFE_CONN59_1 0x34a0
-#define AFE_CONN59_2 0x34a4
-#define AFE_CONN59_3 0x34a8
-#define AFE_CONN59_4 0x34ac
-#define AFE_CONN60 0x34b0
-#define AFE_CONN60_1 0x34b4
-#define AFE_CONN60_2 0x34b8
-#define AFE_CONN60_3 0x34bc
-#define AFE_CONN60_4 0x34c0
-#define AFE_CONN61 0x34c4
-#define AFE_CONN61_1 0x34c8
-#define AFE_CONN61_2 0x34cc
-#define AFE_CONN61_3 0x34d0
-#define AFE_CONN61_4 0x34d4
-#define AFE_CONN62 0x34d8
-#define AFE_CONN62_1 0x34dc
-#define AFE_CONN62_2 0x34e0
-#define AFE_CONN62_3 0x34e4
-#define AFE_CONN62_4 0x34e8
-#define AFE_CONN63 0x34ec
-#define AFE_CONN63_1 0x34f0
-#define AFE_CONN63_2 0x34f4
-#define AFE_CONN63_3 0x34f8
-#define AFE_CONN63_4 0x34fc
-#define AFE_CONN64 0x3500
-#define AFE_CONN64_1 0x3504
-#define AFE_CONN64_2 0x3508
-#define AFE_CONN64_3 0x350c
-#define AFE_CONN64_4 0x3510
-#define AFE_CONN65 0x3514
-#define AFE_CONN65_1 0x3518
-#define AFE_CONN65_2 0x351c
-#define AFE_CONN65_3 0x3520
-#define AFE_CONN65_4 0x3524
-#define AFE_CONN66 0x3528
-#define AFE_CONN66_1 0x352c
-#define AFE_CONN66_2 0x3530
-#define AFE_CONN66_3 0x3534
-#define AFE_CONN66_4 0x3538
-#define AFE_CONN67 0x353c
-#define AFE_CONN67_1 0x3540
-#define AFE_CONN67_2 0x3544
-#define AFE_CONN67_3 0x3548
-#define AFE_CONN67_4 0x354c
-#define AFE_CONN68 0x3550
-#define AFE_CONN68_1 0x3554
-#define AFE_CONN68_2 0x3558
-#define AFE_CONN68_3 0x355c
-#define AFE_CONN68_4 0x3560
-#define AFE_CONN69 0x3564
-#define AFE_CONN69_1 0x3568
-#define AFE_CONN69_2 0x356c
-#define AFE_CONN69_3 0x3570
-#define AFE_CONN69_4 0x3574
-#define AFE_CONN70 0x3578
-#define AFE_CONN70_1 0x357c
-#define AFE_CONN70_2 0x3580
-#define AFE_CONN70_3 0x3584
-#define AFE_CONN70_4 0x3588
-#define AFE_CONN71 0x358c
-#define AFE_CONN71_1 0x3590
-#define AFE_CONN71_2 0x3594
-#define AFE_CONN71_3 0x3598
-#define AFE_CONN71_4 0x359c
-#define AFE_CONN72 0x35a0
-#define AFE_CONN72_1 0x35a4
-#define AFE_CONN72_2 0x35a8
-#define AFE_CONN72_3 0x35ac
-#define AFE_CONN72_4 0x35b0
-#define AFE_CONN73 0x35b4
-#define AFE_CONN73_1 0x35b8
-#define AFE_CONN73_2 0x35bc
-#define AFE_CONN73_3 0x35c0
-#define AFE_CONN73_4 0x35c4
-#define AFE_CONN74 0x35c8
-#define AFE_CONN74_1 0x35cc
-#define AFE_CONN74_2 0x35d0
-#define AFE_CONN74_3 0x35d4
-#define AFE_CONN74_4 0x35d8
-#define AFE_CONN75 0x35dc
-#define AFE_CONN75_1 0x35e0
-#define AFE_CONN75_2 0x35e4
-#define AFE_CONN75_3 0x35e8
-#define AFE_CONN75_4 0x35ec
-#define AFE_CONN76 0x35f0
-#define AFE_CONN76_1 0x35f4
-#define AFE_CONN76_2 0x35f8
-#define AFE_CONN76_3 0x35fc
-#define AFE_CONN76_4 0x3600
-#define AFE_CONN77 0x3604
-#define AFE_CONN77_1 0x3608
-#define AFE_CONN77_2 0x360c
-#define AFE_CONN77_3 0x3610
-#define AFE_CONN77_4 0x3614
-#define AFE_CONN78 0x3618
-#define AFE_CONN78_1 0x361c
-#define AFE_CONN78_2 0x3620
-#define AFE_CONN78_3 0x3624
-#define AFE_CONN78_4 0x3628
-#define AFE_CONN79 0x362c
-#define AFE_CONN79_1 0x3630
-#define AFE_CONN79_2 0x3634
-#define AFE_CONN79_3 0x3638
-#define AFE_CONN79_4 0x363c
-#define AFE_CONN80 0x3640
-#define AFE_CONN80_1 0x3644
-#define AFE_CONN80_2 0x3648
-#define AFE_CONN80_3 0x364c
-#define AFE_CONN80_4 0x3650
-#define AFE_CONN81 0x3654
-#define AFE_CONN81_1 0x3658
-#define AFE_CONN81_2 0x365c
-#define AFE_CONN81_3 0x3660
-#define AFE_CONN81_4 0x3664
-#define AFE_CONN82 0x3668
-#define AFE_CONN82_1 0x366c
-#define AFE_CONN82_2 0x3670
-#define AFE_CONN82_3 0x3674
-#define AFE_CONN82_4 0x3678
-#define AFE_CONN83 0x367c
-#define AFE_CONN83_1 0x3680
-#define AFE_CONN83_2 0x3684
-#define AFE_CONN83_3 0x3688
-#define AFE_CONN83_4 0x368c
-#define AFE_CONN84 0x3690
-#define AFE_CONN84_1 0x3694
-#define AFE_CONN84_2 0x3698
-#define AFE_CONN84_3 0x369c
-#define AFE_CONN84_4 0x36a0
-#define AFE_CONN85 0x36a4
-#define AFE_CONN85_1 0x36a8
-#define AFE_CONN85_2 0x36ac
-#define AFE_CONN85_3 0x36b0
-#define AFE_CONN85_4 0x36b4
-#define AFE_CONN86 0x36b8
-#define AFE_CONN86_1 0x36bc
-#define AFE_CONN86_2 0x36c0
-#define AFE_CONN86_3 0x36c4
-#define AFE_CONN86_4 0x36c8
-#define AFE_CONN87 0x36cc
-#define AFE_CONN87_1 0x36d0
-#define AFE_CONN87_2 0x36d4
-#define AFE_CONN87_3 0x36d8
-#define AFE_CONN87_4 0x36dc
-#define AFE_CONN88 0x36e0
-#define AFE_CONN88_1 0x36e4
-#define AFE_CONN88_2 0x36e8
-#define AFE_CONN88_3 0x36ec
-#define AFE_CONN88_4 0x36f0
-#define AFE_CONN89 0x36f4
-#define AFE_CONN89_1 0x36f8
-#define AFE_CONN89_2 0x36fc
-#define AFE_CONN89_3 0x3700
-#define AFE_CONN89_4 0x3704
-#define AFE_CONN90 0x3708
-#define AFE_CONN90_1 0x370c
-#define AFE_CONN90_2 0x3710
-#define AFE_CONN90_3 0x3714
-#define AFE_CONN90_4 0x3718
-#define AFE_CONN91 0x371c
-#define AFE_CONN91_1 0x3720
-#define AFE_CONN91_2 0x3724
-#define AFE_CONN91_3 0x3728
-#define AFE_CONN91_4 0x372c
-#define AFE_CONN92 0x3730
-#define AFE_CONN92_1 0x3734
-#define AFE_CONN92_2 0x3738
-#define AFE_CONN92_3 0x373c
-#define AFE_CONN92_4 0x3740
-#define AFE_CONN93 0x3744
-#define AFE_CONN93_1 0x3748
-#define AFE_CONN93_2 0x374c
-#define AFE_CONN93_3 0x3750
-#define AFE_CONN93_4 0x3754
-#define AFE_CONN94 0x3758
-#define AFE_CONN94_1 0x375c
-#define AFE_CONN94_2 0x3760
-#define AFE_CONN94_3 0x3764
-#define AFE_CONN94_4 0x3768
-#define AFE_CONN95 0x376c
-#define AFE_CONN95_1 0x3770
-#define AFE_CONN95_2 0x3774
-#define AFE_CONN95_3 0x3778
-#define AFE_CONN95_4 0x377c
-#define AFE_CONN96 0x3780
-#define AFE_CONN96_1 0x3784
-#define AFE_CONN96_2 0x3788
-#define AFE_CONN96_3 0x378c
-#define AFE_CONN96_4 0x3790
-#define AFE_CONN97 0x3794
-#define AFE_CONN97_1 0x3798
-#define AFE_CONN97_2 0x379c
-#define AFE_CONN97_3 0x37a0
-#define AFE_CONN97_4 0x37a4
-#define AFE_CONN98 0x37a8
-#define AFE_CONN98_1 0x37ac
-#define AFE_CONN98_2 0x37b0
-#define AFE_CONN98_3 0x37b4
-#define AFE_CONN98_4 0x37b8
-#define AFE_CONN99 0x37bc
-#define AFE_CONN99_1 0x37c0
-#define AFE_CONN99_2 0x37c4
-#define AFE_CONN99_3 0x37c8
-#define AFE_CONN99_4 0x37cc
-#define AFE_CONN100 0x37d0
-#define AFE_CONN100_1 0x37d4
-#define AFE_CONN100_2 0x37d8
-#define AFE_CONN100_3 0x37dc
-#define AFE_CONN100_4 0x37e0
-#define AFE_CONN101 0x37e4
-#define AFE_CONN101_1 0x37e8
-#define AFE_CONN101_2 0x37ec
-#define AFE_CONN101_3 0x37f0
-#define AFE_CONN101_4 0x37f4
-#define AFE_CONN102 0x37f8
-#define AFE_CONN102_1 0x37fc
-#define AFE_CONN102_2 0x3800
-#define AFE_CONN102_3 0x3804
-#define AFE_CONN102_4 0x3808
-#define AFE_CONN103 0x380c
-#define AFE_CONN103_1 0x3810
-#define AFE_CONN103_2 0x3814
-#define AFE_CONN103_3 0x3818
-#define AFE_CONN103_4 0x381c
-#define AFE_CONN104 0x3820
-#define AFE_CONN104_1 0x3824
-#define AFE_CONN104_2 0x3828
-#define AFE_CONN104_3 0x382c
-#define AFE_CONN104_4 0x3830
-#define AFE_CONN105 0x3834
-#define AFE_CONN105_1 0x3838
-#define AFE_CONN105_2 0x383c
-#define AFE_CONN105_3 0x3840
-#define AFE_CONN105_4 0x3844
-#define AFE_CONN106 0x3848
-#define AFE_CONN106_1 0x384c
-#define AFE_CONN106_2 0x3850
-#define AFE_CONN106_3 0x3854
-#define AFE_CONN106_4 0x3858
-#define AFE_CONN107 0x385c
-#define AFE_CONN107_1 0x3860
-#define AFE_CONN107_2 0x3864
-#define AFE_CONN107_3 0x3868
-#define AFE_CONN107_4 0x386c
-#define AFE_CONN108 0x3870
-#define AFE_CONN108_1 0x3874
-#define AFE_CONN108_2 0x3878
-#define AFE_CONN108_3 0x387c
-#define AFE_CONN108_4 0x3880
-#define AFE_CONN109 0x3884
-#define AFE_CONN109_1 0x3888
-#define AFE_CONN109_2 0x388c
-#define AFE_CONN109_3 0x3890
-#define AFE_CONN109_4 0x3894
-#define AFE_CONN110 0x3898
-#define AFE_CONN110_1 0x389c
-#define AFE_CONN110_2 0x38a0
-#define AFE_CONN110_3 0x38a4
-#define AFE_CONN110_4 0x38a8
-#define AFE_CONN111 0x38ac
-#define AFE_CONN111_1 0x38b0
-#define AFE_CONN111_2 0x38b4
-#define AFE_CONN111_3 0x38b8
-#define AFE_CONN111_4 0x38bc
-#define AFE_CONN112 0x38c0
-#define AFE_CONN112_1 0x38c4
-#define AFE_CONN112_2 0x38c8
-#define AFE_CONN112_3 0x38cc
-#define AFE_CONN112_4 0x38d0
-#define AFE_CONN113 0x38d4
-#define AFE_CONN113_1 0x38d8
-#define AFE_CONN113_2 0x38dc
-#define AFE_CONN113_3 0x38e0
-#define AFE_CONN113_4 0x38e4
-#define AFE_CONN114 0x38e8
-#define AFE_CONN114_1 0x38ec
-#define AFE_CONN114_2 0x38f0
-#define AFE_CONN114_3 0x38f4
-#define AFE_CONN114_4 0x38f8
-#define AFE_CONN115 0x38fc
-#define AFE_CONN115_1 0x3900
-#define AFE_CONN115_2 0x3904
-#define AFE_CONN115_3 0x3908
-#define AFE_CONN115_4 0x390c
-#define AFE_CONN116 0x3910
-#define AFE_CONN116_1 0x3914
-#define AFE_CONN116_2 0x3918
-#define AFE_CONN116_3 0x391c
-#define AFE_CONN116_4 0x3920
-#define AFE_CONN117 0x3924
-#define AFE_CONN117_1 0x3928
-#define AFE_CONN117_2 0x392c
-#define AFE_CONN117_3 0x3930
-#define AFE_CONN117_4 0x3934
-#define AFE_CONN118 0x3938
-#define AFE_CONN118_1 0x393c
-#define AFE_CONN118_2 0x3940
-#define AFE_CONN118_3 0x3944
-#define AFE_CONN118_4 0x3948
-#define AFE_CONN119 0x394c
-#define AFE_CONN119_1 0x3950
-#define AFE_CONN119_2 0x3954
-#define AFE_CONN119_3 0x3958
-#define AFE_CONN119_4 0x395c
-#define AFE_CONN120 0x3960
-#define AFE_CONN120_1 0x3964
-#define AFE_CONN120_2 0x3968
-#define AFE_CONN120_3 0x396c
-#define AFE_CONN120_4 0x3970
-#define AFE_CONN121 0x3974
-#define AFE_CONN121_1 0x3978
-#define AFE_CONN121_2 0x397c
-#define AFE_CONN121_3 0x3980
-#define AFE_CONN121_4 0x3984
-#define AFE_CONN122 0x3988
-#define AFE_CONN122_1 0x398c
-#define AFE_CONN122_2 0x3990
-#define AFE_CONN122_3 0x3994
-#define AFE_CONN122_4 0x3998
-#define AFE_CONN123 0x399c
-#define AFE_CONN123_1 0x39a0
-#define AFE_CONN123_2 0x39a4
-#define AFE_CONN123_3 0x39a8
-#define AFE_CONN123_4 0x39ac
-#define AFE_CONN124 0x39b0
-#define AFE_CONN124_1 0x39b4
-#define AFE_CONN124_2 0x39b8
-#define AFE_CONN124_3 0x39bc
-#define AFE_CONN124_4 0x39c0
-#define AFE_CONN125 0x39c4
-#define AFE_CONN125_1 0x39c8
-#define AFE_CONN125_2 0x39cc
-#define AFE_CONN125_3 0x39d0
-#define AFE_CONN125_4 0x39d4
-#define AFE_CONN126 0x39d8
-#define AFE_CONN126_1 0x39dc
-#define AFE_CONN126_2 0x39e0
-#define AFE_CONN126_3 0x39e4
-#define AFE_CONN126_4 0x39e8
-#define AFE_CONN127 0x39ec
-#define AFE_CONN127_1 0x39f0
-#define AFE_CONN127_2 0x39f4
-#define AFE_CONN127_3 0x39f8
-#define AFE_CONN127_4 0x39fc
-#define AFE_CONN128 0x3a00
-#define AFE_CONN128_1 0x3a04
-#define AFE_CONN128_2 0x3a08
-#define AFE_CONN128_3 0x3a0c
-#define AFE_CONN128_4 0x3a10
-#define AFE_CONN129 0x3a14
-#define AFE_CONN129_1 0x3a18
-#define AFE_CONN129_2 0x3a1c
-#define AFE_CONN129_3 0x3a20
-#define AFE_CONN129_4 0x3a24
-#define AFE_CONN130 0x3a28
-#define AFE_CONN130_1 0x3a2c
-#define AFE_CONN130_2 0x3a30
-#define AFE_CONN130_3 0x3a34
-#define AFE_CONN130_4 0x3a38
-#define AFE_CONN131 0x3a3c
-#define AFE_CONN131_1 0x3a40
-#define AFE_CONN131_2 0x3a44
-#define AFE_CONN131_3 0x3a48
-#define AFE_CONN131_4 0x3a4c
-#define AFE_CONN132 0x3a50
-#define AFE_CONN132_1 0x3a54
-#define AFE_CONN132_2 0x3a58
-#define AFE_CONN132_3 0x3a5c
-#define AFE_CONN132_4 0x3a60
-#define AFE_CONN133 0x3a64
-#define AFE_CONN133_1 0x3a68
-#define AFE_CONN133_2 0x3a6c
-#define AFE_CONN133_3 0x3a70
-#define AFE_CONN133_4 0x3a74
-#define AFE_CONN134 0x3a78
-#define AFE_CONN134_1 0x3a7c
-#define AFE_CONN134_2 0x3a80
-#define AFE_CONN134_3 0x3a84
-#define AFE_CONN134_4 0x3a88
-#define AFE_CONN135 0x3a8c
-#define AFE_CONN135_1 0x3a90
-#define AFE_CONN135_2 0x3a94
-#define AFE_CONN135_3 0x3a98
-#define AFE_CONN135_4 0x3a9c
-#define AFE_CONN136 0x3aa0
-#define AFE_CONN136_1 0x3aa4
-#define AFE_CONN136_2 0x3aa8
-#define AFE_CONN136_3 0x3aac
-#define AFE_CONN136_4 0x3ab0
-#define AFE_CONN137 0x3ab4
-#define AFE_CONN137_1 0x3ab8
-#define AFE_CONN137_2 0x3abc
-#define AFE_CONN137_3 0x3ac0
-#define AFE_CONN137_4 0x3ac4
-#define AFE_CONN138 0x3ac8
-#define AFE_CONN138_1 0x3acc
-#define AFE_CONN138_2 0x3ad0
-#define AFE_CONN138_3 0x3ad4
-#define AFE_CONN138_4 0x3ad8
-#define AFE_CONN139 0x3adc
-#define AFE_CONN139_1 0x3ae0
-#define AFE_CONN139_2 0x3ae4
-#define AFE_CONN139_3 0x3ae8
-#define AFE_CONN139_4 0x3aec
-#define AFE_CONN_RS 0x3af0
-#define AFE_CONN_RS_1 0x3af4
-#define AFE_CONN_RS_2 0x3af8
-#define AFE_CONN_RS_3 0x3afc
-#define AFE_CONN_RS_4 0x3b00
-#define AFE_CONN_16BIT 0x3b04
-#define AFE_CONN_16BIT_1 0x3b08
-#define AFE_CONN_16BIT_2 0x3b0c
-#define AFE_CONN_16BIT_3 0x3b10
-#define AFE_CONN_16BIT_4 0x3b14
-#define AFE_CONN_24BIT 0x3b18
-#define AFE_CONN_24BIT_1 0x3b1c
-#define AFE_CONN_24BIT_2 0x3b20
-#define AFE_CONN_24BIT_3 0x3b24
-#define AFE_CONN_24BIT_4 0x3b28
-#define AFE_CONN_DI 0x3b2c
-#define AFE_CONN_DI_1 0x3b30
-#define AFE_CONN_DI_2 0x3b34
-#define AFE_CONN_DI_3 0x3b38
-#define AFE_CONN_DI_4 0x3b3c
-#define AFE_CONN176 0x3ea0
-#define AFE_CONN176_1 0x3ea4
-#define AFE_CONN176_2 0x3ea8
-#define AFE_CONN176_3 0x3eac
-#define AFE_CONN176_4 0x3eb0
-#define AFE_CONN176_5 0x3eb4
-#define AFE_CONN177 0x3eb8
-#define AFE_CONN177_1 0x3ebc
-#define AFE_CONN177_2 0x3ec0
-#define AFE_CONN177_3 0x3ec4
-#define AFE_CONN177_4 0x3ec8
-#define AFE_CONN177_5 0x3ecc
-#define AFE_CONN182 0x3f30
-#define AFE_CONN182_1 0x3f34
-#define AFE_CONN182_2 0x3f38
-#define AFE_CONN182_3 0x3f3c
-#define AFE_CONN182_4 0x3f40
-#define AFE_CONN182_5 0x3f44
-#define AFE_CONN183 0x3f48
-#define AFE_CONN183_1 0x3f4c
-#define AFE_CONN183_2 0x3f50
-#define AFE_CONN183_3 0x3f54
-#define AFE_CONN183_4 0x3f58
-#define AFE_CONN183_5 0x3f5c
-#define AFE_SECURE_MASK_CONN0 0x4000
-#define AFE_SECURE_MASK_CONN0_1 0x4004
-#define AFE_SECURE_MASK_CONN0_2 0x4008
-#define AFE_SECURE_MASK_CONN0_3 0x400c
-#define AFE_SECURE_MASK_CONN0_4 0x4010
-#define AFE_SECURE_MASK_CONN1 0x4014
-#define AFE_SECURE_MASK_CONN1_1 0x4018
-#define AFE_SECURE_MASK_CONN1_2 0x401c
-#define AFE_SECURE_MASK_CONN1_3 0x4020
-#define AFE_SECURE_MASK_CONN1_4 0x4024
-#define AFE_SECURE_MASK_CONN2 0x4028
-#define AFE_SECURE_MASK_CONN2_1 0x402c
-#define AFE_SECURE_MASK_CONN2_2 0x4030
-#define AFE_SECURE_MASK_CONN2_3 0x4034
-#define AFE_SECURE_MASK_CONN2_4 0x4038
-#define AFE_SECURE_MASK_CONN3 0x403c
-#define AFE_SECURE_MASK_CONN3_1 0x4040
-#define AFE_SECURE_MASK_CONN3_2 0x4044
-#define AFE_SECURE_MASK_CONN3_3 0x4048
-#define AFE_SECURE_MASK_CONN3_4 0x404c
-#define AFE_SECURE_MASK_CONN4 0x4050
-#define AFE_SECURE_MASK_CONN4_1 0x4054
-#define AFE_SECURE_MASK_CONN4_2 0x4058
-#define AFE_SECURE_MASK_CONN4_3 0x405c
-#define AFE_SECURE_MASK_CONN4_4 0x4060
-#define AFE_SECURE_MASK_CONN5 0x4064
-#define AFE_SECURE_MASK_CONN5_1 0x4068
-#define AFE_SECURE_MASK_CONN5_2 0x406c
-#define AFE_SECURE_MASK_CONN5_3 0x4070
-#define AFE_SECURE_MASK_CONN5_4 0x4074
-#define AFE_SECURE_MASK_CONN6 0x4078
-#define AFE_SECURE_MASK_CONN6_1 0x407c
-#define AFE_SECURE_MASK_CONN6_2 0x4080
-#define AFE_SECURE_MASK_CONN6_3 0x4084
-#define AFE_SECURE_MASK_CONN6_4 0x4088
-#define AFE_SECURE_MASK_CONN7 0x408c
-#define AFE_SECURE_MASK_CONN7_1 0x4090
-#define AFE_SECURE_MASK_CONN7_2 0x4094
-#define AFE_SECURE_MASK_CONN7_3 0x4098
-#define AFE_SECURE_MASK_CONN7_4 0x409c
-#define AFE_SECURE_MASK_CONN8 0x40a0
-#define AFE_SECURE_MASK_CONN8_1 0x40a4
-#define AFE_SECURE_MASK_CONN8_2 0x40a8
-#define AFE_SECURE_MASK_CONN8_3 0x40ac
-#define AFE_SECURE_MASK_CONN8_4 0x40b0
-#define AFE_SECURE_MASK_CONN9 0x40b4
-#define AFE_SECURE_MASK_CONN9_1 0x40b8
-#define AFE_SECURE_MASK_CONN9_2 0x40bc
-#define AFE_SECURE_MASK_CONN9_3 0x40c0
-#define AFE_SECURE_MASK_CONN9_4 0x40c4
-#define AFE_SECURE_MASK_CONN10 0x40c8
-#define AFE_SECURE_MASK_CONN10_1 0x40cc
-#define AFE_SECURE_MASK_CONN10_2 0x40d0
-#define AFE_SECURE_MASK_CONN10_3 0x40d4
-#define AFE_SECURE_MASK_CONN10_4 0x40d8
-#define AFE_SECURE_MASK_CONN11 0x40dc
-#define AFE_SECURE_MASK_CONN11_1 0x40e0
-#define AFE_SECURE_MASK_CONN11_2 0x40e4
-#define AFE_SECURE_MASK_CONN11_3 0x40e8
-#define AFE_SECURE_MASK_CONN11_4 0x40ec
-#define AFE_SECURE_MASK_CONN12 0x40f0
-#define AFE_SECURE_MASK_CONN12_1 0x40f4
-#define AFE_SECURE_MASK_CONN12_2 0x40f8
-#define AFE_SECURE_MASK_CONN12_3 0x40fc
-#define AFE_SECURE_MASK_CONN12_4 0x4100
-#define AFE_SECURE_MASK_CONN13 0x4104
-#define AFE_SECURE_MASK_CONN13_1 0x4108
-#define AFE_SECURE_MASK_CONN13_2 0x410c
-#define AFE_SECURE_MASK_CONN13_3 0x4110
-#define AFE_SECURE_MASK_CONN13_4 0x4114
-#define AFE_SECURE_MASK_CONN14 0x4118
-#define AFE_SECURE_MASK_CONN14_1 0x411c
-#define AFE_SECURE_MASK_CONN14_2 0x4120
-#define AFE_SECURE_MASK_CONN14_3 0x4124
-#define AFE_SECURE_MASK_CONN14_4 0x4128
-#define AFE_SECURE_MASK_CONN15 0x412c
-#define AFE_SECURE_MASK_CONN15_1 0x4130
-#define AFE_SECURE_MASK_CONN15_2 0x4134
-#define AFE_SECURE_MASK_CONN15_3 0x4138
-#define AFE_SECURE_MASK_CONN15_4 0x413c
-#define AFE_SECURE_MASK_CONN16 0x4140
-#define AFE_SECURE_MASK_CONN16_1 0x4144
-#define AFE_SECURE_MASK_CONN16_2 0x4148
-#define AFE_SECURE_MASK_CONN16_3 0x414c
-#define AFE_SECURE_MASK_CONN16_4 0x4150
-#define AFE_SECURE_MASK_CONN17 0x4154
-#define AFE_SECURE_MASK_CONN17_1 0x4158
-#define AFE_SECURE_MASK_CONN17_2 0x415c
-#define AFE_SECURE_MASK_CONN17_3 0x4160
-#define AFE_SECURE_MASK_CONN17_4 0x4164
-#define AFE_SECURE_MASK_CONN18 0x4168
-#define AFE_SECURE_MASK_CONN18_1 0x416c
-#define AFE_SECURE_MASK_CONN18_2 0x4170
-#define AFE_SECURE_MASK_CONN18_3 0x4174
-#define AFE_SECURE_MASK_CONN18_4 0x4178
-#define AFE_SECURE_MASK_CONN19 0x417c
-#define AFE_SECURE_MASK_CONN19_1 0x4180
-#define AFE_SECURE_MASK_CONN19_2 0x4184
-#define AFE_SECURE_MASK_CONN19_3 0x4188
-#define AFE_SECURE_MASK_CONN19_4 0x418c
-#define AFE_SECURE_MASK_CONN20 0x4190
-#define AFE_SECURE_MASK_CONN20_1 0x4194
-#define AFE_SECURE_MASK_CONN20_2 0x4198
-#define AFE_SECURE_MASK_CONN20_3 0x419c
-#define AFE_SECURE_MASK_CONN20_4 0x41a0
-#define AFE_SECURE_MASK_CONN21 0x41a4
-#define AFE_SECURE_MASK_CONN21_1 0x41a8
-#define AFE_SECURE_MASK_CONN21_2 0x41ac
-#define AFE_SECURE_MASK_CONN21_3 0x41b0
-#define AFE_SECURE_MASK_CONN21_4 0x41b4
-#define AFE_SECURE_MASK_CONN22 0x41b8
-#define AFE_SECURE_MASK_CONN22_1 0x41bc
-#define AFE_SECURE_MASK_CONN22_2 0x41c0
-#define AFE_SECURE_MASK_CONN22_3 0x41c4
-#define AFE_SECURE_MASK_CONN22_4 0x41c8
-#define AFE_SECURE_MASK_CONN23 0x41cc
-#define AFE_SECURE_MASK_CONN23_1 0x41d0
-#define AFE_SECURE_MASK_CONN23_2 0x41d4
-#define AFE_SECURE_MASK_CONN23_3 0x41d8
-#define AFE_SECURE_MASK_CONN23_4 0x41dc
-#define AFE_SECURE_MASK_CONN24 0x41e0
-#define AFE_SECURE_MASK_CONN24_1 0x41e4
-#define AFE_SECURE_MASK_CONN24_2 0x41e8
-#define AFE_SECURE_MASK_CONN24_3 0x41ec
-#define AFE_SECURE_MASK_CONN24_4 0x41f0
-#define AFE_SECURE_MASK_CONN25 0x41f4
-#define AFE_SECURE_MASK_CONN25_1 0x41f8
-#define AFE_SECURE_MASK_CONN25_2 0x41fc
-#define AFE_SECURE_MASK_CONN25_3 0x4200
-#define AFE_SECURE_MASK_CONN25_4 0x4204
-#define AFE_SECURE_MASK_CONN26 0x4208
-#define AFE_SECURE_MASK_CONN26_1 0x420c
-#define AFE_SECURE_MASK_CONN26_2 0x4210
-#define AFE_SECURE_MASK_CONN26_3 0x4214
-#define AFE_SECURE_MASK_CONN26_4 0x4218
-#define AFE_SECURE_MASK_CONN27 0x421c
-#define AFE_SECURE_MASK_CONN27_1 0x4220
-#define AFE_SECURE_MASK_CONN27_2 0x4224
-#define AFE_SECURE_MASK_CONN27_3 0x4228
-#define AFE_SECURE_MASK_CONN27_4 0x422c
-#define AFE_SECURE_MASK_CONN28 0x4230
-#define AFE_SECURE_MASK_CONN28_1 0x4234
-#define AFE_SECURE_MASK_CONN28_2 0x4238
-#define AFE_SECURE_MASK_CONN28_3 0x423c
-#define AFE_SECURE_MASK_CONN28_4 0x4240
-#define AFE_SECURE_MASK_CONN29 0x4244
-#define AFE_SECURE_MASK_CONN29_1 0x4248
-#define AFE_SECURE_MASK_CONN29_2 0x424c
-#define AFE_SECURE_MASK_CONN29_3 0x4250
-#define AFE_SECURE_MASK_CONN29_4 0x4254
-#define AFE_SECURE_MASK_CONN30 0x4258
-#define AFE_SECURE_MASK_CONN30_1 0x425c
-#define AFE_SECURE_MASK_CONN30_2 0x4260
-#define AFE_SECURE_MASK_CONN30_3 0x4264
-#define AFE_SECURE_MASK_CONN30_4 0x4268
-#define AFE_SECURE_MASK_CONN31 0x426c
-#define AFE_SECURE_MASK_CONN31_1 0x4270
-#define AFE_SECURE_MASK_CONN31_2 0x4274
-#define AFE_SECURE_MASK_CONN31_3 0x4278
-#define AFE_SECURE_MASK_CONN31_4 0x427c
-#define AFE_SECURE_MASK_CONN32 0x4280
-#define AFE_SECURE_MASK_CONN32_1 0x4284
-#define AFE_SECURE_MASK_CONN32_2 0x4288
-#define AFE_SECURE_MASK_CONN32_3 0x428c
-#define AFE_SECURE_MASK_CONN32_4 0x4290
-#define AFE_SECURE_MASK_CONN33 0x4294
-#define AFE_SECURE_MASK_CONN33_1 0x4298
-#define AFE_SECURE_MASK_CONN33_2 0x429c
-#define AFE_SECURE_MASK_CONN33_3 0x42a0
-#define AFE_SECURE_MASK_CONN33_4 0x42a4
-#define AFE_SECURE_MASK_CONN34 0x42a8
-#define AFE_SECURE_MASK_CONN34_1 0x42ac
-#define AFE_SECURE_MASK_CONN34_2 0x42b0
-#define AFE_SECURE_MASK_CONN34_3 0x42b4
-#define AFE_SECURE_MASK_CONN34_4 0x42b8
-#define AFE_SECURE_MASK_CONN35 0x42bc
-#define AFE_SECURE_MASK_CONN35_1 0x42c0
-#define AFE_SECURE_MASK_CONN35_2 0x42c4
-#define AFE_SECURE_MASK_CONN35_3 0x42c8
-#define AFE_SECURE_MASK_CONN35_4 0x42cc
-#define AFE_SECURE_MASK_CONN36 0x42d0
-#define AFE_SECURE_MASK_CONN36_1 0x42d4
-#define AFE_SECURE_MASK_CONN36_2 0x42d8
-#define AFE_SECURE_MASK_CONN36_3 0x42dc
-#define AFE_SECURE_MASK_CONN36_4 0x42e0
-#define AFE_SECURE_MASK_CONN37 0x42e4
-#define AFE_SECURE_MASK_CONN37_1 0x42e8
-#define AFE_SECURE_MASK_CONN37_2 0x42ec
-#define AFE_SECURE_MASK_CONN37_3 0x42f0
-#define AFE_SECURE_MASK_CONN37_4 0x42f4
-#define AFE_SECURE_MASK_CONN38 0x42f8
-#define AFE_SECURE_MASK_CONN38_1 0x42fc
-#define AFE_SECURE_MASK_CONN38_2 0x4300
-#define AFE_SECURE_MASK_CONN38_3 0x4304
-#define AFE_SECURE_MASK_CONN38_4 0x4308
-#define AFE_SECURE_MASK_CONN39 0x430c
-#define AFE_SECURE_MASK_CONN39_1 0x4310
-#define AFE_SECURE_MASK_CONN39_2 0x4314
-#define AFE_SECURE_MASK_CONN39_3 0x4318
-#define AFE_SECURE_MASK_CONN39_4 0x431c
-#define AFE_SECURE_MASK_CONN40 0x4320
-#define AFE_SECURE_MASK_CONN40_1 0x4324
-#define AFE_SECURE_MASK_CONN40_2 0x4328
-#define AFE_SECURE_MASK_CONN40_3 0x432c
-#define AFE_SECURE_MASK_CONN40_4 0x4330
-#define AFE_SECURE_MASK_CONN41 0x4334
-#define AFE_SECURE_MASK_CONN41_1 0x4338
-#define AFE_SECURE_MASK_CONN41_2 0x433c
-#define AFE_SECURE_MASK_CONN41_3 0x4340
-#define AFE_SECURE_MASK_CONN41_4 0x4344
-#define AFE_SECURE_MASK_CONN42 0x4348
-#define AFE_SECURE_MASK_CONN42_1 0x434c
-#define AFE_SECURE_MASK_CONN42_2 0x4350
-#define AFE_SECURE_MASK_CONN42_3 0x4354
-#define AFE_SECURE_MASK_CONN42_4 0x4358
-#define AFE_SECURE_MASK_CONN43 0x435c
-#define AFE_SECURE_MASK_CONN43_1 0x4360
-#define AFE_SECURE_MASK_CONN43_2 0x4364
-#define AFE_SECURE_MASK_CONN43_3 0x4368
-#define AFE_SECURE_MASK_CONN43_4 0x436c
-#define AFE_SECURE_MASK_CONN44 0x4370
-#define AFE_SECURE_MASK_CONN44_1 0x4374
-#define AFE_SECURE_MASK_CONN44_2 0x4378
-#define AFE_SECURE_MASK_CONN44_3 0x437c
-#define AFE_SECURE_MASK_CONN44_4 0x4380
-#define AFE_SECURE_MASK_CONN45 0x4384
-#define AFE_SECURE_MASK_CONN45_1 0x4388
-#define AFE_SECURE_MASK_CONN45_2 0x438c
-#define AFE_SECURE_MASK_CONN45_3 0x4390
-#define AFE_SECURE_MASK_CONN45_4 0x4394
-#define AFE_SECURE_MASK_CONN46 0x4398
-#define AFE_SECURE_MASK_CONN46_1 0x439c
-#define AFE_SECURE_MASK_CONN46_2 0x43a0
-#define AFE_SECURE_MASK_CONN46_3 0x43a4
-#define AFE_SECURE_MASK_CONN46_4 0x43a8
-#define AFE_SECURE_MASK_CONN47 0x43ac
-#define AFE_SECURE_MASK_CONN47_1 0x43b0
-#define AFE_SECURE_MASK_CONN47_2 0x43b4
-#define AFE_SECURE_MASK_CONN47_3 0x43b8
-#define AFE_SECURE_MASK_CONN47_4 0x43bc
-#define AFE_SECURE_MASK_CONN48 0x43c0
-#define AFE_SECURE_MASK_CONN48_1 0x43c4
-#define AFE_SECURE_MASK_CONN48_2 0x43c8
-#define AFE_SECURE_MASK_CONN48_3 0x43cc
-#define AFE_SECURE_MASK_CONN48_4 0x43d0
-#define AFE_SECURE_MASK_CONN49 0x43d4
-#define AFE_SECURE_MASK_CONN49_1 0x43d8
-#define AFE_SECURE_MASK_CONN49_2 0x43dc
-#define AFE_SECURE_MASK_CONN49_3 0x43e0
-#define AFE_SECURE_MASK_CONN49_4 0x43e4
-#define AFE_SECURE_MASK_CONN50 0x43e8
-#define AFE_SECURE_MASK_CONN50_1 0x43ec
-#define AFE_SECURE_MASK_CONN50_2 0x43f0
-#define AFE_SECURE_MASK_CONN50_3 0x43f4
-#define AFE_SECURE_MASK_CONN50_4 0x43f8
-#define AFE_SECURE_MASK_CONN51 0x43fc
-#define AFE_SECURE_MASK_CONN51_1 0x4400
-#define AFE_SECURE_MASK_CONN51_2 0x4404
-#define AFE_SECURE_MASK_CONN51_3 0x4408
-#define AFE_SECURE_MASK_CONN51_4 0x440c
-#define AFE_SECURE_MASK_CONN52 0x4410
-#define AFE_SECURE_MASK_CONN52_1 0x4414
-#define AFE_SECURE_MASK_CONN52_2 0x4418
-#define AFE_SECURE_MASK_CONN52_3 0x441c
-#define AFE_SECURE_MASK_CONN52_4 0x4420
-#define AFE_SECURE_MASK_CONN53 0x4424
-#define AFE_SECURE_MASK_CONN53_1 0x4428
-#define AFE_SECURE_MASK_CONN53_2 0x442c
-#define AFE_SECURE_MASK_CONN53_3 0x4430
-#define AFE_SECURE_MASK_CONN53_4 0x4434
-#define AFE_SECURE_MASK_CONN54 0x4438
-#define AFE_SECURE_MASK_CONN54_1 0x443c
-#define AFE_SECURE_MASK_CONN54_2 0x4440
-#define AFE_SECURE_MASK_CONN54_3 0x4444
-#define AFE_SECURE_MASK_CONN54_4 0x4448
-#define AFE_SECURE_MASK_CONN55 0x444c
-#define AFE_SECURE_MASK_CONN55_1 0x4450
-#define AFE_SECURE_MASK_CONN55_2 0x4454
-#define AFE_SECURE_MASK_CONN55_3 0x4458
-#define AFE_SECURE_MASK_CONN55_4 0x445c
-#define AFE_SECURE_MASK_CONN56 0x4460
-#define AFE_SECURE_MASK_CONN56_1 0x4464
-#define AFE_SECURE_MASK_CONN56_2 0x4468
-#define AFE_SECURE_MASK_CONN56_3 0x446c
-#define AFE_SECURE_MASK_CONN56_4 0x4470
-#define AFE_SECURE_MASK_CONN57 0x4474
-#define AFE_SECURE_MASK_CONN57_1 0x4478
-#define AFE_SECURE_MASK_CONN57_2 0x447c
-#define AFE_SECURE_MASK_CONN57_3 0x4480
-#define AFE_SECURE_MASK_CONN57_4 0x4484
-#define AFE_SECURE_MASK_CONN58 0x4488
-#define AFE_SECURE_MASK_CONN58_1 0x448c
-#define AFE_SECURE_MASK_CONN58_2 0x4490
-#define AFE_SECURE_MASK_CONN58_3 0x4494
-#define AFE_SECURE_MASK_CONN58_4 0x4498
-#define AFE_SECURE_MASK_CONN59 0x449c
-#define AFE_SECURE_MASK_CONN59_1 0x44a0
-#define AFE_SECURE_MASK_CONN59_2 0x44a4
-#define AFE_SECURE_MASK_CONN59_3 0x44a8
-#define AFE_SECURE_MASK_CONN59_4 0x44ac
-#define AFE_SECURE_MASK_CONN60 0x44b0
-#define AFE_SECURE_MASK_CONN60_1 0x44b4
-#define AFE_SECURE_MASK_CONN60_2 0x44b8
-#define AFE_SECURE_MASK_CONN60_3 0x44bc
-#define AFE_SECURE_MASK_CONN60_4 0x44c0
-#define AFE_SECURE_MASK_CONN61 0x44c4
-#define AFE_SECURE_MASK_CONN61_1 0x44c8
-#define AFE_SECURE_MASK_CONN61_2 0x44cc
-#define AFE_SECURE_MASK_CONN61_3 0x44d0
-#define AFE_SECURE_MASK_CONN61_4 0x44d4
-#define AFE_SECURE_MASK_CONN62 0x44d8
-#define AFE_SECURE_MASK_CONN62_1 0x44dc
-#define AFE_SECURE_MASK_CONN62_2 0x44e0
-#define AFE_SECURE_MASK_CONN62_3 0x44e4
-#define AFE_SECURE_MASK_CONN62_4 0x44e8
-#define AFE_SECURE_MASK_CONN63 0x44ec
-#define AFE_SECURE_MASK_CONN63_1 0x44f0
-#define AFE_SECURE_MASK_CONN63_2 0x44f4
-#define AFE_SECURE_MASK_CONN63_3 0x44f8
-#define AFE_SECURE_MASK_CONN63_4 0x44fc
-#define AFE_SECURE_MASK_CONN64 0x4500
-#define AFE_SECURE_MASK_CONN64_1 0x4504
-#define AFE_SECURE_MASK_CONN64_2 0x4508
-#define AFE_SECURE_MASK_CONN64_3 0x450c
-#define AFE_SECURE_MASK_CONN64_4 0x4510
-#define AFE_SECURE_MASK_CONN65 0x4514
-#define AFE_SECURE_MASK_CONN65_1 0x4518
-#define AFE_SECURE_MASK_CONN65_2 0x451c
-#define AFE_SECURE_MASK_CONN65_3 0x4520
-#define AFE_SECURE_MASK_CONN65_4 0x4524
-#define AFE_SECURE_MASK_CONN66 0x4528
-#define AFE_SECURE_MASK_CONN66_1 0x452c
-#define AFE_SECURE_MASK_CONN66_2 0x4530
-#define AFE_SECURE_MASK_CONN66_3 0x4534
-#define AFE_SECURE_MASK_CONN66_4 0x4538
-#define AFE_SECURE_MASK_CONN67 0x453c
-#define AFE_SECURE_MASK_CONN67_1 0x4540
-#define AFE_SECURE_MASK_CONN67_2 0x4544
-#define AFE_SECURE_MASK_CONN67_3 0x4548
-#define AFE_SECURE_MASK_CONN67_4 0x454c
-#define AFE_SECURE_MASK_CONN68 0x4550
-#define AFE_SECURE_MASK_CONN68_1 0x4554
-#define AFE_SECURE_MASK_CONN68_2 0x4558
-#define AFE_SECURE_MASK_CONN68_3 0x455c
-#define AFE_SECURE_MASK_CONN68_4 0x4560
-#define AFE_SECURE_MASK_CONN69 0x4564
-#define AFE_SECURE_MASK_CONN69_1 0x4568
-#define AFE_SECURE_MASK_CONN69_2 0x456c
-#define AFE_SECURE_MASK_CONN69_3 0x4570
-#define AFE_SECURE_MASK_CONN69_4 0x4574
-#define AFE_SECURE_MASK_CONN70 0x4578
-#define AFE_SECURE_MASK_CONN70_1 0x457c
-#define AFE_SECURE_MASK_CONN70_2 0x4580
-#define AFE_SECURE_MASK_CONN70_3 0x4584
-#define AFE_SECURE_MASK_CONN70_4 0x4588
-#define AFE_SECURE_MASK_CONN71 0x458c
-#define AFE_SECURE_MASK_CONN71_1 0x4590
-#define AFE_SECURE_MASK_CONN71_2 0x4594
-#define AFE_SECURE_MASK_CONN71_3 0x4598
-#define AFE_SECURE_MASK_CONN71_4 0x459c
-#define AFE_SECURE_MASK_CONN72 0x45a0
-#define AFE_SECURE_MASK_CONN72_1 0x45a4
-#define AFE_SECURE_MASK_CONN72_2 0x45a8
-#define AFE_SECURE_MASK_CONN72_3 0x45ac
-#define AFE_SECURE_MASK_CONN72_4 0x45b0
-#define AFE_SECURE_MASK_CONN73 0x45b4
-#define AFE_SECURE_MASK_CONN73_1 0x45b8
-#define AFE_SECURE_MASK_CONN73_2 0x45bc
-#define AFE_SECURE_MASK_CONN73_3 0x45c0
-#define AFE_SECURE_MASK_CONN73_4 0x45c4
-#define AFE_SECURE_MASK_CONN74 0x45c8
-#define AFE_SECURE_MASK_CONN74_1 0x45cc
-#define AFE_SECURE_MASK_CONN74_2 0x45d0
-#define AFE_SECURE_MASK_CONN74_3 0x45d4
-#define AFE_SECURE_MASK_CONN74_4 0x45d8
-#define AFE_SECURE_MASK_CONN75 0x45dc
-#define AFE_SECURE_MASK_CONN75_1 0x45e0
-#define AFE_SECURE_MASK_CONN75_2 0x45e4
-#define AFE_SECURE_MASK_CONN75_3 0x45e8
-#define AFE_SECURE_MASK_CONN75_4 0x45ec
-#define AFE_SECURE_MASK_CONN76 0x45f0
-#define AFE_SECURE_MASK_CONN76_1 0x45f4
-#define AFE_SECURE_MASK_CONN76_2 0x45f8
-#define AFE_SECURE_MASK_CONN76_3 0x45fc
-#define AFE_SECURE_MASK_CONN76_4 0x4600
-#define AFE_SECURE_MASK_CONN77 0x4604
-#define AFE_SECURE_MASK_CONN77_1 0x4608
-#define AFE_SECURE_MASK_CONN77_2 0x460c
-#define AFE_SECURE_MASK_CONN77_3 0x4610
-#define AFE_SECURE_MASK_CONN77_4 0x4614
-#define AFE_SECURE_MASK_CONN78 0x4618
-#define AFE_SECURE_MASK_CONN78_1 0x461c
-#define AFE_SECURE_MASK_CONN78_2 0x4620
-#define AFE_SECURE_MASK_CONN78_3 0x4624
-#define AFE_SECURE_MASK_CONN78_4 0x4628
-#define AFE_SECURE_MASK_CONN79 0x462c
-#define AFE_SECURE_MASK_CONN79_1 0x4630
-#define AFE_SECURE_MASK_CONN79_2 0x4634
-#define AFE_SECURE_MASK_CONN79_3 0x4638
-#define AFE_SECURE_MASK_CONN79_4 0x463c
-#define AFE_SECURE_MASK_CONN80 0x4640
-#define AFE_SECURE_MASK_CONN80_1 0x4644
-#define AFE_SECURE_MASK_CONN80_2 0x4648
-#define AFE_SECURE_MASK_CONN80_3 0x464c
-#define AFE_SECURE_MASK_CONN80_4 0x4650
-#define AFE_SECURE_MASK_CONN81 0x4654
-#define AFE_SECURE_MASK_CONN81_1 0x4658
-#define AFE_SECURE_MASK_CONN81_2 0x465c
-#define AFE_SECURE_MASK_CONN81_3 0x4660
-#define AFE_SECURE_MASK_CONN81_4 0x4664
-#define AFE_SECURE_MASK_CONN82 0x4668
-#define AFE_SECURE_MASK_CONN82_1 0x466c
-#define AFE_SECURE_MASK_CONN82_2 0x4670
-#define AFE_SECURE_MASK_CONN82_3 0x4674
-#define AFE_SECURE_MASK_CONN82_4 0x4678
-#define AFE_SECURE_MASK_CONN83 0x467c
-#define AFE_SECURE_MASK_CONN83_1 0x4680
-#define AFE_SECURE_MASK_CONN83_2 0x4684
-#define AFE_SECURE_MASK_CONN83_3 0x4688
-#define AFE_SECURE_MASK_CONN83_4 0x468c
-#define AFE_SECURE_MASK_CONN84 0x4690
-#define AFE_SECURE_MASK_CONN84_1 0x4694
-#define AFE_SECURE_MASK_CONN84_2 0x4698
-#define AFE_SECURE_MASK_CONN84_3 0x469c
-#define AFE_SECURE_MASK_CONN84_4 0x46a0
-#define AFE_SECURE_MASK_CONN85 0x46a4
-#define AFE_SECURE_MASK_CONN85_1 0x46a8
-#define AFE_SECURE_MASK_CONN85_2 0x46ac
-#define AFE_SECURE_MASK_CONN85_3 0x46b0
-#define AFE_SECURE_MASK_CONN85_4 0x46b4
-#define AFE_SECURE_MASK_CONN86 0x46b8
-#define AFE_SECURE_MASK_CONN86_1 0x46bc
-#define AFE_SECURE_MASK_CONN86_2 0x46c0
-#define AFE_SECURE_MASK_CONN86_3 0x46c4
-#define AFE_SECURE_MASK_CONN86_4 0x46c8
-#define AFE_SECURE_MASK_CONN87 0x46cc
-#define AFE_SECURE_MASK_CONN87_1 0x46d0
-#define AFE_SECURE_MASK_CONN87_2 0x46d4
-#define AFE_SECURE_MASK_CONN87_3 0x46d8
-#define AFE_SECURE_MASK_CONN87_4 0x46dc
-#define AFE_SECURE_MASK_CONN88 0x46e0
-#define AFE_SECURE_MASK_CONN88_1 0x46e4
-#define AFE_SECURE_MASK_CONN88_2 0x46e8
-#define AFE_SECURE_MASK_CONN88_3 0x46ec
-#define AFE_SECURE_MASK_CONN88_4 0x46f0
-#define AFE_SECURE_MASK_CONN89 0x46f4
-#define AFE_SECURE_MASK_CONN89_1 0x46f8
-#define AFE_SECURE_MASK_CONN89_2 0x46fc
-#define AFE_SECURE_MASK_CONN89_3 0x4700
-#define AFE_SECURE_MASK_CONN89_4 0x4704
-#define AFE_SECURE_MASK_CONN90 0x4708
-#define AFE_SECURE_MASK_CONN90_1 0x470c
-#define AFE_SECURE_MASK_CONN90_2 0x4710
-#define AFE_SECURE_MASK_CONN90_3 0x4714
-#define AFE_SECURE_MASK_CONN90_4 0x4718
-#define AFE_SECURE_MASK_CONN91 0x471c
-#define AFE_SECURE_MASK_CONN91_1 0x4720
-#define AFE_SECURE_MASK_CONN91_2 0x4724
-#define AFE_SECURE_MASK_CONN91_3 0x4728
-#define AFE_SECURE_MASK_CONN91_4 0x472c
-#define AFE_SECURE_MASK_CONN92 0x4730
-#define AFE_SECURE_MASK_CONN92_1 0x4734
-#define AFE_SECURE_MASK_CONN92_2 0x4738
-#define AFE_SECURE_MASK_CONN92_3 0x473c
-#define AFE_SECURE_MASK_CONN92_4 0x4740
-#define AFE_SECURE_MASK_CONN93 0x4744
-#define AFE_SECURE_MASK_CONN93_1 0x4748
-#define AFE_SECURE_MASK_CONN93_2 0x474c
-#define AFE_SECURE_MASK_CONN93_3 0x4750
-#define AFE_SECURE_MASK_CONN93_4 0x4754
-#define AFE_SECURE_MASK_CONN94 0x4758
-#define AFE_SECURE_MASK_CONN94_1 0x475c
-#define AFE_SECURE_MASK_CONN94_2 0x4760
-#define AFE_SECURE_MASK_CONN94_3 0x4764
-#define AFE_SECURE_MASK_CONN94_4 0x4768
-#define AFE_SECURE_MASK_CONN95 0x476c
-#define AFE_SECURE_MASK_CONN95_1 0x4770
-#define AFE_SECURE_MASK_CONN95_2 0x4774
-#define AFE_SECURE_MASK_CONN95_3 0x4778
-#define AFE_SECURE_MASK_CONN95_4 0x477c
-#define AFE_SECURE_MASK_CONN96 0x4780
-#define AFE_SECURE_MASK_CONN96_1 0x4784
-#define AFE_SECURE_MASK_CONN96_2 0x4788
-#define AFE_SECURE_MASK_CONN96_3 0x478c
-#define AFE_SECURE_MASK_CONN96_4 0x4790
-#define AFE_SECURE_MASK_CONN97 0x4794
-#define AFE_SECURE_MASK_CONN97_1 0x4798
-#define AFE_SECURE_MASK_CONN97_2 0x479c
-#define AFE_SECURE_MASK_CONN97_3 0x47a0
-#define AFE_SECURE_MASK_CONN97_4 0x47a4
-#define AFE_SECURE_MASK_CONN98 0x47a8
-#define AFE_SECURE_MASK_CONN98_1 0x47ac
-#define AFE_SECURE_MASK_CONN98_2 0x47b0
-#define AFE_SECURE_MASK_CONN98_3 0x47b4
-#define AFE_SECURE_MASK_CONN98_4 0x47b8
-#define AFE_SECURE_MASK_CONN99 0x47bc
-#define AFE_SECURE_MASK_CONN99_1 0x47c0
-#define AFE_SECURE_MASK_CONN99_2 0x47c4
-#define AFE_SECURE_MASK_CONN99_3 0x47c8
-#define AFE_SECURE_MASK_CONN99_4 0x47cc
-#define AFE_SECURE_MASK_CONN100 0x47d0
-#define AFE_SECURE_MASK_CONN100_1 0x47d4
-#define AFE_SECURE_MASK_CONN100_2 0x47d8
-#define AFE_SECURE_MASK_CONN100_3 0x47dc
-#define AFE_SECURE_MASK_CONN100_4 0x47e0
-#define AFE_SECURE_MASK_CONN101 0x47e4
-#define AFE_SECURE_MASK_CONN101_1 0x47e8
-#define AFE_SECURE_MASK_CONN101_2 0x47ec
-#define AFE_SECURE_MASK_CONN101_3 0x47f0
-#define AFE_SECURE_MASK_CONN101_4 0x47f4
-#define AFE_SECURE_MASK_CONN102 0x47f8
-#define AFE_SECURE_MASK_CONN102_1 0x47fc
-#define AFE_SECURE_MASK_CONN102_2 0x4800
-#define AFE_SECURE_MASK_CONN102_3 0x4804
-#define AFE_SECURE_MASK_CONN102_4 0x4808
-#define AFE_SECURE_MASK_CONN103 0x480c
-#define AFE_SECURE_MASK_CONN103_1 0x4810
-#define AFE_SECURE_MASK_CONN103_2 0x4814
-#define AFE_SECURE_MASK_CONN103_3 0x4818
-#define AFE_SECURE_MASK_CONN103_4 0x481c
-#define AFE_SECURE_MASK_CONN104 0x4820
-#define AFE_SECURE_MASK_CONN104_1 0x4824
-#define AFE_SECURE_MASK_CONN104_2 0x4828
-#define AFE_SECURE_MASK_CONN104_3 0x482c
-#define AFE_SECURE_MASK_CONN104_4 0x4830
-#define AFE_SECURE_MASK_CONN105 0x4834
-#define AFE_SECURE_MASK_CONN105_1 0x4838
-#define AFE_SECURE_MASK_CONN105_2 0x483c
-#define AFE_SECURE_MASK_CONN105_3 0x4840
-#define AFE_SECURE_MASK_CONN105_4 0x4844
-#define AFE_SECURE_MASK_CONN106 0x4848
-#define AFE_SECURE_MASK_CONN106_1 0x484c
-#define AFE_SECURE_MASK_CONN106_2 0x4850
-#define AFE_SECURE_MASK_CONN106_3 0x4854
-#define AFE_SECURE_MASK_CONN106_4 0x4858
-#define AFE_SECURE_MASK_CONN107 0x485c
-#define AFE_SECURE_MASK_CONN107_1 0x4860
-#define AFE_SECURE_MASK_CONN107_2 0x4864
-#define AFE_SECURE_MASK_CONN107_3 0x4868
-#define AFE_SECURE_MASK_CONN107_4 0x486c
-#define AFE_SECURE_MASK_CONN108 0x4870
-#define AFE_SECURE_MASK_CONN108_1 0x4874
-#define AFE_SECURE_MASK_CONN108_2 0x4878
-#define AFE_SECURE_MASK_CONN108_3 0x487c
-#define AFE_SECURE_MASK_CONN108_4 0x4880
-#define AFE_SECURE_MASK_CONN109 0x4884
-#define AFE_SECURE_MASK_CONN109_1 0x4888
-#define AFE_SECURE_MASK_CONN109_2 0x488c
-#define AFE_SECURE_MASK_CONN109_3 0x4890
-#define AFE_SECURE_MASK_CONN109_4 0x4894
-#define AFE_SECURE_MASK_CONN110 0x4898
-#define AFE_SECURE_MASK_CONN110_1 0x489c
-#define AFE_SECURE_MASK_CONN110_2 0x48a0
-#define AFE_SECURE_MASK_CONN110_3 0x48a4
-#define AFE_SECURE_MASK_CONN110_4 0x48a8
-#define AFE_SECURE_MASK_CONN111 0x48ac
-#define AFE_SECURE_MASK_CONN111_1 0x48b0
-#define AFE_SECURE_MASK_CONN111_2 0x48b4
-#define AFE_SECURE_MASK_CONN111_3 0x48b8
-#define AFE_SECURE_MASK_CONN111_4 0x48bc
-#define AFE_SECURE_MASK_CONN112 0x48c0
-#define AFE_SECURE_MASK_CONN112_1 0x48c4
-#define AFE_SECURE_MASK_CONN112_2 0x48c8
-#define AFE_SECURE_MASK_CONN112_3 0x48cc
-#define AFE_SECURE_MASK_CONN112_4 0x48d0
-#define AFE_SECURE_MASK_CONN113 0x48d4
-#define AFE_SECURE_MASK_CONN113_1 0x48d8
-#define AFE_SECURE_MASK_CONN113_2 0x48dc
-#define AFE_SECURE_MASK_CONN113_3 0x48e0
-#define AFE_SECURE_MASK_CONN113_4 0x48e4
-#define AFE_SECURE_MASK_CONN114 0x48e8
-#define AFE_SECURE_MASK_CONN114_1 0x48ec
-#define AFE_SECURE_MASK_CONN114_2 0x48f0
-#define AFE_SECURE_MASK_CONN114_3 0x48f4
-#define AFE_SECURE_MASK_CONN114_4 0x48f8
-#define AFE_SECURE_MASK_CONN115 0x48fc
-#define AFE_SECURE_MASK_CONN115_1 0x4900
-#define AFE_SECURE_MASK_CONN115_2 0x4904
-#define AFE_SECURE_MASK_CONN115_3 0x4908
-#define AFE_SECURE_MASK_CONN115_4 0x490c
-#define AFE_SECURE_MASK_CONN116 0x4910
-#define AFE_SECURE_MASK_CONN116_1 0x4914
-#define AFE_SECURE_MASK_CONN116_2 0x4918
-#define AFE_SECURE_MASK_CONN116_3 0x491c
-#define AFE_SECURE_MASK_CONN116_4 0x4920
-#define AFE_SECURE_MASK_CONN117 0x4924
-#define AFE_SECURE_MASK_CONN117_1 0x4928
-#define AFE_SECURE_MASK_CONN117_2 0x492c
-#define AFE_SECURE_MASK_CONN117_3 0x4930
-#define AFE_SECURE_MASK_CONN117_4 0x4934
-#define AFE_SECURE_MASK_CONN118 0x4938
-#define AFE_SECURE_MASK_CONN118_1 0x493c
-#define AFE_SECURE_MASK_CONN118_2 0x4940
-#define AFE_SECURE_MASK_CONN118_3 0x4944
-#define AFE_SECURE_MASK_CONN118_4 0x4948
-#define AFE_SECURE_MASK_CONN119 0x494c
-#define AFE_SECURE_MASK_CONN119_1 0x4950
-#define AFE_SECURE_MASK_CONN119_2 0x4954
-#define AFE_SECURE_MASK_CONN119_3 0x4958
-#define AFE_SECURE_MASK_CONN119_4 0x495c
-#define AFE_SECURE_MASK_CONN120 0x4960
-#define AFE_SECURE_MASK_CONN120_1 0x4964
-#define AFE_SECURE_MASK_CONN120_2 0x4968
-#define AFE_SECURE_MASK_CONN120_3 0x496c
-#define AFE_SECURE_MASK_CONN120_4 0x4970
-#define AFE_SECURE_MASK_CONN121 0x4974
-#define AFE_SECURE_MASK_CONN121_1 0x4978
-#define AFE_SECURE_MASK_CONN121_2 0x497c
-#define AFE_SECURE_MASK_CONN121_3 0x4980
-#define AFE_SECURE_MASK_CONN121_4 0x4984
-#define AFE_SECURE_MASK_CONN122 0x4988
-#define AFE_SECURE_MASK_CONN122_1 0x498c
-#define AFE_SECURE_MASK_CONN122_2 0x4990
-#define AFE_SECURE_MASK_CONN122_3 0x4994
-#define AFE_SECURE_MASK_CONN122_4 0x4998
-#define AFE_SECURE_MASK_CONN123 0x499c
-#define AFE_SECURE_MASK_CONN123_1 0x49a0
-#define AFE_SECURE_MASK_CONN123_2 0x49a4
-#define AFE_SECURE_MASK_CONN123_3 0x49a8
-#define AFE_SECURE_MASK_CONN123_4 0x49ac
-#define AFE_SECURE_MASK_CONN124 0x49b0
-#define AFE_SECURE_MASK_CONN124_1 0x49b4
-#define AFE_SECURE_MASK_CONN124_2 0x49b8
-#define AFE_SECURE_MASK_CONN124_3 0x49bc
-#define AFE_SECURE_MASK_CONN124_4 0x49c0
-#define AFE_SECURE_MASK_CONN125 0x49c4
-#define AFE_SECURE_MASK_CONN125_1 0x49c8
-#define AFE_SECURE_MASK_CONN125_2 0x49cc
-#define AFE_SECURE_MASK_CONN125_3 0x49d0
-#define AFE_SECURE_MASK_CONN125_4 0x49d4
-#define AFE_SECURE_MASK_CONN126 0x49d8
-#define AFE_SECURE_MASK_CONN126_1 0x49dc
-#define AFE_SECURE_MASK_CONN126_2 0x49e0
-#define AFE_SECURE_MASK_CONN126_3 0x49e4
-#define AFE_SECURE_MASK_CONN126_4 0x49e8
-#define AFE_SECURE_MASK_CONN127 0x49ec
-#define AFE_SECURE_MASK_CONN127_1 0x49f0
-#define AFE_SECURE_MASK_CONN127_2 0x49f4
-#define AFE_SECURE_MASK_CONN127_3 0x49f8
-#define AFE_SECURE_MASK_CONN127_4 0x49fc
-#define AFE_SECURE_MASK_CONN128 0x4a00
-#define AFE_SECURE_MASK_CONN128_1 0x4a04
-#define AFE_SECURE_MASK_CONN128_2 0x4a08
-#define AFE_SECURE_MASK_CONN128_3 0x4a0c
-#define AFE_SECURE_MASK_CONN128_4 0x4a10
-#define AFE_SECURE_MASK_CONN129 0x4a14
-#define AFE_SECURE_MASK_CONN129_1 0x4a18
-#define AFE_SECURE_MASK_CONN129_2 0x4a1c
-#define AFE_SECURE_MASK_CONN129_3 0x4a20
-#define AFE_SECURE_MASK_CONN129_4 0x4a24
-#define AFE_SECURE_MASK_CONN130 0x4a28
-#define AFE_SECURE_MASK_CONN130_1 0x4a2c
-#define AFE_SECURE_MASK_CONN130_2 0x4a30
-#define AFE_SECURE_MASK_CONN130_3 0x4a34
-#define AFE_SECURE_MASK_CONN130_4 0x4a38
-#define AFE_SECURE_MASK_CONN131 0x4a3c
-#define AFE_SECURE_MASK_CONN131_1 0x4a40
-#define AFE_SECURE_MASK_CONN131_2 0x4a44
-#define AFE_SECURE_MASK_CONN131_3 0x4a48
-#define AFE_SECURE_MASK_CONN131_4 0x4a4c
-#define AFE_SECURE_MASK_CONN132 0x4a50
-#define AFE_SECURE_MASK_CONN132_1 0x4a54
-#define AFE_SECURE_MASK_CONN132_2 0x4a58
-#define AFE_SECURE_MASK_CONN132_3 0x4a5c
-#define AFE_SECURE_MASK_CONN132_4 0x4a60
-#define AFE_SECURE_MASK_CONN133 0x4a64
-#define AFE_SECURE_MASK_CONN133_1 0x4a68
-#define AFE_SECURE_MASK_CONN133_2 0x4a6c
-#define AFE_SECURE_MASK_CONN133_3 0x4a70
-#define AFE_SECURE_MASK_CONN133_4 0x4a74
-#define AFE_SECURE_MASK_CONN134 0x4a78
-#define AFE_SECURE_MASK_CONN134_1 0x4a7c
-#define AFE_SECURE_MASK_CONN134_2 0x4a80
-#define AFE_SECURE_MASK_CONN134_3 0x4a84
-#define AFE_SECURE_MASK_CONN134_4 0x4a88
-#define AFE_SECURE_MASK_CONN135 0x4a8c
-#define AFE_SECURE_MASK_CONN135_1 0x4a90
-#define AFE_SECURE_MASK_CONN135_2 0x4a94
-#define AFE_SECURE_MASK_CONN135_3 0x4a98
-#define AFE_SECURE_MASK_CONN135_4 0x4a9c
-#define AFE_SECURE_MASK_CONN136 0x4aa0
-#define AFE_SECURE_MASK_CONN136_1 0x4aa4
-#define AFE_SECURE_MASK_CONN136_2 0x4aa8
-#define AFE_SECURE_MASK_CONN136_3 0x4aac
-#define AFE_SECURE_MASK_CONN136_4 0x4ab0
-#define AFE_SECURE_MASK_CONN137 0x4ab4
-#define AFE_SECURE_MASK_CONN137_1 0x4ab8
-#define AFE_SECURE_MASK_CONN137_2 0x4abc
-#define AFE_SECURE_MASK_CONN137_3 0x4ac0
-#define AFE_SECURE_MASK_CONN137_4 0x4ac4
-#define AFE_SECURE_MASK_CONN138 0x4ac8
-#define AFE_SECURE_MASK_CONN138_1 0x4acc
-#define AFE_SECURE_MASK_CONN138_2 0x4ad0
-#define AFE_SECURE_MASK_CONN138_3 0x4ad4
-#define AFE_SECURE_MASK_CONN138_4 0x4ad8
-#define AFE_SECURE_MASK_CONN139 0x4adc
-#define AFE_SECURE_MASK_CONN139_1 0x4ae0
-#define AFE_SECURE_MASK_CONN139_2 0x4ae4
-#define AFE_SECURE_MASK_CONN139_3 0x4ae8
-#define AFE_SECURE_MASK_CONN139_4 0x4aec
-#define AFE_SECURE_MASK_CONN_RS 0x4af0
-#define AFE_SECURE_MASK_CONN_RS_1 0x4af4
-#define AFE_SECURE_MASK_CONN_RS_2 0x4af8
-#define AFE_SECURE_MASK_CONN_RS_3 0x4afc
-#define AFE_SECURE_MASK_CONN_RS_4 0x4b00
-#define AFE_SECURE_MASK_CONN_16BIT 0x4b04
-#define AFE_SECURE_MASK_CONN_16BIT_1 0x4b08
-#define AFE_SECURE_MASK_CONN_16BIT_2 0x4b0c
-#define AFE_SECURE_MASK_CONN_16BIT_3 0x4b10
-#define AFE_SECURE_MASK_CONN_16BIT_4 0x4b14
-#define AFE_SECURE_MASK_CONN_24BIT 0x4b18
-#define AFE_SECURE_MASK_CONN_24BIT_1 0x4b1c
-#define AFE_SECURE_MASK_CONN_24BIT_2 0x4b20
-#define AFE_SECURE_MASK_CONN_24BIT_3 0x4b24
-#define AFE_SECURE_MASK_CONN_24BIT_4 0x4b28
-#define AFE_GASRC0_NEW_CON0 0x4c40
-#define AFE_GASRC0_NEW_CON1 0x4c44
-#define AFE_GASRC0_NEW_CON2 0x4c48
-#define AFE_GASRC0_NEW_CON3 0x4c4c
-#define AFE_GASRC0_NEW_CON4 0x4c50
-#define AFE_GASRC0_NEW_CON5 0x4c54
-#define AFE_GASRC0_NEW_CON6 0x4c58
-#define AFE_GASRC0_NEW_CON7 0x4c5c
-#define AFE_GASRC0_NEW_CON8 0x4c60
-#define AFE_GASRC0_NEW_CON9 0x4c64
-#define AFE_GASRC0_NEW_CON10 0x4c68
-#define AFE_GASRC0_NEW_CON11 0x4c6c
-#define AFE_GASRC0_NEW_CON12 0x4c70
-#define AFE_GASRC0_NEW_CON13 0x4c74
-#define AFE_GASRC0_NEW_CON14 0x4c78
-#define AFE_GASRC1_NEW_CON0 0x4c80
-#define AFE_GASRC1_NEW_CON1 0x4c84
-#define AFE_GASRC1_NEW_CON2 0x4c88
-#define AFE_GASRC1_NEW_CON3 0x4c8c
-#define AFE_GASRC1_NEW_CON4 0x4c90
-#define AFE_GASRC1_NEW_CON5 0x4c94
-#define AFE_GASRC1_NEW_CON6 0x4c98
-#define AFE_GASRC1_NEW_CON7 0x4c9c
-#define AFE_GASRC1_NEW_CON8 0x4ca0
-#define AFE_GASRC1_NEW_CON9 0x4ca4
-#define AFE_GASRC1_NEW_CON10 0x4ca8
-#define AFE_GASRC1_NEW_CON11 0x4cac
-#define AFE_GASRC1_NEW_CON12 0x4cb0
-#define AFE_GASRC1_NEW_CON13 0x4cb4
-#define AFE_GASRC1_NEW_CON14 0x4cb8
-#define AFE_GASRC2_NEW_CON0 0x4cc0
-#define AFE_GASRC2_NEW_CON1 0x4cc4
-#define AFE_GASRC2_NEW_CON2 0x4cc8
-#define AFE_GASRC2_NEW_CON3 0x4ccc
-#define AFE_GASRC2_NEW_CON4 0x4cd0
-#define AFE_GASRC2_NEW_CON5 0x4cd4
-#define AFE_GASRC2_NEW_CON6 0x4cd8
-#define AFE_GASRC2_NEW_CON7 0x4cdc
-#define AFE_GASRC2_NEW_CON8 0x4ce0
-#define AFE_GASRC2_NEW_CON9 0x4ce4
-#define AFE_GASRC2_NEW_CON10 0x4ce8
-#define AFE_GASRC2_NEW_CON11 0x4cec
-#define AFE_GASRC2_NEW_CON12 0x4cf0
-#define AFE_GASRC2_NEW_CON13 0x4cf4
-#define AFE_GASRC2_NEW_CON14 0x4cf8
-#define AFE_GASRC3_NEW_CON0 0x4d00
-#define AFE_GASRC3_NEW_CON1 0x4d04
-#define AFE_GASRC3_NEW_CON2 0x4d08
-#define AFE_GASRC3_NEW_CON3 0x4d0c
-#define AFE_GASRC3_NEW_CON4 0x4d10
-#define AFE_GASRC3_NEW_CON5 0x4d14
-#define AFE_GASRC3_NEW_CON6 0x4d18
-#define AFE_GASRC3_NEW_CON7 0x4d1c
-#define AFE_GASRC3_NEW_CON8 0x4d20
-#define AFE_GASRC3_NEW_CON9 0x4d24
-#define AFE_GASRC3_NEW_CON10 0x4d28
-#define AFE_GASRC3_NEW_CON11 0x4d2c
-#define AFE_GASRC3_NEW_CON12 0x4d30
-#define AFE_GASRC3_NEW_CON13 0x4d34
-#define AFE_GASRC3_NEW_CON14 0x4d38
-#define AFE_GASRC4_NEW_CON0 0x4d40
-#define AFE_GASRC4_NEW_CON1 0x4d44
-#define AFE_GASRC4_NEW_CON2 0x4d48
-#define AFE_GASRC4_NEW_CON3 0x4d4c
-#define AFE_GASRC4_NEW_CON4 0x4d50
-#define AFE_GASRC4_NEW_CON5 0x4d54
-#define AFE_GASRC4_NEW_CON6 0x4d58
-#define AFE_GASRC4_NEW_CON7 0x4d5c
-#define AFE_GASRC4_NEW_CON8 0x4d60
-#define AFE_GASRC4_NEW_CON9 0x4d64
-#define AFE_GASRC4_NEW_CON10 0x4d68
-#define AFE_GASRC4_NEW_CON11 0x4d6c
-#define AFE_GASRC4_NEW_CON12 0x4d70
-#define AFE_GASRC4_NEW_CON13 0x4d74
-#define AFE_GASRC4_NEW_CON14 0x4d78
-#define AFE_GASRC5_NEW_CON0 0x4d80
-#define AFE_GASRC5_NEW_CON1 0x4d84
-#define AFE_GASRC5_NEW_CON2 0x4d88
-#define AFE_GASRC5_NEW_CON3 0x4d8c
-#define AFE_GASRC5_NEW_CON4 0x4d90
-#define AFE_GASRC5_NEW_CON5 0x4d94
-#define AFE_GASRC5_NEW_CON6 0x4d98
-#define AFE_GASRC5_NEW_CON7 0x4d9c
-#define AFE_GASRC5_NEW_CON8 0x4da0
-#define AFE_GASRC5_NEW_CON9 0x4da4
-#define AFE_GASRC5_NEW_CON10 0x4da8
-#define AFE_GASRC5_NEW_CON11 0x4dac
-#define AFE_GASRC5_NEW_CON12 0x4db0
-#define AFE_GASRC5_NEW_CON13 0x4db4
-#define AFE_GASRC5_NEW_CON14 0x4db8
-#define AFE_GASRC6_NEW_CON0 0x4dc0
-#define AFE_GASRC6_NEW_CON1 0x4dc4
-#define AFE_GASRC6_NEW_CON2 0x4dc8
-#define AFE_GASRC6_NEW_CON3 0x4dcc
-#define AFE_GASRC6_NEW_CON4 0x4dd0
-#define AFE_GASRC6_NEW_CON5 0x4dd4
-#define AFE_GASRC6_NEW_CON6 0x4dd8
-#define AFE_GASRC6_NEW_CON7 0x4ddc
-#define AFE_GASRC6_NEW_CON8 0x4de0
-#define AFE_GASRC6_NEW_CON9 0x4de4
-#define AFE_GASRC6_NEW_CON10 0x4de8
-#define AFE_GASRC6_NEW_CON11 0x4dec
-#define AFE_GASRC6_NEW_CON12 0x4df0
-#define AFE_GASRC6_NEW_CON13 0x4df4
-#define AFE_GASRC6_NEW_CON14 0x4df8
-#define AFE_GASRC7_NEW_CON0 0x4e00
-#define AFE_GASRC7_NEW_CON1 0x4e04
-#define AFE_GASRC7_NEW_CON2 0x4e08
-#define AFE_GASRC7_NEW_CON3 0x4e0c
-#define AFE_GASRC7_NEW_CON4 0x4e10
-#define AFE_GASRC7_NEW_CON5 0x4e14
-#define AFE_GASRC7_NEW_CON6 0x4e18
-#define AFE_GASRC7_NEW_CON7 0x4e1c
-#define AFE_GASRC7_NEW_CON8 0x4e20
-#define AFE_GASRC7_NEW_CON9 0x4e24
-#define AFE_GASRC7_NEW_CON10 0x4e28
-#define AFE_GASRC7_NEW_CON11 0x4e2c
-#define AFE_GASRC7_NEW_CON12 0x4e30
-#define AFE_GASRC7_NEW_CON13 0x4e34
-#define AFE_GASRC7_NEW_CON14 0x4e38
-#define AFE_GASRC8_NEW_CON0 0x4e40
-#define AFE_GASRC8_NEW_CON1 0x4e44
-#define AFE_GASRC8_NEW_CON2 0x4e48
-#define AFE_GASRC8_NEW_CON3 0x4e4c
-#define AFE_GASRC8_NEW_CON4 0x4e50
-#define AFE_GASRC8_NEW_CON5 0x4e54
-#define AFE_GASRC8_NEW_CON6 0x4e58
-#define AFE_GASRC8_NEW_CON7 0x4e5c
-#define AFE_GASRC8_NEW_CON8 0x4e60
-#define AFE_GASRC8_NEW_CON9 0x4e64
-#define AFE_GASRC8_NEW_CON10 0x4e68
-#define AFE_GASRC8_NEW_CON11 0x4e6c
-#define AFE_GASRC8_NEW_CON12 0x4e70
-#define AFE_GASRC8_NEW_CON13 0x4e74
-#define AFE_GASRC8_NEW_CON14 0x4e78
-#define AFE_GASRC9_NEW_CON0 0x4e80
-#define AFE_GASRC9_NEW_CON1 0x4e84
-#define AFE_GASRC9_NEW_CON2 0x4e88
-#define AFE_GASRC9_NEW_CON3 0x4e8c
-#define AFE_GASRC9_NEW_CON4 0x4e90
-#define AFE_GASRC9_NEW_CON5 0x4e94
-#define AFE_GASRC9_NEW_CON6 0x4e98
-#define AFE_GASRC9_NEW_CON7 0x4e9c
-#define AFE_GASRC9_NEW_CON8 0x4ea0
-#define AFE_GASRC9_NEW_CON9 0x4ea4
-#define AFE_GASRC9_NEW_CON10 0x4ea8
-#define AFE_GASRC9_NEW_CON11 0x4eac
-#define AFE_GASRC9_NEW_CON12 0x4eb0
-#define AFE_GASRC9_NEW_CON13 0x4eb4
-#define AFE_GASRC9_NEW_CON14 0x4eb8
-#define AFE_GASRC10_NEW_CON0 0x4ec0
-#define AFE_GASRC10_NEW_CON1 0x4ec4
-#define AFE_GASRC10_NEW_CON2 0x4ec8
-#define AFE_GASRC10_NEW_CON3 0x4ecc
-#define AFE_GASRC10_NEW_CON4 0x4ed0
-#define AFE_GASRC10_NEW_CON5 0x4ed4
-#define AFE_GASRC10_NEW_CON6 0x4ed8
-#define AFE_GASRC10_NEW_CON7 0x4edc
-#define AFE_GASRC10_NEW_CON8 0x4ee0
-#define AFE_GASRC10_NEW_CON9 0x4ee4
-#define AFE_GASRC10_NEW_CON10 0x4ee8
-#define AFE_GASRC10_NEW_CON11 0x4eec
-#define AFE_GASRC10_NEW_CON12 0x4ef0
-#define AFE_GASRC10_NEW_CON13 0x4ef4
-#define AFE_GASRC10_NEW_CON14 0x4ef8
-#define AFE_GASRC11_NEW_CON0 0x4f00
-#define AFE_GASRC11_NEW_CON1 0x4f04
-#define AFE_GASRC11_NEW_CON2 0x4f08
-#define AFE_GASRC11_NEW_CON3 0x4f0c
-#define AFE_GASRC11_NEW_CON4 0x4f10
-#define AFE_GASRC11_NEW_CON5 0x4f14
-#define AFE_GASRC11_NEW_CON6 0x4f18
-#define AFE_GASRC11_NEW_CON7 0x4f1c
-#define AFE_GASRC11_NEW_CON8 0x4f20
-#define AFE_GASRC11_NEW_CON9 0x4f24
-#define AFE_GASRC11_NEW_CON10 0x4f28
-#define AFE_GASRC11_NEW_CON11 0x4f2c
-#define AFE_GASRC11_NEW_CON12 0x4f30
-#define AFE_GASRC11_NEW_CON13 0x4f34
-#define AFE_GASRC11_NEW_CON14 0x4f38
-#define AFE_GASRC12_NEW_CON0 0x4f40
-#define AFE_GASRC12_NEW_CON1 0x4f44
-#define AFE_GASRC12_NEW_CON2 0x4f48
-#define AFE_GASRC12_NEW_CON3 0x4f4c
-#define AFE_GASRC12_NEW_CON4 0x4f50
-#define AFE_GASRC12_NEW_CON5 0x4f54
-#define AFE_GASRC12_NEW_CON6 0x4f58
-#define AFE_GASRC12_NEW_CON7 0x4f5c
-#define AFE_GASRC12_NEW_CON8 0x4f60
-#define AFE_GASRC12_NEW_CON9 0x4f64
-#define AFE_GASRC12_NEW_CON10 0x4f68
-#define AFE_GASRC12_NEW_CON11 0x4f6c
-#define AFE_GASRC12_NEW_CON12 0x4f70
-#define AFE_GASRC12_NEW_CON13 0x4f74
-#define AFE_GASRC12_NEW_CON14 0x4f78
-#define AFE_GASRC13_NEW_CON0 0x4f80
-#define AFE_GASRC13_NEW_CON1 0x4f84
-#define AFE_GASRC13_NEW_CON2 0x4f88
-#define AFE_GASRC13_NEW_CON3 0x4f8c
-#define AFE_GASRC13_NEW_CON4 0x4f90
-#define AFE_GASRC13_NEW_CON5 0x4f94
-#define AFE_GASRC13_NEW_CON6 0x4f98
-#define AFE_GASRC13_NEW_CON7 0x4f9c
-#define AFE_GASRC13_NEW_CON8 0x4fa0
-#define AFE_GASRC13_NEW_CON9 0x4fa4
-#define AFE_GASRC13_NEW_CON10 0x4fa8
-#define AFE_GASRC13_NEW_CON11 0x4fac
-#define AFE_GASRC13_NEW_CON12 0x4fb0
-#define AFE_GASRC13_NEW_CON13 0x4fb4
-#define AFE_GASRC13_NEW_CON14 0x4fb8
-#define AFE_GASRC14_NEW_CON0 0x4fc0
-#define AFE_GASRC14_NEW_CON1 0x4fc4
-#define AFE_GASRC14_NEW_CON2 0x4fc8
-#define AFE_GASRC14_NEW_CON3 0x4fcc
-#define AFE_GASRC14_NEW_CON4 0x4fd0
-#define AFE_GASRC14_NEW_CON5 0x4fd4
-#define AFE_GASRC14_NEW_CON6 0x4fd8
-#define AFE_GASRC14_NEW_CON7 0x4fdc
-#define AFE_GASRC14_NEW_CON8 0x4fe0
-#define AFE_GASRC14_NEW_CON9 0x4fe4
-#define AFE_GASRC14_NEW_CON10 0x4fe8
-#define AFE_GASRC14_NEW_CON11 0x4fec
-#define AFE_GASRC14_NEW_CON12 0x4ff0
-#define AFE_GASRC14_NEW_CON13 0x4ff4
-#define AFE_GASRC14_NEW_CON14 0x4ff8
-#define AFE_GASRC15_NEW_CON0 0x5000
-#define AFE_GASRC15_NEW_CON1 0x5004
-#define AFE_GASRC15_NEW_CON2 0x5008
-#define AFE_GASRC15_NEW_CON3 0x500c
-#define AFE_GASRC15_NEW_CON4 0x5010
-#define AFE_GASRC15_NEW_CON5 0x5014
-#define AFE_GASRC15_NEW_CON6 0x5018
-#define AFE_GASRC15_NEW_CON7 0x501c
-#define AFE_GASRC15_NEW_CON8 0x5020
-#define AFE_GASRC15_NEW_CON9 0x5024
-#define AFE_GASRC15_NEW_CON10 0x5028
-#define AFE_GASRC15_NEW_CON11 0x502c
-#define AFE_GASRC15_NEW_CON12 0x5030
-#define AFE_GASRC15_NEW_CON13 0x5034
-#define AFE_GASRC15_NEW_CON14 0x5038
-#define AFE_GASRC16_NEW_CON0 0x5040
-#define AFE_GASRC16_NEW_CON1 0x5044
-#define AFE_GASRC16_NEW_CON2 0x5048
-#define AFE_GASRC16_NEW_CON3 0x504c
-#define AFE_GASRC16_NEW_CON4 0x5050
-#define AFE_GASRC16_NEW_CON5 0x5054
-#define AFE_GASRC16_NEW_CON6 0x5058
-#define AFE_GASRC16_NEW_CON7 0x505c
-#define AFE_GASRC16_NEW_CON8 0x5060
-#define AFE_GASRC16_NEW_CON9 0x5064
-#define AFE_GASRC16_NEW_CON10 0x5068
-#define AFE_GASRC16_NEW_CON11 0x506c
-#define AFE_GASRC16_NEW_CON12 0x5070
-#define AFE_GASRC16_NEW_CON13 0x5074
-#define AFE_GASRC16_NEW_CON14 0x5078
-#define AFE_GASRC17_NEW_CON0 0x5080
-#define AFE_GASRC17_NEW_CON1 0x5084
-#define AFE_GASRC17_NEW_CON2 0x5088
-#define AFE_GASRC17_NEW_CON3 0x508c
-#define AFE_GASRC17_NEW_CON4 0x5090
-#define AFE_GASRC17_NEW_CON5 0x5094
-#define AFE_GASRC17_NEW_CON6 0x5098
-#define AFE_GASRC17_NEW_CON7 0x509c
-#define AFE_GASRC17_NEW_CON8 0x50a0
-#define AFE_GASRC17_NEW_CON9 0x50a4
-#define AFE_GASRC17_NEW_CON10 0x50a8
-#define AFE_GASRC17_NEW_CON11 0x50ac
-#define AFE_GASRC17_NEW_CON12 0x50b0
-#define AFE_GASRC17_NEW_CON13 0x50b4
-#define AFE_GASRC17_NEW_CON14 0x50b8
-#define AFE_GASRC18_NEW_CON0 0x50c0
-#define AFE_GASRC18_NEW_CON1 0x50c4
-#define AFE_GASRC18_NEW_CON2 0x50c8
-#define AFE_GASRC18_NEW_CON3 0x50cc
-#define AFE_GASRC18_NEW_CON4 0x50d0
-#define AFE_GASRC18_NEW_CON5 0x50d4
-#define AFE_GASRC18_NEW_CON6 0x50d8
-#define AFE_GASRC18_NEW_CON7 0x50dc
-#define AFE_GASRC18_NEW_CON8 0x50e0
-#define AFE_GASRC18_NEW_CON9 0x50e4
-#define AFE_GASRC18_NEW_CON10 0x50e8
-#define AFE_GASRC18_NEW_CON11 0x50ec
-#define AFE_GASRC18_NEW_CON12 0x50f0
-#define AFE_GASRC18_NEW_CON13 0x50f4
-#define AFE_GASRC18_NEW_CON14 0x50f8
-#define AFE_GASRC19_NEW_CON0 0x5100
-#define AFE_GASRC19_NEW_CON1 0x5104
-#define AFE_GASRC19_NEW_CON2 0x5108
-#define AFE_GASRC19_NEW_CON3 0x510c
-#define AFE_GASRC19_NEW_CON4 0x5110
-#define AFE_GASRC19_NEW_CON5 0x5114
-#define AFE_GASRC19_NEW_CON6 0x5118
-#define AFE_GASRC19_NEW_CON7 0x511c
-#define AFE_GASRC19_NEW_CON8 0x5120
-#define AFE_GASRC19_NEW_CON9 0x5124
-#define AFE_GASRC19_NEW_CON10 0x5128
-#define AFE_GASRC19_NEW_CON11 0x512c
-#define AFE_GASRC19_NEW_CON12 0x5130
-#define AFE_GASRC19_NEW_CON13 0x5134
-#define AFE_GASRC19_NEW_CON14 0x5138
-
-/* ASYS_TOP_CON */
-#define ASYS_TOP_CON_A1SYS_TIMING_ON BIT(0)
-#define ASYS_TOP_CON_A2SYS_TIMING_ON BIT(1)
-#define ASYS_TOP_CON_A3SYS_TIMING_ON BIT(4)
-#define ASYS_TOP_CON_A4SYS_TIMING_ON BIT(5)
-#define ASYS_TOP_CON_26M_TIMING_ON BIT(2)
-
-/* PWR2_TOP_CON0 */
-#define PWR2_TOP_CON_DMIC8_SRC_SEL_MASK GENMASK(31, 29)
-#define PWR2_TOP_CON_DMIC7_SRC_SEL_MASK GENMASK(28, 26)
-#define PWR2_TOP_CON_DMIC6_SRC_SEL_MASK GENMASK(25, 23)
-#define PWR2_TOP_CON_DMIC5_SRC_SEL_MASK GENMASK(22, 20)
-#define PWR2_TOP_CON_DMIC4_SRC_SEL_MASK GENMASK(19, 17)
-#define PWR2_TOP_CON_DMIC3_SRC_SEL_MASK GENMASK(16, 14)
-#define PWR2_TOP_CON_DMIC2_SRC_SEL_MASK GENMASK(13, 11)
-#define PWR2_TOP_CON_DMIC1_SRC_SEL_MASK GENMASK(10, 8)
-#define PWR2_TOP_CON_DMIC8_SRC_SEL_VAL(x) ((x) << 29)
-#define PWR2_TOP_CON_DMIC7_SRC_SEL_VAL(x) ((x) << 26)
-#define PWR2_TOP_CON_DMIC6_SRC_SEL_VAL(x) ((x) << 23)
-#define PWR2_TOP_CON_DMIC5_SRC_SEL_VAL(x) ((x) << 20)
-#define PWR2_TOP_CON_DMIC4_SRC_SEL_VAL(x) ((x) << 17)
-#define PWR2_TOP_CON_DMIC3_SRC_SEL_VAL(x) ((x) << 14)
-#define PWR2_TOP_CON_DMIC2_SRC_SEL_VAL(x) ((x) << 11)
-#define PWR2_TOP_CON_DMIC1_SRC_SEL_VAL(x) ((x) << 8)
-
-/* PWR2_TOP_CON1 */
-#define PWR2_TOP_CON1_DMIC_CKDIV_ON BIT(1)
-
-/* PCM_INTF_CON1 */
-#define PCM_INTF_CON1_SYNC_OUT_INV BIT(23)
-#define PCM_INTF_CON1_BCLK_OUT_INV BIT(22)
-#define PCM_INTF_CON1_CLK_OUT_INV_MASK GENMASK(23, 22)
-#define PCM_INTF_CON1_SYNC_IN_INV BIT(21)
-#define PCM_INTF_CON1_BCLK_IN_INV BIT(20)
-#define PCM_INTF_CON1_CLK_IN_INV_MASK GENMASK(21, 20)
-#define PCM_INTF_CON1_PCM_24BIT BIT(16)
-#define PCM_INTF_CON1_PCM_16BIT (0 << 16)
-#define PCM_INTF_CON1_PCM_BIT_MASK BIT(16)
-#define PCM_INTF_CON1_PCM_WLEN_32BCK (0 << 14)
-#define PCM_INTF_CON1_PCM_WLEN_64BCK BIT(14)
-#define PCM_INTF_CON1_PCM_WLEN_MASK BIT(14)
-#define PCM_INTF_CON1_SYNC_LENGTH(x) (((x) & 0x1f) << 9)
-#define PCM_INTF_CON1_SYNC_LENGTH_MASK (0x1f << 9)
-#define PCM_INTF_CON1_PCM_SLAVE BIT(5)
-#define PCM_INTF_CON1_PCM_MASTER (0 << 5)
-#define PCM_INTF_CON1_PCM_M_S_MASK BIT(5)
-#define PCM_INTF_CON1_PCM_MODE(x) (((x) & 0x3) << 3)
-#define PCM_INTF_CON1_PCM_MODE_MASK (0x3 << 3)
-#define PCM_INTF_CON1_PCM_FMT(x) (((x) & 0x3) << 1)
-#define PCM_INTF_CON1_PCM_FMT_MASK (0x3 << 1)
-#define PCM_INTF_CON1_PCM_EN BIT(0)
-
-/* PCM_INTF_CON2 */
-#define PCM_INTF_CON2_CLK_DOMAIN_SEL(x) (((x) & 0x3) << 23)
-#define PCM_INTF_CON2_CLK_DOMAIN_SEL_MASK (0x3 << 23)
-#define PCM_INTF_CON2_SYNC_FREQ_MODE(x) (((x) & 0x1f) << 12)
-#define PCM_INTF_CON2_SYNC_FREQ_MODE_MASK (0x1f << 12)
-#define PCM_INTF_CON2_PCM_TX2RX_LPBK BIT(8)
-
-/* AFE_MPHONE_MULTIx_CON0 */
-#define AFE_MPHONE_MULTI_CON0_16BIT_SWAP BIT(3)
-#define AFE_MPHONE_MULTI_CON0_16BIT_SWAP_MASK BIT(3)
-#define AFE_MPHONE_MULTI_CON0_24BIT_DATA (0x1 << 1)
-#define AFE_MPHONE_MULTI_CON0_16BIT_DATA (0x0 << 1)
-#define AFE_MPHONE_MULIT_CON0_24BIT_DATA_MASK BIT(1)
-#define AFE_MPHONE_MULTI_CON0_EN BIT(0)
-#define AFE_MPHONE_MULTI_CON0_EN_MASK BIT(0)
-
-/* AFE_MPHONE_MULTIx_CON1 */
-#define AFE_MPHONE_MULTI_CON1_SYNC_ON BIT(24)
-#define AFE_MPHONE_MULTI_CON1_SYNC_ON_MASK BIT(24)
-#define AFE_MPHONE_MULTI_CON1_24BIT_SWAP_BYPASS BIT(22)
-#define AFE_MPHONE_MULTI_CON1_24BIT_SWAP_BYPASS_MASK BIT(22)
-#define AFE_MPHONE_MULTI_CON1_NON_COMPACT_MODE (0x1 << 19)
-#define AFE_MPHONE_MULTI_CON1_COMPACT_MODE (0x0 << 19)
-#define AFE_MPHONE_MULTI_CON1_NON_COMPACT_MODE_MASK BIT(19)
-#define AFE_MPHONE_MULTI_CON1_HBR_MODE BIT(18)
-#define AFE_MPHONE_MULTI_CON1_HBR_MODE_MASK BIT(18)
-#define AFE_MPHONE_MULTI_CON1_LRCK_32_CYCLE (0x2 << 16)
-#define AFE_MPHONE_MULTI_CON1_LRCK_24_CYCLE (0x1 << 16)
-#define AFE_MPHONE_MULTI_CON1_LRCK_16_CYCLE (0x0 << 16)
-#define AFE_MPHONE_MULTI_CON1_LRCK_CYCLE_SEL_MASK GENMASK(17, 16)
-#define AFE_MPHONE_MULTI_CON1_LRCK_INV BIT(15)
-#define AFE_MPHONE_MULTI_CON1_LRCK_INV_MASK BIT(15)
-#define AFE_MPHONE_MULTI_CON1_DELAY_DATA BIT(14)
-#define AFE_MPHONE_MULTI_CON1_DELAY_DATA_MASK BIT(14)
-#define AFE_MPHONE_MULTI_CON1_LEFT_ALIGN BIT(13)
-#define AFE_MPHONE_MULTI_CON1_LEFT_ALIGN_MASK BIT(13)
-#define AFE_MPHONE_MULTI_CON1_BIT_NUM(x) ((((x) - 1) & 0x1f) << 8)
-#define AFE_MPHONE_MULTI_CON1_BIT_NUM_MASK GENMASK(12, 8)
-#define AFE_MPHONE_MULTI_CON1_BCK_INV BIT(6)
-#define AFE_MPHONE_MULTI_CON1_BCK_INV_MASK BIT(6)
-#define AFE_MPHONE_MULTI_CON1_CH_NUM(x) ((((x) >> 1) - 1) & 0x3)
-#define AFE_MPHONE_MULTI_CON1_CH_NUM_MASK GENMASK(1, 0)
-
-/* AFE_MPHONE_MULTIx_CON2 */
-#define AFE_MPHONE_MULTI_CON2_SEL_SPDIFIN BIT(19)
-#define AFE_MPHONE_MULTI_CON2_SEL_SPDIFIN_MASK BIT(19)
-
-/* AFE_AUD_PAD_TOP */
-#define RG_RX_PROTOCOL2 BIT(3)
-#define RG_RX_FIFO_ON BIT(0)
-
-/* AFE_ADDA_MTKAIF_CFG0 */
-#define MTKAIF_RXIF_CLKINV_ADC BIT(31)
-#define MTKAIF_RXIF_PROTOCOL2 BIT(16)
-#define MTKAIF_TXIF_PROTOCOL2 BIT(4)
-#define MTKAIF_TXIF_8TO5 BIT(2)
-#define MTKAIF_RXIF_8TO5 BIT(1)
-#define MTKAIF_IF_LOOPBACK1 BIT(0)
-
-/* AFE_ADDA_MTKAIF_RX_CFG2 */
-#define MTKAIF_RXIF_DELAY_CYCLE(x) ((x) << 12)
-#define MTKAIF_RXIF_DELAY_CYCLE_MASK GENMASK(15, 12)
-#define MTKAIF_RXIF_DELAY_DATA BIT(8)
-#define MTKAIF_RXIF_DELAY_DATA_SHIFT 8
-
-/* AFE_ADDA_MTKAIF_SYNCWORD_CFG */
-#define ADDA6_MTKAIF_RX_SYNC_WORD2_DISABLE BIT(23)
-
-/* AFE_DMICx_UL_SRC_CON0 */
-#define AFE_DMIC_UL_SRC_CON0_UL_PHASE_SEL_CH1(x) (((x) & 0x7) << 27)
-#define AFE_DMIC_UL_SRC_CON0_UL_PHASE_SEL_CH2(x) (((x) & 0x7) << 24)
-#define AFE_DMIC_UL_SRC_CON0_UL_TWO_WIRE_MODE_CTL BIT(23)
-#define AFE_DMIC_UL_SRC_CON0_UL_MODE_3P25M_CH2_CTL BIT(22)
-#define AFE_DMIC_UL_SRC_CON0_UL_MODE_3P25M_CH1_CTL BIT(21)
-#define AFE_DMIC_UL_VOICE_MODE(x) (((x) & 0x7) << 17)
-#define AFE_DMIC_UL_CON0_VOCIE_MODE_8K AFE_DMIC_UL_VOICE_MODE(0)
-#define AFE_DMIC_UL_CON0_VOCIE_MODE_16K AFE_DMIC_UL_VOICE_MODE(1)
-#define AFE_DMIC_UL_CON0_VOCIE_MODE_32K AFE_DMIC_UL_VOICE_MODE(2)
-#define AFE_DMIC_UL_CON0_VOCIE_MODE_48K AFE_DMIC_UL_VOICE_MODE(3)
-#define AFE_DMIC_UL_SRC_CON0_UL_IIR_MODE_CTL(x) (((x) & 0x7) << 7)
-#define AFE_DMIC_UL_SRC_CON0_UL_IIR_ON_TMP_CTL BIT(10)
-#define AFE_DMIC_UL_SRC_CON0_UL_SDM_3_LEVEL_CTL BIT(1)
-#define AFE_DMIC_UL_SRC_CON0_UL_SRC_ON_TMP_CTL BIT(0)
-
-/* ETDM_INx_AFIFO_CON */
-#define ETDM_IN_USE_AFIFO BIT(8)
-#define ETDM_IN_AFIFO_CLOCK(x) ((x) << 5)
-#define ETDM_IN_AFIFO_CLOCK_MASK GENMASK(7, 5)
-#define ETDM_IN_AFIFO_MODE(x) ((x) << 0)
-#define ETDM_IN_AFIFO_MODE_MASK GENMASK(4, 0)
-
-/* ETDM_COWORK_CON0 */
-#define ETDM_OUT1_SLAVE_SEL(x) ((x) << 20)
-#define ETDM_OUT1_SLAVE_SEL_MASK GENMASK(23, 20)
-#define ETDM_OUT1_SLAVE_SEL_SHIFT 20
-
-/* ETDM_COWORK_CON1 */
-#define ETDM_IN1_SDATA_SEL(x) ((x) << 20)
-#define ETDM_IN1_SDATA_SEL_MASK GENMASK(23, 20)
-#define ETDM_IN1_SDATA_SEL_SHIFT 20
-#define ETDM_IN1_SDATA0_SEL(x) ((x) << 16)
-#define ETDM_IN1_SDATA0_SEL_MASK GENMASK(19, 16)
-#define ETDM_IN1_SDATA0_SEL_SHIFT 16
-#define ETDM_IN1_SLAVE_SEL(x) ((x) << 8)
-#define ETDM_IN1_SLAVE_SEL_MASK GENMASK(11, 8)
-#define ETDM_IN1_SLAVE_SEL_SHIFT 8
-
-/* ETDM_COWORK_CON2 */
-#define ETDM_IN2_SLAVE_SEL(x) ((x) << 24)
-#define ETDM_IN2_SLAVE_SEL_MASK GENMASK(27, 24)
-#define ETDM_IN2_SLAVE_SEL_SHIFT 24
-#define ETDM_OUT3_SLAVE_SEL(x) ((x) << 20)
-#define ETDM_OUT3_SLAVE_SEL_MASK GENMASK(23, 20)
-#define ETDM_OUT3_SLAVE_SEL_SHIFT 20
-#define ETDM_OUT2_SLAVE_SEL(x) ((x) << 8)
-#define ETDM_OUT2_SLAVE_SEL_MASK GENMASK(11, 8)
-#define ETDM_OUT2_SLAVE_SEL_SHIFT 8
-
-/* ETDM_COWORK_CON3 */
-#define ETDM_IN2_SDATA_SEL(x) ((x) << 4)
-#define ETDM_IN2_SDATA_SEL_MASK GENMASK(7, 4)
-#define ETDM_IN2_SDATA_SEL_SHIFT 4
-#define ETDM_IN2_SDATA0_SEL(x) ((x) << 0)
-#define ETDM_IN2_SDATA0_SEL_MASK GENMASK(3, 0)
-#define ETDM_IN2_SDATA0_SEL_SHIFT 0
-
-/* ETDM_x_CONx */
-#define ETDM_CON0_CH_NUM(x) (((x) - 1) << 23)
-#define ETDM_CON0_CH_NUM_MASK GENMASK(27, 23)
-#define ETDM_CON0_WORD_LEN(x) (((x) - 1) << 16)
-#define ETDM_CON0_WORD_LEN_MASK GENMASK(20, 16)
-#define ETDM_CON0_BIT_LEN(x) (((x) - 1) << 11)
-#define ETDM_CON0_BIT_LEN_MASK GENMASK(15, 11)
-#define ETDM_CON0_FORMAT(x) ((x) << 6)
-#define ETDM_CON0_FORMAT_MASK GENMASK(8, 6)
-#define ETDM_CON0_SLAVE_MODE BIT(5)
-#define ETDM_CON0_EN BIT(0)
-
-#define ETDM_OUT_CON0_RELATCH_DOMAIN(x) ((x) << 28)
-#define ETDM_OUT_CON0_RELATCH_DOMAIN_MASK GENMASK(29, 28)
-
-#define ETDM_CON1_LRCK_AUTO_MODE BIT(29)
-#define ETDM_CON1_LRCK_WIDTH(x) (((x) - 1) << 20)
-#define ETDM_CON1_LRCK_WIDTH_MASK GENMASK(29, 20)
-#define ETDM_CON1_MCLK_OUTPUT BIT(16)
-
-#define ETDM_IN_CON2_MULTI_IP_2CH_MODE BIT(31)
-#define ETDM_IN_CON2_MULTI_IP_TOTAL_CH(x) (((x) - 1) << 15)
-#define ETDM_IN_CON2_MULTI_IP_TOTAL_CH_MASK GENMASK(19, 15)
-#define ETDM_IN_CON2_CLOCK(x) ((x) << 10)
-#define ETDM_IN_CON2_CLOCK_MASK GENMASK(12, 10)
-#define ETDM_IN_CON2_CLOCK_SHIFT 10
-#define ETDM_IN_CON2_UPDATE_GAP(x) ((x) << 5)
-#define ETDM_IN_CON2_UPDATE_GAP_MASK GENMASK(9, 5)
-
-#define ETDM_OUT_CON2_LRCK_DELAY_BCK_INV BIT(30)
-#define ETDM_OUT_CON2_LRCK_DELAY_0P5T_EN BIT(29)
-
-#define ETDM_IN_CON3_FS(x) ((x) << 26)
-#define ETDM_IN_CON3_FS_MASK GENMASK(30, 26)
-#define ETDM_IN_CON3_DISABLE_OUT(x) BIT(((x) & 0xffff))
-#define ETDM_IN_CON3_DISABLE_OUT_MASK GENMASK(15, 0)
-
-#define ETDM_IN_CON4_MASTER_LRCK_INV BIT(19)
-#define ETDM_IN_CON4_MASTER_BCK_INV BIT(18)
-#define ETDM_IN_CON4_SLAVE_LRCK_INV BIT(17)
-#define ETDM_IN_CON4_SLAVE_BCK_INV BIT(16)
-
-#define ETDM_OUT_CON4_RELATCH_EN(x) ((x) << 24)
-#define ETDM_OUT_CON4_RELATCH_EN_MASK GENMASK(28, 24)
-#define ETDM_OUT_CON4_CLOCK(x) ((x) << 6)
-#define ETDM_OUT_CON4_CLOCK_MASK GENMASK(8, 6)
-#define ETDM_OUT_CON4_CLOCK_SHIFT 6
-#define ETDM_OUT_CON4_FS(x) ((x) << 0)
-#define ETDM_OUT_CON4_FS_MASK GENMASK(4, 0)
-
-#define ETDM_IN_CON5_LR_SWAP(x) BIT(((x) & 0xffff) + 16)
-#define ETDM_IN_CON5_LR_SWAP_MASK GENMASK(31, 16)
-#define ETDM_IN_CON5_ENABLE_ODD(x) BIT(((x) & 0xffff))
-#define ETDM_IN_CON5_ENABLE_ODD_MASK GENMASK(15, 0)
-
-#define ETDM_OUT_CON5_MASTER_LRCK_INV BIT(10)
-#define ETDM_OUT_CON5_MASTER_BCK_INV BIT(9)
-#define ETDM_OUT_CON5_SLAVE_LRCK_INV BIT(8)
-#define ETDM_OUT_CON5_SLAVE_BCK_INV BIT(7)
-
-/* AFE_DPTX_CON */
-#define AFE_DPTX_CON_CH_EN(x) (((x) & 0xf) << 8)
-#define AFE_DPTX_CON_CH_EN_2CH (AFE_DPTX_CON_CH_EN(GENMASK(1, 0)))
-#define AFE_DPTX_CON_CH_EN_4CH (AFE_DPTX_CON_CH_EN(GENMASK(3, 0)))
-#define AFE_DPTX_CON_CH_EN_6CH (AFE_DPTX_CON_CH_EN(GENMASK(5, 0)))
-#define AFE_DPTX_CON_CH_EN_8CH (AFE_DPTX_CON_CH_EN(GENMASK(7, 0)))
-#define AFE_DPTX_CON_CH_EN_MASK GENMASK(15, 8)
-#define AFE_DPTX_CON_16BIT BIT(2)
-#define AFE_DPTX_CON_24BIT (0 << 2)
-#define AFE_DPTX_CON_16BIT_MASK BIT(2)
-#define AFE_DPTX_CON_CH_NUM(x) (((x) & 0x1) << 1)
-#define AFE_DPTX_CON_CH_NUM_2CH (AFE_DPTX_CON_CH_NUM(0))
-#define AFE_DPTX_CON_CH_NUM_8CH (AFE_DPTX_CON_CH_NUM(1))
-#define AFE_DPTX_CON_CH_NUM_MASK (0x1 << 1)
-#define AFE_DPTX_CON_ON BIT(0)
-#define AFE_DPTX_CON_ON_MASK BIT(0)
-
-/* AFE_ADDA_UL_DL_CON0 */
-#define ADDA_AFE_ON_SHIFT 0
-
-/* AFE_ADDA_DL_SRC2_CON0 */
-#define DL_2_INPUT_MODE_CTL(x) ((x) << 28)
-#define DL_2_INPUT_MODE_CTL_MASK GENMASK(31, 28)
-#define DL_2_CH1_SATURATION_EN_CTL BIT(27)
-#define DL_2_CH2_SATURATION_EN_CTL BIT(26)
-#define DL_2_MUTE_CH1_OFF_CTL_PRE BIT(12)
-#define DL_2_MUTE_CH2_OFF_CTL_PRE BIT(11)
-#define DL_2_VOICE_MODE_CTL_PRE BIT(5)
-#define DL_2_GAIN_ON_CTL_PRE_SHIFT 1
-#define DL_2_SRC_ON_TMP_CTRL_PRE_SHIFT 0
-
-/* AFE_ADDA_DL_SRC2_CON1 */
-#define DL_2_GAIN_CTL_PRE(x) ((x) << 16)
-#define DL_2_GAIN_CTL_PRE_MASK GENMASK(31, 16)
-#define DL_2_GAIN_CTL_PRE_SHIFT 16
-
-/* AFE_ADDA_TOP_CON0 */
-#define C_LOOPBACK_MODE_CTL_MASK GENMASK(15, 12)
-#define DL_INPUT_FROM_SINEGEN (4 << 12)
-
-/* AFE_ADDA_DL_SDM_DCCOMP_CON */
-#define DL_USE_NEW_2ND_SDM BIT(30)
-#define ATTGAIN_CTL_MASK GENMASK(5, 0)
-
-/* AFE_ADDA_UL_SRC_CON0 */
-#define UL_MODE_3P25M_CH2_CTL BIT(22)
-#define UL_MODE_3P25M_CH1_CTL BIT(21)
-#define UL_VOICE_MODE_CTL(x) ((x) << 17)
-#define UL_VOICE_MODE_CTL_MASK GENMASK(19, 17)
-#define UL_LOOPBACK_MODE_CTL BIT(2)
-#define UL_SDM3_LEVEL_CTL BIT(1)
-#define UL_SRC_ON_TMP_CTL_SHIFT 0
-
-#endif
diff --git a/src/platform/mt8195/include/platform/platform.h b/src/platform/mt8195/include/platform/platform.h
deleted file mode 100644
index dba4a22805a4..000000000000
--- a/src/platform/mt8195/include/platform/platform.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2021 MediaTek. All rights reserved.
- *
- * Author: YC Hung <yc.hung@mediatek.com>
- */
-
-#ifdef __SOF_PLATFORM_H__
-
-#ifndef __PLATFORM_PLATFORM_H__
-#define __PLATFORM_PLATFORM_H__
-
-#if !defined(__ASSEMBLER__) && !defined(LINKER)
-
-#include <sof/lib/mailbox.h>
-#include <stddef.h>
-#include <stdint.h>
-
-struct ll_schedule_domain;
-struct timer;
-
-#define PLATFORM_DEFAULT_CLOCK CLK_CPU(0)
-#define LPSRAM_SIZE 16384
-
-/*MTK_TODO : use correct ipc interrupt , mailbox int group 16 bit 0*/
-/* IPC Interrupt */
-#define PLATFORM_IPC_INTERRUPT IRQ_MASK_GROUP16
-#define PLATFORM_IPC_INTERRUPT_NAME NULL
-
-/* Host page size */
-#define HOST_PAGE_SIZE 4096
-#define PLATFORM_PAGE_TABLE_SIZE 256
-
-/* pipeline IRQ */
-#define PLATFORM_SCHEDULE_IRQ IRQ_NUM_SOFTWARE0
-#define PLATFORM_SCHEDULE_IRQ_NAME NULL
-
-/* Platform stream capabilities */
-#define PLATFORM_MAX_CHANNELS 4
-#define PLATFORM_MAX_STREAMS 5
-
-/* local buffer size of DMA tracing */
-#define DMA_TRACE_LOCAL_SIZE HOST_PAGE_SIZE
-
-/* trace bytes flushed during panic */
-#define DMA_FLUSH_TRACE_SIZE (MAILBOX_TRACE_SIZE >> 2)
-
-/* the interval of DMA trace copying */
-#define DMA_TRACE_PERIOD 500000
-
-/*
- * the interval of reschedule DMA trace copying in special case like half
- * fullness of local DMA trace buffer
- */
-#define DMA_TRACE_RESCHEDULE_TIME 100
-
-/* DSP default delay in cycles */
-#define PLATFORM_DEFAULT_DELAY 12
-
-#define SRAM_REG_FW_STATUS 0x4
-
-/* Platform defined panic code */
-static inline void platform_panic(uint32_t p)
-{
-	/* Store the error code in the debug box so the
-	 * application processor can pick it up. Takes up 4 bytes
-	 * from the debug box.
-	 */
-	mailbox_sw_reg_write(SRAM_REG_FW_STATUS, p);
-
-	/* Notify application processor */
-	trigger_irq_to_host_req();
-}
-
-/**
- * \brief Platform specific CPU entering idle.
- * May be power-optimized using platform specific capabilities.
- * @param level Interrupt level.
- */
-void platform_wait_for_interrupt(int level);
-
-extern intptr_t _module_init_start;
-extern intptr_t _module_init_end;
-#endif
-
-#endif /* __PLATFORM_PLATFORM_H__ */
-
-#else
-
-#error "This file shouldn't be included from outside of sof/platform.h"
-
-#endif /* __SOF_PLATFORM_H__ */
diff --git a/src/platform/mt8195/include/platform/trace/trace.h b/src/platform/mt8195/include/platform/trace/trace.h
deleted file mode 100644
index a1bd3c149846..000000000000
--- a/src/platform/mt8195/include/platform/trace/trace.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2021 MediaTek. All rights reserved.
- *
- * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
- */
-
-#ifdef __SOF_TRACE_TRACE_H__
-
-#ifndef __PLATFORM_TRACE_TRACE_H__
-#define __PLATFORM_TRACE_TRACE_H__
-
-#include <sof/lib/mailbox.h>
-#include <sof/lib/memory.h>
-#include <sof/lib/io.h>
-#include <platform/drivers/mt_reg_base.h>
-
-#define ADSP_TRACE_POINT (0x2)
-
-/* Platform defined trace code */
-#define platform_trace_point(__x)                               \
-	do {                                                        \
-		io_reg_write(MTK_DSP_MBOX_OUT_CMD_MSG0(2), __x);        \
-		io_reg_write(MTK_DSP_MBOX_OUT_CMD(2), ADSP_TRACE_POINT);\
-	} while (0)
-
-#endif /* __PLATFORM_TRACE_TRACE_H__ */
-
-#else
-
-#error "This file shouldn't be included from outside of sof/trace/trace.h"
-
-#endif /* __SOF_TRACE_TRACE_H__ */
diff --git a/src/platform/mt8195/lib/CMakeLists.txt b/src/platform/mt8195/lib/CMakeLists.txt
deleted file mode 100644
index ef71f8eea6cd..000000000000
--- a/src/platform/mt8195/lib/CMakeLists.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-
-add_local_sources(sof
-	clk.c
-	dma.c
-	memory.c
-	dai.c
-)
diff --git a/src/platform/mt8195/lib/clk.c b/src/platform/mt8195/lib/clk.c
deleted file mode 100644
index f0e0ce936e0c..000000000000
--- a/src/platform/mt8195/lib/clk.c
+++ /dev/null
@@ -1,197 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-/*
- * Copyright(c) 2021 MediaTek. All rights reserved.
- *
- * Author: YC Hung <yc.hung@mediatek.com>
- */
-
-#include <sof/common.h>
-#include <rtos/clk.h>
-#include <sof/lib/cpu.h>
-#include <sof/lib/memory.h>
-#include <sof/lib/notifier.h>
-#include <sof/lib/uuid.h>
-#include <rtos/wait.h>
-#include <rtos/sof.h>
-
-SOF_DEFINE_REG_UUID(clkdrv_mt8195);
-
-/* unused with Zephyr, generates no output */
-DECLARE_TR_CTX(clkdrv_tr, SOF_UUID(clkdrv_mt8195_uuid), LOG_LEVEL_INFO);
-
-static int dsppll_enable; /* default no adsp clock*/
-static int adsp_clock;
-
-/*Use external Ostimer*/
-const struct freq_table platform_cpu_freq[] = {
-	{ 13000000, 26000},
-	{ 26000000, 26000},
-	{ 370000000, 26000},
-	{ 540000000, 26000},
-	{ 720000000, 26000},
-};
-
-const uint32_t cpu_freq_enc[] = {
-	13000000,
-	26000000,
-	0x831C7628,
-	0x8214C4ED,
-	0x821BB13C,
-};
-
-STATIC_ASSERT(ARRAY_SIZE(platform_cpu_freq) == NUM_CPU_FREQ,
-	      invalid_number_of_cpu_frequencies);
-
-static struct clock_info platform_clocks_info[NUM_CLOCKS];
-
-static inline void clk_setl(uint32_t addr, uint32_t val)
-{
-	io_reg_write(addr, io_reg_read(addr) | (val));
-}
-
-static inline void clk_clrl(uint32_t addr, uint32_t val)
-{
-	io_reg_write(addr, io_reg_read(addr) & ~(val));
-}
-
-static inline int dsp_clk_value_convert(int value)
-{
-	int ret;
-
-	switch (value) {
-	case DSP_CLK_13M:
-	case DSP_CLK_26M:
-		ret = CLK_ADSP_SEL_26M;
-		break;
-	case DSP_CLK_PLL_370M:
-	case DSP_CLK_PLL_540M:
-	case DSP_CLK_PLL_720M:
-		ret = CLK_ADSP_SEL_ADSPPLL;
-		break;
-	default:
-		ret = CLK_ADSP_SEL_26M;
-		break;
-	}
-
-	return ret;
-}
-
-static void clk_dsppll_enable(void)
-{
-	tr_dbg(&clkdrv_tr, "entry");
-
-	io_reg_update_bits(AUDIODSP_CK_CG, 0x1 << RG_AUDIODSP_SW_CG, 0x0);
-	clk_setl(DSPPLL_CON4, PLL_PWR_ON);
-	wait_delay_us(1);
-	clk_clrl(DSPPLL_CON4, PLL_ISO_EN);
-	wait_delay_us(1);
-	clk_setl(DSPPLL_CON0, PLL_EN);
-	wait_delay_us(20);
-	dsppll_enable = 1;
-}
-
-static void clk_dsppll_disable(void)
-{
-	tr_dbg(&clkdrv_tr, "entry");
-
-	clk_clrl(DSPPLL_CON0, PLL_EN);
-	wait_delay_us(1);
-	clk_setl(DSPPLL_CON4, PLL_ISO_EN);
-	wait_delay_us(1);
-	clk_clrl(DSPPLL_CON4, PLL_PWR_ON);
-	dsppll_enable = 0;
-}
-
-static int dsppll_get_enable(void)
-{
-	tr_dbg(&clkdrv_tr, "dsppll_enable=%d.\n", dsppll_enable);
-
-	return dsppll_enable;
-}
-
-static int set_mux_sel(enum mux_id_t mux_id, uint32_t value)
-{
-	switch (mux_id) {
-	case MUX_CLK_ADSP_SEL:
-		io_reg_update_bits(CLK_CFG_22_CLR, (0xF << 0), (0xF << 0));
-		io_reg_update_bits(CLK_CFG_22_SET, (0xF << 0), (value << 0));
-		io_reg_write(CLK_CFG_UPDATE2, 1 << CLK_UPDATE_ADSP_CK);
-
-		tr_dbg(&clkdrv_tr, "adspclk_mux=%x, CLK_CFG_22=0x%08x\n",
-		       value, io_reg_read(CLK_CFG_22));
-		break;
-	case MUX_CLK_AUDIO_LOCAL_BUS_SEL:
-		io_reg_update_bits(CLK_CFG_28_CLR, (0xF << 16), (0xF << 16));
-		io_reg_update_bits(CLK_CFG_28_SET, (0xF << 16), (value << 16));
-		io_reg_write(CLK_CFG_UPDATE3, 1 << CLK_UPDATE_AUDIO_LOCAL_BUS_CK);
-
-		tr_dbg(&clkdrv_tr, "audio_local_bus_clk_mux=%x, CLK_CFG_28=0x%08x\n",
-		       value, io_reg_read(CLK_CFG_28));
-		break;
-	default:
-		tr_dbg(&clkdrv_tr, "error: unknown mux_id (%d)\n", mux_id);
-		break;
-	}
-
-	return 0;
-}
-
-static int clock_platform_set_cpu_freq(int clock, int freq_idx)
-{
-	uint32_t enc = cpu_freq_enc[freq_idx];
-	int clk_mux;
-	int adsp_clk_req = platform_cpu_freq[freq_idx].freq;
-
-	if (adsp_clock == adsp_clk_req)
-		return 0;
-
-	tr_info(&clkdrv_tr, "%d\n", adsp_clk_req);
-
-	/* convert res manager value to driver map */
-	clk_mux = dsp_clk_value_convert(freq_idx);
-
-	if (enc > 26000000) {
-		/* adsp pll */
-		if (!dsppll_get_enable()) {
-			clk_dsppll_enable();
-			set_mux_sel(MUX_CLK_ADSP_SEL, clk_mux);
-			set_mux_sel(MUX_CLK_AUDIO_LOCAL_BUS_SEL,
-				    CLK_AUDIO_LOCAL_BUS_SEL_MAINPLL_D_7);
-		}
-		/* set adsp pll clock */
-		io_reg_update_bits(DSPPLL_CON2, 0xffffffff, enc);
-	} else {
-		/* clk26m */
-		if (dsppll_get_enable()) {
-			set_mux_sel(MUX_CLK_AUDIO_LOCAL_BUS_SEL, CLK_AUDIO_LOCAL_BUS_SEL_26M);
-			set_mux_sel(MUX_CLK_ADSP_SEL, clk_mux);
-			clk_dsppll_disable();
-		}
-	}
-
-	adsp_clock = adsp_clk_req;
-
-	return 0;
-}
-
-void platform_clock_init(struct sof *sof)
-{
-	int i;
-
-	sof->clocks = platform_clocks_info;
-
-	for (i = 0; i < CONFIG_CORE_COUNT; i++) {
-		sof->clocks[i] = (struct clock_info){
-			.freqs_num = NUM_CPU_FREQ,
-			.freqs = platform_cpu_freq,
-			.default_freq_idx = CPU_DEFAULT_IDX,
-			.current_freq_idx = CPU_DEFAULT_IDX,
-			.notification_id = NOTIFIER_ID_CPU_FREQ,
-			.notification_mask = NOTIFIER_TARGET_CORE_MASK(i),
-			.set_freq = clock_platform_set_cpu_freq,
-		};
-	}
-
-	adsp_clock = 0;
-	dsppll_enable = 0;
-}
diff --git a/src/platform/mt8195/lib/dai.c b/src/platform/mt8195/lib/dai.c
deleted file mode 100644
index e2e291e19f6e..000000000000
--- a/src/platform/mt8195/lib/dai.c
+++ /dev/null
@@ -1,57 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-/*
- * Copyright(c) 2021 MediaTek. All rights reserved.
- *
- * Author: YC Hung <yc.hung@mediatek.com>
- */
-
-#include <sof/common.h>
-#include <sof/lib/dai.h>
-#include <sof/lib/memory.h>
-#include <rtos/sof.h>
-#include <rtos/spinlock.h>
-#include <ipc/dai.h>
-#include <ipc/stream.h>
-
-#include <sof/drivers/afe-dai.h>
-#include <mt8195-afe-common.h>
-
-static int afe_dai_handshake[MT8195_DAI_NUM] = {
-	AFE_HANDSHAKE(MT8195_AFE_IO_ETDM2_OUT, MT8195_IRQ_13, MT8195_MEMIF_DL2),
-	AFE_HANDSHAKE(MT8195_AFE_IO_ETDM1_OUT, MT8195_IRQ_14, MT8195_MEMIF_DL3),
-	AFE_HANDSHAKE(MT8195_AFE_IO_UL_SRC1, MT8195_IRQ_21, MT8195_MEMIF_UL4),
-	AFE_HANDSHAKE(MT8195_AFE_IO_ETDM2_IN, MT8195_IRQ_22, MT8195_MEMIF_UL5),
-};
-
-static struct dai afe_dai[MT8195_DAI_NUM];
-
-const struct dai_type_info dti[] = {
-	{
-		.type = SOF_DAI_MEDIATEK_AFE,
-		.dai_array = afe_dai,
-		.num_dais = ARRAY_SIZE(afe_dai),
-	},
-};
-
-const struct dai_info lib_dai = {
-	.dai_type_array = dti,
-	.num_dai_types = ARRAY_SIZE(dti),
-};
-
-int dai_init(struct sof *sof)
-{
-	int i;
-
-	/* initialize spin locks early to enable ref counting */
-	for (i = 0; i < ARRAY_SIZE(afe_dai); i++) {
-		k_spinlock_init(&afe_dai[i].lock);
-		afe_dai[i].index = AFE_HS_GET_DAI(afe_dai_handshake[i]);
-		afe_dai[i].drv = &afe_dai_driver;
-		/* TODO, fifo[0] change to target playback or capture */
-		afe_dai[i].plat_data.fifo[0].handshake = afe_dai_handshake[i];
-	}
-
-	sof->dai_info = &lib_dai;
-
-	return 0;
-}
diff --git a/src/platform/mt8195/lib/dma.c b/src/platform/mt8195/lib/dma.c
deleted file mode 100644
index 89ee43af7eac..000000000000
--- a/src/platform/mt8195/lib/dma.c
+++ /dev/null
@@ -1,59 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-/*
- * Copyright(c) 2021 MediaTek. All rights reserved.
- *
- * Author: YC Hung <yc.hung@mediatek.com>
- */
-
-#include <sof/common.h>
-#include <sof/drivers/afe-memif.h>
-#include <rtos/interrupt.h>
-#include <sof/lib/dma.h>
-#include <sof/lib/memory.h>
-#include <rtos/sof.h>
-#include <rtos/spinlock.h>
-
-#include <mt8195-afe-regs.h>
-#include <mt8195-afe-common.h>
-
-extern struct dma_ops dummy_dma_ops;
-
-static struct dma dma[PLATFORM_NUM_DMACS] = {
-{
-	.plat_data = {
-		.id		= DMA_ID_HOST,
-		.dir		= DMA_DIR_HMEM_TO_LMEM | DMA_DIR_LMEM_TO_HMEM,
-		.devs		= DMA_DEV_HOST,
-		.channels	= 16,
-	},
-	.ops	= &dummy_dma_ops,
-},
-{
-	.plat_data = {
-		.id		= DMA_ID_AFE_MEMIF,
-		.dir		= DMA_DIR_MEM_TO_DEV | DMA_DIR_DEV_TO_MEM,
-		.devs		= DMA_DEV_AFE_MEMIF,
-		.base		= AFE_BASE_ADDR,
-		.channels	= MT8195_MEMIF_NUM,
-	},
-	.ops	= &memif_ops,
-},
-};
-
-static const struct dma_info lib_dma = {
-	.dma_array = cache_to_uncache_init((struct dma *)dma),
-	.num_dmas = ARRAY_SIZE(dma)
-};
-
-int dmac_init(struct sof *sof)
-{
-	int i;
-
-	/* early lock initialization for ref counting */
-	for (i = 0; i < ARRAY_SIZE(dma); i++)
-		k_spinlock_init(&dma[i].lock);
-
-	sof->dma_info = &lib_dma;
-
-	return 0;
-}
diff --git a/src/platform/mt8195/lib/memory.c b/src/platform/mt8195/lib/memory.c
deleted file mode 100644
index 0fbfb0f5b3d1..000000000000
--- a/src/platform/mt8195/lib/memory.c
+++ /dev/null
@@ -1,101 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-/*
- * Copyright(c) 2021 MediaTek. All rights reserved.
- *
- * Author: YC Hung <yc.hung@mediatek.com>
- */
-
-#include <sof/common.h>
-#include <sof/lib/mm_heap.h>
-#include <sof/lib/memory.h>
-#include <rtos/sof.h>
-#include <ipc/topology.h>
-
-/* Heap blocks for system runtime */
-static struct block_hdr sys_rt_block64[HEAP_SYS_RT_COUNT64];
-static struct block_hdr sys_rt_block512[HEAP_SYS_RT_COUNT512];
-static struct block_hdr sys_rt_block1024[HEAP_SYS_RT_COUNT1024];
-
-/* Heap memory for system runtime */
-static struct block_map sys_rt_heap_map[] = {
-	BLOCK_DEF(64, HEAP_SYS_RT_COUNT64, sys_rt_block64),
-	BLOCK_DEF(512, HEAP_SYS_RT_COUNT512, sys_rt_block512),
-	BLOCK_DEF(1024, HEAP_SYS_RT_COUNT1024, sys_rt_block1024),
-};
-
-/* Heap blocks for modules */
-static struct block_hdr mod_block16[HEAP_RT_COUNT16];
-static struct block_hdr mod_block32[HEAP_RT_COUNT32];
-static struct block_hdr mod_block64[HEAP_RT_COUNT64];
-static struct block_hdr mod_block128[HEAP_RT_COUNT128];
-static struct block_hdr mod_block256[HEAP_RT_COUNT256];
-static struct block_hdr mod_block512[HEAP_RT_COUNT512];
-static struct block_hdr mod_block1024[HEAP_RT_COUNT1024];
-static struct block_hdr mod_block2048[HEAP_RT_COUNT2048];
-static struct block_hdr mod_block4096[HEAP_RT_COUNT4096];
-
-/* Heap memory map for modules */
-static struct block_map rt_heap_map[] = {
-	BLOCK_DEF(16, HEAP_RT_COUNT16, mod_block16),
-	BLOCK_DEF(32, HEAP_RT_COUNT32, mod_block32),
-	BLOCK_DEF(64, HEAP_RT_COUNT64, mod_block64),
-	BLOCK_DEF(128, HEAP_RT_COUNT128, mod_block128),
-	BLOCK_DEF(256, HEAP_RT_COUNT256, mod_block256),
-	BLOCK_DEF(512, HEAP_RT_COUNT512, mod_block512),
-	BLOCK_DEF(1024, HEAP_RT_COUNT1024, mod_block1024),
-	BLOCK_DEF(2048, HEAP_RT_COUNT2048, mod_block2048),
-	BLOCK_DEF(4096, HEAP_RT_COUNT4096, mod_block4096),
-};
-
-/* Heap blocks for buffers */
-static struct block_hdr buf_block[HEAP_BUFFER_COUNT];
-
-/* Heap memory map for buffers */
-static struct block_map buf_heap_map[] = {
-	BLOCK_DEF(HEAP_BUFFER_BLOCK_SIZE, HEAP_BUFFER_COUNT, buf_block),
-};
-
-static struct mm memmap = {
-	.system[0] = {
-		.heap = HEAP_SYSTEM_BASE,
-		.size = HEAP_SYSTEM_SIZE,
-		.info = {.free = HEAP_SYSTEM_SIZE,},
-		.caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_CACHE |
-			SOF_MEM_CAPS_DMA,
-	},
-	.system_runtime[0] = {
-		.blocks = ARRAY_SIZE(sys_rt_heap_map),
-		.map = sys_rt_heap_map,
-		.heap = HEAP_SYS_RUNTIME_BASE,
-		.size = HEAP_SYS_RUNTIME_SIZE,
-		.info = {.free = HEAP_SYS_RUNTIME_SIZE,},
-		.caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_CACHE |
-			SOF_MEM_CAPS_DMA,
-	},
-	.runtime[0] = {
-		.blocks = ARRAY_SIZE(rt_heap_map),
-		.map = rt_heap_map,
-		.heap = HEAP_RUNTIME_BASE,
-		.size = HEAP_RUNTIME_SIZE,
-		.info = {.free = HEAP_RUNTIME_SIZE,},
-		.caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_CACHE |
-			SOF_MEM_CAPS_DMA,
-	},
-	.buffer[0] = {
-		.blocks = ARRAY_SIZE(buf_heap_map),
-		.map = buf_heap_map,
-		.heap = HEAP_BUFFER_BASE,
-		.size = HEAP_BUFFER_SIZE,
-		.info = {.free = HEAP_BUFFER_SIZE,},
-		.caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_CACHE |
-			SOF_MEM_CAPS_DMA,
-	},
-	.total = {.free = HEAP_SYSTEM_SIZE + HEAP_SYS_RUNTIME_SIZE +
-			HEAP_RUNTIME_SIZE + HEAP_BUFFER_SIZE,},
-};
-
-void platform_init_memmap(struct sof *sof)
-{
-	/* memmap has been initialized statically as a part of .data */
-	sof->memory_map = &memmap;
-}
diff --git a/src/platform/mt8195/mt8195.x.in b/src/platform/mt8195/mt8195.x.in
deleted file mode 100644
index e34db20246cd..000000000000
--- a/src/platform/mt8195/mt8195.x.in
+++ /dev/null
@@ -1,515 +0,0 @@
-/*
- * Linker Script for mt8195 MediaTek
- *
- * This script is run through the GNU C preprocessor to align the memory
- * offsets with headers.
- *
- * Use spaces for formatting as cpp ignore tab sizes.
- */
-
-
-#include <sof/lib/memory.h>
-#include <xtensa/config/core-isa.h>
-
-OUTPUT_ARCH(xtensa)
-
-MEMORY
-{
-  vector_reset_text :
-        org = XCHAL_RESET_VECTOR0_PADDR,
-        len = SOF_MEM_RESET_TEXT_SIZE
-  vector_reset_lit :
-        org = XCHAL_RESET_VECTOR0_PADDR + SOF_MEM_RESET_TEXT_SIZE,
-        len = SOF_MEM_RESET_LIT_SIZE
-  vector_base_text :
-        org = XCHAL_VECBASE_RESET_PADDR,
-        len = SOF_MEM_VECBASE_LIT_SIZE
-  vector_int2_lit :
-        org = XCHAL_INTLEVEL2_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
-        len = SOF_MEM_VECT_LIT_SIZE
-  vector_int2_text :
-        org = XCHAL_INTLEVEL2_VECTOR_PADDR,
-        len = SOF_MEM_VECT_TEXT_SIZE
-  vector_int3_lit :
-        org = XCHAL_INTLEVEL3_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
-        len = SOF_MEM_VECT_LIT_SIZE
-  vector_int3_text :
-        org = XCHAL_INTLEVEL3_VECTOR_PADDR,
-        len = SOF_MEM_VECT_TEXT_SIZE
-  vector_int4_lit :
-        org = XCHAL_INTLEVEL4_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
-        len = SOF_MEM_VECT_LIT_SIZE
-  vector_int4_text :
-        org = XCHAL_INTLEVEL4_VECTOR_PADDR,
-        len = SOF_MEM_VECT_TEXT_SIZE
-  vector_kernel_lit :
-        org = XCHAL_KERNEL_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
-        len = SOF_MEM_VECT_LIT_SIZE
-  vector_kernel_text :
-        org = XCHAL_KERNEL_VECTOR_PADDR,
-        len = SOF_MEM_VECT_TEXT_SIZE
-  vector_user_lit :
-        org = XCHAL_USER_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
-        len = SOF_MEM_VECT_LIT_SIZE
-  vector_user_text :
-        org = XCHAL_USER_VECTOR_PADDR,
-        len = SOF_MEM_VECT_TEXT_SIZE
-  vector_double_lit :
-        org = XCHAL_DOUBLEEXC_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
-        len = SOF_MEM_VECT_LIT_SIZE
-  vector_double_text :
-        org = XCHAL_DOUBLEEXC_VECTOR_PADDR,
-        len = SOF_MEM_VECT_TEXT_SIZE
-  sof_sram0 :
-        org = SRAM0_BASE,
-        len = SRAM0_SIZE
-  sof_sram1 :
-        org = SRAM1_BASE,
-        len = SRAM1_SIZE
-  system_heap :
-        org = HEAP_SYSTEM_BASE,
-        len = HEAP_SYSTEM_SIZE
-  system_runtime_heap :
-        org = HEAP_SYS_RUNTIME_BASE,
-        len = HEAP_SYS_RUNTIME_SIZE
-  runtime_heap :
-        org = HEAP_RUNTIME_BASE,
-        len = HEAP_RUNTIME_SIZE
-  buffer_heap :
-        org = HEAP_BUFFER_BASE,
-        len = HEAP_BUFFER_SIZE
-  sof_stack :
-        org = SOF_STACK_END,
-        len = SOF_STACK_BASE - SOF_STACK_END
-  static_uuid_entries_seg (!ari) :
-        org = UUID_ENTRY_ELF_BASE,
-        len = UUID_ENTRY_ELF_SIZE
-  static_log_entries_seg (!ari) :
-        org = LOG_ENTRY_ELF_BASE,
-        len = LOG_ENTRY_ELF_SIZE
-  fw_metadata_seg (!ari) :
-        org = EXT_MANIFEST_ELF_BASE,
-        len = EXT_MANIFEST_ELF_SIZE
-}
-
-PHDRS
-{
-  vector_reset_text_phdr PT_LOAD;
-  vector_reset_lit_phdr PT_LOAD;
-  vector_base_text_phdr PT_LOAD;
-  vector_base_lit_phdr PT_LOAD;
-  vector_int2_text_phdr PT_LOAD;
-  vector_int2_lit_phdr PT_LOAD;
-  vector_int3_text_phdr PT_LOAD;
-  vector_int3_lit_phdr PT_LOAD;
-  vector_int4_text_phdr PT_LOAD;
-  vector_int4_lit_phdr PT_LOAD;
-  vector_kernel_text_phdr PT_LOAD;
-  vector_kernel_lit_phdr PT_LOAD;
-  vector_user_text_phdr PT_LOAD;
-  vector_user_lit_phdr PT_LOAD;
-  vector_double_text_phdr PT_LOAD;
-  vector_double_lit_phdr PT_LOAD;
-  sof_sram0_phdr PT_LOAD;
-  sof_sram1_phdr PT_LOAD;
-  system_heap_phdr PT_LOAD;
-  system_runtime_heap_phdr PT_LOAD;
-  runtime_heap_phdr PT_LOAD;
-  buffer_heap_phdr PT_LOAD;
-  sof_stack_phdr PT_LOAD;
-  static_uuid_entries_phdr PT_NOTE;
-  static_log_entries_phdr PT_NOTE;
-  metadata_entries_phdr PT_NOTE;
-}
-
-/*  Default entry point:  */
-ENTRY(_ResetVector)
-_rom_store_table = 0;
-
-/* ABI0 does not use Window base */
-PROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR);
-
-/* Various memory-map dependent cache attribute settings: */
-_memmap_cacheattr_wb_base = 0x00000100;
-_memmap_cacheattr_wt_base = 0x00000300;
-_memmap_cacheattr_bp_base = 0x00000400;
-_memmap_cacheattr_unused_mask = 0xFFFFF0FF;
-_memmap_cacheattr_wb_trapnull = 0x44444140;
-_memmap_cacheattr_wba_trapnull = 0x44444140;
-_memmap_cacheattr_wbna_trapnull = 0x44444240;
-_memmap_cacheattr_wt_trapnull = 0x44444340;
-_memmap_cacheattr_bp_trapnull = 0x44444440;
-_memmap_cacheattr_wb_strict = 0x00000100;
-_memmap_cacheattr_wt_strict = 0x00000300;
-_memmap_cacheattr_bp_strict = 0x00000400;
-_memmap_cacheattr_wb_allvalid = 0x44444144;
-_memmap_cacheattr_wt_allvalid = 0x44444344;
-_memmap_cacheattr_bp_allvalid = 0x44444444;
-PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);
-
-_EXT_MAN_ALIGN_ = 16;
-EXTERN(ext_man_fw_ver)
-
-SECTIONS
-{
-  .ResetVector.text : ALIGN(4)
-  {
-    _ResetVector_text_start = ABSOLUTE(.);
-    KEEP (*(.ResetVector.text))
-    _ResetVector_text_end = ABSOLUTE(.);
-  } >vector_reset_text :vector_reset_text_phdr
-
-  .ResetVector.literal : ALIGN(4)
-  {
-    _ResetVector_literal_start = ABSOLUTE(.);
-    *(.ResetVector.literal)
-    _ResetVector_literal_end = ABSOLUTE(.);
-  } >vector_reset_lit :vector_reset_lit_phdr
-
-  .WindowVectors.text : ALIGN(4)
-  {
-    _WindowVectors_text_start = ABSOLUTE(.);
-    KEEP (*(.WindowVectors.text))
-    _WindowVectors_text_end = ABSOLUTE(.);
-  } >vector_base_text :vector_base_text_phdr
-
-  .Level2InterruptVector.literal : ALIGN(4)
-  {
-    _Level2InterruptVector_literal_start = ABSOLUTE(.);
-    *(.Level2InterruptVector.literal)
-    _Level2InterruptVector_literal_end = ABSOLUTE(.);
-  } >vector_int2_lit :vector_int2_lit_phdr
-
-  .Level2InterruptVector.text : ALIGN(4)
-  {
-    _Level2InterruptVector_text_start = ABSOLUTE(.);
-    KEEP (*(.Level2InterruptVector.text))
-    _Level2InterruptVector_text_end = ABSOLUTE(.);
-  } >vector_int2_text :vector_int2_text_phdr
-
-  .Level3InterruptVector.literal : ALIGN(4)
-  {
-    _Level3InterruptVector_literal_start = ABSOLUTE(.);
-    *(.Level3InterruptVector.literal)
-    _Level3InterruptVector_literal_end = ABSOLUTE(.);
-  } >vector_int3_lit :vector_int3_lit_phdr
-
-  .Level3InterruptVector.text : ALIGN(4)
-  {
-    _Level3InterruptVector_text_start = ABSOLUTE(.);
-    KEEP (*(.Level3InterruptVector.text))
-    _Level3InterruptVector_text_end = ABSOLUTE(.);
-  } >vector_int3_text :vector_int3_text_phdr
-
-  .DebugExceptionVector.literal : ALIGN(4)
-  {
-    _DebugExceptionVector_literal_start = ABSOLUTE(.);
-    *(.DebugExceptionVector.literal)
-    _DebugExceptionVector_literal_end = ABSOLUTE(.);
-  } >vector_int4_lit :vector_int4_lit_phdr
-
-  .DebugExceptionVector.text : ALIGN(4)
-  {
-    _DebugExceptionVector_text_start = ABSOLUTE(.);
-    KEEP (*(.DebugExceptionVector.text))
-    _DebugExceptionVector_text_end = ABSOLUTE(.);
-  } >vector_int4_text :vector_int4_text_phdr
-
-  .KernelExceptionVector.literal : ALIGN(4)
-  {
-    _KernelExceptionVector_literal_start = ABSOLUTE(.);
-    *(.KernelExceptionVector.literal)
-    _KernelExceptionVector_literal_end = ABSOLUTE(.);
-  } >vector_kernel_lit :vector_kernel_lit_phdr
-
-  .KernelExceptionVector.text : ALIGN(4)
-  {
-    _KernelExceptionVector_text_start = ABSOLUTE(.);
-    KEEP (*(.KernelExceptionVector.text))
-    _KernelExceptionVector_text_end = ABSOLUTE(.);
-  } >vector_kernel_text :vector_kernel_text_phdr
-
-  .UserExceptionVector.literal : ALIGN(4)
-  {
-    _UserExceptionVector_literal_start = ABSOLUTE(.);
-    *(.UserExceptionVector.literal)
-    _UserExceptionVector_literal_end = ABSOLUTE(.);
-  } >vector_user_lit :vector_user_lit_phdr
-
-  .UserExceptionVector.text : ALIGN(4)
-  {
-    _UserExceptionVector_text_start = ABSOLUTE(.);
-    KEEP (*(.UserExceptionVector.text))
-    _UserExceptionVector_text_end = ABSOLUTE(.);
-  } >vector_user_text :vector_user_text_phdr
-
-  .DoubleExceptionVector.literal : ALIGN(4)
-  {
-    _DoubleExceptionVector_literal_start = ABSOLUTE(.);
-    *(.DoubleExceptionVector.literal)
-    _DoubleExceptionVector_literal_end = ABSOLUTE(.);
-  } >vector_double_lit :vector_double_lit_phdr
-
-  .DoubleExceptionVector.text : ALIGN(4)
-  {
-    _DoubleExceptionVector_text_start = ABSOLUTE(.);
-    KEEP (*(.DoubleExceptionVector.text))
-    _DoubleExceptionVector_text_end = ABSOLUTE(.);
-  } >vector_double_text :vector_double_text_phdr
-
-  .rodata : ALIGN(4)
-  {
-    _rodata_start = ABSOLUTE(.);
-    *(.rodata)
-    *(.rodata.*)
-    *(.gnu.linkonce.r.*)
-    *(.rodata1)
-    *(.clib.rodata)
-    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);
-    KEEP (*(.xt_except_table))
-    KEEP (*(.gcc_except_table))
-    *(.gnu.linkonce.e.*)
-    *(.gnu.version_r)
-    KEEP (*(.eh_frame))
-    /*  C++ constructor and destructor tables, properly ordered:  */
-    KEEP (*crtbegin.o(.ctors))
-    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
-    KEEP (*(SORT(.ctors.*)))
-    KEEP (*(.ctors))
-    KEEP (*crtbegin.o(.dtors))
-    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
-    KEEP (*(SORT(.dtors.*)))
-    KEEP (*(.dtors))
-    /*  C++ exception handlers table:  */
-    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);
-    *(.xt_except_desc)
-    *(.gnu.linkonce.h.*)
-    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
-    *(.xt_except_desc_end)
-    *(.dynamic)
-    *(.gnu.version_d)
-    . = ALIGN(4);		/* this table MUST be 4-byte aligned */
-    _bss_table_start = ABSOLUTE(.);
-    LONG(_bss_start)
-    LONG(_bss_end)
-    _bss_table_end = ABSOLUTE(.);
-    _rodata_end = ABSOLUTE(.);
-  } >sof_sram0 :sof_sram0_phdr
-
-  .module_init : ALIGN(4)
-  {
-   _module_init_start = ABSOLUTE(.);
-    *(*.initcall)
-    _module_init_end = ABSOLUTE(.);
-  } >sof_sram0 :sof_sram0_phdr
-
-  .text : ALIGN(4)
-  {
-    _stext = .;
-    _text_start = ABSOLUTE(.);
-    *(.entry.text)
-    *(.init.literal)
-    KEEP(*(.init))
-    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
-    *(.fini.literal)
-    KEEP(*(.fini))
-    *(.gnu.version)
-    _text_end = ABSOLUTE(.);
-    _etext = .;
-  } >sof_sram0 :sof_sram0_phdr
-
-  .reset.rodata : ALIGN(4)
-  {
-    _reset_rodata_start = ABSOLUTE(.);
-    *(.reset.rodata)
-    _reset_rodata_end = ABSOLUTE(.);
-  } >sof_sram0 :sof_sram0_phdr
-
-
-  .data : ALIGN(4)
-  {
-    _data_start = ABSOLUTE(.);
-    *(.data)
-    *(.data.*)
-    *(.gnu.linkonce.d.*)
-    KEEP(*(.gnu.linkonce.d.*personality*))
-    *(.data1)
-    *(.sdata)
-    *(.sdata.*)
-    *(.gnu.linkonce.s.*)
-    *(.sdata2)
-    *(.sdata2.*)
-    *(.clib.data)
-    *(.gnu.linkonce.s2.*)
-    KEEP(*(.jcr))
-    _trace_ctx_start = ABSOLUTE(.);
-    *(.trace_ctx)
-    _trace_ctx_end = ABSOLUTE(.);
-    _data_end = ABSOLUTE(.);
-  } >sof_sram0 :sof_sram0_phdr
-
-  .clib.data : ALIGN(4)
-  {
-    _clib_data_start = ABSOLUTE(.);
-    *(.clib.data)
-    . = ALIGN (4);
-    _clib_data_end = ABSOLUTE(.);
-  } >sof_sram0 :sof_sram0_phdr
-
-  .clib.rodata : ALIGN(4)
-  {
-    _clib_rodata_start = ABSOLUTE(.);
-    *(.clib.rodata)
-    . = ALIGN (4);
-    _clib_rodata_end = ABSOLUTE(.);
-  } >sof_sram0 :sof_sram0_phdr
-
-  .lit4 : ALIGN(4)
-  {
-    _lit4_start = ABSOLUTE(.);
-    *(*.lit4)
-    *(.lit4.*)
-    *(.gnu.linkonce.lit4.*)
-    _lit4_end = ABSOLUTE(.);
-  } >sof_sram0 :sof_sram0_phdr
-
-  .bss (NOLOAD) : ALIGN(8)
-  {
-    . = ALIGN (8);
-    _bss_start = ABSOLUTE(.);
-    *(.dynsbss)
-    *(.sbss)
-    *(.sbss.*)
-    *(.gnu.linkonce.sb.*)
-    *(.scommon)
-    *(.sbss2)
-    *(.sbss2.*)
-    *(.gnu.linkonce.sb2.*)
-    *(.dynbss)
-    *(.bss)
-    *(.bss.*)
-    *(.gnu.linkonce.b.*)
-    *(COMMON)
-    . = ALIGN (8);
-    _bss_end = ABSOLUTE(.);
-  } >sof_sram0 :sof_sram0_phdr
-
-  /* stack */
-  _end = SOF_STACK_END;
-  PROVIDE(end = SOF_STACK_END);
-  _stack_sentry = SOF_STACK_END;
-  __stack = SOF_STACK_BASE;
-
-  .debug  0 :  { *(.debug) }
-  .line  0 :  { *(.line) }
-  .debug_srcinfo  0 :  { *(.debug_srcinfo) }
-  .debug_sfnames  0 :  { *(.debug_sfnames) }
-  .debug_aranges  0 :  { *(.debug_aranges) }
-  .debug_pubnames  0 :  { *(.debug_pubnames) }
-  .debug_info  0 :  { *(.debug_info) }
-  .debug_abbrev  0 :  { *(.debug_abbrev) }
-  .debug_line  0 :  { *(.debug_line) }
-  .debug_frame  0 :  { *(.debug_frame) }
-  .debug_str  0 :  { *(.debug_str) }
-  .debug_loc  0 :  { *(.debug_loc) }
-  .debug_macinfo  0 :  { *(.debug_macinfo) }
-  .debug_weaknames  0 :  { *(.debug_weaknames) }
-  .debug_funcnames  0 :  { *(.debug_funcnames) }
-  .debug_typenames  0 :  { *(.debug_typenames) }
-  .debug_varnames  0 :  { *(.debug_varnames) }
-
-  .xt.insn 0 :
-  {
-    KEEP (*(.xt.insn))
-    KEEP (*(.gnu.linkonce.x.*))
-  }
-  .xt.prop 0 :
-  {
-    KEEP (*(.xt.prop))
-    KEEP (*(.xt.prop.*))
-    KEEP (*(.gnu.linkonce.prop.*))
-  }
-  .xt.lit 0 :
-  {
-    KEEP (*(.xt.lit))
-    KEEP (*(.xt.lit.*))
-    KEEP (*(.gnu.linkonce.p.*))
-  }
-  .xt.profile_range 0 :
-  {
-    KEEP (*(.xt.profile_range))
-    KEEP (*(.gnu.linkonce.profile_range.*))
-  }
-  .xt.profile_ranges 0 :
-  {
-    KEEP (*(.xt.profile_ranges))
-    KEEP (*(.gnu.linkonce.xt.profile_ranges.*))
-  }
-  .xt.profile_files 0 :
-  {
-    KEEP (*(.xt.profile_files))
-    KEEP (*(.gnu.linkonce.xt.profile_files.*))
-  }
-
-  .system_heap (NOLOAD) : ALIGN(8)
-  {
-    . = ALIGN (32);
-    _system_heap_start = ABSOLUTE(.);
-    . = . + HEAP_SYSTEM_SIZE;
-    _system_heap_end = ABSOLUTE(.);
-  } >system_heap :system_heap_phdr
-
-  .system_runtime_heap (NOLOAD) : ALIGN(8)
-  {
-    . = ALIGN (HEAP_BUF_ALIGNMENT);
-    _system_runtime_heap_start = ABSOLUTE(.);
-    . = . + HEAP_SYS_RUNTIME_SIZE;
-    _system_runtime_heap_end = ABSOLUTE(.);
-  } >system_runtime_heap :system_runtime_heap_phdr
-
-  .runtime_heap (NOLOAD) : ALIGN(8)
-  {
-    . = ALIGN (32);
-    _runtime_heap_start = ABSOLUTE(.);
-    . = . + HEAP_RUNTIME_SIZE;
-    _runtime_heap_end = ABSOLUTE(.);
-  } >runtime_heap :runtime_heap_phdr
-
-  .buffer_heap (NOLOAD) : ALIGN(8)
-  {
-    . = ALIGN (HEAP_BUF_ALIGNMENT);
-    _buffer_heap_start = ABSOLUTE(.);
-    . = . + HEAP_BUFFER_SIZE;
-    _buffer_heap_end = ABSOLUTE(.);
-  } >buffer_heap :buffer_heap_phdr
-
-  .sof_stack (NOLOAD) : ALIGN(8)
-  {
-    . = ALIGN (4096);
-    _sof_stack_start = ABSOLUTE(.);
-    . = . + SOF_STACK_TOTAL_SIZE;
-    _sof_stack_end = ABSOLUTE(.);
-  } >sof_stack :sof_stack_phdr
-
-  .static_uuid_entries (COPY) : ALIGN(1024)
-  {
-    *(*.static_uuids)
-  } > static_uuid_entries_seg :static_uuid_entries_phdr
-
-  .static_log_entries (COPY) : ALIGN(1024)
-  {
-    *(*.static_log*)
-  } > static_log_entries_seg :static_log_entries_phdr
-
-  .fw_ready : ALIGN(4)
-  {
-    KEEP (*(.fw_ready))
-    KEEP (*(.fw_ready_metadata))
-  } >sof_sram0 :sof_sram0_phdr
-
-  .fw_metadata (COPY) : ALIGN(1024)
-  {
-    KEEP (*(.fw_metadata))
-    . = ALIGN(_EXT_MAN_ALIGN_);
-  } >fw_metadata_seg :metadata_entries_phdr
-}
diff --git a/src/platform/mt8195/platform.c b/src/platform/mt8195/platform.c
deleted file mode 100644
index c1e59049b57a..000000000000
--- a/src/platform/mt8195/platform.c
+++ /dev/null
@@ -1,251 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-/*
- * Copyright(c) 2021 MediaTek. All rights reserved.
- *
- * Author: YC Hung <yc.hung@mediatek.com>
- *         Allen-KH Cheng <allen-kh.cheng@mediatek.com>
- */
-
-#include <sof/compiler_info.h>
-#include <sof/debug/debug.h>
-#include <sof/drivers/edma.h>
-#include <rtos/interrupt.h>
-#include <sof/ipc/msg.h>
-#include <rtos/timer.h>
-#include <sof/fw-ready-metadata.h>
-#include <sof/lib/agent.h>
-#include <rtos/clk.h>
-#include <sof/lib/cpu.h>
-#include <sof/lib/dai.h>
-#include <sof/lib/dma.h>
-#include <sof/lib/mailbox.h>
-#include <sof/lib/memory.h>
-#include <sof/lib/mm_heap.h>
-#include <sof/platform.h>
-#include <sof/schedule/edf_schedule.h>
-#include <sof/schedule/ll_schedule.h>
-#include <sof/schedule/ll_schedule_domain.h>
-#include <rtos/sof.h>
-#include <sof/trace/dma-trace.h>
-#include <platform/drivers/timer.h>
-#include <ipc/dai.h>
-#include <ipc/header.h>
-#include <ipc/info.h>
-#include <kernel/abi.h>
-#include <kernel/ext_manifest.h>
-#include <sof_versions.h>
-#include <errno.h>
-#include <stdint.h>
-#include <xtensa/hal.h>
-
-struct sof;
-
-static const struct sof_ipc_fw_ready ready
-	__section(".fw_ready") = {
-	.hdr = {
-		.cmd = SOF_IPC_FW_READY,
-		.size = sizeof(struct sof_ipc_fw_ready),
-	},
-	/* dspbox is for DSP initiated IPC, hostbox is for host initiated IPC */
-	.version = {
-		.hdr.size = sizeof(struct sof_ipc_fw_version),
-		.micro = SOF_MICRO,
-		.minor = SOF_MINOR,
-		.major = SOF_MAJOR,
-		.tag = SOF_TAG,
-		.abi_version = SOF_ABI_VERSION,
-		.src_hash = SOF_SRC_HASH,
-	},
-	.flags = DEBUG_SET_FW_READY_FLAGS,
-};
-
-#define NUM_MTK_WINDOWS 6
-
-const struct ext_man_windows xsram_window
-		__aligned(EXT_MAN_ALIGN) __section(".fw_metadata") __unused = {
-	.hdr = {
-		.type = EXT_MAN_ELEM_WINDOW,
-		.elem_size = ALIGN_UP_COMPILE(sizeof(struct ext_man_windows), EXT_MAN_ALIGN),
-	},
-	.window = {
-		.ext_hdr	= {
-			.hdr.cmd = SOF_IPC_FW_READY,
-			.hdr.size = sizeof(struct sof_ipc_window),
-			.type	= SOF_IPC_EXT_WINDOW,
-		},
-		.num_windows	= NUM_MTK_WINDOWS,
-		.window	= {
-			{
-				.type	= SOF_IPC_REGION_UPBOX,
-				.id	= 0,	/* map to host window 0 */
-				.flags	= 0, /* TODO: set later */
-				.size	= MAILBOX_DSPBOX_SIZE,
-				.offset	= MAILBOX_DSPBOX_OFFSET,
-			},
-			{
-				.type	= SOF_IPC_REGION_DOWNBOX,
-				.id	= 0,	/* map to host window 0 */
-				.flags	= 0, /* TODO: set later */
-				.size	= MAILBOX_HOSTBOX_SIZE,
-				.offset	= MAILBOX_HOSTBOX_OFFSET,
-			},
-			{
-				.type	= SOF_IPC_REGION_DEBUG,
-				.id	= 0,	/* map to host window 0 */
-				.flags	= 0, /* TODO: set later */
-				.size	= MAILBOX_DEBUG_SIZE,
-				.offset	= MAILBOX_DEBUG_OFFSET,
-			},
-			{
-				.type	= SOF_IPC_REGION_TRACE,
-				.id	= 0,	/* map to host window 0 */
-				.flags	= 0, /* TODO: set later */
-				.size	= MAILBOX_TRACE_SIZE,
-				.offset	= MAILBOX_TRACE_OFFSET,
-			},
-			{
-				.type	= SOF_IPC_REGION_STREAM,
-				.id	= 0,	/* map to host window 0 */
-				.flags	= 0, /* TODO: set later */
-				.size	= MAILBOX_STREAM_SIZE,
-				.offset	= MAILBOX_STREAM_OFFSET,
-			},
-			{
-				.type	= SOF_IPC_REGION_EXCEPTION,
-				.id	= 0,	/* map to host window 0 */
-				.flags	= 0, /* TODO: set later */
-				.size	= MAILBOX_EXCEPTION_SIZE,
-				.offset	= MAILBOX_EXCEPTION_OFFSET,
-			},
-		},
-	}
-};
-
-static struct timer timer_shared = {
-	.id = OSTIMER0,
-	.irq = LX_ADSP_TIMTER_IRQ0_B,
-};
-
-/* Override the default MPU setup. This table matches the memory map
- * of the 'sample_controller' core and will need to be modified for
- * other cores.
- * NOTE: This table sets up all of external memory as shared uncached.
- * For best results, edit the LSP memory map to create a separate
- * section in shared memory, place all sections that need to be uncached
- * into that section, and only map that section uncached. See README
- * for more details.
- */
-const unsigned int __xt_mpu_init_table_size __attribute__((section(".ResetVector.text"))) = 11;
-
-const struct xthal_MPU_entry __xt_mpu_init_table[] __attribute__((section(".ResetVector.text"))) = {
-	XTHAL_MPU_ENTRY(0x00000000, 1, XTHAL_AR_NONE,
-			XTHAL_MEM_DEVICE), /* illegal: no access */
-	XTHAL_MPU_ENTRY(0x0C000000, 1, XTHAL_AR_RWrw,
-			XTHAL_MEM_DEVICE), /* MCU & DBG Registers read/write */
-	XTHAL_MPU_ENTRY(0x0F000000, 1, XTHAL_AR_NONE,
-			XTHAL_MEM_DEVICE), /* illegal: no access */
-	XTHAL_MPU_ENTRY(0x10000000, 1, XTHAL_AR_RWrw,
-			XTHAL_MEM_DEVICE), /* DSP register: read/write */
-	XTHAL_MPU_ENTRY(0x12000000, 1, XTHAL_AR_NONE,
-			XTHAL_MEM_DEVICE), /* illegal: no access */
-	XTHAL_MPU_ENTRY(0x40000000, 1, XTHAL_AR_RWXrwx,
-			XTHAL_MEM_WRITEBACK), /* DSP SRAM: read/write/execute writeback */
-	XTHAL_MPU_ENTRY(0x40040000, 1, XTHAL_AR_NONE,
-			XTHAL_MEM_DEVICE), /* illegal: no access */
-	XTHAL_MPU_ENTRY(0x60000000, 1, XTHAL_AR_RWXrwx,
-			XTHAL_MEM_WRITEBACK), /* DRAM: read/write/execute writeback */
-	XTHAL_MPU_ENTRY(0x60800000, 1, XTHAL_AR_RWrw,
-			XTHAL_MEM_WRITEBACK), /* DRAM: read/write writeback */
-	XTHAL_MPU_ENTRY(0x61000000, 1, XTHAL_AR_RWrw,
-			XTHAL_MEM_DEVICE), /* DMA: read/write writeback */
-	XTHAL_MPU_ENTRY(0x61100000, 1, XTHAL_AR_NONE,
-			XTHAL_MEM_DEVICE), /* illegal: no access */
-};
-
-int platform_boot_complete(uint32_t boot_message)
-{
-	mailbox_dspbox_write(0, &ready, sizeof(ready));
-
-	/* now interrupt host to tell it we are done booting */
-	trigger_irq_to_host_req();
-
-	/* boot now complete so we can relax the CPU */
-	/* For now skip this to gain more processing performance
-	 * for SRC component.
-	 */
-	clock_set_freq(CLK_CPU(cpu_get_id()), CLK_DEFAULT_CPU_HZ);
-
-	return 0;
-}
-
-int platform_init(struct sof *sof)
-{
-	int ret;
-
-	sof->platform_timer = &timer_shared;
-	sof->cpu_timers = sof->platform_timer;
-
-	platform_interrupt_init();
-	platform_clock_init(sof);
-	scheduler_init_edf();
-
-	/* init low latency domains and schedulers */
-	sof->platform_timer_domain = timer_domain_init(sof->platform_timer, PLATFORM_DEFAULT_CLOCK);
-	scheduler_init_ll(sof->platform_timer_domain);
-
-	platform_timer_start(sof->platform_timer);
-	sa_init(sof, CONFIG_SYSTICK_PERIOD);
-
-	clock_set_freq(CLK_CPU(cpu_get_id()), CLK_MAX_CPU_HZ);
-
-	/* init DMA */
-	ret = dmac_init(sof);
-	if (ret < 0)
-		return -ENODEV;
-
-	/* Init platform domain */
-	sof->platform_dma_domain = dma_multi_chan_domain_init(&sof->dma_info->dma_array[0], 1,
-							      PLATFORM_DEFAULT_CLOCK, false);
-	scheduler_init_ll(sof->platform_dma_domain);
-
-	/* initialize the host IPC mechanims */
-	ipc_init(sof);
-
-	ret = dai_init(sof);
-	if (ret < 0)
-		return -ENODEV;
-
-#if CONFIG_TRACE
-	/* Initialize DMA for Trace*/
-	trace_point(TRACE_BOOT_PLATFORM_DMA_TRACE);
-	dma_trace_init_complete(sof->dmat);
-#endif
-
-	/* show heap status */
-	heap_trace_all(1);
-
-	return 0;
-}
-
-int platform_context_save(struct sof *sof)
-{
-	return 0;
-}
-
-void platform_wait_for_interrupt(int level)
-{
-	arch_wait_for_interrupt(level);
-}
-
-#ifdef __XCC__
-/* This is a stub for the Xtensa libc (not their newlib version),
- * which inexplicably wants to pull in an unlink() implementation when
- * linked against the C++ standard library.  Obviously nothing in SOF
- * uses the C library filesystem layer, this is just spurious.
- */
-int __attribute__((weak)) _unlink_r(struct _reent *ptr, const char *file);
-int __attribute__((weak)) _unlink_r(struct _reent *ptr, const char *file)
-{
-	return -1;
-}
-#endif
diff --git a/src/platform/mt8196/CMakeLists.txt b/src/platform/mt8196/CMakeLists.txt
deleted file mode 100644
index f7a68fd4ea31..000000000000
--- a/src/platform/mt8196/CMakeLists.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-
-add_subdirectory(lib)
-
-add_local_sources(sof platform.c afe-platform.c)
-target_include_directories(sof_options INTERFACE ${PROJECT_SOURCE_DIR}/src/platform/mt8196/include/arch)
-target_include_directories(sof_options INTERFACE ${PROJECT_SOURCE_DIR}/src/platform/mt8196/include/platform)
diff --git a/src/platform/mt8196/afe-platform.c b/src/platform/mt8196/afe-platform.c
deleted file mode 100755
index 3d9452772ba7..000000000000
--- a/src/platform/mt8196/afe-platform.c
+++ /dev/null
@@ -1,281 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-/*
- * Copyright(c) 2024 MediaTek. All rights reserved.
- *
- * Author: Darren Ye <darren.ye@mediatek.com>
- */
-
-#include <sof/common.h>
-#include <errno.h>
-#include <sof/drivers/afe-drv.h>
-#include <mt8196-afe-reg.h>
-#include <mt8196-afe-common.h>
-
-/*
- * AFE: Audio Front-End
- *
- * frontend (memif):
- *   memory interface
- *   UL (uplink for capture)
- *   DL (downlink for playback)
- * backend:
- *   TDM In
- *   TDM Out
- *   DMIC
- *   GASRC
- *   I2S Out
- *   I2S In
- *   etc.
- * interconn:
- *   inter-connection,
- *   connect frontends and backends as DSP path
- */
-
-static const struct mtk_base_memif_data memif_data[MT8196_MEMIF_NUM] = {
-	[MT8196_MEMIF_DL1] = {
-		.name = "DL1",
-		.id = MT8196_MEMIF_DL1,
-		.reg_ofs_base = AFE_DL1_BASE,
-		.reg_ofs_cur = AFE_DL1_CUR,
-		.reg_ofs_end = AFE_DL1_END,
-		.reg_ofs_base_msb = AFE_DL1_BASE_MSB,
-		.reg_ofs_cur_msb = AFE_DL1_CUR_MSB,
-		.reg_ofs_end_msb = AFE_DL1_END_MSB,
-		.fs_reg = AFE_DL1_CON0,
-		.fs_shift = DL1_SEL_FS_SFT,
-		.fs_maskbit = DL1_SEL_FS_MASK,
-		.mono_reg = AFE_DL1_CON0,
-		.mono_shift = DL1_MONO_SFT,
-		.int_odd_flag_reg = -1,
-		.int_odd_flag_shift = 0,
-		.enable_reg = AFE_DL1_CON0,
-		.enable_shift = DL1_ON_SFT,
-		.hd_reg = AFE_DL1_CON0,
-		.hd_shift = DL1_HD_MODE_SFT,
-		.hd_align_reg = AFE_DL1_CON0,
-		.hd_align_mshift = DL1_HALIGN_SFT,
-		.agent_disable_reg = -1,
-		.agent_disable_shift = -1,
-		.ch_num_reg = -1,
-		.msb_reg = -1,
-		.msb_shift = -1,
-		.pbuf_reg = AFE_DL1_CON0,
-		.pbuf_mask = DL1_PBUF_SIZE_MASK,
-		.pbuf_shift = DL1_PBUF_SIZE_SFT,
-		.minlen_reg = AFE_DL1_CON0,
-		.minlen_mask = DL1_MINLEN_MASK,
-		.minlen_shift = DL1_MINLEN_SFT,
-	},
-	[MT8196_MEMIF_DL_24CH] = {
-		.name = "DL_24CH",
-		.id = MT8196_MEMIF_DL_24CH,
-		.reg_ofs_base = AFE_DL_24CH_BASE,
-		.reg_ofs_cur = AFE_DL_24CH_CUR,
-		.reg_ofs_end = AFE_DL_24CH_END,
-		.reg_ofs_base_msb = AFE_DL_24CH_BASE_MSB,
-		.reg_ofs_cur_msb = AFE_DL_24CH_CUR_MSB,
-		.reg_ofs_end_msb = AFE_DL_24CH_END_MSB,
-		.fs_reg = AFE_DL_24CH_CON0,
-		.fs_shift = DL_24CH_SEL_FS_SFT,
-		.fs_maskbit = DL_24CH_SEL_FS_MASK,
-		.mono_reg = -1,
-		.mono_shift = -1,
-		.int_odd_flag_reg = -1,
-		.int_odd_flag_shift = 0,
-		.enable_reg = AFE_DL_24CH_CON0,
-		.enable_shift = DL_24CH_ON_SFT,
-		.hd_reg = AFE_DL_24CH_CON0,
-		.hd_shift = DL_24CH_HD_MODE_SFT,
-		.hd_align_reg = AFE_DL_24CH_CON0,
-		.hd_align_mshift = DL_24CH_HALIGN_SFT,
-		.agent_disable_reg = -1,
-		.agent_disable_shift = -1,
-		.msb_reg = -1,
-		.msb_shift = -1,
-		.pbuf_reg = AFE_DL_24CH_CON0,
-		.pbuf_mask = DL_24CH_PBUF_SIZE_MASK,
-		.pbuf_shift = DL_24CH_PBUF_SIZE_SFT,
-		.minlen_reg = AFE_DL_24CH_CON0,
-		.minlen_mask = DL_24CH_MINLEN_MASK,
-		.minlen_shift = DL_24CH_MINLEN_SFT,
-		.ch_num_reg = AFE_DL_24CH_CON0,
-		.ch_num_maskbit = DL_24CH_NUM_MASK,
-		.ch_num_shift = DL_24CH_NUM_SFT,
-	},
-	[MT8196_MEMIF_UL0] = {
-		.name = "UL0",
-		.id = MT8196_MEMIF_UL0,
-		.reg_ofs_base = AFE_VUL0_BASE,
-		.reg_ofs_cur = AFE_VUL0_CUR,
-		.reg_ofs_end = AFE_VUL0_END,
-		.reg_ofs_base_msb = AFE_VUL0_BASE_MSB,
-		.reg_ofs_cur_msb = AFE_VUL0_CUR_MSB,
-		.reg_ofs_end_msb = AFE_VUL0_END_MSB,
-		.fs_reg = AFE_VUL0_CON0,
-		.fs_shift = VUL0_SEL_FS_SFT,
-		.fs_maskbit = VUL0_SEL_FS_MASK,
-		.mono_reg = AFE_VUL0_CON0,
-		.mono_shift = VUL0_MONO_SFT,
-		.int_odd_flag_reg = -1,
-		.int_odd_flag_shift = 0,
-		.enable_reg = AFE_VUL0_CON0,
-		.enable_shift = VUL0_ON_SFT,
-		.hd_reg = AFE_VUL0_CON0,
-		.hd_shift = VUL0_HD_MODE_SFT,
-		.hd_align_reg = AFE_VUL0_CON0,
-		.hd_align_mshift = VUL0_HALIGN_SFT,
-		.agent_disable_reg = -1,
-		.agent_disable_shift = -1,
-		.msb_reg = -1,
-		.msb_shift = -1,
-	},
-	[MT8196_MEMIF_UL1] = {
-		.name = "UL1",
-		.id = MT8196_MEMIF_UL1,
-		.reg_ofs_base = AFE_VUL1_BASE,
-		.reg_ofs_cur = AFE_VUL1_CUR,
-		.reg_ofs_end = AFE_VUL1_END,
-		.reg_ofs_base_msb = AFE_VUL1_BASE_MSB,
-		.reg_ofs_cur_msb = AFE_VUL1_CUR_MSB,
-		.reg_ofs_end_msb = AFE_VUL1_END_MSB,
-		.fs_reg = AFE_VUL1_CON0,
-		.fs_shift = VUL1_SEL_FS_SFT,
-		.fs_maskbit = VUL1_SEL_FS_MASK,
-		.mono_reg = AFE_VUL1_CON0,
-		.mono_shift = VUL1_MONO_SFT,
-		.enable_reg = AFE_VUL1_CON0,
-		.enable_shift = VUL1_ON_SFT,
-		.hd_reg = AFE_VUL1_CON0,
-		.hd_shift = VUL1_HD_MODE_SFT,
-		.hd_align_reg = AFE_VUL1_CON0,
-		.hd_align_mshift = VUL1_HALIGN_SFT,
-		.agent_disable_reg = -1,
-		.agent_disable_shift = -1,
-		.msb_reg = -1,
-		.msb_shift = -1,
-	},
-	[MT8196_MEMIF_UL2] = {
-		.name = "UL2",
-		.id = MT8196_MEMIF_UL2,
-		.reg_ofs_base = AFE_VUL2_BASE,
-		.reg_ofs_cur = AFE_VUL2_CUR,
-		.reg_ofs_end = AFE_VUL2_END,
-		.reg_ofs_base_msb = AFE_VUL2_BASE_MSB,
-		.reg_ofs_cur_msb = AFE_VUL2_CUR_MSB,
-		.reg_ofs_end_msb = AFE_VUL2_END_MSB,
-		.fs_reg = AFE_VUL2_CON0,
-		.fs_shift = VUL2_SEL_FS_SFT,
-		.fs_maskbit = VUL2_SEL_FS_MASK,
-		.mono_reg = AFE_VUL2_CON0,
-		.mono_shift = VUL2_MONO_SFT,
-		.int_odd_flag_reg = -1,
-		.int_odd_flag_shift = 0,
-		.enable_reg = AFE_VUL2_CON0,
-		.enable_shift = VUL2_ON_SFT,
-		.hd_reg = AFE_VUL2_CON0,
-		.hd_shift = VUL2_HD_MODE_SFT,
-		.hd_align_reg = AFE_VUL2_CON0,
-		.hd_align_mshift = VUL2_HALIGN_SFT,
-		.agent_disable_reg = -1,
-		.agent_disable_shift = -1,
-		.msb_reg = -1,
-		.msb_shift = -1,
-	},
-};
-
-struct mt8196_afe_rate {
-	unsigned int rate;
-	unsigned int reg_value;
-};
-
-static const struct mt8196_afe_rate mt8196_afe_rates[] = {
-	{
-		.rate = 8000,
-		.reg_value = 0,
-	},
-	{
-		.rate = 12000,
-		.reg_value = 2,
-	},
-	{
-		.rate = 16000,
-		.reg_value = 4,
-	},
-	{
-		.rate = 24000,
-		.reg_value = 6,
-	},
-	{
-		.rate = 32000,
-		.reg_value = 8,
-	},
-	{
-		.rate = 48000,
-		.reg_value = 0x0a,
-	},
-	{
-		.rate = 96000,
-		.reg_value = 14,
-	},
-	{
-		.rate = 192000,
-		.reg_value = 18,
-	},
-	{
-		.rate = 384000,
-		.reg_value = 22,
-	},
-	{
-		.rate = 11025,
-		.reg_value = 1,
-	},
-	{
-		.rate = 22050,
-		.reg_value = 5,
-	},
-	{
-		.rate = 44100,
-		.reg_value = 9,
-	},
-	{
-		.rate = 88200,
-		.reg_value = 13,
-	},
-	{
-		.rate = 176400,
-		.reg_value = 17,
-	},
-	{
-		.rate = 352800,
-		.reg_value = 21,
-	},
-};
-
-static unsigned int mt8196_afe_fs_timing(unsigned int rate)
-{
-	int i;
-
-	for (i = 0; i < ARRAY_SIZE(mt8196_afe_rates); i++)
-		if (mt8196_afe_rates[i].rate == rate)
-			return mt8196_afe_rates[i].reg_value;
-
-	return -EINVAL;
-}
-
-static unsigned int mt8196_afe_fs(unsigned int rate, int aud_blk)
-{
-	return mt8196_afe_fs_timing(rate);
-}
-
-struct mtk_base_afe_platform mtk_afe_platform = {
-	.base_addr = AFE_BASE_ADDR,
-	.memif_datas = memif_data,
-	.memif_size = MT8196_MEMIF_NUM,
-	.memif_dl_num = MT8196_MEMIF_DL_NUM,
-	.memif_32bit_supported = 0,
-	.irq_datas = NULL,
-	.irqs_size = 0,
-	.dais_size = MT8196_DAI_NUM,
-	.afe_fs = mt8196_afe_fs,
-	.irq_fs = mt8196_afe_fs_timing,
-};
diff --git a/src/platform/mt8196/include/arch/xtensa/config/core-isa.h b/src/platform/mt8196/include/arch/xtensa/config/core-isa.h
deleted file mode 100644
index b0d7ed6a7c67..000000000000
--- a/src/platform/mt8196/include/arch/xtensa/config/core-isa.h
+++ /dev/null
@@ -1,831 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
- *				processor CORE configuration
- *
- *  See <xtensa/config/core.h>, which includes this file, for more details.
- */
-
-/* Xtensa processor core configuration information.
- *
- * Customer ID=7578; Build=0xa69ab; Copyright (c) 1999-2023 Tensilica Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef XTENSA_CORE_CONFIGURATION_H_
-#define XTENSA_CORE_CONFIGURATION_H_
-
-/****************************************************************************
- *	    Parameters Useful for Any Code, USER or PRIVILEGED
- ****************************************************************************
- */
-
-/*
- *  Note:  Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
- *  configured, and a value of 0 otherwise.  These macros are always defined.
- */
-
-/*----------------------------------------------------------------------
- *				ISA
- *----------------------------------------------------------------------
- */
-
-#define XCHAL_HAVE_BE			0	/* big-endian byte ordering */
-#define XCHAL_HAVE_WINDOWED		1	/* windowed registers option */
-#define XCHAL_NUM_AREGS			64	/* num of physical addr regs */
-#define XCHAL_NUM_AREGS_LOG2		6	/* log2(XCHAL_NUM_AREGS) */
-#define XCHAL_MAX_INSTRUCTION_SIZE	16	/* max instr bytes (3..8) */
-#define XCHAL_HAVE_DEBUG		1	/* debug option */
-#define XCHAL_HAVE_DENSITY		1	/* 16-bit instructions */
-#define XCHAL_HAVE_LOOPS		1	/* zero-overhead loops */
-#define XCHAL_LOOP_BUFFER_SIZE		256	/* zero-ov. loop instr buffer size */
-#define XCHAL_HAVE_NSA			1	/* NSA/NSAU instructions */
-#define XCHAL_HAVE_MINMAX		1	/* MIN/MAX instructions */
-#define XCHAL_HAVE_SEXT			1	/* SEXT instruction */
-#define XCHAL_HAVE_DEPBITS		0	/* DEPBITS instruction */
-#define XCHAL_HAVE_CLAMPS		1	/* CLAMPS instruction */
-#define XCHAL_HAVE_MUL16		1	/* MUL16S/MUL16U instructions */
-#define XCHAL_HAVE_MUL32		1	/* MULL instruction */
-#define XCHAL_HAVE_MUL32_HIGH		0	/* MULUH/MULSH instructions */
-#define XCHAL_HAVE_DIV32		1	/* QUOS/QUOU/REMS/REMU instructions */
-#define XCHAL_HAVE_L32R			1	/* L32R instruction */
-#define XCHAL_HAVE_ABSOLUTE_LITERALS	0	/* non-PC-rel (extended) L32R */
-#define XCHAL_HAVE_CONST16		0	/* CONST16 instruction */
-#define XCHAL_HAVE_ADDX			1	/* ADDX#/SUBX# instructions */
-#define XCHAL_HAVE_EXCLUSIVE            1	/* L32EX/S32EX instructions */
-#define XCHAL_HAVE_WIDE_BRANCHES	0	/* B*.W18 or B*.W15 instr's */
-#define XCHAL_HAVE_PREDICTED_BRANCHES	0	/* B[EQ/EQZ/NE/NEZ]T instr's */
-#define XCHAL_HAVE_CALL4AND12		1	/* (obsolete option) */
-#define XCHAL_HAVE_ABS			1	/* ABS instruction */
-#define XCHAL_HAVE_RELEASE_SYNC		1	/* L32AI/S32RI instructions */
-#define XCHAL_HAVE_S32C1I		0	/* S32C1I instruction */
-#define XCHAL_HAVE_SPECULATION		0	/* speculation */
-#define XCHAL_HAVE_FULL_RESET		1	/* all regs/state reset */
-#define XCHAL_NUM_CONTEXTS		1	/* */
-#define XCHAL_NUM_MISC_REGS		4	/* num of scratch regs (0..4) */
-#define XCHAL_HAVE_TAP_MASTER		0	/* JTAG TAP control instr's */
-#define XCHAL_HAVE_PRID			1	/* processor ID register */
-#define XCHAL_HAVE_EXTERN_REGS		1	/* WER/RER instructions */
-#define XCHAL_HAVE_MX			0	/* MX core (Tensilica internal) */
-#define XCHAL_HAVE_MP_INTERRUPTS	0	/* interrupt distributor port */
-#define XCHAL_HAVE_MP_RUNSTALL		0	/* core RunStall control port */
-#define XCHAL_HAVE_PSO			0	/* Power Shut-Off */
-#define XCHAL_HAVE_PSO_CDM		0	/* core/debug/mem pwr domains */
-#define XCHAL_HAVE_PSO_FULL_RETENTION	0	/* all regs preserved on PSO */
-#define XCHAL_HAVE_THREADPTR		1	/* THREADPTR register */
-#define XCHAL_HAVE_BOOLEANS		1	/* boolean registers */
-#define XCHAL_HAVE_CP			1	/* CPENABLE reg (coprocessor) */
-#define XCHAL_CP_MAXCFG			2	/* max allowed cp id plus one */
-#define XCHAL_HAVE_MAC16		0	/* MAC16 package */
-#define XCHAL_HAVE_LX			1	/* LX core */
-#define XCHAL_HAVE_NX     0	/* NX core (starting RH) */
-#define XCHAL_HAVE_RNX    0	/* RNX core (starting RJ) */
-
-#define XCHAL_HAVE_SUPERGATHER		0	/* SuperGather */
-
-#define XCHAL_HAVE_FUSION		0                      /* Fusion */
-#define XCHAL_HAVE_FUSION_FP		0	/* Fusion FP option */
-#define XCHAL_HAVE_FUSION_LOW_POWER	0	/* Fusion Low Power option */
-#define XCHAL_HAVE_FUSION_AES		0	/* Fusion BLE/Wifi AES-128 CCM option */
-#define XCHAL_HAVE_FUSION_CONVENC	0	/* Fusion Conv Encode option */
-#define XCHAL_HAVE_FUSION_LFSR_CRC	0	/* Fusion LFSR-CRC option */
-#define XCHAL_HAVE_FUSION_BITOPS	0	/* Fusion Bit Operations Support option */
-#define XCHAL_HAVE_FUSION_AVS		0	/* Fusion AVS option */
-#define XCHAL_HAVE_FUSION_16BIT_BASEBAND 0	/* Fusion 16-bit Baseband option */
-#define XCHAL_HAVE_FUSION_VITERBI	0	/* Fusion Viterbi option */
-#define XCHAL_HAVE_FUSION_SOFTDEMAP	0	/* Fusion Soft Bit Demap option */
-#define XCHAL_HAVE_HIFIPRO		0	/* HiFiPro Audio Engine pkg */
-#define XCHAL_HAVE_HIFI5		1	/* HiFi5 Audio Engine pkg */
-#define XCHAL_HAVE_HIFI5_NN_MAC		1	/* HiFi5 Audio Engine NN-MAC option */
-
-/* HiFi5 Audio Engine Single--Precision VFPU option */
-#define XCHAL_HAVE_HIFI5_VFPU		1
-#define XCHAL_HAVE_HIFI5_HP_VFPU	1	/* HiFi5 Audio Engine Half-Precision VFPU option */
-#define XCHAL_HAVE_HIFI4		0	/* HiFi4 Audio Engine pkg */
-#define XCHAL_HAVE_HIFI4_VFPU		1	/* HiFi4 Audio Engine VFPU option */
-#define XCHAL_HAVE_HIFI3		1	/* HiFi3 Audio Engine pkg */
-#define XCHAL_HAVE_HIFI3_VFPU		1	/* HiFi3 Audio Engine VFPU option */
-#define XCHAL_HAVE_HIFI3Z		0	/* HiFi3Z Audio Engine pkg */
-#define XCHAL_HAVE_HIFI3Z_VFPU	0	/* HiFi3Z Audio Engine VFPU option */
-#define XCHAL_HAVE_HIFI1		0	/* HiFi1 */
-#define XCHAL_HAVE_HIFI1_VFPU		0	/* HiFi1 VFPU option */
-/* HiFi1 Low-latency MAC/FMA option */
-#define XCHAL_HAVE_HIFI1_LOW_LATENCY_MAC_FMA		0
-#define XCHAL_HAVE_HIFI2		0	/* HiFi2 Audio Engine pkg */
-#define XCHAL_HAVE_HIFI2EP		0	/* HiFi2EP */
-#define XCHAL_HAVE_HIFI_MINI		0
-
-#define XCHAL_HAVE_VECTORFPU2005	0	/* vector floating-point pkg */
-#define XCHAL_HAVE_USER_DPFPU		0       /* user DP floating-point pkg */
-#define XCHAL_HAVE_USER_SPFPU		1       /* user SP floating-point pkg */
-#define XCHAL_HAVE_FP			1	/* single prec floating point */
-#define XCHAL_HAVE_FP_DIV		1	/* FP with DIV instructions */
-#define XCHAL_HAVE_FP_RECIP		1	/* FP with RECIP instructions */
-#define XCHAL_HAVE_FP_SQRT		1	/* FP with SQRT instructions */
-#define XCHAL_HAVE_FP_RSQRT		1	/* FP with RSQRT instructions */
-#define XCHAL_HAVE_DFP			0	/* double precision FP pkg */
-#define XCHAL_HAVE_DFP_DIV		0	/* DFP with DIV instructions */
-#define XCHAL_HAVE_DFP_RECIP		0	/* DFP with RECIP instructions*/
-#define XCHAL_HAVE_DFP_SQRT		0	/* DFP with SQRT instructions */
-#define XCHAL_HAVE_DFP_RSQRT		0	/* DFP with RSQRT instructions*/
-#define XCHAL_HAVE_DFP_ACCEL		0	/* double precision FP acceleration pkg */
-#define XCHAL_HAVE_DFP_accel		XCHAL_HAVE_DFP_ACCEL	/* for backward compatibility */
-
-#define XCHAL_HAVE_DFPU_SINGLE_ONLY	0	/* DFPU Coprocessor, single precision only */
-#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE	0	/* DFPU Coprocessor, single and double precision */
-#define XCHAL_HAVE_VECTRA1		0	/* Vectra I  pkg */
-#define XCHAL_HAVE_VECTRALX		0	/* Vectra LX pkg */
-
-#define XCHAL_HAVE_FUSIONG		0    /* FusionG */
-#define XCHAL_HAVE_FUSIONG3		0    /* FusionG3 */
-#define XCHAL_HAVE_FUSIONG6		0    /* FusionG6 */
-#define XCHAL_HAVE_FUSIONG_SP_VFPU	0    /* sp_vfpu option on FusionG */
-#define XCHAL_HAVE_FUSIONG_DP_VFPU	0    /* dp_vfpu option on FusionG */
-#define XCHAL_FUSIONG_SIMD32		0    /* simd32 for FusionG */
-
-#define XCHAL_HAVE_FUSIONJ		0    /* FusionJ */
-#define XCHAL_HAVE_FUSIONJ6		0    /* FusionJ6 */
-#define XCHAL_HAVE_FUSIONJ_SP_VFPU	0    /* sp_vfpu option on FusionJ */
-#define XCHAL_HAVE_FUSIONJ_DP_VFPU	0    /* dp_vfpu option on FusionJ */
-#define XCHAL_FUSIONJ_SIMD32		0    /* simd32 for FusionJ */
-
-#define XCHAL_HAVE_PDX			0    /* PDX-LX */
-#define XCHAL_PDX_SIMD32		0    /* simd32 for PDX */
-#define XCHAL_HAVE_PDX4			0    /* PDX4-LX */
-#define XCHAL_HAVE_PDX8			0    /* PDX8-LX */
-#define XCHAL_HAVE_PDX16		0    /* PDX16-LX */
-#define XCHAL_HAVE_PDXNX		0    /* PDX-NX */
-
-#define XCHAL_HAVE_CONNXD2		0	/* ConnX D2 pkg */
-#define XCHAL_HAVE_CONNXD2_DUALLSFLIX   0	/* ConnX D2 & Dual LoadStore Flix */
-#define XCHAL_HAVE_BALL			0
-#define XCHAL_HAVE_BALLAP		0
-#define XCHAL_HAVE_BBE16		0	/* ConnX BBE16 pkg */
-#define XCHAL_HAVE_BBE16_RSQRT		0	/* BBE16 & vector recip sqrt */
-#define XCHAL_HAVE_BBE16_VECDIV		0	/* BBE16 & vector divide */
-#define XCHAL_HAVE_BBE16_DESPREAD	0	/* BBE16 & despread */
-#define XCHAL_HAVE_CONNX_B10            0    /* ConnX B10 pkg*/
-#define XCHAL_HAVE_CONNX_B20            0    /* ConnX B20 pkg*/
-
-/* Double-precision Vector Floating-point option on ConnX B10 & B20 */
-#define XCHAL_HAVE_CONNX_B_DP_VFPU      0
-/* Double-precision Vector Floating-point option on FP Machine*/
-#define XCHAL_HAVE_CONNX_B_DPX_VFPU     0
-/* Single-precision Vector Floating-point option on ConnX B10 & B20 */
-#define XCHAL_HAVE_CONNX_B_SP_VFPU      0
-/* Single-precision Extended Vector Floating-point option on ConnX B10 & B20 */
-#define XCHAL_HAVE_CONNX_B_SPX_VFPU     0
-/* Half-precision Vector Floating-point option on ConnX B10 & B20 */
-#define XCHAL_HAVE_CONNX_B_HP_VFPU      0
-/* Half-precision Extended Vector Floating-point option on ConnX B10 & B20 */
-#define XCHAL_HAVE_CONNX_B_HPX_VFPU     0
-/* 32-bit vector MAC (real and complex), FIR & FFT option on ConnX B10 & B20 */
-#define XCHAL_HAVE_CONNX_B_32B_MAC      0
-#define XCHAL_HAVE_CONNX_B_VITERBI      0    /* Viterbi option on ConnX B10 & B20 */
-#define XCHAL_HAVE_CONNX_B_TURBO        0    /* Turbo option on ConnX B10 & B20 */
-#define XCHAL_HAVE_CONNX_B_LDPC         0    /* LDPC option on ConnX B10 & B20 */
-#define XCHAL_HAVE_BBENEP		0	/* ConnX BBENEP pkgs */
-#define XCHAL_HAVE_BBENEP_SP_VFPU	0       /* sp_vfpu option on BBE-EP */
-#define XCHAL_HAVE_BSP3			0	/* ConnX BSP3 pkg */
-#define XCHAL_HAVE_BSP3_TRANSPOSE	0	/* BSP3 & transpose32x32 */
-#define XCHAL_HAVE_SSP16		0	/* ConnX SSP16 pkg */
-#define XCHAL_HAVE_SSP16_VITERBI	0	/* SSP16 & viterbi */
-#define XCHAL_HAVE_TURBO16		0	/* ConnX Turbo16 pkg */
-#define XCHAL_HAVE_BBP16		0	/* ConnX BBP16 pkg */
-#define XCHAL_HAVE_FLIX3		0	/* basic 3-way FLIX option */
-#define XCHAL_HAVE_GRIVPEP		0	/* General Release of IVPEP */
-#define XCHAL_HAVE_GRIVPEP_HISTOGRAM	0       /* Histogram option on GRIVPEP */
-
-#define XCHAL_HAVE_VISION	        0     /* Vision P5/P6 */
-#define XCHAL_VISION_SIMD16             0     /* simd16 for Vision P5/P6 */
-#define XCHAL_VISION_TYPE               0     /* Vision P5, P6, Q6, Q7 or Q8 */
-#define XCHAL_VISION_QUAD_MAC_TYPE      0     /* quad_mac option on Vision P6 */
-#define XCHAL_HAVE_VISION_HISTOGRAM     0     /* histogram option on Vision P5/P6 */
-#define XCHAL_HAVE_VISION_DP_VFPU       0     /* dp_vfpu option on Vision Q7/Q8 */
-#define XCHAL_HAVE_VISION_SP_VFPU       0     /* sp_vfpu option on Vision P5/P6/Q6/Q7 */
-#define XCHAL_HAVE_VISION_SP_VFPU_2XFMAC 0     /* sp_vfpu_2xfma option on Vision Q7 */
-#define XCHAL_HAVE_VISION_HP_VFPU       0     /* hp_vfpu option on Vision P6/Q6 */
-#define XCHAL_HAVE_VISION_HP_VFPU_2XFMAC 0     /* hp_vfpu_2xfma option on Vision Q7 */
-
-#define XCHAL_HAVE_VISIONC	        0     /* Vision C */
-
-#define XCHAL_HAVE_XNNE			0		/* XNNE */
-
-/*----------------------------------------------------------------------
- *			MISC
- *----------------------------------------------------------------------
- */
-
-#define XCHAL_NUM_LOADSTORE_UNITS	2	/* load/store units */
-#define XCHAL_NUM_WRITEBUFFER_ENTRIES	32	/* size of write buffer */
-#define XCHAL_INST_FETCH_WIDTH		16	/* instr-fetch width in bytes */
-#define XCHAL_DATA_WIDTH		16	/* data width in bytes */
-
-/* d-side pipeline delay (1 = 5-stage, 2 = 7-stage) */
-#define XCHAL_DATA_PIPE_DELAY		2
-#define XCHAL_CLOCK_GATING_GLOBAL	1	/* global clock gating */
-#define XCHAL_CLOCK_GATING_FUNCUNIT	1	/* funct. unit clock gating */
-/*  In T1050, applies to selected core load and store instructions (see ISA): */
-#define XCHAL_UNALIGNED_LOAD_EXCEPTION	1	/* unaligned loads cause exc. */
-#define XCHAL_UNALIGNED_STORE_EXCEPTION	1	/* unaligned stores cause exc.*/
-#define XCHAL_UNALIGNED_LOAD_HW		0	/* unaligned loads work in hw */
-#define XCHAL_UNALIGNED_STORE_HW	0	/* unaligned stores work in hw*/
-
-#define XCHAL_UNIFIED_LOADSTORE         0
-
-#define XCHAL_SW_VERSION		1411000	/* sw version of this header */
-#define XCHAL_SW_VERSION_MAJOR		14000	/* major ver# of sw          */
-#define XCHAL_SW_VERSION_MINOR		11	/* minor ver# of sw          */
-#define XCHAL_SW_VERSION_MICRO		0	/* micro ver# of sw          */
-#define XCHAL_SW_MINOR_VERSION		1411000	/* with zeroed micro */
-#define XCHAL_SW_MICRO_VERSION		1411000
-
-/* alphanum core name (CoreID) set in the Xtensa Processor Generator */
-#define XCHAL_CORE_ID			"HiFi5_MPU_lock_2023_11"
-
-#define XCHAL_BUILD_UNIQUE_ID		0x000A69AB	/* 22-bit sw build ID */
-
-/*
- *  These definitions describe the hardware targeted by this software.
- */
-#define XCHAL_HW_CONFIGID0		0xC003B286	/* ConfigID hi 32 bits*/
-#define XCHAL_HW_CONFIGID1		0x2A09D04B	/* ConfigID lo 32 bits*/
-#define XCHAL_HW_VERSION_NAME		"LX7.1.8"	/* full version name */
-#define XCHAL_HW_VERSION_MAJOR		2810	/* major ver# of targeted hw */
-#define XCHAL_HW_VERSION_MINOR		8	/* minor ver# of targeted hw */
-#define XCHAL_HW_VERSION_MICRO		0	/* subdot ver# of targeted hw */
-/* major*100+(major<2810 ? minor : minor*10+micro) */
-#define XCHAL_HW_VERSION		281080
-#define XCHAL_HW_REL_LX7		1
-#define XCHAL_HW_REL_LX7_1		1
-#define XCHAL_HW_REL_LX7_1_8		1
-#define XCHAL_HW_CONFIGID_RELIABLE	1
-/*  If software targets a *range* of hardware versions, these are the bounds: */
-#define XCHAL_HW_MIN_VERSION_MAJOR	2810	/* major v of earliest tgt hw */
-#define XCHAL_HW_MIN_VERSION_MINOR	8	/* minor v of earliest tgt hw */
-#define XCHAL_HW_MIN_VERSION_MICRO	0	/* micro v of earliest tgt hw */
-#define XCHAL_HW_MIN_VERSION		281080	/* earliest targeted hw */
-#define XCHAL_HW_MAX_VERSION_MAJOR	2810	/* major v of latest tgt hw */
-#define XCHAL_HW_MAX_VERSION_MINOR	8	/* minor v of latest tgt hw */
-#define XCHAL_HW_MAX_VERSION_MICRO	0	/* micro v of latest tgt hw */
-#define XCHAL_HW_MAX_VERSION		281080	/* latest targeted hw */
-
-/*  Config is enabled for functional safety: */
-#define XCHAL_HAVE_FUNC_SAFETY		0
-
-/*  Config is enabled for secure operation: */
-#define XCHAL_HAVE_SECURE     0
-
-#define XCHAL_HAVE_APB			0
-
-/*----------------------------------------------------------------------
- *				CACHE
- *----------------------------------------------------------------------
- */
-
-#define XCHAL_ICACHE_LINESIZE		128	/* I-cache line size in bytes */
-#define XCHAL_DCACHE_LINESIZE		128	/* D-cache line size in bytes */
-#define XCHAL_ICACHE_LINEWIDTH		7	/* log2(I line size in bytes) */
-#define XCHAL_DCACHE_LINEWIDTH		7	/* log2(D line size in bytes) */
-
-#define XCHAL_ICACHE_SIZE		65536	/* I-cache size in bytes or 0 */
-#define XCHAL_ICACHE_SIZE_LOG2		16
-#define XCHAL_DCACHE_SIZE		131072	/* D-cache size in bytes or 0 */
-#define XCHAL_DCACHE_SIZE_LOG2		17
-
-#define XCHAL_DCACHE_IS_WRITEBACK	1	/* writeback feature */
-#define XCHAL_DCACHE_IS_COHERENT	0	/* MP coherence feature */
-
-#define XCHAL_HAVE_PREFETCH		1	/* PREFCTL register */
-#define XCHAL_HAVE_PREFETCH_L1		1	/* prefetch to L1 cache */
-#define XCHAL_PREFETCH_CASTOUT_LINES	2	/* dcache pref. castout bufsz */
-#define XCHAL_PREFETCH_ENTRIES		16	/* cache prefetch entries */
-#define XCHAL_PREFETCH_BLOCK_ENTRIES	0	/* prefetch block streams */
-#define XCHAL_HAVE_CACHE_BLOCKOPS	0	/* block prefetch for caches */
-#define XCHAL_HAVE_CME_DOWNGRADES	0
-#define XCHAL_HAVE_ICACHE_TEST		1	/* Icache test instructions */
-#define XCHAL_HAVE_DCACHE_TEST		1	/* Dcache test instructions */
-#define XCHAL_HAVE_ICACHE_DYN_WAYS	1	/* Icache dynamic way support */
-#define XCHAL_HAVE_DCACHE_DYN_WAYS	1	/* Dcache dynamic way support */
-#define XCHAL_HAVE_ICACHE_DYN_ENABLE	1	/* Icache enabled via MEMCTL */
-#define XCHAL_HAVE_DCACHE_DYN_ENABLE	1	/* Dcache enabled via MEMCTL */
-
-#define XCHAL_L1SCACHE_SIZE		0
-#define XCHAL_L1SCACHE_SIZE_LOG2	0
-#define XCHAL_L1SCACHE_WAYS		1
-#define XCHAL_L1SCACHE_WAYS_LOG2	0
-#define XCHAL_L1SCACHE_ACCESS_SIZE	0
-#define XCHAL_L1SCACHE_BANKS		1
-
-#define XCHAL_L1VCACHE_SIZE		0
-
-#define XCHAL_HAVE_L2			0	/* NX L2 cache controller */
-#define XCHAL_HAVE_L2_CACHE		0
-#define XCHAL_NUM_CORES_IN_CLUSTER	0
-
-/* PRID_ID macros are for internal use only ... subject to removal */
-#define PRID_ID_SHIFT           0
-#define PRID_ID_BITS            4
-#define PRID_ID_MASK            0x0000000F
-
-/*  This one is a form of caching, though not architecturally visible:  */
-#define XCHAL_HAVE_BRANCH_PREDICTION	0	/* branch [target] prediction */
-
-/****************************************************************************
- *   Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
- ****************************************************************************/
-
-#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
-
-/*----------------------------------------------------------------------
- *			CACHE
- *----------------------------------------------------------------------
- */
-
-#define XCHAL_HAVE_PIF			1	/* any outbound bus present */
-
-#define XCHAL_HAVE_AXI			1	/* AXI bus */
-#define XCHAL_HAVE_AXI_ECC		1	/* ECC on AXI bus */
-#define XCHAL_HAVE_ACELITE		0	/* ACELite bus */
-
-#define XCHAL_HAVE_PIF_WR_RESP			1	/* pif write response */
-#define XCHAL_HAVE_PIF_REQ_ATTR			1	/* pif attribute */
-
-/*  If present, cache size in bytes == (ways * 2^(linewidth + setwidth)).  */
-
-/*  Number of cache sets in log2(lines per way):  */
-#define XCHAL_ICACHE_SETWIDTH		7
-#define XCHAL_DCACHE_SETWIDTH		8
-
-/*  Cache set associativity (number of ways):  */
-#define XCHAL_ICACHE_WAYS		4
-#define XCHAL_ICACHE_WAYS_LOG2		2
-#define XCHAL_DCACHE_WAYS		4
-#define XCHAL_DCACHE_WAYS_LOG2		2
-
-/*  Cache features:  */
-#define XCHAL_ICACHE_LINE_LOCKABLE	1
-#define XCHAL_DCACHE_LINE_LOCKABLE	1
-#define XCHAL_ICACHE_ECC_PARITY		0
-#define XCHAL_DCACHE_ECC_PARITY		0
-#define XCHAL_ICACHE_ECC_WIDTH		4
-#define XCHAL_DCACHE_ECC_WIDTH		1
-
-/*  Cache access size in bytes (affects operation of SICW instruction):  */
-#define XCHAL_ICACHE_ACCESS_SIZE	16
-#define XCHAL_DCACHE_ACCESS_SIZE	16
-
-#define XCHAL_DCACHE_BANKS		2	/* number of banks */
-
-/* The number of Cache lines associated with a single cache tag */
-#define XCHAL_DCACHE_LINES_PER_TAG_LOG2	0
-
-/*  Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits):  */
-
-/*  Extended memory attributes supported.  */
-#define XCHAL_HAVE_EXT_CA		0
-
-/*----------------------------------------------------------------------
- *			INTERNAL I/D RAM/ROMs and XLMI
- *----------------------------------------------------------------------
- */
-#define XCHAL_NUM_INSTROM		0	/* number of core instr. ROMs */
-#define XCHAL_NUM_INSTRAM		1	/* number of core instr. RAMs */
-#define XCHAL_NUM_DATAROM		0	/* number of core data ROMs */
-#define XCHAL_NUM_DATARAM		2	/* number of core data RAMs */
-#define XCHAL_NUM_URAM			0	/* number of core unified RAMs*/
-#define XCHAL_NUM_XLMI			0	/* number of core XLMI ports */
-#define	XCHAL_HAVE_IRAMCFG		0	/* IRAMxCFG register present */
-#define	XCHAL_HAVE_DRAMCFG		0	/* DRAMxCFG register present */
-
-/*  Instruction RAM 0:  */
-#define XCHAL_INSTRAM0_VADDR		0x3FFF0000	/* virtual address */
-#define XCHAL_INSTRAM0_PADDR		0x3FFF0000	/* physical address */
-#define XCHAL_INSTRAM0_SIZE		262144	/* size in bytes */
-#define XCHAL_INSTRAM0_ECC_PARITY	0	/* ECC/parity type, 0=none */
-#define XCHAL_HAVE_INSTRAM0		1
-#define XCHAL_INSTRAM0_HAVE_IDMA	0	/* idma supported by this local memory */
-
-/*  Data RAM 0:  */
-#define XCHAL_DATARAM0_VADDR		0x3FFE8000	/* virtual address */
-#define XCHAL_DATARAM0_PADDR		0x3FFE8000	/* physical address */
-#define XCHAL_DATARAM0_SIZE		65536	/* size in bytes */
-#define XCHAL_DATARAM0_ECC_PARITY	0	/* ECC/parity type, 0=none */
-#define XCHAL_DATARAM0_BANKS		2	/* number of banks */
-#define XCHAL_HAVE_DATARAM0		1
-#define XCHAL_DATARAM0_HAVE_IDMA	0	/* idma supported by this local memory */
-
-/*  Data RAM 1:  */
-#define XCHAL_DATARAM1_VADDR		0x3FFE9000	/* virtual address */
-#define XCHAL_DATARAM1_PADDR		0x3FFE9000	/* physical address */
-#define XCHAL_DATARAM1_SIZE		131072	/* size in bytes */
-#define XCHAL_DATARAM1_ECC_PARITY	0	/* ECC/parity type, 0=none */
-#define XCHAL_DATARAM1_BANKS		2	/* number of banks */
-#define XCHAL_HAVE_DATARAM1		1
-#define XCHAL_DATARAM1_HAVE_IDMA	0	/* idma supported by this local memory */
-
-#define XCHAL_HAVE_IMEM_LOADSTORE	1	/* can load/store to IROM/IRAM*/
-
-/*----------------------------------------------------------------------
- *		IDMA
- *----------------------------------------------------------------------
- */
-
-#define XCHAL_HAVE_IDMA			0
-
-/*----------------------------------------------------------------------
- *		INTERRUPTS and TIMERS
- *----------------------------------------------------------------------
- */
-
-#define XCHAL_HAVE_INTERRUPTS		1	/* interrupt option */
-#define XCHAL_HAVE_NMI			1	/* non-maskable interrupt */
-#define XCHAL_HAVE_CCOUNT		1	/* CCOUNT reg. (timer option) */
-#define XCHAL_NUM_TIMERS		3	/* number of CCOMPAREn regs */
-#define XCHAL_NUM_INTERRUPTS		32	/* number of interrupts */
-#define XCHAL_NUM_INTERRUPTS_LOG2	5	/* ceil(log2(NUM_INTERRUPTS)) */
-#define XCHAL_NUM_EXTINTERRUPTS		26	/* num of external interrupts */
-/* number of interrupt levels (not including level zero) */
-#define XCHAL_NUM_INTLEVELS		5
-#define XCHAL_INTERRUPT_RANGE		32	/* range of interrupt numbers */
-
-#define XCHAL_HAVE_HIGHPRI_INTERRUPTS	1   /* med/high-pri. interrupts */
-#define XCHAL_EXCM_LEVEL		3	/* level masked by PS.EXCM */
-	/* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
-
-/*  Masks of interrupts at each interrupt level:  */
-#define XCHAL_INTLEVEL1_MASK		0x040000FF
-#define XCHAL_INTLEVEL2_MASK		0xA800FF00
-#define XCHAL_INTLEVEL3_MASK		0x518F0000
-#define XCHAL_INTLEVEL4_MASK		0x00700000
-#define XCHAL_INTLEVEL5_MASK		0x00000000
-#define XCHAL_INTLEVEL6_MASK		0x02000000
-#define XCHAL_INTLEVEL7_MASK		0x00000000
-
-/*  Masks of interrupts at each range 1..n of interrupt levels:  */
-#define XCHAL_INTLEVEL1_ANDBELOW_MASK	0x040000FF
-#define XCHAL_INTLEVEL2_ANDBELOW_MASK	0xAC00FFFF
-#define XCHAL_INTLEVEL3_ANDBELOW_MASK	0xFD8FFFFF
-#define XCHAL_INTLEVEL4_ANDBELOW_MASK	0xFDFFFFFF
-#define XCHAL_INTLEVEL5_ANDBELOW_MASK	0xFDFFFFFF
-#define XCHAL_INTLEVEL6_ANDBELOW_MASK	0xFFFFFFFF
-#define XCHAL_INTLEVEL7_ANDBELOW_MASK	0xFFFFFFFF
-
-/*  Level of each interrupt:  */
-#define XCHAL_INT0_LEVEL		1
-#define XCHAL_INT1_LEVEL		1
-#define XCHAL_INT2_LEVEL		1
-#define XCHAL_INT3_LEVEL		1
-#define XCHAL_INT4_LEVEL		1
-#define XCHAL_INT5_LEVEL		1
-#define XCHAL_INT6_LEVEL		1
-#define XCHAL_INT7_LEVEL		1
-#define XCHAL_INT8_LEVEL		2
-#define XCHAL_INT9_LEVEL		2
-#define XCHAL_INT10_LEVEL		2
-#define XCHAL_INT11_LEVEL		2
-#define XCHAL_INT12_LEVEL		2
-#define XCHAL_INT13_LEVEL		2
-#define XCHAL_INT14_LEVEL		2
-#define XCHAL_INT15_LEVEL		2
-#define XCHAL_INT16_LEVEL		3
-#define XCHAL_INT17_LEVEL		3
-#define XCHAL_INT18_LEVEL		3
-#define XCHAL_INT19_LEVEL		3
-#define XCHAL_INT20_LEVEL		4
-#define XCHAL_INT21_LEVEL		4
-#define XCHAL_INT22_LEVEL		4
-#define XCHAL_INT23_LEVEL		3
-#define XCHAL_INT24_LEVEL		3
-#define XCHAL_INT25_LEVEL		6
-#define XCHAL_INT26_LEVEL		1
-#define XCHAL_INT27_LEVEL		2
-#define XCHAL_INT28_LEVEL		3
-#define XCHAL_INT29_LEVEL		2
-#define XCHAL_INT30_LEVEL		3
-#define XCHAL_INT31_LEVEL		2
-#define XCHAL_DEBUGLEVEL		5	/* debug interrupt level */
-#define XCHAL_HAVE_DEBUG_EXTERN_INT	1	/* OCD external db interrupt */
-/* NMI "level" (for use with EXCSAVE/EPS/EPC_n, RFI n) */
-#define XCHAL_NMILEVEL			6
-
-/*  Type of each interrupt:  */
-#define XCHAL_INT0_TYPE   XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT1_TYPE   XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT2_TYPE   XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT3_TYPE   XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT4_TYPE   XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT5_TYPE   XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT6_TYPE   XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT7_TYPE   XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT8_TYPE   XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT9_TYPE   XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT10_TYPE    XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT11_TYPE    XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT12_TYPE    XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT13_TYPE    XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT14_TYPE    XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT15_TYPE    XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT16_TYPE    XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT17_TYPE    XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT18_TYPE    XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT19_TYPE    XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT20_TYPE    XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT21_TYPE    XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT22_TYPE    XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT23_TYPE    XTHAL_INTTYPE_EXTERN_EDGE
-#define XCHAL_INT24_TYPE    XTHAL_INTTYPE_EXTERN_EDGE
-#define XCHAL_INT25_TYPE    XTHAL_INTTYPE_NMI
-#define XCHAL_INT26_TYPE    XTHAL_INTTYPE_TIMER
-#define XCHAL_INT27_TYPE    XTHAL_INTTYPE_TIMER
-#define XCHAL_INT28_TYPE    XTHAL_INTTYPE_TIMER
-#define XCHAL_INT29_TYPE    XTHAL_INTTYPE_PROFILING
-#define XCHAL_INT30_TYPE    XTHAL_INTTYPE_WRITE_ERROR
-#define XCHAL_INT31_TYPE    XTHAL_INTTYPE_SOFTWARE
-
-/*  Masks of interrupts for each type of interrupt:  */
-#define XCHAL_INTTYPE_MASK_UNCONFIGURED	0x00000000
-#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL	0x007FFFFF
-#define XCHAL_INTTYPE_MASK_EXTERN_EDGE	0x01800000
-#define XCHAL_INTTYPE_MASK_NMI		0x02000000
-#define XCHAL_INTTYPE_MASK_SOFTWARE	0x80000000
-#define XCHAL_INTTYPE_MASK_TIMER	0x1C000000
-#define XCHAL_INTTYPE_MASK_ETIE		0x00000000
-#define XCHAL_INTTYPE_MASK_WRITE_ERROR	0x40000000
-#define XCHAL_INTTYPE_MASK_DBG_REQUEST	0x00000000
-#define XCHAL_INTTYPE_MASK_BREAKIN	0x00000000
-#define XCHAL_INTTYPE_MASK_TRAX		0x00000000
-#define XCHAL_INTTYPE_MASK_PROFILING	0x20000000
-#define XCHAL_INTTYPE_MASK_IDMA_DONE	0x00000000
-#define XCHAL_INTTYPE_MASK_IDMA_ERR	0x00000000
-#define XCHAL_INTTYPE_MASK_GS_ERR	0x00000000
-#define XCHAL_INTTYPE_MASK_L2_ERR	0x00000000
-#define XCHAL_INTTYPE_MASK_L2_STATUS	0x00000000
-#define XCHAL_INTTYPE_MASK_COR_ECC_ERR	0x00000000
-#define XCHAL_INTTYPE_MASK_WWDT		0x00000000
-#define XCHAL_INTTYPE_MASK_FXLK		0x00000000
-
-/*  Interrupt numbers assigned to specific interrupt sources:  */
-#define XCHAL_TIMER0_INTERRUPT		26	/* CCOMPARE0 */
-#define XCHAL_TIMER1_INTERRUPT		27	/* CCOMPARE1 */
-#define XCHAL_TIMER2_INTERRUPT		28	/* CCOMPARE2 */
-#define XCHAL_TIMER3_INTERRUPT		XTHAL_TIMER_UNCONFIGURED
-#define XCHAL_NMI_INTERRUPT		25	/* non-maskable interrupt */
-#define XCHAL_WRITE_ERROR_INTERRUPT	30
-#define XCHAL_PROFILING_INTERRUPT	29
-
-/*  Interrupt numbers for levels at which only one interrupt is configured:  */
-#define XCHAL_INTLEVEL6_NUM		25
-/*  (There are many interrupts each at level(s) 1, 2, 3, 4.)  */
-
-/*
- *  External interrupt mapping.
- *  These macros describe how Xtensa processor interrupt numbers
- *  (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
- *  map to external BInterrupt<n> pins, for those interrupts
- *  configured as external (level-triggered, edge-triggered, or NMI).
- *  See the Xtensa processor databook for more details.
- */
-
-/*  Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number:  */
-#define XCHAL_EXTINT0_NUM		0	/* (intlevel 1) */
-#define XCHAL_EXTINT1_NUM		1	/* (intlevel 1) */
-#define XCHAL_EXTINT2_NUM		2	/* (intlevel 1) */
-#define XCHAL_EXTINT3_NUM		3	/* (intlevel 1) */
-#define XCHAL_EXTINT4_NUM		4	/* (intlevel 1) */
-#define XCHAL_EXTINT5_NUM		5	/* (intlevel 1) */
-#define XCHAL_EXTINT6_NUM		6	/* (intlevel 1) */
-#define XCHAL_EXTINT7_NUM		7	/* (intlevel 1) */
-#define XCHAL_EXTINT8_NUM		8	/* (intlevel 2) */
-#define XCHAL_EXTINT9_NUM		9	/* (intlevel 2) */
-#define XCHAL_EXTINT10_NUM		10	/* (intlevel 2) */
-#define XCHAL_EXTINT11_NUM		11	/* (intlevel 2) */
-#define XCHAL_EXTINT12_NUM		12	/* (intlevel 2) */
-#define XCHAL_EXTINT13_NUM		13	/* (intlevel 2) */
-#define XCHAL_EXTINT14_NUM		14	/* (intlevel 2) */
-#define XCHAL_EXTINT15_NUM		15	/* (intlevel 2) */
-#define XCHAL_EXTINT16_NUM		16	/* (intlevel 3) */
-#define XCHAL_EXTINT17_NUM		17	/* (intlevel 3) */
-#define XCHAL_EXTINT18_NUM		18	/* (intlevel 3) */
-#define XCHAL_EXTINT19_NUM		19	/* (intlevel 3) */
-#define XCHAL_EXTINT20_NUM		20	/* (intlevel 4) */
-#define XCHAL_EXTINT21_NUM		21	/* (intlevel 4) */
-#define XCHAL_EXTINT22_NUM		22	/* (intlevel 4) */
-#define XCHAL_EXTINT23_NUM		23	/* (intlevel 3) */
-#define XCHAL_EXTINT24_NUM		24	/* (intlevel 3) */
-#define XCHAL_EXTINT25_NUM		25	/* (intlevel 6) */
-/*  EXTERNAL BInterrupt pin numbers mapped to each core interrupt number:  */
-#define XCHAL_INT0_EXTNUM		0	/* (intlevel 1) */
-#define XCHAL_INT1_EXTNUM		1	/* (intlevel 1) */
-#define XCHAL_INT2_EXTNUM		2	/* (intlevel 1) */
-#define XCHAL_INT3_EXTNUM		3	/* (intlevel 1) */
-#define XCHAL_INT4_EXTNUM		4	/* (intlevel 1) */
-#define XCHAL_INT5_EXTNUM		5	/* (intlevel 1) */
-#define XCHAL_INT6_EXTNUM		6	/* (intlevel 1) */
-#define XCHAL_INT7_EXTNUM		7	/* (intlevel 1) */
-#define XCHAL_INT8_EXTNUM		8	/* (intlevel 2) */
-#define XCHAL_INT9_EXTNUM		9	/* (intlevel 2) */
-#define XCHAL_INT10_EXTNUM		10	/* (intlevel 2) */
-#define XCHAL_INT11_EXTNUM		11	/* (intlevel 2) */
-#define XCHAL_INT12_EXTNUM		12	/* (intlevel 2) */
-#define XCHAL_INT13_EXTNUM		13	/* (intlevel 2) */
-#define XCHAL_INT14_EXTNUM		14	/* (intlevel 2) */
-#define XCHAL_INT15_EXTNUM		15	/* (intlevel 2) */
-#define XCHAL_INT16_EXTNUM		16	/* (intlevel 3) */
-#define XCHAL_INT17_EXTNUM		17	/* (intlevel 3) */
-#define XCHAL_INT18_EXTNUM		18	/* (intlevel 3) */
-#define XCHAL_INT19_EXTNUM		19	/* (intlevel 3) */
-#define XCHAL_INT20_EXTNUM		20	/* (intlevel 4) */
-#define XCHAL_INT21_EXTNUM		21	/* (intlevel 4) */
-#define XCHAL_INT22_EXTNUM		22	/* (intlevel 4) */
-#define XCHAL_INT23_EXTNUM		23	/* (intlevel 3) */
-#define XCHAL_INT24_EXTNUM		24	/* (intlevel 3) */
-#define XCHAL_INT25_EXTNUM		25	/* (intlevel 6) */
-
-#define	XCHAL_HAVE_ISB			0	/* No ISB */
-#define	XCHAL_ISB_VADDR			0	/* N/A    */
-#define	XCHAL_HAVE_ITB			0	/* No ITB */
-#define	XCHAL_ITB_VADDR			0	/* N/A    */
-
-#define	XCHAL_HAVE_KSL			0	/* Kernel Stack Limit */
-#define	XCHAL_HAVE_ISL			0	/* Interrupt Stack Limit */
-#define	XCHAL_HAVE_PSL			0	/* Pageable Stack Limit */
-
-/*----------------------------------------------------------------------
- *		EXCEPTIONS and VECTORS
- *----------------------------------------------------------------------
- */
-
-/* Xtensa Exception Architecture
- *	     number: 1 == XEA1 (until T1050)
- *						   2 == XEA2 (LX)
- *						   3 == XEA3 (NX)
- *						   0 == XEA5 (RNX)
- */
-#define XCHAL_XEA_VERSION		2
-#define XCHAL_HAVE_XEA1			0	/* Exception Architecture 1 */
-#define XCHAL_HAVE_XEA2			1	/* Exception Architecture 2 */
-#define XCHAL_HAVE_XEA3			0	/* Exception Architecture 3 */
-#define XCHAL_HAVE_XEA5			0	/* Exception Architecture 5 */
-#define XCHAL_HAVE_EXCEPTIONS		1	/* exception option */
-#define XCHAL_HAVE_IMPRECISE_EXCEPTIONS	0	/* imprecise exception option */
-#define	XCHAL_EXCCAUSE_NUM		64	/* Number of exceptions */
-#define XCHAL_HAVE_HALT			0	/* halt architecture option */
-#define XCHAL_HAVE_BOOTLOADER		0	/* boot loader (for TX) */
-#define XCHAL_HAVE_MEM_ECC_PARITY	0	/* local memory ECC/parity */
-#define XCHAL_HAVE_VECTOR_SELECT	1	/* relocatable vectors */
-#define XCHAL_HAVE_VECBASE		1	/* relocatable vectors */
-#define XCHAL_VECBASE_RESET_VADDR	0x4e100400  /* VECBASE reset value */
-#define XCHAL_VECBASE_RESET_PADDR	0x4e100400
-#define XCHAL_RESET_VECBASE_OVERLAP	0	/* UNUSED */
-
-#define XCHAL_RESET_VECTOR0_VADDR	0x4e100000
-#define XCHAL_RESET_VECTOR0_PADDR	0x4e100000
-#define XCHAL_RESET_VECTOR1_VADDR	0x4e100680
-#define XCHAL_RESET_VECTOR1_PADDR	0x4e100680
-#define XCHAL_RESET_VECTOR_VADDR	XCHAL_RESET_VECTOR1_VADDR
-#define XCHAL_RESET_VECTOR_PADDR	XCHAL_RESET_VECTOR1_PADDR
-#define XCHAL_USER_VECOFS		0x0000023C
-#define XCHAL_USER_VECTOR_VADDR		0x4e10063C
-#define XCHAL_USER_VECTOR_PADDR		0x4e10063C
-#define XCHAL_KERNEL_VECOFS		0x0000021C
-#define XCHAL_KERNEL_VECTOR_VADDR	0x4e10061C
-#define XCHAL_KERNEL_VECTOR_PADDR	0x4e10061C
-#define XCHAL_DOUBLEEXC_VECOFS		0x0000025C
-#define XCHAL_DOUBLEEXC_VECTOR_VADDR	0x4e10065C
-#define XCHAL_DOUBLEEXC_VECTOR_PADDR	0x4e10065C
-#define XCHAL_WINDOW_OF4_VECOFS		0x00000000
-#define XCHAL_WINDOW_UF4_VECOFS		0x00000040
-#define XCHAL_WINDOW_OF8_VECOFS		0x00000080
-#define XCHAL_WINDOW_UF8_VECOFS		0x000000C0
-#define XCHAL_WINDOW_OF12_VECOFS	0x00000100
-#define XCHAL_WINDOW_UF12_VECOFS	0x00000140
-#define XCHAL_WINDOW_VECTORS_VADDR	0x4e100400
-#define XCHAL_WINDOW_VECTORS_PADDR	0x4e100400
-#define XCHAL_INTLEVEL2_VECOFS		0x0000017C
-#define XCHAL_INTLEVEL2_VECTOR_VADDR	0x4e10057C
-#define XCHAL_INTLEVEL2_VECTOR_PADDR	0x4e10057C
-#define XCHAL_INTLEVEL3_VECOFS		0x0000019C
-#define XCHAL_INTLEVEL3_VECTOR_VADDR	0x4e10059C
-#define XCHAL_INTLEVEL3_VECTOR_PADDR	0x4e10059C
-#define XCHAL_INTLEVEL4_VECOFS		0x000001BC
-#define XCHAL_INTLEVEL4_VECTOR_VADDR	0x4e1005BC
-#define XCHAL_INTLEVEL4_VECTOR_PADDR	0x4e1005BC
-#define XCHAL_INTLEVEL5_VECOFS		0x000001DC
-#define XCHAL_INTLEVEL5_VECTOR_VADDR	0x4e1005DC
-#define XCHAL_INTLEVEL5_VECTOR_PADDR	0x4e1005DC
-#define XCHAL_DEBUG_VECOFS		XCHAL_INTLEVEL5_VECOFS
-#define XCHAL_DEBUG_VECTOR_VADDR	XCHAL_INTLEVEL5_VECTOR_VADDR
-#define XCHAL_DEBUG_VECTOR_PADDR	XCHAL_INTLEVEL5_VECTOR_PADDR
-#define XCHAL_NMI_VECOFS		0x000001FC
-#define XCHAL_NMI_VECTOR_VADDR		0x4e1005FC
-#define XCHAL_NMI_VECTOR_PADDR		0x4e1005FC
-#define XCHAL_INTLEVEL6_VECOFS		XCHAL_NMI_VECOFS
-#define XCHAL_INTLEVEL6_VECTOR_VADDR	XCHAL_NMI_VECTOR_VADDR
-#define XCHAL_INTLEVEL6_VECTOR_PADDR	XCHAL_NMI_VECTOR_PADDR
-
-/*----------------------------------------------------------------------
- *			DEBUG MODULE
- *----------------------------------------------------------------------
- */
-
-/*  Misc  */
-#define XCHAL_HAVE_DEBUG_ERI		1	/* ERI to debug module */
-#define XCHAL_HAVE_DEBUG_APB		1	/* APB to debug module */
-#define XCHAL_HAVE_DEBUG_JTAG		1	/* JTAG to debug module */
-
-/*  On-Chip Debug (OCD)  */
-#define XCHAL_HAVE_OCD			1	/* OnChipDebug option */
-#define XCHAL_NUM_IBREAK		2	/* number of IBREAKn regs */
-#define XCHAL_NUM_DBREAK		2	/* number of DBREAKn regs */
-#define XCHAL_HAVE_OCD_DIR_ARRAY	0	/* faster OCD option (to LX4) */
-#define XCHAL_HAVE_OCD_LS32DDR		1	/* L32DDR/S32DDR (faster OCD) */
-
-/*  TRAX (in core)  */
-#define XCHAL_HAVE_TRAX			1	/* TRAX in debug module */
-#define XCHAL_TRAX_MEM_SIZE		4096	/* TRAX memory size in bytes */
-#define XCHAL_TRAX_MEM_SHAREABLE	1	/* start/end regs; ready sig. */
-#define XCHAL_TRAX_ATB_WIDTH		32	/* ATB width (bits), 0=no ATB */
-#define XCHAL_TRAX_TIME_WIDTH		64	/* timestamp bitwidth, 0=none */
-
-/*  Perf counters  */
-#define XCHAL_NUM_PERF_COUNTERS		8	/* performance counters */
-
-/*----------------------------------------------------------------------
- *			MMU
- *----------------------------------------------------------------------
- */
-
-/*  See core-matmap.h header file for more details.  */
-#define XCHAL_HAVE_TLBS			0	/* inverse of HAVE_CACHEATTR */
-#define XCHAL_HAVE_SPANNING_WAY		0	/* one way maps I+D 4GB vaddr */
-#define XCHAL_HAVE_IDENTITY_MAP		1	/* vaddr == paddr always */
-#define XCHAL_HAVE_CACHEATTR		0	/* CACHEATTR register present */
-#define XCHAL_HAVE_MIMIC_CACHEATTR	0	/* region protection */
-#define XCHAL_HAVE_XLT_CACHEATTR	0	/* region prot. w/translation */
-/* full MMU (with page table [autorefill] and protection) usable for an MMU-based OS */
-#define XCHAL_HAVE_PTP_MMU		0
-
-/*  If none of the above last 5 are set, it's a custom TLB configuration.  */
-
-#define XCHAL_MMU_ASID_BITS		0	/* number of bits in ASIDs */
-#define XCHAL_MMU_RINGS			1	/* number of rings (1..4) */
-#define XCHAL_MMU_RING_BITS		0	/* num of bits in RING field */
-
-/*----------------------------------------------------------------------
- *				MPU
- *----------------------------------------------------------------------
- */
-#define XCHAL_HAVE_MPU			1
-#define XCHAL_MPU_ENTRIES		32
-#define XCHAL_MPU_LOCK			1
-
-/* MPU requires alignment of entries to background map */
-#define XCHAL_MPU_ALIGN_REQ		1
-#define XCHAL_MPU_BACKGROUND_ENTRIES	2	/* number of entries in bg map*/
-#define XCHAL_MPU_BG_CACHEADRDIS	0xFF	/* default CACHEADRDIS for bg */
-
-#define XCHAL_MPU_ALIGN_BITS		7
-#define XCHAL_MPU_ALIGN			128
-
-/*-----------------------------------------------------------------------
- *				CSR Parity
- *------------------------------------------------------------------------
- */
-#define XCHAL_HAVE_CSR_PARITY		0
-
-
-/*----------------------------------------------------------------------
- *				FLEX-LOCK
- *------------------------------------------------------------------------
- */
-
-#define XCHAL_HAVE_FXLK			0
-
-/*----------------------------------------------------------------------
- *				WWDT (Windowed Watchdog Timer)
- *------------------------------------------------------------------------
- */
-#define XCHAL_HAVE_WWDT			0
-#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
-
-#endif /* XTENSA_CORE_CONFIGURATION_H_ */
-
diff --git a/src/platform/mt8196/include/arch/xtensa/config/core-matmap.h b/src/platform/mt8196/include/arch/xtensa/config/core-matmap.h
deleted file mode 100644
index a35a16752f8b..000000000000
--- a/src/platform/mt8196/include/arch/xtensa/config/core-matmap.h
+++ /dev/null
@@ -1,101 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * xtensa/config/core-matmap.h -- Memory access and translation mapping
- *	parameters (CHAL) of the Xtensa processor core configuration.
- *
- *  If you are using Xtensa Tools, see <xtensa/config/core.h> (which includes
- *  this file) for more details.
- *
- *  In the Xtensa processor products released to date, all parameters
- *  defined in this file are derivable (at least in theory) from
- *  information contained in the core-isa.h header file.
- *  In particular, the following core configuration parameters are relevant:
- *	XCHAL_HAVE_CACHEATTR
- *	XCHAL_HAVE_MIMIC_CACHEATTR
- *	XCHAL_HAVE_XLT_CACHEATTR
- *	XCHAL_HAVE_PTP_MMU
- *	XCHAL_ITLB_ARF_ENTRIES_LOG2
- *	XCHAL_DTLB_ARF_ENTRIES_LOG2
- *	XCHAL_DCACHE_IS_WRITEBACK
- *	XCHAL_ICACHE_SIZE		(presence of I-cache)
- *	XCHAL_DCACHE_SIZE		(presence of D-cache)
- *	XCHAL_HW_VERSION_MAJOR
- *	XCHAL_HW_VERSION_MINOR
- */
-
-/* Customer ID=7578; Build=0xa69ab; Copyright (c) 1999-2023 Tensilica Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef XTENSA_CONFIG_CORE_MATMAP_H
-#define XTENSA_CONFIG_CORE_MATMAP_H
-
-/*----------------------------------------------------------------------
- * CACHE (MEMORY ACCESS) ATTRIBUTES
- *----------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------
- * MPU
- *----------------------------------------------------------------------
- */
-
-/* Mappings for legacy constants where appropriate */
-
-#define XCHAL_CA_WRITEBACK (XTHAL_MEM_WRITEBACK | XTHAL_AR_RWXrwx)
-
-#define XCHAL_CA_WRITEBACK_NOALLOC (XTHAL_MEM_WRITEBACK_NOALLOC | XTHAL_AR_RWXrwx)
-
-#define XCHAL_CA_WRITETHRU (XTHAL_MEM_WRITETHRU | XTHAL_AR_RWXrwx)
-
-#define XCHAL_CA_ILLEGAL   (XTHAL_AR_NONE   | XTHAL_MEM_DEVICE)
-#define XCHAL_CA_BYPASS    (XTHAL_AR_RWXrwx | XTHAL_MEM_DEVICE)
-#define XCHAL_CA_BYPASSBUF    (XTHAL_AR_RWXrwx | XTHAL_MEM_DEVICE |\
-XTHAL_MEM_BUFFERABLE)
-#define XCHAL_CA_BYPASS_RX (XTHAL_AR_RX     | XTHAL_MEM_DEVICE)
-#define XCHAL_CA_BYPASS_RW (XTHAL_AR_RW     | XTHAL_MEM_DEVICE)
-#define XCHAL_CA_BYPASS_R  (XTHAL_AR_R      | XTHAL_MEM_DEVICE)
-#define XCHAL_HAVE_CA_WRITEBACK_NOALLOC 1
-
-/*
- * Contents of MPU background map.
- * NOTE:  caller must define the XCHAL_MPU_BGMAP() macro (not defined here
- * but specified below) before expanding the XCHAL_MPU_BACKGROUND_MAP(s) macro.
- *
- * XCHAL_MPU_BGMAP(s, vaddr_start, vaddr_last, rights, memtype, x...)
- *
- *	s = passed from XCHAL_MPU_BACKGROUND_MAP(s), eg. to select how to expand
- *	vaddr_start = first byte of region (always 0 for first entry)
- *	vaddr_end = last byte of region (always 0xFFFFFFFF for last entry)
- *	rights = access rights
- *	memtype = memory type
- *	x = reserved for future use (0 until then)
- */
-/* parasoft-begin-suppress MISRA2012-RULE-20_7 "Macro use model requires s to not be in ()" */
-#define XCHAL_MPU_BACKGROUND_MAP(s) (\
-XCHAL_MPU_BGMAP(s, 0x00000000, 0x7fffffff, 7, 6, 0) \
-XCHAL_MPU_BGMAP(s, 0x80000000, 0xffffffff, 7, 6, 0) \)
-/* parasoft-end-suppress MISRA2012-RULE-20_7 "Macro use model requires s to not be in ()" */
-
-/* end */
-
-#endif /*XTENSA_CONFIG_CORE_MATMAP_H*/
-
diff --git a/src/platform/mt8196/include/arch/xtensa/config/defs.h b/src/platform/mt8196/include/arch/xtensa/config/defs.h
deleted file mode 100644
index 18ee59f671b3..000000000000
--- a/src/platform/mt8196/include/arch/xtensa/config/defs.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/* Definitions for Xtensa instructions, types, and protos. */
-
-/* Customer ID = 7578; Build = 0xa69ab; Copyright (c) 2003-2004 Tensilica Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/* NOTE: This file exists only for backward compatibility with T1050
- * and earlier Xtensa releases.  It includes only a subset of the
- * available header files.
- */
-
-#ifndef _XTENSA_BASE_HEADER
-#define _XTENSA_BASE_HEADER
-
-#ifdef __XTENSA__
-
-#include <xtensa/tie/xt_core.h>
-#include <xtensa/tie/xt_misc.h>
-#include <xtensa/tie/xt_booleans.h>
-
-#endif /* __XTENSA__ */
-#endif /* !_XTENSA_BASE_HEADER */
diff --git a/src/platform/mt8196/include/arch/xtensa/config/key.h b/src/platform/mt8196/include/arch/xtensa/config/key.h
deleted file mode 100644
index 61a1fa79ed1c..000000000000
--- a/src/platform/mt8196/include/arch/xtensa/config/key.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Customer ID = 7578; Build = 0xa69ab; Copyright (c) 2020-2021 by Cadence Design Systems. Inc.
- * ALL RIGHTS RESERVED.
- * These coded instructions, statements, and computer programs are the
- * copyrighted works and confidential proprietary information of Tensilica Inc.
- * They may not be modified, copied, reproduced, distributed, or disclosed to
- * third parties in any manner, medium, or form, in whole or in part, without
- * the prior written consent of Cadence Design Systems Inc.
- */
-
-#ifndef TENSILICA_CONFIG_KEY
-#define TENSILICA_CONFIG_KEY 1
-
-#include <xtensa/xtensa-types.h>
-
-#endif
-
diff --git a/src/platform/mt8196/include/arch/xtensa/config/secure.h b/src/platform/mt8196/include/arch/xtensa/config/secure.h
deleted file mode 100644
index 8d46c3eb0257..000000000000
--- a/src/platform/mt8196/include/arch/xtensa/config/secure.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/* Secure Mode defines. */
-
-/* Customer ID = 7578; Build = 0xa69ab; Copyright (c) 2020 Cadence Design Systems, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef XTENSA_SECURE_H
-#define XTENSA_SECURE_H
-
-/* SRAM */
-#define XCHAL_HAVE_SECURE_SRAM	0
-
-/* INSTRAM0 */
-#define XCHAL_HAVE_SECURE_INSTRAM0	0
-
-/* DATARAM1 */
-#define XCHAL_HAVE_SECURE_DATARAM1	0
-
-/* DATARAM0 */
-#define XCHAL_HAVE_SECURE_DATARAM0	0
-
-/* Array of all secure regions' start/size */
-#define XCHAL_SECURE_MEM_LIST \
-{ \
-}
-
-#endif /* XTENSA_SECURE_H */
-
diff --git a/src/platform/mt8196/include/arch/xtensa/config/specreg.h b/src/platform/mt8196/include/arch/xtensa/config/specreg.h
deleted file mode 100644
index e2ef5d4dd469..000000000000
--- a/src/platform/mt8196/include/arch/xtensa/config/specreg.h
+++ /dev/null
@@ -1,112 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Xtensa Special Register symbolic names
- */
-
-/* Id:
- * //depot/rel/Homewood/ib.11/Xtensa/SWConfig/hal/specreg.h.tpp#1
- */
-
-/* Customer ID = 7578; Build = 0xa69ab; Copyright (c) 1998-2002 Tensilica Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef XTENSA_SPECREG_H
-#define XTENSA_SPECREG_H
-
-/*  Include these special register bitfield definitions, for historical reasons:  */
-#include <xtensa/corebits.h>
-
-/*  Special registers:  */
-#define LBEG		0
-#define LEND		1
-#define LCOUNT		2
-#define SAR		3
-#define BR		4
-#define PREFCTL		40
-#define WINDOWBASE	72
-#define WINDOWSTART	73
-#define MPUENB		90
-#define ERACCESS	95
-#define IBREAKENABLE	96
-#define MEMCTL		97
-#define CACHEADRDIS	98
-#define DDR		104
-#define IBREAKA_0	128
-#define IBREAKA_1	129
-#define DBREAKA_0	144
-#define DBREAKA_1	145
-#define DBREAKC_0	160
-#define DBREAKC_1	161
-#define EPC_1		177
-#define EPC_2		178
-#define EPC_3		179
-#define EPC_4		180
-#define EPC_5		181
-#define EPC_6		182
-#define DEPC		192
-#define EPS_2		194
-#define EPS_3		195
-#define EPS_4		196
-#define EPS_5		197
-#define EPS_6		198
-#define EXCSAVE_1	209
-#define EXCSAVE_2	210
-#define EXCSAVE_3	211
-#define EXCSAVE_4	212
-#define EXCSAVE_5	213
-#define EXCSAVE_6	214
-#define CPENABLE	224
-#define INTERRUPT	226
-#define INTCLEAR	227
-#define INTENABLE	228
-#define PS		230
-#define VECBASE		231
-#define EXCCAUSE	232
-#define DEBUGCAUSE	233
-#define CCOUNT		234
-#define PRID		235
-#define ICOUNT		236
-#define ICOUNTLEVEL	237
-#define EXCVADDR	238
-#define CCOMPARE_0	240
-#define CCOMPARE_1	241
-#define CCOMPARE_2	242
-#define MISC_REG_0	244
-#define MISC_REG_1	245
-#define MISC_REG_2	246
-#define MISC_REG_3	247
-
-/*  Special cases (bases of special register series):  */
-#define IBREAKA		128
-#define DBREAKA		144
-#define DBREAKC		160
-#define EPC		176
-#define EPS		192
-#define EXCSAVE		208
-#define CCOMPARE	240
-
-/*  Special names for read-only and write-only interrupt registers:  */
-#define INTREAD		226
-#define INTSET		226
-
-#endif /* XTENSA_SPECREG_H */
-
diff --git a/src/platform/mt8196/include/arch/xtensa/config/system.h b/src/platform/mt8196/include/arch/xtensa/config/system.h
deleted file mode 100644
index 77b6a105f71f..000000000000
--- a/src/platform/mt8196/include/arch/xtensa/config/system.h
+++ /dev/null
@@ -1,293 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * xtensa/config/system.h -- HAL definitions that are dependent on SYSTEM configuration
- *
- *  NOTE: The location and contents of this file are highly subject to change.
- *
- *  Source for configuration-independent binaries (which link in a
- *  configuration-specific HAL library) must NEVER include this file.
- *  The HAL itself has historically included this file in some instances,
- *  but this is not appropriate either, because the HAL is meant to be
- *  core-specific but system independent.
- */
-
-/* Customer ID = 7578; Build = 0xa69ab; Copyright (c) 2000-2010 Tensilica Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef XTENSA_CONFIG_SYSTEM_H
-#define XTENSA_CONFIG_SYSTEM_H
-
-/*----------------------------------------------------------------------
- * CONFIGURED SOFTWARE OPTIONS
- *----------------------------------------------------------------------
- */
-
-/* (sw-only option, whether software uses absolute literals) */
-#define XSHAL_USE_ABSOLUTE_LITERALS	0
-/* Set if there is some memory that allows both code and literals.  */
-#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1
-
-/* (sw-only option, selected ABI) */
-#define XSHAL_ABI			XTHAL_ABI_WINDOWED
-/*  The above maps to one of the following constants:  */
-#define XTHAL_ABI_WINDOWED		0
-#define XTHAL_ABI_CALL0			1
-
-/* (sw-only option, selected C library) */
-#define XSHAL_CLIB			XTHAL_CLIB_XCLIB
-/*  The above maps to one of the following constants:  */
-#define XTHAL_CLIB_NEWLIB		0
-#define XTHAL_CLIB_UCLIBC		1
-#define XTHAL_CLIB_XCLIB		2
-
-#define XSHAL_USE_FLOATING_POINT	1
-
-#define XSHAL_FLOATING_POINT_ABI        1
-
-/*  SW workarounds enabled for HW errata:  */
-
-/*----------------------------------------------------------------------
- * DEVICE ADDRESSES
- *----------------------------------------------------------------------
- */
-
-/*
- *  Strange place to find these, but the configuration GUI
- *  allows moving these around to account for various core
- *  configurations.  Specific boards (and their BSP software)
- *  will have specific meanings for these components.
- */
-
-/*  I/O Block areas:  */
-#define XSHAL_IOBLOCK_CACHED_VADDR	0x70000000
-#define XSHAL_IOBLOCK_CACHED_PADDR	0x70000000
-#define XSHAL_IOBLOCK_CACHED_SIZE	0x0E000000
-
-#define XSHAL_IOBLOCK_BYPASS_VADDR	0x90000000
-#define XSHAL_IOBLOCK_BYPASS_PADDR	0x90000000
-#define XSHAL_IOBLOCK_BYPASS_SIZE	0x0E000000
-
-/*  System ROM:  */
-
-/*  System RAM:  */
-#define XSHAL_RAM_VADDR		0x40000000
-#define XSHAL_RAM_PADDR		0x40000000
-#define XSHAL_RAM_VSIZE		0x80000000
-#define XSHAL_RAM_PSIZE		0x80000000
-#define XSHAL_RAM_SIZE		XSHAL_RAM_PSIZE
-/*  Largest available area (free of vectors):  */
-#define XSHAL_RAM_AVAIL_VADDR	0x50000000
-#define XSHAL_RAM_AVAIL_VSIZE	0x80000000
-
-/*
- *  Shadow system RAM (same device as system RAM, at different address).
- *  (Emulation boards need this for the SONIC Ethernet driver
- *   when data caches are configured for writeback mode.)
- *  NOTE: on full MMU configs, this points to the BYPASS virtual address
- *  of system RAM, ie. is the same as XSHAL_RAM_* except that virtual
- *  addresses are viewed through the BYPASS static map rather than
- *  the CACHED static map.
- */
-#define XSHAL_RAM_BYPASS_VADDR		0x20000000
-#define XSHAL_RAM_BYPASS_PADDR		0x20000000
-#define XSHAL_RAM_BYPASS_PSIZE		0x20000000
-
-/*  Alternate system RAM (different device than system RAM):  */
-
-/*  Some available location in which to place devices in a simulation (eg. XTMP):  */
-#define XSHAL_SIMIO_CACHED_VADDR	0x20000000
-#define XSHAL_SIMIO_BYPASS_VADDR	0x20000000
-#define XSHAL_SIMIO_PADDR		0x20000000
-#define XSHAL_SIMIO_SIZE		0x20000000
-
-/*----------------------------------------------------------------------
- *  For use by reference testbench exit and diagnostic routines.
- *----------------------------------------------------------------------
- */
-#define XSHAL_MAGIC_EXIT		0xdeeeb400
-#define XSHAL_STL_INFO_LOCATION		0xfffffffc
-
-/*----------------------------------------------------------------------
- *			DEVICE-ADDRESS DEPENDENT...
- *
- *  Values written to CACHEATTR special register (or its equivalent)
- *  to enable and disable caches in various modes.
- *----------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------
- * BACKWARD COMPATIBILITY ...
- *----------------------------------------------------------------------
- */
-
-/*
- *  NOTE:  the following two macros are DEPRECATED.  Use the latter
- *  board-specific macros instead, which are specially tuned for the
- *  particular target environments' memory maps.
- */
-/* disable caches in bypass mode */
-#define XSHAL_CACHEATTR_BYPASS		XSHAL_XT2000_CACHEATTR_BYPASS
-/* default setting to enable caches (no writeback!) */
-#define XSHAL_CACHEATTR_DEFAULT		XSHAL_XT2000_CACHEATTR_DEFAULT
-
-/*----------------------------------------------------------------------
- * GENERIC
- *----------------------------------------------------------------------
- */
-
-/*  For the following, a 512MB region is used if it contains a system (PIF) RAM,
- *  system (PIF) ROM, local memory, or XLMI.
- */
-
-/*  These set any unused 512MB region to cache-BYPASS attribute:  */
-/* enable caches in write-back mode */
-#define XSHAL_ALLVALID_CACHEATTR_WRITEBACK	0x24444422
-/* enable caches in write-allocate mode */
-#define XSHAL_ALLVALID_CACHEATTR_WRITEALLOC	0x21111122
-/* enable caches in write-through mode */
-#define XSHAL_ALLVALID_CACHEATTR_WRITETHRU	0x21111122
-/* disable caches in bypass mode */
-#define XSHAL_ALLVALID_CACHEATTR_BYPASS		0x22222222
-/* default setting to enable caches */
-#define XSHAL_ALLVALID_CACHEATTR_DEFAULT	XSHAL_ALLVALID_CACHEATTR_WRITEBACK
-
-/*  These set any unused 512MB region to ILLEGAL attribute:  */
-/* enable caches in write-back mode */
-#define XSHAL_STRICT_CACHEATTR_WRITEBACK	0xF44444FF
-/* enable caches in write-allocate mode */
-#define XSHAL_STRICT_CACHEATTR_WRITEALLOC	0xF11111FF
-/* enable caches in write-through mode */
-#define XSHAL_STRICT_CACHEATTR_WRITETHRU	0xF11111FF
-/* disable caches in bypass mode */
-#define XSHAL_STRICT_CACHEATTR_BYPASS		0xF22222FF
-/* default setting to enable caches */
-#define XSHAL_STRICT_CACHEATTR_DEFAULT		XSHAL_STRICT_CACHEATTR_WRITEBACK
-
-/*  These set the first 512MB, if unused, to ILLEGAL attribute to help catch
- *  NULL-pointer dereference bugs; all other unused 512MB regions are set
- *  to cache-BYPASS attribute:
- */
-/* enable caches in write-back mode */
-#define XSHAL_TRAPNULL_CACHEATTR_WRITEBACK	0x2444442F
-/* enable caches in write-allocate mode */
-#define XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC	0x2111112F
-/* enable caches in write-through mode */
-#define XSHAL_TRAPNULL_CACHEATTR_WRITETHRU	0x2111112F
-/* disable caches in bypass mode */
-#define XSHAL_TRAPNULL_CACHEATTR_BYPASS		0x2222222F
-/* default setting to enable caches */
-#define XSHAL_TRAPNULL_CACHEATTR_DEFAULT	XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
-
-/*----------------------------------------------------------------------
- *ISS (Instruction Set Simulator) SPECIFIC ...
- *----------------------------------------------------------------------
- */
-
-/*  For now, ISS defaults to the TRAPNULL settings:  */
-#define XSHAL_ISS_CACHEATTR_WRITEBACK	XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
-#define XSHAL_ISS_CACHEATTR_WRITEALLOC	XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC
-#define XSHAL_ISS_CACHEATTR_WRITETHRU	XSHAL_TRAPNULL_CACHEATTR_WRITETHRU
-#define XSHAL_ISS_CACHEATTR_BYPASS	XSHAL_TRAPNULL_CACHEATTR_BYPASS
-#define XSHAL_ISS_CACHEATTR_DEFAULT	XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
-
-#define XSHAL_ISS_PIPE_REGIONS	0
-#define XSHAL_ISS_SDRAM_REGIONS	0
-
-/*----------------------------------------------------------------------
- * XT2000 BOARD SPECIFIC ...
- *----------------------------------------------------------------------
- */
-
-/*  For the following, a 512MB region is used if it contains any system RAM,
- *  system ROM, local memory, XLMI, or other XT2000 board device or memory.
- *  Regions containing devices are forced to cache-BYPASS mode regardless
- *  of whether the macro is _WRITEBACK vs. _BYPASS etc.
- */
-
-/*  These set any 512MB region unused on the XT2000 to ILLEGAL attribute:  */
-/* enable caches in write-back mode */
-#define XSHAL_XT2000_CACHEATTR_WRITEBACK	0xF442442F
-/* enable caches in write-allocate mode */
-#define XSHAL_XT2000_CACHEATTR_WRITEALLOC	0xF112112F
-/* enable caches in write-through mode */
-#define XSHAL_XT2000_CACHEATTR_WRITETHRU	0xF112112F
-/* disable caches in bypass mode */
-#define XSHAL_XT2000_CACHEATTR_BYPASS		0xF222222F
-/* default setting to enable caches */
-#define XSHAL_XT2000_CACHEATTR_DEFAULT		XSHAL_XT2000_CACHEATTR_WRITEBACK
-
-#define XSHAL_XT2000_PIPE_REGIONS	0x00000000	/* BusInt pipeline regions */
-#define XSHAL_XT2000_SDRAM_REGIONS	0x00000024	/* BusInt SDRAM regions */
-
-/*----------------------------------------------------------------------
- * VECTOR INFO AND SIZES
- *----------------------------------------------------------------------
- */
-
-#define XSHAL_VECTORS_PACKED		0	/* UNUSED */
-#define XSHAL_STATIC_VECTOR_SELECT	1
-#define XSHAL_RESET_VECTOR_VADDR	0x4e100680
-#define XSHAL_RESET_VECTOR_PADDR	0x4e100680
-
-/*
- *  Sizes allocated to vectors by the system (memory map) configuration.
- *  These sizes are constrained by core configuration (eg. one vector's
- *  code cannot overflow into another vector) but are dependent on the
- *  system or board (or LSP) memory map configuration.
- *
- *  Whether or not each vector happens to be in a system ROM is also
- *  a system configuration matter, sometimes useful, included here also:
- */
-#define XSHAL_RESET_VECTOR_SIZE	0x000002E0
-#define XSHAL_RESET_VECTOR_ISROM	0
-#define XSHAL_USER_VECTOR_SIZE	0x0000001C
-#define XSHAL_USER_VECTOR_ISROM	0
-/* for backward compatibility */
-#define XSHAL_PROGRAMEXC_VECTOR_SIZE	XSHAL_USER_VECTOR_SIZE
-/* for backward compatibility */
-#define XSHAL_USEREXC_VECTOR_SIZE	XSHAL_USER_VECTOR_SIZE
-#define XSHAL_KERNEL_VECTOR_SIZE	0x0000001C
-#define XSHAL_KERNEL_VECTOR_ISROM	0
-/* for backward compatibility */
-#define XSHAL_STACKEDEXC_VECTOR_SIZE	XSHAL_KERNEL_VECTOR_SIZE
-/* for backward compatibility */
-#define XSHAL_KERNELEXC_VECTOR_SIZE	XSHAL_KERNEL_VECTOR_SIZE
-#define XSHAL_DOUBLEEXC_VECTOR_SIZE	0x0000001C
-#define XSHAL_DOUBLEEXC_VECTOR_ISROM	0
-#define XSHAL_WINDOW_VECTORS_SIZE	0x00000178
-#define XSHAL_WINDOW_VECTORS_ISROM	0
-#define XSHAL_INTLEVEL2_VECTOR_SIZE	0x0000001C
-#define XSHAL_INTLEVEL2_VECTOR_ISROM	0
-#define XSHAL_INTLEVEL3_VECTOR_SIZE	0x0000001C
-#define XSHAL_INTLEVEL3_VECTOR_ISROM	0
-#define XSHAL_INTLEVEL4_VECTOR_SIZE	0x0000001C
-#define XSHAL_INTLEVEL4_VECTOR_ISROM	0
-#define XSHAL_INTLEVEL5_VECTOR_SIZE	0x0000001C
-#define XSHAL_INTLEVEL5_VECTOR_ISROM	0
-#define XSHAL_DEBUG_VECTOR_SIZE		XSHAL_INTLEVEL5_VECTOR_SIZE
-#define XSHAL_DEBUG_VECTOR_ISROM	XSHAL_INTLEVEL5_VECTOR_ISROM
-#define XSHAL_NMI_VECTOR_SIZE	0x0000001C
-#define XSHAL_NMI_VECTOR_ISROM	0
-#define XSHAL_INTLEVEL6_VECTOR_SIZE	XSHAL_NMI_VECTOR_SIZE
-
-#endif /*XTENSA_CONFIG_SYSTEM_H*/
-
diff --git a/src/platform/mt8196/include/arch/xtensa/config/tie-asm.h b/src/platform/mt8196/include/arch/xtensa/config/tie-asm.h
deleted file mode 100644
index ebef0818d327..000000000000
--- a/src/platform/mt8196/include/arch/xtensa/config/tie-asm.h
+++ /dev/null
@@ -1,362 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * tie-asm.h -- compile-time HAL assembler definitions dependent on CORE & TIE
- *
- *  NOTE:  This header file is not meant to be included directly.
- */
-
-/* This header file contains assembly-language definitions (assembly
- * macros, etc.) for this specific Xtensa processor's TIE extensions
- * and options.  It is customized to this Xtensa processor configuration.
- *
- * Customer ID = 7578; Build = 0xa69ab; Copyright (c) 1999-2023 Cadence Design Systems Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef _XTENSA_CORE_TIE_ASM_H
-#define _XTENSA_CORE_TIE_ASM_H
-
-#include <xtensa/coreasm.h>
-
-/*  Selection parameter values for save-area save/restore macros:  */
-/*  Option vs. TIE:  */
-#define XTHAL_SAS_TIE	0x0001	/* custom extension or coprocessor */
-#define XTHAL_SAS_OPT	0x0002	/* optional (and not a coprocessor) */
-#define XTHAL_SAS_ANYOT	0x0003	/* both of the above */
-/*  Whether used automatically by compiler:  */
-#define XTHAL_SAS_NOCC	0x0004	/* not used by compiler w/o special opts/code */
-#define XTHAL_SAS_CC	0x0008	/* used by compiler without special opts/code */
-#define XTHAL_SAS_ANYCC	0x000C	/* both of the above */
-/*  ABI handling across function calls:  */
-#define XTHAL_SAS_CALR	0x0010	/* caller-saved */
-#define XTHAL_SAS_CALE	0x0020	/* callee-saved */
-#define XTHAL_SAS_GLOB	0x0040	/* global across function calls (in thread) */
-#define XTHAL_SAS_ANYABI	0x0070	/* all of the above three */
-/*  Misc  */
-#define XTHAL_SAS_ALL	0xFFFF	/* include all default NCP contents */
-#define XTHAL_SAS3(optie, ccuse, abi)	(((optie) & XTHAL_SAS_ANYOT)  \
-| ((ccuse) & XTHAL_SAS_ANYCC)  \
-| ((abi)   & XTHAL_SAS_ANYABI))
-
-/*
- *  Macro to store all non-coprocessor (extra) custom TIE and optional state
- *  (not including zero-overhead loop registers).
- *  Required parameters:
- *      ptr         Save area pointer address register (clobbered)
- *                  (register must contain a 4 byte aligned address).
- *      at1..at4    Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
- *                  registers are clobbered, the remaining are unused).
- *  Optional parameters:
- *      continue    If macro invoked as part of a larger store sequence, set to 1
- *                  if this is not the first in the sequence.  Defaults to 0.
- *      ofs         Offset from start of larger sequence (from value of first ptr
- *                  in sequence) at which to store.  Defaults to next available space
- *                  (or 0 if <continue> is 0).
- *      select      Select what category(ies) of registers to store, as a bitmask
- *                  (see XTHAL_SAS_xxx constants).  Defaults to all registers.
- *      alloc       Select what category(ies) of registers to allocate; if any
- *                  category is selected here that is not in <select>, space for
- *                  the corresponding registers is skipped without doing any store.
- */
-.macro xchal_ncp_store  ptr at1 at2 at3 at4  continue = 0 ofs = -1 select = XTHAL_SAS_ALL alloc = 0
-xchal_sa_start	\continue, \ofs
-// Optional global registers used by default by the compiler:
-.ifeq(XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
-xchal_sa_align	\ptr, 0, 1016, 4, 4
-rur.threadptr	\at1		// threadptr option
-s32i	\at1, \ptr, .Lxchal_ofs_ + 0
-.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
-.elseif((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
-xchal_sa_align	\ptr, 0, 1016, 4, 4
-.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
-.endif
-// Optional caller-saved registers not used by default by the compiler:
-.ifeq(XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
-xchal_sa_align	\ptr, 0, 1016, 4, 4
-rsr.br	\at1		// boolean option
-s32i	\at1, \ptr, .Lxchal_ofs_ + 0
-.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
-.elseif((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
-xchal_sa_align	\ptr, 0, 1016, 4, 4
-.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
-.endif
-.endm	// xchal_ncp_store
-
-/*
- *  Macro to load all non-coprocessor (extra) custom TIE and optional state
- *  (not including zero-overhead loop registers).
- *  Required parameters:
- *      ptr         Save area pointer address register (clobbered)
- *                  (register must contain a 4 byte aligned address).
- *      at1..at4    Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
- *                  registers are clobbered, the remaining are unused).
- *  Optional parameters:
- *      continue    If macro invoked as part of a larger load sequence, set to 1
- *                  if this is not the first in the sequence.  Defaults to 0.
- *      ofs         Offset from start of larger sequence (from value of first ptr
- *                  in sequence) at which to load.  Defaults to next available space
- *                  (or 0 if <continue> is 0).
- *      select      Select what category(ies) of registers to load, as a bitmask
- *                  (see XTHAL_SAS_xxx constants).  Defaults to all registers.
- *      alloc       Select what category(ies) of registers to allocate; if any
- *                  category is selected here that is not in <select>, space for
- *                  the corresponding registers is skipped without doing any load.
- */
-.macro xchal_ncp_load  ptr at1 at2 at3 at4  continue = 0 ofs = -1 select = XTHAL_SAS_ALL alloc = 0
-xchal_sa_start	\continue, \ofs
-// Optional global registers used by default by the compiler:
-.ifeq(XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
-xchal_sa_align	\ptr, 0, 1016, 4, 4
-l32i	\at1, \ptr, .Lxchal_ofs_ + 0
-wur.threadptr	\at1		// threadptr option
-.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
-.elseif((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
-xchal_sa_align	\ptr, 0, 1016, 4, 4
-.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
-.endif
-// Optional caller-saved registers not used by default by the compiler:
-.ifeq(XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
-xchal_sa_align	\ptr, 0, 1016, 4, 4
-l32i	\at1, \ptr, .Lxchal_ofs_ + 0
-wsr.br	\at1		// boolean option
-.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
-.elseif((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
-xchal_sa_align	\ptr, 0, 1016, 4, 4
-.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
-.endif
-.endm	// xchal_ncp_load
-
-#define XCHAL_NCP_NUM_ATMPS	1
-
-/*
- *  Macro to store the state of TIE coprocessor AudioEngineLX.
- *  Required parameters:
- *      ptr         Save area pointer address register (clobbered)
- *                  (register must contain a 16 byte aligned address).
- *      at1..at4    Four temporary address registers (first XCHAL_CP1_NUM_ATMPS
- *                  registers are clobbered, the remaining are unused).
- *  Optional parameters are the same as for xchal_ncp_store.
- */
-#define xchal_cp_AudioEngineLX_store	xchal_cp1_store
-.macro	xchal_cp1_store  ptr at1 at2 at3 at4  continue = 0 ofs = -1 select = XTHAL_SAS_ALL alloc = 0
-xchal_sa_start \continue, \ofs
-// Custom caller-saved registers not used by default by the compiler:
-.ifeq(XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
-xchal_sa_align	\ptr, 0, 0, 16, 16
-ae_s64.i	aed0, \ptr, .Lxchal_ofs_ + 56
-addi.a	\ptr, \ptr, 64
-ae_s64.i	aed1, \ptr, .Lxchal_ofs_ + 0
-ae_s64.i	aed2, \ptr, .Lxchal_ofs_ + 8
-ae_s64.i	aed3, \ptr, .Lxchal_ofs_ + 16
-ae_s64.i	aed4, \ptr, .Lxchal_ofs_ + 24
-ae_s64.i	aed5, \ptr, .Lxchal_ofs_ + 32
-ae_s64.i	aed6, \ptr, .Lxchal_ofs_ + 40
-ae_s64.i	aed7, \ptr, .Lxchal_ofs_ + 48
-ae_s64.i	aed8, \ptr, .Lxchal_ofs_ + 56
-addi.a	\ptr, \ptr, 64
-ae_s64.i	aed9, \ptr, .Lxchal_ofs_ + 0
-ae_s64.i	aed10, \ptr, .Lxchal_ofs_ + 8
-ae_s64.i	aed11, \ptr, .Lxchal_ofs_ + 16
-ae_s64.i	aed12, \ptr, .Lxchal_ofs_ + 24
-ae_s64.i	aed13, \ptr, .Lxchal_ofs_ + 32
-ae_s64.i	aed14, \ptr, .Lxchal_ofs_ + 40
-ae_s64.i	aed15, \ptr, .Lxchal_ofs_ + 48
-ae_s64.i	aed16, \ptr, .Lxchal_ofs_ + 56
-addi.a	\ptr, \ptr, 64
-ae_s64.i	aed17, \ptr, .Lxchal_ofs_ + 0
-ae_s64.i	aed18, \ptr, .Lxchal_ofs_ + 8
-ae_s64.i	aed19, \ptr, .Lxchal_ofs_ + 16
-ae_s64.i	aed20, \ptr, .Lxchal_ofs_ + 24
-ae_s64.i	aed21, \ptr, .Lxchal_ofs_ + 32
-ae_s64.i	aed22, \ptr, .Lxchal_ofs_ + 40
-ae_s64.i	aed23, \ptr, .Lxchal_ofs_ + 48
-ae_s64.i	aed24, \ptr, .Lxchal_ofs_ + 56
-addi.a	\ptr, \ptr, 64
-ae_s64.i	aed25, \ptr, .Lxchal_ofs_ + 0
-ae_s64.i	aed26, \ptr, .Lxchal_ofs_ + 8
-ae_s64.i	aed27, \ptr, .Lxchal_ofs_ + 16
-ae_s64.i	aed28, \ptr, .Lxchal_ofs_ + 24
-ae_s64.i	aed29, \ptr, .Lxchal_ofs_ + 32
-ae_s64.i	aed30, \ptr, .Lxchal_ofs_ + 40
-ae_s64.i	aed31, \ptr, .Lxchal_ofs_ + 48
-ae_movae	\at1, aep0
-s8i	\at1, \ptr, .Lxchal_ofs_ + 56
-ae_movae	\at1, aep1
-s8i	\at1, \ptr, .Lxchal_ofs_ + 57
-ae_movae	\at1, aep2
-s8i	\at1, \ptr, .Lxchal_ofs_ + 58
-ae_movae	\at1, aep3
-s8i	\at1, \ptr, .Lxchal_ofs_ + 59
-addi.a	\ptr, \ptr, 64
-ae_salign128.i	u0, \ptr, .Lxchal_ofs_ + 0
-ae_salign128.i	u1, \ptr, .Lxchal_ofs_ + 16
-ae_salign128.i	u2, \ptr, .Lxchal_ofs_ + 32
-ae_salign128.i	u3, \ptr, .Lxchal_ofs_ + 48
-addi.a	\ptr, \ptr, -320
-ae_movdrzbvc	aed0		// ureg AE_ZBIASV8C
-ae_s64.i	aed0, \ptr, .Lxchal_ofs_ + 0 + 0
-ae_movvfcrfsr	aed0		// ureg FCR_FSR
-ae_s64.i	aed0, \ptr, .Lxchal_ofs_ + 8 + 0
-rur.ae_ovf_sar	\at1		// ureg 240
-s32i	\at1, \ptr, .Lxchal_ofs_ + 16
-rur.ae_bithead	\at1		// ureg 241
-s32i	\at1, \ptr, .Lxchal_ofs_ + 20
-rur.ae_ts_fts_bu_bp	\at1		// ureg 242
-s32i	\at1, \ptr, .Lxchal_ofs_ + 24
-rur.ae_cw_sd_no	\at1		// ureg 243
-s32i	\at1, \ptr, .Lxchal_ofs_ + 28
-rur.ae_cbegin0	\at1		// ureg 246
-s32i	\at1, \ptr, .Lxchal_ofs_ + 32
-rur.ae_cend0	\at1		// ureg 247
-s32i	\at1, \ptr, .Lxchal_ofs_ + 36
-rur.ae_cbegin1	\at1		// ureg 248
-s32i	\at1, \ptr, .Lxchal_ofs_ + 40
-rur.ae_cend1	\at1		// ureg 249
-s32i	\at1, \ptr, .Lxchal_ofs_ + 44
-rur.ae_cbegin2	\at1		// ureg 250
-s32i	\at1, \ptr, .Lxchal_ofs_ + 48
-rur.ae_cend2	\at1		// ureg 251
-s32i	\at1, \ptr, .Lxchal_ofs_ + 52
-.set	.Lxchal_ofs_, .Lxchal_ofs_ + 384
-.elseif((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
-xchal_sa_align	\ptr, 0, 0, 16, 16
-.set	.Lxchal_ofs_, .Lxchal_ofs_ + 384
-.endif
-.endm	// xchal_cp1_store
-
-/*
- *  Macro to load the state of TIE coprocessor AudioEngineLX.
- *  Required parameters:
- *      ptr         Save area pointer address register (clobbered)
- *                  (register must contain a 16 byte aligned address).
- *      at1..at4    Four temporary address registers (first XCHAL_CP1_NUM_ATMPS
- *                  registers are clobbered, the remaining are unused).
- *  Optional parameters are the same as for xchal_ncp_load.
- */
-#define xchal_cp_AudioEngineLX_load	xchal_cp1_load
-.macro	xchal_cp1_load  ptr at1 at2 at3 at4  continue = 0 ofs = -1 select = XTHAL_SAS_ALL alloc = 0
-xchal_sa_start \continue, \ofs
-// Custom caller-saved registers not used by default by the compiler:
-.ifeq(XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
-xchal_sa_align	\ptr, 0, 0, 16, 16
-ae_l64.i	aed0, \ptr, .Lxchal_ofs_ + 0 + 0		// ureg AE_ZBIASV8C
-ae_movzbvcdr	aed0
-ae_l64.i	aed0, \ptr, .Lxchal_ofs_ + 8 + 0		// ureg FCR_FSR
-ae_movfcrfsrv	aed0
-l32i	\at1, \ptr, .Lxchal_ofs_ + 16
-wur.ae_ovf_sar	\at1		// ureg 240
-l32i	\at1, \ptr, .Lxchal_ofs_ + 20
-wur.ae_bithead	\at1		// ureg 241
-l32i	\at1, \ptr, .Lxchal_ofs_ + 24
-wur.ae_ts_fts_bu_bp	\at1		// ureg 242
-l32i	\at1, \ptr, .Lxchal_ofs_ + 28
-wur.ae_cw_sd_no	\at1		// ureg 243
-l32i	\at1, \ptr, .Lxchal_ofs_ + 32
-wur.ae_cbegin0	\at1		// ureg 246
-l32i	\at1, \ptr, .Lxchal_ofs_ + 36
-wur.ae_cend0	\at1		// ureg 247
-l32i	\at1, \ptr, .Lxchal_ofs_ + 40
-wur.ae_cbegin1	\at1		// ureg 248
-l32i	\at1, \ptr, .Lxchal_ofs_ + 44
-wur.ae_cend1	\at1		// ureg 249
-l32i	\at1, \ptr, .Lxchal_ofs_ + 48
-wur.ae_cbegin2	\at1		// ureg 250
-l32i	\at1, \ptr, .Lxchal_ofs_ + 52
-wur.ae_cend2	\at1		// ureg 251
-ae_l64.i	aed0, \ptr, .Lxchal_ofs_ + 56
-addi.a	\ptr, \ptr, 64
-ae_l64.i	aed1, \ptr, .Lxchal_ofs_ + 0
-ae_l64.i	aed2, \ptr, .Lxchal_ofs_ + 8
-ae_l64.i	aed3, \ptr, .Lxchal_ofs_ + 16
-ae_l64.i	aed4, \ptr, .Lxchal_ofs_ + 24
-ae_l64.i	aed5, \ptr, .Lxchal_ofs_ + 32
-ae_l64.i	aed6, \ptr, .Lxchal_ofs_ + 40
-ae_l64.i	aed7, \ptr, .Lxchal_ofs_ + 48
-ae_l64.i	aed8, \ptr, .Lxchal_ofs_ + 56
-addi.a	\ptr, \ptr, 64
-ae_l64.i	aed9, \ptr, .Lxchal_ofs_ + 0
-ae_l64.i	aed10, \ptr, .Lxchal_ofs_ + 8
-ae_l64.i	aed11, \ptr, .Lxchal_ofs_ + 16
-ae_l64.i	aed12, \ptr, .Lxchal_ofs_ + 24
-ae_l64.i	aed13, \ptr, .Lxchal_ofs_ + 32
-ae_l64.i	aed14, \ptr, .Lxchal_ofs_ + 40
-ae_l64.i	aed15, \ptr, .Lxchal_ofs_ + 48
-ae_l64.i	aed16, \ptr, .Lxchal_ofs_ + 56
-addi.a	\ptr, \ptr, 64
-ae_l64.i	aed17, \ptr, .Lxchal_ofs_ + 0
-ae_l64.i	aed18, \ptr, .Lxchal_ofs_ + 8
-ae_l64.i	aed19, \ptr, .Lxchal_ofs_ + 16
-ae_l64.i	aed20, \ptr, .Lxchal_ofs_ + 24
-ae_l64.i	aed21, \ptr, .Lxchal_ofs_ + 32
-ae_l64.i	aed22, \ptr, .Lxchal_ofs_ + 40
-ae_l64.i	aed23, \ptr, .Lxchal_ofs_ + 48
-ae_l64.i	aed24, \ptr, .Lxchal_ofs_ + 56
-addi.a	\ptr, \ptr, 64
-ae_l64.i	aed25, \ptr, .Lxchal_ofs_ + 0
-ae_l64.i	aed26, \ptr, .Lxchal_ofs_ + 8
-ae_l64.i	aed27, \ptr, .Lxchal_ofs_ + 16
-ae_l64.i	aed28, \ptr, .Lxchal_ofs_ + 24
-ae_l64.i	aed29, \ptr, .Lxchal_ofs_ + 32
-ae_l64.i	aed30, \ptr, .Lxchal_ofs_ + 40
-ae_l64.i	aed31, \ptr, .Lxchal_ofs_ + 48
-addi.a	\ptr, \ptr, 56
-l8ui	\at1, \ptr, .Lxchal_ofs_ + 0
-ae_movea	aep0, \at1
-l8ui	\at1, \ptr, .Lxchal_ofs_ + 1
-ae_movea	aep1, \at1
-l8ui	\at1, \ptr, .Lxchal_ofs_ + 2
-ae_movea	aep2, \at1
-l8ui	\at1, \ptr, .Lxchal_ofs_ + 3
-ae_movea	aep3, \at1
-addi.a	\ptr, \ptr, 8
-ae_lalign128.i	u0, \ptr, .Lxchal_ofs_ + 0
-ae_lalign128.i	u1, \ptr, .Lxchal_ofs_ + 16
-ae_lalign128.i	u2, \ptr, .Lxchal_ofs_ + 32
-ae_lalign128.i	u3, \ptr, .Lxchal_ofs_ + 48
-.set	.Lxchal_pofs_, .Lxchal_pofs_ + 320
-.set	.Lxchal_ofs_, .Lxchal_ofs_ + 64
-.elseif((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
-xchal_sa_align	\ptr, 0, 0, 16, 16
-.set	.Lxchal_ofs_, .Lxchal_ofs_ + 384
-.endif
-.endm	// xchal_cp1_load
-
-#define XCHAL_CP1_NUM_ATMPS	1
-#define XCHAL_SA_NUM_ATMPS	1
-
-/*  Empty macros for unconfigured coprocessors:  */
-.macro xchal_cp0_store	p a b c d continue = 0 ofs = -1 select = -1 ; .endm
-.macro xchal_cp0_load	p a b c d continue = 0 ofs = -1 select = -1 ; .endm
-.macro xchal_cp2_store	p a b c d continue = 0 ofs = -1 select = -1 ; .endm
-.macro xchal_cp2_load	p a b c d continue = 0 ofs = -1 select = -1 ; .endm
-.macro xchal_cp3_store	p a b c d continue = 0 ofs = -1 select = -1 ; .endm
-.macro xchal_cp3_load	p a b c d continue = 0 ofs = -1 select = -1 ; .endm
-.macro xchal_cp4_store	p a b c d continue = 0 ofs = -1 select = -1 ; .endm
-.macro xchal_cp4_load	p a b c d continue = 0 ofs = -1 select = -1 ; .endm
-.macro xchal_cp5_store	p a b c d continue = 0 ofs = -1 select = -1 ; .endm
-.macro xchal_cp5_load	p a b c d continue = 0 ofs = -1 select = -1 ; .endm
-.macro xchal_cp6_store	p a b c d continue = 0 ofs = -1 select = -1 ; .endm
-.macro xchal_cp6_load	p a b c d continue = 0 ofs = -1 select = -1 ; .endm
-.macro xchal_cp7_store	p a b c d continue = 0 ofs = -1 select = -1 ; .endm
-.macro xchal_cp7_load	p a b c d continue = 0 ofs = -1 select = -1 ; .endm
-
-#endif /*_XTENSA_CORE_TIE_ASM_H*/
-
diff --git a/src/platform/mt8196/include/arch/xtensa/config/tie.h b/src/platform/mt8196/include/arch/xtensa/config/tie.h
deleted file mode 100644
index 517d79faab47..000000000000
--- a/src/platform/mt8196/include/arch/xtensa/config/tie.h
+++ /dev/null
@@ -1,220 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
- *
- *  NOTE:  This header file is not meant to be included directly.
- */
-
-/* This header file describes this specific Xtensa processor's TIE extensions
- * that extend basic Xtensa core functionality.  It is customized to this
- * Xtensa processor configuration.
- *
- * Customer ID = 7578; Build = 0xa69ab; Copyright (c) 1999-2023 Cadence Design Systems Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef XTENSA_CORE_TIE_H
-#define XTENSA_CORE_TIE_H
-
-/* parasoft-begin-suppress ALL "This file not MISRA checked." */
-
-#define XCHAL_CP_NUM			UINT32_C(1)	/* number of coprocessors */
-#define XCHAL_CP_MAX			UINT32_C(2)	/* max CP ID + 1 (0 if none) */
-#define XCHAL_CP_MASK			UINT32_C(0x02)	/* bitmask of all CPs by ID */
-#define XCHAL_CP_PORT_MASK		UINT32_C(0x00)	/* bitmask of only port CPs */
-
-/*  Basic parameters of each coprocessor:  */
-#define XCHAL_CP1_NAME			"audio_engine_lx"
-#define XCHAL_CP1_IDENT			audio_engine_lx
-#define XCHAL_CP1_SA_SIZE		UINT32_C(384)	/* size of state save area */
-#define XCHAL_CP1_SA_ALIGN		UINT32_C(16)	/* min alignment of save area */
-#define XCHAL_CP_ID_AUDIOENGINELX         1  /* coprocessor ID (0..7) */
-
-/*  Filler info for unassigned coprocessors, to simplify arrays etc:  */
-#define XCHAL_CP0_SA_SIZE		UINT32_C(0)
-#define XCHAL_CP0_SA_ALIGN		UINT32_C(1)
-#define XCHAL_CP2_SA_SIZE		UINT32_C(0)
-#define XCHAL_CP2_SA_ALIGN		UINT32_C(1)
-#define XCHAL_CP3_SA_SIZE		UINT32_C(0)
-#define XCHAL_CP3_SA_ALIGN		UINT32_C(1)
-#define XCHAL_CP4_SA_SIZE		UINT32_C(0)
-#define XCHAL_CP4_SA_ALIGN		UINT32_C(1)
-#define XCHAL_CP5_SA_SIZE		UINT32_C(0)
-#define XCHAL_CP5_SA_ALIGN		UINT32_C(1)
-#define XCHAL_CP6_SA_SIZE		UINT32_C(0)
-#define XCHAL_CP6_SA_ALIGN		UINT32_C(1)
-#define XCHAL_CP7_SA_SIZE		UINT32_C(0)
-#define XCHAL_CP7_SA_ALIGN		UINT32_C(1)
-
-/*  Save area for non-coprocessor optional and custom (TIE) state:  */
-#define XCHAL_NCP_SA_SIZE		UINT32_C(8)
-#define XCHAL_NCP_SA_ALIGN		UINT32_C(4)
-
-/*  Total save area for optional and custom state (NCP + CPn):  */
-#define XCHAL_TOTAL_SA_SIZE		UINT32_C(400)	/* with 16-byte align padding */
-#define XCHAL_TOTAL_SA_ALIGN		UINT32_C(16)	/* actual minimum alignment */
-
-/*
- * Detailed contents of save areas.
- * NOTE:  caller must define the XCHAL_SA_REG macro (not defined here)
- * before expanding the XCHAL_xxx_SA_LIST() macros.
- *
- * XCHAL_SA_REG(s, ccused, abikind, kind, opt, name, galign, align, asize,
- *		dbnum, base, regnum, bitsz, gapsz, reset, x...)
- *
- *	s = passed from XCHAL_*_LIST(s), eg. to select how to expand
- *	ccused = set if used by compiler without special options or code
- *	abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
- *	kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
- *	opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg)
- *	name = lowercase reg name (no quotes)
- *	galign = group byte alignment (power of 2) (galign >= align)
- *	align = register byte alignment (power of 2)
- *	asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz)
- *	  (not including any pad bytes required to galign this or next reg)
- *	dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>)
- *	base = reg shortname w/o index (or sr = special, ur = TIE user reg)
- *	regnum = reg index in regfile, or special/TIE-user reg number
- *	bitsz = number of significant bits (regfile width, or ur/sr mask bits)
- *	gapsz = intervening bits, if bitsz bits not stored contiguously
- *	(padsz = pad bits at end [TIE regfile] or at msbits [ur, sr] of asize)
- *	reset = register reset value (or 0 if undefined at reset)
- *	x = reserved for future use (0 until then)
- *
- *  To filter out certain registers, e.g. to expand only the non-global
- *  registers used by the compiler, you can do something like this:
- *
- *  #define XCHAL_SA_REG(s, ccused, p...)	SELCC##ccused(p)
- *  #define SELCC0(p...)
- *  #define SELCC1(abikind, p...)	SELAK##abikind(p)
- *  #define SELAK0(p...)		REG(p)
- *  #define SELAK1(p...)		REG(p)
- *  #define SELAK2(p...)
- *  #define REG(kind, tie, name, galn, aln, asz, csz, dbnum, base, rnum, bsz, rst, x...) \
- *		...what you want to expand...
- */
-
-#define XCHAL_NCP_SA_NUM	2
-#define XCHAL_NCP_SA_LIST(s)	(\
-XCHAL_SA_REG(s, 1, 2, 1, 1, threadptr, 4, 4, 4, 0x03E7, ur, 231, 32, 0, 0, 0) \
-XCHAL_SA_REG(s, 0, 0, 0, 1, br, 4, 4, 4, 0x0204, sr, 4, 16, 0, 0, 0))
-
-#define XCHAL_CP0_SA_NUM	0
-#define XCHAL_CP0_SA_LIST(s)	/* empty */
-
-#define XCHAL_CP1_SA_NUM	52
-#define XCHAL_CP1_SA_LIST(s)	(\
-XCHAL_SA_REG(s, 0, 0, 1, 0, ae_zbiasv8c, 16, 8, 8, 0x1029, ur, -1, 16, 0, 0, 0) \
-XCHAL_SA_REG(s, 0, 0, 1, 0, fcr_fsr, 8, 8, 8, 0x102A, ur, -1, 7, 0, 0, 0) \
-XCHAL_SA_REG(s, 0, 0, 1, 0, ae_ovf_sar, 4, 4, 4, 0x03F0, ur, 240, 15, 0, 0, 0) \
-XCHAL_SA_REG(s, 0, 0, 1, 0, ae_bithead, 4, 4, 4, 0x03F1, ur, 241, 32, 0, 0, 0) \
-XCHAL_SA_REG(s, 0, 0, 1, 0, ae_ts_fts_bu_bp, 4, 4, 4, 0x03F2, ur, 242, 16, 0, 0, 0) \
-XCHAL_SA_REG(s, 0, 0, 1, 0, ae_cw_sd_no, 4, 4, 4, 0x03F3, ur, 243, 29, 0, 0, 0) \
-XCHAL_SA_REG(s, 0, 0, 1, 0, ae_cbegin0, 4, 4, 4, 0x03F6, ur, 246, 32, 0, 0, 0) \
-XCHAL_SA_REG(s, 0, 0, 1, 0, ae_cend0, 4, 4, 4, 0x03F7, ur, 247, 32, 0, 0, 0) \
-XCHAL_SA_REG(s, 0, 0, 1, 0, ae_cbegin1, 4, 4, 4, 0x03F8, ur, 248, 32, 0, 0, 0) \
-XCHAL_SA_REG(s, 0, 0, 1, 0, ae_cend1, 4, 4, 4, 0x03F9, ur, 249, 32, 0, 0, 0) \
-XCHAL_SA_REG(s, 0, 0, 1, 0, ae_cbegin2, 4, 4, 4, 0x03FA, ur, 250, 32, 0, 0, 0) \
-XCHAL_SA_REG(s, 0, 0, 1, 0, ae_cend2, 4, 4, 4, 0x03FB, ur, 251, 32, 0, 0, 0) \
-XCHAL_SA_REG(s, 0, 0, 2, 0, aed0, 8, 8, 8, 0x1000, aed, 0, 64, 0, 0, 0) \
-XCHAL_SA_REG(s, 0, 0, 2, 0, aed1, 8, 8, 8, 0x1001, aed, 1, 64, 0, 0, 0) \
-XCHAL_SA_REG(s, 0, 0, 2, 0, aed2, 8, 8, 8, 0x1002, aed, 2, 64, 0, 0, 0) \
-XCHAL_SA_REG(s, 0, 0, 2, 0, aed3, 8, 8, 8, 0x1003, aed, 3, 64, 0, 0, 0) \
-XCHAL_SA_REG(s, 0, 0, 2, 0, aed4, 8, 8, 8, 0x1004, aed, 4, 64, 0, 0, 0) \
-XCHAL_SA_REG(s, 0, 0, 2, 0, aed5, 8, 8, 8, 0x1005, aed, 5, 64, 0, 0, 0) \
-XCHAL_SA_REG(s, 0, 0, 2, 0, aed6, 8, 8, 8, 0x1006, aed, 6, 64, 0, 0, 0) \
-XCHAL_SA_REG(s, 0, 0, 2, 0, aed7, 8, 8, 8, 0x1007, aed, 7, 64, 0, 0, 0) \
-XCHAL_SA_REG(s, 0, 0, 2, 0, aed8, 8, 8, 8, 0x1008, aed, 8, 64, 0, 0, 0) \
-XCHAL_SA_REG(s, 0, 0, 2, 0, aed9, 8, 8, 8, 0x1009, aed, 9, 64, 0, 0, 0) \
-XCHAL_SA_REG(s, 0, 0, 2, 0, aed10, 8, 8, 8, 0x100A, aed, 10, 64, 0, 0, 0) \
-XCHAL_SA_REG(s, 0, 0, 2, 0, aed11, 8, 8, 8, 0x100B, aed, 11, 64, 0, 0, 0) \
-XCHAL_SA_REG(s, 0, 0, 2, 0, aed12, 8, 8, 8, 0x100C, aed, 12, 64, 0, 0, 0) \
-XCHAL_SA_REG(s, 0, 0, 2, 0, aed13, 8, 8, 8, 0x100D, aed, 13, 64, 0, 0, 0) \
-XCHAL_SA_REG(s, 0, 0, 2, 0, aed14, 8, 8, 8, 0x100E, aed, 14, 64, 0, 0, 0) \
-XCHAL_SA_REG(s, 0, 0, 2, 0, aed15, 8, 8, 8, 0x100F, aed, 15, 64, 0, 0, 0) \
-XCHAL_SA_REG(s, 0, 0, 2, 0, aed16, 8, 8, 8, 0x1010, aed, 16, 64, 0, 0, 0) \
-XCHAL_SA_REG(s, 0, 0, 2, 0, aed17, 8, 8, 8, 0x1011, aed, 17, 64, 0, 0, 0) \
-XCHAL_SA_REG(s, 0, 0, 2, 0, aed18, 8, 8, 8, 0x1012, aed, 18, 64, 0, 0, 0) \
-XCHAL_SA_REG(s, 0, 0, 2, 0, aed19, 8, 8, 8, 0x1013, aed, 19, 64, 0, 0, 0) \
-XCHAL_SA_REG(s, 0, 0, 2, 0, aed20, 8, 8, 8, 0x1014, aed, 20, 64, 0, 0, 0) \
-XCHAL_SA_REG(s, 0, 0, 2, 0, aed21, 8, 8, 8, 0x1015, aed, 21, 64, 0, 0, 0) \
-XCHAL_SA_REG(s, 0, 0, 2, 0, aed22, 8, 8, 8, 0x1016, aed, 22, 64, 0, 0, 0) \
-XCHAL_SA_REG(s, 0, 0, 2, 0, aed23, 8, 8, 8, 0x1017, aed, 23, 64, 0, 0, 0) \
-XCHAL_SA_REG(s, 0, 0, 2, 0, aed24, 8, 8, 8, 0x1018, aed, 24, 64, 0, 0, 0) \
-XCHAL_SA_REG(s, 0, 0, 2, 0, aed25, 8, 8, 8, 0x1019, aed, 25, 64, 0, 0, 0) \
-XCHAL_SA_REG(s, 0, 0, 2, 0, aed26, 8, 8, 8, 0x101A, aed, 26, 64, 0, 0, 0) \
-XCHAL_SA_REG(s, 0, 0, 2, 0, aed27, 8, 8, 8, 0x101B, aed, 27, 64, 0, 0, 0) \
-XCHAL_SA_REG(s, 0, 0, 2, 0, aed28, 8, 8, 8, 0x101C, aed, 28, 64, 0, 0, 0) \
-XCHAL_SA_REG(s, 0, 0, 2, 0, aed29, 8, 8, 8, 0x101D, aed, 29, 64, 0, 0, 0) \
-XCHAL_SA_REG(s, 0, 0, 2, 0, aed30, 8, 8, 8, 0x101E, aed, 30, 64, 0, 0, 0) \
-XCHAL_SA_REG(s, 0, 0, 2, 0, aed31, 8, 8, 8, 0x101F, aed, 31, 64, 0, 0, 0) \
-XCHAL_SA_REG(s, 0, 0, 2, 0, aep0, 1, 1, 1, 0x1024, aep, 0, 8, 0, 0, 0) \
-XCHAL_SA_REG(s, 0, 0, 2, 0, aep1, 1, 1, 1, 0x1025, aep, 1, 8, 0, 0, 0) \
-XCHAL_SA_REG(s, 0, 0, 2, 0, aep2, 1, 1, 1, 0x1026, aep, 2, 8, 0, 0, 0) \
-XCHAL_SA_REG(s, 0, 0, 2, 0, aep3, 1, 1, 1, 0x1027, aep, 3, 8, 0, 0, 0) \
-XCHAL_SA_REG(s, 0, 0, 2, 0, u0, 16, 16, 16, 0x1020, u, 0, 128, 0, 0, 0) \
-XCHAL_SA_REG(s, 0, 0, 2, 0, u1, 16, 16, 16, 0x1021, u, 1, 128, 0, 0, 0) \
-XCHAL_SA_REG(s, 0, 0, 2, 0, u2, 16, 16, 16, 0x1022, u, 2, 128, 0, 0, 0) \
-XCHAL_SA_REG(s, 0, 0, 2, 0, u3, 16, 16, 16, 0x1023, u, 3, 128, 0, 0, 0))
-
-#define XCHAL_CP2_SA_NUM	0
-#define XCHAL_CP2_SA_LIST(s)	/* empty */
-
-#define XCHAL_CP3_SA_NUM	0
-#define XCHAL_CP3_SA_LIST(s)	/* empty */
-
-#define XCHAL_CP4_SA_NUM	0
-#define XCHAL_CP4_SA_LIST(s)	/* empty */
-
-#define XCHAL_CP5_SA_NUM	0
-#define XCHAL_CP5_SA_LIST(s)	/* empty */
-
-#define XCHAL_CP6_SA_NUM	0
-#define XCHAL_CP6_SA_LIST(s)	/* empty */
-
-#define XCHAL_CP7_SA_NUM	0
-#define XCHAL_CP7_SA_LIST(s)	/* empty */
-
-/* Byte length of instruction from its first nibble (op0 field), per FLIX.  */
-#define XCHAL_OP0_FORMAT_LENGTHS	(3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 8, 16)
-/* Byte length of instruction from its first byte, per FLIX.  */
-#define XCHAL_BYTE0_FORMAT_LENGTHS	(\
-3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 8, 16, \
-3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 8, 16, \
-3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 8, 16, \
-3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 8, 16, \
-3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 8, 16, \
-3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 8, 16, \
-3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 8, 16, \
-3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 8, 16, \
-3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 8, 16, \
-3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 8, 16, \
-3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 8, 16, \
-3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 8, 16, \
-3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 8, 16, \
-3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 8, 16, \
-3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 8, 16, \
-3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 8, 16, \)
-
-/* parasoft-end-suppress ALL "This file not MISRA checked." */
-
-#endif /* XTENSA_CORE_TIE_H */
-
diff --git a/src/platform/mt8196/include/platform/drivers/idc.h b/src/platform/mt8196/include/platform/drivers/idc.h
deleted file mode 100644
index 8ad311b1471b..000000000000
--- a/src/platform/mt8196/include/platform/drivers/idc.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2024 MediaTek. All rights reserved.
- *
- * Author: Hailong Fan <hailong.fan@mediatek.com>
- */
-
-#if defined(__XTOS_RTOS_IDC_H__) || defined(__ZEPHYR_RTOS_IDC_H__)
-
-#ifndef __PLATFORM_DRIVERS_IDC_H__
-#define __PLATFORM_DRIVERS_IDC_H__
-
-#include <stdint.h>
-
-struct idc_msg;
-
-static inline int idc_send_msg(struct idc_msg *msg, uint32_t mode)
-{
-	return 0;
-}
-
-static inline int idc_init(void)
-{
-	return 0;
-}
-
-#endif /* __PLATFORM_DRIVERS_IDC_H__ */
-
-#else
-
-#error "This file shouldn't be included from outside of Zephyr/XTOS's rtos/idc.h"
-
-#endif
diff --git a/src/platform/mt8196/include/platform/drivers/intc.h b/src/platform/mt8196/include/platform/drivers/intc.h
deleted file mode 100644
index be741ae6e484..000000000000
--- a/src/platform/mt8196/include/platform/drivers/intc.h
+++ /dev/null
@@ -1,186 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2024 MediaTek. All rights reserved.
- *
- * Author: Hailong Fan <hailong.fan@mediatek.com>
- */
-#ifndef MTK_INTC_H
-#define MTK_INTC_H
-
-#include <rtos/bit.h>
-#include <stdint.h>
-#include <platform/drivers/mt_reg_base.h>
-
-enum IRQn_Type {
-	CCU_IRQn           = 0,
-	SCP_IRQn           = 1,
-	SPM_IRQn           = 2,
-	PCIE_IRQn          = 3,
-	INFRA_HANG_IRQn    = 4,
-	PERI_TIMEOUT_IRQn  = 5,
-	MBOX_C0_IRQn       = 6,
-	MBOX_C1_IRQn       = 7,
-	TIMER0_IRQn        = 8,
-	TIMER1_IRQn        = 9,
-	IPC_C0_IRQn        = 10,
-	IPC_C1_IRQn        = 11,
-	IPC1_RSV_IRQn      = 12,
-	C2C_SW_C0_IRQn     = 13,
-	C2C_SW_C1_IRQn     = 14,
-	UART_IRQn          = 15,
-	UART_BT_IRQn       = 16,
-	LATENCY_MON_IRQn   = 17,
-	BUS_TRACKER_IRQn   = 18,
-	USB0_IRQn          = 19,
-	USB1_IRQn          = 20,
-	SCPVOW_IRQn        = 21,
-	CCIF3_C0_IRQn      = 22,
-	CCIF3_C1_IRQn      = 23,
-	PWR_CTRL_IRQn      = 24,
-	DMA_C0_IRQn        = 25,
-	DMA_C1_IRQn        = 26, // no use as gdma only has one set
-	AXI_DMA0_IRQn      = 27,
-	AXI_DMA1_IRQn      = 28,
-	AUDIO_C0_IRQn      = 29,
-	AUDIO_C1_IRQn      = 30,
-	HIFI5_WDT_C0_IRQn  = 31,
-	HIFI5_WDT_C1_IRQn  = 32,
-	APU_MBOX_C0_IRQn   = 33,
-	APU_MBOX_C1_IRQn   = 34,
-	TIMER2_IRQn        = 35,
-	PWR_ON_C0_IRQ      = 36,
-	PWR_ON_C1_IRQ      = 37,
-	WAKEUP_SRC_C0_IRQn = 38,
-	WAKEUP_SRC_C1_IRQn = 39,
-	WDT_IRQn           = 40,
-	CONNSYS1_IRQn      = 41, // BTCVSD
-	CONNSYS3_IRQn      = 42, // BLEISO
-	CONNSYS4_IRQn      = 43, // ISOCH, bt2dsp_isoch_irq_mask
-	CONNSYS2_IRQn      = 44, // A2DP
-	IPIC_IRQn          = 45,
-	AXI_DMA2_IRQn      = 46,
-	AXI_DMA3_IRQn      = 47,
-	APSRC_DDREN_IRQn   = 48,
-	LAT_MON_EMI_IRQn   = 49,
-	LAT_MON_INFRA_IRQn = 50,
-	DEVAPC_VIO_IRQn    = 51,
-	AO_INFRA_HANG_IRQn = 52,
-	BUS_TRA_EMI_IRQn   = 53,
-	BUS_TRA_INFRA_IRQn = 54,
-	L2SRAM_VIO_IRQn    = 55,
-	L2SRAM_SETERR_IRQn = 56,
-	PCIERC_GRP2_IRQn   = 57,
-	PCIERC_GRP3_IRQn   = 58,
-	IRQ_MAX_CHANNEL    = 59,
-	NO_IRQ             = 0xFFFFFFFFU, // -1
-};
-
-#define INTC_GRP_LEN                2
-#define INTC_GRP_GAP                3 // size of group = 2 words = 8 bytes
-#define WORD_LEN                    32
-#define INTC_WORD(irq)              ((irq) >> 5)
-#define INTC_BIT(irq)               (1 << ((irq) & 0x1F))
-#define INTC_WORD_OFS(word)         ((word) << 2)
-#ifndef INTC_GROUP_OFS
-#define INTC_GROUP_OFS(grp)         ((grp) << INTC_GRP_GAP)
-#endif
-
-// #define INTC_IRQ_RAW_STA(word)      (INTC_IRQ_RAW_STA0 + INTC_WORD_OFS(word))
-#define INTC_IRQ_STA(word)          (INTC_IRQ_STA0 + INTC_WORD_OFS(word))
-#define INTC_IRQ_EN(word)           (INTC_IRQ_EN0 + INTC_WORD_OFS(word))
-#define INTC_IRQ_WAKE_EN(word)      (INTC_IRQ_WAKE_EN0 + INTC_WORD_OFS(word))
-#define INTC_IRQ_STAGE1_EN(word)    (INTC_IRQ_STAGE1_EN0 + INTC_WORD_OFS(word))
-#define INTC_IRQ_POL(word)          (INTC_IRQ_POL0 + INTC_WORD_OFS(word))
-#define INTC_IRQ_GRP(grp, word)     (INTC_IRQ_GRP0_0 + INTC_GROUP_OFS(grp)\
-				     + INTC_WORD_OFS(word))
-#define INTC_IRQ_GRP_STA(grp, word) (INTC_IRQ_GRP0_STA0 + INTC_GROUP_OFS(grp)\
-				     + INTC_WORD_OFS(word))
-
-/* intc group level */
-#define INTC_GRP0_LEVEL             XCHAL_INT0_LEVEL
-#define INTC_GRP1_LEVEL             XCHAL_INT1_LEVEL
-#define INTC_GRP2_LEVEL             XCHAL_INT2_LEVEL
-#define INTC_GRP3_LEVEL             XCHAL_INT3_LEVEL
-#define INTC_GRP4_LEVEL             XCHAL_INT4_LEVEL
-#define INTC_GRP5_LEVEL             XCHAL_INT5_LEVEL
-#define INTC_GRP6_LEVEL             XCHAL_INT7_LEVEL
-#define INTC_GRP7_LEVEL             XCHAL_INT8_LEVEL
-#define INTC_GRP8_LEVEL             XCHAL_INT9_LEVEL
-#define INTC_GRP9_LEVEL             XCHAL_INT10_LEVEL
-#define INTC_GRP10_LEVEL            XCHAL_INT11_LEVEL
-#define INTC_GRP11_LEVEL            XCHAL_INT16_LEVEL
-#define INTC_GRP12_LEVEL            XCHAL_INT17_LEVEL
-#define INTC_GRP13_LEVEL            XCHAL_INT18_LEVEL
-#define INTC_GRP14_LEVEL            XCHAL_INT20_LEVEL
-#define INTC_GRP15_LEVEL            XCHAL_INT21_LEVEL
-
-
-enum INTC_GROUP {
-	INTC_GRP0 = 0,
-	INTC_GRP1,
-	INTC_GRP2,
-	INTC_GRP3,
-	INTC_GRP4,
-	INTC_GRP5,
-	INTC_GRP6,
-	INTC_GRP7,
-	INTC_GRP8,
-	INTC_GRP9,
-	INTC_GRP10,
-	INTC_GRP11,
-	INTC_GRP12,
-	INTC_GRP13,
-	INTC_GRP14,
-	INTC_GRP15,
-	INTC_GRP_NUM,
-	NO_GRP,
-};
-
-enum INTC_POL {
-	INTC_POL_HIGH = 0x0,
-	INTC_POL_LOW = 0x1,
-	INTC_POL_NUM,
-};
-
-struct intc_irq_desc_t {
-	uint8_t id;
-	uint8_t group;
-	uint8_t pol;
-};
-
-struct intc_desc_t {
-	uint32_t int_en[INTC_GRP_LEN];
-	uint32_t grp_irqs[INTC_GRP_NUM][INTC_GRP_LEN];
-	struct intc_irq_desc_t irqs[IRQ_MAX_CHANNEL];
-};
-
-struct intc_irq_config {
-	uint32_t int_en[INTC_GRP_LEN];
-};
-
-struct intc_grp_config {
-	uint32_t grp_irq[INTC_GRP_NUM][INTC_GRP_LEN];
-};
-
-struct intc_coreoff_wake_en_config {
-	uint32_t wake_en[INTC_GRP_LEN];
-};
-
-struct intc_sleep_wake_en_config {
-	uint32_t wake_en[INTC_GRP_LEN];
-};
-
-extern const unsigned char grp_pri[INTC_GRP_NUM];
-extern const uint8_t irq2grp_map[IRQ_MAX_CHANNEL];
-extern const uint8_t grp2hifi_irq_map[INTC_GRP_NUM];
-void intc_init(void);
-
-#ifdef CFG_TICKLESS_SUPPORT
-extern struct intc_sleep_wake_en_config sleep_wakeup_src_en;
-#endif
-#ifdef CFG_CORE_OFF_SUPPORT
-extern struct intc_coreoff_wake_en_config coreoff_wakeup_src_en;
-#endif
-
-#endif /* INTC_H */
-
diff --git a/src/platform/mt8196/include/platform/drivers/interrupt.h b/src/platform/mt8196/include/platform/drivers/interrupt.h
deleted file mode 100644
index 71048100df8c..000000000000
--- a/src/platform/mt8196/include/platform/drivers/interrupt.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2024 MediaTek. All rights reserved.
- *
- * Author: Hailong Fan <hailong.fan@mediatek.com>
- */
-
-#ifdef __SOF_DRIVERS_INTERRUPT_H__
-
-#ifndef __PLATFORM_DRIVERS_INTERRUPT_H__
-#define __PLATFORM_DRIVERS_INTERRUPT_H__
-
-#include <stdint.h>
-#include <platform/drivers/mt_reg_base.h>
-#include <platform/drivers/intc.h>
-
-#define PLATFORM_IRQ_HW_NUM		XCHAL_NUM_INTERRUPTS
-#define PLATFORM_IRQ_FIRST_CHILD	PLATFORM_IRQ_HW_NUM
-#define PLATFORM_IRQ_CHILDREN		32
-
-/* MTK_ADSP_IRQ_MASK */
-#define MTK_DSP_OUT_IRQ_MASK		0x3FF
-
-#define HIFI_IRQ_MAX_CHANNEL   26
-
-#define DEFALUT_WAKEUP_SRC_MASK_BIT    0x001A5E13
-#define DEFAULT_WAKEUP_SRC_EN0_BIT     0xA046B550
-#define DEFAULT_WAKEUP_SRC_EN1_BIT     0x00002148
-
-#define MTK_DSP_IRQ_MBOX_C0         2
-#define MTK_DSP_IRQ_OSTIMER32_C0	1
-#define IPC0_IRQn         IPC_C0_IRQn
-#define C2C_SW_IRQn       C2C_SW_C0_IRQn
-#define CCIF3_IRQn        CCIF3_C0_IRQn
-#define DMA_IRQn          DMA_C0_IRQn
-#define AUDIO_IRQn        AUDIO_C0_IRQn
-#define HIFI5_WDT_IRQn    HIFI5_WDT_C0_IRQn
-#define APU_MBOX_IRQn     APU_MBOX_C0_IRQn
-#define PWR_ON_CORE_IRQn  PWR_ON_C0_IRQ
-#define WAKEUP_SRC_IRQn   WAKEUP_SRC_C0_IRQn
-#define AXI_DMA_CH0_IRQn  AXI_DMA0_IRQn
-#define AXI_DMA_CH1_IRQn  AXI_DMA2_IRQn
-
-/* following interrupts are HiFi internal interrupts */
-#define MTK_DSP_IRQ_NMI                 25
-#define MTK_DSP_IRQ_PROFILING           29
-#define MTK_DSP_IRQ_WERR                30
-#define MTK_DSP_IRQ_SW                  31
-#define MTK_MAX_IRQ_NUM			59
-
-/* grouped mailbox IRQ */
-#define MTK_DSP_IRQ_MBOX0		59
-#define MTK_DSP_IRQ_MBOX1		60
-#define MTK_DSP_IRQ_MBOX2		61
-#define MTK_DSP_IRQ_MBOX3		62
-#define MTK_DSP_IRQ_MBOX4		63
-
-#define	MTK_DSP_MBOX_MASK		0xF
-
-int mtk_irq_group_id(uint32_t irq);
-void intc_irq_unmask(enum IRQn_Type irq);
-void intc_irq_mask(enum IRQn_Type irq);
-int intc_irq_enable(enum IRQn_Type irq);
-int intc_irq_disable(enum IRQn_Type irq);
-
-#endif /* __PLATFORM_DRIVERS_INTERRUPT_H__ */
-
-#else
-
-#error "This file shouldn't be included from outside of sof/drivers/interrupt.h"
-
-#endif /* __SOF_DRIVERS_INTERRUPT_H__ */
diff --git a/src/platform/mt8196/include/platform/drivers/mt_reg_base.h b/src/platform/mt8196/include/platform/drivers/mt_reg_base.h
deleted file mode 100644
index bb990270512e..000000000000
--- a/src/platform/mt8196/include/platform/drivers/mt_reg_base.h
+++ /dev/null
@@ -1,115 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2024 MediaTek. All rights reserved.
- *
- * Author: Hailong Fan <hailong.fan@mediatek.com>
- *
- */
-
-#ifndef MT_REG_BASE_H
-#define MT_REG_BASE_H
-
-#define MTK_DSP_CFGREG_BASE		0x1A000000 /* DSP Register base */
-#define MTK_DSP_CFGREG_SIZE		0x1000
-#define MTK_ADSP_CFGREG_SW_RSTN		(MTK_DSP_CFGREG_BASE + 0x0000)
-#define MTK_ADSP_HIFI_IO_CONFIG		(MTK_DSP_CFGREG_BASE + 0x000c)
-#define MTK_ADSP_IRQ_STATUS		(MTK_DSP_CFGREG_BASE + 0x0010)
-#define MTK_ADSP_SW_INT_SET		(MTK_DSP_CFGREG_BASE + 0x0018)
-#define MTK_ADSP_SW_INT_CLR		(MTK_DSP_CFGREG_BASE + 0x001c)
-#define MTK_ADSP_SW_INT_32A		(MTK_DSP_CFGREG_BASE + 0x0020)
-#define MTK_ADSP_IRQ_MASK		(MTK_DSP_CFGREG_BASE + 0x0030)
-#define MTK_ADSP_GENERAL_IRQ_SET	(MTK_DSP_CFGREG_BASE + 0x0034)
-#define MTK_ADSP_GENERAL_IRQ_CLR	(MTK_DSP_CFGREG_BASE + 0x0038)
-#define MTK_ADSP_DVFSRC_STATE		(MTK_DSP_CFGREG_BASE + 0x003c)
-#define MTK_ADSP_DVFSRC_REQ		(MTK_DSP_CFGREG_BASE + 0x0040)
-#define MTK_ADSP_DDREN_REQ_0		(MTK_DSP_CFGREG_BASE + 0x0044)
-#define MTK_ADSP_SPM_ACK		(MTK_DSP_CFGREG_BASE + 0x004c)
-#define MTK_ADSP_IRQ_EN			(MTK_DSP_CFGREG_BASE + 0x0050)
-#define MTK_ADSP_IRQ_POL_FIX		(MTK_DSP_CFGREG_BASE + 0x0054)
-#define MTK_ADSP_SPM_WAKEUPSRC_CORE0	(MTK_DSP_CFGREG_BASE + 0x005c)
-#define MTK_ADSP_SEMAPHORE		(MTK_DSP_CFGREG_BASE + 0x0064)
-#define MTK_ADSP_DBG_SEL		(MTK_DSP_CFGREG_BASE + 0x0074)
-#define MTK_ADSP_DBG_INFO		(MTK_DSP_CFGREG_BASE + 0x0078)
-#define MTK_ADSP_WDT_CON_C0		(MTK_DSP_CFGREG_BASE + 0x007c)
-#define MTK_ADSP_WDT_INIT_VALUE_C0	(MTK_DSP_CFGREG_BASE + 0x0080)
-#define MTK_ADSP_WDT_CNT_C0		(MTK_DSP_CFGREG_BASE + 0x0084)
-#define MTK_ADSP_WAKEUPSRC_MASK_C0	(MTK_DSP_CFGREG_BASE + 0x00a0)
-#define MTK_ADSP_WAKEUPSRC_IRQ_C0	(MTK_DSP_CFGREG_BASE + 0x00a4)
-#define MTK_ADSP2SPM_MBOX		(MTK_DSP_CFGREG_BASE + 0x00bc)
-#define MTK_SPM2ADSP_MBOX		(MTK_DSP_CFGREG_BASE + 0x00c0)
-
-/* intc */
-#define MTK_ADSP_INTC_BASE                   (MTK_DSP_CFGREG_BASE + 0x14000)
-
-#define INTC_IRQ_RAW_STA0                (MTK_ADSP_INTC_BASE + 0x000)
-#define INTC_IRQ_STA0                    (MTK_ADSP_INTC_BASE + 0x008)
-#define INTC_IRQ_STA1                    (MTK_ADSP_INTC_BASE + 0x00c)
-#define INTC_IRQ_EN0                     (MTK_ADSP_INTC_BASE + 0x010)
-#define INTC_IRQ_POL0                    (MTK_ADSP_INTC_BASE + 0x018)
-#define INTC_IRQ_WAKE_EN0                (MTK_ADSP_INTC_BASE + 0x020)
-#define INTC_IRQ_STAGE1_EN0              (MTK_ADSP_INTC_BASE + 0x030)
-#define INTC_IRQ_GRP0_0                  (MTK_ADSP_INTC_BASE + 0x040)
-#define INTC_IRQ_GRP0_STA0               (MTK_ADSP_INTC_BASE + 0x0C0)
-#define INTC_GRP_IRQ_OUT_STA             (MTK_ADSP_INTC_BASE + 0x140)
-
-#define MTK_GPR_RW_REG0			(MTK_DSP_CFGREG_BASE + 0x0440)
-#define MTK_GPR_RW_REG1			(MTK_DSP_CFGREG_BASE + 0x0444)
-#define MTK_GPR_RW_REG2			(MTK_DSP_CFGREG_BASE + 0x0448)
-#define MTK_GPR_RW_REG3			(MTK_DSP_CFGREG_BASE + 0x044c)
-#define MTK_GPR_RW_REG4			(MTK_DSP_CFGREG_BASE + 0x0450)
-#define MTK_GPR_RW_REG5			(MTK_DSP_CFGREG_BASE + 0x0454)
-#define MTK_GPR_RW_REG6			(MTK_DSP_CFGREG_BASE + 0x0458)
-#define MTK_GPR_RW_REG7			(MTK_DSP_CFGREG_BASE + 0x045c)
-#define MTK_GPR_RW_REG8			(MTK_DSP_CFGREG_BASE + 0x0460)
-#define MTK_GPR_RW_REG9			(MTK_DSP_CFGREG_BASE + 0x0464)
-#define MTK_GPR_RW_REG10		(MTK_DSP_CFGREG_BASE + 0x0468)
-#define MTK_GPR_RW_REG11		(MTK_DSP_CFGREG_BASE + 0x046c)
-#define MTK_GPR_RW_REG12		(MTK_DSP_CFGREG_BASE + 0x0470)
-#define MTK_GPR_RW_REG13		(MTK_DSP_CFGREG_BASE + 0x0474)
-#define MTK_GPR_RW_REG14		(MTK_DSP_CFGREG_BASE + 0x0478)
-#define MTK_GPR_RW_REG15		(MTK_DSP_CFGREG_BASE + 0x047c)
-#define MTK_GPR_RW_REG16		(MTK_DSP_CFGREG_BASE + 0x0480)
-#define MTK_GPR_RW_REG17		(MTK_DSP_CFGREG_BASE + 0x0484)
-#define MTK_GPR_RW_REG18		(MTK_DSP_CFGREG_BASE + 0x0488)
-#define MTK_GPR_RW_REG19		(MTK_DSP_CFGREG_BASE + 0x048c)
-#define MTK_GPR_RW_REG20		(MTK_DSP_CFGREG_BASE + 0x0490)
-#define MTK_GPR_RW_REG21		(MTK_DSP_CFGREG_BASE + 0x0494)
-#define MTK_GPR_RW_REG22		(MTK_DSP_CFGREG_BASE + 0x0498)
-#define MTK_GPR_RW_REG23		(MTK_DSP_CFGREG_BASE + 0x049c)
-#define MTK_GPR_RW_REG24		(MTK_DSP_CFGREG_BASE + 0x04a0)
-#define MTK_GPR_RW_REG25		(MTK_DSP_CFGREG_BASE + 0x04a4)
-#define MTK_GPR_RW_REG26		(MTK_DSP_CFGREG_BASE + 0x04a8)
-#define MTK_GPR_RW_REG27		(MTK_DSP_CFGREG_BASE + 0x04ac)
-/* use for tickless status */
-#define MTK_GPR_RW_REG28		(MTK_DSP_CFGREG_BASE + 0x04b0)
-#define MTK_GPR_RW_REG29		(MTK_DSP_CFGREG_BASE + 0x04b4)
-
-#define MTK_ADSP_IRQ_OUT_MASK		(MTK_DSP_CFGREG_BASE + 0x0500)
-
-#define MTK_DSP_CKCTRL_BASE		(MTK_DSP_CFGREG_BASE + 0x1000)
-#define MTK_DSP_CKCTRL_SIZE		0x1000
-
-#define MTK_DSP_OS_TIMER_BASE		(MTK_DSP_CFGREG_BASE + 0xB000)
-#define MTK_DSP_OS_TIMER_SIZE		0x1000
-
-#define MTK_DSP_UART0_BASE		(MTK_DSP_CFGREG_BASE + 0xD000)
-#define MTK_DSP_UART0_SIZE		0x1000
-#define MTK_DSP_BT_UART_BASE           (MTK_DSP_CFGREG_BASE + 0xE000)
-#define MTK_DSP_BT_UART_SIZE		0x1000
-
-#define MTK_DSP_BUS_BASE		(MTK_DSP_CFGREG_BASE + 0xF000)
-#define MTK_DSP_BUS_SIZE		0x1000
-
-#define MTK_DSP_SECURE_BASE		(MTK_DSP_CFGREG_BASE + 0x345000)
-#define MTK_MBOX_IRQ_IN                 (MTK_DSP_SECURE_BASE + 0x70)
-
-/* MBOX registers */
-#define MTK_ADSP_MBOX_BASE		(MTK_DSP_CFGREG_BASE + 0x350000)
-#define MTK_ADSP_MBOX_REG_BASE(x)	(MTK_ADSP_MBOX_BASE + (0x10000 * (x)))
-#define MTK_ADSP_MBOX_REG_SIZE		(0x50000)
-#define MTK_ADSP_MBOX_IN_CMD(x)		(MTK_ADSP_MBOX_REG_BASE(x) + 0x100)
-#define MTK_ADSP_MBOX_IN_CMD_CLR(x)	(MTK_ADSP_MBOX_REG_BASE(x) + 0x108)
-#define MTK_ADSP_MBOX_OUT_CMD(x)	(MTK_ADSP_MBOX_REG_BASE(x) + 0x104)
-#define MTK_ADSP_MBOX_OUT_CMD_CLR(x)	(MTK_ADSP_MBOX_REG_BASE(x) + 0x10c)
-
-#endif /* MT_REG_BASE_H */
diff --git a/src/platform/mt8196/include/platform/drivers/timer.h b/src/platform/mt8196/include/platform/drivers/timer.h
deleted file mode 100644
index 8aeacca52981..000000000000
--- a/src/platform/mt8196/include/platform/drivers/timer.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2024 MediaTek. All rights reserved.
- *
- * Author: Hailong Fan <hailong.fan@mediatek.com>
- */
-
-#ifndef __PLATFORM_DRIVERS_TIMER_H__
-#define __PLATFORM_DRIVERS_TIMER_H__
-
-#include <rtos/bit.h>
-#include <platform/drivers/mt_reg_base.h>
-
-/*-------timer:ostimer0-------*/
-enum ostimer {
-	OSTIMER0 = 0,
-	OSTIMER1,
-	OSTIMER2,
-	OSTIMER3,
-	NR_TMRS
-};
-
-#define MTK_TIMER_CON(n)		(MTK_DSP_OS_TIMER_BASE + 0x0 + 0x10 * (n))
-#define MTK_TIMER_RST_VAL(n)		(MTK_DSP_OS_TIMER_BASE + 0x4 + 0x10 * (n))
-#define MTK_TIMER_CUR_VAL(n)		(MTK_DSP_OS_TIMER_BASE + 0x8 + 0x10 * (n))
-#define MTK_TIMER_IRQ_ACK(n)		(MTK_DSP_OS_TIMER_BASE + 0xC + 0x10 * (n))
-
-#define MTK_TIMER_ENABLE_BIT		BIT(0)
-#define MTK_TIMER_IRQ_ENABLE		BIT(0)
-#define MTK_TIMER_IRQ_STA		BIT(4)
-#define MTK_TIMER_IRQ_CLEAR		BIT(5)
-
-#define MTK_TIMER_CLKSRC_BIT		(BIT(4) | BIT(5))
-#define MTK_TIMER_CLK_SRC_CLK_26M	0
-#define MTK_TIMER_CLK_SRC_BCLK		BIT(5)
-#define MTK_TIMER_CLK_SRC_PCLK		(BIT(4) | BIT(5))
-
-/*-------platform_timer: 64 bit systimer-------*/
-#define MTK_OSTIMER_CON			(MTK_DSP_OS_TIMER_BASE + 0x80)
-#define MTK_OSTIMER_CUR_L		(MTK_DSP_OS_TIMER_BASE + 0x8C)
-#define MTK_OSTIMER_CUR_H		(MTK_DSP_OS_TIMER_BASE + 0x90)
-#define MTK_OSTIMER_TVAL		(MTK_DSP_OS_TIMER_BASE + 0x94)
-#define MTK_OSTIMER_IRQ_ACK		(MTK_DSP_OS_TIMER_BASE + 0x98)
-
-#define MTK_OSTIMER_EN_BIT			BIT(0)
-
-#endif /* __PLATFORM_DRIVERS_TIMER_H__ */
diff --git a/src/platform/mt8196/include/platform/lib/clk.h b/src/platform/mt8196/include/platform/lib/clk.h
deleted file mode 100644
index f4f311948fb4..000000000000
--- a/src/platform/mt8196/include/platform/lib/clk.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2024 MediaTek. All rights reserved.
- *
- * Author: Hailong Fan <hailong.fan@mediatek.com>
- */
-
-#ifdef __SOF_LIB_CLK_H__
-
-#ifndef __PLATFORM_LIB_CLK_H__
-#define __PLATFORM_LIB_CLK_H__
-
-#include <stdint.h>
-
-struct sof;
-
-#define CPU_DEFAULT_IDX				0
-
-#define CLK_CPU(x)				(x)
-#define CLK_DEFAULT_CPU_HZ			26000000
-#define CLK_MAX_CPU_HZ				800000000
-#define NUM_CLOCKS				1
-#define NUM_CPU_FREQ				2
-
-void platform_clock_init(struct sof *sof);
-
-#endif /* __PLATFORM_LIB_CLK_H__ */
-
-#else
-
-#error "This file shouldn't be included from outside of sof/lib/clk.h"
-
-#endif /* __SOF_LIB_CLK_H__ */
diff --git a/src/platform/mt8196/include/platform/lib/cpu.h b/src/platform/mt8196/include/platform/lib/cpu.h
deleted file mode 100644
index f99974213c2f..000000000000
--- a/src/platform/mt8196/include/platform/lib/cpu.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2024 MediaTek. All rights reserved.
- *
- * Author: Hailong Fan <hailong.fan@mediatek.com>
- */
-
-#ifdef __SOF_LIB_CPU_H__
-
-#ifndef __PLATFORM_LIB_CPU_H__
-#define __PLATFORM_LIB_CPU_H__
-
-/** \brief Id of primary DSP core */
-#define PLATFORM_PRIMARY_CORE_ID	0
-
-#endif /* __PLATFORM_LIB_CPU_H__ */
-
-#else
-
-#error "This file shouldn't be included from outside of sof/lib/cpu.h"
-
-#endif /* __SOF_LIB_CPU_H__ */
diff --git a/src/platform/mt8196/include/platform/lib/dai.h b/src/platform/mt8196/include/platform/lib/dai.h
deleted file mode 100644
index e56a35d5ccc1..000000000000
--- a/src/platform/mt8196/include/platform/lib/dai.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2024 MediaTek. All rights reserved.
- *
- * Author: Hailong Fan <hailong.fan@mediatek.com>
- */
-
-#ifdef __SOF_LIB_DAI_H__
-
-#ifndef __PLATFORM_LIB_DAI_H__
-#define __PLATFORM_LIB_DAI_H__
-
-#endif /* __PLATFORM_LIB_DAI_H__ */
-
-#else
-
-#error "This file shouldn't be included from outside of sof/lib/dai.h"
-
-#endif /* __SOF_LIB_DAI_H__ */
diff --git a/src/platform/mt8196/include/platform/lib/dma.h b/src/platform/mt8196/include/platform/lib/dma.h
deleted file mode 100644
index 419f160cbfd9..000000000000
--- a/src/platform/mt8196/include/platform/lib/dma.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2024 MediaTek. All rights reserved.
- *
- * Author: Hailong Fan <hailong.fan@mediatek.com>
- */
-
-#ifdef __SOF_LIB_DMA_H__
-
-#ifndef __PLATFORM_LIB_DMA_H__
-#define __PLATFORM_LIB_DMA_H__
-
-#define PLATFORM_NUM_DMACS		2
-
-/* max number of supported DMA channels */
-#define PLATFORM_MAX_DMA_CHAN		32
-
-#define DMA_ID_AFE_MEMIF		0
-#define DMA_ID_HOST			1
-
-#define dma_chan_irq(dma, chan)		dma_irq(dma)
-#define dma_chan_irq_name(dma, chan)	dma_irq_name(dma)
-
-#endif /* __PLATFORM_LIB_DMA_H__ */
-
-#else
-
-#error "This file shouldn't be included from outside of sof/lib/dma.h"
-
-#endif /* __SOF_LIB_DMA_H__ */
diff --git a/src/platform/mt8196/include/platform/lib/mailbox.h b/src/platform/mt8196/include/platform/lib/mailbox.h
deleted file mode 100644
index 04896aaa3ee5..000000000000
--- a/src/platform/mt8196/include/platform/lib/mailbox.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2024 MediaTek. All rights reserved.
- *
- * Author: Hailong Fan <hailong.fan@mediatek.com>
- */
-
-#ifdef __SOF_LIB_MAILBOX_H__
-
-#ifndef __PLATFORM_LIB_MAILBOX_H__
-#define __PLATFORM_LIB_MAILBOX_H__
-
-#include <sof/lib/io.h>
-#include <sof/lib/memory.h>
-#include <stddef.h>
-#include <stdint.h>
-
-/*
- * The Window Region on MT8186 SRAM is organised like this :-
- * +--------------------------------------------------------------------------+
- * | Offset              | Region         |  Size                             |
- * +---------------------+----------------+-----------------------------------+
- * | SRAM_OUTBOX_BASE    | Outbox         |  SRAM_MAILBOX_SIZE                |
- * +---------------------+----------------+-----------------------------------+
- * | SRAM_INBOX_BASE     | Inbox          |  SRAM_INBOX_SIZE                  |
- * +---------------------+----------------+-----------------------------------+
- * | SRAM_DEBUG_BASE     | Debug data     |  SRAM_DEBUG_SIZE                  |
- * +---------------------+----------------+-----------------------------------+
- * | SRAM_EXCEPT_BASE    | Except         |  SRAM_EXCEPT_SIZE                 |
- * +---------------------+----------------+-----------------------------------+
- * | SRAM_STREAM_BASE    | Stream         |  SRAM_STREAM_SIZE                 |
- * +---------------------+----------------+-----------------------------------+
- * | SRAM_TRACE_BASE     | Trace Buffer   |  SRAM_TRACE_SIZE                  |
- * +---------------------+----------------+-----------------------------------+
- */
-
-#define MAILBOX_DSPBOX_SIZE		SRAM_OUTBOX_SIZE
-#define MAILBOX_DSPBOX_BASE		SRAM_OUTBOX_BASE
-#define MAILBOX_DSPBOX_OFFSET		SRAM_OUTBOX_OFFSET
-
-#define MAILBOX_HOSTBOX_SIZE		SRAM_INBOX_SIZE
-#define MAILBOX_HOSTBOX_BASE		SRAM_INBOX_BASE
-#define MAILBOX_HOSTBOX_OFFSET		SRAM_INBOX_OFFSET
-
-#define MAILBOX_DEBUG_SIZE		SRAM_DEBUG_SIZE
-#define MAILBOX_DEBUG_BASE		SRAM_DEBUG_BASE
-#define MAILBOX_DEBUG_OFFSET		SRAM_DEBUG_OFFSET
-
-#define MAILBOX_EXCEPTION_SIZE		SRAM_EXCEPT_SIZE
-#define MAILBOX_EXCEPTION_BASE		SRAM_EXCEPT_BASE
-#define MAILBOX_EXCEPTION_OFFSET	SRAM_EXCEPT_OFFSET
-
-#define MAILBOX_STREAM_SIZE		SRAM_STREAM_SIZE
-#define MAILBOX_STREAM_BASE		SRAM_STREAM_BASE
-#define MAILBOX_STREAM_OFFSET		SRAM_STREAM_OFFSET
-
-#define MAILBOX_TRACE_SIZE		SRAM_TRACE_SIZE
-#define MAILBOX_TRACE_BASE		SRAM_TRACE_BASE
-#define MAILBOX_TRACE_OFFSET		SRAM_TRACE_OFFSET
-
-#define ADSP_IPI_OP_REQ	0x1
-#define ADSP_IPI_OP_RSP	0x2
-void trigger_irq_to_host_req(void);
-void trigger_irq_to_host_rsp(void);
-
-static inline void mailbox_sw_reg_write(size_t offset, uint32_t src)
-{
-	io_reg_write(MAILBOX_DEBUG_BASE + offset, src);
-}
-
-#endif /* __PLATFORM_LIB_MAILBOX_H__ */
-
-#else
-
-#error "This file shouldn't be included from outside of sof/lib/mailbox.h"
-
-#endif /* __SOF_LIB_MAILBOX_H__ */
diff --git a/src/platform/mt8196/include/platform/lib/memory.h b/src/platform/mt8196/include/platform/lib/memory.h
deleted file mode 100644
index 41536d2ace4b..000000000000
--- a/src/platform/mt8196/include/platform/lib/memory.h
+++ /dev/null
@@ -1,216 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2024 MediaTek. All rights reserved.
- *
- * Author: Hailong Fan <hailong.fan@mediatek.com>
- */
-
-#ifdef __SOF_LIB_MEMORY_H__
-
-#ifndef __PLATFORM_LIB_MEMORY_H__
-#define __PLATFORM_LIB_MEMORY_H__
-
-#include <rtos/cache.h>
-
-/* data cache line alignment */
-#define PLATFORM_DCACHE_ALIGN sizeof(void *)
-
-/* physical DSP addresses */
-#define SRAM_BASE			0x4e100000
-#define SRAM_SIZE			0x80000
-
-/* reset vector + rodata + module_init + text + data + bss */
-#define SOF_DATA_SIZE			0x80000
-#define VECTOR_SIZE			0x700
-#define SRAM_START			(SRAM_BASE + VECTOR_SIZE)
-
-#define DRAM_BASE			0x90000000
-#define DRAM0_SIZE			0x500000
-#define MAILBOX_BASE			(DRAM_BASE + DRAM0_SIZE)
-#define DSP_SYS_SIZE			0xA00000
-
-#define UUID_ENTRY_ELF_BASE		(SRAM_BASE + SOF_DATA_SIZE)
-#define UUID_ENTRY_ELF_SIZE		0x6000
-
-#define LOG_ENTRY_ELF_BASE		(UUID_ENTRY_ELF_BASE + UUID_ENTRY_ELF_SIZE)
-#define LOG_ENTRY_ELF_SIZE		0x20000
-#define EXT_MANIFEST_ELF_BASE		(LOG_ENTRY_ELF_BASE + LOG_ENTRY_ELF_SIZE)
-#define EXT_MANIFEST_ELF_SIZE		(SRAM_BASE + SRAM_SIZE - EXT_MANIFEST_ELF_BASE)
-
-/*
- * The Memory Layout on MT8196 are organised like this :-
- *
- * +--------------------------------------------------------------------------+
- * | Offset              | Region         |  Size                             |
- * +---------------------+----------------+-----------------------------------+
- * | SRAM_START          | RO Data        |  SOF_DATA_SIZE                    |
- * |                     | text           |                                   |
- * |                     | Data           |                                   |
- * |                     | BSS            |                                   |
- * +---------------------+----------------+-----------------------------------+
- * | fw_ready                                                                 |
- * +---------------------+----------------+-----------------------------------+
- * | static_uuid                                                              |
- * +---------------------+----------------+-----------------------------------+
- * | static_log                                                               |
- * +---------------------+----------------+-----------------------------------+
- * | fw_metadata                                                              |
- * +---------------------+----------------+-----------------------------------+
- *
- * +---------------------+----------------+-----------------------------------+
- * | SOF_DRAM_BASE       |                |  SOF_DRAM_SIZE                    |
- * +---------------------+----------------+-----------------------------------+
- * | HEAP_SYSTEM_BASE    | System Heap    |  HEAP_SYSTEM_SIZE                 |
- * +---------------------+----------------+-----------------------------------+
- * | HEAP_RUNTIME_BASE   | Runtime Heap   |  HEAP_RUNTIME_SIZE                |
- * +---------------------+----------------+-----------------------------------+
- * | HEAP_BUFFER_BASE    | Module Buffers |  HEAP_BUFFER_SIZE                 |
- * +---------------------+----------------+-----------------------------------+
- * | SOF_STACK_END       | Stack          |  SOF_STACK_SIZE                   |
- * +---------------------+----------------+-----------------------------------+
- * | SOF_STACK_BASE      |                |                                   |
- * +---------------------+----------------+-----------------------------------+
- * | MAILBOX_BASE        |                |  SOF_MAILBOX_SIZE                 |
- * +---------------------+----------------+-----------------------------------+
- */
-
-#define SRAM_OUTBOX_BASE	MAILBOX_BASE
-#define SRAM_OUTBOX_SIZE	0x1000
-#define SRAM_OUTBOX_OFFSET	0
-
-#define SRAM_INBOX_BASE		(SRAM_OUTBOX_BASE + SRAM_OUTBOX_SIZE)
-#define SRAM_INBOX_SIZE		0x1000
-#define SRAM_INBOX_OFFSET	SRAM_OUTBOX_SIZE
-
-#define SRAM_DEBUG_BASE		(SRAM_INBOX_BASE + SRAM_INBOX_SIZE)
-#define SRAM_DEBUG_SIZE		0x800
-#define SRAM_DEBUG_OFFSET	(SRAM_INBOX_OFFSET + SRAM_INBOX_SIZE)
-
-#define SRAM_EXCEPT_BASE	(SRAM_DEBUG_BASE + SRAM_DEBUG_SIZE)
-#define SRAM_EXCEPT_SIZE	0x800
-#define SRAM_EXCEPT_OFFSET	(SRAM_DEBUG_OFFSET + SRAM_DEBUG_SIZE)
-
-#define SRAM_STREAM_BASE	(SRAM_EXCEPT_BASE + SRAM_EXCEPT_SIZE)
-#define SRAM_STREAM_SIZE	0x1000
-#define SRAM_STREAM_OFFSET	(SRAM_EXCEPT_OFFSET + SRAM_EXCEPT_SIZE)
-
-#define SRAM_TRACE_BASE		(SRAM_STREAM_BASE + SRAM_STREAM_SIZE)
-#define SRAM_TRACE_SIZE		0x1000
-#define SRAM_TRACE_OFFSET	(SRAM_STREAM_OFFSET + SRAM_STREAM_SIZE)
-
-/*4K + 4K +2K + 2K + 4K + 4K = 20KB*/
-#define SOF_MAILBOX_SIZE                                        \
-	(SRAM_INBOX_SIZE + SRAM_OUTBOX_SIZE + SRAM_DEBUG_SIZE + \
-	 SRAM_EXCEPT_SIZE + SRAM_STREAM_SIZE + SRAM_TRACE_SIZE)
-
-/* SOF image on DRAM */
-#define SOF_DRAM_BASE	DRAM_BASE
-#define SOF_DRAM_SIZE	0x100000
-
-/* Heap section sizes for module pool */
-#define HEAP_RT_COUNT8		0
-#define HEAP_RT_COUNT16		48
-#define HEAP_RT_COUNT32		48
-#define HEAP_RT_COUNT64		32
-#define HEAP_RT_COUNT128	32
-#define HEAP_RT_COUNT256	32
-#define HEAP_RT_COUNT512	32
-#define HEAP_RT_COUNT1024	4
-#define HEAP_RT_COUNT2048	2
-#define HEAP_RT_COUNT4096	2
-
-/* Heap section sizes for system runtime heap */
-#define HEAP_SYS_RT_COUNT64	128
-#define HEAP_SYS_RT_COUNT512	16
-#define HEAP_SYS_RT_COUNT1024	8
-
-/* Heap configuration */
-
-#define HEAP_SYSTEM_BASE	(SOF_DRAM_BASE + SOF_DRAM_SIZE)
-#define HEAP_SYSTEM_SIZE	0x6000
-
-#define HEAP_SYS_RUNTIME_BASE	(HEAP_SYSTEM_BASE + HEAP_SYSTEM_SIZE)
-/*24KB*/
-#define HEAP_SYS_RUNTIME_SIZE                                    \
-	(HEAP_SYS_RT_COUNT64 * 64 + HEAP_SYS_RT_COUNT512 * 512 + \
-	 HEAP_SYS_RT_COUNT1024 * 1024)
-
-#define HEAP_RUNTIME_BASE (HEAP_SYS_RUNTIME_BASE + HEAP_SYS_RUNTIME_SIZE)
-/*48*(16 +32) + 32*(64 128+256) + 4*(512+1024) + 1*2048 = 24832 = 24.25KB*/
-#define HEAP_RUNTIME_SIZE                                        \
-	(HEAP_RT_COUNT8 * 8 + HEAP_RT_COUNT16 * 16 +             \
-	 HEAP_RT_COUNT32 * 32 + HEAP_RT_COUNT64 * 64 +           \
-	 HEAP_RT_COUNT128 * 128 + HEAP_RT_COUNT256 * 256 +       \
-	 HEAP_RT_COUNT512 * 512 + HEAP_RT_COUNT1024 * 1024 +     \
-	 HEAP_RT_COUNT2048 * 2048 + HEAP_RT_COUNT4096 * 4096)
-
-#define HEAP_BUFFER_BASE (HEAP_RUNTIME_BASE + HEAP_RUNTIME_SIZE)
-#define HEAP_BUFFER_SIZE                                           \
-	(DRAM0_SIZE - SOF_DRAM_SIZE - HEAP_RUNTIME_SIZE - SOF_STACK_TOTAL_SIZE -   \
-	 HEAP_SYS_RUNTIME_SIZE - HEAP_SYSTEM_SIZE)
-
-#define HEAP_BUFFER_BLOCK_SIZE		0x100
-#define HEAP_BUFFER_COUNT		(HEAP_BUFFER_SIZE / HEAP_BUFFER_BLOCK_SIZE)
-
-#define PLATFORM_HEAP_SYSTEM		1 /* one per core */
-#define PLATFORM_HEAP_SYSTEM_RUNTIME	1 /* one per core */
-#define PLATFORM_HEAP_RUNTIME		1
-#define PLATFORM_HEAP_BUFFER		1
-
-/* Stack configuration */
-#define SOF_STACK_SIZE			(CONFIG_SOF_STACK_SIZE)
-#define SOF_STACK_TOTAL_SIZE		SOF_STACK_SIZE /*4KB*/
-#define SOF_STACK_BASE			(DRAM_BASE + DRAM0_SIZE)
-#define SOF_STACK_END			(SOF_STACK_BASE - SOF_STACK_TOTAL_SIZE)
-
-/* Vector and literal sizes - not in core-isa.h */
-#define SOF_MEM_VECT_LIT_SIZE		0x4
-#define SOF_MEM_VECT_TEXT_SIZE		0x1c
-#define SOF_MEM_VECT_SIZE		(SOF_MEM_VECT_TEXT_SIZE + SOF_MEM_VECT_LIT_SIZE)
-
-#define SOF_MEM_RESET_TEXT_SIZE		0x2e0
-#define SOF_MEM_RESET_LIT_SIZE		0x120
-#define SOF_MEM_VECBASE_LIT_SIZE	0x178
-
-#define SOF_MEM_RO_SIZE			0x8
-
-#define HEAP_BUF_ALIGNMENT		DCACHE_LINE_SIZE
-
-/** \brief EDF task's default stack size in bytes. */
-#define PLATFORM_TASK_DEFAULT_STACK_SIZE	3072
-
-#if !defined(__ASSEMBLER__) && !defined(LINKER)
-
-struct sof;
-
-void platform_init_memmap(struct sof *sof);
-
-#define uncache_to_cache(address)	address
-#define cache_to_uncache(address)	address
-#define cache_to_uncache_init(address)	address
-#define is_uncached(address)		0
-
-/**
- * \brief Function for keeping shared data synchronized.
- * It's used after usage of data shared by different cores.
- * Such data is dynamically allocated with SOF_MEM_FLAG_SHARED
- * flag. Does nothing, since mt8196 doesn't support SMP.
- */
-
-static inline void *platform_rfree_prepare(void *ptr)
-{
-	return ptr;
-}
-
-#endif
-
-#define host_to_local(addr)	(addr)
-#define local_to_host(addr)	(addr)
-
-#endif /* __PLATFORM_LIB_MEMORY_H__ */
-
-#else
-
-#error "This file shouldn't be included from outside of sof/lib/memory.h"
-
-#endif /* __SOF_LIB_MEMORY_H__ */
diff --git a/src/platform/mt8196/include/platform/lib/pm_runtime.h b/src/platform/mt8196/include/platform/lib/pm_runtime.h
deleted file mode 100644
index 7d6213823fd6..000000000000
--- a/src/platform/mt8196/include/platform/lib/pm_runtime.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2024 MediaTek. All rights reserved.
- *
- * Author: Hailong Fan <hailong.fan@mediatek.com>
- */
-
-#ifdef __SOF_LIB_PM_RUNTIME_H__
-
-#ifndef __PLATFORM_LIB_PM_RUNTIME_H__
-#define __PLATFORM_LIB_PM_RUNTIME_H__
-
-#include <stdint.h>
-
-struct pm_runtime_data;
-
-/**
- * \brief Initializes platform specific runtime power management.
- * \param[in,out] prd Runtime power management data.
- */
-static inline void platform_pm_runtime_init(struct pm_runtime_data *prd)
-{
-}
-
-/**
- * \brief Retrieves platform specific power management resource.
- *
- * \param[in] context Type of power management context.
- * \param[in] index The index of the device.
- * \param[in] flags The flags, set of RPM_...
- */
-static inline void platform_pm_runtime_get(uint32_t context, uint32_t index, uint32_t flags)
-{
-}
-
-/**
- * \brief Releases platform specific power management resource.
- *
- * \param[in] context Type of power management context.
- * \param[in] index The index of the device.
- * \param[in] flags The flags, set of RPM_...
- */
-static inline void platform_pm_runtime_put(uint32_t context, uint32_t index, uint32_t flags)
-{
-}
-
-static inline void platform_pm_runtime_enable(uint32_t context, uint32_t index)
-{
-}
-
-static inline void platform_pm_runtime_disable(uint32_t context, uint32_t index)
-{
-}
-
-static inline bool platform_pm_runtime_is_active(uint32_t context, uint32_t index)
-{
-	return false;
-}
-
-#endif /* __PLATFORM_LIB_PM_RUNTIME_H__ */
-
-#else
-
-#error "This file shouldn't be included from outside of sof/lib/pm_runtime.h"
-
-#endif /* __SOF_LIB_PM_RUNTIME_H__ */
diff --git a/src/platform/mt8196/include/platform/mt8196-afe-common.h b/src/platform/mt8196/include/platform/mt8196-afe-common.h
deleted file mode 100755
index e75195b50bd4..000000000000
--- a/src/platform/mt8196/include/platform/mt8196-afe-common.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2024 MediaTek. All rights reserved.
- *
- * Author: Darren Ye <darren.ye@mediatek.com>
- */
-
-#ifndef _MT_8196_AFE_COMMON_H_
-#define _MT_8196_AFE_COMMON_H_
-
-enum {
-	MT8196_MEMIF_START,
-	MT8196_MEMIF_DL_START = MT8196_MEMIF_START,
-	MT8196_MEMIF_DL1 = MT8196_MEMIF_DL_START,
-	MT8196_MEMIF_DL_24CH,
-	MT8196_MEMIF_DL_END,
-	MT8196_MEMIF_UL_START = MT8196_MEMIF_DL_END,
-	MT8196_MEMIF_UL0 = MT8196_MEMIF_UL_START,
-	MT8196_MEMIF_UL1,
-	MT8196_MEMIF_UL2,
-	MT8196_MEMIF_UL_END,
-	MT8196_MEMIF_END = MT8196_MEMIF_UL_END,
-	MT8196_MEMIF_DL_NUM = (MT8196_MEMIF_DL_END - MT8196_MEMIF_DL_START),
-	MT8196_MEMIF_UL_NUM = (MT8196_MEMIF_UL_END - MT8196_MEMIF_UL_START),
-	MT8196_MEMIF_NUM = (MT8196_MEMIF_END - MT8196_MEMIF_START),
-};
-
-/* update irq ID (= enum) from AFE_IRQ_MCU_STATUS */
-enum {
-	MT8196_IRQ_0,
-	MT8196_IRQ_1,
-	MT8196_IRQ_2,
-	MT8196_IRQ_3,
-	MT8196_IRQ_4,
-	MT8196_IRQ_5,
-	MT8196_IRQ_6,
-	MT8196_IRQ_7,
-	MT8196_IRQ_8,
-	MT8196_IRQ_9,
-	MT8196_IRQ_10,
-	MT8196_IRQ_11,
-	MT8196_IRQ_12,
-	MT8196_IRQ_13,
-	MT8196_IRQ_14,
-	MT8196_IRQ_15,
-	MT8196_IRQ_16,
-	MT8196_IRQ_17,
-	MT8196_IRQ_18,
-	MT8196_IRQ_19,
-	MT8196_IRQ_20,
-	MT8196_IRQ_21,
-	MT8196_IRQ_22,
-	MT8196_IRQ_23,
-	MT8196_IRQ_24,
-	MT8196_IRQ_25,
-	MT8196_IRQ_26,
-	MT8196_IRQ_31,  /* used only for TDM */
-	MT8196_IRQ_NUM,
-};
-
-enum {
-	MT8196_DAI_I2S_OUT4, /* speaker */
-	MT8196_DAI_I2S_OUT6, /* headset out */
-	MT8196_DAI_AP_DMIC, /* DMIC */
-	MT8196_DAI_I2S_IN6, /* headset mic */
-	MT8196_DAI_AP_DMIC_CH34,
-	MT8196_DAI_NUM,
-};
-
-#endif
diff --git a/src/platform/mt8196/include/platform/mt8196-afe-reg.h b/src/platform/mt8196/include/platform/mt8196-afe-reg.h
deleted file mode 100755
index 10c4237dd6b5..000000000000
--- a/src/platform/mt8196/include/platform/mt8196-afe-reg.h
+++ /dev/null
@@ -1,2979 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2024 MediaTek. All rights reserved.
- *
- * Author: Darren Ye <darren.ye@mediatek.com>
- */
-
-#ifndef _MT8196_AFE_REG_H_
-#define _MT8196_AFE_REG_H_
-
-#define AFE_BASE_ADDR 0x1A110000
-
-/*****************************************************************************
- * R E G I S T E R  D E F I N I T I O N
- *****************************************************************************/
-/* AFE_DL1_BASE_MSB */
-#define DL1_BASE_ADDR_MSB_SFT                                 0
-#define DL1_BASE_ADDR_MSB_MASK                                0x1ff
-#define DL1_BASE_ADDR_MSB_MASK_SFT                            (0x1ff << 0)
-
-/* AFE_DL1_BASE */
-#define DL1_BASE_ADDR_SFT                                     4
-#define DL1_BASE_ADDR_MASK                                    0xfffffff
-#define DL1_BASE_ADDR_MASK_SFT                                (0xfffffff << 4)
-
-/* AFE_DL1_CUR_MSB */
-#define DL1_CUR_PTR_MSB_SFT                                   0
-#define DL1_CUR_PTR_MSB_MASK                                  0x1ff
-#define DL1_CUR_PTR_MSB_MASK_SFT                              (0x1ff << 0)
-
-/* AFE_DL1_CUR */
-#define DL1_CUR_PTR_SFT                                       0
-#define DL1_CUR_PTR_MASK                                      0xffffffff
-#define DL1_CUR_PTR_MASK_SFT                                  (0xffffffff << 0)
-
-/* AFE_DL1_END_MSB */
-#define DL1_END_ADDR_MSB_SFT                                  0
-#define DL1_END_ADDR_MSB_MASK                                 0x1ff
-#define DL1_END_ADDR_MSB_MASK_SFT                             (0x1ff << 0)
-
-/* AFE_DL1_END */
-#define DL1_END_ADDR_SFT                                      4
-#define DL1_END_ADDR_MASK                                     0xfffffff
-#define DL1_END_ADDR_MASK_SFT                                 (0xfffffff << 4)
-
-/* AFE_DL1_RCH_MON */
-#define DL1_RCH_DATA_SFT                                      0
-#define DL1_RCH_DATA_MASK                                     0xffffffff
-#define DL1_RCH_DATA_MASK_SFT                                 (0xffffffff << 0)
-
-/* AFE_DL1_LCH_MON */
-#define DL1_LCH_DATA_SFT                                      0
-#define DL1_LCH_DATA_MASK                                     0xffffffff
-#define DL1_LCH_DATA_MASK_SFT                                 (0xffffffff << 0)
-
-/* AFE_DL1_CON0 */
-#define DL1_ON_SFT                                            28
-#define DL1_ON_MASK                                           0x1
-#define DL1_ON_MASK_SFT                                       (0x1 << 28)
-#define DL1_ONE_HEART_SEL_SFT                                 22
-#define DL1_ONE_HEART_SEL_MASK                                0x3
-#define DL1_ONE_HEART_SEL_MASK_SFT                            (0x3 << 22)
-#define DL1_MINLEN_SFT                                        20
-#define DL1_MINLEN_MASK                                       0x3
-#define DL1_MINLEN_MASK_SFT                                   (0x3 << 20)
-#define DL1_MAXLEN_SFT                                        16
-#define DL1_MAXLEN_MASK                                       0x3
-#define DL1_MAXLEN_MASK_SFT                                   (0x3 << 16)
-#define DL1_SEL_DOMAIN_SFT                                    13
-#define DL1_SEL_DOMAIN_MASK                                   0x7
-#define DL1_SEL_DOMAIN_MASK_SFT                               (0x7 << 13)
-#define DL1_SEL_FS_SFT                                        8
-#define DL1_SEL_FS_MASK                                       0x1f
-#define DL1_SEL_FS_MASK_SFT                                   (0x1f << 8)
-#define DL1_SW_CLEAR_BUF_EMPTY_SFT                            7
-#define DL1_SW_CLEAR_BUF_EMPTY_MASK                           0x1
-#define DL1_SW_CLEAR_BUF_EMPTY_MASK_SFT                       (0x1 << 7)
-#define DL1_PBUF_SIZE_SFT                                     5
-#define DL1_PBUF_SIZE_MASK                                    0x3
-#define DL1_PBUF_SIZE_MASK_SFT                                (0x3 << 5)
-#define DL1_MONO_SFT                                          4
-#define DL1_MONO_MASK                                         0x1
-#define DL1_MONO_MASK_SFT                                     (0x1 << 4)
-#define DL1_NORMAL_MODE_SFT                                   3
-#define DL1_NORMAL_MODE_MASK                                  0x1
-#define DL1_NORMAL_MODE_MASK_SFT                              (0x1 << 3)
-#define DL1_HALIGN_SFT                                        2
-#define DL1_HALIGN_MASK                                       0x1
-#define DL1_HALIGN_MASK_SFT                                   (0x1 << 2)
-#define DL1_HD_MODE_SFT                                       0
-#define DL1_HD_MODE_MASK                                      0x3
-#define DL1_HD_MODE_MASK_SFT                                  (0x3 << 0)
-
-/* AFE_DL_24CH_BASE_MSB */
-#define DL_24CH_BASE__ADDR_MSB_SFT                            0
-#define DL_24CH_BASE__ADDR_MSB_MASK                           0x1ff
-#define DL_24CH_BASE__ADDR_MSB_MASK_SFT                       (0x1ff << 0)
-
-/* AFE_DL_24CH_BASE */
-#define DL_24CH_BASE_ADDR_SFT                                 4
-#define DL_24CH_BASE_ADDR_MASK                                0xfffffff
-#define DL_24CH_BASE_ADDR_MASK_SFT                            (0xfffffff << 4)
-
-/* AFE_DL_24CH_CUR_MSB */
-#define DL_24CH_CUR_PTR_MSB_SFT                               0
-#define DL_24CH_CUR_PTR_MSB_MASK                              0x1ff
-#define DL_24CH_CUR_PTR_MSB_MASK_SFT                          (0x1ff << 0)
-
-/* AFE_DL_24CH_CUR */
-#define DL_24CH_CUR_PTR_SFT                                   0
-#define DL_24CH_CUR_PTR_MASK                                  0xffffffff
-#define DL_24CH_CUR_PTR_MASK_SFT                              (0xffffffff << 0)
-
-/* AFE_DL_24CH_END_MSB */
-#define DL_24CH_END_ADDR_MSB_SFT                              0
-#define DL_24CH_END_ADDR_MSB_MASK                             0x1ff
-#define DL_24CH_END_ADDR_MSB_MASK_SFT                         (0x1ff << 0)
-
-/* AFE_DL_24CH_END */
-#define DL_24CH_END_ADDR_SFT                                  4
-#define DL_24CH_END_ADDR_MASK                                 0xfffffff
-#define DL_24CH_END_ADDR_MASK_SFT                             (0xfffffff << 4)
-
-/* AFE_DL_24CH_CON0 */
-#define DL_24CH_ON_SFT                                        31
-#define DL_24CH_ON_MASK                                       0x1
-#define DL_24CH_ON_MASK_SFT                                   (0x1 << 31)
-#define DL_24CH_NUM_SFT                                       24
-#define DL_24CH_NUM_MASK                                      0x3f
-#define DL_24CH_NUM_MASK_SFT                                  (0x3f << 24)
-#define DL_24CH_ONE_HEART_SEL_SFT                             22
-#define DL_24CH_ONE_HEART_SEL_MASK                            0x3
-#define DL_24CH_ONE_HEART_SEL_MASK_SFT                        (0x3 << 22)
-#define DL_24CH_MINLEN_SFT                                    20
-#define DL_24CH_MINLEN_MASK                                   0x3
-#define DL_24CH_MINLEN_MASK_SFT                               (0x3 << 20)
-#define DL_24CH_MAXLEN_SFT                                    16
-#define DL_24CH_MAXLEN_MASK                                   0x3
-#define DL_24CH_MAXLEN_MASK_SFT                               (0x3 << 16)
-#define DL_24CH_SEL_DOMAIN_SFT                                13
-#define DL_24CH_SEL_DOMAIN_MASK                               0x7
-#define DL_24CH_SEL_DOMAIN_MASK_SFT                           (0x7 << 13)
-#define DL_24CH_SEL_FS_SFT                                    8
-#define DL_24CH_SEL_FS_MASK                                   0x1f
-#define DL_24CH_SEL_FS_MASK_SFT                               (0x1f << 8)
-#define DL_24CH_BUF_EMPTY_CLR_SFT                             7
-#define DL_24CH_BUF_EMPTY_CLR_MASK                            0x1
-#define DL_24CH_BUF_EMPTY_CLR_MASK_SFT                        (0x1 << 7)
-#define DL_24CH_PBUF_SIZE_SFT                                 5
-#define DL_24CH_PBUF_SIZE_MASK                                0x3
-#define DL_24CH_PBUF_SIZE_MASK_SFT                            (0x3 << 5)
-#define DL_24CH_HANG_CLR_SFT                                  4
-#define DL_24CH_HANG_CLR_MASK                                 0x1
-#define DL_24CH_HANG_CLR_MASK_SFT                             (0x1 << 4)
-#define DL_24CH_NORMAL_MODE_SFT                               3
-#define DL_24CH_NORMAL_MODE_MASK                              0x1
-#define DL_24CH_NORMAL_MODE_MASK_SFT                          (0x1 << 3)
-#define DL_24CH_HALIGN_SFT                                    2
-#define DL_24CH_HALIGN_MASK                                   0x1
-#define DL_24CH_HALIGN_MASK_SFT                               (0x1 << 2)
-#define DL_24CH_HD_MODE_SFT                                   0
-#define DL_24CH_HD_MODE_MASK                                  0x3
-#define DL_24CH_HD_MODE_MASK_SFT                              (0x3 << 0)
-
-/* AFE_DL24_BASE_MSB */
-#define DL24_BASE__ADDR_MSB_SFT                               0
-#define DL24_BASE__ADDR_MSB_MASK                              0x1ff
-#define DL24_BASE__ADDR_MSB_MASK_SFT                          (0x1ff << 0)
-
-/* AFE_DL24_BASE */
-#define DL24_BASE_ADDR_SFT                                    4
-#define DL24_BASE_ADDR_MASK                                   0xfffffff
-#define DL24_BASE_ADDR_MASK_SFT                               (0xfffffff << 4)
-
-/* AFE_DL24_CUR_MSB */
-#define DL24_CUR_PTR_MSB_SFT                                  0
-#define DL24_CUR_PTR_MSB_MASK                                 0x1ff
-#define DL24_CUR_PTR_MSB_MASK_SFT                             (0x1ff << 0)
-
-/* AFE_DL24_CUR */
-#define DL24_CUR_PTR_SFT                                      0
-#define DL24_CUR_PTR_MASK                                     0xffffffff
-#define DL24_CUR_PTR_MASK_SFT                                 (0xffffffff << 0)
-
-/* AFE_DL24_END_MSB */
-#define DL24_END_ADDR_MSB_SFT                                 0
-#define DL24_END_ADDR_MSB_MASK                                0x1ff
-#define DL24_END_ADDR_MSB_MASK_SFT                            (0x1ff << 0)
-
-/* AFE_DL24_END */
-#define DL24_END_ADDR_SFT                                     4
-#define DL24_END_ADDR_MASK                                    0xfffffff
-#define DL24_END_ADDR_MASK_SFT                                (0xfffffff << 4)
-
-/* AFE_DL24_RCH_MON */
-#define DL24_RCH_DATA_SFT                                     0
-#define DL24_RCH_DATA_MASK                                    0xffffffff
-#define DL24_RCH_DATA_MASK_SFT                                (0xffffffff << 0)
-
-/* AFE_DL24_LCH_MON */
-#define DL24_LCH_DATA_SFT                                     0
-#define DL24_LCH_DATA_MASK                                    0xffffffff
-#define DL24_LCH_DATA_MASK_SFT                                (0xffffffff << 0)
-
-/* AFE_DL24_CON0 */
-#define DL24_ON_SFT                                           28
-#define DL24_ON_MASK                                          0x1
-#define DL24_ON_MASK_SFT                                      (0x1 << 28)
-#define DL24_ONE_HEART_SEL_SFT                                22
-#define DL24_ONE_HEART_SEL_MASK                               0x3
-#define DL24_ONE_HEART_SEL_MASK_SFT                           (0x3 << 22)
-#define DL24_MINLEN_SFT                                       20
-#define DL24_MINLEN_MASK                                      0x3
-#define DL24_MINLEN_MASK_SFT                                  (0x3 << 20)
-#define DL24_MAXLEN_SFT                                       16
-#define DL24_MAXLEN_MASK                                      0x3
-#define DL24_MAXLEN_MASK_SFT                                  (0x3 << 16)
-#define DL24_SEL_DOMAIN_SFT                                   13
-#define DL24_SEL_DOMAIN_MASK                                  0x7
-#define DL24_SEL_DOMAIN_MASK_SFT                              (0x7 << 13)
-#define DL24_SEL_FS_SFT                                       8
-#define DL24_SEL_FS_MASK                                      0x1f
-#define DL24_SEL_FS_MASK_SFT                                  (0x1f << 8)
-#define DL24_SW_CLEAR_BUF_EMPTY_SFT                           7
-#define DL24_SW_CLEAR_BUF_EMPTY_MASK                          0x1
-#define DL24_SW_CLEAR_BUF_EMPTY_MASK_SFT                      (0x1 << 7)
-#define DL24_PBUF_SIZE_SFT                                    5
-#define DL24_PBUF_SIZE_MASK                                   0x3
-#define DL24_PBUF_SIZE_MASK_SFT                               (0x3 << 5)
-#define DL24_MONO_SFT                                         4
-#define DL24_MONO_MASK                                        0x1
-#define DL24_MONO_MASK_SFT                                    (0x1 << 4)
-#define DL24_NORMAL_MODE_SFT                                  3
-#define DL24_NORMAL_MODE_MASK                                 0x1
-#define DL24_NORMAL_MODE_MASK_SFT                             (0x1 << 3)
-#define DL24_HALIGN_SFT                                       2
-#define DL24_HALIGN_MASK                                      0x1
-#define DL24_HALIGN_MASK_SFT                                  (0x1 << 2)
-#define DL24_HD_MODE_SFT                                      0
-#define DL24_HD_MODE_MASK                                     0x3
-#define DL24_HD_MODE_MASK_SFT                                 (0x3 << 0)
-
-/* AFE_VUL0_BASE_MSB */
-#define VUL0_BASE_ADDR_MSB_SFT                                0
-#define VUL0_BASE_ADDR_MSB_MASK                               0x1ff
-#define VUL0_BASE_ADDR_MSB_MASK_SFT                           (0x1ff << 0)
-
-/* AFE_VUL0_BASE */
-#define VUL0_BASE_ADDR_SFT                                    4
-#define VUL0_BASE_ADDR_MASK                                   0xfffffff
-#define VUL0_BASE_ADDR_MASK_SFT                               (0xfffffff << 4)
-
-/* AFE_VUL0_CUR_MSB */
-#define VUL0_CUR_PTR_MSB_SFT                                  0
-#define VUL0_CUR_PTR_MSB_MASK                                 0x1ff
-#define VUL0_CUR_PTR_MSB_MASK_SFT                             (0x1ff << 0)
-
-/* AFE_VUL0_CUR */
-#define VUL0_CUR_PTR_SFT                                      0
-#define VUL0_CUR_PTR_MASK                                     0xffffffff
-#define VUL0_CUR_PTR_MASK_SFT                                 (0xffffffff << 0)
-
-/* AFE_VUL0_END_MSB */
-#define VUL0_END_ADDR_MSB_SFT                                 0
-#define VUL0_END_ADDR_MSB_MASK                                0x1ff
-#define VUL0_END_ADDR_MSB_MASK_SFT                            (0x1ff << 0)
-
-/* AFE_VUL0_END */
-#define VUL0_END_ADDR_SFT                                     4
-#define VUL0_END_ADDR_MASK                                    0xfffffff
-#define VUL0_END_ADDR_MASK_SFT                                (0xfffffff << 4)
-
-/* AFE_VUL0_RCH_MON */
-#define VUL0_RCH_DATA_SFT                                     0
-#define VUL0_RCH_DATA_MASK                                    0xffffffff
-#define VUL0_RCH_DATA_MASK_SFT                                (0xffffffff << 0)
-
-/* AFE_VUL0_LCH_MON */
-#define VUL0_LCH_DATA_SFT                                     0
-#define VUL0_LCH_DATA_MASK                                    0xffffffff
-#define VUL0_LCH_DATA_MASK_SFT                                (0xffffffff << 0)
-
-/* AFE_VUL0_CON0 */
-#define VUL0_ON_SFT                                           28
-#define VUL0_ON_MASK                                          0x1
-#define VUL0_ON_MASK_SFT                                      (0x1 << 28)
-#define VUL0_MINLEN_SFT                                       20
-#define VUL0_MINLEN_MASK                                      0x3
-#define VUL0_MINLEN_MASK_SFT                                  (0x3 << 20)
-#define VUL0_MAXLEN_SFT                                       16
-#define VUL0_MAXLEN_MASK                                      0x3
-#define VUL0_MAXLEN_MASK_SFT                                  (0x3 << 16)
-#define VUL0_SEL_DOMAIN_SFT                                   13
-#define VUL0_SEL_DOMAIN_MASK                                  0x7
-#define VUL0_SEL_DOMAIN_MASK_SFT                              (0x7 << 13)
-#define VUL0_SEL_FS_SFT                                       8
-#define VUL0_SEL_FS_MASK                                      0x1f
-#define VUL0_SEL_FS_MASK_SFT                                  (0x1f << 8)
-#define VUL0_SW_CLEAR_BUF_FULL_SFT                            7
-#define VUL0_SW_CLEAR_BUF_FULL_MASK                           0x1
-#define VUL0_SW_CLEAR_BUF_FULL_MASK_SFT                       (0x1 << 7)
-#define VUL0_WR_SIGN_SFT                                      6
-#define VUL0_WR_SIGN_MASK                                     0x1
-#define VUL0_WR_SIGN_MASK_SFT                                 (0x1 << 6)
-#define VUL0_R_MONO_SFT                                       5
-#define VUL0_R_MONO_MASK                                      0x1
-#define VUL0_R_MONO_MASK_SFT                                  (0x1 << 5)
-#define VUL0_MONO_SFT                                         4
-#define VUL0_MONO_MASK                                        0x1
-#define VUL0_MONO_MASK_SFT                                    (0x1 << 4)
-#define VUL0_NORMAL_MODE_SFT                                  3
-#define VUL0_NORMAL_MODE_MASK                                 0x1
-#define VUL0_NORMAL_MODE_MASK_SFT                             (0x1 << 3)
-#define VUL0_HALIGN_SFT                                       2
-#define VUL0_HALIGN_MASK                                      0x1
-#define VUL0_HALIGN_MASK_SFT                                  (0x1 << 2)
-#define VUL0_HD_MODE_SFT                                      0
-#define VUL0_HD_MODE_MASK                                     0x3
-#define VUL0_HD_MODE_MASK_SFT                                 (0x3 << 0)
-
-/* AFE_VUL1_BASE_MSB */
-#define VUL1_BASE_ADDR_MSB_SFT                                0
-#define VUL1_BASE_ADDR_MSB_MASK                               0x1ff
-#define VUL1_BASE_ADDR_MSB_MASK_SFT                           (0x1ff << 0)
-
-/* AFE_VUL1_BASE */
-#define VUL1_BASE_ADDR_SFT                                    4
-#define VUL1_BASE_ADDR_MASK                                   0xfffffff
-#define VUL1_BASE_ADDR_MASK_SFT                               (0xfffffff << 4)
-
-/* AFE_VUL1_CUR_MSB */
-#define VUL1_CUR_PTR_MSB_SFT                                  0
-#define VUL1_CUR_PTR_MSB_MASK                                 0x1ff
-#define VUL1_CUR_PTR_MSB_MASK_SFT                             (0x1ff << 0)
-
-/* AFE_VUL1_CUR */
-#define VUL1_CUR_PTR_SFT                                      0
-#define VUL1_CUR_PTR_MASK                                     0xffffffff
-#define VUL1_CUR_PTR_MASK_SFT                                 (0xffffffff << 0)
-
-/* AFE_VUL1_END_MSB */
-#define VUL1_END_ADDR_MSB_SFT                                 0
-#define VUL1_END_ADDR_MSB_MASK                                0x1ff
-#define VUL1_END_ADDR_MSB_MASK_SFT                            (0x1ff << 0)
-
-/* AFE_VUL1_END */
-#define VUL1_END_ADDR_SFT                                     4
-#define VUL1_END_ADDR_MASK                                    0xfffffff
-#define VUL1_END_ADDR_MASK_SFT                                (0xfffffff << 4)
-
-/* AFE_VUL1_RCH_MON */
-#define VUL1_RCH_DATA_SFT                                     0
-#define VUL1_RCH_DATA_MASK                                    0xffffffff
-#define VUL1_RCH_DATA_MASK_SFT                                (0xffffffff << 0)
-
-/* AFE_VUL1_LCH_MON */
-#define VUL1_LCH_DATA_SFT                                     0
-#define VUL1_LCH_DATA_MASK                                    0xffffffff
-#define VUL1_LCH_DATA_MASK_SFT                                (0xffffffff << 0)
-
-/* AFE_VUL1_CON0 */
-#define VUL1_ON_SFT                                           28
-#define VUL1_ON_MASK                                          0x1
-#define VUL1_ON_MASK_SFT                                      (0x1 << 28)
-#define VUL1_MINLEN_SFT                                       20
-#define VUL1_MINLEN_MASK                                      0x3
-#define VUL1_MINLEN_MASK_SFT                                  (0x3 << 20)
-#define VUL1_MAXLEN_SFT                                       16
-#define VUL1_MAXLEN_MASK                                      0x3
-#define VUL1_MAXLEN_MASK_SFT                                  (0x3 << 16)
-#define VUL1_SEL_DOMAIN_SFT                                   13
-#define VUL1_SEL_DOMAIN_MASK                                  0x7
-#define VUL1_SEL_DOMAIN_MASK_SFT                              (0x7 << 13)
-#define VUL1_SEL_FS_SFT                                       8
-#define VUL1_SEL_FS_MASK                                      0x1f
-#define VUL1_SEL_FS_MASK_SFT                                  (0x1f << 8)
-#define VUL1_SW_CLEAR_BUF_FULL_SFT                            7
-#define VUL1_SW_CLEAR_BUF_FULL_MASK                           0x1
-#define VUL1_SW_CLEAR_BUF_FULL_MASK_SFT                       (0x1 << 7)
-#define VUL1_WR_SIGN_SFT                                      6
-#define VUL1_WR_SIGN_MASK                                     0x1
-#define VUL1_WR_SIGN_MASK_SFT                                 (0x1 << 6)
-#define VUL1_R_MONO_SFT                                       5
-#define VUL1_R_MONO_MASK                                      0x1
-#define VUL1_R_MONO_MASK_SFT                                  (0x1 << 5)
-#define VUL1_MONO_SFT                                         4
-#define VUL1_MONO_MASK                                        0x1
-#define VUL1_MONO_MASK_SFT                                    (0x1 << 4)
-#define VUL1_NORMAL_MODE_SFT                                  3
-#define VUL1_NORMAL_MODE_MASK                                 0x1
-#define VUL1_NORMAL_MODE_MASK_SFT                             (0x1 << 3)
-#define VUL1_HALIGN_SFT                                       2
-#define VUL1_HALIGN_MASK                                      0x1
-#define VUL1_HALIGN_MASK_SFT                                  (0x1 << 2)
-#define VUL1_HD_MODE_SFT                                      0
-#define VUL1_HD_MODE_MASK                                     0x3
-#define VUL1_HD_MODE_MASK_SFT                                 (0x3 << 0)
-
-/* AFE_VUL2_BASE_MSB */
-#define VUL2_BASE_ADDR_MSB_SFT                                0
-#define VUL2_BASE_ADDR_MSB_MASK                               0x1ff
-#define VUL2_BASE_ADDR_MSB_MASK_SFT                           (0x1ff << 0)
-
-/* AFE_VUL2_BASE */
-#define VUL2_BASE_ADDR_SFT                                    4
-#define VUL2_BASE_ADDR_MASK                                   0xfffffff
-#define VUL2_BASE_ADDR_MASK_SFT                               (0xfffffff << 4)
-
-/* AFE_VUL2_CUR_MSB */
-#define VUL2_CUR_PTR_MSB_SFT                                  0
-#define VUL2_CUR_PTR_MSB_MASK                                 0x1ff
-#define VUL2_CUR_PTR_MSB_MASK_SFT                             (0x1ff << 0)
-
-/* AFE_VUL2_CUR */
-#define VUL2_CUR_PTR_SFT                                      0
-#define VUL2_CUR_PTR_MASK                                     0xffffffff
-#define VUL2_CUR_PTR_MASK_SFT                                 (0xffffffff << 0)
-
-/* AFE_VUL2_END_MSB */
-#define VUL2_END_ADDR_MSB_SFT                                 0
-#define VUL2_END_ADDR_MSB_MASK                                0x1ff
-#define VUL2_END_ADDR_MSB_MASK_SFT                            (0x1ff << 0)
-
-/* AFE_VUL2_END */
-#define VUL2_END_ADDR_SFT                                     4
-#define VUL2_END_ADDR_MASK                                    0xfffffff
-#define VUL2_END_ADDR_MASK_SFT                                (0xfffffff << 4)
-
-/* AFE_VUL2_RCH_MON */
-#define VUL2_RCH_DATA_SFT                                     0
-#define VUL2_RCH_DATA_MASK                                    0xffffffff
-#define VUL2_RCH_DATA_MASK_SFT                                (0xffffffff << 0)
-
-/* AFE_VUL2_LCH_MON */
-#define VUL2_LCH_DATA_SFT                                     0
-#define VUL2_LCH_DATA_MASK                                    0xffffffff
-#define VUL2_LCH_DATA_MASK_SFT                                (0xffffffff << 0)
-
-/* AFE_VUL2_CON0 */
-#define VUL2_ON_SFT                                           28
-#define VUL2_ON_MASK                                          0x1
-#define VUL2_ON_MASK_SFT                                      (0x1 << 28)
-#define VUL2_MINLEN_SFT                                       20
-#define VUL2_MINLEN_MASK                                      0x3
-#define VUL2_MINLEN_MASK_SFT                                  (0x3 << 20)
-#define VUL2_MAXLEN_SFT                                       16
-#define VUL2_MAXLEN_MASK                                      0x3
-#define VUL2_MAXLEN_MASK_SFT                                  (0x3 << 16)
-#define VUL2_SEL_DOMAIN_SFT                                   13
-#define VUL2_SEL_DOMAIN_MASK                                  0x7
-#define VUL2_SEL_DOMAIN_MASK_SFT                              (0x7 << 13)
-#define VUL2_SEL_FS_SFT                                       8
-#define VUL2_SEL_FS_MASK                                      0x1f
-#define VUL2_SEL_FS_MASK_SFT                                  (0x1f << 8)
-#define VUL2_SW_CLEAR_BUF_FULL_SFT                            7
-#define VUL2_SW_CLEAR_BUF_FULL_MASK                           0x1
-#define VUL2_SW_CLEAR_BUF_FULL_MASK_SFT                       (0x1 << 7)
-#define VUL2_WR_SIGN_SFT                                      6
-#define VUL2_WR_SIGN_MASK                                     0x1
-#define VUL2_WR_SIGN_MASK_SFT                                 (0x1 << 6)
-#define VUL2_R_MONO_SFT                                       5
-#define VUL2_R_MONO_MASK                                      0x1
-#define VUL2_R_MONO_MASK_SFT                                  (0x1 << 5)
-#define VUL2_MONO_SFT                                         4
-#define VUL2_MONO_MASK                                        0x1
-#define VUL2_MONO_MASK_SFT                                    (0x1 << 4)
-#define VUL2_NORMAL_MODE_SFT                                  3
-#define VUL2_NORMAL_MODE_MASK                                 0x1
-#define VUL2_NORMAL_MODE_MASK_SFT                             (0x1 << 3)
-#define VUL2_HALIGN_SFT                                       2
-#define VUL2_HALIGN_MASK                                      0x1
-#define VUL2_HALIGN_MASK_SFT                                  (0x1 << 2)
-#define VUL2_HD_MODE_SFT                                      0
-#define VUL2_HD_MODE_MASK                                     0x3
-#define VUL2_HD_MODE_MASK_SFT                                 (0x3 << 0)
-
-/* AFE_DL_24CH_CH0_MON */
-#define DL_24CH_CH0_DATA_SFT                                  0
-#define DL_24CH_CH0_DATA_MASK                                 0xffffffff
-#define DL_24CH_CH0_DATA_MASK_SFT                             (0xffffffff << 0)
-
-/* AFE_DL_24CH_CH1_MON */
-#define DL_24CH_CH1_DATA_SFT                                  0
-#define DL_24CH_CH1_DATA_MASK                                 0xffffffff
-#define DL_24CH_CH1_DATA_MASK_SFT                             (0xffffffff << 0)
-
-/* AFE_DL_24CH_CH2_MON */
-#define DL_24CH_CH2_DATA_SFT                                  0
-#define DL_24CH_CH2_DATA_MASK                                 0xffffffff
-#define DL_24CH_CH2_DATA_MASK_SFT                             (0xffffffff << 0)
-
-/* AFE_DL_24CH_CH3_MON */
-#define DL_24CH_CH3_DATA_SFT                                  0
-#define DL_24CH_CH3_DATA_MASK                                 0xffffffff
-#define DL_24CH_CH3_DATA_MASK_SFT                             (0xffffffff << 0)
-
-/* AFE_DL_24CH_CH4_MON */
-#define DL_24CH_CH4_DATA_SFT                                  0
-#define DL_24CH_CH4_DATA_MASK                                 0xffffffff
-#define DL_24CH_CH4_DATA_MASK_SFT                             (0xffffffff << 0)
-
-/* AFE_DL_24CH_CH5_MON */
-#define DL_24CH_CH5_DATA_SFT                                  0
-#define DL_24CH_CH5_DATA_MASK                                 0xffffffff
-#define DL_24CH_CH5_DATA_MASK_SFT                             (0xffffffff << 0)
-
-/* AFE_DL_24CH_CH6_MON */
-#define DL_24CH_CH6_DATA_SFT                                  0
-#define DL_24CH_CH6_DATA_MASK                                 0xffffffff
-#define DL_24CH_CH6_DATA_MASK_SFT                             (0xffffffff << 0)
-
-/* AFE_DL_24CH_CH7_MON */
-#define DL_24CH_CH7_DATA_SFT                                  0
-#define DL_24CH_CH7_DATA_MASK                                 0xffffffff
-#define DL_24CH_CH7_DATA_MASK_SFT                             (0xffffffff << 0)
-
-/* AFE_DL_24CH_CH8_MON */
-#define DL_24CH_CH8_DATA_SFT                                  0
-#define DL_24CH_CH8_DATA_MASK                                 0xffffffff
-#define DL_24CH_CH8_DATA_MASK_SFT                             (0xffffffff << 0)
-
-/* AFE_DL_24CH_CH9_MON */
-#define DL_24CH_CH9_DATA_SFT                                  0
-#define DL_24CH_CH9_DATA_MASK                                 0xffffffff
-#define DL_24CH_CH9_DATA_MASK_SFT                             (0xffffffff << 0)
-
-/* AFE_DL_24CH_CH10_MON */
-#define DL_24CH_CH10_DATA_SFT                                 0
-#define DL_24CH_CH10_DATA_MASK                                0xffffffff
-#define DL_24CH_CH10_DATA_MASK_SFT                            (0xffffffff << 0)
-
-/* AFE_DL_24CH_CH11_MON */
-#define DL_24CH_CH11_DATA_SFT                                 0
-#define DL_24CH_CH11_DATA_MASK                                0xffffffff
-#define DL_24CH_CH11_DATA_MASK_SFT                            (0xffffffff << 0)
-
-/* AFE_DL_24CH_CH12_MON */
-#define DL_24CH_CH12_DATA_SFT                                 0
-#define DL_24CH_CH12_DATA_MASK                                0xffffffff
-#define DL_24CH_CH12_DATA_MASK_SFT                            (0xffffffff << 0)
-
-/* AFE_DL_24CH_CH13_MON */
-#define DL_24CH_CH13_DATA_SFT                                 0
-#define DL_24CH_CH13_DATA_MASK                                0xffffffff
-#define DL_24CH_CH13_DATA_MASK_SFT                            (0xffffffff << 0)
-
-/* AFE_DL_24CH_CH14_MON */
-#define DL_24CH_CH14_DATA_SFT                                 0
-#define DL_24CH_CH14_DATA_MASK                                0xffffffff
-#define DL_24CH_CH14_DATA_MASK_SFT                            (0xffffffff << 0)
-
-/* AFE_DL_24CH_CH15_MON */
-#define DL_24CH_CH15_DATA_SFT                                 0
-#define DL_24CH_CH15_DATA_MASK                                0xffffffff
-#define DL_24CH_CH15_DATA_MASK_SFT                            (0xffffffff << 0)
-
-#define AUDIO_TOP_CON0                       0x0
-#define AUDIO_TOP_CON1                       0x4
-#define AUDIO_TOP_CON2                       0x8
-#define AUDIO_TOP_CON3                       0xc
-#define AUDIO_TOP_CON4                       0x10
-#define AUDIO_ENGEN_CON0                     0x14
-#define AUDIO_ENGEN_CON0_USER1               0x18
-#define AUDIO_ENGEN_CON0_USER2               0x1c
-#define AFE_SINEGEN_CON0                     0x20
-#define AFE_SINEGEN_CON1                     0x24
-#define AFE_SINEGEN_CON2                     0x28
-#define AFE_SINEGEN_CON3                     0x2c
-#define AFE_APLL1_TUNER_CFG                  0x30
-#define AFE_APLL1_TUNER_MON0                 0x34
-#define AFE_APLL2_TUNER_CFG                  0x38
-#define AFE_APLL2_TUNER_MON0                 0x3c
-#define AUDIO_TOP_RG0                        0x4c
-#define AUDIO_TOP_RG1                        0x50
-#define AUDIO_TOP_RG2                        0x54
-#define AUDIO_TOP_RG3                        0x58
-#define AUDIO_TOP_RG4                        0x5c
-#define AFE_SPM_CONTROL_REQ                  0x60
-#define AFE_SPM_CONTROL_ACK                  0x64
-#define AUD_TOP_CFG_VCORE_RG                 0x68
-#define AUDIO_TOP_IP_VERSION                 0x6c
-#define AUDIO_ENGEN_CON0_MON                 0x7c
-#define AUD_TOP_CFG_VLP_RG                   0x98
-#define AUD_TOP_MON_RG                       0x9c
-#define AUDIO_USE_DEFAULT_DELSEL0            0xa0
-#define AUDIO_USE_DEFAULT_DELSEL1            0xa4
-#define AUDIO_USE_DEFAULT_DELSEL2            0xa8
-#define AFE_CONNSYS_I2S_IPM_VER_MON          0xb0
-#define AFE_CONNSYS_I2S_MON_SEL              0xb4
-#define AFE_CONNSYS_I2S_MON                  0xb8
-#define AFE_CONNSYS_I2S_CON                  0xbc
-#define AFE_PCM0_INTF_CON0                   0xc0
-#define AFE_PCM0_INTF_CON1                   0xc4
-#define AFE_PCM_INTF_MON                     0xc8
-#define AFE_PCM1_INTF_CON0                   0xd0
-#define AFE_PCM1_INTF_CON1                   0xd4
-#define AFE_PCM_TOP_IP_VERSION               0xe8
-#define AFE_IRQ_MCU_EN                       0x100
-#define AFE_IRQ_MCU_DSP_EN                   0x104
-#define AFE_IRQ_MCU_DSP2_EN                  0x108
-#define AFE_IRQ_MCU_SCP_EN                   0x10c
-#define AFE_CUSTOM_IRQ_MCU_EN                0x110
-#define AFE_CUSTOM_IRQ_MCU_DSP_EN            0x114
-#define AFE_CUSTOM_IRQ_MCU_DSP2_EN           0x118
-#define AFE_CUSTOM_IRQ_MCU_SCP_EN            0x11c
-#define AFE_IRQ_MCU_STATUS                   0x120
-#define AFE_CUSTOM_IRQ_MCU_STATUS            0x124
-#define AFE_IRQ0_MCU_CFG0                    0x140
-#define AFE_IRQ0_MCU_CFG1                    0x144
-#define AFE_IRQ1_MCU_CFG0                    0x148
-#define AFE_IRQ1_MCU_CFG1                    0x14c
-#define AFE_IRQ2_MCU_CFG0                    0x150
-#define AFE_IRQ2_MCU_CFG1                    0x154
-#define AFE_IRQ3_MCU_CFG0                    0x158
-#define AFE_IRQ3_MCU_CFG1                    0x15c
-#define AFE_IRQ4_MCU_CFG0                    0x160
-#define AFE_IRQ4_MCU_CFG1                    0x164
-#define AFE_IRQ5_MCU_CFG0                    0x168
-#define AFE_IRQ5_MCU_CFG1                    0x16c
-#define AFE_IRQ6_MCU_CFG0                    0x170
-#define AFE_IRQ6_MCU_CFG1                    0x174
-#define AFE_IRQ7_MCU_CFG0                    0x178
-#define AFE_IRQ7_MCU_CFG1                    0x17c
-#define AFE_IRQ8_MCU_CFG0                    0x180
-#define AFE_IRQ8_MCU_CFG1                    0x184
-#define AFE_IRQ9_MCU_CFG0                    0x188
-#define AFE_IRQ9_MCU_CFG1                    0x18c
-#define AFE_IRQ10_MCU_CFG0                   0x190
-#define AFE_IRQ10_MCU_CFG1                   0x194
-#define AFE_IRQ11_MCU_CFG0                   0x198
-#define AFE_IRQ11_MCU_CFG1                   0x19c
-#define AFE_IRQ12_MCU_CFG0                   0x1a0
-#define AFE_IRQ12_MCU_CFG1                   0x1a4
-#define AFE_IRQ13_MCU_CFG0                   0x1a8
-#define AFE_IRQ13_MCU_CFG1                   0x1ac
-#define AFE_IRQ14_MCU_CFG0                   0x1b0
-#define AFE_IRQ14_MCU_CFG1                   0x1b4
-#define AFE_IRQ15_MCU_CFG0                   0x1b8
-#define AFE_IRQ15_MCU_CFG1                   0x1bc
-#define AFE_IRQ16_MCU_CFG0                   0x1c0
-#define AFE_IRQ16_MCU_CFG1                   0x1c4
-#define AFE_IRQ17_MCU_CFG0                   0x1c8
-#define AFE_IRQ17_MCU_CFG1                   0x1cc
-#define AFE_IRQ18_MCU_CFG0                   0x1d0
-#define AFE_IRQ18_MCU_CFG1                   0x1d4
-#define AFE_IRQ19_MCU_CFG0                   0x1d8
-#define AFE_IRQ19_MCU_CFG1                   0x1dc
-#define AFE_IRQ20_MCU_CFG0                   0x1e0
-#define AFE_IRQ20_MCU_CFG1                   0x1e4
-#define AFE_IRQ21_MCU_CFG0                   0x1e8
-#define AFE_IRQ21_MCU_CFG1                   0x1ec
-#define AFE_IRQ22_MCU_CFG0                   0x1f0
-#define AFE_IRQ22_MCU_CFG1                   0x1f4
-#define AFE_IRQ23_MCU_CFG0                   0x1f8
-#define AFE_IRQ23_MCU_CFG1                   0x1fc
-#define AFE_IRQ24_MCU_CFG0                   0x200
-#define AFE_IRQ24_MCU_CFG1                   0x204
-#define AFE_IRQ25_MCU_CFG0                   0x208
-#define AFE_IRQ25_MCU_CFG1                   0x20c
-#define AFE_IRQ26_MCU_CFG0                   0x210
-#define AFE_IRQ26_MCU_CFG1                   0x214
-#define AFE_CUSTOM_IRQ0_MCU_CFG0             0x268
-#define AFE_IRQ_MCU_MON0                     0x300
-#define AFE_IRQ_MCU_MON1                     0x304
-#define AFE_IRQ_MCU_MON2                     0x308
-#define AFE_IRQ0_CNT_MON                     0x310
-#define AFE_IRQ1_CNT_MON                     0x314
-#define AFE_IRQ2_CNT_MON                     0x318
-#define AFE_IRQ3_CNT_MON                     0x31c
-#define AFE_IRQ4_CNT_MON                     0x320
-#define AFE_IRQ5_CNT_MON                     0x324
-#define AFE_IRQ6_CNT_MON                     0x328
-#define AFE_IRQ7_CNT_MON                     0x32c
-#define AFE_IRQ8_CNT_MON                     0x330
-#define AFE_IRQ9_CNT_MON                     0x334
-#define AFE_IRQ10_CNT_MON                    0x338
-#define AFE_IRQ11_CNT_MON                    0x33c
-#define AFE_IRQ12_CNT_MON                    0x340
-#define AFE_IRQ13_CNT_MON                    0x344
-#define AFE_IRQ14_CNT_MON                    0x348
-#define AFE_IRQ15_CNT_MON                    0x34c
-#define AFE_IRQ16_CNT_MON                    0x350
-#define AFE_IRQ17_CNT_MON                    0x354
-#define AFE_IRQ18_CNT_MON                    0x358
-#define AFE_IRQ19_CNT_MON                    0x35c
-#define AFE_IRQ20_CNT_MON                    0x360
-#define AFE_IRQ21_CNT_MON                    0x364
-#define AFE_IRQ22_CNT_MON                    0x368
-#define AFE_IRQ23_CNT_MON                    0x36c
-#define AFE_IRQ24_CNT_MON                    0x370
-#define AFE_IRQ25_CNT_MON                    0x374
-#define AFE_IRQ26_CNT_MON                    0x378
-#define AFE_CUSTOM_IRQ0_CNT_MON              0x390
-#define AFE_CUSTOM_IRQ0_MCU_CFG1             0x3dc
-#define AFE_GAIN0_CON0                       0x400
-#define AFE_GAIN0_CON1_R                     0x404
-#define AFE_GAIN0_CON1_L                     0x408
-#define AFE_GAIN0_CON2                       0x40c
-#define AFE_GAIN0_CON3                       0x410
-#define AFE_GAIN0_CUR_R                      0x414
-#define AFE_GAIN0_CUR_L                      0x418
-#define AFE_GAIN1_CON0                       0x41c
-#define AFE_GAIN1_CON1_R                     0x420
-#define AFE_GAIN1_CON1_L                     0x424
-#define AFE_GAIN1_CON2                       0x428
-#define AFE_GAIN1_CON3                       0x42c
-#define AFE_GAIN1_CUR_R                      0x430
-#define AFE_GAIN1_CUR_L                      0x434
-#define AFE_GAIN2_CON0                       0x438
-#define AFE_GAIN2_CON1_R                     0x43c
-#define AFE_GAIN2_CON1_L                     0x440
-#define AFE_GAIN2_CON2                       0x444
-#define AFE_GAIN2_CON3                       0x448
-#define AFE_GAIN2_CUR_R                      0x44c
-#define AFE_GAIN2_CUR_L                      0x450
-#define AFE_GAIN3_CON0                       0x454
-#define AFE_GAIN3_CON1_R                     0x458
-#define AFE_GAIN3_CON1_L                     0x45c
-#define AFE_GAIN3_CON2                       0x460
-#define AFE_GAIN3_CON3                       0x464
-#define AFE_GAIN3_CUR_R                      0x468
-#define AFE_GAIN3_CUR_L                      0x46c
-#define AFE_STF_CON0                         0xb80
-#define AFE_STF_CON1                         0xb84
-#define AFE_STF_COEFF                        0xb88
-#define AFE_STF_GAIN                         0xb8c
-#define AFE_STF_MON                          0xb90
-#define AFE_STF_IP_VERSION                   0xb94
-#define AFE_CM0_CON0                         0xba0
-#define AFE_CM0_MON                          0xba4
-#define AFE_CM0_IP_VERSION                   0xba8
-#define AFE_CM1_CON0                         0xbb0
-#define AFE_CM1_MON                          0xbb4
-#define AFE_CM1_IP_VERSION                   0xbb8
-#define AFE_CM2_CON0                         0xbc0
-#define AFE_CM2_MON                          0xbc4
-#define AFE_CM2_IP_VERSION                   0xbc8
-#define AFE_ADDA_UL0_SRC_CON0                0xbd0
-#define AFE_ADDA_UL0_SRC_CON1                0xbd4
-#define AFE_ADDA_UL0_SRC_CON2                0xbd8
-#define AFE_ADDA_UL0_SRC_DEBUG               0xbdc
-#define AFE_ADDA_UL0_SRC_DEBUG_MON0          0xbe0
-#define AFE_ADDA_UL0_SRC_MON0                0xbe4
-#define AFE_ADDA_UL0_SRC_MON1                0xbe8
-#define AFE_ADDA_UL0_IIR_COEF_02_01          0xbec
-#define AFE_ADDA_UL0_IIR_COEF_04_03          0xbf0
-#define AFE_ADDA_UL0_IIR_COEF_06_05          0xbf4
-#define AFE_ADDA_UL0_IIR_COEF_08_07          0xbf8
-#define AFE_ADDA_UL0_IIR_COEF_10_09          0xbfc
-#define AFE_ADDA_UL0_ULCF_CFG_02_01          0xc00
-#define AFE_ADDA_UL0_ULCF_CFG_04_03          0xc04
-#define AFE_ADDA_UL0_ULCF_CFG_06_05          0xc08
-#define AFE_ADDA_UL0_ULCF_CFG_08_07          0xc0c
-#define AFE_ADDA_UL0_ULCF_CFG_10_09          0xc10
-#define AFE_ADDA_UL0_ULCF_CFG_12_11          0xc14
-#define AFE_ADDA_UL0_ULCF_CFG_14_13          0xc18
-#define AFE_ADDA_UL0_ULCF_CFG_16_15          0xc1c
-#define AFE_ADDA_UL0_ULCF_CFG_18_17          0xc20
-#define AFE_ADDA_UL0_ULCF_CFG_20_19          0xc24
-#define AFE_ADDA_UL0_ULCF_CFG_22_21          0xc28
-#define AFE_ADDA_UL0_ULCF_CFG_24_23          0xc2c
-#define AFE_ADDA_UL0_ULCF_CFG_26_25          0xc30
-#define AFE_ADDA_UL0_ULCF_CFG_28_27          0xc34
-#define AFE_ADDA_UL0_ULCF_CFG_30_29          0xc38
-#define AFE_ADDA_UL0_ULCF_CFG_32_31          0xc3c
-#define AFE_ADDA_UL0_IP_VERSION              0xc4c
-#define AFE_ADDA_UL1_SRC_CON0                0xc50
-#define AFE_ADDA_UL1_SRC_CON1                0xc54
-#define AFE_ADDA_UL1_SRC_CON2                0xc58
-#define AFE_ADDA_UL1_SRC_DEBUG               0xc5c
-#define AFE_ADDA_UL1_SRC_DEBUG_MON0          0xc60
-#define AFE_ADDA_UL1_SRC_MON0                0xc64
-#define AFE_ADDA_UL1_SRC_MON1                0xc68
-#define AFE_ADDA_UL1_IIR_COEF_02_01          0xc6c
-#define AFE_ADDA_UL1_IIR_COEF_04_03          0xc70
-#define AFE_ADDA_UL1_IIR_COEF_06_05          0xc74
-#define AFE_ADDA_UL1_IIR_COEF_08_07          0xc78
-#define AFE_ADDA_UL1_IIR_COEF_10_09          0xc7c
-#define AFE_ADDA_UL1_ULCF_CFG_02_01          0xc80
-#define AFE_ADDA_UL1_ULCF_CFG_04_03          0xc84
-#define AFE_ADDA_UL1_ULCF_CFG_06_05          0xc88
-#define AFE_ADDA_UL1_ULCF_CFG_08_07          0xc8c
-#define AFE_ADDA_UL1_ULCF_CFG_10_09          0xc90
-#define AFE_ADDA_UL1_ULCF_CFG_12_11          0xc94
-#define AFE_ADDA_UL1_ULCF_CFG_14_13          0xc98
-#define AFE_ADDA_UL1_ULCF_CFG_16_15          0xc9c
-#define AFE_ADDA_UL1_ULCF_CFG_18_17          0xca0
-#define AFE_ADDA_UL1_ULCF_CFG_20_19          0xca4
-#define AFE_ADDA_UL1_ULCF_CFG_22_21          0xca8
-#define AFE_ADDA_UL1_ULCF_CFG_24_23          0xcac
-#define AFE_ADDA_UL1_ULCF_CFG_26_25          0xcb0
-#define AFE_ADDA_UL1_ULCF_CFG_28_27          0xcb4
-#define AFE_ADDA_UL1_ULCF_CFG_30_29          0xcb8
-#define AFE_ADDA_UL1_ULCF_CFG_32_31          0xcbc
-#define AFE_ADDA_UL1_IP_VERSION              0xccc
-#define AFE_ADDA_UL2_SRC_CON0                0xcd0
-#define AFE_ADDA_UL2_SRC_CON1                0xcd4
-#define AFE_ADDA_UL2_SRC_CON2                0xcd8
-#define AFE_ADDA_UL2_SRC_DEBUG               0xcdc
-#define AFE_ADDA_UL2_SRC_DEBUG_MON0          0xce0
-#define AFE_ADDA_UL2_SRC_MON0                0xce4
-#define AFE_ADDA_UL2_SRC_MON1                0xce8
-#define AFE_ADDA_UL2_IIR_COEF_02_01          0xcec
-#define AFE_ADDA_UL2_IIR_COEF_04_03          0xcf0
-#define AFE_ADDA_UL2_IIR_COEF_06_05          0xcf4
-#define AFE_ADDA_UL2_IIR_COEF_08_07          0xcf8
-#define AFE_ADDA_UL2_IIR_COEF_10_09          0xcfc
-#define AFE_ADDA_UL2_ULCF_CFG_02_01          0xd00
-#define AFE_ADDA_UL2_ULCF_CFG_04_03          0xd04
-#define AFE_ADDA_UL2_ULCF_CFG_06_05          0xd08
-#define AFE_ADDA_UL2_ULCF_CFG_08_07          0xd0c
-#define AFE_ADDA_UL2_ULCF_CFG_10_09          0xd10
-#define AFE_ADDA_UL2_ULCF_CFG_12_11          0xd14
-#define AFE_ADDA_UL2_ULCF_CFG_14_13          0xd18
-#define AFE_ADDA_UL2_ULCF_CFG_16_15          0xd1c
-#define AFE_ADDA_UL2_ULCF_CFG_18_17          0xd20
-#define AFE_ADDA_UL2_ULCF_CFG_20_19          0xd24
-#define AFE_ADDA_UL2_ULCF_CFG_22_21          0xd28
-#define AFE_ADDA_UL2_ULCF_CFG_24_23          0xd2c
-#define AFE_ADDA_UL2_ULCF_CFG_26_25          0xd30
-#define AFE_ADDA_UL2_ULCF_CFG_28_27          0xd34
-#define AFE_ADDA_UL2_ULCF_CFG_30_29          0xd38
-#define AFE_ADDA_UL2_ULCF_CFG_32_31          0xd3c
-#define AFE_ADDA_UL2_IP_VERSION              0xd4c
-#define AFE_ADDA_PROXIMITY_CON0              0xed0
-#define AFE_ADDA_ULSRC_PHASE_CON0            0xf00
-#define AFE_ADDA_ULSRC_PHASE_CON1            0xf04
-#define AFE_ADDA_ULSRC_PHASE_CON2            0xf08
-#define AFE_ADDA_ULSRC_PHASE_CON3            0xf0c
-#define AFE_MTKAIF_IPM_VER_MON               0x1180
-#define AFE_MTKAIF_MON_SEL                   0x1184
-#define AFE_MTKAIF_MON                       0x1188
-#define AFE_MTKAIF0_CFG0                     0x1190
-#define AFE_MTKAIF0_TX_CFG0                  0x1194
-#define AFE_MTKAIF0_RX_CFG0                  0x1198
-#define AFE_MTKAIF0_RX_CFG1                  0x119c
-#define AFE_MTKAIF0_RX_CFG2                  0x11a0
-#define AFE_MTKAIF1_CFG0                     0x11f0
-#define AFE_MTKAIF1_TX_CFG0                  0x11f4
-#define AFE_MTKAIF1_RX_CFG0                  0x11f8
-#define AFE_MTKAIF1_RX_CFG1                  0x11fc
-#define AFE_MTKAIF1_RX_CFG2                  0x1200
-#define AFE_AUD_PAD_TOP_CFG0                 0x1204
-#define AFE_AUD_PAD_TOP_MON                  0x1208
-#define AFE_ADDA_MTKAIFV4_TX_CFG0            0x1280
-#define AFE_ADDA6_MTKAIFV4_TX_CFG0           0x1284
-#define AFE_ADDA_MTKAIFV4_RX_CFG0            0x1288
-#define AFE_ADDA_MTKAIFV4_RX_CFG1            0x128c
-#define AFE_ADDA6_MTKAIFV4_RX_CFG0           0x1290
-#define AFE_ADDA6_MTKAIFV4_RX_CFG1           0x1294
-#define AFE_ADDA_MTKAIFV4_TX_SYNCWORD_CFG    0x1298
-#define AFE_ADDA_MTKAIFV4_RX_SYNCWORD_CFG    0x129c
-#define AFE_ADDA_MTKAIFV4_MON0               0x12a0
-#define AFE_ADDA_MTKAIFV4_MON1               0x12a4
-#define AFE_ADDA6_MTKAIFV4_MON0              0x12a8
-#define ETDM_IN0_CON0                        0x1300
-#define ETDM_IN0_CON1                        0x1304
-#define ETDM_IN0_CON2                        0x1308
-#define ETDM_IN0_CON3                        0x130c
-#define ETDM_IN0_CON4                        0x1310
-#define ETDM_IN0_CON5                        0x1314
-#define ETDM_IN0_CON6                        0x1318
-#define ETDM_IN0_CON7                        0x131c
-#define ETDM_IN0_CON8                        0x1320
-#define ETDM_IN0_CON9                        0x1324
-#define ETDM_IN0_MON                         0x1328
-#define ETDM_IN1_CON0                        0x1330
-#define ETDM_IN1_CON1                        0x1334
-#define ETDM_IN1_CON2                        0x1338
-#define ETDM_IN1_CON3                        0x133c
-#define ETDM_IN1_CON4                        0x1340
-#define ETDM_IN1_CON5                        0x1344
-#define ETDM_IN1_CON6                        0x1348
-#define ETDM_IN1_CON7                        0x134c
-#define ETDM_IN1_CON8                        0x1350
-#define ETDM_IN1_CON9                        0x1354
-#define ETDM_IN1_MON                         0x1358
-#define ETDM_IN2_CON0                        0x1360
-#define ETDM_IN2_CON1                        0x1364
-#define ETDM_IN2_CON2                        0x1368
-#define ETDM_IN2_CON3                        0x136c
-#define ETDM_IN2_CON4                        0x1370
-#define ETDM_IN2_CON5                        0x1374
-#define ETDM_IN2_CON6                        0x1378
-#define ETDM_IN2_CON7                        0x137c
-#define ETDM_IN2_CON8                        0x1380
-#define ETDM_IN2_CON9                        0x1384
-#define ETDM_IN2_MON                         0x1388
-#define ETDM_IN3_CON0                        0x1390
-#define ETDM_IN3_CON1                        0x1394
-#define ETDM_IN3_CON2                        0x1398
-#define ETDM_IN3_CON3                        0x139c
-#define ETDM_IN3_CON4                        0x13a0
-#define ETDM_IN3_CON5                        0x13a4
-#define ETDM_IN3_CON6                        0x13a8
-#define ETDM_IN3_CON7                        0x13ac
-#define ETDM_IN3_CON8                        0x13b0
-#define ETDM_IN3_CON9                        0x13b4
-#define ETDM_IN3_MON                         0x13b8
-#define ETDM_IN4_CON0                        0x13c0
-#define ETDM_IN4_CON1                        0x13c4
-#define ETDM_IN4_CON2                        0x13c8
-#define ETDM_IN4_CON3                        0x13cc
-#define ETDM_IN4_CON4                        0x13d0
-#define ETDM_IN4_CON5                        0x13d4
-#define ETDM_IN4_CON6                        0x13d8
-#define ETDM_IN4_CON7                        0x13dc
-#define ETDM_IN4_CON8                        0x13e0
-#define ETDM_IN4_CON9                        0x13e4
-#define ETDM_IN4_MON                         0x13e8
-#define ETDM_IN5_CON0                        0x13f0
-#define ETDM_IN5_CON1                        0x13f4
-#define ETDM_IN5_CON2                        0x13f8
-#define ETDM_IN5_CON3                        0x13fc
-#define ETDM_IN5_CON4                        0x1400
-#define ETDM_IN5_CON5                        0x1404
-#define ETDM_IN5_CON6                        0x1408
-#define ETDM_IN5_CON7                        0x140c
-#define ETDM_IN5_CON8                        0x1410
-#define ETDM_IN5_CON9                        0x1414
-#define ETDM_IN5_MON                         0x1418
-#define ETDM_IN6_CON0                        0x1420
-#define ETDM_IN6_CON1                        0x1424
-#define ETDM_IN6_CON2                        0x1428
-#define ETDM_IN6_CON3                        0x142c
-#define ETDM_IN6_CON4                        0x1430
-#define ETDM_IN6_CON5                        0x1434
-#define ETDM_IN6_CON6                        0x1438
-#define ETDM_IN6_CON7                        0x143c
-#define ETDM_IN6_CON8                        0x1440
-#define ETDM_IN6_CON9                        0x1444
-#define ETDM_IN6_MON                         0x1448
-#define ETDM_OUT0_CON0                       0x1480
-#define ETDM_OUT0_CON1                       0x1484
-#define ETDM_OUT0_CON2                       0x1488
-#define ETDM_OUT0_CON3                       0x148c
-#define ETDM_OUT0_CON4                       0x1490
-#define ETDM_OUT0_CON5                       0x1494
-#define ETDM_OUT0_CON6                       0x1498
-#define ETDM_OUT0_CON7                       0x149c
-#define ETDM_OUT0_CON8                       0x14a0
-#define ETDM_OUT0_CON9                       0x14a4
-#define ETDM_OUT0_MON                        0x14a8
-#define ETDM_OUT1_CON0                       0x14c0
-#define ETDM_OUT1_CON1                       0x14c4
-#define ETDM_OUT1_CON2                       0x14c8
-#define ETDM_OUT1_CON3                       0x14cc
-#define ETDM_OUT1_CON4                       0x14d0
-#define ETDM_OUT1_CON5                       0x14d4
-#define ETDM_OUT1_CON6                       0x14d8
-#define ETDM_OUT1_CON7                       0x14dc
-#define ETDM_OUT1_CON8                       0x14e0
-#define ETDM_OUT1_CON9                       0x14e4
-#define ETDM_OUT1_MON                        0x14e8
-#define ETDM_OUT2_CON0                       0x1500
-#define ETDM_OUT2_CON1                       0x1504
-#define ETDM_OUT2_CON2                       0x1508
-#define ETDM_OUT2_CON3                       0x150c
-#define ETDM_OUT2_CON4                       0x1510
-#define ETDM_OUT2_CON5                       0x1514
-#define ETDM_OUT2_CON6                       0x1518
-#define ETDM_OUT2_CON7                       0x151c
-#define ETDM_OUT2_CON8                       0x1520
-#define ETDM_OUT2_CON9                       0x1524
-#define ETDM_OUT2_MON                        0x1528
-#define ETDM_OUT3_CON0                       0x1540
-#define ETDM_OUT3_CON1                       0x1544
-#define ETDM_OUT3_CON2                       0x1548
-#define ETDM_OUT3_CON3                       0x154c
-#define ETDM_OUT3_CON4                       0x1550
-#define ETDM_OUT3_CON5                       0x1554
-#define ETDM_OUT3_CON6                       0x1558
-#define ETDM_OUT3_CON7                       0x155c
-#define ETDM_OUT3_CON8                       0x1560
-#define ETDM_OUT3_CON9                       0x1564
-#define ETDM_OUT3_MON                        0x1568
-#define ETDM_OUT4_CON0                       0x1580
-#define ETDM_OUT4_CON1                       0x1584
-#define ETDM_OUT4_CON2                       0x1588
-#define ETDM_OUT4_CON3                       0x158c
-#define ETDM_OUT4_CON4                       0x1590
-#define ETDM_OUT4_CON5                       0x1594
-#define ETDM_OUT4_CON6                       0x1598
-#define ETDM_OUT4_CON7                       0x159c
-#define ETDM_OUT4_CON8                       0x15a0
-#define ETDM_OUT4_CON9                       0x15a4
-#define ETDM_OUT4_MON                        0x15a8
-#define ETDM_OUT5_CON0                       0x15c0
-#define ETDM_OUT5_CON1                       0x15c4
-#define ETDM_OUT5_CON2                       0x15c8
-#define ETDM_OUT5_CON3                       0x15cc
-#define ETDM_OUT5_CON4                       0x15d0
-#define ETDM_OUT5_CON5                       0x15d4
-#define ETDM_OUT5_CON6                       0x15d8
-#define ETDM_OUT5_CON7                       0x15dc
-#define ETDM_OUT5_CON8                       0x15e0
-#define ETDM_OUT5_CON9                       0x15e4
-#define ETDM_OUT5_MON                        0x15e8
-#define ETDM_OUT6_CON0                       0x1600
-#define ETDM_OUT6_CON1                       0x1604
-#define ETDM_OUT6_CON2                       0x1608
-#define ETDM_OUT6_CON3                       0x160c
-#define ETDM_OUT6_CON4                       0x1610
-#define ETDM_OUT6_CON5                       0x1614
-#define ETDM_OUT6_CON6                       0x1618
-#define ETDM_OUT6_CON7                       0x161c
-#define ETDM_OUT6_CON8                       0x1620
-#define ETDM_OUT6_CON9                       0x1624
-#define ETDM_OUT6_MON                        0x1628
-#define ETDM_0_3_COWORK_CON0                 0x1680
-#define ETDM_0_3_COWORK_CON1                 0x1684
-#define ETDM_0_3_COWORK_CON2                 0x1688
-#define ETDM_0_3_COWORK_CON3                 0x168c
-#define ETDM_4_7_COWORK_CON0                 0x1690
-#define ETDM_4_7_COWORK_CON1                 0x1694
-#define ETDM_4_7_COWORK_CON2                 0x1698
-#define ETDM_4_7_COWORK_CON3                 0x169c
-#define AFE_DPTX_CON                         0x2040
-#define AFE_DPTX_MON                         0x2044
-#define AFE_TDM_CON1                         0x2048
-#define AFE_TDM_CON2                         0x204c
-#define AFE_TDM_CON3                         0x2050
-#define AFE_TDM_OUT_MON                      0x2054
-#define AFE_HDMI_CONN0                       0x2078
-#define AFE_TDM_TOP_IP_VERSION               0x207c
-#define AFE_CONN004_0                        0x2100
-#define AFE_CONN004_1                        0x2104
-#define AFE_CONN004_2                        0x2108
-#define AFE_CONN004_4                        0x2110
-#define AFE_CONN004_5                        0x2114
-#define AFE_CONN004_6                        0x2118
-#define AFE_CONN004_7                        0x211c
-#define AFE_CONN005_0                        0x2120
-#define AFE_CONN005_1                        0x2124
-#define AFE_CONN005_2                        0x2128
-#define AFE_CONN005_4                        0x2130
-#define AFE_CONN005_5                        0x2134
-#define AFE_CONN005_6                        0x2138
-#define AFE_CONN005_7                        0x213c
-#define AFE_CONN006_0                        0x2140
-#define AFE_CONN006_1                        0x2144
-#define AFE_CONN006_2                        0x2148
-#define AFE_CONN006_4                        0x2150
-#define AFE_CONN006_5                        0x2154
-#define AFE_CONN006_6                        0x2158
-#define AFE_CONN006_7                        0x215c
-#define AFE_CONN007_0                        0x2160
-#define AFE_CONN007_1                        0x2164
-#define AFE_CONN007_2                        0x2168
-#define AFE_CONN007_4                        0x2170
-#define AFE_CONN007_5                        0x2174
-#define AFE_CONN007_6                        0x2178
-#define AFE_CONN007_7                        0x217c
-#define AFE_CONN008_0                        0x2180
-#define AFE_CONN008_1                        0x2184
-#define AFE_CONN008_2                        0x2188
-#define AFE_CONN008_4                        0x2190
-#define AFE_CONN008_5                        0x2194
-#define AFE_CONN008_6                        0x2198
-#define AFE_CONN008_7                        0x219c
-#define AFE_CONN009_0                        0x21a0
-#define AFE_CONN009_1                        0x21a4
-#define AFE_CONN009_2                        0x21a8
-#define AFE_CONN009_4                        0x21b0
-#define AFE_CONN009_5                        0x21b4
-#define AFE_CONN009_6                        0x21b8
-#define AFE_CONN009_7                        0x21bc
-#define AFE_CONN010_0                        0x21c0
-#define AFE_CONN010_1                        0x21c4
-#define AFE_CONN010_2                        0x21c8
-#define AFE_CONN010_4                        0x21d0
-#define AFE_CONN010_5                        0x21d4
-#define AFE_CONN010_6                        0x21d8
-#define AFE_CONN010_7                        0x21dc
-#define AFE_CONN011_0                        0x21e0
-#define AFE_CONN011_1                        0x21e4
-#define AFE_CONN011_2                        0x21e8
-#define AFE_CONN011_4                        0x21f0
-#define AFE_CONN011_5                        0x21f4
-#define AFE_CONN011_6                        0x21f8
-#define AFE_CONN011_7                        0x21fc
-#define AFE_CONN012_0                        0x2200
-#define AFE_CONN012_1                        0x2204
-#define AFE_CONN012_2                        0x2208
-#define AFE_CONN012_4                        0x2210
-#define AFE_CONN012_5                        0x2214
-#define AFE_CONN012_6                        0x2218
-#define AFE_CONN012_7                        0x221c
-#define AFE_CONN014_0                        0x2240
-#define AFE_CONN014_1                        0x2244
-#define AFE_CONN014_2                        0x2248
-#define AFE_CONN014_4                        0x2250
-#define AFE_CONN014_5                        0x2254
-#define AFE_CONN014_6                        0x2258
-#define AFE_CONN014_7                        0x225c
-#define AFE_CONN015_0                        0x2260
-#define AFE_CONN015_1                        0x2264
-#define AFE_CONN015_2                        0x2268
-#define AFE_CONN015_4                        0x2270
-#define AFE_CONN015_5                        0x2274
-#define AFE_CONN015_6                        0x2278
-#define AFE_CONN015_7                        0x227c
-#define AFE_CONN016_0                        0x2280
-#define AFE_CONN016_1                        0x2284
-#define AFE_CONN016_2                        0x2288
-#define AFE_CONN016_4                        0x2290
-#define AFE_CONN016_5                        0x2294
-#define AFE_CONN016_6                        0x2298
-#define AFE_CONN016_7                        0x229c
-#define AFE_CONN017_0                        0x22a0
-#define AFE_CONN017_1                        0x22a4
-#define AFE_CONN017_2                        0x22a8
-#define AFE_CONN017_4                        0x22b0
-#define AFE_CONN017_5                        0x22b4
-#define AFE_CONN017_6                        0x22b8
-#define AFE_CONN017_7                        0x22bc
-#define AFE_CONN018_0                        0x22c0
-#define AFE_CONN018_1                        0x22c4
-#define AFE_CONN018_2                        0x22c8
-#define AFE_CONN018_4                        0x22d0
-#define AFE_CONN018_5                        0x22d4
-#define AFE_CONN018_6                        0x22d8
-#define AFE_CONN018_7                        0x22dc
-#define AFE_CONN019_0                        0x22e0
-#define AFE_CONN019_1                        0x22e4
-#define AFE_CONN019_2                        0x22e8
-#define AFE_CONN019_4                        0x22f0
-#define AFE_CONN019_5                        0x22f4
-#define AFE_CONN019_6                        0x22f8
-#define AFE_CONN019_7                        0x22fc
-#define AFE_CONN020_0                        0x2300
-#define AFE_CONN020_1                        0x2304
-#define AFE_CONN020_2                        0x2308
-#define AFE_CONN020_4                        0x2310
-#define AFE_CONN020_5                        0x2314
-#define AFE_CONN020_6                        0x2318
-#define AFE_CONN020_7                        0x231c
-#define AFE_CONN021_0                        0x2320
-#define AFE_CONN021_1                        0x2324
-#define AFE_CONN021_2                        0x2328
-#define AFE_CONN021_4                        0x2330
-#define AFE_CONN021_5                        0x2334
-#define AFE_CONN021_6                        0x2338
-#define AFE_CONN021_7                        0x233c
-#define AFE_CONN022_0                        0x2340
-#define AFE_CONN022_1                        0x2344
-#define AFE_CONN022_2                        0x2348
-#define AFE_CONN022_4                        0x2350
-#define AFE_CONN022_5                        0x2354
-#define AFE_CONN022_6                        0x2358
-#define AFE_CONN022_7                        0x235c
-#define AFE_CONN023_0                        0x2360
-#define AFE_CONN023_1                        0x2364
-#define AFE_CONN023_2                        0x2368
-#define AFE_CONN023_4                        0x2370
-#define AFE_CONN023_5                        0x2374
-#define AFE_CONN023_6                        0x2378
-#define AFE_CONN023_7                        0x237c
-#define AFE_CONN024_0                        0x2380
-#define AFE_CONN024_1                        0x2384
-#define AFE_CONN024_2                        0x2388
-#define AFE_CONN024_4                        0x2390
-#define AFE_CONN024_5                        0x2394
-#define AFE_CONN024_6                        0x2398
-#define AFE_CONN024_7                        0x239c
-#define AFE_CONN025_0                        0x23a0
-#define AFE_CONN025_1                        0x23a4
-#define AFE_CONN025_2                        0x23a8
-#define AFE_CONN025_4                        0x23b0
-#define AFE_CONN025_5                        0x23b4
-#define AFE_CONN025_6                        0x23b8
-#define AFE_CONN025_7                        0x23bc
-#define AFE_CONN026_0                        0x23c0
-#define AFE_CONN026_1                        0x23c4
-#define AFE_CONN026_2                        0x23c8
-#define AFE_CONN026_4                        0x23d0
-#define AFE_CONN026_5                        0x23d4
-#define AFE_CONN026_6                        0x23d8
-#define AFE_CONN026_7                        0x23dc
-#define AFE_CONN027_0                        0x23e0
-#define AFE_CONN027_1                        0x23e4
-#define AFE_CONN027_2                        0x23e8
-#define AFE_CONN027_4                        0x23f0
-#define AFE_CONN027_5                        0x23f4
-#define AFE_CONN027_6                        0x23f8
-#define AFE_CONN027_7                        0x23fc
-#define AFE_CONN028_0                        0x2400
-#define AFE_CONN028_1                        0x2404
-#define AFE_CONN028_2                        0x2408
-#define AFE_CONN028_4                        0x2410
-#define AFE_CONN028_5                        0x2414
-#define AFE_CONN028_6                        0x2418
-#define AFE_CONN028_7                        0x241c
-#define AFE_CONN029_0                        0x2420
-#define AFE_CONN029_1                        0x2424
-#define AFE_CONN029_2                        0x2428
-#define AFE_CONN029_4                        0x2430
-#define AFE_CONN029_5                        0x2434
-#define AFE_CONN029_6                        0x2438
-#define AFE_CONN029_7                        0x243c
-#define AFE_CONN030_0                        0x2440
-#define AFE_CONN030_1                        0x2444
-#define AFE_CONN030_2                        0x2448
-#define AFE_CONN030_4                        0x2450
-#define AFE_CONN030_5                        0x2454
-#define AFE_CONN030_6                        0x2458
-#define AFE_CONN030_7                        0x245c
-#define AFE_CONN031_0                        0x2460
-#define AFE_CONN031_1                        0x2464
-#define AFE_CONN031_2                        0x2468
-#define AFE_CONN031_4                        0x2470
-#define AFE_CONN031_5                        0x2474
-#define AFE_CONN031_6                        0x2478
-#define AFE_CONN031_7                        0x247c
-#define AFE_CONN032_0                        0x2480
-#define AFE_CONN032_1                        0x2484
-#define AFE_CONN032_2                        0x2488
-#define AFE_CONN032_4                        0x2490
-#define AFE_CONN032_5                        0x2494
-#define AFE_CONN032_6                        0x2498
-#define AFE_CONN032_7                        0x249c
-#define AFE_CONN033_0                        0x24a0
-#define AFE_CONN033_1                        0x24a4
-#define AFE_CONN033_2                        0x24a8
-#define AFE_CONN033_4                        0x24b0
-#define AFE_CONN033_5                        0x24b4
-#define AFE_CONN033_6                        0x24b8
-#define AFE_CONN033_7                        0x24bc
-#define AFE_CONN034_0                        0x24c0
-#define AFE_CONN034_1                        0x24c4
-#define AFE_CONN034_2                        0x24c8
-#define AFE_CONN034_4                        0x24d0
-#define AFE_CONN034_5                        0x24d4
-#define AFE_CONN034_6                        0x24d8
-#define AFE_CONN034_7                        0x24dc
-#define AFE_CONN035_0                        0x24e0
-#define AFE_CONN035_1                        0x24e4
-#define AFE_CONN035_2                        0x24e8
-#define AFE_CONN035_4                        0x24f0
-#define AFE_CONN035_5                        0x24f4
-#define AFE_CONN035_6                        0x24f8
-#define AFE_CONN035_7                        0x24fc
-#define AFE_CONN036_0                        0x2500
-#define AFE_CONN036_1                        0x2504
-#define AFE_CONN036_2                        0x2508
-#define AFE_CONN036_4                        0x2510
-#define AFE_CONN036_5                        0x2514
-#define AFE_CONN036_6                        0x2518
-#define AFE_CONN036_7                        0x251c
-#define AFE_CONN037_0                        0x2520
-#define AFE_CONN037_1                        0x2524
-#define AFE_CONN037_2                        0x2528
-#define AFE_CONN037_4                        0x2530
-#define AFE_CONN037_5                        0x2534
-#define AFE_CONN037_6                        0x2538
-#define AFE_CONN037_7                        0x253c
-#define AFE_CONN038_0                        0x2540
-#define AFE_CONN038_1                        0x2544
-#define AFE_CONN038_2                        0x2548
-#define AFE_CONN038_4                        0x2550
-#define AFE_CONN038_5                        0x2554
-#define AFE_CONN038_6                        0x2558
-#define AFE_CONN038_7                        0x255c
-#define AFE_CONN039_0                        0x2560
-#define AFE_CONN039_1                        0x2564
-#define AFE_CONN039_2                        0x2568
-#define AFE_CONN039_4                        0x2570
-#define AFE_CONN039_5                        0x2574
-#define AFE_CONN039_6                        0x2578
-#define AFE_CONN039_7                        0x257c
-#define AFE_CONN040_0                        0x2580
-#define AFE_CONN040_1                        0x2584
-#define AFE_CONN040_2                        0x2588
-#define AFE_CONN040_4                        0x2590
-#define AFE_CONN040_5                        0x2594
-#define AFE_CONN040_6                        0x2598
-#define AFE_CONN040_7                        0x259c
-#define AFE_CONN041_0                        0x25a0
-#define AFE_CONN041_1                        0x25a4
-#define AFE_CONN041_2                        0x25a8
-#define AFE_CONN041_4                        0x25b0
-#define AFE_CONN041_5                        0x25b4
-#define AFE_CONN041_6                        0x25b8
-#define AFE_CONN041_7                        0x25bc
-#define AFE_CONN042_0                        0x25c0
-#define AFE_CONN042_1                        0x25c4
-#define AFE_CONN042_2                        0x25c8
-#define AFE_CONN042_4                        0x25d0
-#define AFE_CONN042_5                        0x25d4
-#define AFE_CONN042_6                        0x25d8
-#define AFE_CONN042_7                        0x25dc
-#define AFE_CONN043_0                        0x25e0
-#define AFE_CONN043_1                        0x25e4
-#define AFE_CONN043_2                        0x25e8
-#define AFE_CONN043_4                        0x25f0
-#define AFE_CONN043_5                        0x25f4
-#define AFE_CONN043_6                        0x25f8
-#define AFE_CONN043_7                        0x25fc
-#define AFE_CONN044_0                        0x2600
-#define AFE_CONN044_1                        0x2604
-#define AFE_CONN044_2                        0x2608
-#define AFE_CONN044_4                        0x2610
-#define AFE_CONN044_5                        0x2614
-#define AFE_CONN044_6                        0x2618
-#define AFE_CONN044_7                        0x261c
-#define AFE_CONN045_0                        0x2620
-#define AFE_CONN045_1                        0x2624
-#define AFE_CONN045_2                        0x2628
-#define AFE_CONN045_4                        0x2630
-#define AFE_CONN045_5                        0x2634
-#define AFE_CONN045_6                        0x2638
-#define AFE_CONN045_7                        0x263c
-#define AFE_CONN046_0                        0x2640
-#define AFE_CONN046_1                        0x2644
-#define AFE_CONN046_2                        0x2648
-#define AFE_CONN046_4                        0x2650
-#define AFE_CONN046_5                        0x2654
-#define AFE_CONN046_6                        0x2658
-#define AFE_CONN046_7                        0x265c
-#define AFE_CONN047_0                        0x2660
-#define AFE_CONN047_1                        0x2664
-#define AFE_CONN047_2                        0x2668
-#define AFE_CONN047_4                        0x2670
-#define AFE_CONN047_5                        0x2674
-#define AFE_CONN047_6                        0x2678
-#define AFE_CONN047_7                        0x267c
-#define AFE_CONN048_0                        0x2680
-#define AFE_CONN048_1                        0x2684
-#define AFE_CONN048_2                        0x2688
-#define AFE_CONN048_4                        0x2690
-#define AFE_CONN048_5                        0x2694
-#define AFE_CONN048_6                        0x2698
-#define AFE_CONN048_7                        0x269c
-#define AFE_CONN049_0                        0x26a0
-#define AFE_CONN049_1                        0x26a4
-#define AFE_CONN049_2                        0x26a8
-#define AFE_CONN049_4                        0x26b0
-#define AFE_CONN049_5                        0x26b4
-#define AFE_CONN049_6                        0x26b8
-#define AFE_CONN049_7                        0x26bc
-#define AFE_CONN050_0                        0x26c0
-#define AFE_CONN050_1                        0x26c4
-#define AFE_CONN050_2                        0x26c8
-#define AFE_CONN050_4                        0x26d0
-#define AFE_CONN050_5                        0x26d4
-#define AFE_CONN050_6                        0x26d8
-#define AFE_CONN050_7                        0x26dc
-#define AFE_CONN051_0                        0x26e0
-#define AFE_CONN051_1                        0x26e4
-#define AFE_CONN051_2                        0x26e8
-#define AFE_CONN051_4                        0x26f0
-#define AFE_CONN051_5                        0x26f4
-#define AFE_CONN051_6                        0x26f8
-#define AFE_CONN051_7                        0x26fc
-#define AFE_CONN052_0                        0x2700
-#define AFE_CONN052_1                        0x2704
-#define AFE_CONN052_2                        0x2708
-#define AFE_CONN052_4                        0x2710
-#define AFE_CONN052_5                        0x2714
-#define AFE_CONN052_6                        0x2718
-#define AFE_CONN052_7                        0x271c
-#define AFE_CONN053_0                        0x2720
-#define AFE_CONN053_1                        0x2724
-#define AFE_CONN053_2                        0x2728
-#define AFE_CONN053_4                        0x2730
-#define AFE_CONN053_5                        0x2734
-#define AFE_CONN053_6                        0x2738
-#define AFE_CONN053_7                        0x273c
-#define AFE_CONN054_0                        0x2740
-#define AFE_CONN054_1                        0x2744
-#define AFE_CONN054_2                        0x2748
-#define AFE_CONN054_4                        0x2750
-#define AFE_CONN054_5                        0x2754
-#define AFE_CONN054_6                        0x2758
-#define AFE_CONN054_7                        0x275c
-#define AFE_CONN055_0                        0x2760
-#define AFE_CONN055_1                        0x2764
-#define AFE_CONN055_2                        0x2768
-#define AFE_CONN055_4                        0x2770
-#define AFE_CONN055_5                        0x2774
-#define AFE_CONN055_6                        0x2778
-#define AFE_CONN055_7                        0x277c
-#define AFE_CONN056_0                        0x2780
-#define AFE_CONN056_1                        0x2784
-#define AFE_CONN056_2                        0x2788
-#define AFE_CONN056_4                        0x2790
-#define AFE_CONN056_5                        0x2794
-#define AFE_CONN056_6                        0x2798
-#define AFE_CONN056_7                        0x279c
-#define AFE_CONN057_0                        0x27a0
-#define AFE_CONN057_1                        0x27a4
-#define AFE_CONN057_2                        0x27a8
-#define AFE_CONN057_4                        0x27b0
-#define AFE_CONN057_5                        0x27b4
-#define AFE_CONN057_6                        0x27b8
-#define AFE_CONN057_7                        0x27bc
-#define AFE_CONN058_0                        0x27c0
-#define AFE_CONN058_1                        0x27c4
-#define AFE_CONN058_2                        0x27c8
-#define AFE_CONN058_4                        0x27d0
-#define AFE_CONN058_5                        0x27d4
-#define AFE_CONN058_6                        0x27d8
-#define AFE_CONN058_7                        0x27dc
-#define AFE_CONN059_0                        0x27e0
-#define AFE_CONN059_1                        0x27e4
-#define AFE_CONN059_2                        0x27e8
-#define AFE_CONN059_4                        0x27f0
-#define AFE_CONN059_5                        0x27f4
-#define AFE_CONN059_6                        0x27f8
-#define AFE_CONN059_7                        0x27fc
-#define AFE_CONN060_0                        0x2800
-#define AFE_CONN060_1                        0x2804
-#define AFE_CONN060_2                        0x2808
-#define AFE_CONN060_4                        0x2810
-#define AFE_CONN060_5                        0x2814
-#define AFE_CONN060_6                        0x2818
-#define AFE_CONN060_7                        0x281c
-#define AFE_CONN061_0                        0x2820
-#define AFE_CONN061_1                        0x2824
-#define AFE_CONN061_2                        0x2828
-#define AFE_CONN061_4                        0x2830
-#define AFE_CONN061_5                        0x2834
-#define AFE_CONN061_6                        0x2838
-#define AFE_CONN061_7                        0x283c
-#define AFE_CONN062_0                        0x2840
-#define AFE_CONN062_1                        0x2844
-#define AFE_CONN062_2                        0x2848
-#define AFE_CONN062_4                        0x2850
-#define AFE_CONN062_5                        0x2854
-#define AFE_CONN062_6                        0x2858
-#define AFE_CONN062_7                        0x285c
-#define AFE_CONN063_0                        0x2860
-#define AFE_CONN063_1                        0x2864
-#define AFE_CONN063_2                        0x2868
-#define AFE_CONN063_4                        0x2870
-#define AFE_CONN063_5                        0x2874
-#define AFE_CONN063_6                        0x2878
-#define AFE_CONN063_7                        0x287c
-#define AFE_CONN064_0                        0x2880
-#define AFE_CONN064_1                        0x2884
-#define AFE_CONN064_2                        0x2888
-#define AFE_CONN064_4                        0x2890
-#define AFE_CONN064_5                        0x2894
-#define AFE_CONN064_6                        0x2898
-#define AFE_CONN064_7                        0x289c
-#define AFE_CONN065_0                        0x28a0
-#define AFE_CONN065_1                        0x28a4
-#define AFE_CONN065_2                        0x28a8
-#define AFE_CONN065_4                        0x28b0
-#define AFE_CONN065_5                        0x28b4
-#define AFE_CONN065_6                        0x28b8
-#define AFE_CONN065_7                        0x28bc
-#define AFE_CONN066_0                        0x28c0
-#define AFE_CONN066_1                        0x28c4
-#define AFE_CONN066_2                        0x28c8
-#define AFE_CONN066_4                        0x28d0
-#define AFE_CONN066_5                        0x28d4
-#define AFE_CONN066_6                        0x28d8
-#define AFE_CONN066_7                        0x28dc
-#define AFE_CONN067_0                        0x28e0
-#define AFE_CONN067_1                        0x28e4
-#define AFE_CONN067_2                        0x28e8
-#define AFE_CONN067_4                        0x28f0
-#define AFE_CONN067_5                        0x28f4
-#define AFE_CONN067_6                        0x28f8
-#define AFE_CONN067_7                        0x28fc
-#define AFE_CONN068_0                        0x2900
-#define AFE_CONN068_1                        0x2904
-#define AFE_CONN068_2                        0x2908
-#define AFE_CONN068_4                        0x2910
-#define AFE_CONN068_5                        0x2914
-#define AFE_CONN068_6                        0x2918
-#define AFE_CONN068_7                        0x291c
-#define AFE_CONN069_0                        0x2920
-#define AFE_CONN069_1                        0x2924
-#define AFE_CONN069_2                        0x2928
-#define AFE_CONN069_4                        0x2930
-#define AFE_CONN069_5                        0x2934
-#define AFE_CONN069_6                        0x2938
-#define AFE_CONN069_7                        0x293c
-#define AFE_CONN070_0                        0x2940
-#define AFE_CONN070_1                        0x2944
-#define AFE_CONN070_2                        0x2948
-#define AFE_CONN070_4                        0x2950
-#define AFE_CONN070_5                        0x2954
-#define AFE_CONN070_6                        0x2958
-#define AFE_CONN070_7                        0x295c
-#define AFE_CONN071_0                        0x2960
-#define AFE_CONN071_1                        0x2964
-#define AFE_CONN071_2                        0x2968
-#define AFE_CONN071_4                        0x2970
-#define AFE_CONN071_5                        0x2974
-#define AFE_CONN071_6                        0x2978
-#define AFE_CONN071_7                        0x297c
-#define AFE_CONN072_0                        0x2980
-#define AFE_CONN072_1                        0x2984
-#define AFE_CONN072_2                        0x2988
-#define AFE_CONN072_4                        0x2990
-#define AFE_CONN072_5                        0x2994
-#define AFE_CONN072_6                        0x2998
-#define AFE_CONN072_7                        0x299c
-#define AFE_CONN073_0                        0x29a0
-#define AFE_CONN073_1                        0x29a4
-#define AFE_CONN073_2                        0x29a8
-#define AFE_CONN073_4                        0x29b0
-#define AFE_CONN073_5                        0x29b4
-#define AFE_CONN073_6                        0x29b8
-#define AFE_CONN073_7                        0x29bc
-#define AFE_CONN074_0                        0x29c0
-#define AFE_CONN074_1                        0x29c4
-#define AFE_CONN074_2                        0x29c8
-#define AFE_CONN074_4                        0x29d0
-#define AFE_CONN074_5                        0x29d4
-#define AFE_CONN074_6                        0x29d8
-#define AFE_CONN074_7                        0x29dc
-#define AFE_CONN075_0                        0x29e0
-#define AFE_CONN075_1                        0x29e4
-#define AFE_CONN075_2                        0x29e8
-#define AFE_CONN075_4                        0x29f0
-#define AFE_CONN075_5                        0x29f4
-#define AFE_CONN075_6                        0x29f8
-#define AFE_CONN075_7                        0x29fc
-#define AFE_CONN076_0                        0x2a00
-#define AFE_CONN076_1                        0x2a04
-#define AFE_CONN076_2                        0x2a08
-#define AFE_CONN076_4                        0x2a10
-#define AFE_CONN076_5                        0x2a14
-#define AFE_CONN076_6                        0x2a18
-#define AFE_CONN076_7                        0x2a1c
-#define AFE_CONN077_0                        0x2a20
-#define AFE_CONN077_1                        0x2a24
-#define AFE_CONN077_2                        0x2a28
-#define AFE_CONN077_4                        0x2a30
-#define AFE_CONN077_5                        0x2a34
-#define AFE_CONN077_6                        0x2a38
-#define AFE_CONN077_7                        0x2a3c
-#define AFE_CONN078_0                        0x2a40
-#define AFE_CONN078_1                        0x2a44
-#define AFE_CONN078_2                        0x2a48
-#define AFE_CONN078_4                        0x2a50
-#define AFE_CONN078_5                        0x2a54
-#define AFE_CONN078_6                        0x2a58
-#define AFE_CONN078_7                        0x2a5c
-#define AFE_CONN079_0                        0x2a60
-#define AFE_CONN079_1                        0x2a64
-#define AFE_CONN079_2                        0x2a68
-#define AFE_CONN079_4                        0x2a70
-#define AFE_CONN079_5                        0x2a74
-#define AFE_CONN079_6                        0x2a78
-#define AFE_CONN079_7                        0x2a7c
-#define AFE_CONN080_0                        0x2a80
-#define AFE_CONN080_1                        0x2a84
-#define AFE_CONN080_2                        0x2a88
-#define AFE_CONN080_4                        0x2a90
-#define AFE_CONN080_5                        0x2a94
-#define AFE_CONN080_6                        0x2a98
-#define AFE_CONN080_7                        0x2a9c
-#define AFE_CONN081_0                        0x2aa0
-#define AFE_CONN081_1                        0x2aa4
-#define AFE_CONN081_2                        0x2aa8
-#define AFE_CONN081_4                        0x2ab0
-#define AFE_CONN081_5                        0x2ab4
-#define AFE_CONN081_6                        0x2ab8
-#define AFE_CONN081_7                        0x2abc
-#define AFE_CONN082_0                        0x2ac0
-#define AFE_CONN082_1                        0x2ac4
-#define AFE_CONN082_2                        0x2ac8
-#define AFE_CONN082_4                        0x2ad0
-#define AFE_CONN082_5                        0x2ad4
-#define AFE_CONN082_6                        0x2ad8
-#define AFE_CONN082_7                        0x2adc
-#define AFE_CONN083_0                        0x2ae0
-#define AFE_CONN083_1                        0x2ae4
-#define AFE_CONN083_2                        0x2ae8
-#define AFE_CONN083_4                        0x2af0
-#define AFE_CONN083_5                        0x2af4
-#define AFE_CONN083_6                        0x2af8
-#define AFE_CONN083_7                        0x2afc
-#define AFE_CONN084_0                        0x2b00
-#define AFE_CONN084_1                        0x2b04
-#define AFE_CONN084_2                        0x2b08
-#define AFE_CONN084_4                        0x2b10
-#define AFE_CONN084_5                        0x2b14
-#define AFE_CONN084_6                        0x2b18
-#define AFE_CONN084_7                        0x2b1c
-#define AFE_CONN085_0                        0x2b20
-#define AFE_CONN085_1                        0x2b24
-#define AFE_CONN085_2                        0x2b28
-#define AFE_CONN085_4                        0x2b30
-#define AFE_CONN085_5                        0x2b34
-#define AFE_CONN085_6                        0x2b38
-#define AFE_CONN085_7                        0x2b3c
-#define AFE_CONN086_0                        0x2b40
-#define AFE_CONN086_1                        0x2b44
-#define AFE_CONN086_2                        0x2b48
-#define AFE_CONN086_4                        0x2b50
-#define AFE_CONN086_5                        0x2b54
-#define AFE_CONN086_6                        0x2b58
-#define AFE_CONN086_7                        0x2b5c
-#define AFE_CONN087_0                        0x2b60
-#define AFE_CONN087_1                        0x2b64
-#define AFE_CONN087_2                        0x2b68
-#define AFE_CONN087_4                        0x2b70
-#define AFE_CONN087_5                        0x2b74
-#define AFE_CONN087_6                        0x2b78
-#define AFE_CONN087_7                        0x2b7c
-#define AFE_CONN088_0                        0x2b80
-#define AFE_CONN088_1                        0x2b84
-#define AFE_CONN088_2                        0x2b88
-#define AFE_CONN088_4                        0x2b90
-#define AFE_CONN088_5                        0x2b94
-#define AFE_CONN088_6                        0x2b98
-#define AFE_CONN088_7                        0x2b9c
-#define AFE_CONN089_0                        0x2ba0
-#define AFE_CONN089_1                        0x2ba4
-#define AFE_CONN089_2                        0x2ba8
-#define AFE_CONN089_4                        0x2bb0
-#define AFE_CONN089_5                        0x2bb4
-#define AFE_CONN089_6                        0x2bb8
-#define AFE_CONN089_7                        0x2bbc
-#define AFE_CONN090_0                        0x2bc0
-#define AFE_CONN090_1                        0x2bc4
-#define AFE_CONN090_2                        0x2bc8
-#define AFE_CONN090_4                        0x2bd0
-#define AFE_CONN090_5                        0x2bd4
-#define AFE_CONN090_6                        0x2bd8
-#define AFE_CONN090_7                        0x2bdc
-#define AFE_CONN091_0                        0x2be0
-#define AFE_CONN091_1                        0x2be4
-#define AFE_CONN091_2                        0x2be8
-#define AFE_CONN091_4                        0x2bf0
-#define AFE_CONN091_5                        0x2bf4
-#define AFE_CONN091_6                        0x2bf8
-#define AFE_CONN091_7                        0x2bfc
-#define AFE_CONN092_0                        0x2c00
-#define AFE_CONN092_1                        0x2c04
-#define AFE_CONN092_2                        0x2c08
-#define AFE_CONN092_4                        0x2c10
-#define AFE_CONN092_5                        0x2c14
-#define AFE_CONN092_6                        0x2c18
-#define AFE_CONN092_7                        0x2c1c
-#define AFE_CONN093_0                        0x2c20
-#define AFE_CONN093_1                        0x2c24
-#define AFE_CONN093_2                        0x2c28
-#define AFE_CONN093_4                        0x2c30
-#define AFE_CONN093_5                        0x2c34
-#define AFE_CONN093_6                        0x2c38
-#define AFE_CONN093_7                        0x2c3c
-#define AFE_CONN094_0                        0x2c40
-#define AFE_CONN094_1                        0x2c44
-#define AFE_CONN094_2                        0x2c48
-#define AFE_CONN094_4                        0x2c50
-#define AFE_CONN094_5                        0x2c54
-#define AFE_CONN094_6                        0x2c58
-#define AFE_CONN094_7                        0x2c5c
-#define AFE_CONN095_0                        0x2c60
-#define AFE_CONN095_1                        0x2c64
-#define AFE_CONN095_2                        0x2c68
-#define AFE_CONN095_4                        0x2c70
-#define AFE_CONN095_5                        0x2c74
-#define AFE_CONN095_6                        0x2c78
-#define AFE_CONN095_7                        0x2c7c
-#define AFE_CONN096_0                        0x2c80
-#define AFE_CONN096_1                        0x2c84
-#define AFE_CONN096_2                        0x2c88
-#define AFE_CONN096_4                        0x2c90
-#define AFE_CONN096_5                        0x2c94
-#define AFE_CONN096_6                        0x2c98
-#define AFE_CONN096_7                        0x2c9c
-#define AFE_CONN097_0                        0x2ca0
-#define AFE_CONN097_1                        0x2ca4
-#define AFE_CONN097_2                        0x2ca8
-#define AFE_CONN097_4                        0x2cb0
-#define AFE_CONN097_5                        0x2cb4
-#define AFE_CONN097_6                        0x2cb8
-#define AFE_CONN097_7                        0x2cbc
-#define AFE_CONN098_0                        0x2cc0
-#define AFE_CONN098_1                        0x2cc4
-#define AFE_CONN098_2                        0x2cc8
-#define AFE_CONN098_4                        0x2cd0
-#define AFE_CONN098_5                        0x2cd4
-#define AFE_CONN098_6                        0x2cd8
-#define AFE_CONN098_7                        0x2cdc
-#define AFE_CONN099_0                        0x2ce0
-#define AFE_CONN099_1                        0x2ce4
-#define AFE_CONN099_2                        0x2ce8
-#define AFE_CONN099_4                        0x2cf0
-#define AFE_CONN099_5                        0x2cf4
-#define AFE_CONN099_6                        0x2cf8
-#define AFE_CONN099_7                        0x2cfc
-#define AFE_CONN100_0                        0x2d00
-#define AFE_CONN100_1                        0x2d04
-#define AFE_CONN100_2                        0x2d08
-#define AFE_CONN100_4                        0x2d10
-#define AFE_CONN100_5                        0x2d14
-#define AFE_CONN100_6                        0x2d18
-#define AFE_CONN100_7                        0x2d1c
-#define AFE_CONN102_0                        0x2d40
-#define AFE_CONN102_1                        0x2d44
-#define AFE_CONN102_2                        0x2d48
-#define AFE_CONN102_4                        0x2d50
-#define AFE_CONN102_5                        0x2d54
-#define AFE_CONN102_6                        0x2d58
-#define AFE_CONN102_7                        0x2d5c
-#define AFE_CONN103_0                        0x2d60
-#define AFE_CONN103_1                        0x2d64
-#define AFE_CONN103_2                        0x2d68
-#define AFE_CONN103_4                        0x2d70
-#define AFE_CONN103_5                        0x2d74
-#define AFE_CONN103_6                        0x2d78
-#define AFE_CONN103_7                        0x2d7c
-#define AFE_CONN104_0                        0x2d80
-#define AFE_CONN104_1                        0x2d84
-#define AFE_CONN104_2                        0x2d88
-#define AFE_CONN104_4                        0x2d90
-#define AFE_CONN104_5                        0x2d94
-#define AFE_CONN104_6                        0x2d98
-#define AFE_CONN104_7                        0x2d9c
-#define AFE_CONN105_0                        0x2da0
-#define AFE_CONN105_1                        0x2da4
-#define AFE_CONN105_2                        0x2da8
-#define AFE_CONN105_4                        0x2db0
-#define AFE_CONN105_5                        0x2db4
-#define AFE_CONN105_6                        0x2db8
-#define AFE_CONN105_7                        0x2dbc
-#define AFE_CONN106_0                        0x2dc0
-#define AFE_CONN106_1                        0x2dc4
-#define AFE_CONN106_2                        0x2dc8
-#define AFE_CONN106_4                        0x2dd0
-#define AFE_CONN106_5                        0x2dd4
-#define AFE_CONN106_6                        0x2dd8
-#define AFE_CONN106_7                        0x2ddc
-#define AFE_CONN108_0                        0x2e00
-#define AFE_CONN108_1                        0x2e04
-#define AFE_CONN108_2                        0x2e08
-#define AFE_CONN108_4                        0x2e10
-#define AFE_CONN108_5                        0x2e14
-#define AFE_CONN108_6                        0x2e18
-#define AFE_CONN108_7                        0x2e1c
-#define AFE_CONN109_0                        0x2e20
-#define AFE_CONN109_1                        0x2e24
-#define AFE_CONN109_2                        0x2e28
-#define AFE_CONN109_4                        0x2e30
-#define AFE_CONN109_5                        0x2e34
-#define AFE_CONN109_6                        0x2e38
-#define AFE_CONN109_7                        0x2e3c
-#define AFE_CONN110_0                        0x2e40
-#define AFE_CONN110_1                        0x2e44
-#define AFE_CONN110_2                        0x2e48
-#define AFE_CONN110_4                        0x2e50
-#define AFE_CONN110_5                        0x2e54
-#define AFE_CONN110_6                        0x2e58
-#define AFE_CONN110_7                        0x2e5c
-#define AFE_CONN111_0                        0x2e60
-#define AFE_CONN111_1                        0x2e64
-#define AFE_CONN111_2                        0x2e68
-#define AFE_CONN111_4                        0x2e70
-#define AFE_CONN111_5                        0x2e74
-#define AFE_CONN111_6                        0x2e78
-#define AFE_CONN111_7                        0x2e7c
-#define AFE_CONN112_0                        0x2e80
-#define AFE_CONN112_1                        0x2e84
-#define AFE_CONN112_2                        0x2e88
-#define AFE_CONN112_4                        0x2e90
-#define AFE_CONN112_5                        0x2e94
-#define AFE_CONN112_6                        0x2e98
-#define AFE_CONN112_7                        0x2e9c
-#define AFE_CONN113_0                        0x2ea0
-#define AFE_CONN113_1                        0x2ea4
-#define AFE_CONN113_2                        0x2ea8
-#define AFE_CONN113_4                        0x2eb0
-#define AFE_CONN113_5                        0x2eb4
-#define AFE_CONN113_6                        0x2eb8
-#define AFE_CONN113_7                        0x2ebc
-#define AFE_CONN114_0                        0x2ec0
-#define AFE_CONN114_1                        0x2ec4
-#define AFE_CONN114_2                        0x2ec8
-#define AFE_CONN114_4                        0x2ed0
-#define AFE_CONN114_5                        0x2ed4
-#define AFE_CONN114_6                        0x2ed8
-#define AFE_CONN114_7                        0x2edc
-#define AFE_CONN115_0                        0x2ee0
-#define AFE_CONN115_1                        0x2ee4
-#define AFE_CONN115_2                        0x2ee8
-#define AFE_CONN115_4                        0x2ef0
-#define AFE_CONN115_5                        0x2ef4
-#define AFE_CONN115_6                        0x2ef8
-#define AFE_CONN115_7                        0x2efc
-#define AFE_CONN116_0                        0x2f00
-#define AFE_CONN116_1                        0x2f04
-#define AFE_CONN116_2                        0x2f08
-#define AFE_CONN116_4                        0x2f10
-#define AFE_CONN116_5                        0x2f14
-#define AFE_CONN116_6                        0x2f18
-#define AFE_CONN116_7                        0x2f1c
-#define AFE_CONN117_0                        0x2f20
-#define AFE_CONN117_1                        0x2f24
-#define AFE_CONN117_2                        0x2f28
-#define AFE_CONN117_4                        0x2f30
-#define AFE_CONN117_5                        0x2f34
-#define AFE_CONN117_6                        0x2f38
-#define AFE_CONN117_7                        0x2f3c
-#define AFE_CONN118_0                        0x2f40
-#define AFE_CONN118_1                        0x2f44
-#define AFE_CONN118_2                        0x2f48
-#define AFE_CONN118_4                        0x2f50
-#define AFE_CONN118_5                        0x2f54
-#define AFE_CONN118_6                        0x2f58
-#define AFE_CONN118_7                        0x2f5c
-#define AFE_CONN119_0                        0x2f60
-#define AFE_CONN119_1                        0x2f64
-#define AFE_CONN119_2                        0x2f68
-#define AFE_CONN119_4                        0x2f70
-#define AFE_CONN119_5                        0x2f74
-#define AFE_CONN119_6                        0x2f78
-#define AFE_CONN119_7                        0x2f7c
-#define AFE_CONN120_0                        0x2f80
-#define AFE_CONN120_1                        0x2f84
-#define AFE_CONN120_2                        0x2f88
-#define AFE_CONN120_4                        0x2f90
-#define AFE_CONN120_5                        0x2f94
-#define AFE_CONN120_6                        0x2f98
-#define AFE_CONN120_7                        0x2f9c
-#define AFE_CONN121_0                        0x2fa0
-#define AFE_CONN121_1                        0x2fa4
-#define AFE_CONN121_2                        0x2fa8
-#define AFE_CONN121_4                        0x2fb0
-#define AFE_CONN121_5                        0x2fb4
-#define AFE_CONN121_6                        0x2fb8
-#define AFE_CONN121_7                        0x2fbc
-#define AFE_CONN122_0                        0x2fc0
-#define AFE_CONN122_1                        0x2fc4
-#define AFE_CONN122_2                        0x2fc8
-#define AFE_CONN122_4                        0x2fd0
-#define AFE_CONN122_5                        0x2fd4
-#define AFE_CONN122_6                        0x2fd8
-#define AFE_CONN122_7                        0x2fdc
-#define AFE_CONN123_0                        0x2fe0
-#define AFE_CONN123_1                        0x2fe4
-#define AFE_CONN123_2                        0x2fe8
-#define AFE_CONN123_4                        0x2ff0
-#define AFE_CONN123_5                        0x2ff4
-#define AFE_CONN123_6                        0x2ff8
-#define AFE_CONN123_7                        0x2ffc
-#define AFE_CONN124_0                        0x3000
-#define AFE_CONN124_1                        0x3004
-#define AFE_CONN124_2                        0x3008
-#define AFE_CONN124_4                        0x3010
-#define AFE_CONN124_5                        0x3014
-#define AFE_CONN124_6                        0x3018
-#define AFE_CONN124_7                        0x301c
-#define AFE_CONN125_0                        0x3020
-#define AFE_CONN125_1                        0x3024
-#define AFE_CONN125_2                        0x3028
-#define AFE_CONN125_4                        0x3030
-#define AFE_CONN125_5                        0x3034
-#define AFE_CONN125_6                        0x3038
-#define AFE_CONN125_7                        0x303c
-#define AFE_CONN126_0                        0x3040
-#define AFE_CONN126_1                        0x3044
-#define AFE_CONN126_2                        0x3048
-#define AFE_CONN126_4                        0x3050
-#define AFE_CONN126_5                        0x3054
-#define AFE_CONN126_6                        0x3058
-#define AFE_CONN126_7                        0x305c
-#define AFE_CONN127_0                        0x3060
-#define AFE_CONN127_1                        0x3064
-#define AFE_CONN127_2                        0x3068
-#define AFE_CONN127_4                        0x3070
-#define AFE_CONN127_5                        0x3074
-#define AFE_CONN127_6                        0x3078
-#define AFE_CONN127_7                        0x307c
-#define AFE_CONN128_0                        0x3080
-#define AFE_CONN128_1                        0x3084
-#define AFE_CONN128_2                        0x3088
-#define AFE_CONN128_4                        0x3090
-#define AFE_CONN128_5                        0x3094
-#define AFE_CONN128_6                        0x3098
-#define AFE_CONN128_7                        0x309c
-#define AFE_CONN129_0                        0x30a0
-#define AFE_CONN129_1                        0x30a4
-#define AFE_CONN129_2                        0x30a8
-#define AFE_CONN129_4                        0x30b0
-#define AFE_CONN129_5                        0x30b4
-#define AFE_CONN129_6                        0x30b8
-#define AFE_CONN129_7                        0x30bc
-#define AFE_CONN130_0                        0x30c0
-#define AFE_CONN130_1                        0x30c4
-#define AFE_CONN130_2                        0x30c8
-#define AFE_CONN130_4                        0x30d0
-#define AFE_CONN130_5                        0x30d4
-#define AFE_CONN130_6                        0x30d8
-#define AFE_CONN130_7                        0x30dc
-#define AFE_CONN131_0                        0x30e0
-#define AFE_CONN131_1                        0x30e4
-#define AFE_CONN131_2                        0x30e8
-#define AFE_CONN131_4                        0x30f0
-#define AFE_CONN131_5                        0x30f4
-#define AFE_CONN131_6                        0x30f8
-#define AFE_CONN131_7                        0x30fc
-#define AFE_CONN132_0                        0x3100
-#define AFE_CONN132_1                        0x3104
-#define AFE_CONN132_2                        0x3108
-#define AFE_CONN132_4                        0x3110
-#define AFE_CONN132_5                        0x3114
-#define AFE_CONN132_6                        0x3118
-#define AFE_CONN132_7                        0x311c
-#define AFE_CONN133_0                        0x3120
-#define AFE_CONN133_1                        0x3124
-#define AFE_CONN133_2                        0x3128
-#define AFE_CONN133_4                        0x3130
-#define AFE_CONN133_5                        0x3134
-#define AFE_CONN133_6                        0x3138
-#define AFE_CONN133_7                        0x313c
-#define AFE_CONN134_0                        0x3140
-#define AFE_CONN134_1                        0x3144
-#define AFE_CONN134_2                        0x3148
-#define AFE_CONN134_4                        0x3150
-#define AFE_CONN134_5                        0x3154
-#define AFE_CONN134_6                        0x3158
-#define AFE_CONN134_7                        0x315c
-#define AFE_CONN135_0                        0x3160
-#define AFE_CONN135_1                        0x3164
-#define AFE_CONN135_2                        0x3168
-#define AFE_CONN135_4                        0x3170
-#define AFE_CONN135_5                        0x3174
-#define AFE_CONN135_6                        0x3178
-#define AFE_CONN135_7                        0x317c
-#define AFE_CONN136_0                        0x3180
-#define AFE_CONN136_1                        0x3184
-#define AFE_CONN136_2                        0x3188
-#define AFE_CONN136_4                        0x3190
-#define AFE_CONN136_5                        0x3194
-#define AFE_CONN136_6                        0x3198
-#define AFE_CONN136_7                        0x319c
-#define AFE_CONN137_0                        0x31a0
-#define AFE_CONN137_1                        0x31a4
-#define AFE_CONN137_2                        0x31a8
-#define AFE_CONN137_4                        0x31b0
-#define AFE_CONN137_5                        0x31b4
-#define AFE_CONN137_6                        0x31b8
-#define AFE_CONN137_7                        0x31bc
-#define AFE_CONN138_0                        0x31c0
-#define AFE_CONN138_1                        0x31c4
-#define AFE_CONN138_2                        0x31c8
-#define AFE_CONN138_4                        0x31d0
-#define AFE_CONN138_5                        0x31d4
-#define AFE_CONN138_6                        0x31d8
-#define AFE_CONN138_7                        0x31dc
-#define AFE_CONN139_0                        0x31e0
-#define AFE_CONN139_1                        0x31e4
-#define AFE_CONN139_2                        0x31e8
-#define AFE_CONN139_4                        0x31f0
-#define AFE_CONN139_5                        0x31f4
-#define AFE_CONN139_6                        0x31f8
-#define AFE_CONN139_7                        0x31fc
-#define AFE_CONN148_0                        0x3300
-#define AFE_CONN148_1                        0x3304
-#define AFE_CONN148_2                        0x3308
-#define AFE_CONN148_4                        0x3310
-#define AFE_CONN148_5                        0x3314
-#define AFE_CONN148_6                        0x3318
-#define AFE_CONN148_7                        0x331c
-#define AFE_CONN149_0                        0x3320
-#define AFE_CONN149_1                        0x3324
-#define AFE_CONN149_2                        0x3328
-#define AFE_CONN149_4                        0x3330
-#define AFE_CONN149_5                        0x3334
-#define AFE_CONN149_6                        0x3338
-#define AFE_CONN149_7                        0x333c
-#define AFE_CONN180_0                        0x3700
-#define AFE_CONN180_1                        0x3704
-#define AFE_CONN180_2                        0x3708
-#define AFE_CONN180_4                        0x3710
-#define AFE_CONN180_5                        0x3714
-#define AFE_CONN180_6                        0x3718
-#define AFE_CONN180_7                        0x371c
-#define AFE_CONN181_0                        0x3720
-#define AFE_CONN181_1                        0x3724
-#define AFE_CONN181_2                        0x3728
-#define AFE_CONN181_4                        0x3730
-#define AFE_CONN181_5                        0x3734
-#define AFE_CONN181_6                        0x3738
-#define AFE_CONN181_7                        0x373c
-#define AFE_CONN182_0                        0x3740
-#define AFE_CONN182_1                        0x3744
-#define AFE_CONN182_2                        0x3748
-#define AFE_CONN182_4                        0x3750
-#define AFE_CONN182_5                        0x3754
-#define AFE_CONN182_6                        0x3758
-#define AFE_CONN182_7                        0x375c
-#define AFE_CONN183_0                        0x3760
-#define AFE_CONN183_1                        0x3764
-#define AFE_CONN183_2                        0x3768
-#define AFE_CONN183_4                        0x3770
-#define AFE_CONN183_5                        0x3774
-#define AFE_CONN183_6                        0x3778
-#define AFE_CONN183_7                        0x377c
-#define AFE_CONN184_0                        0x3780
-#define AFE_CONN184_1                        0x3784
-#define AFE_CONN184_2                        0x3788
-#define AFE_CONN184_4                        0x3790
-#define AFE_CONN184_5                        0x3794
-#define AFE_CONN184_6                        0x3798
-#define AFE_CONN184_7                        0x379c
-#define AFE_CONN185_0                        0x37a0
-#define AFE_CONN185_1                        0x37a4
-#define AFE_CONN185_2                        0x37a8
-#define AFE_CONN185_4                        0x37b0
-#define AFE_CONN185_5                        0x37b4
-#define AFE_CONN185_6                        0x37b8
-#define AFE_CONN185_7                        0x37bc
-#define AFE_CONN186_0                        0x37c0
-#define AFE_CONN186_1                        0x37c4
-#define AFE_CONN186_2                        0x37c8
-#define AFE_CONN186_4                        0x37d0
-#define AFE_CONN186_5                        0x37d4
-#define AFE_CONN186_6                        0x37d8
-#define AFE_CONN186_7                        0x37dc
-#define AFE_CONN187_0                        0x37e0
-#define AFE_CONN187_1                        0x37e4
-#define AFE_CONN187_2                        0x37e8
-#define AFE_CONN187_4                        0x37f0
-#define AFE_CONN187_5                        0x37f4
-#define AFE_CONN187_6                        0x37f8
-#define AFE_CONN187_7                        0x37fc
-#define AFE_CONN188_0                        0x3800
-#define AFE_CONN188_1                        0x3804
-#define AFE_CONN188_2                        0x3808
-#define AFE_CONN188_4                        0x3810
-#define AFE_CONN188_5                        0x3814
-#define AFE_CONN188_6                        0x3818
-#define AFE_CONN188_7                        0x381c
-#define AFE_CONN189_0                        0x3820
-#define AFE_CONN189_1                        0x3824
-#define AFE_CONN189_2                        0x3828
-#define AFE_CONN189_4                        0x3830
-#define AFE_CONN189_5                        0x3834
-#define AFE_CONN189_6                        0x3838
-#define AFE_CONN189_7                        0x383c
-#define AFE_CONN190_0                        0x3840
-#define AFE_CONN190_1                        0x3844
-#define AFE_CONN190_2                        0x3848
-#define AFE_CONN190_4                        0x3850
-#define AFE_CONN190_5                        0x3854
-#define AFE_CONN190_6                        0x3858
-#define AFE_CONN190_7                        0x385c
-#define AFE_CONN191_0                        0x3860
-#define AFE_CONN191_1                        0x3864
-#define AFE_CONN191_2                        0x3868
-#define AFE_CONN191_4                        0x3870
-#define AFE_CONN191_5                        0x3874
-#define AFE_CONN191_6                        0x3878
-#define AFE_CONN191_7                        0x387c
-#define AFE_CONN192_0                        0x3880
-#define AFE_CONN192_1                        0x3884
-#define AFE_CONN192_2                        0x3888
-#define AFE_CONN192_4                        0x3890
-#define AFE_CONN192_5                        0x3894
-#define AFE_CONN192_6                        0x3898
-#define AFE_CONN192_7                        0x389c
-#define AFE_CONN193_0                        0x38a0
-#define AFE_CONN193_1                        0x38a4
-#define AFE_CONN193_2                        0x38a8
-#define AFE_CONN193_4                        0x38b0
-#define AFE_CONN193_5                        0x38b4
-#define AFE_CONN193_6                        0x38b8
-#define AFE_CONN193_7                        0x38bc
-#define AFE_CONN194_0                        0x38c0
-#define AFE_CONN194_1                        0x38c4
-#define AFE_CONN194_2                        0x38c8
-#define AFE_CONN194_4                        0x38d0
-#define AFE_CONN194_5                        0x38d4
-#define AFE_CONN194_6                        0x38d8
-#define AFE_CONN194_7                        0x38dc
-#define AFE_CONN195_0                        0x38e0
-#define AFE_CONN195_1                        0x38e4
-#define AFE_CONN195_2                        0x38e8
-#define AFE_CONN195_4                        0x38f0
-#define AFE_CONN195_5                        0x38f4
-#define AFE_CONN195_6                        0x38f8
-#define AFE_CONN195_7                        0x38fc
-#define AFE_CONN196_0                        0x3900
-#define AFE_CONN196_1                        0x3904
-#define AFE_CONN196_2                        0x3908
-#define AFE_CONN196_4                        0x3910
-#define AFE_CONN196_5                        0x3914
-#define AFE_CONN196_6                        0x3918
-#define AFE_CONN196_7                        0x391c
-#define AFE_CONN197_0                        0x3920
-#define AFE_CONN197_1                        0x3924
-#define AFE_CONN197_2                        0x3928
-#define AFE_CONN197_4                        0x3930
-#define AFE_CONN197_5                        0x3934
-#define AFE_CONN197_6                        0x3938
-#define AFE_CONN197_7                        0x393c
-#define AFE_CONN198_0                        0x3940
-#define AFE_CONN198_1                        0x3944
-#define AFE_CONN198_2                        0x3948
-#define AFE_CONN198_4                        0x3950
-#define AFE_CONN198_5                        0x3954
-#define AFE_CONN198_6                        0x3958
-#define AFE_CONN198_7                        0x395c
-#define AFE_CONN199_0                        0x3960
-#define AFE_CONN199_1                        0x3964
-#define AFE_CONN199_2                        0x3968
-#define AFE_CONN199_4                        0x3970
-#define AFE_CONN199_5                        0x3974
-#define AFE_CONN199_6                        0x3978
-#define AFE_CONN199_7                        0x397c
-#define AFE_CONN200_0                        0x3980
-#define AFE_CONN200_1                        0x3984
-#define AFE_CONN200_2                        0x3988
-#define AFE_CONN200_4                        0x3990
-#define AFE_CONN200_5                        0x3994
-#define AFE_CONN200_6                        0x3998
-#define AFE_CONN200_7                        0x399c
-#define AFE_CONN201_0                        0x39a0
-#define AFE_CONN201_1                        0x39a4
-#define AFE_CONN201_2                        0x39a8
-#define AFE_CONN201_4                        0x39b0
-#define AFE_CONN201_5                        0x39b4
-#define AFE_CONN201_6                        0x39b8
-#define AFE_CONN201_7                        0x39bc
-#define AFE_CONN202_0                        0x39c0
-#define AFE_CONN202_1                        0x39c4
-#define AFE_CONN202_2                        0x39c8
-#define AFE_CONN202_4                        0x39d0
-#define AFE_CONN202_5                        0x39d4
-#define AFE_CONN202_6                        0x39d8
-#define AFE_CONN202_7                        0x39dc
-#define AFE_CONN203_0                        0x39e0
-#define AFE_CONN203_1                        0x39e4
-#define AFE_CONN203_2                        0x39e8
-#define AFE_CONN203_4                        0x39f0
-#define AFE_CONN203_5                        0x39f4
-#define AFE_CONN203_6                        0x39f8
-#define AFE_CONN203_7                        0x39fc
-#define AFE_CONN204_0                        0x3a00
-#define AFE_CONN204_1                        0x3a04
-#define AFE_CONN204_2                        0x3a08
-#define AFE_CONN204_4                        0x3a10
-#define AFE_CONN204_5                        0x3a14
-#define AFE_CONN204_6                        0x3a18
-#define AFE_CONN204_7                        0x3a1c
-#define AFE_CONN205_0                        0x3a20
-#define AFE_CONN205_1                        0x3a24
-#define AFE_CONN205_2                        0x3a28
-#define AFE_CONN205_4                        0x3a30
-#define AFE_CONN205_5                        0x3a34
-#define AFE_CONN205_6                        0x3a38
-#define AFE_CONN205_7                        0x3a3c
-#define AFE_CONN206_0                        0x3a40
-#define AFE_CONN206_1                        0x3a44
-#define AFE_CONN206_2                        0x3a48
-#define AFE_CONN206_4                        0x3a50
-#define AFE_CONN206_5                        0x3a54
-#define AFE_CONN206_6                        0x3a58
-#define AFE_CONN206_7                        0x3a5c
-#define AFE_CONN207_0                        0x3a60
-#define AFE_CONN207_1                        0x3a64
-#define AFE_CONN207_2                        0x3a68
-#define AFE_CONN207_4                        0x3a70
-#define AFE_CONN207_5                        0x3a74
-#define AFE_CONN207_6                        0x3a78
-#define AFE_CONN207_7                        0x3a7c
-#define AFE_CONN208_0                        0x3a80
-#define AFE_CONN208_1                        0x3a84
-#define AFE_CONN208_2                        0x3a88
-#define AFE_CONN208_4                        0x3a90
-#define AFE_CONN208_5                        0x3a94
-#define AFE_CONN208_6                        0x3a98
-#define AFE_CONN208_7                        0x3a9c
-#define AFE_CONN209_0                        0x3aa0
-#define AFE_CONN209_1                        0x3aa4
-#define AFE_CONN209_2                        0x3aa8
-#define AFE_CONN209_4                        0x3ab0
-#define AFE_CONN209_5                        0x3ab4
-#define AFE_CONN209_6                        0x3ab8
-#define AFE_CONN209_7                        0x3abc
-#define AFE_CONN210_0                        0x3ac0
-#define AFE_CONN210_1                        0x3ac4
-#define AFE_CONN210_2                        0x3ac8
-#define AFE_CONN210_4                        0x3ad0
-#define AFE_CONN210_5                        0x3ad4
-#define AFE_CONN210_6                        0x3ad8
-#define AFE_CONN210_7                        0x3adc
-#define AFE_CONN211_0                        0x3ae0
-#define AFE_CONN211_1                        0x3ae4
-#define AFE_CONN211_2                        0x3ae8
-#define AFE_CONN211_4                        0x3af0
-#define AFE_CONN211_5                        0x3af4
-#define AFE_CONN211_6                        0x3af8
-#define AFE_CONN211_7                        0x3afc
-#define AFE_CONN_MON_CFG                     0x4080
-#define AFE_CONN_MON0                        0x4084
-#define AFE_CONN_MON1                        0x4088
-#define AFE_CONN_MON2                        0x408c
-#define AFE_CONN_MON3                        0x4090
-#define AFE_CONN_MON4                        0x4094
-#define AFE_CONN_MON5                        0x4098
-#define AFE_CONN_RS_0                        0x40a0
-#define AFE_CONN_RS_1                        0x40a4
-#define AFE_CONN_RS_2                        0x40a8
-#define AFE_CONN_RS_3                        0x40ac
-#define AFE_CONN_RS_4                        0x40b0
-#define AFE_CONN_RS_5                        0x40b4
-#define AFE_CONN_RS_6                        0x40b8
-#define AFE_CONN_DI_0                        0x40c0
-#define AFE_CONN_DI_1                        0x40c4
-#define AFE_CONN_DI_2                        0x40c8
-#define AFE_CONN_DI_3                        0x40cc
-#define AFE_CONN_DI_4                        0x40d0
-#define AFE_CONN_DI_5                        0x40d4
-#define AFE_CONN_DI_6                        0x40d8
-#define AFE_CONN_16BIT_0                     0x40e0
-#define AFE_CONN_16BIT_1                     0x40e4
-#define AFE_CONN_16BIT_2                     0x40e8
-#define AFE_CONN_16BIT_3                     0x40ec
-#define AFE_CONN_16BIT_4                     0x40f0
-#define AFE_CONN_16BIT_5                     0x40f4
-#define AFE_CONN_16BIT_6                     0x40f8
-#define AFE_CONN_24BIT_0                     0x4100
-#define AFE_CONN_24BIT_1                     0x4104
-#define AFE_CONN_24BIT_2                     0x4108
-#define AFE_CONN_24BIT_3                     0x410c
-#define AFE_CONN_24BIT_4                     0x4110
-#define AFE_CONN_24BIT_5                     0x4114
-#define AFE_CONN_24BIT_6                     0x4118
-#define AFE_CBIP_CFG0                        0x4380
-#define AFE_CBIP_SLV_DECODER_MON0            0x4384
-#define AFE_CBIP_SLV_DECODER_MON1            0x4388
-#define AFE_CBIP_SLV_MUX_MON_CFG             0x438c
-#define AFE_CBIP_SLV_MUX_MON0                0x4390
-#define AFE_CBIP_SLV_MUX_MON1                0x4394
-#define AFE_MEMIF_CON0                       0x4400
-#define AFE_MEMIF_ONE_HEART                  0x4420
-#define AFE_DL0_BASE_MSB                     0x4440
-#define AFE_DL0_BASE                         0x4444
-#define AFE_DL0_CUR_MSB                      0x4448
-#define AFE_DL0_CUR                          0x444c
-#define AFE_DL0_END_MSB                      0x4450
-#define AFE_DL0_END                          0x4454
-#define AFE_DL0_RCH_MON                      0x4458
-#define AFE_DL0_LCH_MON                      0x445c
-#define AFE_DL0_CON0                         0x4460
-#define AFE_DL0_MON0                         0x4464
-#define AFE_DL1_BASE_MSB                     0x4470
-#define AFE_DL1_BASE                         0x4474
-#define AFE_DL1_CUR_MSB                      0x4478
-#define AFE_DL1_CUR                          0x447c
-#define AFE_DL1_END_MSB                      0x4480
-#define AFE_DL1_END                          0x4484
-#define AFE_DL1_RCH_MON                      0x4488
-#define AFE_DL1_LCH_MON                      0x448c
-#define AFE_DL1_CON0                         0x4490
-#define AFE_DL1_MON0                         0x4494
-#define AFE_DL2_BASE_MSB                     0x44a0
-#define AFE_DL2_BASE                         0x44a4
-#define AFE_DL2_CUR_MSB                      0x44a8
-#define AFE_DL2_CUR                          0x44ac
-#define AFE_DL2_END_MSB                      0x44b0
-#define AFE_DL2_END                          0x44b4
-#define AFE_DL2_RCH_MON                      0x44b8
-#define AFE_DL2_LCH_MON                      0x44bc
-#define AFE_DL2_CON0                         0x44c0
-#define AFE_DL2_MON0                         0x44c4
-#define AFE_DL3_BASE_MSB                     0x44d0
-#define AFE_DL3_BASE                         0x44d4
-#define AFE_DL3_CUR_MSB                      0x44d8
-#define AFE_DL3_CUR                          0x44dc
-#define AFE_DL3_END_MSB                      0x44e0
-#define AFE_DL3_END                          0x44e4
-#define AFE_DL3_RCH_MON                      0x44e8
-#define AFE_DL3_LCH_MON                      0x44ec
-#define AFE_DL3_CON0                         0x44f0
-#define AFE_DL3_MON0                         0x44f4
-#define AFE_DL4_BASE_MSB                     0x4500
-#define AFE_DL4_BASE                         0x4504
-#define AFE_DL4_CUR_MSB                      0x4508
-#define AFE_DL4_CUR                          0x450c
-#define AFE_DL4_END_MSB                      0x4510
-#define AFE_DL4_END                          0x4514
-#define AFE_DL4_RCH_MON                      0x4518
-#define AFE_DL4_LCH_MON                      0x451c
-#define AFE_DL4_CON0                         0x4520
-#define AFE_DL4_MON0                         0x4524
-#define AFE_DL5_BASE_MSB                     0x4530
-#define AFE_DL5_BASE                         0x4534
-#define AFE_DL5_CUR_MSB                      0x4538
-#define AFE_DL5_CUR                          0x453c
-#define AFE_DL5_END_MSB                      0x4540
-#define AFE_DL5_END                          0x4544
-#define AFE_DL5_RCH_MON                      0x4548
-#define AFE_DL5_LCH_MON                      0x454c
-#define AFE_DL5_CON0                         0x4550
-#define AFE_DL5_MON0                         0x4554
-#define AFE_DL6_BASE_MSB                     0x4560
-#define AFE_DL6_BASE                         0x4564
-#define AFE_DL6_CUR_MSB                      0x4568
-#define AFE_DL6_CUR                          0x456c
-#define AFE_DL6_END_MSB                      0x4570
-#define AFE_DL6_END                          0x4574
-#define AFE_DL6_RCH_MON                      0x4578
-#define AFE_DL6_LCH_MON                      0x457c
-#define AFE_DL6_CON0                         0x4580
-#define AFE_DL6_MON0                         0x4584
-#define AFE_DL7_BASE_MSB                     0x4590
-#define AFE_DL7_BASE                         0x4594
-#define AFE_DL7_CUR_MSB                      0x4598
-#define AFE_DL7_CUR                          0x459c
-#define AFE_DL7_END_MSB                      0x45a0
-#define AFE_DL7_END                          0x45a4
-#define AFE_DL7_RCH_MON                      0x45a8
-#define AFE_DL7_LCH_MON                      0x45ac
-#define AFE_DL7_CON0                         0x45b0
-#define AFE_DL7_MON0                         0x45b4
-#define AFE_DL8_BASE_MSB                     0x45c0
-#define AFE_DL8_BASE                         0x45c4
-#define AFE_DL8_CUR_MSB                      0x45c8
-#define AFE_DL8_CUR                          0x45cc
-#define AFE_DL8_END_MSB                      0x45d0
-#define AFE_DL8_END                          0x45d4
-#define AFE_DL8_RCH_MON                      0x45d8
-#define AFE_DL8_LCH_MON                      0x45dc
-#define AFE_DL8_CON0                         0x45e0
-#define AFE_DL8_MON0                         0x45e4
-#define AFE_DL_4CH_BASE_MSB                  0x45f0
-#define AFE_DL_4CH_BASE                      0x45f4
-#define AFE_DL_4CH_CUR_MSB                   0x45f8
-#define AFE_DL_4CH_CUR                       0x45fc
-#define AFE_DL_4CH_END_MSB                   0x4600
-#define AFE_DL_4CH_END                       0x4604
-#define AFE_DL_4CH_CON0                      0x4610
-#define AFE_DL_4CH_MON0                      0x4618
-#define AFE_DL_24CH_BASE_MSB                 0x4620
-#define AFE_DL_24CH_BASE                     0x4624
-#define AFE_DL_24CH_CUR_MSB                  0x4628
-#define AFE_DL_24CH_CUR                      0x462c
-#define AFE_DL_24CH_END_MSB                  0x4630
-#define AFE_DL_24CH_END                      0x4634
-#define AFE_DL_24CH_CON0                     0x4640
-#define AFE_DL_24CH_MON0                     0x4648
-#define AFE_DL23_BASE_MSB                    0x4680
-#define AFE_DL23_BASE                        0x4684
-#define AFE_DL23_CUR_MSB                     0x4688
-#define AFE_DL23_CUR                         0x468c
-#define AFE_DL23_END_MSB                     0x4690
-#define AFE_DL23_END                         0x4694
-#define AFE_DL23_RCH_MON                     0x4698
-#define AFE_DL23_LCH_MON                     0x469c
-#define AFE_DL23_CON0                        0x46a0
-#define AFE_DL23_MON0                        0x46a4
-#define AFE_DL24_BASE_MSB                    0x46b0
-#define AFE_DL24_BASE                        0x46b4
-#define AFE_DL24_CUR_MSB                     0x46b8
-#define AFE_DL24_CUR                         0x46bc
-#define AFE_DL24_END_MSB                     0x46c0
-#define AFE_DL24_END                         0x46c4
-#define AFE_DL24_RCH_MON                     0x46c8
-#define AFE_DL24_LCH_MON                     0x46cc
-#define AFE_DL24_CON0                        0x46d0
-#define AFE_DL24_MON0                        0x46d4
-#define AFE_DL25_BASE_MSB                    0x46e0
-#define AFE_DL25_BASE                        0x46e4
-#define AFE_DL25_CUR_MSB                     0x46e8
-#define AFE_DL25_CUR                         0x46ec
-#define AFE_DL25_END_MSB                     0x46f0
-#define AFE_DL25_END                         0x46f4
-#define AFE_DL25_RCH_MON                     0x46f8
-#define AFE_DL25_LCH_MON                     0x46fc
-#define AFE_DL25_CON0                        0x4700
-#define AFE_DL25_MON0                        0x4704
-#define AFE_DL26_BASE_MSB                    0x4710
-#define AFE_DL26_BASE                        0x4714
-#define AFE_DL26_CUR_MSB                     0x4718
-#define AFE_DL26_CUR                         0x471c
-#define AFE_DL26_END_MSB                     0x4720
-#define AFE_DL26_END                         0x4724
-#define AFE_DL26_RCH_MON                     0x4728
-#define AFE_DL26_LCH_MON                     0x472c
-#define AFE_DL26_CON0                        0x4730
-#define AFE_DL26_MON0                        0x4734
-#define AFE_VUL0_BASE_MSB                    0x4d60
-#define AFE_VUL0_BASE                        0x4d64
-#define AFE_VUL0_CUR_MSB                     0x4d68
-#define AFE_VUL0_CUR                         0x4d6c
-#define AFE_VUL0_END_MSB                     0x4d70
-#define AFE_VUL0_END                         0x4d74
-#define AFE_VUL0_RCH_MON                     0x4d78
-#define AFE_VUL0_LCH_MON                     0x4d7c
-#define AFE_VUL0_CON0                        0x4d80
-#define AFE_VUL0_MON0                        0x4d84
-#define AFE_VUL1_BASE_MSB                    0x4d90
-#define AFE_VUL1_BASE                        0x4d94
-#define AFE_VUL1_CUR_MSB                     0x4d98
-#define AFE_VUL1_CUR                         0x4d9c
-#define AFE_VUL1_END_MSB                     0x4da0
-#define AFE_VUL1_END                         0x4da4
-#define AFE_VUL1_RCH_MON                     0x4da8
-#define AFE_VUL1_LCH_MON                     0x4dac
-#define AFE_VUL1_CON0                        0x4db0
-#define AFE_VUL1_MON0                        0x4db4
-#define AFE_VUL2_BASE_MSB                    0x4dc0
-#define AFE_VUL2_BASE                        0x4dc4
-#define AFE_VUL2_CUR_MSB                     0x4dc8
-#define AFE_VUL2_CUR                         0x4dcc
-#define AFE_VUL2_END_MSB                     0x4dd0
-#define AFE_VUL2_END                         0x4dd4
-#define AFE_VUL2_RCH_MON                     0x4dd8
-#define AFE_VUL2_LCH_MON                     0x4ddc
-#define AFE_VUL2_CON0                        0x4de0
-#define AFE_VUL2_MON0                        0x4de4
-#define AFE_VUL3_BASE_MSB                    0x4df0
-#define AFE_VUL3_BASE                        0x4df4
-#define AFE_VUL3_CUR_MSB                     0x4df8
-#define AFE_VUL3_CUR                         0x4dfc
-#define AFE_VUL3_END_MSB                     0x4e00
-#define AFE_VUL3_END                         0x4e04
-#define AFE_VUL3_RCH_MON                     0x4e08
-#define AFE_VUL3_LCH_MON                     0x4e0c
-#define AFE_VUL3_CON0                        0x4e10
-#define AFE_VUL3_MON0                        0x4e14
-#define AFE_VUL4_BASE_MSB                    0x4e20
-#define AFE_VUL4_BASE                        0x4e24
-#define AFE_VUL4_CUR_MSB                     0x4e28
-#define AFE_VUL4_CUR                         0x4e2c
-#define AFE_VUL4_END_MSB                     0x4e30
-#define AFE_VUL4_END                         0x4e34
-#define AFE_VUL4_RCH_MON                     0x4e38
-#define AFE_VUL4_LCH_MON                     0x4e3c
-#define AFE_VUL4_CON0                        0x4e40
-#define AFE_VUL4_MON0                        0x4e44
-#define AFE_VUL5_BASE_MSB                    0x4e50
-#define AFE_VUL5_BASE                        0x4e54
-#define AFE_VUL5_CUR_MSB                     0x4e58
-#define AFE_VUL5_CUR                         0x4e5c
-#define AFE_VUL5_END_MSB                     0x4e60
-#define AFE_VUL5_END                         0x4e64
-#define AFE_VUL5_RCH_MON                     0x4e68
-#define AFE_VUL5_LCH_MON                     0x4e6c
-#define AFE_VUL5_CON0                        0x4e70
-#define AFE_VUL5_MON0                        0x4e74
-#define AFE_VUL6_BASE_MSB                    0x4e80
-#define AFE_VUL6_BASE                        0x4e84
-#define AFE_VUL6_CUR_MSB                     0x4e88
-#define AFE_VUL6_CUR                         0x4e8c
-#define AFE_VUL6_END_MSB                     0x4e90
-#define AFE_VUL6_END                         0x4e94
-#define AFE_VUL6_RCH_MON                     0x4e98
-#define AFE_VUL6_LCH_MON                     0x4e9c
-#define AFE_VUL6_CON0                        0x4ea0
-#define AFE_VUL6_MON0                        0x4ea4
-#define AFE_VUL7_BASE_MSB                    0x4eb0
-#define AFE_VUL7_BASE                        0x4eb4
-#define AFE_VUL7_CUR_MSB                     0x4eb8
-#define AFE_VUL7_CUR                         0x4ebc
-#define AFE_VUL7_END_MSB                     0x4ec0
-#define AFE_VUL7_END                         0x4ec4
-#define AFE_VUL7_RCH_MON                     0x4ec8
-#define AFE_VUL7_LCH_MON                     0x4ecc
-#define AFE_VUL7_CON0                        0x4ed0
-#define AFE_VUL7_MON0                        0x4ed4
-#define AFE_VUL8_BASE_MSB                    0x4ee0
-#define AFE_VUL8_BASE                        0x4ee4
-#define AFE_VUL8_CUR_MSB                     0x4ee8
-#define AFE_VUL8_CUR                         0x4eec
-#define AFE_VUL8_END_MSB                     0x4ef0
-#define AFE_VUL8_END                         0x4ef4
-#define AFE_VUL8_RCH_MON                     0x4ef8
-#define AFE_VUL8_LCH_MON                     0x4efc
-#define AFE_VUL8_CON0                        0x4f00
-#define AFE_VUL8_MON0                        0x4f04
-#define AFE_VUL9_BASE_MSB                    0x4f10
-#define AFE_VUL9_BASE                        0x4f14
-#define AFE_VUL9_CUR_MSB                     0x4f18
-#define AFE_VUL9_CUR                         0x4f1c
-#define AFE_VUL9_END_MSB                     0x4f20
-#define AFE_VUL9_END                         0x4f24
-#define AFE_VUL9_RCH_MON                     0x4f28
-#define AFE_VUL9_LCH_MON                     0x4f2c
-#define AFE_VUL9_CON0                        0x4f30
-#define AFE_VUL9_MON0                        0x4f34
-#define AFE_VUL10_BASE_MSB                   0x4f40
-#define AFE_VUL10_BASE                       0x4f44
-#define AFE_VUL10_CUR_MSB                    0x4f48
-#define AFE_VUL10_CUR                        0x4f4c
-#define AFE_VUL10_END_MSB                    0x4f50
-#define AFE_VUL10_END                        0x4f54
-#define AFE_VUL10_RCH_MON                    0x4f58
-#define AFE_VUL10_LCH_MON                    0x4f5c
-#define AFE_VUL10_CON0                       0x4f60
-#define AFE_VUL10_MON0                       0x4f64
-#define AFE_VUL24_BASE_MSB                   0x4fa0
-#define AFE_VUL24_BASE                       0x4fa4
-#define AFE_VUL24_CUR_MSB                    0x4fa8
-#define AFE_VUL24_CUR                        0x4fac
-#define AFE_VUL24_END_MSB                    0x4fb0
-#define AFE_VUL24_END                        0x4fb4
-#define AFE_VUL24_CON0                       0x4fb8
-#define AFE_VUL24_MON0                       0x4fbc
-#define AFE_VUL25_BASE_MSB                   0x4fc0
-#define AFE_VUL25_BASE                       0x4fc4
-#define AFE_VUL25_CUR_MSB                    0x4fc8
-#define AFE_VUL25_CUR                        0x4fcc
-#define AFE_VUL25_END_MSB                    0x4fd0
-#define AFE_VUL25_END                        0x4fd4
-#define AFE_VUL25_CON0                       0x4fd8
-#define AFE_VUL25_MON0                       0x4fdc
-#define AFE_VUL26_BASE_MSB                   0x4fe0
-#define AFE_VUL26_BASE                       0x4fe4
-#define AFE_VUL26_CUR_MSB                    0x4fe8
-#define AFE_VUL26_CUR                        0x4fec
-#define AFE_VUL26_END_MSB                    0x4ff0
-#define AFE_VUL26_END                        0x4ff4
-#define AFE_VUL26_CON0                       0x4ff8
-#define AFE_VUL26_MON0                       0x4ffc
-#define AFE_VUL_CM0_BASE_MSB                 0x51c0
-#define AFE_VUL_CM0_BASE                     0x51c4
-#define AFE_VUL_CM0_CUR_MSB                  0x51c8
-#define AFE_VUL_CM0_CUR                      0x51cc
-#define AFE_VUL_CM0_END_MSB                  0x51d0
-#define AFE_VUL_CM0_END                      0x51d4
-#define AFE_VUL_CM0_CON0                     0x51d8
-#define AFE_VUL_CM1_BASE_MSB                 0x51e0
-#define AFE_VUL_CM1_BASE                     0x51e4
-#define AFE_VUL_CM1_CUR_MSB                  0x51e8
-#define AFE_VUL_CM1_CUR                      0x51ec
-#define AFE_VUL_CM1_END_MSB                  0x51f0
-#define AFE_VUL_CM1_END                      0x51f4
-#define AFE_VUL_CM1_CON0                     0x51f8
-#define AFE_VUL_CM2_BASE_MSB                 0x5200
-#define AFE_VUL_CM2_BASE                     0x5204
-#define AFE_VUL_CM2_CUR_MSB                  0x5208
-#define AFE_VUL_CM2_CUR                      0x520c
-#define AFE_VUL_CM2_END_MSB                  0x5210
-#define AFE_VUL_CM2_END                      0x5214
-#define AFE_VUL_CM2_CON0                     0x5218
-#define AFE_ETDM_IN0_BASE_MSB                0x5220
-#define AFE_ETDM_IN0_BASE                    0x5224
-#define AFE_ETDM_IN0_CUR_MSB                 0x5228
-#define AFE_ETDM_IN0_CUR                     0x522c
-#define AFE_ETDM_IN0_END_MSB                 0x5230
-#define AFE_ETDM_IN0_END                     0x5234
-#define AFE_ETDM_IN0_CON0                    0x5238
-#define AFE_ETDM_IN1_BASE_MSB                0x5240
-#define AFE_ETDM_IN1_BASE                    0x5244
-#define AFE_ETDM_IN1_CUR_MSB                 0x5248
-#define AFE_ETDM_IN1_CUR                     0x524c
-#define AFE_ETDM_IN1_END_MSB                 0x5250
-#define AFE_ETDM_IN1_END                     0x5254
-#define AFE_ETDM_IN1_CON0                    0x5258
-#define AFE_ETDM_IN2_BASE_MSB                0x5260
-#define AFE_ETDM_IN2_BASE                    0x5264
-#define AFE_ETDM_IN2_CUR_MSB                 0x5268
-#define AFE_ETDM_IN2_CUR                     0x526c
-#define AFE_ETDM_IN2_END_MSB                 0x5270
-#define AFE_ETDM_IN2_END                     0x5274
-#define AFE_ETDM_IN2_CON0                    0x5278
-#define AFE_ETDM_IN3_BASE_MSB                0x5280
-#define AFE_ETDM_IN3_BASE                    0x5284
-#define AFE_ETDM_IN3_CUR_MSB                 0x5288
-#define AFE_ETDM_IN3_CUR                     0x528c
-#define AFE_ETDM_IN3_END_MSB                 0x5290
-#define AFE_ETDM_IN3_END                     0x5294
-#define AFE_ETDM_IN3_CON0                    0x5298
-#define AFE_ETDM_IN4_BASE_MSB                0x52a0
-#define AFE_ETDM_IN4_BASE                    0x52a4
-#define AFE_ETDM_IN4_CUR_MSB                 0x52a8
-#define AFE_ETDM_IN4_CUR                     0x52ac
-#define AFE_ETDM_IN4_END_MSB                 0x52b0
-#define AFE_ETDM_IN4_END                     0x52b4
-#define AFE_ETDM_IN4_CON0                    0x52b8
-#define AFE_ETDM_IN5_BASE_MSB                0x52c0
-#define AFE_ETDM_IN5_BASE                    0x52c4
-#define AFE_ETDM_IN5_CUR_MSB                 0x52c8
-#define AFE_ETDM_IN5_CUR                     0x52cc
-#define AFE_ETDM_IN5_END_MSB                 0x52d0
-#define AFE_ETDM_IN5_END                     0x52d4
-#define AFE_ETDM_IN5_CON0                    0x52d8
-#define AFE_ETDM_IN6_BASE_MSB                0x52e0
-#define AFE_ETDM_IN6_BASE                    0x52e4
-#define AFE_ETDM_IN6_CUR_MSB                 0x52e8
-#define AFE_ETDM_IN6_CUR                     0x52ec
-#define AFE_ETDM_IN6_END_MSB                 0x52f0
-#define AFE_ETDM_IN6_END                     0x52f4
-#define AFE_ETDM_IN6_CON0                    0x52f8
-#define AFE_HDMI_OUT_BASE_MSB                0x5360
-#define AFE_HDMI_OUT_BASE                    0x5364
-#define AFE_HDMI_OUT_CUR_MSB                 0x5368
-#define AFE_HDMI_OUT_CUR                     0x536c
-#define AFE_HDMI_OUT_END_MSB                 0x5370
-#define AFE_HDMI_OUT_END                     0x5374
-#define AFE_HDMI_OUT_CON0                    0x5378
-#define AFE_VUL24_RCH_MON                    0x53e0
-#define AFE_VUL24_LCH_MON                    0x53e4
-#define AFE_VUL25_RCH_MON                    0x53e8
-#define AFE_VUL25_LCH_MON                    0x53ec
-#define AFE_VUL26_RCH_MON                    0x53f0
-#define AFE_VUL26_LCH_MON                    0x53f4
-#define AFE_VUL_CM0_RCH_MON                  0x5458
-#define AFE_VUL_CM0_LCH_MON                  0x545c
-#define AFE_VUL_CM1_RCH_MON                  0x5460
-#define AFE_VUL_CM1_LCH_MON                  0x5464
-#define AFE_VUL_CM2_RCH_MON                  0x5468
-#define AFE_VUL_CM2_LCH_MON                  0x546c
-#define AFE_DL_4CH_CH0_MON                   0x54f4
-#define AFE_DL_4CH_CH1_MON                   0x54f8
-#define AFE_DL_4CH_CH2_MON                   0x54fc
-#define AFE_DL_4CH_CH3_MON                   0x5500
-#define AFE_DL_24CH_CH0_MON                  0x5504
-#define AFE_DL_24CH_CH1_MON                  0x5508
-#define AFE_DL_24CH_CH2_MON                  0x550c
-#define AFE_DL_24CH_CH3_MON                  0x5510
-#define AFE_DL_24CH_CH4_MON                  0x5514
-#define AFE_DL_24CH_CH5_MON                  0x5518
-#define AFE_DL_24CH_CH6_MON                  0x551c
-#define AFE_DL_24CH_CH7_MON                  0x5520
-#define AFE_DL_24CH_CH8_MON                  0x5524
-#define AFE_DL_24CH_CH9_MON                  0x5528
-#define AFE_DL_24CH_CH10_MON                 0x552c
-#define AFE_DL_24CH_CH11_MON                 0x5530
-#define AFE_DL_24CH_CH12_MON                 0x5534
-#define AFE_DL_24CH_CH13_MON                 0x5538
-#define AFE_DL_24CH_CH14_MON                 0x553c
-#define AFE_DL_24CH_CH15_MON                 0x5540
-#define AFE_SRAM_BOUND                       0x5620
-#define AFE_SECURE_CON0                      0x5624
-#define AFE_SECURE_CON1                      0x5628
-#define AFE_SE_SECURE_CON0                   0x5630
-#define AFE_SE_SECURE_CON1                   0x5634
-#define AFE_SE_SECURE_CON2                   0x5638
-#define AFE_SE_SECURE_CON3                   0x563c
-#define AFE_SE_PROT_SIDEBAND0                0x5640
-#define AFE_SE_PROT_SIDEBAND1                0x5644
-#define AFE_SE_PROT_SIDEBAND2                0x5648
-#define AFE_SE_PROT_SIDEBAND3                0x564c
-#define AFE_SE_DOMAIN_SIDEBAND0              0x5650
-#define AFE_SE_DOMAIN_SIDEBAND1              0x5654
-#define AFE_SE_DOMAIN_SIDEBAND2              0x5658
-#define AFE_SE_DOMAIN_SIDEBAND3              0x565c
-#define AFE_SE_DOMAIN_SIDEBAND4              0x5660
-#define AFE_SE_DOMAIN_SIDEBAND5              0x5664
-#define AFE_SE_DOMAIN_SIDEBAND6              0x5668
-#define AFE_SE_DOMAIN_SIDEBAND7              0x566c
-#define AFE_SE_DOMAIN_SIDEBAND8              0x5670
-#define AFE_SE_DOMAIN_SIDEBAND9              0x5674
-#define AFE_PROT_SIDEBAND0_MON               0x5678
-#define AFE_PROT_SIDEBAND1_MON               0x567c
-#define AFE_PROT_SIDEBAND2_MON               0x5680
-#define AFE_PROT_SIDEBAND3_MON               0x5684
-#define AFE_DOMAIN_SIDEBAND0_MON             0x5688
-#define AFE_DOMAIN_SIDEBAND1_MON             0x568c
-#define AFE_DOMAIN_SIDEBAND2_MON             0x5690
-#define AFE_DOMAIN_SIDEBAND3_MON             0x5694
-#define AFE_DOMAIN_SIDEBAND4_MON             0x5698
-#define AFE_DOMAIN_SIDEBAND5_MON             0x569c
-#define AFE_DOMAIN_SIDEBAND6_MON             0x56a0
-#define AFE_DOMAIN_SIDEBAND7_MON             0x56a4
-#define AFE_DOMAIN_SIDEBAND8_MON             0x56a8
-#define AFE_DOMAIN_SIDEBAND9_MON             0x56ac
-#define AFE_SECURE_CONN0                     0x56b0
-#define AFE_SECURE_CONN_ETDM0                0x56b4
-#define AFE_SECURE_CONN_ETDM1                0x56b8
-#define AFE_SECURE_CONN_ETDM2                0x56bc
-#define AFE_SECURE_SRAM_CON0                 0x56c0
-#define AFE_SECURE_SRAM_CON1                 0x56c4
-#define AFE_SE_CONN_INPUT_MASK0              0x56d0
-#define AFE_SE_CONN_INPUT_MASK1              0x56d4
-#define AFE_SE_CONN_INPUT_MASK2              0x56d8
-#define AFE_SE_CONN_INPUT_MASK3              0x56dc
-#define AFE_SE_CONN_INPUT_MASK4              0x56e0
-#define AFE_SE_CONN_INPUT_MASK5              0x56e4
-#define AFE_SE_CONN_INPUT_MASK6              0x56e8
-#define AFE_SE_CONN_INPUT_MASK7              0x56ec
-#define AFE_NON_SE_CONN_INPUT_MASK0          0x56f0
-#define AFE_NON_SE_CONN_INPUT_MASK1          0x56f4
-#define AFE_NON_SE_CONN_INPUT_MASK2          0x56f8
-#define AFE_NON_SE_CONN_INPUT_MASK3          0x56fc
-#define AFE_NON_SE_CONN_INPUT_MASK4          0x5700
-#define AFE_NON_SE_CONN_INPUT_MASK5          0x5704
-#define AFE_NON_SE_CONN_INPUT_MASK6          0x5708
-#define AFE_NON_SE_CONN_INPUT_MASK7          0x570c
-#define AFE_SE_CONN_OUTPUT_SEL0              0x5710
-#define AFE_SE_CONN_OUTPUT_SEL1              0x5714
-#define AFE_SE_CONN_OUTPUT_SEL2              0x5718
-#define AFE_SE_CONN_OUTPUT_SEL3              0x571c
-#define AFE_SE_CONN_OUTPUT_SEL4              0x5720
-#define AFE_SE_CONN_OUTPUT_SEL5              0x5724
-#define AFE_SE_CONN_OUTPUT_SEL6              0x5728
-#define AFE_SE_CONN_OUTPUT_SEL7              0x572c
-#define AFE_PCM0_INTF_CON1_MASK_MON          0x5730
-#define AFE_PCM0_INTF_CON0_MASK_MON          0x5734
-#define AFE_CONNSYS_I2S_CON_MASK_MON         0x5738
-#define AFE_TDM_CON2_MASK_MON                0x5744
-#define AFE_MTKAIF0_CFG0_MASK_MON            0x574c
-#define AFE_MTKAIF1_CFG0_MASK_MON            0x5750
-#define AFE_ADDA_UL0_SRC_CON0_MASK_MON       0x5754
-#define AFE_ADDA_UL1_SRC_CON0_MASK_MON       0x5758
-#define AFE_ADDA_UL2_SRC_CON0_MASK_MON       0x575c
-#define AFE_ASRC_NEW_CON0                    0x7800
-#define AFE_ASRC_NEW_CON1                    0x7804
-#define AFE_ASRC_NEW_CON2                    0x7808
-#define AFE_ASRC_NEW_CON3                    0x780c
-#define AFE_ASRC_NEW_CON4                    0x7810
-#define AFE_ASRC_NEW_CON5                    0x7814
-#define AFE_ASRC_NEW_CON6                    0x7818
-#define AFE_ASRC_NEW_CON7                    0x781c
-#define AFE_ASRC_NEW_CON8                    0x7820
-#define AFE_ASRC_NEW_CON9                    0x7824
-#define AFE_ASRC_NEW_CON10                   0x7828
-#define AFE_ASRC_NEW_CON11                   0x782c
-#define AFE_ASRC_NEW_CON12                   0x7830
-#define AFE_ASRC_NEW_CON13                   0x7834
-#define AFE_ASRC_NEW_CON14                   0x7838
-#define AFE_ASRC_NEW_IP_VERSION              0x783c
-#define AFE_GASRC0_NEW_CON0                  0x7840
-#define AFE_GASRC0_NEW_CON1                  0x7844
-#define AFE_GASRC0_NEW_CON2                  0x7848
-#define AFE_GASRC0_NEW_CON3                  0x784c
-#define AFE_GASRC0_NEW_CON4                  0x7850
-#define AFE_GASRC0_NEW_CON5                  0x7854
-#define AFE_GASRC0_NEW_CON6                  0x7858
-#define AFE_GASRC0_NEW_CON7                  0x785c
-#define AFE_GASRC0_NEW_CON8                  0x7860
-#define AFE_GASRC0_NEW_CON9                  0x7864
-#define AFE_GASRC0_NEW_CON10                 0x7868
-#define AFE_GASRC0_NEW_CON11                 0x786c
-#define AFE_GASRC0_NEW_CON12                 0x7870
-#define AFE_GASRC0_NEW_CON13                 0x7874
-#define AFE_GASRC0_NEW_CON14                 0x7878
-#define AFE_GASRC0_NEW_IP_VERSION            0x787c
-#define AFE_GASRC1_NEW_CON0                  0x7880
-#define AFE_GASRC1_NEW_CON1                  0x7884
-#define AFE_GASRC1_NEW_CON2                  0x7888
-#define AFE_GASRC1_NEW_CON3                  0x788c
-#define AFE_GASRC1_NEW_CON4                  0x7890
-#define AFE_GASRC1_NEW_CON5                  0x7894
-#define AFE_GASRC1_NEW_CON6                  0x7898
-#define AFE_GASRC1_NEW_CON7                  0x789c
-#define AFE_GASRC1_NEW_CON8                  0x78a0
-#define AFE_GASRC1_NEW_CON9                  0x78a4
-#define AFE_GASRC1_NEW_CON10                 0x78a8
-#define AFE_GASRC1_NEW_CON11                 0x78ac
-#define AFE_GASRC1_NEW_CON12                 0x78b0
-#define AFE_GASRC1_NEW_CON13                 0x78b4
-#define AFE_GASRC1_NEW_CON14                 0x78b8
-#define AFE_GASRC1_NEW_IP_VERSION            0x78bc
-#define AFE_GASRC2_NEW_CON0                  0x78c0
-#define AFE_GASRC2_NEW_CON1                  0x78c4
-#define AFE_GASRC2_NEW_CON2                  0x78c8
-#define AFE_GASRC2_NEW_CON3                  0x78cc
-#define AFE_GASRC2_NEW_CON4                  0x78d0
-#define AFE_GASRC2_NEW_CON5                  0x78d4
-#define AFE_GASRC2_NEW_CON6                  0x78d8
-#define AFE_GASRC2_NEW_CON7                  0x78dc
-#define AFE_GASRC2_NEW_CON8                  0x78e0
-#define AFE_GASRC2_NEW_CON9                  0x78e4
-#define AFE_GASRC2_NEW_CON10                 0x78e8
-#define AFE_GASRC2_NEW_CON11                 0x78ec
-#define AFE_GASRC2_NEW_CON12                 0x78f0
-#define AFE_GASRC2_NEW_CON13                 0x78f4
-#define AFE_GASRC2_NEW_CON14                 0x78f8
-#define AFE_GASRC2_NEW_IP_VERSION            0x78fc
-#define AFE_GASRC3_NEW_CON0                  0x7900
-#define AFE_GASRC3_NEW_CON1                  0x7904
-#define AFE_GASRC3_NEW_CON2                  0x7908
-#define AFE_GASRC3_NEW_CON3                  0x790c
-#define AFE_GASRC3_NEW_CON4                  0x7910
-#define AFE_GASRC3_NEW_CON5                  0x7914
-#define AFE_GASRC3_NEW_CON6                  0x7918
-#define AFE_GASRC3_NEW_CON7                  0x791c
-#define AFE_GASRC3_NEW_CON8                  0x7920
-#define AFE_GASRC3_NEW_CON9                  0x7924
-#define AFE_GASRC3_NEW_CON10                 0x7928
-#define AFE_GASRC3_NEW_CON11                 0x792c
-#define AFE_GASRC3_NEW_CON12                 0x7930
-#define AFE_GASRC3_NEW_CON13                 0x7934
-#define AFE_GASRC3_NEW_CON14                 0x7938
-#define AFE_GASRC3_NEW_IP_VERSION            0x793c
-#define AFE_GASRC4_NEW_CON0                  0x7940
-#define AFE_GASRC4_NEW_CON1                  0x7944
-#define AFE_GASRC4_NEW_CON2                  0x7948
-#define AFE_GASRC4_NEW_CON3                  0x794c
-#define AFE_GASRC4_NEW_CON4                  0x7950
-#define AFE_GASRC4_NEW_CON5                  0x7954
-#define AFE_GASRC4_NEW_CON6                  0x7958
-#define AFE_GASRC4_NEW_CON7                  0x795c
-#define AFE_GASRC4_NEW_CON8                  0x7960
-#define AFE_GASRC4_NEW_CON9                  0x7964
-#define AFE_GASRC4_NEW_CON10                 0x7968
-#define AFE_GASRC4_NEW_CON11                 0x796c
-#define AFE_GASRC4_NEW_CON12                 0x7970
-#define AFE_GASRC4_NEW_CON13                 0x7974
-#define AFE_GASRC4_NEW_CON14                 0x7978
-#define AFE_GASRC4_NEW_IP_VERSION            0x797c
-#define AFE_GASRC5_NEW_CON0                  0x7980
-#define AFE_GASRC5_NEW_CON1                  0x7984
-#define AFE_GASRC5_NEW_CON2                  0x7988
-#define AFE_GASRC5_NEW_CON3                  0x798c
-#define AFE_GASRC5_NEW_CON4                  0x7990
-#define AFE_GASRC5_NEW_CON5                  0x7994
-#define AFE_GASRC5_NEW_CON6                  0x7998
-#define AFE_GASRC5_NEW_CON7                  0x799c
-#define AFE_GASRC5_NEW_CON8                  0x79a0
-#define AFE_GASRC5_NEW_CON9                  0x79a4
-#define AFE_GASRC5_NEW_CON10                 0x79a8
-#define AFE_GASRC5_NEW_CON11                 0x79ac
-#define AFE_GASRC5_NEW_CON12                 0x79b0
-#define AFE_GASRC5_NEW_CON13                 0x79b4
-#define AFE_GASRC5_NEW_CON14                 0x79b8
-#define AFE_GASRC5_NEW_IP_VERSION            0x79bc
-#define AFE_GASRC6_NEW_CON0                  0x79c0
-#define AFE_GASRC6_NEW_CON1                  0x79c4
-#define AFE_GASRC6_NEW_CON2                  0x79c8
-#define AFE_GASRC6_NEW_CON3                  0x79cc
-#define AFE_GASRC6_NEW_CON4                  0x79d0
-#define AFE_GASRC6_NEW_CON5                  0x79d4
-#define AFE_GASRC6_NEW_CON6                  0x79d8
-#define AFE_GASRC6_NEW_CON7                  0x79dc
-#define AFE_GASRC6_NEW_CON8                  0x79e0
-#define AFE_GASRC6_NEW_CON9                  0x79e4
-#define AFE_GASRC6_NEW_CON10                 0x79e8
-#define AFE_GASRC6_NEW_CON11                 0x79ec
-#define AFE_GASRC6_NEW_CON12                 0x79f0
-#define AFE_GASRC6_NEW_CON13                 0x79f4
-#define AFE_GASRC6_NEW_CON14                 0x79f8
-#define AFE_GASRC6_NEW_IP_VERSION            0x79fc
-#define AFE_GASRC7_NEW_CON0                  0x7a00
-#define AFE_GASRC7_NEW_CON1                  0x7a04
-#define AFE_GASRC7_NEW_CON2                  0x7a08
-#define AFE_GASRC7_NEW_CON3                  0x7a0c
-#define AFE_GASRC7_NEW_CON4                  0x7a10
-#define AFE_GASRC7_NEW_CON5                  0x7a14
-#define AFE_GASRC7_NEW_CON6                  0x7a18
-#define AFE_GASRC7_NEW_CON7                  0x7a1c
-#define AFE_GASRC7_NEW_CON8                  0x7a20
-#define AFE_GASRC7_NEW_CON9                  0x7a24
-#define AFE_GASRC7_NEW_CON10                 0x7a28
-#define AFE_GASRC7_NEW_CON11                 0x7a2c
-#define AFE_GASRC7_NEW_CON12                 0x7a30
-#define AFE_GASRC7_NEW_CON13                 0x7a34
-#define AFE_GASRC7_NEW_CON14                 0x7a38
-#define AFE_GASRC7_NEW_IP_VERSION            0x7a3c
-#define AFE_GASRC8_NEW_CON0                  0x7a40
-#define AFE_GASRC8_NEW_CON1                  0x7a44
-#define AFE_GASRC8_NEW_CON2                  0x7a48
-#define AFE_GASRC8_NEW_CON3                  0x7a4c
-#define AFE_GASRC8_NEW_CON4                  0x7a50
-#define AFE_GASRC8_NEW_CON5                  0x7a54
-#define AFE_GASRC8_NEW_CON6                  0x7a58
-#define AFE_GASRC8_NEW_CON7                  0x7a5c
-#define AFE_GASRC8_NEW_CON8                  0x7a60
-#define AFE_GASRC8_NEW_CON9                  0x7a64
-#define AFE_GASRC8_NEW_CON10                 0x7a68
-#define AFE_GASRC8_NEW_CON11                 0x7a6c
-#define AFE_GASRC8_NEW_CON12                 0x7a70
-#define AFE_GASRC8_NEW_CON13                 0x7a74
-#define AFE_GASRC8_NEW_CON14                 0x7a78
-#define AFE_GASRC8_NEW_IP_VERSION            0x7a7c
-#define AFE_GASRC9_NEW_CON0                  0x7a80
-#define AFE_GASRC9_NEW_CON1                  0x7a84
-#define AFE_GASRC9_NEW_CON2                  0x7a88
-#define AFE_GASRC9_NEW_CON3                  0x7a8c
-#define AFE_GASRC9_NEW_CON4                  0x7a90
-#define AFE_GASRC9_NEW_CON5                  0x7a94
-#define AFE_GASRC9_NEW_CON6                  0x7a98
-#define AFE_GASRC9_NEW_CON7                  0x7a9c
-#define AFE_GASRC9_NEW_CON8                  0x7aa0
-#define AFE_GASRC9_NEW_CON9                  0x7aa4
-#define AFE_GASRC9_NEW_CON10                 0x7aa8
-#define AFE_GASRC9_NEW_CON11                 0x7aac
-#define AFE_GASRC9_NEW_CON12                 0x7ab0
-#define AFE_GASRC9_NEW_CON13                 0x7ab4
-#define AFE_GASRC9_NEW_CON14                 0x7ab8
-#define AFE_GASRC9_NEW_IP_VERSION            0x7abc
-#define AFE_GASRC10_NEW_CON0                 0x7ac0
-#define AFE_GASRC10_NEW_CON1                 0x7ac4
-#define AFE_GASRC10_NEW_CON2                 0x7ac8
-#define AFE_GASRC10_NEW_CON3                 0x7acc
-#define AFE_GASRC10_NEW_CON4                 0x7ad0
-#define AFE_GASRC10_NEW_CON5                 0x7ad4
-#define AFE_GASRC10_NEW_CON6                 0x7ad8
-#define AFE_GASRC10_NEW_CON7                 0x7adc
-#define AFE_GASRC10_NEW_CON8                 0x7ae0
-#define AFE_GASRC10_NEW_CON9                 0x7ae4
-#define AFE_GASRC10_NEW_CON10                0x7ae8
-#define AFE_GASRC10_NEW_CON11                0x7aec
-#define AFE_GASRC10_NEW_CON12                0x7af0
-#define AFE_GASRC10_NEW_CON13                0x7af4
-#define AFE_GASRC10_NEW_CON14                0x7af8
-#define AFE_GASRC10_NEW_IP_VERSION           0x7afc
-#define AFE_GASRC11_NEW_CON0                 0x7b00
-#define AFE_GASRC11_NEW_CON1                 0x7b04
-#define AFE_GASRC11_NEW_CON2                 0x7b08
-#define AFE_GASRC11_NEW_CON3                 0x7b0c
-#define AFE_GASRC11_NEW_CON4                 0x7b10
-#define AFE_GASRC11_NEW_CON5                 0x7b14
-#define AFE_GASRC11_NEW_CON6                 0x7b18
-#define AFE_GASRC11_NEW_CON7                 0x7b1c
-#define AFE_GASRC11_NEW_CON8                 0x7b20
-#define AFE_GASRC11_NEW_CON9                 0x7b24
-#define AFE_GASRC11_NEW_CON10                0x7b28
-#define AFE_GASRC11_NEW_CON11                0x7b2c
-#define AFE_GASRC11_NEW_CON12                0x7b30
-#define AFE_GASRC11_NEW_CON13                0x7b34
-#define AFE_GASRC11_NEW_CON14                0x7b38
-#define AFE_GASRC11_NEW_IP_VERSION           0x7b3c
-#define AFE_GASRC12_NEW_CON0                 0x7b40
-#define AFE_GASRC12_NEW_CON1                 0x7b44
-#define AFE_GASRC12_NEW_CON2                 0x7b48
-#define AFE_GASRC12_NEW_CON3                 0x7b4c
-#define AFE_GASRC12_NEW_CON4                 0x7b50
-#define AFE_GASRC12_NEW_CON5                 0x7b54
-#define AFE_GASRC12_NEW_CON6                 0x7b58
-#define AFE_GASRC12_NEW_CON7                 0x7b5c
-#define AFE_GASRC12_NEW_CON8                 0x7b60
-#define AFE_GASRC12_NEW_CON9                 0x7b64
-#define AFE_GASRC12_NEW_CON10                0x7b68
-#define AFE_GASRC12_NEW_CON11                0x7b6c
-#define AFE_GASRC12_NEW_CON12                0x7b70
-#define AFE_GASRC12_NEW_CON13                0x7b74
-#define AFE_GASRC12_NEW_CON14                0x7b78
-#define AFE_GASRC12_NEW_IP_VERSION           0x7b7c
-#define AFE_GASRC13_NEW_CON0                 0x7b80
-#define AFE_GASRC13_NEW_CON1                 0x7b84
-#define AFE_GASRC13_NEW_CON2                 0x7b88
-#define AFE_GASRC13_NEW_CON3                 0x7b8c
-#define AFE_GASRC13_NEW_CON4                 0x7b90
-#define AFE_GASRC13_NEW_CON5                 0x7b94
-#define AFE_GASRC13_NEW_CON6                 0x7b98
-#define AFE_GASRC13_NEW_CON7                 0x7b9c
-#define AFE_GASRC13_NEW_CON8                 0x7ba0
-#define AFE_GASRC13_NEW_CON9                 0x7ba4
-#define AFE_GASRC13_NEW_CON10                0x7ba8
-#define AFE_GASRC13_NEW_CON11                0x7bac
-#define AFE_GASRC13_NEW_CON12                0x7bb0
-#define AFE_GASRC13_NEW_CON13                0x7bb4
-#define AFE_GASRC13_NEW_CON14                0x7bb8
-#define AFE_GASRC13_NEW_IP_VERSION           0x7bbc
-#define AFE_GASRC14_NEW_CON0                 0x7bc0
-#define AFE_GASRC14_NEW_CON1                 0x7bc4
-#define AFE_GASRC14_NEW_CON2                 0x7bc8
-#define AFE_GASRC14_NEW_CON3                 0x7bcc
-#define AFE_GASRC14_NEW_CON4                 0x7bd0
-#define AFE_GASRC14_NEW_CON5                 0x7bd4
-#define AFE_GASRC14_NEW_CON6                 0x7bd8
-#define AFE_GASRC14_NEW_CON7                 0x7bdc
-#define AFE_GASRC14_NEW_CON8                 0x7be0
-#define AFE_GASRC14_NEW_CON9                 0x7be4
-#define AFE_GASRC14_NEW_CON10                0x7be8
-#define AFE_GASRC14_NEW_CON11                0x7bec
-#define AFE_GASRC14_NEW_CON12                0x7bf0
-#define AFE_GASRC14_NEW_CON13                0x7bf4
-#define AFE_GASRC14_NEW_CON14                0x7bf8
-#define AFE_GASRC14_NEW_IP_VERSION           0x7bfc
-#define AFE_GASRC15_NEW_CON0                 0x7c00
-#define AFE_GASRC15_NEW_CON1                 0x7c04
-#define AFE_GASRC15_NEW_CON2                 0x7c08
-#define AFE_GASRC15_NEW_CON3                 0x7c0c
-#define AFE_GASRC15_NEW_CON4                 0x7c10
-#define AFE_GASRC15_NEW_CON5                 0x7c14
-#define AFE_GASRC15_NEW_CON6                 0x7c18
-#define AFE_GASRC15_NEW_CON7                 0x7c1c
-#define AFE_GASRC15_NEW_CON8                 0x7c20
-#define AFE_GASRC15_NEW_CON9                 0x7c24
-#define AFE_GASRC15_NEW_CON10                0x7c28
-#define AFE_GASRC15_NEW_CON11                0x7c2c
-#define AFE_GASRC15_NEW_CON12                0x7c30
-#define AFE_GASRC15_NEW_CON13                0x7c34
-#define AFE_GASRC15_NEW_CON14                0x7c38
-#define AFE_GASRC15_NEW_IP_VERSION           0x7c3c
-
-#define AFE_MAX_REGISTER AFE_GASRC15_NEW_IP_VERSION
-
-#define AFE_IRQ_STATUS_BITS 0x87FFFFFF
-#define AFE_IRQ_CNT_SHIFT 0
-#define AFE_IRQ_CNT_MASK 0xffffff
-#endif
diff --git a/src/platform/mt8196/include/platform/platform.h b/src/platform/mt8196/include/platform/platform.h
deleted file mode 100644
index 60becc79ded7..000000000000
--- a/src/platform/mt8196/include/platform/platform.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2024 MediaTek. All rights reserved.
- *
- * Author: Hailong Fan <hailong.fan@mediatek.com>
- */
-
-#ifdef __SOF_PLATFORM_H__
-
-#ifndef __PLATFORM_PLATFORM_H__
-#define __PLATFORM_PLATFORM_H__
-
-#if !defined(__ASSEMBLER__) && !defined(LINKER)
-
-#include <sof/lib/mailbox.h>
-#include <stddef.h>
-#include <stdint.h>
-
-struct ll_schedule_domain;
-struct timer;
-
-#define PLATFORM_DEFAULT_CLOCK CLK_CPU(0)
-#define LPSRAM_SIZE 16384
-
-/* IPC Interrupt */
-#define PLATFORM_IPC_INTERRUPT MTK_DSP_IRQ_MAILBOX
-#define PLATFORM_IPC_INTERRUPT_NAME NULL
-
-/* Host page size */
-#define HOST_PAGE_SIZE 4096
-#define PLATFORM_PAGE_TABLE_SIZE 256
-
-/* pipeline IRQ */
-#define PLATFORM_SCHEDULE_IRQ MTK_DSP_IRQ_SW
-#define PLATFORM_SCHEDULE_IRQ_NAME NULL
-
-/* Platform stream capabilities */
-#define PLATFORM_MAX_CHANNELS 4
-#define PLATFORM_MAX_STREAMS 5
-
-/* local buffer size of DMA tracing */
-#define DMA_TRACE_LOCAL_SIZE HOST_PAGE_SIZE
-
-/* trace bytes flushed during panic */
-#define DMA_FLUSH_TRACE_SIZE (MAILBOX_TRACE_SIZE >> 2)
-
-/* the interval of DMA trace copying */
-#define DMA_TRACE_PERIOD 500000
-
-/*
- * the interval of reschedule DMA trace copying in special case like half
- * fullness of local DMA trace buffer
- */
-#define DMA_TRACE_RESCHEDULE_TIME 100
-
-/* DSP default delay in cycles */
-#define PLATFORM_DEFAULT_DELAY 12
-
-#define SRAM_REG_FW_STATUS 0x4
-
-/* Platform defined panic code */
-static inline void platform_panic(uint32_t p)
-{
-	/* Store the error code in the debug box so the
-	 * application processor can pick it up. Takes up 4 bytes
-	 * from the debug box.
-	 */
-	mailbox_sw_reg_write(SRAM_REG_FW_STATUS, p);
-
-	/* Notify application processor */
-	trigger_irq_to_host_req();
-}
-
-/**
- * \brief Platform specific CPU entering idle.
- * May be power-optimized using platform specific capabilities.
- * @param level Interrupt level.
- */
-void platform_wait_for_interrupt(int level);
-
-extern intptr_t _module_init_start;
-extern intptr_t _module_init_end;
-#endif
-
-#endif /* __PLATFORM_PLATFORM_H__ */
-
-#else
-
-#error "This file shouldn't be included from outside of sof/platform.h"
-
-#endif /* __SOF_PLATFORM_H__ */
diff --git a/src/platform/mt8196/include/platform/trace/trace.h b/src/platform/mt8196/include/platform/trace/trace.h
deleted file mode 100644
index ede2259cf192..000000000000
--- a/src/platform/mt8196/include/platform/trace/trace.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2024 MediaTek. All rights reserved.
- *
- * Author: Hailong Fan <hailong.fan@mediatek.com>
- */
-
-#ifdef __SOF_TRACE_TRACE_H__
-
-#ifndef __PLATFORM_TRACE_TRACE_H__
-#define __PLATFORM_TRACE_TRACE_H__
-
-#include <sof/lib/mailbox.h>
-#include <sof/lib/memory.h>
-#include <sof/lib/io.h>
-#include <platform/drivers/mt_reg_base.h>
-
-#define platform_trace_point(__x)
-
-#endif /* __PLATFORM_TRACE_TRACE_H__ */
-
-#else
-
-#error "This file shouldn't be included from outside of sof/trace/trace.h"
-
-#endif /* __SOF_TRACE_TRACE_H__ */
diff --git a/src/platform/mt8196/lib/CMakeLists.txt b/src/platform/mt8196/lib/CMakeLists.txt
deleted file mode 100644
index ef71f8eea6cd..000000000000
--- a/src/platform/mt8196/lib/CMakeLists.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-
-add_local_sources(sof
-	clk.c
-	dma.c
-	memory.c
-	dai.c
-)
diff --git a/src/platform/mt8196/lib/clk.c b/src/platform/mt8196/lib/clk.c
deleted file mode 100644
index 3717fc288fbc..000000000000
--- a/src/platform/mt8196/lib/clk.c
+++ /dev/null
@@ -1,59 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-/*
- * Copyright(c) 2024 MediaTek. All rights reserved.
- *
- * Author: Hailong Fan <hailong.fan@mediatek.com>
- */
-
-#include <platform/drivers/mt_reg_base.h>
-#include <rtos/clk.h>
-#include <rtos/wait.h>
-#include <sof/common.h>
-#include <sof/lib/cpu.h>
-#include <sof/lib/io.h>
-#include <sof/lib/memory.h>
-#include <sof/lib/notifier.h>
-#include <sof/lib/uuid.h>
-#include <rtos/sof.h>
-#include <sof/trace/trace.h>
-
-SOF_DEFINE_REG_UUID(clkdrv_mt8196);
-
-/* unused with Zephyr, generates no output */
-DECLARE_TR_CTX(clkdrv_tr, SOF_UUID(clkdrv_mt8196_uuid), LOG_LEVEL_INFO);
-
-/* default voltage is 0.75V */
-const struct freq_table platform_cpu_freq[] = {
-	{  26000000, 26000},
-	{ 800000000, 26000},
-};
-
-STATIC_ASSERT(ARRAY_SIZE(platform_cpu_freq) == NUM_CPU_FREQ,
-	      invalid_number_of_cpu_frequencies);
-
-static struct clock_info platform_clocks_info[NUM_CLOCKS];
-
-void platform_clock_init(struct sof *sof)
-{
-	int i;
-
-	tr_dbg(&clkdrv_tr, "clock init\n");
-	sof->clocks = platform_clocks_info;
-
-	/* When the system is in an active state, the DSP clock operates at 800MHz (0.75V).
-	 * In a low power scenario, the DSP enters WFI state, and the clock reduces to 26MHz.
-	 * The clock selection is controlled by the host, and we do not allow SOF to change
-	 * the ADSP frequency.
-	 */
-	for (i = 0; i < CONFIG_CORE_COUNT; i++) {
-		sof->clocks[i] = (struct clock_info){
-			.freqs_num = NUM_CPU_FREQ,
-			.freqs = platform_cpu_freq,
-			.default_freq_idx = CPU_DEFAULT_IDX,
-			.current_freq_idx = CPU_DEFAULT_IDX,
-			.notification_id = NOTIFIER_ID_CPU_FREQ,
-			.notification_mask = NOTIFIER_TARGET_CORE_MASK(i),
-			.set_freq = NULL,
-		};
-	}
-}
diff --git a/src/platform/mt8196/lib/dai.c b/src/platform/mt8196/lib/dai.c
deleted file mode 100755
index 63a08e5eb095..000000000000
--- a/src/platform/mt8196/lib/dai.c
+++ /dev/null
@@ -1,58 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-/*
- * Copyright(c) 2024 MediaTek. All rights reserved.
- *
- * Author: Darren Ye <darren.ye@mediatek.com>
- */
-
-#include <sof/common.h>
-#include <sof/lib/dai.h>
-#include <sof/lib/memory.h>
-#include <sof/lib/uuid.h>
-#include <rtos/sof.h>
-#include <rtos/spinlock.h>
-#include <ipc/dai.h>
-#include <ipc/stream.h>
-#include <sof/drivers/afe-dai.h>
-#include <mt8196-afe-common.h>
-
-static int afe_dai_handshake[MT8196_DAI_NUM] = {
-	AFE_HANDSHAKE(MT8196_DAI_I2S_OUT4, MT8196_IRQ_12, MT8196_MEMIF_DL_24CH),
-	AFE_HANDSHAKE(MT8196_DAI_I2S_OUT6, MT8196_IRQ_1, MT8196_MEMIF_DL1),
-	AFE_HANDSHAKE(MT8196_DAI_AP_DMIC, MT8196_IRQ_13, MT8196_MEMIF_UL0),
-	AFE_HANDSHAKE(MT8196_DAI_I2S_IN6, MT8196_IRQ_0, MT8196_MEMIF_UL1),
-	AFE_HANDSHAKE(MT8196_DAI_AP_DMIC_CH34, MT8196_IRQ_15, MT8196_MEMIF_UL2),
-};
-
-static struct dai afe_dai[MT8196_DAI_NUM];
-
-const struct dai_type_info dti[] = {
-	{
-		.type = SOF_DAI_MEDIATEK_AFE,
-		.dai_array = afe_dai,
-		.num_dais = ARRAY_SIZE(afe_dai),
-	},
-};
-
-const struct dai_info lib_dai = {
-	.dai_type_array = dti,
-	.num_dai_types = ARRAY_SIZE(dti),
-};
-
-int dai_init(struct sof *sof)
-{
-	int i;
-
-	/* initialize spin locks early to enable ref counting */
-	for (i = 0; i < ARRAY_SIZE(afe_dai); i++) {
-		k_spinlock_init(&afe_dai[i].lock);
-		afe_dai[i].index = AFE_HS_GET_DAI(afe_dai_handshake[i]);
-		afe_dai[i].drv = &afe_dai_driver;
-		/* TODO, fifo[0] change to target playback or capture */
-		afe_dai[i].plat_data.fifo[0].handshake = afe_dai_handshake[i];
-	}
-
-	sof->dai_info = &lib_dai;
-
-	return 0;
-}
diff --git a/src/platform/mt8196/lib/dma.c b/src/platform/mt8196/lib/dma.c
deleted file mode 100644
index fef728fc87ea..000000000000
--- a/src/platform/mt8196/lib/dma.c
+++ /dev/null
@@ -1,60 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-/*
- * Copyright(c) 2024 MediaTek. All rights reserved.
- *
- * Author: Hailong Fan <hailong.fan@mediatek.com>
- *         Darren Ye <darren.ye@mediatek.com>
- */
-
-#include <rtos/interrupt.h>
-#include <rtos/spinlock.h>
-#include <sof/common.h>
-#include <sof/drivers/afe-memif.h>
-#include <sof/lib/dma.h>
-#include <sof/lib/memory.h>
-#include <rtos/sof.h>
-#include <mt8196-afe-reg.h>
-#include <mt8196-afe-common.h>
-
-extern const struct dma_ops dummy_dma_ops;
-
-static struct dma dma[PLATFORM_NUM_DMACS] = {
-{
-	.plat_data = {
-		.id		= DMA_ID_HOST,
-		.dir		= DMA_DIR_HMEM_TO_LMEM | DMA_DIR_LMEM_TO_HMEM,
-		.devs		= DMA_DEV_HOST,
-		.channels	= 16,
-	},
-	.ops	= &dummy_dma_ops,
-},
-{
-	.plat_data = {
-		.id		= DMA_ID_AFE_MEMIF,
-		.dir		= DMA_DIR_MEM_TO_DEV | DMA_DIR_DEV_TO_MEM,
-		.devs		= DMA_DEV_AFE_MEMIF,
-		.base		= AFE_BASE_ADDR,
-		.channels	= MT8196_MEMIF_NUM,
-	},
-	.ops	= &memif_ops,
-},
-
-};
-
-static const struct dma_info lib_dma = {
-	.dma_array = cache_to_uncache_init((struct dma *)dma),
-	.num_dmas = ARRAY_SIZE(dma)
-};
-
-int dmac_init(struct sof *sof)
-{
-	int i;
-
-	/* early lock initialization for ref counting */
-	for (i = 0; i < ARRAY_SIZE(dma); i++)
-		k_spinlock_init(&dma[i].lock);
-
-	sof->dma_info = &lib_dma;
-
-	return 0;
-}
diff --git a/src/platform/mt8196/lib/memory.c b/src/platform/mt8196/lib/memory.c
deleted file mode 100644
index c46956ed4946..000000000000
--- a/src/platform/mt8196/lib/memory.c
+++ /dev/null
@@ -1,101 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-/*
- * Copyright(c) 2024 MediaTek. All rights reserved.
- *
- * Author: Hailong Fan <hailong.fan@mediatek.com>
- */
-
-#include <ipc/topology.h>
-#include <sof/common.h>
-#include <sof/lib/mm_heap.h>
-#include <sof/lib/memory.h>
-#include <rtos/sof.h>
-
-/* Heap blocks for system runtime */
-static struct block_hdr sys_rt_block64[HEAP_SYS_RT_COUNT64];
-static struct block_hdr sys_rt_block512[HEAP_SYS_RT_COUNT512];
-static struct block_hdr sys_rt_block1024[HEAP_SYS_RT_COUNT1024];
-
-/* Heap memory for system runtime */
-static struct block_map sys_rt_heap_map[] = {
-	BLOCK_DEF(64, HEAP_SYS_RT_COUNT64, sys_rt_block64),
-	BLOCK_DEF(512, HEAP_SYS_RT_COUNT512, sys_rt_block512),
-	BLOCK_DEF(1024, HEAP_SYS_RT_COUNT1024, sys_rt_block1024),
-};
-
-/* Heap blocks for modules */
-static struct block_hdr mod_block16[HEAP_RT_COUNT16];
-static struct block_hdr mod_block32[HEAP_RT_COUNT32];
-static struct block_hdr mod_block64[HEAP_RT_COUNT64];
-static struct block_hdr mod_block128[HEAP_RT_COUNT128];
-static struct block_hdr mod_block256[HEAP_RT_COUNT256];
-static struct block_hdr mod_block512[HEAP_RT_COUNT512];
-static struct block_hdr mod_block1024[HEAP_RT_COUNT1024];
-static struct block_hdr mod_block2048[HEAP_RT_COUNT2048];
-static struct block_hdr mod_block4096[HEAP_RT_COUNT4096];
-
-/* Heap memory map for modules */
-static struct block_map rt_heap_map[] = {
-	BLOCK_DEF(16, HEAP_RT_COUNT16, mod_block16),
-	BLOCK_DEF(32, HEAP_RT_COUNT32, mod_block32),
-	BLOCK_DEF(64, HEAP_RT_COUNT64, mod_block64),
-	BLOCK_DEF(128, HEAP_RT_COUNT128, mod_block128),
-	BLOCK_DEF(256, HEAP_RT_COUNT256, mod_block256),
-	BLOCK_DEF(512, HEAP_RT_COUNT512, mod_block512),
-	BLOCK_DEF(1024, HEAP_RT_COUNT1024, mod_block1024),
-	BLOCK_DEF(2048, HEAP_RT_COUNT2048, mod_block2048),
-	BLOCK_DEF(4096, HEAP_RT_COUNT4096, mod_block4096),
-};
-
-/* Heap blocks for buffers */
-static struct block_hdr buf_block[HEAP_BUFFER_COUNT];
-
-/* Heap memory map for buffers */
-static struct block_map buf_heap_map[] = {
-	BLOCK_DEF(HEAP_BUFFER_BLOCK_SIZE, HEAP_BUFFER_COUNT, buf_block),
-};
-
-static struct mm memmap = {
-	.system[0] = {
-		.heap = HEAP_SYSTEM_BASE,
-		.size = HEAP_SYSTEM_SIZE,
-		.info = {.free = HEAP_SYSTEM_SIZE,},
-		.caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_CACHE |
-			SOF_MEM_CAPS_DMA,
-	},
-	.system_runtime[0] = {
-		.blocks = ARRAY_SIZE(sys_rt_heap_map),
-		.map = sys_rt_heap_map,
-		.heap = HEAP_SYS_RUNTIME_BASE,
-		.size = HEAP_SYS_RUNTIME_SIZE,
-		.info = {.free = HEAP_SYS_RUNTIME_SIZE,},
-		.caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_CACHE |
-			SOF_MEM_CAPS_DMA,
-	},
-	.runtime[0] = {
-		.blocks = ARRAY_SIZE(rt_heap_map),
-		.map = rt_heap_map,
-		.heap = HEAP_RUNTIME_BASE,
-		.size = HEAP_RUNTIME_SIZE,
-		.info = {.free = HEAP_RUNTIME_SIZE,},
-		.caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_CACHE |
-			SOF_MEM_CAPS_DMA,
-	},
-	.buffer[0] = {
-		.blocks = ARRAY_SIZE(buf_heap_map),
-		.map = buf_heap_map,
-		.heap = HEAP_BUFFER_BASE,
-		.size = HEAP_BUFFER_SIZE,
-		.info = {.free = HEAP_BUFFER_SIZE,},
-		.caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_CACHE |
-			SOF_MEM_CAPS_DMA,
-	},
-	.total = {.free = HEAP_SYSTEM_SIZE + HEAP_SYS_RUNTIME_SIZE +
-			HEAP_RUNTIME_SIZE + HEAP_BUFFER_SIZE,},
-};
-
-void platform_init_memmap(struct sof *sof)
-{
-	/* memmap has been initialized statically as a part of .data */
-	sof->memory_map = &memmap;
-}
diff --git a/src/platform/mt8196/mt8196.x.in b/src/platform/mt8196/mt8196.x.in
deleted file mode 100644
index 939779d8f120..000000000000
--- a/src/platform/mt8196/mt8196.x.in
+++ /dev/null
@@ -1,554 +0,0 @@
-/*
- * Linker Script for mt8196 MediaTek
- *
- * This script is run through the GNU C preprocessor to align the memory
- * offsets with headers.
- *
- * Use spaces for formatting as cpp ignore tab sizes.
- */
-
-
-#include <sof/lib/memory.h>
-#include <xtensa/config/core-isa.h>
-
-#if CONFIG_MEDIATEK_DRAM_IMAGE
-#define IMAGE_LOC sof_dram
-#else
-#define IMAGE_LOC sof_sram
-#endif
-
-OUTPUT_ARCH(xtensa)
-
-MEMORY
-{
-  vector_reset_text :
-        org = XCHAL_RESET_VECTOR0_PADDR,
-        len = SOF_MEM_RESET_TEXT_SIZE
-  vector_reset_lit :
-        org = XCHAL_RESET_VECTOR0_PADDR + SOF_MEM_RESET_TEXT_SIZE,
-        len = SOF_MEM_RESET_LIT_SIZE
-  vector_base_text :
-        org = XCHAL_VECBASE_RESET_PADDR,
-        len = SOF_MEM_VECBASE_LIT_SIZE
-  vector_int2_lit :
-        org = XCHAL_INTLEVEL2_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
-        len = SOF_MEM_VECT_LIT_SIZE
-  vector_int2_text :
-        org = XCHAL_INTLEVEL2_VECTOR_PADDR,
-        len = SOF_MEM_VECT_TEXT_SIZE
-  vector_int3_lit :
-        org = XCHAL_INTLEVEL3_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
-        len = SOF_MEM_VECT_LIT_SIZE
-  vector_int3_text :
-        org = XCHAL_INTLEVEL3_VECTOR_PADDR,
-        len = SOF_MEM_VECT_TEXT_SIZE
-  vector_int4_lit :
-        org = XCHAL_INTLEVEL4_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
-        len = SOF_MEM_VECT_LIT_SIZE
-  vector_int4_text :
-        org = XCHAL_INTLEVEL4_VECTOR_PADDR,
-        len = SOF_MEM_VECT_TEXT_SIZE
-  vector_int5_lit :
-        org = XCHAL_INTLEVEL5_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
-        len = SOF_MEM_VECT_LIT_SIZE
-  vector_int5_text :
-        org = XCHAL_INTLEVEL5_VECTOR_PADDR,
-        len = SOF_MEM_VECT_TEXT_SIZE
-  vector_kernel_lit :
-        org = XCHAL_KERNEL_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
-        len = SOF_MEM_VECT_LIT_SIZE
-  vector_kernel_text :
-        org = XCHAL_KERNEL_VECTOR_PADDR,
-        len = SOF_MEM_VECT_TEXT_SIZE
-  vector_user_lit :
-        org = XCHAL_USER_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
-        len = SOF_MEM_VECT_LIT_SIZE
-  vector_user_text :
-        org = XCHAL_USER_VECTOR_PADDR,
-        len = SOF_MEM_VECT_TEXT_SIZE
-  vector_double_lit :
-        org = XCHAL_DOUBLEEXC_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
-        len = SOF_MEM_VECT_LIT_SIZE
-  vector_double_text :
-        org = XCHAL_DOUBLEEXC_VECTOR_PADDR,
-        len = SOF_MEM_VECT_TEXT_SIZE
-  sof_sram :
-        org = SRAM_START,
-        len = SRAM_SIZE
-  sof_dram :
-        org = SOF_DRAM_BASE,
-        len = SOF_DRAM_SIZE
-  system_heap :
-        org = HEAP_SYSTEM_BASE,
-        len = HEAP_SYSTEM_SIZE
-  system_runtime_heap :
-        org = HEAP_SYS_RUNTIME_BASE,
-        len = HEAP_SYS_RUNTIME_SIZE
-  runtime_heap :
-        org = HEAP_RUNTIME_BASE,
-        len = HEAP_RUNTIME_SIZE
-  buffer_heap :
-        org = HEAP_BUFFER_BASE,
-        len = HEAP_BUFFER_SIZE
-  sof_stack :
-        org = SOF_STACK_END,
-        len = SOF_STACK_BASE - SOF_STACK_END
-  static_uuid_entries_seg (!ari) :
-        org = UUID_ENTRY_ELF_BASE,
-        len = UUID_ENTRY_ELF_SIZE
-  static_log_entries_seg (!ari) :
-        org = LOG_ENTRY_ELF_BASE,
-        len = LOG_ENTRY_ELF_SIZE
-  fw_metadata_seg (!ari) :
-        org = EXT_MANIFEST_ELF_BASE,
-        len = EXT_MANIFEST_ELF_SIZE
-}
-
-PHDRS
-{
-  vector_reset_text_phdr PT_LOAD;
-  vector_reset_lit_phdr PT_LOAD;
-  vector_base_text_phdr PT_LOAD;
-  vector_base_lit_phdr PT_LOAD;
-  vector_int2_text_phdr PT_LOAD;
-  vector_int2_lit_phdr PT_LOAD;
-  vector_int3_text_phdr PT_LOAD;
-  vector_int3_lit_phdr PT_LOAD;
-  vector_int4_text_phdr PT_LOAD;
-  vector_int4_lit_phdr PT_LOAD;
-  vector_int5_text_phdr PT_LOAD;
-  vector_int5_lit_phdr PT_LOAD;
-  vector_kernel_text_phdr PT_LOAD;
-  vector_kernel_lit_phdr PT_LOAD;
-  vector_user_text_phdr PT_LOAD;
-  vector_user_lit_phdr PT_LOAD;
-  vector_double_text_phdr PT_LOAD;
-  vector_double_lit_phdr PT_LOAD;
-  sof_sram_phdr PT_LOAD;
-  system_heap_phdr PT_LOAD;
-  system_runtime_heap_phdr PT_LOAD;
-  runtime_heap_phdr PT_LOAD;
-  buffer_heap_phdr PT_LOAD;
-  sof_stack_phdr PT_LOAD;
-  static_uuid_entries_phdr PT_NOTE;
-  static_log_entries_phdr PT_NOTE;
-  metadata_entries_phdr PT_NOTE;
-}
-
-/*  Default entry point:  */
-ENTRY(_ResetVector)
-_rom_store_table = 0;
-
-/* ABI0 does not use Window base */
-PROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR);
-
-/* Various memory-map dependent cache attribute settings: */
-_memmap_cacheattr_wb_base = 0x00000404;
-_memmap_cacheattr_wt_base = 0x00000404;
-_memmap_cacheattr_bp_base = 0x00000404;
-_memmap_cacheattr_unused_mask = 0xFFFFF0FF;
-_memmap_cacheattr_wb_trapnull = 0x44444444;
-_memmap_cacheattr_wba_trapnull = 0x44444444;
-_memmap_cacheattr_wbna_trapnull = 0x44444444;
-_memmap_cacheattr_wt_trapnull = 0x44444444;
-_memmap_cacheattr_bp_trapnull = 0x44444444;
-_memmap_cacheattr_wb_strict = 0x00000404;
-_memmap_cacheattr_wt_strict = 0x00000404;
-_memmap_cacheattr_bp_strict = 0x00000404;
-_memmap_cacheattr_wb_allvalid = 0x44444444;
-_memmap_cacheattr_wt_allvalid = 0x44444444;
-_memmap_cacheattr_bp_allvalid = 0x44444444;
-PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);
-
-_EXT_MAN_ALIGN_ = 16;
-EXTERN(ext_man_fw_ver)
-
-SECTIONS
-{
-  .ResetVector.text : ALIGN(4)
-  {
-    _ResetVector_text_start = ABSOLUTE(.);
-    KEEP (*(.ResetVector.text))
-    _ResetVector_text_end = ABSOLUTE(.);
-  } >vector_reset_text :vector_reset_text_phdr
-
-  .ResetVector.literal : ALIGN(4)
-  {
-    _ResetVector_literal_start = ABSOLUTE(.);
-    *(.ResetVector.literal)
-    _ResetVector_literal_end = ABSOLUTE(.);
-  } >vector_reset_lit :vector_reset_lit_phdr
-
-  .WindowVectors.text : ALIGN(4)
-  {
-    _WindowVectors_text_start = ABSOLUTE(.);
-    KEEP (*(.WindowVectors.text))
-    _WindowVectors_text_end = ABSOLUTE(.);
-  } >vector_base_text :vector_base_text_phdr
-
-  .Level2InterruptVector.literal : ALIGN(4)
-  {
-    _Level2InterruptVector_literal_start = ABSOLUTE(.);
-    *(.Level2InterruptVector.literal)
-    _Level2InterruptVector_literal_end = ABSOLUTE(.);
-  } >vector_int2_lit :vector_int2_lit_phdr
-
-  .Level2InterruptVector.text : ALIGN(4)
-  {
-    _Level2InterruptVector_text_start = ABSOLUTE(.);
-    KEEP (*(.Level2InterruptVector.text))
-    _Level2InterruptVector_text_end = ABSOLUTE(.);
-  } >vector_int2_text :vector_int2_text_phdr
-
-  .Level3InterruptVector.literal : ALIGN(4)
-  {
-    _Level3InterruptVector_literal_start = ABSOLUTE(.);
-    *(.Level3InterruptVector.literal)
-    _Level3InterruptVector_literal_end = ABSOLUTE(.);
-  } >vector_int3_lit :vector_int3_lit_phdr
-
-  .Level3InterruptVector.text : ALIGN(4)
-  {
-    _Level3InterruptVector_text_start = ABSOLUTE(.);
-    KEEP (*(.Level3InterruptVector.text))
-    _Level3InterruptVector_text_end = ABSOLUTE(.);
-  } >vector_int3_text :vector_int3_text_phdr
-
-  .Level4InterruptVector.literal : ALIGN(4)
-  {
-    _Level4InterruptVector_literal_start = ABSOLUTE(.);
-    *(.Level4InterruptVector.literal)
-    _Level4InterruptVector_literal_end = ABSOLUTE(.);
-  } >vector_int4_lit :vector_int4_lit_phdr
-
-  .Level4InterruptVector.text : ALIGN(4)
-  {
-    _Level4InterruptVector_text_start = ABSOLUTE(.);
-    KEEP (*(.Level4InterruptVector.text))
-    _Level4InterruptVector_text_end = ABSOLUTE(.);
-  } >vector_int4_text :vector_int4_text_phdr
-
-  .DebugExceptionVector.literal : ALIGN(4)
-  {
-    _DebugExceptionVector_literal_start = ABSOLUTE(.);
-    *(.DebugExceptionVector.literal)
-    _DebugExceptionVector_literal_end = ABSOLUTE(.);
-  } >vector_int5_lit :vector_int5_lit_phdr
-
-  .DebugExceptionVector.text : ALIGN(4)
-  {
-    _DebugExceptionVector_text_start = ABSOLUTE(.);
-    KEEP (*(.DebugExceptionVector.text))
-    _DebugExceptionVector_text_end = ABSOLUTE(.);
-  } >vector_int5_text :vector_int5_text_phdr
-
-  .NMIExceptionVector.literal : ALIGN(4)
-  {
-    _NMIExceptionVector_literal_start = ABSOLUTE(.);
-    *(.NMIExceptionVector.literal)
-    _NMIExceptionVector_literal_end = ABSOLUTE(.);
-  } >vector_int5_lit :vector_int5_lit_phdr
-
-  .NMIExceptionVector.text : ALIGN(4)
-  {
-    _NMIExceptionVector_text_start = ABSOLUTE(.);
-    KEEP (*(.NMIExceptionVector.text))
-    _NMIExceptionVector_text_end = ABSOLUTE(.);
-  } >vector_int5_text :vector_int5_text_phdr
-
-  .KernelExceptionVector.literal : ALIGN(4)
-  {
-    _KernelExceptionVector_literal_start = ABSOLUTE(.);
-    *(.KernelExceptionVector.literal)
-    _KernelExceptionVector_literal_end = ABSOLUTE(.);
-  } >vector_kernel_lit :vector_kernel_lit_phdr
-
-  .KernelExceptionVector.text : ALIGN(4)
-  {
-    _KernelExceptionVector_text_start = ABSOLUTE(.);
-    KEEP (*(.KernelExceptionVector.text))
-    _KernelExceptionVector_text_end = ABSOLUTE(.);
-  } >vector_kernel_text :vector_kernel_text_phdr
-
-  .UserExceptionVector.literal : ALIGN(4)
-  {
-    _UserExceptionVector_literal_start = ABSOLUTE(.);
-    *(.UserExceptionVector.literal)
-    _UserExceptionVector_literal_end = ABSOLUTE(.);
-  } >vector_user_lit :vector_user_lit_phdr
-
-  .UserExceptionVector.text : ALIGN(4)
-  {
-    _UserExceptionVector_text_start = ABSOLUTE(.);
-    KEEP (*(.UserExceptionVector.text))
-    _UserExceptionVector_text_end = ABSOLUTE(.);
-  } >vector_user_text :vector_user_text_phdr
-
-  .DoubleExceptionVector.literal : ALIGN(4)
-  {
-    _DoubleExceptionVector_literal_start = ABSOLUTE(.);
-    *(.DoubleExceptionVector.literal)
-    _DoubleExceptionVector_literal_end = ABSOLUTE(.);
-  } >vector_double_lit :vector_double_lit_phdr
-
-  .DoubleExceptionVector.text : ALIGN(4)
-  {
-    _DoubleExceptionVector_text_start = ABSOLUTE(.);
-    KEEP (*(.DoubleExceptionVector.text))
-    _DoubleExceptionVector_text_end = ABSOLUTE(.);
-  } >vector_double_text :vector_double_text_phdr
-
-  .fw_ready : ALIGN(4)
-  {
-    KEEP (*(.fw_ready))
-    KEEP (*(.fw_ready_metadata))
-  } >IMAGE_LOC :sof_sram_phdr
-
-  .rodata : ALIGN(4)
-  {
-    _rodata_start = ABSOLUTE(.);
-    *(.rodata)
-    *(.rodata.*)
-    *(.gnu.linkonce.r.*)
-    *(.rodata1)
-    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);
-    KEEP (*(.xt_except_table))
-    KEEP (*(.gcc_except_table))
-    *(.gnu.linkonce.e.*)
-    *(.gnu.version_r)
-    KEEP (*(.eh_frame))
-    /*  C++ constructor and destructor tables, properly ordered:  */
-    KEEP (*crtbegin.o(.ctors))
-    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
-    KEEP (*(SORT(.ctors.*)))
-    KEEP (*(.ctors))
-    KEEP (*crtbegin.o(.dtors))
-    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
-    KEEP (*(SORT(.dtors.*)))
-    KEEP (*(.dtors))
-    /*  C++ exception handlers table:  */
-    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);
-    *(.xt_except_desc)
-    *(.gnu.linkonce.h.*)
-    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
-    *(.xt_except_desc_end)
-    *(.dynamic)
-    *(.gnu.version_d)
-    . = ALIGN(4);		/* this table MUST be 4-byte aligned */
-    _bss_table_start = ABSOLUTE(.);
-    LONG(_bss_start)
-    LONG(_bss_end)
-    _bss_table_end = ABSOLUTE(.);
-    _rodata_end = ABSOLUTE(.);
-  } >IMAGE_LOC :sof_sram_phdr
-
-  .module_init : ALIGN(4)
-  {
-   _module_init_start = ABSOLUTE(.);
-    *(*.initcall)
-    _module_init_end = ABSOLUTE(.);
-  } >IMAGE_LOC :sof_sram_phdr
-
-  .text : ALIGN(4)
-  {
-    _stext = .;
-    _text_start = ABSOLUTE(.);
-    *(.entry.text)
-    *(.init.literal)
-    KEEP(*(.init))
-    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
-    *(.fini.literal)
-    KEEP(*(.fini))
-    *(.gnu.version)
-    _text_end = ABSOLUTE(.);
-    _etext = .;
-  } >IMAGE_LOC :sof_sram_phdr
-
-  .reset.rodata : ALIGN(4)
-  {
-    _reset_rodata_start = ABSOLUTE(.);
-    *(.reset.rodata)
-    _reset_rodata_end = ABSOLUTE(.);
-  } >IMAGE_LOC :sof_sram_phdr
-
-
-  .data : ALIGN(4)
-  {
-    _data_start = ABSOLUTE(.);
-    *(.data)
-    *(.data.*)
-    *(.gnu.linkonce.d.*)
-    KEEP(*(.gnu.linkonce.d.*personality*))
-    *(.data1)
-    *(.sdata)
-    *(.sdata.*)
-    *(.gnu.linkonce.s.*)
-    *(.sdata2)
-    *(.sdata2.*)
-    *(.gnu.linkonce.s2.*)
-    KEEP(*(.jcr))
-    _trace_ctx_start = ABSOLUTE(.);
-    *(.trace_ctx)
-    _trace_ctx_end = ABSOLUTE(.);
-    _data_end = ABSOLUTE(.);
-  } >IMAGE_LOC :sof_sram_phdr
-
-  .lit4 : ALIGN(4)
-  {
-    _lit4_start = ABSOLUTE(.);
-    *(*.lit4)
-    *(.lit4.*)
-    *(.gnu.linkonce.lit4.*)
-    _lit4_end = ABSOLUTE(.);
-  } >IMAGE_LOC :sof_sram_phdr
-
-  .bss (NOLOAD) : ALIGN(8)
-  {
-    . = ALIGN (8);
-    _bss_start = ABSOLUTE(.);
-    *(.dynsbss)
-    *(.sbss)
-    *(.sbss.*)
-    *(.gnu.linkonce.sb.*)
-    *(.scommon)
-    *(.sbss2)
-    *(.sbss2.*)
-    *(.gnu.linkonce.sb2.*)
-    *(.dynbss)
-    *(.bss)
-    *(.bss.*)
-    *(.gnu.linkonce.b.*)
-    *(COMMON)
-    . = ALIGN (8);
-    _bss_end = ABSOLUTE(.);
-  } >IMAGE_LOC :sof_sram_phdr
-
-  /* stack */
-  _end = SOF_STACK_END;
-  PROVIDE(end = SOF_STACK_END);
-  _stack_sentry = SOF_STACK_END;
-  __stack = SOF_STACK_BASE;
-
-  .debug  0 :  { *(.debug) }
-  .line  0 :  { *(.line) }
-  .debug_srcinfo  0 :  { *(.debug_srcinfo) }
-  .debug_sfnames  0 :  { *(.debug_sfnames) }
-  .debug_aranges  0 :  { *(.debug_aranges) }
-  .debug_ranges   0 :  { *(.debug_ranges) }
-  .debug_pubnames  0 :  { *(.debug_pubnames) }
-  .debug_info  0 :  { *(.debug_info) }
-  .debug_abbrev  0 :  { *(.debug_abbrev) }
-  .debug_line  0 :  { *(.debug_line) }
-  .debug_frame  0 :  { *(.debug_frame) }
-  .debug_str  0 :  { *(.debug_str) }
-  .debug_loc  0 :  { *(.debug_loc) }
-  .debug_macinfo  0 :  { *(.debug_macinfo) }
-  .debug_weaknames  0 :  { *(.debug_weaknames) }
-  .debug_funcnames  0 :  { *(.debug_funcnames) }
-  .debug_typenames  0 :  { *(.debug_typenames) }
-  .debug_varnames  0 :  { *(.debug_varnames) }
-
-  .xt.insn 0 :
-  {
-    KEEP (*(.xt.insn))
-    KEEP (*(.gnu.linkonce.x.*))
-  }
-  .xt.prop 0 :
-  {
-    KEEP (*(.xt.prop))
-    KEEP (*(.xt.prop.*))
-    KEEP (*(.gnu.linkonce.prop.*))
-  }
-  .xt.lit 0 :
-  {
-    KEEP (*(.xt.lit))
-    KEEP (*(.xt.lit.*))
-    KEEP (*(.gnu.linkonce.p.*))
-  }
-  .xt.profile_range 0 :
-  {
-    KEEP (*(.xt.profile_range))
-    KEEP (*(.gnu.linkonce.profile_range.*))
-  }
-  .xt.profile_ranges 0 :
-  {
-    KEEP (*(.xt.profile_ranges))
-    KEEP (*(.gnu.linkonce.xt.profile_ranges.*))
-  }
-  .xt.profile_files 0 :
-  {
-    KEEP (*(.xt.profile_files))
-    KEEP (*(.gnu.linkonce.xt.profile_files.*))
-  }
-
-  .xtensa.info 0 :
-  {
-    *(.xtensa.info)
-  }
-
-  .comment 0 :
-  {
-    KEEP(*(.comment))
-  }
-
-  .note.GNU-stack 0 :
-  {
-    *(.note.GNU-stack)
-  }
-
-  .system_heap (NOLOAD) : ALIGN(8)
-  {
-    . = ALIGN (32);
-    _system_heap_start = ABSOLUTE(.);
-    . = . + HEAP_SYSTEM_SIZE;
-    _system_heap_end = ABSOLUTE(.);
-  } >system_heap :system_heap_phdr
-
-  .system_runtime_heap (NOLOAD) : ALIGN(8)
-  {
-    . = ALIGN (HEAP_BUF_ALIGNMENT);
-    _system_runtime_heap_start = ABSOLUTE(.);
-    . = . + HEAP_SYS_RUNTIME_SIZE;
-    _system_runtime_heap_end = ABSOLUTE(.);
-  } >system_runtime_heap :system_runtime_heap_phdr
-
-  .runtime_heap (NOLOAD) : ALIGN(8)
-  {
-    . = ALIGN (32);
-    _runtime_heap_start = ABSOLUTE(.);
-    . = . + HEAP_RUNTIME_SIZE;
-    _runtime_heap_end = ABSOLUTE(.);
-  } >runtime_heap :runtime_heap_phdr
-
-  .buffer_heap (NOLOAD) : ALIGN(8)
-  {
-    . = ALIGN (HEAP_BUF_ALIGNMENT);
-    _buffer_heap_start = ABSOLUTE(.);
-    . = . + HEAP_BUFFER_SIZE;
-    _buffer_heap_end = ABSOLUTE(.);
-  } >buffer_heap :buffer_heap_phdr
-
-  .sof_stack (NOLOAD) : ALIGN(8)
-  {
-    . = ALIGN (4096);
-    _sof_stack_start = ABSOLUTE(.);
-    . = . + SOF_STACK_TOTAL_SIZE;
-    _sof_stack_end = ABSOLUTE(.);
-  } >sof_stack :sof_stack_phdr
-
-  .static_uuid_entries (COPY) : ALIGN(1024)
-  {
-    *(*.static_uuids)
-  } > static_uuid_entries_seg :static_uuid_entries_phdr
-
-  .static_log_entries (COPY) : ALIGN(1024)
-  {
-    *(*.static_log*)
-  } > static_log_entries_seg :static_log_entries_phdr
-
-  .fw_metadata (COPY) : ALIGN(1024)
-  {
-    KEEP (*(.fw_metadata))
-    . = ALIGN(_EXT_MAN_ALIGN_);
-  } >fw_metadata_seg :metadata_entries_phdr
-}
diff --git a/src/platform/mt8196/platform.c b/src/platform/mt8196/platform.c
deleted file mode 100644
index 8cb188ce2210..000000000000
--- a/src/platform/mt8196/platform.c
+++ /dev/null
@@ -1,217 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-/*
- * Copyright(c) 2024 MediaTek. All rights reserved.
- *
- * Author: Hailong Fan <hailong.fan@mediatek.com>
- *         Darren Ye <darren.ye@mediatek.com>
- */
-
-#include <errno.h>
-#include <ipc/header.h>
-#include <ipc/info.h>
-#include <kernel/abi.h>
-#include <kernel/ext_manifest.h>
-#include <platform/drivers/timer.h>
-#include <rtos/clk.h>
-#include <rtos/timer.h>
-#include <rtos/interrupt.h>
-#include <sof/compiler_info.h>
-#include <sof/debug/debug.h>
-#include <sof/drivers/edma.h>
-#include <sof/ipc/msg.h>
-#include <sof/fw-ready-metadata.h>
-#include <sof/lib/agent.h>
-#include <sof/lib/cpu.h>
-#include <sof/lib/dai.h>
-#include <sof/lib/dma.h>
-#include <sof/lib/mailbox.h>
-#include <sof/lib/memory.h>
-#include <sof/lib/mm_heap.h>
-#include <sof/platform.h>
-#include <sof/schedule/edf_schedule.h>
-#include <sof/schedule/ll_schedule.h>
-#include <sof/schedule/ll_schedule_domain.h>
-#include <rtos/sof.h>
-#include <sof/trace/dma-trace.h>
-#include <sof_versions.h>
-#include <stdint.h>
-#include <xtensa/hal.h>
-
-struct sof;
-
-static const struct sof_ipc_fw_ready ready
-	__section(".fw_ready") = {
-	.hdr = {
-		.cmd = SOF_IPC_FW_READY,
-		.size = sizeof(struct sof_ipc_fw_ready),
-	},
-	/* dspbox is for DSP initiated IPC, hostbox is for host initiated IPC */
-	.version = {
-		.hdr.size = sizeof(struct sof_ipc_fw_version),
-		.micro = SOF_MICRO,
-		.minor = SOF_MINOR,
-		.major = SOF_MAJOR,
-		.tag = SOF_TAG,
-		.abi_version = SOF_ABI_VERSION,
-		.src_hash = SOF_SRC_HASH,
-	},
-	.flags = DEBUG_SET_FW_READY_FLAGS,
-};
-
-#define NUM_MTK_WINDOWS 6
-
-const struct ext_man_windows xsram_window
-		__aligned(EXT_MAN_ALIGN) __section(".fw_metadata") __unused = {
-	.hdr = {
-		.type = EXT_MAN_ELEM_WINDOW,
-		.elem_size = ALIGN_UP_COMPILE(sizeof(struct ext_man_windows), EXT_MAN_ALIGN),
-	},
-	.window = {
-		.ext_hdr	= {
-			.hdr.cmd = SOF_IPC_FW_READY,
-			.hdr.size = sizeof(struct sof_ipc_window),
-			.type	= SOF_IPC_EXT_WINDOW,
-		},
-		.num_windows	= NUM_MTK_WINDOWS,
-		.window	= {
-			{
-				.type	= SOF_IPC_REGION_UPBOX,
-				.id	= 0,	/* map to host window 0 */
-				.flags	= 0,
-				.size	= MAILBOX_DSPBOX_SIZE,
-				.offset	= MAILBOX_DSPBOX_OFFSET,
-			},
-			{
-				.type	= SOF_IPC_REGION_DOWNBOX,
-				.id	= 0,	/* map to host window 0 */
-				.flags	= 0,
-				.size	= MAILBOX_HOSTBOX_SIZE,
-				.offset	= MAILBOX_HOSTBOX_OFFSET,
-			},
-			{
-				.type	= SOF_IPC_REGION_DEBUG,
-				.id	= 0,	/* map to host window 0 */
-				.flags	= 0,
-				.size	= MAILBOX_DEBUG_SIZE,
-				.offset	= MAILBOX_DEBUG_OFFSET,
-			},
-			{
-				.type	= SOF_IPC_REGION_TRACE,
-				.id	= 0,	/* map to host window 0 */
-				.flags	= 0,
-				.size	= MAILBOX_TRACE_SIZE,
-				.offset	= MAILBOX_TRACE_OFFSET,
-			},
-			{
-				.type	= SOF_IPC_REGION_STREAM,
-				.id	= 0,	/* map to host window 0 */
-				.flags	= 0,
-				.size	= MAILBOX_STREAM_SIZE,
-				.offset	= MAILBOX_STREAM_OFFSET,
-			},
-			{
-				.type	= SOF_IPC_REGION_EXCEPTION,
-				.id	= 0,	/* map to host window 0 */
-				.flags	= 0,
-				.size	= MAILBOX_EXCEPTION_SIZE,
-				.offset	= MAILBOX_EXCEPTION_OFFSET,
-			},
-		},
-	}
-};
-
-static struct timer timer_shared = {
-	.id = OSTIMER0,
-	.irq = MTK_DSP_IRQ_OSTIMER32_C0,
-};
-
-/* Override the default MPU setup. This table matches the memory map
- * of the 'sample_controller' core and will need to be modified for
- * other cores.
- * NOTE: This table sets up all of external memory as shared uncached.
- * For best results, edit the LSP memory map to create a separate
- * section in shared memory, place all sections that need to be uncached
- * into that section, and only map that section uncached. See README
- * for more details.
- */
-const struct xthal_MPU_entry __xt_mpu_init_table[] __section(".ResetVector.text") = {
-	XTHAL_MPU_ENTRY(0x00000000, 1, XTHAL_AR_RWXrwx, XTHAL_MEM_DEVICE),		// infra
-	XTHAL_MPU_ENTRY(0x10000000, 1, XTHAL_AR_RWXrwx, XTHAL_MEM_DEVICE),		// infra
-	XTHAL_MPU_ENTRY(0x1a000000, 1, XTHAL_AR_RWXrwx, XTHAL_MEM_DEVICE),		// cfg
-	XTHAL_MPU_ENTRY(0x1a110000, 1, XTHAL_AR_RWXrwx, XTHAL_MEM_DEVICE),		// audio
-	XTHAL_MPU_ENTRY(0x4e100000, 1, XTHAL_AR_RWXrwx, XTHAL_MEM_WRITEBACK),		// sram
-	XTHAL_MPU_ENTRY(0x4e180000, 1, XTHAL_AR_NONE, XTHAL_MEM_DEVICE),		// unused
-	XTHAL_MPU_ENTRY(0x90000000, 1, XTHAL_AR_RWXrwx, XTHAL_MEM_WRITEBACK),	// dram
-	XTHAL_MPU_ENTRY(0x90500000, 1, XTHAL_AR_RWXrwx, XTHAL_MEM_NON_CACHEABLE),	// dram
-	XTHAL_MPU_ENTRY(0x90900000, 1, XTHAL_AR_NONE, XTHAL_MEM_DEVICE),		// unused
-};
-
-const unsigned int __xt_mpu_init_table_size __section(".ResetVector.text") =
-	ARRAY_SIZE(__xt_mpu_init_table);
-
-int platform_boot_complete(uint32_t boot_message)
-{
-	mailbox_dspbox_write(0, &ready, sizeof(ready));
-	/* now interrupt host to tell it we are done booting */
-	trigger_irq_to_host_req();
-
-	return 0;
-}
-
-int platform_init(struct sof *sof)
-{
-	int ret;
-
-	sof->platform_timer = &timer_shared;
-	sof->cpu_timers = sof->platform_timer;
-	platform_interrupt_init();
-	platform_clock_init(sof);
-
-	scheduler_init_edf();
-
-	/* init low latency domains and schedulers */
-	sof->platform_timer_domain = timer_domain_init(sof->platform_timer, PLATFORM_DEFAULT_CLOCK);
-	scheduler_init_ll(sof->platform_timer_domain);
-	platform_timer_start(sof->platform_timer);
-	sa_init(sof, CONFIG_SYSTICK_PERIOD);
-
-	/* init DMA */
-	ret = dmac_init(sof);
-	if (ret < 0)
-		return -ENODEV;
-
-	/* Init platform domain */
-	sof->platform_dma_domain = dma_multi_chan_domain_init(&sof->dma_info->dma_array[0], 1,
-							      PLATFORM_DEFAULT_CLOCK, false);
-
-	scheduler_init_ll(sof->platform_dma_domain);
-
-	/* initialize the host IPC mechanisms */
-	ipc_init(sof);
-
-	ret = dai_init(sof);
-	if (ret < 0)
-		return ret;
-
-#if CONFIG_TRACE
-	/* Initialize DMA for Trace*/
-	trace_point(TRACE_BOOT_PLATFORM_DMA_TRACE);
-	dma_trace_init_complete(sof->dmat);
-#endif
-
-	/* show heap status */
-	heap_trace_all(1);
-
-	return 0;
-}
-
-int platform_context_save(struct sof *sof)
-{
-	return 0;
-}
-
-void platform_wait_for_interrupt(int level)
-{
-	arch_wait_for_interrupt(level);
-}
-
diff --git a/src/platform/mt8365/CMakeLists.txt b/src/platform/mt8365/CMakeLists.txt
deleted file mode 100644
index 4091be2eeaff..000000000000
--- a/src/platform/mt8365/CMakeLists.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-
-add_subdirectory(lib)
-
-add_local_sources(sof platform.c afe-platform.c)
-target_include_directories(sof_options INTERFACE ${PROJECT_SOURCE_DIR}/src/platform/mt8365/include/arch)
-target_include_directories(sof_options INTERFACE ${PROJECT_SOURCE_DIR}/src/platform/mt8365/include/platform)
diff --git a/src/platform/mt8365/afe-platform.c b/src/platform/mt8365/afe-platform.c
deleted file mode 100644
index 1255972479ce..000000000000
--- a/src/platform/mt8365/afe-platform.c
+++ /dev/null
@@ -1,336 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-/*
- * Copyright(c) 2024 MediaTek. All rights reserved.
- *
- * Author: Andrew Perepech <andrew.perepech@mediatek.com>
- */
-
-#include <sof/common.h>
-#include <errno.h>
-#include <sof/drivers/afe-drv.h>
-#include <mt8365-afe-regs.h>
-#include <mt8365-afe-common.h>
-
-/*
- * AFE: Audio Front-End
- *
- * frontend (memif):
- *   memory interface
- *   AWB, VULx, TDM_IN (uplink for capture)
- *   DLx, TDM_OUT (downlink for playback)
- * backend:
- *   TDM In
- *   TMD out
- *   DMIC
- *   GASRC
- *   etc.
- * interconn:
- *   inter-connection,
- *   connect frontends and backends as DSP path
- */
-
-static const struct mtk_base_memif_data memif_data[MT8365_MEMIF_NUM] = {
-	[MT8365_MEMIF_DL1] = {
-		.name = "DL1",
-		.id = MT8365_MEMIF_DL1,
-		.reg_ofs_base = AFE_DL1_BASE,
-		.reg_ofs_cur = AFE_DL1_CUR,
-		.reg_ofs_end = AFE_DL1_END,
-		.fs_reg = AFE_DAC_CON1,
-		.fs_shift = 0,
-		.fs_maskbit = 0xf,
-		.mono_reg = AFE_DAC_CON1,
-		.mono_shift = 21,
-		.enable_reg = AFE_DAC_CON0,
-		.enable_shift = 1,
-		.hd_reg = AFE_MEMIF_PBUF_SIZE,
-		.hd_shift = 16,
-		.agent_disable_reg = -1,
-		.agent_disable_shift = 0,
-		.ch_num_reg = -1,
-		.ch_num_shift = 0,
-		.ch_num_maskbit = 0,
-		.msb_reg = -1,
-		.msb_shift = 0,
-		.msb2_reg = -1,
-		.msb2_shift = 0,
-	},
-	[MT8365_MEMIF_DL2] = {
-		.name = "DL2",
-		.id = MT8365_MEMIF_DL2,
-		.reg_ofs_base = AFE_DL2_BASE,
-		.reg_ofs_cur = AFE_DL2_CUR,
-		.reg_ofs_end = AFE_DL2_END,
-		.fs_reg = AFE_DAC_CON1,
-		.fs_shift = 4,
-		.fs_maskbit = 0xf,
-		.mono_reg = AFE_DAC_CON1,
-		.mono_shift = 22,
-		.enable_reg = AFE_DAC_CON0,
-		.enable_shift = 2,
-		.hd_reg = AFE_MEMIF_PBUF_SIZE,
-		.hd_shift = 18,
-		.agent_disable_reg = -1,
-		.agent_disable_shift = 0,
-		.ch_num_reg = -1,
-		.ch_num_shift = 0,
-		.ch_num_maskbit = 0,
-		.msb_reg = -1,
-		.msb_shift = 0,
-		.msb2_reg = -1,
-		.msb2_shift = 0,
-	},
-	[MT8365_MEMIF_TDM_OUT] = {
-		.name = "TDM_OUT",
-		.id = MT8365_MEMIF_DL2,
-		.reg_ofs_base = AFE_HDMI_OUT_BASE,
-		.reg_ofs_cur = AFE_HDMI_OUT_CUR,
-		.reg_ofs_end = AFE_HDMI_OUT_END,
-		.fs_reg = -1,
-		.fs_shift = 0,
-		.fs_maskbit = 0,
-		.mono_reg = -1,
-		.mono_shift = 0,
-		.enable_reg = AFE_HDMI_OUT_CON0,
-		.enable_shift = 0,
-		.hd_reg = AFE_MEMIF_PBUF_SIZE,
-		.hd_shift = 28,
-		.agent_disable_reg = -1,
-		.agent_disable_shift = 0,
-		.ch_num_reg = -1,
-		.ch_num_shift = 0,
-		.ch_num_maskbit = 0,
-		.msb_reg = -1,
-		.msb_shift = 0,
-		.msb2_reg = -1,
-		.msb2_shift = 0,
-	},
-	[MT8365_MEMIF_AWB] = {
-		.name = "AWB",
-		.id = MT8365_MEMIF_AWB,
-		.reg_ofs_base = AFE_AWB_BASE,
-		.reg_ofs_cur = AFE_AWB_CUR,
-		.reg_ofs_end = AFE_AWB_END,
-		.fs_reg = AFE_DAC_CON1,
-		.fs_shift = 12,
-		.fs_maskbit = 0xf,
-		.mono_reg = AFE_DAC_CON1,
-		.mono_shift = 24,
-		.enable_reg = AFE_DAC_CON0,
-		.enable_shift = 6,
-		.hd_reg = AFE_MEMIF_PBUF_SIZE,
-		.hd_shift = 20,
-		.agent_disable_reg = -1,
-		.agent_disable_shift = 0,
-		.ch_num_reg = -1,
-		.ch_num_shift = 0,
-		.ch_num_maskbit = 0,
-		.msb_reg = AFE_MEMIF_MSB,
-		.msb_shift = 17,
-		.msb2_reg = -1,
-		.msb2_shift = 0,
-	},
-	[MT8365_MEMIF_VUL] = {
-		.name = "VUL",
-		.id = MT8365_MEMIF_VUL,
-		.reg_ofs_base = AFE_VUL_BASE,
-		.reg_ofs_cur = AFE_VUL_CUR,
-		.reg_ofs_end = AFE_VUL_END,
-		.fs_reg = AFE_DAC_CON1,
-		.fs_shift = 16,
-		.fs_maskbit = 0xf,
-		.mono_reg = AFE_DAC_CON1,
-		.mono_shift = 27,
-		.enable_reg = AFE_DAC_CON0,
-		.enable_shift = 3,
-		.hd_reg = AFE_MEMIF_PBUF_SIZE,
-		.hd_shift = 22,
-		.agent_disable_reg = -1,
-		.agent_disable_shift = 0,
-		.ch_num_reg = -1,
-		.ch_num_shift = 0,
-		.ch_num_maskbit = 0,
-		.msb_reg = AFE_MEMIF_MSB,
-		.msb_shift = 20,
-		.msb2_reg = -1,
-		.msb2_shift = 0,
-	},
-	[MT8365_MEMIF_VUL2] = {
-		.name = "VUL2",
-		.id = MT8365_MEMIF_VUL2,
-		.reg_ofs_base = AFE_VUL_D2_BASE,
-		.reg_ofs_cur = AFE_VUL_D2_CUR,
-		.reg_ofs_end = AFE_VUL_D2_END,
-		.fs_reg = AFE_DAC_CON0,
-		.fs_shift = 20,
-		.fs_maskbit = 0xf,
-		.mono_reg = AFE_DAC_CON0,
-		.mono_shift = 10,
-		.enable_reg = AFE_DAC_CON0,
-		.enable_shift = 9,
-		.hd_reg = AFE_MEMIF_PBUF_SIZE,
-		.hd_shift = 14,
-		.agent_disable_reg = -1,
-		.agent_disable_shift = 0,
-		.ch_num_reg = -1,
-		.ch_num_shift = 0,
-		.ch_num_maskbit = 0,
-		.msb_reg = AFE_MEMIF_MSB,
-		.msb_shift = 21,
-		.msb2_reg = -1,
-		.msb2_shift = 0,
-	},
-	[MT8365_MEMIF_VUL3] = {
-		.name = "VUL3",
-		.id = MT8365_MEMIF_VUL3,
-		.reg_ofs_base = AFE_VUL3_BASE,
-		.reg_ofs_cur = AFE_VUL3_CUR,
-		.reg_ofs_end = AFE_VUL3_END,
-		.fs_reg = AFE_DAC_CON1,
-		.fs_shift = 8,
-		.fs_maskbit = 0xf,
-		.mono_reg = AFE_DAC_CON0,
-		.mono_shift = 13,
-		.enable_reg = AFE_DAC_CON0,
-		.enable_shift = 12,
-		.hd_reg = AFE_MEMIF_PBUF2_SIZE,
-		.hd_shift = 10,
-		.agent_disable_reg = -1,
-		.agent_disable_shift = 0,
-		.ch_num_reg = -1,
-		.ch_num_shift = 0,
-		.ch_num_maskbit = 0,
-		.msb_reg = AFE_MEMIF_MSB,
-		.msb_shift = 27,
-		.msb2_reg = -1,
-		.msb2_shift = 0,
-	},
-	[MT8365_MEMIF_TDM_IN] = {
-		.name = "TDM_IN",
-		.id = MT8365_MEMIF_TDM_IN,
-		.reg_ofs_base = AFE_HDMI_IN_2CH_BASE,
-		.reg_ofs_cur = AFE_HDMI_IN_2CH_CUR,
-		.reg_ofs_end = AFE_HDMI_IN_2CH_END,
-		.fs_reg = -1,
-		.fs_shift = 0,
-		.fs_maskbit = 0,
-		.mono_reg = AFE_HDMI_IN_2CH_CON0,
-		.mono_shift = 1,
-		.enable_reg = AFE_HDMI_IN_2CH_CON0,
-		.enable_shift = 0,
-		.hd_reg = AFE_MEMIF_PBUF2_SIZE,
-		.hd_shift = 8,
-		.agent_disable_reg = -1,
-		.agent_disable_shift = 0,
-		.ch_num_reg = -1,
-		.ch_num_shift = 0,
-		.ch_num_maskbit = 0,
-		.msb_reg = AFE_MEMIF_MSB,
-		.msb_shift = 28,
-		.msb2_reg = -1,
-		.msb2_shift = 0,
-	},
-};
-
-struct mt8365_afe_rate {
-	unsigned int rate;
-	unsigned int reg_value;
-};
-
-static const struct mt8365_afe_rate mt8365_afe_rates[] = {
-	{
-		.rate = 8000,
-		.reg_value = 0,
-	},
-	{
-		.rate = 11025,
-		.reg_value = 1,
-	},
-	{
-		.rate = 12000,
-		.reg_value = 2,
-	},
-	{
-		.rate = 16000,
-		.reg_value = 4,
-	},
-	{
-		.rate = 22050,
-		.reg_value = 5,
-	},
-	{
-		.rate = 24000,
-		.reg_value = 6,
-	},
-	{
-		.rate = 32000,
-		.reg_value = 8,
-	},
-	{
-		.rate = 44100,
-		.reg_value = 9,
-	},
-	{
-		.rate = 48000,
-		.reg_value = 10,
-	},
-	{
-		.rate = 88200,
-		.reg_value = 11,
-	},
-	{
-		.rate = 96000,
-		.reg_value = 12,
-	},
-	{
-		.rate = 176400,
-		.reg_value = 13,
-	},
-	{
-		.rate = 192000,
-		.reg_value = 14,
-	},
-};
-
-static unsigned int mt8365_afe_fs_timing(unsigned int rate)
-{
-	int i;
-
-	for (i = 0; i < ARRAY_SIZE(mt8365_afe_rates); i++)
-		if (mt8365_afe_rates[i].rate == rate)
-			return mt8365_afe_rates[i].reg_value;
-
-	return -EINVAL;
-}
-
-static unsigned int mt8365_afe_fs(unsigned int rate, int aud_blk)
-{
-	return mt8365_afe_fs_timing(rate);
-}
-
-static unsigned int mt8365_afe2adsp_addr(unsigned int addr)
-{
-	/*TODO : Need apply the address remap */
-	return addr;
-}
-
-static unsigned int mt8365_adsp2afe_addr(unsigned int addr)
-{
-	/* TODO : Need apply the address remap */
-	return addr;
-}
-
-struct mtk_base_afe_platform mtk_afe_platform = {
-	.base_addr = AFE_REG_BASE,
-	.memif_datas = memif_data,
-	.memif_size = MT8365_MEMIF_NUM,
-	.memif_dl_num = MT8365_MEMIF_DL_NUM,
-	.memif_32bit_supported = 0,
-	.irq_datas = NULL,
-	.irqs_size = 0,
-	.dais_size = MT8365_DAI_NUM,
-	.afe2adsp_addr = mt8365_afe2adsp_addr,
-	.adsp2afe_addr = mt8365_adsp2afe_addr,
-	.afe_fs = mt8365_afe_fs,
-	.irq_fs = mt8365_afe_fs_timing,
-};
diff --git a/src/platform/mt8365/include/arch/xtensa/config/core-isa.h b/src/platform/mt8365/include/arch/xtensa/config/core-isa.h
deleted file mode 100644
index b8efd6318c50..000000000000
--- a/src/platform/mt8365/include/arch/xtensa/config/core-isa.h
+++ /dev/null
@@ -1,649 +0,0 @@
-/* 
- * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
- *				processor CORE configuration
- *
- *  See <xtensa/config/core.h>, which includes this file, for more details.
- */
-
-/* Xtensa processor core configuration information.
-
-   Customer ID=13943; Build=0x75f5e; Copyright (c) 1999-2018 Tensilica Inc.
-
-   Permission is hereby granted, free of charge, to any person obtaining
-   a copy of this software and associated documentation files (the
-   "Software"), to deal in the Software without restriction, including
-   without limitation the rights to use, copy, modify, merge, publish,
-   distribute, sublicense, and/or sell copies of the Software, and to
-   permit persons to whom the Software is furnished to do so, subject to
-   the following conditions:
-
-   The above copyright notice and this permission notice shall be included
-   in all copies or substantial portions of the Software.
-
-   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
-
-#ifndef _XTENSA_CORE_CONFIGURATION_H
-#define _XTENSA_CORE_CONFIGURATION_H
-
-
-/****************************************************************************
-	    Parameters Useful for Any Code, USER or PRIVILEGED
- ****************************************************************************/
-
-/*
- *  Note:  Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
- *  configured, and a value of 0 otherwise.  These macros are always defined.
- */
-
-
-/*----------------------------------------------------------------------
-				ISA
-  ----------------------------------------------------------------------*/
-
-#define XCHAL_HAVE_BE			0	/* big-endian byte ordering */
-#define XCHAL_HAVE_WINDOWED		1	/* windowed registers option */
-#define XCHAL_NUM_AREGS			64	/* num of physical addr regs */
-#define XCHAL_NUM_AREGS_LOG2		6	/* log2(XCHAL_NUM_AREGS) */
-#define XCHAL_MAX_INSTRUCTION_SIZE	11	/* max instr bytes (3..8) */
-#define XCHAL_HAVE_DEBUG		1	/* debug option */
-#define XCHAL_HAVE_DENSITY		1	/* 16-bit instructions */
-#define XCHAL_HAVE_LOOPS		1	/* zero-overhead loops */
-#define XCHAL_LOOP_BUFFER_SIZE		256	/* zero-ov. loop instr buffer size */
-#define XCHAL_HAVE_NSA			1	/* NSA/NSAU instructions */
-#define XCHAL_HAVE_MINMAX		1	/* MIN/MAX instructions */
-#define XCHAL_HAVE_SEXT			1	/* SEXT instruction */
-#define XCHAL_HAVE_DEPBITS		0	/* DEPBITS instruction */
-#define XCHAL_HAVE_CLAMPS		1	/* CLAMPS instruction */
-#define XCHAL_HAVE_MUL16		1	/* MUL16S/MUL16U instructions */
-#define XCHAL_HAVE_MUL32		1	/* MULL instruction */
-#define XCHAL_HAVE_MUL32_HIGH		0	/* MULUH/MULSH instructions */
-#define XCHAL_HAVE_DIV32		1	/* QUOS/QUOU/REMS/REMU instructions */
-#define XCHAL_HAVE_L32R			1	/* L32R instruction */
-#define XCHAL_HAVE_ABSOLUTE_LITERALS	0	/* non-PC-rel (extended) L32R */
-#define XCHAL_HAVE_CONST16		0	/* CONST16 instruction */
-#define XCHAL_HAVE_ADDX			1	/* ADDX#/SUBX# instructions */
-#define XCHAL_HAVE_EXCLUSIVE            1	/* L32EX/S32EX instructions */
-#define XCHAL_HAVE_WIDE_BRANCHES	0	/* B*.W18 or B*.W15 instr's */
-#define XCHAL_HAVE_PREDICTED_BRANCHES	0	/* B[EQ/EQZ/NE/NEZ]T instr's */
-#define XCHAL_HAVE_CALL4AND12		1	/* (obsolete option) */
-#define XCHAL_HAVE_ABS			1	/* ABS instruction */
-/*#define XCHAL_HAVE_POPC		0*/	/* POPC instruction */
-/*#define XCHAL_HAVE_CRC		0*/	/* CRC instruction */
-#define XCHAL_HAVE_RELEASE_SYNC		1	/* L32AI/S32RI instructions */
-#define XCHAL_HAVE_S32C1I		0	/* S32C1I instruction */
-#define XCHAL_HAVE_SPECULATION		0	/* speculation */
-#define XCHAL_HAVE_FULL_RESET		1	/* all regs/state reset */
-#define XCHAL_NUM_CONTEXTS		1	/* */
-#define XCHAL_NUM_MISC_REGS		4	/* num of scratch regs (0..4) */
-#define XCHAL_HAVE_TAP_MASTER		0	/* JTAG TAP control instr's */
-#define XCHAL_HAVE_PRID			1	/* processor ID register */
-#define XCHAL_HAVE_EXTERN_REGS		1	/* WER/RER instructions */
-#define XCHAL_HAVE_MX			0	/* MX core (Tensilica internal) */
-#define XCHAL_HAVE_MP_INTERRUPTS	0	/* interrupt distributor port */
-#define XCHAL_HAVE_MP_RUNSTALL		0	/* core RunStall control port */
-#define XCHAL_HAVE_PSO			0	/* Power Shut-Off */
-#define XCHAL_HAVE_PSO_CDM		0	/* core/debug/mem pwr domains */
-#define XCHAL_HAVE_PSO_FULL_RETENTION	0	/* all regs preserved on PSO */
-#define XCHAL_HAVE_THREADPTR		1	/* THREADPTR register */
-#define XCHAL_HAVE_BOOLEANS		1	/* boolean registers */
-#define XCHAL_HAVE_CP			1	/* CPENABLE reg (coprocessor) */
-#define XCHAL_CP_MAXCFG			2	/* max allowed cp id plus one */
-#define XCHAL_HAVE_MAC16		0	/* MAC16 package */
-
-#define XCHAL_HAVE_FUSION		0	/* Fusion*/
-#define XCHAL_HAVE_FUSION_FP		0	/* Fusion FP option */
-#define XCHAL_HAVE_FUSION_LOW_POWER	0	/* Fusion Low Power option */
-#define XCHAL_HAVE_FUSION_AES		0	/* Fusion BLE/Wifi AES-128 CCM option */
-#define XCHAL_HAVE_FUSION_CONVENC	0	/* Fusion Conv Encode option */
-#define XCHAL_HAVE_FUSION_LFSR_CRC	0	/* Fusion LFSR-CRC option */
-#define XCHAL_HAVE_FUSION_BITOPS	0	/* Fusion Bit Operations Support option */
-#define XCHAL_HAVE_FUSION_AVS		0	/* Fusion AVS option */
-#define XCHAL_HAVE_FUSION_16BIT_BASEBAND 0	/* Fusion 16-bit Baseband option */
-#define XCHAL_HAVE_FUSION_VITERBI	0	/* Fusion Viterbi option */
-#define XCHAL_HAVE_FUSION_SOFTDEMAP	0	/* Fusion Soft Bit Demap option */
-#define XCHAL_HAVE_HIFIPRO		0	/* HiFiPro Audio Engine pkg */
-#define XCHAL_HAVE_HIFI5		0	/* HiFi5 Audio Engine pkg */
-#define XCHAL_HAVE_HIFI5_VFPU		0	/* HiFi5 Audio Engine VFPU option */
-#define XCHAL_HAVE_HIFI4		1	/* HiFi4 Audio Engine pkg */
-#define XCHAL_HAVE_HIFI4_VFPU		1	/* HiFi4 Audio Engine VFPU option */
-#define XCHAL_HAVE_HIFI3		1	/* HiFi3 Audio Engine pkg */
-#define XCHAL_HAVE_HIFI3_VFPU		0	/* HiFi3 Audio Engine VFPU option */
-#define XCHAL_HAVE_HIFI3Z		0	/* HiFi3Z Audio Engine pkg */
-#define XCHAL_HAVE_HIFI3Z_VFPU	0	/* HiFi3Z Audio Engine VFPU option */
-#define XCHAL_HAVE_HIFI2		0	/* HiFi2 Audio Engine pkg */
-#define XCHAL_HAVE_HIFI2EP		0	/* HiFi2EP */
-#define XCHAL_HAVE_HIFI_MINI		0	
-
-
-
-#define XCHAL_HAVE_VECTORFPU2005	0	/* vector floating-point pkg */
-#define XCHAL_HAVE_USER_DPFPU		0       /* user DP floating-point pkg */
-#define XCHAL_HAVE_USER_SPFPU		1       /* user SP floating-point pkg */
-#define XCHAL_HAVE_FP			1	/* single prec floating point */
-#define XCHAL_HAVE_FP_DIV		1	/* FP with DIV instructions */
-#define XCHAL_HAVE_FP_RECIP		1	/* FP with RECIP instructions */
-#define XCHAL_HAVE_FP_SQRT		1	/* FP with SQRT instructions */
-#define XCHAL_HAVE_FP_RSQRT		1	/* FP with RSQRT instructions */
-#define XCHAL_HAVE_DFP			0	/* double precision FP pkg */
-#define XCHAL_HAVE_DFP_DIV		0	/* DFP with DIV instructions */
-#define XCHAL_HAVE_DFP_RECIP		0	/* DFP with RECIP instructions*/
-#define XCHAL_HAVE_DFP_SQRT		0	/* DFP with SQRT instructions */
-#define XCHAL_HAVE_DFP_RSQRT		0	/* DFP with RSQRT instructions*/
-#define XCHAL_HAVE_DFP_ACCEL		0	/* double precision FP acceleration pkg */
-#define XCHAL_HAVE_DFP_accel		XCHAL_HAVE_DFP_ACCEL	/* for backward compatibility */
-
-#define XCHAL_HAVE_DFPU_SINGLE_ONLY	0	/* DFPU Coprocessor, single precision only */
-#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE	0	/* DFPU Coprocessor, single and double precision */
-#define XCHAL_HAVE_VECTRA1		0	/* Vectra I  pkg */
-#define XCHAL_HAVE_VECTRALX		0	/* Vectra LX pkg */
-
-#define XCHAL_HAVE_FUSIONG		0    /* FusionG */
-#define XCHAL_HAVE_FUSIONG3		0    /* FusionG3 */
-#define XCHAL_HAVE_FUSIONG6		0    /* FusionG6 */
-#define XCHAL_HAVE_FUSIONG_SP_VFPU	0    /* sp_vfpu option on FusionG */
-#define XCHAL_HAVE_FUSIONG_DP_VFPU	0    /* dp_vfpu option on FusionG */
-#define XCHAL_FUSIONG_SIMD32		0    /* simd32 for FusionG */
-
-#define XCHAL_HAVE_PDX			0    /* PDX */
-#define XCHAL_PDX_SIMD32		0    /* simd32 for PDX */
-#define XCHAL_HAVE_PDX4			0    /* PDX4 */
-#define XCHAL_HAVE_PDX8			0    /* PDX8 */
-#define XCHAL_HAVE_PDX16		0    /* PDX16 */
-
-#define XCHAL_HAVE_CONNXD2		0	/* ConnX D2 pkg */
-#define XCHAL_HAVE_CONNXD2_DUALLSFLIX   0	/* ConnX D2 & Dual LoadStore Flix */
-#define XCHAL_HAVE_BBE16		0	/* ConnX BBE16 pkg */
-#define XCHAL_HAVE_BBE16_RSQRT		0	/* BBE16 & vector recip sqrt */
-#define XCHAL_HAVE_BBE16_VECDIV		0	/* BBE16 & vector divide */
-#define XCHAL_HAVE_BBE16_DESPREAD	0	/* BBE16 & despread */
-#define XCHAL_HAVE_BBENEP		0	/* ConnX BBENEP pkgs */
-#define XCHAL_HAVE_BBENEP_SP_VFPU	0      /* sp_vfpu option on BBE-EP */
-#define XCHAL_HAVE_BSP3			0	/* ConnX BSP3 pkg */
-#define XCHAL_HAVE_BSP3_TRANSPOSE	0	/* BSP3 & transpose32x32 */
-#define XCHAL_HAVE_SSP16		0	/* ConnX SSP16 pkg */
-#define XCHAL_HAVE_SSP16_VITERBI	0	/* SSP16 & viterbi */
-#define XCHAL_HAVE_TURBO16		0	/* ConnX Turbo16 pkg */
-#define XCHAL_HAVE_BBP16		0	/* ConnX BBP16 pkg */
-#define XCHAL_HAVE_FLIX3		0	/* basic 3-way FLIX option */
-#define XCHAL_HAVE_GRIVPEP		0	/* General Release of IVPEP */
-#define XCHAL_HAVE_GRIVPEP_HISTOGRAM	0       /* Histogram option on GRIVPEP */
-
-#define XCHAL_HAVE_VISION	        0     /* Vision P5/P6 */
-#define XCHAL_VISION_SIMD16             0     /* simd16 for Vision P5/P6 */
-#define XCHAL_VISION_TYPE               0     /* Vision P5, P6, or P3 */
-#define XCHAL_VISION_QUAD_MAC_TYPE      0     /* quad_mac option on Vision P6 */
-#define XCHAL_HAVE_VISION_HISTOGRAM     0     /* histogram option on Vision P5/P6 */
-#define XCHAL_HAVE_VISION_SP_VFPU       0     /* sp_vfpu option on Vision P5/P6 */
-#define XCHAL_HAVE_VISION_HP_VFPU       0     /* hp_vfpu option on Vision P6 */
-
-#define XCHAL_HAVE_VISIONC	        0     /* Vision C */
-
-/*----------------------------------------------------------------------
-				MISC
-  ----------------------------------------------------------------------*/
-
-#define XCHAL_NUM_LOADSTORE_UNITS	2	/* load/store units */
-#define XCHAL_NUM_WRITEBUFFER_ENTRIES	32	/* size of write buffer */
-#define XCHAL_INST_FETCH_WIDTH		16	/* instr-fetch width in bytes */
-#define XCHAL_DATA_WIDTH		8	/* data width in bytes */
-#define XCHAL_DATA_PIPE_DELAY		2	/* d-side pipeline delay
-						   (1 = 5-stage, 2 = 7-stage) */
-#define XCHAL_CLOCK_GATING_GLOBAL	1	/* global clock gating */
-#define XCHAL_CLOCK_GATING_FUNCUNIT	1	/* funct. unit clock gating */
-/*  In T1050, applies to selected core load and store instructions (see ISA): */
-#define XCHAL_UNALIGNED_LOAD_EXCEPTION	1	/* unaligned loads cause exc. */
-#define XCHAL_UNALIGNED_STORE_EXCEPTION	1	/* unaligned stores cause exc.*/
-#define XCHAL_UNALIGNED_LOAD_HW		0	/* unaligned loads work in hw */
-#define XCHAL_UNALIGNED_STORE_HW	0	/* unaligned stores work in hw*/
-
-#define XCHAL_SW_VERSION		1200009	/* sw version of this header */
-
-#define XCHAL_CORE_ID			"hifi4_Aquila_E2_PROD"	/* alphanum core name
-						   (CoreID) set in the Xtensa
-						   Processor Generator */
-
-#define XCHAL_BUILD_UNIQUE_ID		0x00075F5E	/* 22-bit sw build ID */
-
-/*
- *  These definitions describe the hardware targeted by this software.
- */
-#define XCHAL_HW_CONFIGID0		0xC0F3FBFE	/* ConfigID hi 32 bits*/
-#define XCHAL_HW_CONFIGID1		0x22475F5E	/* ConfigID lo 32 bits*/
-#define XCHAL_HW_VERSION_NAME		"LX7.0.9"	/* full version name */
-#define XCHAL_HW_VERSION_MAJOR		2700	/* major ver# of targeted hw */
-#define XCHAL_HW_VERSION_MINOR		9	/* minor ver# of targeted hw */
-#define XCHAL_HW_VERSION		270009	/* major*100+minor */
-#define XCHAL_HW_REL_LX7		1
-#define XCHAL_HW_REL_LX7_0		1
-#define XCHAL_HW_REL_LX7_0_9		1
-#define XCHAL_HW_CONFIGID_RELIABLE	1
-/*  If software targets a *range* of hardware versions, these are the bounds: */
-#define XCHAL_HW_MIN_VERSION_MAJOR	2700	/* major v of earliest tgt hw */
-#define XCHAL_HW_MIN_VERSION_MINOR	9	/* minor v of earliest tgt hw */
-#define XCHAL_HW_MIN_VERSION		270009	/* earliest targeted hw */
-#define XCHAL_HW_MAX_VERSION_MAJOR	2700	/* major v of latest tgt hw */
-#define XCHAL_HW_MAX_VERSION_MINOR	9	/* minor v of latest tgt hw */
-#define XCHAL_HW_MAX_VERSION		270009	/* latest targeted hw */
-
-
-/*----------------------------------------------------------------------
-				CACHE
-  ----------------------------------------------------------------------*/
-
-#define XCHAL_ICACHE_LINESIZE		128	/* I-cache line size in bytes */
-#define XCHAL_DCACHE_LINESIZE		128	/* D-cache line size in bytes */
-#define XCHAL_ICACHE_LINEWIDTH		7	/* log2(I line size in bytes) */
-#define XCHAL_DCACHE_LINEWIDTH		7	/* log2(D line size in bytes) */
-
-#define XCHAL_ICACHE_SIZE		32768	/* I-cache size in bytes or 0 */
-#define XCHAL_DCACHE_SIZE		32768	/* D-cache size in bytes or 0 */
-
-#define XCHAL_DCACHE_IS_WRITEBACK	1	/* writeback feature */
-#define XCHAL_DCACHE_IS_COHERENT	0	/* MP coherence feature */
-
-#define XCHAL_HAVE_PREFETCH		1	/* PREFCTL register */
-#define XCHAL_HAVE_PREFETCH_L1		0	/* prefetch to L1 dcache */
-#define XCHAL_PREFETCH_CASTOUT_LINES	1	/* dcache pref. castout bufsz */
-#define XCHAL_PREFETCH_ENTRIES		16	/* cache prefetch entries */
-#define XCHAL_PREFETCH_BLOCK_ENTRIES	0	/* prefetch block streams */
-#define XCHAL_HAVE_CACHE_BLOCKOPS	0	/* block prefetch for caches */
-#define XCHAL_HAVE_ICACHE_TEST		1	/* Icache test instructions */
-#define XCHAL_HAVE_DCACHE_TEST		1	/* Dcache test instructions */
-#define XCHAL_HAVE_ICACHE_DYN_WAYS	1	/* Icache dynamic way support */
-#define XCHAL_HAVE_DCACHE_DYN_WAYS	1	/* Dcache dynamic way support */
-
-
-
-
-/****************************************************************************
-    Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
- ****************************************************************************/
-
-
-#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
-
-/*----------------------------------------------------------------------
-				CACHE
-  ----------------------------------------------------------------------*/
-
-#define XCHAL_HAVE_PIF			1	/* any outbound bus present */
-
-#define XCHAL_HAVE_AXI			1	/* AXI bus */
-#define XCHAL_HAVE_AXI_ECC		1	/* ECC on AXI bus */
-#define XCHAL_HAVE_ACELITE		0	/* ACELite bus */
-
-#define XCHAL_HAVE_PIF_WR_RESP			1	/* pif write response */
-#define XCHAL_HAVE_PIF_REQ_ATTR			1	/* pif attribute */
-
-/*  If present, cache size in bytes == (ways * 2^(linewidth + setwidth)).  */
-
-/*  Number of cache sets in log2(lines per way):  */
-#define XCHAL_ICACHE_SETWIDTH		6
-#define XCHAL_DCACHE_SETWIDTH		6
-
-/*  Cache set associativity (number of ways):  */
-#define XCHAL_ICACHE_WAYS		4
-#define XCHAL_DCACHE_WAYS		4
-
-/*  Cache features:  */
-#define XCHAL_ICACHE_LINE_LOCKABLE	1
-#define XCHAL_DCACHE_LINE_LOCKABLE	1
-#define XCHAL_ICACHE_ECC_PARITY		0
-#define XCHAL_DCACHE_ECC_PARITY		0
-
-/*  Cache access size in bytes (affects operation of SICW instruction):  */
-#define XCHAL_ICACHE_ACCESS_SIZE	16
-#define XCHAL_DCACHE_ACCESS_SIZE	8
-
-#define XCHAL_DCACHE_BANKS		2	/* number of banks */
-
-/*  Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits):  */
-
-
-/*----------------------------------------------------------------------
-			INTERNAL I/D RAM/ROMs and XLMI
-  ----------------------------------------------------------------------*/
-#define XCHAL_NUM_INSTROM		0	/* number of core instr. ROMs */
-#define XCHAL_NUM_INSTRAM		2	/* number of core instr. RAMs */
-#define XCHAL_NUM_DATAROM		0	/* number of core data ROMs */
-#define XCHAL_NUM_DATARAM		2	/* number of core data RAMs */
-#define XCHAL_NUM_URAM			0	/* number of core unified RAMs*/
-#define XCHAL_NUM_XLMI			0	/* number of core XLMI ports */
-
-/*  Instruction RAM 0:  */
-#define XCHAL_INSTRAM0_VADDR		0x40000000	/* virtual address */
-#define XCHAL_INSTRAM0_PADDR		0x40000000	/* physical address */
-#define XCHAL_INSTRAM0_SIZE		65536	/* size in bytes */
-#define XCHAL_INSTRAM0_ECC_PARITY	0	/* ECC/parity type, 0=none */
-#define XCHAL_HAVE_INSTRAM0		1
-#define XCHAL_INSTRAM0_HAVE_IDMA	0	/* idma supported by this local memory */
-
-/*  Instruction RAM 1:  */
-#define XCHAL_INSTRAM1_VADDR		0x40010000	/* virtual address */
-#define XCHAL_INSTRAM1_PADDR		0x40010000	/* physical address */
-#define XCHAL_INSTRAM1_SIZE		65536	/* size in bytes */
-#define XCHAL_INSTRAM1_ECC_PARITY	0	/* ECC/parity type, 0=none */
-#define XCHAL_HAVE_INSTRAM1		1
-#define XCHAL_INSTRAM1_HAVE_IDMA	0	/* idma supported by this local memory */
-
-/*  Data RAM 0:  */
-#define XCHAL_DATARAM0_VADDR		0x1E000000	/* virtual address */
-#define XCHAL_DATARAM0_PADDR		0x1E000000	/* physical address */
-#define XCHAL_DATARAM0_SIZE		262144	/* size in bytes */
-#define XCHAL_DATARAM0_ECC_PARITY	0	/* ECC/parity type, 0=none */
-#define XCHAL_DATARAM0_BANKS		2	/* number of banks */
-#define XCHAL_HAVE_DATARAM0		1
-#define XCHAL_DATARAM0_HAVE_IDMA	0	/* idma supported by this local memory */
-
-/*  Data RAM 1:  */
-#define XCHAL_DATARAM1_VADDR		0x1E040000	/* virtual address */
-#define XCHAL_DATARAM1_PADDR		0x1E040000	/* physical address */
-#define XCHAL_DATARAM1_SIZE		262144	/* size in bytes */
-#define XCHAL_DATARAM1_ECC_PARITY	0	/* ECC/parity type, 0=none */
-#define XCHAL_DATARAM1_BANKS		2	/* number of banks */
-#define XCHAL_HAVE_DATARAM1		1
-#define XCHAL_DATARAM1_HAVE_IDMA	0	/* idma supported by this local memory */
-
-#define XCHAL_HAVE_IDMA			0
-#define XCHAL_HAVE_IDMA_TRANSPOSE	0
-
-#define XCHAL_HAVE_IMEM_LOADSTORE	1	/* can load/store to IROM/IRAM*/
-
-
-/*----------------------------------------------------------------------
-			INTERRUPTS and TIMERS
-  ----------------------------------------------------------------------*/
-
-#define XCHAL_HAVE_INTERRUPTS		1	/* interrupt option */
-#define XCHAL_HAVE_HIGHPRI_INTERRUPTS	1	/* med/high-pri. interrupts */
-#define XCHAL_HAVE_NMI			0	/* non-maskable interrupt */
-#define XCHAL_HAVE_CCOUNT		1	/* CCOUNT reg. (timer option) */
-#define XCHAL_NUM_TIMERS		3	/* number of CCOMPAREn regs */
-#define XCHAL_NUM_INTERRUPTS		25	/* number of interrupts */
-#define XCHAL_NUM_INTERRUPTS_LOG2	5	/* ceil(log2(NUM_INTERRUPTS)) */
-#define XCHAL_NUM_EXTINTERRUPTS		18	/* num of external interrupts */
-#define XCHAL_NUM_INTLEVELS		4	/* number of interrupt levels
-						   (not including level zero) */
-#define XCHAL_EXCM_LEVEL		2	/* level masked by PS.EXCM */
-	/* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
-
-/*  Masks of interrupts at each interrupt level:  */
-#define XCHAL_INTLEVEL1_MASK		0x00B900FF
-#define XCHAL_INTLEVEL2_MASK		0x0142FF00
-#define XCHAL_INTLEVEL3_MASK		0x00040000
-#define XCHAL_INTLEVEL4_MASK		0x00000000
-#define XCHAL_INTLEVEL5_MASK		0x00000000
-#define XCHAL_INTLEVEL6_MASK		0x00000000
-#define XCHAL_INTLEVEL7_MASK		0x00000000
-
-/*  Masks of interrupts at each range 1..n of interrupt levels:  */
-#define XCHAL_INTLEVEL1_ANDBELOW_MASK	0x00B900FF
-#define XCHAL_INTLEVEL2_ANDBELOW_MASK	0x01FBFFFF
-#define XCHAL_INTLEVEL3_ANDBELOW_MASK	0x01FFFFFF
-#define XCHAL_INTLEVEL4_ANDBELOW_MASK	0x01FFFFFF
-#define XCHAL_INTLEVEL5_ANDBELOW_MASK	0x01FFFFFF
-#define XCHAL_INTLEVEL6_ANDBELOW_MASK	0x01FFFFFF
-#define XCHAL_INTLEVEL7_ANDBELOW_MASK	0x01FFFFFF
-
-/*  Level of each interrupt:  */
-#define XCHAL_INT0_LEVEL		1
-#define XCHAL_INT1_LEVEL		1
-#define XCHAL_INT2_LEVEL		1
-#define XCHAL_INT3_LEVEL		1
-#define XCHAL_INT4_LEVEL		1
-#define XCHAL_INT5_LEVEL		1
-#define XCHAL_INT6_LEVEL		1
-#define XCHAL_INT7_LEVEL		1
-#define XCHAL_INT8_LEVEL		2
-#define XCHAL_INT9_LEVEL		2
-#define XCHAL_INT10_LEVEL		2
-#define XCHAL_INT11_LEVEL		2
-#define XCHAL_INT12_LEVEL		2
-#define XCHAL_INT13_LEVEL		2
-#define XCHAL_INT14_LEVEL		2
-#define XCHAL_INT15_LEVEL		2
-#define XCHAL_INT16_LEVEL		1
-#define XCHAL_INT17_LEVEL		2
-#define XCHAL_INT18_LEVEL		3
-#define XCHAL_INT19_LEVEL		1
-#define XCHAL_INT20_LEVEL		1
-#define XCHAL_INT21_LEVEL		1
-#define XCHAL_INT22_LEVEL		2
-#define XCHAL_INT23_LEVEL		1
-#define XCHAL_INT24_LEVEL		2
-#define XCHAL_DEBUGLEVEL		4	/* debug interrupt level */
-#define XCHAL_HAVE_DEBUG_EXTERN_INT	1	/* OCD external db interrupt */
-
-/*  Type of each interrupt:  */
-#define XCHAL_INT0_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT1_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT2_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT3_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT4_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT5_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT6_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
-#define XCHAL_INT7_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
-#define XCHAL_INT8_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT9_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT10_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT11_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT12_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT13_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT14_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
-#define XCHAL_INT15_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
-#define XCHAL_INT16_TYPE 	XTHAL_INTTYPE_TIMER
-#define XCHAL_INT17_TYPE 	XTHAL_INTTYPE_TIMER
-#define XCHAL_INT18_TYPE 	XTHAL_INTTYPE_TIMER
-#define XCHAL_INT19_TYPE 	XTHAL_INTTYPE_WRITE_ERROR
-#define XCHAL_INT20_TYPE 	XTHAL_INTTYPE_PROFILING
-#define XCHAL_INT21_TYPE 	XTHAL_INTTYPE_SOFTWARE
-#define XCHAL_INT22_TYPE 	XTHAL_INTTYPE_SOFTWARE
-#define XCHAL_INT23_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT24_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-
-/*  Masks of interrupts for each type of interrupt:  */
-#define XCHAL_INTTYPE_MASK_UNCONFIGURED	0xFE000000
-#define XCHAL_INTTYPE_MASK_SOFTWARE	0x00600000
-#define XCHAL_INTTYPE_MASK_EXTERN_EDGE	0x0000C0C0
-#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL	0x01803F3F
-#define XCHAL_INTTYPE_MASK_TIMER	0x00070000
-#define XCHAL_INTTYPE_MASK_NMI		0x00000000
-#define XCHAL_INTTYPE_MASK_WRITE_ERROR	0x00080000
-#define XCHAL_INTTYPE_MASK_PROFILING	0x00100000
-#define XCHAL_INTTYPE_MASK_IDMA_DONE	0x00000000
-#define XCHAL_INTTYPE_MASK_IDMA_ERR	0x00000000
-#define XCHAL_INTTYPE_MASK_GS_ERR	0x00000000
-
-/*  Interrupt numbers assigned to specific interrupt sources:  */
-#define XCHAL_TIMER0_INTERRUPT		16	/* CCOMPARE0 */
-#define XCHAL_TIMER1_INTERRUPT		17	/* CCOMPARE1 */
-#define XCHAL_TIMER2_INTERRUPT		18	/* CCOMPARE2 */
-#define XCHAL_TIMER3_INTERRUPT		XTHAL_TIMER_UNCONFIGURED
-#define XCHAL_WRITE_ERROR_INTERRUPT	19
-#define XCHAL_PROFILING_INTERRUPT	20
-
-/*  Interrupt numbers for levels at which only one interrupt is configured:  */
-#define XCHAL_INTLEVEL3_NUM		18
-/*  (There are many interrupts each at level(s) 1, 2.)  */
-
-
-/*
- *  External interrupt mapping.
- *  These macros describe how Xtensa processor interrupt numbers
- *  (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
- *  map to external BInterrupt<n> pins, for those interrupts
- *  configured as external (level-triggered, edge-triggered, or NMI).
- *  See the Xtensa processor databook for more details.
- */
-
-/*  Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number:  */
-#define XCHAL_EXTINT0_NUM		0	/* (intlevel 1) */
-#define XCHAL_EXTINT1_NUM		1	/* (intlevel 1) */
-#define XCHAL_EXTINT2_NUM		2	/* (intlevel 1) */
-#define XCHAL_EXTINT3_NUM		3	/* (intlevel 1) */
-#define XCHAL_EXTINT4_NUM		4	/* (intlevel 1) */
-#define XCHAL_EXTINT5_NUM		5	/* (intlevel 1) */
-#define XCHAL_EXTINT6_NUM		6	/* (intlevel 1) */
-#define XCHAL_EXTINT7_NUM		7	/* (intlevel 1) */
-#define XCHAL_EXTINT8_NUM		8	/* (intlevel 2) */
-#define XCHAL_EXTINT9_NUM		9	/* (intlevel 2) */
-#define XCHAL_EXTINT10_NUM		10	/* (intlevel 2) */
-#define XCHAL_EXTINT11_NUM		11	/* (intlevel 2) */
-#define XCHAL_EXTINT12_NUM		12	/* (intlevel 2) */
-#define XCHAL_EXTINT13_NUM		13	/* (intlevel 2) */
-#define XCHAL_EXTINT14_NUM		14	/* (intlevel 2) */
-#define XCHAL_EXTINT15_NUM		15	/* (intlevel 2) */
-#define XCHAL_EXTINT16_NUM		23	/* (intlevel 1) */
-#define XCHAL_EXTINT17_NUM		24	/* (intlevel 2) */
-/*  EXTERNAL BInterrupt pin numbers mapped to each core interrupt number:  */
-#define XCHAL_INT0_EXTNUM		0	/* (intlevel 1) */
-#define XCHAL_INT1_EXTNUM		1	/* (intlevel 1) */
-#define XCHAL_INT2_EXTNUM		2	/* (intlevel 1) */
-#define XCHAL_INT3_EXTNUM		3	/* (intlevel 1) */
-#define XCHAL_INT4_EXTNUM		4	/* (intlevel 1) */
-#define XCHAL_INT5_EXTNUM		5	/* (intlevel 1) */
-#define XCHAL_INT6_EXTNUM		6	/* (intlevel 1) */
-#define XCHAL_INT7_EXTNUM		7	/* (intlevel 1) */
-#define XCHAL_INT8_EXTNUM		8	/* (intlevel 2) */
-#define XCHAL_INT9_EXTNUM		9	/* (intlevel 2) */
-#define XCHAL_INT10_EXTNUM		10	/* (intlevel 2) */
-#define XCHAL_INT11_EXTNUM		11	/* (intlevel 2) */
-#define XCHAL_INT12_EXTNUM		12	/* (intlevel 2) */
-#define XCHAL_INT13_EXTNUM		13	/* (intlevel 2) */
-#define XCHAL_INT14_EXTNUM		14	/* (intlevel 2) */
-#define XCHAL_INT15_EXTNUM		15	/* (intlevel 2) */
-#define XCHAL_INT23_EXTNUM		16	/* (intlevel 1) */
-#define XCHAL_INT24_EXTNUM		17	/* (intlevel 2) */
-
-
-/*----------------------------------------------------------------------
-			EXCEPTIONS and VECTORS
-  ----------------------------------------------------------------------*/
-
-#define XCHAL_XEA_VERSION		2	/* Xtensa Exception Architecture
-						   number: 1 == XEA1 (old)
-							   2 == XEA2 (new)
-							   0 == XEAX (extern) or TX */
-#define XCHAL_HAVE_XEA1			0	/* Exception Architecture 1 */
-#define XCHAL_HAVE_XEA2			1	/* Exception Architecture 2 */
-#define XCHAL_HAVE_XEAX			0	/* External Exception Arch. */
-#define XCHAL_HAVE_EXCEPTIONS		1	/* exception option */
-#define XCHAL_HAVE_HALT			0	/* halt architecture option */
-#define XCHAL_HAVE_BOOTLOADER		0	/* boot loader (for TX) */
-#define XCHAL_HAVE_MEM_ECC_PARITY	0	/* local memory ECC/parity */
-#define XCHAL_HAVE_VECTOR_SELECT	1	/* relocatable vectors */
-#define XCHAL_HAVE_VECBASE		1	/* relocatable vectors */
-#define XCHAL_VECBASE_RESET_VADDR	0x40020400  /* VECBASE reset value */
-#define XCHAL_VECBASE_RESET_PADDR	0x40020400
-#define XCHAL_RESET_VECBASE_OVERLAP	0
-
-#define XCHAL_RESET_VECTOR0_VADDR	0x40020000
-#define XCHAL_RESET_VECTOR0_PADDR	0x40020000
-#define XCHAL_RESET_VECTOR1_VADDR	0x40000640
-#define XCHAL_RESET_VECTOR1_PADDR	0x40000640
-#define XCHAL_RESET_VECTOR_VADDR	0x40000640
-#define XCHAL_RESET_VECTOR_PADDR	0x40000640
-#define XCHAL_USER_VECOFS		0x000001FC
-#define XCHAL_USER_VECTOR_VADDR		0x400205FC
-#define XCHAL_USER_VECTOR_PADDR		0x400205FC
-#define XCHAL_KERNEL_VECOFS		0x000001DC
-#define XCHAL_KERNEL_VECTOR_VADDR	0x400205DC
-#define XCHAL_KERNEL_VECTOR_PADDR	0x400205DC
-#define XCHAL_DOUBLEEXC_VECOFS		0x0000021C
-#define XCHAL_DOUBLEEXC_VECTOR_VADDR	0x4002061C
-#define XCHAL_DOUBLEEXC_VECTOR_PADDR	0x4002061C
-#define XCHAL_WINDOW_OF4_VECOFS		0x00000000
-#define XCHAL_WINDOW_UF4_VECOFS		0x00000040
-#define XCHAL_WINDOW_OF8_VECOFS		0x00000080
-#define XCHAL_WINDOW_UF8_VECOFS		0x000000C0
-#define XCHAL_WINDOW_OF12_VECOFS	0x00000100
-#define XCHAL_WINDOW_UF12_VECOFS	0x00000140
-#define XCHAL_WINDOW_VECTORS_VADDR	0x40020400
-#define XCHAL_WINDOW_VECTORS_PADDR	0x40020400
-#define XCHAL_INTLEVEL2_VECOFS		0x0000017C
-#define XCHAL_INTLEVEL2_VECTOR_VADDR	0x4002057C
-#define XCHAL_INTLEVEL2_VECTOR_PADDR	0x4002057C
-#define XCHAL_INTLEVEL3_VECOFS		0x0000019C
-#define XCHAL_INTLEVEL3_VECTOR_VADDR	0x4002059C
-#define XCHAL_INTLEVEL3_VECTOR_PADDR	0x4002059C
-#define XCHAL_INTLEVEL4_VECOFS		0x000001BC
-#define XCHAL_INTLEVEL4_VECTOR_VADDR	0x400205BC
-#define XCHAL_INTLEVEL4_VECTOR_PADDR	0x400205BC
-#define XCHAL_DEBUG_VECOFS		XCHAL_INTLEVEL4_VECOFS
-#define XCHAL_DEBUG_VECTOR_VADDR	XCHAL_INTLEVEL4_VECTOR_VADDR
-#define XCHAL_DEBUG_VECTOR_PADDR	XCHAL_INTLEVEL4_VECTOR_PADDR
-
-
-/*----------------------------------------------------------------------
-				DEBUG MODULE
-  ----------------------------------------------------------------------*/
-
-/*  Misc  */
-#define XCHAL_HAVE_DEBUG_ERI		1	/* ERI to debug module */
-#define XCHAL_HAVE_DEBUG_APB		1	/* APB to debug module */
-#define XCHAL_HAVE_DEBUG_JTAG		1	/* JTAG to debug module */
-
-/*  On-Chip Debug (OCD)  */
-#define XCHAL_HAVE_OCD			1	/* OnChipDebug option */
-#define XCHAL_NUM_IBREAK		2	/* number of IBREAKn regs */
-#define XCHAL_NUM_DBREAK		2	/* number of DBREAKn regs */
-#define XCHAL_HAVE_OCD_DIR_ARRAY	0	/* faster OCD option (to LX4) */
-#define XCHAL_HAVE_OCD_LS32DDR		1	/* L32DDR/S32DDR (faster OCD) */
-
-/*  TRAX (in core)  */
-#define XCHAL_HAVE_TRAX			1	/* TRAX in debug module */
-#define XCHAL_TRAX_MEM_SIZE		262144	/* TRAX memory size in bytes */
-#define XCHAL_TRAX_MEM_SHAREABLE	1	/* start/end regs; ready sig. */
-#define XCHAL_TRAX_ATB_WIDTH		32	/* ATB width (bits), 0=no ATB */
-#define XCHAL_TRAX_TIME_WIDTH		0	/* timestamp bitwidth, 0=none */
-
-/*  Perf counters  */
-#define XCHAL_NUM_PERF_COUNTERS		8	/* performance counters */
-
-
-/*----------------------------------------------------------------------
-				MMU
-  ----------------------------------------------------------------------*/
-
-/*  See core-matmap.h header file for more details.  */
-
-#define XCHAL_HAVE_TLBS			0	/* inverse of HAVE_CACHEATTR */
-#define XCHAL_HAVE_SPANNING_WAY		0	/* one way maps I+D 4GB vaddr */
-#define XCHAL_HAVE_IDENTITY_MAP		1	/* vaddr == paddr always */
-#define XCHAL_HAVE_CACHEATTR		0	/* CACHEATTR register present */
-#define XCHAL_HAVE_MIMIC_CACHEATTR	0	/* region protection */
-#define XCHAL_HAVE_XLT_CACHEATTR	0	/* region prot. w/translation */
-#define XCHAL_HAVE_PTP_MMU		0	/* full MMU (with page table
-						   [autorefill] and protection)
-						   usable for an MMU-based OS */
-
-/*  If none of the above last 5 are set, it's a custom TLB configuration.  */
-
-#define XCHAL_MMU_ASID_BITS		0	/* number of bits in ASIDs */
-#define XCHAL_MMU_RINGS			1	/* number of rings (1..4) */
-#define XCHAL_MMU_RING_BITS		0	/* num of bits in RING field */
-
-/*----------------------------------------------------------------------
-				MPU
-  ----------------------------------------------------------------------*/
-#define XCHAL_HAVE_MPU			1 
-#define XCHAL_MPU_ENTRIES		32
-
-#define XCHAL_MPU_ALIGN_REQ		1	/* MPU requires alignment of entries to background map */
-#define XCHAL_MPU_BACKGROUND_ENTRIES	2	/* number of entries in bg map*/
-#define XCHAL_MPU_BG_CACHEADRDIS	0xFF	/* default CACHEADRDIS for bg */
- 
-#define XCHAL_MPU_ALIGN_BITS		12
-#define XCHAL_MPU_ALIGN			4096
-
-#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
-
-
-#endif /* _XTENSA_CORE_CONFIGURATION_H */
-
diff --git a/src/platform/mt8365/include/arch/xtensa/config/core-matmap.h b/src/platform/mt8365/include/arch/xtensa/config/core-matmap.h
deleted file mode 100644
index 1235cf0f758b..000000000000
--- a/src/platform/mt8365/include/arch/xtensa/config/core-matmap.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/* 
- * xtensa/config/core-matmap.h -- Memory access and translation mapping
- *	parameters (CHAL) of the Xtensa processor core configuration.
- *
- *  If you are using Xtensa Tools, see <xtensa/config/core.h> (which includes
- *  this file) for more details.
- *
- *  In the Xtensa processor products released to date, all parameters
- *  defined in this file are derivable (at least in theory) from
- *  information contained in the core-isa.h header file.
- *  In particular, the following core configuration parameters are relevant:
- *	XCHAL_HAVE_CACHEATTR
- *	XCHAL_HAVE_MIMIC_CACHEATTR
- *	XCHAL_HAVE_XLT_CACHEATTR
- *	XCHAL_HAVE_PTP_MMU
- *	XCHAL_ITLB_ARF_ENTRIES_LOG2
- *	XCHAL_DTLB_ARF_ENTRIES_LOG2
- *	XCHAL_DCACHE_IS_WRITEBACK
- *	XCHAL_ICACHE_SIZE		(presence of I-cache)
- *	XCHAL_DCACHE_SIZE		(presence of D-cache)
- *	XCHAL_HW_VERSION_MAJOR
- *	XCHAL_HW_VERSION_MINOR
- */
-
-/* Customer ID=13943; Build=0x75f5e; Copyright (c) 1999-2018 Tensilica Inc.
-
-   Permission is hereby granted, free of charge, to any person obtaining
-   a copy of this software and associated documentation files (the
-   "Software"), to deal in the Software without restriction, including
-   without limitation the rights to use, copy, modify, merge, publish,
-   distribute, sublicense, and/or sell copies of the Software, and to
-   permit persons to whom the Software is furnished to do so, subject to
-   the following conditions:
-
-   The above copyright notice and this permission notice shall be included
-   in all copies or substantial portions of the Software.
-
-   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
-
-
-#ifndef XTENSA_CONFIG_CORE_MATMAP_H
-#define XTENSA_CONFIG_CORE_MATMAP_H
-
-
-/*----------------------------------------------------------------------
-			CACHE (MEMORY ACCESS) ATTRIBUTES
-  ----------------------------------------------------------------------*/
-/*----------------------------------------------------------------------
-				MPU
-  ----------------------------------------------------------------------*/
-
-/* Mappings for legacy constants where appropriate */
-
-#define XCHAL_CA_WRITEBACK (XTHAL_MEM_WRITEBACK | XTHAL_AR_RWXrwx)
-
-#define XCHAL_CA_WRITEBACK_NOALLOC (XTHAL_MEM_WRITEBACK_NOALLOC| XTHAL_AR_RWXrwx )
-
-#define XCHAL_CA_WRITETHRU (XTHAL_MEM_WRITETHRU | XTHAL_AR_RWXrwx)
-
-#define XCHAL_CA_ILLEGAL   (XTHAL_AR_NONE   | XTHAL_MEM_DEVICE)
-#define XCHAL_CA_BYPASS    (XTHAL_AR_RWXrwx | XTHAL_MEM_DEVICE)
-#define XCHAL_CA_BYPASSBUF    (XTHAL_AR_RWXrwx | XTHAL_MEM_DEVICE |\
-        XTHAL_MEM_BUFFERABLE)
-#define XCHAL_CA_BYPASS_RX (XTHAL_AR_RX     | XTHAL_MEM_DEVICE)
-#define XCHAL_CA_BYPASS_RW (XTHAL_AR_RW     | XTHAL_MEM_DEVICE)
-#define XCHAL_CA_BYPASS_R  (XTHAL_AR_R      | XTHAL_MEM_DEVICE)
-#define XCHAL_HAVE_CA_WRITEBACK_NOALLOC 1
-
-#define XCHAL_CA_R  (XTHAL_AR_R)
-#define XCHAL_CA_RX (XTHAL_AR_RX) 
-#define XCHAL_CA_RW (XTHAL_AR_RW) 
-#define XCHAL_CA_RWX (XTHAL_AR_RWX)
-
-
-/* 
- * Contents of MPU background map.
- * NOTE:  caller must define the XCHAL_MPU_BGMAP() macro (not defined here
- * but specified below) before expanding the XCHAL_MPU_BACKGROUND_MAP(s) macro.
- *
- * XCHAL_MPU_BGMAP(s, vaddr_start, vaddr_last, rights, memtype, x...)
- *
- *	s = passed from XCHAL_MPU_BACKGROUND_MAP(s), eg. to select how to expand
- *	vaddr_start = first byte of region (always 0 for first entry)
- *	vaddr_end = last byte of region (always 0xFFFFFFFF for last entry)
- *	rights = access rights
- *	memtype = memory type
- *	x = reserved for future use (0 until then)
- */
-#define XCHAL_MPU_BACKGROUND_MAP(s) \
-	XCHAL_MPU_BGMAP(s, 0x00000000, 0x7fffffff,  7,   6, 0) \
-	XCHAL_MPU_BGMAP(s, 0x80000000, 0xffffffff,  7,   6, 0) \
-	/* end */
-
-
-
-#endif /*XTENSA_CONFIG_CORE_MATMAP_H*/
-
diff --git a/src/platform/mt8365/include/arch/xtensa/config/defs.h b/src/platform/mt8365/include/arch/xtensa/config/defs.h
deleted file mode 100644
index 2a05ec08e4bb..000000000000
--- a/src/platform/mt8365/include/arch/xtensa/config/defs.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/* Definitions for Xtensa instructions, types, and protos. */
-
-/* Customer ID=13943; Build=0x75f5e; Copyright (c) 2003-2004 Tensilica Inc.
-
-   Permission is hereby granted, free of charge, to any person obtaining
-   a copy of this software and associated documentation files (the
-   "Software"), to deal in the Software without restriction, including
-   without limitation the rights to use, copy, modify, merge, publish,
-   distribute, sublicense, and/or sell copies of the Software, and to
-   permit persons to whom the Software is furnished to do so, subject to
-   the following conditions:
-
-   The above copyright notice and this permission notice shall be included
-   in all copies or substantial portions of the Software.
-
-   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
-
-/* NOTE: This file exists only for backward compatibility with T1050
-   and earlier Xtensa releases.  It includes only a subset of the
-   available header files.  */
-
-#ifndef _XTENSA_BASE_HEADER
-#define _XTENSA_BASE_HEADER
-
-#ifdef __XTENSA__
-
-#include <xtensa/tie/xt_core.h>
-#include <xtensa/tie/xt_misc.h>
-#include <xtensa/tie/xt_booleans.h>
-
-#endif /* __XTENSA__ */
-#endif /* !_XTENSA_BASE_HEADER */
diff --git a/src/platform/mt8365/include/arch/xtensa/config/specreg.h b/src/platform/mt8365/include/arch/xtensa/config/specreg.h
deleted file mode 100644
index 9345cc424d5a..000000000000
--- a/src/platform/mt8365/include/arch/xtensa/config/specreg.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
- * Xtensa Special Register symbolic names
- */
-
-/* $Id: //depot/rel/Foxhill/dot.9/Xtensa/SWConfig/hal/specreg.h.tpp#1 $ */
-
-/* Customer ID=13943; Build=0x75f5e; Copyright (c) 1998-2002 Tensilica Inc.
-
-   Permission is hereby granted, free of charge, to any person obtaining
-   a copy of this software and associated documentation files (the
-   "Software"), to deal in the Software without restriction, including
-   without limitation the rights to use, copy, modify, merge, publish,
-   distribute, sublicense, and/or sell copies of the Software, and to
-   permit persons to whom the Software is furnished to do so, subject to
-   the following conditions:
-
-   The above copyright notice and this permission notice shall be included
-   in all copies or substantial portions of the Software.
-
-   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
-
-#ifndef XTENSA_SPECREG_H
-#define XTENSA_SPECREG_H
-
-/*  Include these special register bitfield definitions, for historical reasons:  */
-#include <xtensa/corebits.h>
-
-
-/*  Special registers:  */
-#define LBEG		0
-#define LEND		1
-#define LCOUNT		2
-#define SAR		3
-#define BR		4
-#define PREFCTL		40
-#define WINDOWBASE	72
-#define WINDOWSTART	73
-#define MPUENB		90
-#define ERACCESS	95
-#define IBREAKENABLE	96
-#define MEMCTL		97
-#define CACHEADRDIS	98
-#define DDR		104
-#define IBREAKA_0	128
-#define IBREAKA_1	129
-#define DBREAKA_0	144
-#define DBREAKA_1	145
-#define DBREAKC_0	160
-#define DBREAKC_1	161
-#define EPC_1		177
-#define EPC_2		178
-#define EPC_3		179
-#define EPC_4		180
-#define DEPC		192
-#define EPS_2		194
-#define EPS_3		195
-#define EPS_4		196
-#define EXCSAVE_1	209
-#define EXCSAVE_2	210
-#define EXCSAVE_3	211
-#define EXCSAVE_4	212
-#define CPENABLE	224
-#define INTERRUPT	226
-#define INTENABLE	228
-#define PS		230
-#define VECBASE		231
-#define EXCCAUSE	232
-#define DEBUGCAUSE	233
-#define CCOUNT		234
-#define PRID		235
-#define ICOUNT		236
-#define ICOUNTLEVEL	237
-#define EXCVADDR	238
-#define CCOMPARE_0	240
-#define CCOMPARE_1	241
-#define CCOMPARE_2	242
-#define MISC_REG_0	244
-#define MISC_REG_1	245
-#define MISC_REG_2	246
-#define MISC_REG_3	247
-
-/*  Special cases (bases of special register series):  */
-#define IBREAKA		128
-#define DBREAKA		144
-#define DBREAKC		160
-#define EPC		176
-#define EPS		192
-#define EXCSAVE		208
-#define CCOMPARE	240
-
-/*  Special names for read-only and write-only interrupt registers:  */
-#define INTREAD		226
-#define INTSET		226
-#define INTCLEAR	227
-
-#endif /* XTENSA_SPECREG_H */
-
diff --git a/src/platform/mt8365/include/arch/xtensa/config/system.h b/src/platform/mt8365/include/arch/xtensa/config/system.h
deleted file mode 100644
index 2368853e0097..000000000000
--- a/src/platform/mt8365/include/arch/xtensa/config/system.h
+++ /dev/null
@@ -1,267 +0,0 @@
-/* 
- * xtensa/config/system.h -- HAL definitions that are dependent on SYSTEM configuration
- *
- *  NOTE: The location and contents of this file are highly subject to change.
- *
- *  Source for configuration-independent binaries (which link in a
- *  configuration-specific HAL library) must NEVER include this file.
- *  The HAL itself has historically included this file in some instances,
- *  but this is not appropriate either, because the HAL is meant to be
- *  core-specific but system independent.
- */
-
-/* Customer ID=13943; Build=0x75f5e; Copyright (c) 2000-2010 Tensilica Inc.
-
-   Permission is hereby granted, free of charge, to any person obtaining
-   a copy of this software and associated documentation files (the
-   "Software"), to deal in the Software without restriction, including
-   without limitation the rights to use, copy, modify, merge, publish,
-   distribute, sublicense, and/or sell copies of the Software, and to
-   permit persons to whom the Software is furnished to do so, subject to
-   the following conditions:
-
-   The above copyright notice and this permission notice shall be included
-   in all copies or substantial portions of the Software.
-
-   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
-
-
-#ifndef XTENSA_CONFIG_SYSTEM_H
-#define XTENSA_CONFIG_SYSTEM_H
-
-/*#include <xtensa/hal.h>*/
-
-
-
-/*----------------------------------------------------------------------
-				CONFIGURED SOFTWARE OPTIONS
-  ----------------------------------------------------------------------*/
-
-#define XSHAL_USE_ABSOLUTE_LITERALS	0	/* (sw-only option, whether software uses absolute literals) */
-#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals.  */
-
-#define XSHAL_ABI			XTHAL_ABI_WINDOWED	/* (sw-only option, selected ABI) */
-/*  The above maps to one of the following constants:  */
-#define XTHAL_ABI_WINDOWED		0
-#define XTHAL_ABI_CALL0			1
-/*  Alternatives:  */
-/*#define XSHAL_WINDOWED_ABI		1*/	/* set if windowed ABI selected */
-/*#define XSHAL_CALL0_ABI		0*/	/* set if call0 ABI selected */
-
-#define XSHAL_CLIB			XTHAL_CLIB_XCLIB	/* (sw-only option, selected C library) */
-/*  The above maps to one of the following constants:  */
-#define XTHAL_CLIB_NEWLIB		0
-#define XTHAL_CLIB_UCLIBC		1
-#define XTHAL_CLIB_XCLIB		2
-/*  Alternatives:  */
-/*#define XSHAL_NEWLIB			0*/	/* set if newlib C library selected */
-/*#define XSHAL_UCLIBC			0*/	/* set if uCLibC C library selected */
-/*#define XSHAL_XCLIB			1*/	/* set if Xtensa C library selected */
-
-#define XSHAL_USE_FLOATING_POINT	1
-
-#define XSHAL_FLOATING_POINT_ABI	1
-
-/*  SW workarounds enabled for HW errata:  */
-
-/*  SW options for functional safety:  */
-#define XSHAL_FUNC_SAFETY_ENABLED	0
-
-/*----------------------------------------------------------------------
-				DEVICE ADDRESSES
-  ----------------------------------------------------------------------*/
-
-/*
- *  Strange place to find these, but the configuration GUI
- *  allows moving these around to account for various core
- *  configurations.  Specific boards (and their BSP software)
- *  will have specific meanings for these components.
- */
-
-/*  I/O Block areas:  */
-#define XSHAL_IOBLOCK_CACHED_VADDR	0x70000000
-#define XSHAL_IOBLOCK_CACHED_PADDR	0x70000000
-#define XSHAL_IOBLOCK_CACHED_SIZE	0x0E000000
-
-#define XSHAL_IOBLOCK_BYPASS_VADDR	0x50000000
-#define XSHAL_IOBLOCK_BYPASS_PADDR	0x50000000
-#define XSHAL_IOBLOCK_BYPASS_SIZE	0x0E000000
-
-/*  System ROM:  */
-/*#define XSHAL_ROM_[VP]ADDR		...not configured...*/
-/*#define XSHAL_ROM_SIZE		...not configured...*/
-/*#define XSHAL_ROM_AVAIL_V{ADDR,SIZE}	...not configured...*/
-
-/*  System RAM:  */
-#define XSHAL_RAM_VADDR		0x40020000
-#define XSHAL_RAM_PADDR		0x40020000
-#define XSHAL_RAM_VSIZE		0x80000000
-#define XSHAL_RAM_PSIZE		0x80000000
-#define XSHAL_RAM_SIZE		XSHAL_RAM_PSIZE
-/*  Largest available area (free of vectors):  */
-#define XSHAL_RAM_AVAIL_VADDR	0x4002061C
-#define XSHAL_RAM_AVAIL_VSIZE	0x7FFFF9E4
-
-/*
- *  Shadow system RAM (same device as system RAM, at different address).
- *  (Emulation boards need this for the SONIC Ethernet driver
- *   when data caches are configured for writeback mode.)
- *  NOTE: on full MMU configs, this points to the BYPASS virtual address
- *  of system RAM, ie. is the same as XSHAL_RAM_* except that virtual
- *  addresses are viewed through the BYPASS static map rather than
- *  the CACHED static map.
- */
-#define XSHAL_RAM_BYPASS_VADDR		0x20000000
-#define XSHAL_RAM_BYPASS_PADDR		0x20000000
-#define XSHAL_RAM_BYPASS_PSIZE		0x20000000
-
-/*  Alternate system RAM (different device than system RAM):  */
-/*#define XSHAL_ALTRAM_[VP]ADDR		...not configured...*/
-/*#define XSHAL_ALTRAM_SIZE		...not configured...*/
-
-/*  Some available location in which to place devices in a simulation (eg. XTMP):  */
-#define XSHAL_SIMIO_CACHED_VADDR	0x20000000
-#define XSHAL_SIMIO_BYPASS_VADDR	0x20000000
-#define XSHAL_SIMIO_PADDR		0x20000000
-#define XSHAL_SIMIO_SIZE		0x20000000
-
-
-/*----------------------------------------------------------------------
- *  For use by reference testbench exit and diagnostic routines.
- */
-#define XSHAL_MAGIC_EXIT		0xcce5000
-
-/*----------------------------------------------------------------------
- *			DEVICE-ADDRESS DEPENDENT...
- *
- *  Values written to CACHEATTR special register (or its equivalent)
- *  to enable and disable caches in various modes.
- *----------------------------------------------------------------------*/
-
-/*----------------------------------------------------------------------
-			BACKWARD COMPATIBILITY ...
-  ----------------------------------------------------------------------*/
-
-/*
- *  NOTE:  the following two macros are DEPRECATED.  Use the latter
- *  board-specific macros instead, which are specially tuned for the
- *  particular target environments' memory maps.
- */
-#define XSHAL_CACHEATTR_BYPASS		XSHAL_XT2000_CACHEATTR_BYPASS	/* disable caches in bypass mode */
-#define XSHAL_CACHEATTR_DEFAULT		XSHAL_XT2000_CACHEATTR_DEFAULT	/* default setting to enable caches (no writeback!) */
-
-/*----------------------------------------------------------------------
-				GENERIC
-  ----------------------------------------------------------------------*/
-
-/*  For the following, a 512MB region is used if it contains a system (PIF) RAM,
- *  system (PIF) ROM, local memory, or XLMI.  */
-
-/*  These set any unused 512MB region to cache-BYPASS attribute:  */
-#define XSHAL_ALLVALID_CACHEATTR_WRITEBACK	0x24444424	/* enable caches in write-back mode */
-#define XSHAL_ALLVALID_CACHEATTR_WRITEALLOC	0x21111121	/* enable caches in write-allocate mode */
-#define XSHAL_ALLVALID_CACHEATTR_WRITETHRU	0x21111121	/* enable caches in write-through mode */
-#define XSHAL_ALLVALID_CACHEATTR_BYPASS		0x22222222	/* disable caches in bypass mode */
-#define XSHAL_ALLVALID_CACHEATTR_DEFAULT	XSHAL_ALLVALID_CACHEATTR_WRITEBACK	/* default setting to enable caches */
-
-/*  These set any unused 512MB region to ILLEGAL attribute:  */
-#define XSHAL_STRICT_CACHEATTR_WRITEBACK	0xF44444F4	/* enable caches in write-back mode */
-#define XSHAL_STRICT_CACHEATTR_WRITEALLOC	0xF11111F1	/* enable caches in write-allocate mode */
-#define XSHAL_STRICT_CACHEATTR_WRITETHRU	0xF11111F1	/* enable caches in write-through mode */
-#define XSHAL_STRICT_CACHEATTR_BYPASS		0xF22222F2	/* disable caches in bypass mode */
-#define XSHAL_STRICT_CACHEATTR_DEFAULT		XSHAL_STRICT_CACHEATTR_WRITEBACK	/* default setting to enable caches */
-
-/*  These set the first 512MB, if unused, to ILLEGAL attribute to help catch
- *  NULL-pointer dereference bugs; all other unused 512MB regions are set
- *  to cache-BYPASS attribute:  */
-#define XSHAL_TRAPNULL_CACHEATTR_WRITEBACK	0x24444424	/* enable caches in write-back mode */
-#define XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC	0x21111121	/* enable caches in write-allocate mode */
-#define XSHAL_TRAPNULL_CACHEATTR_WRITETHRU	0x21111121	/* enable caches in write-through mode */
-#define XSHAL_TRAPNULL_CACHEATTR_BYPASS		0x22222222	/* disable caches in bypass mode */
-#define XSHAL_TRAPNULL_CACHEATTR_DEFAULT	XSHAL_TRAPNULL_CACHEATTR_WRITEBACK	/* default setting to enable caches */
-
-/*----------------------------------------------------------------------
-			ISS (Instruction Set Simulator) SPECIFIC ...
-  ----------------------------------------------------------------------*/
-
-/*  For now, ISS defaults to the TRAPNULL settings:  */
-#define XSHAL_ISS_CACHEATTR_WRITEBACK	XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
-#define XSHAL_ISS_CACHEATTR_WRITEALLOC	XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC
-#define XSHAL_ISS_CACHEATTR_WRITETHRU	XSHAL_TRAPNULL_CACHEATTR_WRITETHRU
-#define XSHAL_ISS_CACHEATTR_BYPASS	XSHAL_TRAPNULL_CACHEATTR_BYPASS
-#define XSHAL_ISS_CACHEATTR_DEFAULT	XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
-
-#define XSHAL_ISS_PIPE_REGIONS	0
-#define XSHAL_ISS_SDRAM_REGIONS	0
-
-
-/*----------------------------------------------------------------------
-			XT2000 BOARD SPECIFIC ...
-  ----------------------------------------------------------------------*/
-
-/*  For the following, a 512MB region is used if it contains any system RAM,
- *  system ROM, local memory, XLMI, or other XT2000 board device or memory.
- *  Regions containing devices are forced to cache-BYPASS mode regardless
- *  of whether the macro is _WRITEBACK vs. _BYPASS etc.  */
-
-/*  These set any 512MB region unused on the XT2000 to ILLEGAL attribute:  */
-#define XSHAL_XT2000_CACHEATTR_WRITEBACK	0xF4444224	/* enable caches in write-back mode */
-#define XSHAL_XT2000_CACHEATTR_WRITEALLOC	0xF1111221	/* enable caches in write-allocate mode */
-#define XSHAL_XT2000_CACHEATTR_WRITETHRU	0xF1111221	/* enable caches in write-through mode */
-#define XSHAL_XT2000_CACHEATTR_BYPASS		0xF2222222	/* disable caches in bypass mode */
-#define XSHAL_XT2000_CACHEATTR_DEFAULT		XSHAL_XT2000_CACHEATTR_WRITEBACK	/* default setting to enable caches */
-
-#define XSHAL_XT2000_PIPE_REGIONS	0x00000000	/* BusInt pipeline regions */
-#define XSHAL_XT2000_SDRAM_REGIONS	0x00000014	/* BusInt SDRAM regions */
-
-
-/*----------------------------------------------------------------------
-				VECTOR INFO AND SIZES
-  ----------------------------------------------------------------------*/
-
-#define XSHAL_VECTORS_PACKED		0
-#define XSHAL_STATIC_VECTOR_SELECT	1
-#define XSHAL_RESET_VECTOR_VADDR	0x40000640
-#define XSHAL_RESET_VECTOR_PADDR	0x40000640
-
-/*
- *  Sizes allocated to vectors by the system (memory map) configuration.
- *  These sizes are constrained by core configuration (eg. one vector's
- *  code cannot overflow into another vector) but are dependent on the
- *  system or board (or LSP) memory map configuration.
- *
- *  Whether or not each vector happens to be in a system ROM is also
- *  a system configuration matter, sometimes useful, included here also:
- */
-#define XSHAL_RESET_VECTOR_SIZE	0x000002E0
-#define XSHAL_RESET_VECTOR_ISROM	0
-#define XSHAL_USER_VECTOR_SIZE	0x0000001C
-#define XSHAL_USER_VECTOR_ISROM	0
-#define XSHAL_PROGRAMEXC_VECTOR_SIZE	XSHAL_USER_VECTOR_SIZE	/* for backward compatibility */
-#define XSHAL_USEREXC_VECTOR_SIZE	XSHAL_USER_VECTOR_SIZE	/* for backward compatibility */
-#define XSHAL_KERNEL_VECTOR_SIZE	0x0000001C
-#define XSHAL_KERNEL_VECTOR_ISROM	0
-#define XSHAL_STACKEDEXC_VECTOR_SIZE	XSHAL_KERNEL_VECTOR_SIZE	/* for backward compatibility */
-#define XSHAL_KERNELEXC_VECTOR_SIZE	XSHAL_KERNEL_VECTOR_SIZE	/* for backward compatibility */
-#define XSHAL_DOUBLEEXC_VECTOR_SIZE	0x0000001C
-#define XSHAL_DOUBLEEXC_VECTOR_ISROM	0
-#define XSHAL_WINDOW_VECTORS_SIZE	0x00000178
-#define XSHAL_WINDOW_VECTORS_ISROM	0
-#define XSHAL_INTLEVEL2_VECTOR_SIZE	0x0000001C
-#define XSHAL_INTLEVEL2_VECTOR_ISROM	0
-#define XSHAL_INTLEVEL3_VECTOR_SIZE	0x0000001C
-#define XSHAL_INTLEVEL3_VECTOR_ISROM	0
-#define XSHAL_INTLEVEL4_VECTOR_SIZE	0x0000001C
-#define XSHAL_INTLEVEL4_VECTOR_ISROM	0
-#define XSHAL_DEBUG_VECTOR_SIZE		XSHAL_INTLEVEL4_VECTOR_SIZE
-#define XSHAL_DEBUG_VECTOR_ISROM	XSHAL_INTLEVEL4_VECTOR_ISROM
-
-
-#endif /*XTENSA_CONFIG_SYSTEM_H*/
-
diff --git a/src/platform/mt8365/include/arch/xtensa/config/tie-asm.h b/src/platform/mt8365/include/arch/xtensa/config/tie-asm.h
deleted file mode 100644
index 2d9c889ecc5b..000000000000
--- a/src/platform/mt8365/include/arch/xtensa/config/tie-asm.h
+++ /dev/null
@@ -1,336 +0,0 @@
-/* 
- * tie-asm.h -- compile-time HAL assembler definitions dependent on CORE & TIE
- *
- *  NOTE:  This header file is not meant to be included directly.
- */
-
-/* This header file contains assembly-language definitions (assembly
-   macros, etc.) for this specific Xtensa processor's TIE extensions
-   and options.  It is customized to this Xtensa processor configuration.
-
-   Customer ID=13943; Build=0x75f5e; Copyright (c) 1999-2018 Cadence Design Systems Inc.
-
-   Permission is hereby granted, free of charge, to any person obtaining
-   a copy of this software and associated documentation files (the
-   "Software"), to deal in the Software without restriction, including
-   without limitation the rights to use, copy, modify, merge, publish,
-   distribute, sublicense, and/or sell copies of the Software, and to
-   permit persons to whom the Software is furnished to do so, subject to
-   the following conditions:
-
-   The above copyright notice and this permission notice shall be included
-   in all copies or substantial portions of the Software.
-
-   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
-
-#ifndef _XTENSA_CORE_TIE_ASM_H
-#define _XTENSA_CORE_TIE_ASM_H
-
-/*  Selection parameter values for save-area save/restore macros:  */
-/*  Option vs. TIE:  */
-#define XTHAL_SAS_TIE	0x0001	/* custom extension or coprocessor */
-#define XTHAL_SAS_OPT	0x0002	/* optional (and not a coprocessor) */
-#define XTHAL_SAS_ANYOT	0x0003	/* both of the above */
-/*  Whether used automatically by compiler:  */
-#define XTHAL_SAS_NOCC	0x0004	/* not used by compiler w/o special opts/code */
-#define XTHAL_SAS_CC	0x0008	/* used by compiler without special opts/code */
-#define XTHAL_SAS_ANYCC	0x000C	/* both of the above */
-/*  ABI handling across function calls:  */
-#define XTHAL_SAS_CALR	0x0010	/* caller-saved */
-#define XTHAL_SAS_CALE	0x0020	/* callee-saved */
-#define XTHAL_SAS_GLOB	0x0040	/* global across function calls (in thread) */
-#define XTHAL_SAS_ANYABI	0x0070	/* all of the above three */
-/*  Misc  */
-#define XTHAL_SAS_ALL	0xFFFF	/* include all default NCP contents */
-#define XTHAL_SAS3(optie,ccuse,abi)	( ((optie) & XTHAL_SAS_ANYOT)  \
-					| ((ccuse) & XTHAL_SAS_ANYCC)  \
-					| ((abi)   & XTHAL_SAS_ANYABI) )
-
-
-    /*
-      *  Macro to store all non-coprocessor (extra) custom TIE and optional state
-      *  (not including zero-overhead loop registers).
-      *  Required parameters:
-      *      ptr         Save area pointer address register (clobbered)
-      *                  (register must contain a 4 byte aligned address).
-      *      at1..at4    Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
-      *                  registers are clobbered, the remaining are unused).
-      *  Optional parameters:
-      *      continue    If macro invoked as part of a larger store sequence, set to 1
-      *                  if this is not the first in the sequence.  Defaults to 0.
-      *      ofs         Offset from start of larger sequence (from value of first ptr
-      *                  in sequence) at which to store.  Defaults to next available space
-      *                  (or 0 if <continue> is 0).
-      *      select      Select what category(ies) of registers to store, as a bitmask
-      *                  (see XTHAL_SAS_xxx constants).  Defaults to all registers.
-      *      alloc       Select what category(ies) of registers to allocate; if any
-      *                  category is selected here that is not in <select>, space for
-      *                  the corresponding registers is skipped without doing any store.
-      */
-    .macro xchal_ncp_store  ptr at1 at2 at3 at4  continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
-	xchal_sa_start	\continue, \ofs
-	// Optional global registers used by default by the compiler:
-	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
-	xchal_sa_align	\ptr, 0, 1016, 4, 4
-	rur.THREADPTR	\at1		// threadptr option
-	s32i	\at1, \ptr, .Lxchal_ofs_+0
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
-	.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
-	xchal_sa_align	\ptr, 0, 1016, 4, 4
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
-	.endif
-	// Optional caller-saved registers not used by default by the compiler:
-	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
-	xchal_sa_align	\ptr, 0, 1016, 4, 4
-	rsr.BR	\at1		// boolean option
-	s32i	\at1, \ptr, .Lxchal_ofs_+0
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
-	.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
-	xchal_sa_align	\ptr, 0, 1016, 4, 4
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
-	.endif
-	// Custom caller-saved registers not used by default by the compiler:
-	.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
-	xchal_sa_align	\ptr, 0, 1012, 4, 4
-	rur.accreg_0	\at1		// ureg 3
-	s32i	\at1, \ptr, .Lxchal_ofs_+0
-	rur.accreg_1	\at1		// ureg 4
-	s32i	\at1, \ptr, .Lxchal_ofs_+4
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 8
-	.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
-	xchal_sa_align	\ptr, 0, 1012, 4, 4
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 8
-	.endif
-    .endm	// xchal_ncp_store
-
-    /*
-      *  Macro to load all non-coprocessor (extra) custom TIE and optional state
-      *  (not including zero-overhead loop registers).
-      *  Required parameters:
-      *      ptr         Save area pointer address register (clobbered)
-      *                  (register must contain a 4 byte aligned address).
-      *      at1..at4    Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
-      *                  registers are clobbered, the remaining are unused).
-      *  Optional parameters:
-      *      continue    If macro invoked as part of a larger load sequence, set to 1
-      *                  if this is not the first in the sequence.  Defaults to 0.
-      *      ofs         Offset from start of larger sequence (from value of first ptr
-      *                  in sequence) at which to load.  Defaults to next available space
-      *                  (or 0 if <continue> is 0).
-      *      select      Select what category(ies) of registers to load, as a bitmask
-      *                  (see XTHAL_SAS_xxx constants).  Defaults to all registers.
-      *      alloc       Select what category(ies) of registers to allocate; if any
-      *                  category is selected here that is not in <select>, space for
-      *                  the corresponding registers is skipped without doing any load.
-      */
-    .macro xchal_ncp_load  ptr at1 at2 at3 at4  continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
-	xchal_sa_start	\continue, \ofs
-	// Optional global registers used by default by the compiler:
-	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
-	xchal_sa_align	\ptr, 0, 1016, 4, 4
-	l32i	\at1, \ptr, .Lxchal_ofs_+0
-	wur.THREADPTR	\at1		// threadptr option
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
-	.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
-	xchal_sa_align	\ptr, 0, 1016, 4, 4
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
-	.endif
-	// Optional caller-saved registers not used by default by the compiler:
-	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
-	xchal_sa_align	\ptr, 0, 1016, 4, 4
-	l32i	\at1, \ptr, .Lxchal_ofs_+0
-	wsr.BR	\at1		// boolean option
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
-	.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
-	xchal_sa_align	\ptr, 0, 1016, 4, 4
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
-	.endif
-	// Custom caller-saved registers not used by default by the compiler:
-	.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
-	xchal_sa_align	\ptr, 0, 1012, 4, 4
-	l32i	\at1, \ptr, .Lxchal_ofs_+0
-	wur.accreg_0	\at1		// ureg 3
-	l32i	\at1, \ptr, .Lxchal_ofs_+4
-	wur.accreg_1	\at1		// ureg 4
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 8
-	.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
-	xchal_sa_align	\ptr, 0, 1012, 4, 4
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 8
-	.endif
-    .endm	// xchal_ncp_load
-
-
-#define XCHAL_NCP_NUM_ATMPS	1
-
-    /* 
-     *  Macro to store the state of TIE coprocessor AudioEngineLX.
-     *  Required parameters:
-     *      ptr         Save area pointer address register (clobbered)
-     *                  (register must contain a 8 byte aligned address).
-     *      at1..at4    Four temporary address registers (first XCHAL_CP1_NUM_ATMPS
-     *                  registers are clobbered, the remaining are unused).
-     *  Optional parameters are the same as for xchal_ncp_store.
-     */
-#define xchal_cp_AudioEngineLX_store	xchal_cp1_store
-    .macro	xchal_cp1_store  ptr at1 at2 at3 at4  continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
-	xchal_sa_start \continue, \ofs
-	// Custom caller-saved registers not used by default by the compiler:
-	.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
-	xchal_sa_align	\ptr, 0, 0, 8, 8
-	ae_s64.i	aed0, \ptr, .Lxchal_ofs_+40
-	ae_s64.i	aed1, \ptr, .Lxchal_ofs_+48
-	ae_s64.i	aed2, \ptr, .Lxchal_ofs_+56
-	addi	\ptr, \ptr, 64
-	ae_s64.i	aed3, \ptr, .Lxchal_ofs_+0
-	ae_s64.i	aed4, \ptr, .Lxchal_ofs_+8
-	ae_s64.i	aed5, \ptr, .Lxchal_ofs_+16
-	ae_s64.i	aed6, \ptr, .Lxchal_ofs_+24
-	ae_s64.i	aed7, \ptr, .Lxchal_ofs_+32
-	ae_s64.i	aed8, \ptr, .Lxchal_ofs_+40
-	ae_s64.i	aed9, \ptr, .Lxchal_ofs_+48
-	ae_s64.i	aed10, \ptr, .Lxchal_ofs_+56
-	addi	\ptr, \ptr, 64
-	ae_s64.i	aed11, \ptr, .Lxchal_ofs_+0
-	ae_s64.i	aed12, \ptr, .Lxchal_ofs_+8
-	ae_s64.i	aed13, \ptr, .Lxchal_ofs_+16
-	ae_s64.i	aed14, \ptr, .Lxchal_ofs_+24
-	ae_s64.i	aed15, \ptr, .Lxchal_ofs_+32
-	ae_movae	\at1, aep0
-	s8i	\at1, \ptr, .Lxchal_ofs_+40
-	ae_movae	\at1, aep1
-	s8i	\at1, \ptr, .Lxchal_ofs_+41
-	ae_movae	\at1, aep2
-	s8i	\at1, \ptr, .Lxchal_ofs_+42
-	ae_movae	\at1, aep3
-	s8i	\at1, \ptr, .Lxchal_ofs_+43
-	ae_salign64.i	u0, \ptr, .Lxchal_ofs_+48
-	ae_salign64.i	u1, \ptr, .Lxchal_ofs_+56
-	addi	\ptr, \ptr, 64
-	ae_salign64.i	u2, \ptr, .Lxchal_ofs_+0
-	ae_salign64.i	u3, \ptr, .Lxchal_ofs_+8
-	addi	\ptr, \ptr, -192
-	ae_movvfcrfsr	aed0		// ureg FCR_FSR
-	ae_s64.i	aed0, \ptr, .Lxchal_ofs_+0 + 0
-	rur.AE_OVF_SAR	\at1		// ureg 240
-	s32i	\at1, \ptr, .Lxchal_ofs_+8
-	rur.AE_BITHEAD	\at1		// ureg 241
-	s32i	\at1, \ptr, .Lxchal_ofs_+12
-	rur.AE_TS_FTS_BU_BP	\at1		// ureg 242
-	s32i	\at1, \ptr, .Lxchal_ofs_+16
-	rur.AE_CW_SD_NO	\at1		// ureg 243
-	s32i	\at1, \ptr, .Lxchal_ofs_+20
-	rur.AE_CBEGIN0	\at1		// ureg 246
-	s32i	\at1, \ptr, .Lxchal_ofs_+24
-	rur.AE_CEND0	\at1		// ureg 247
-	s32i	\at1, \ptr, .Lxchal_ofs_+28
-	rur.AE_CBEGIN1	\at1		// ureg 248
-	s32i	\at1, \ptr, .Lxchal_ofs_+32
-	rur.AE_CEND1	\at1		// ureg 249
-	s32i	\at1, \ptr, .Lxchal_ofs_+36
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 208
-	.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
-	xchal_sa_align	\ptr, 0, 0, 8, 8
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 208
-	.endif
-    .endm	// xchal_cp1_store
-
-    /* 
-     *  Macro to load the state of TIE coprocessor AudioEngineLX.
-     *  Required parameters:
-     *      ptr         Save area pointer address register (clobbered)
-     *                  (register must contain a 8 byte aligned address).
-     *      at1..at4    Four temporary address registers (first XCHAL_CP1_NUM_ATMPS
-     *                  registers are clobbered, the remaining are unused).
-     *  Optional parameters are the same as for xchal_ncp_load.
-     */
-#define xchal_cp_AudioEngineLX_load	xchal_cp1_load
-    .macro	xchal_cp1_load  ptr at1 at2 at3 at4  continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
-	xchal_sa_start \continue, \ofs
-	// Custom caller-saved registers not used by default by the compiler:
-	.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
-	xchal_sa_align	\ptr, 0, 0, 8, 8
-	ae_l64.i	aed0, \ptr, .Lxchal_ofs_+0 + 0		// ureg FCR_FSR
-	ae_movfcrfsrv	aed0
-	l32i	\at1, \ptr, .Lxchal_ofs_+8
-	wur.AE_OVF_SAR	\at1		// ureg 240
-	l32i	\at1, \ptr, .Lxchal_ofs_+12
-	wur.AE_BITHEAD	\at1		// ureg 241
-	l32i	\at1, \ptr, .Lxchal_ofs_+16
-	wur.AE_TS_FTS_BU_BP	\at1		// ureg 242
-	l32i	\at1, \ptr, .Lxchal_ofs_+20
-	wur.AE_CW_SD_NO	\at1		// ureg 243
-	l32i	\at1, \ptr, .Lxchal_ofs_+24
-	wur.AE_CBEGIN0	\at1		// ureg 246
-	l32i	\at1, \ptr, .Lxchal_ofs_+28
-	wur.AE_CEND0	\at1		// ureg 247
-	l32i	\at1, \ptr, .Lxchal_ofs_+32
-	wur.AE_CBEGIN1	\at1		// ureg 248
-	l32i	\at1, \ptr, .Lxchal_ofs_+36
-	wur.AE_CEND1	\at1		// ureg 249
-	ae_l64.i	aed0, \ptr, .Lxchal_ofs_+40
-	ae_l64.i	aed1, \ptr, .Lxchal_ofs_+48
-	ae_l64.i	aed2, \ptr, .Lxchal_ofs_+56
-	addi	\ptr, \ptr, 64
-	ae_l64.i	aed3, \ptr, .Lxchal_ofs_+0
-	ae_l64.i	aed4, \ptr, .Lxchal_ofs_+8
-	ae_l64.i	aed5, \ptr, .Lxchal_ofs_+16
-	ae_l64.i	aed6, \ptr, .Lxchal_ofs_+24
-	ae_l64.i	aed7, \ptr, .Lxchal_ofs_+32
-	ae_l64.i	aed8, \ptr, .Lxchal_ofs_+40
-	ae_l64.i	aed9, \ptr, .Lxchal_ofs_+48
-	ae_l64.i	aed10, \ptr, .Lxchal_ofs_+56
-	addi	\ptr, \ptr, 64
-	ae_l64.i	aed11, \ptr, .Lxchal_ofs_+0
-	ae_l64.i	aed12, \ptr, .Lxchal_ofs_+8
-	ae_l64.i	aed13, \ptr, .Lxchal_ofs_+16
-	ae_l64.i	aed14, \ptr, .Lxchal_ofs_+24
-	ae_l64.i	aed15, \ptr, .Lxchal_ofs_+32
-	addi	\ptr, \ptr, 40
-	l8ui	\at1, \ptr, .Lxchal_ofs_+0
-	ae_movea	aep0, \at1
-	l8ui	\at1, \ptr, .Lxchal_ofs_+1
-	ae_movea	aep1, \at1
-	l8ui	\at1, \ptr, .Lxchal_ofs_+2
-	ae_movea	aep2, \at1
-	l8ui	\at1, \ptr, .Lxchal_ofs_+3
-	ae_movea	aep3, \at1
-	addi	\ptr, \ptr, 8
-	ae_lalign64.i	u0, \ptr, .Lxchal_ofs_+0
-	ae_lalign64.i	u1, \ptr, .Lxchal_ofs_+8
-	ae_lalign64.i	u2, \ptr, .Lxchal_ofs_+16
-	ae_lalign64.i	u3, \ptr, .Lxchal_ofs_+24
-	.set	.Lxchal_pofs_, .Lxchal_pofs_ + 176
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 32
-	.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
-	xchal_sa_align	\ptr, 0, 0, 8, 8
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 208
-	.endif
-    .endm	// xchal_cp1_load
-
-#define XCHAL_CP1_NUM_ATMPS	1
-#define XCHAL_SA_NUM_ATMPS	1
-
-	/*  Empty macros for unconfigured coprocessors:  */
-	.macro xchal_cp0_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp0_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp2_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp2_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp3_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp3_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp4_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp4_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp5_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp5_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp6_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp6_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp7_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp7_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-
-#endif /*_XTENSA_CORE_TIE_ASM_H*/
-
diff --git a/src/platform/mt8365/include/arch/xtensa/config/tie.h b/src/platform/mt8365/include/arch/xtensa/config/tie.h
deleted file mode 100644
index 196c1fd575b8..000000000000
--- a/src/platform/mt8365/include/arch/xtensa/config/tie.h
+++ /dev/null
@@ -1,189 +0,0 @@
-/* 
- * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
- *
- *  NOTE:  This header file is not meant to be included directly.
- */
-
-/* This header file describes this specific Xtensa processor's TIE extensions
-   that extend basic Xtensa core functionality.  It is customized to this
-   Xtensa processor configuration.
-
-   Customer ID=13943; Build=0x75f5e; Copyright (c) 1999-2018 Cadence Design Systems Inc.
-
-   Permission is hereby granted, free of charge, to any person obtaining
-   a copy of this software and associated documentation files (the
-   "Software"), to deal in the Software without restriction, including
-   without limitation the rights to use, copy, modify, merge, publish,
-   distribute, sublicense, and/or sell copies of the Software, and to
-   permit persons to whom the Software is furnished to do so, subject to
-   the following conditions:
-
-   The above copyright notice and this permission notice shall be included
-   in all copies or substantial portions of the Software.
-
-   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
-
-#ifndef _XTENSA_CORE_TIE_H
-#define _XTENSA_CORE_TIE_H
-
-#define XCHAL_CP_NUM			1	/* number of coprocessors */
-#define XCHAL_CP_MAX			2	/* max CP ID + 1 (0 if none) */
-#define XCHAL_CP_MASK			0x02	/* bitmask of all CPs by ID */
-#define XCHAL_CP_PORT_MASK		0x00	/* bitmask of only port CPs */
-
-/*  Basic parameters of each coprocessor:  */
-#define XCHAL_CP1_NAME			"AudioEngineLX"
-#define XCHAL_CP1_IDENT			AudioEngineLX
-#define XCHAL_CP1_SA_SIZE		208	/* size of state save area */
-#define XCHAL_CP1_SA_ALIGN		8	/* min alignment of save area */
-#define XCHAL_CP_ID_AUDIOENGINELX   	1	/* coprocessor ID (0..7) */
-
-/*  Filler info for unassigned coprocessors, to simplify arrays etc:  */
-#define XCHAL_CP0_SA_SIZE		0
-#define XCHAL_CP0_SA_ALIGN		1
-#define XCHAL_CP2_SA_SIZE		0
-#define XCHAL_CP2_SA_ALIGN		1
-#define XCHAL_CP3_SA_SIZE		0
-#define XCHAL_CP3_SA_ALIGN		1
-#define XCHAL_CP4_SA_SIZE		0
-#define XCHAL_CP4_SA_ALIGN		1
-#define XCHAL_CP5_SA_SIZE		0
-#define XCHAL_CP5_SA_ALIGN		1
-#define XCHAL_CP6_SA_SIZE		0
-#define XCHAL_CP6_SA_ALIGN		1
-#define XCHAL_CP7_SA_SIZE		0
-#define XCHAL_CP7_SA_ALIGN		1
-
-/*  Save area for non-coprocessor optional and custom (TIE) state:  */
-#define XCHAL_NCP_SA_SIZE		16
-#define XCHAL_NCP_SA_ALIGN		4
-
-/*  Total save area for optional and custom state (NCP + CPn):  */
-#define XCHAL_TOTAL_SA_SIZE		224	/* with 16-byte align padding */
-#define XCHAL_TOTAL_SA_ALIGN		8	/* actual minimum alignment */
-
-/*
- * Detailed contents of save areas.
- * NOTE:  caller must define the XCHAL_SA_REG macro (not defined here)
- * before expanding the XCHAL_xxx_SA_LIST() macros.
- *
- * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
- *		dbnum,base,regnum,bitsz,gapsz,reset,x...)
- *
- *	s = passed from XCHAL_*_LIST(s), eg. to select how to expand
- *	ccused = set if used by compiler without special options or code
- *	abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
- *	kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
- *	opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg)
- *	name = lowercase reg name (no quotes)
- *	galign = group byte alignment (power of 2) (galign >= align)
- *	align = register byte alignment (power of 2)
- *	asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz)
- *	  (not including any pad bytes required to galign this or next reg)
- *	dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>)
- *	base = reg shortname w/o index (or sr=special, ur=TIE user reg)
- *	regnum = reg index in regfile, or special/TIE-user reg number
- *	bitsz = number of significant bits (regfile width, or ur/sr mask bits)
- *	gapsz = intervening bits, if bitsz bits not stored contiguously
- *	(padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize)
- *	reset = register reset value (or 0 if undefined at reset)
- *	x = reserved for future use (0 until then)
- *
- *  To filter out certain registers, e.g. to expand only the non-global
- *  registers used by the compiler, you can do something like this:
- *
- *  #define XCHAL_SA_REG(s,ccused,p...)	SELCC##ccused(p)
- *  #define SELCC0(p...)
- *  #define SELCC1(abikind,p...)	SELAK##abikind(p)
- *  #define SELAK0(p...)		REG(p)
- *  #define SELAK1(p...)		REG(p)
- *  #define SELAK2(p...)
- *  #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \
- *		...what you want to expand...
- */
-
-#define XCHAL_NCP_SA_NUM	4
-#define XCHAL_NCP_SA_LIST(s)	\
- XCHAL_SA_REG(s,1,2,1,1,      threadptr, 4, 4, 4,0x03E7,  ur,231, 32,0,0,0) \
- XCHAL_SA_REG(s,0,0,0,1,             br, 4, 4, 4,0x0204,  sr,4  , 16,0,0,0) \
- XCHAL_SA_REG(s,0,0,1,0,       accreg_0, 4, 4, 4,0x0303,  ur,3  , 32,0,0,0) \
- XCHAL_SA_REG(s,0,0,1,0,       accreg_1, 4, 4, 4,0x0304,  ur,4  , 32,0,0,0)
-
-#define XCHAL_CP0_SA_NUM	0
-#define XCHAL_CP0_SA_LIST(s)	/* empty */
-
-#define XCHAL_CP1_SA_NUM	33
-#define XCHAL_CP1_SA_LIST(s)	\
- XCHAL_SA_REG(s,0,0,1,0,        fcr_fsr, 8, 8, 8,0x1019,  ur,-1 ,  7,0,0,0) \
- XCHAL_SA_REG(s,0,0,1,0,     ae_ovf_sar, 4, 4, 4,0x03F0,  ur,240, 15,0,0,0) \
- XCHAL_SA_REG(s,0,0,1,0,     ae_bithead, 4, 4, 4,0x03F1,  ur,241, 32,0,0,0) \
- XCHAL_SA_REG(s,0,0,1,0,ae_ts_fts_bu_bp, 4, 4, 4,0x03F2,  ur,242, 16,0,0,0) \
- XCHAL_SA_REG(s,0,0,1,0,    ae_cw_sd_no, 4, 4, 4,0x03F3,  ur,243, 29,0,0,0) \
- XCHAL_SA_REG(s,0,0,1,0,     ae_cbegin0, 4, 4, 4,0x03F6,  ur,246, 32,0,0,0) \
- XCHAL_SA_REG(s,0,0,1,0,       ae_cend0, 4, 4, 4,0x03F7,  ur,247, 32,0,0,0) \
- XCHAL_SA_REG(s,0,0,1,0,     ae_cbegin1, 4, 4, 4,0x03F8,  ur,248, 32,0,0,0) \
- XCHAL_SA_REG(s,0,0,1,0,       ae_cend1, 4, 4, 4,0x03F9,  ur,249, 32,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aed0, 8, 8, 8,0x1000, aed,0  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aed1, 8, 8, 8,0x1001, aed,1  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aed2, 8, 8, 8,0x1002, aed,2  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aed3, 8, 8, 8,0x1003, aed,3  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aed4, 8, 8, 8,0x1004, aed,4  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aed5, 8, 8, 8,0x1005, aed,5  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aed6, 8, 8, 8,0x1006, aed,6  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aed7, 8, 8, 8,0x1007, aed,7  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aed8, 8, 8, 8,0x1008, aed,8  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aed9, 8, 8, 8,0x1009, aed,9  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed10, 8, 8, 8,0x100A, aed,10 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed11, 8, 8, 8,0x100B, aed,11 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed12, 8, 8, 8,0x100C, aed,12 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed13, 8, 8, 8,0x100D, aed,13 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed14, 8, 8, 8,0x100E, aed,14 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,          aed15, 8, 8, 8,0x100F, aed,15 , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aep0, 1, 1, 1,0x1014, aep,0  ,  8,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aep1, 1, 1, 1,0x1015, aep,1  ,  8,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aep2, 1, 1, 1,0x1016, aep,2  ,  8,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,           aep3, 1, 1, 1,0x1017, aep,3  ,  8,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,             u0, 8, 8, 8,0x1010,   u,0  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,             u1, 8, 8, 8,0x1011,   u,1  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,             u2, 8, 8, 8,0x1012,   u,2  , 64,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,             u3, 8, 8, 8,0x1013,   u,3  , 64,0,0,0)
-
-#define XCHAL_CP2_SA_NUM	0
-#define XCHAL_CP2_SA_LIST(s)	/* empty */
-
-#define XCHAL_CP3_SA_NUM	0
-#define XCHAL_CP3_SA_LIST(s)	/* empty */
-
-#define XCHAL_CP4_SA_NUM	0
-#define XCHAL_CP4_SA_LIST(s)	/* empty */
-
-#define XCHAL_CP5_SA_NUM	0
-#define XCHAL_CP5_SA_LIST(s)	/* empty */
-
-#define XCHAL_CP6_SA_NUM	0
-#define XCHAL_CP6_SA_LIST(s)	/* empty */
-
-#define XCHAL_CP7_SA_NUM	0
-#define XCHAL_CP7_SA_LIST(s)	/* empty */
-
-/* Byte length of instruction from its first nibble (op0 field), per FLIX.  */
-/* (not available, must use XCHAL_BYTE0_FORMAT_LENGTHS for this processor) */
-/* Byte length of instruction from its first byte, per FLIX.  */
-#define XCHAL_BYTE0_FORMAT_LENGTHS	\
-	3,3,3,3,3,3,3,3,2,2,2,2,2,2,6,11, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,6,11,\
-	3,3,3,3,3,3,3,3,2,2,2,2,2,2,6,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,6,11,\
-	3,3,3,3,3,3,3,3,2,2,2,2,2,2,6,11, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,6,11,\
-	3,3,3,3,3,3,3,3,2,2,2,2,2,2,6,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,6,11,\
-	3,3,3,3,3,3,3,3,2,2,2,2,2,2,6,11, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,6,11,\
-	3,3,3,3,3,3,3,3,2,2,2,2,2,2,6,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,6,11,\
-	3,3,3,3,3,3,3,3,2,2,2,2,2,2,6,11, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,6,11,\
-	3,3,3,3,3,3,3,3,2,2,2,2,2,2,6,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,6,11
-
-#endif /*_XTENSA_CORE_TIE_H*/
-
diff --git a/src/platform/mt8365/include/platform/drivers/idc.h b/src/platform/mt8365/include/platform/drivers/idc.h
deleted file mode 100644
index b638b9ec987e..000000000000
--- a/src/platform/mt8365/include/platform/drivers/idc.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2024 MediaTek. All rights reserved.
- *
- * Author: Andrew Perepech <andrew.perepech@mediatek.com>
- */
-
-#if defined(__XTOS_RTOS_IDC_H__) || defined(__ZEPHYR_RTOS_IDC_H__)
-
-#ifndef __PLATFORM_DRIVERS_IDC_H__
-#define __PLATFORM_DRIVERS_IDC_H__
-
-#include <stdint.h>
-
-struct idc_msg;
-
-static inline int idc_send_msg(struct idc_msg *msg, uint32_t mode)
-{
-	return 0;
-}
-
-static inline int idc_init(void)
-{
-	return 0;
-}
-
-#endif /* __PLATFORM_DRIVERS_IDC_H__ */
-
-#else
-
-#error "This file shouldn't be included from outside of Zephyr/XTOS's rtos/idc.h"
-
-#endif
diff --git a/src/platform/mt8365/include/platform/drivers/interrupt.h b/src/platform/mt8365/include/platform/drivers/interrupt.h
deleted file mode 100644
index c40b68ab1f42..000000000000
--- a/src/platform/mt8365/include/platform/drivers/interrupt.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2024 MediaTek. All rights reserved.
- *
- * Author: Andrew Perepech <andrew.perepech@mediatek.com>
- */
-
-#ifdef __SOF_DRIVERS_INTERRUPT_H__
-
-#ifndef __PLATFORM_DRIVERS_INTERRUPT_H__
-#define __PLATFORM_DRIVERS_INTERRUPT_H__
-
-#include <stdint.h>
-#include <platform/drivers/mt_reg_base.h>
-
-#define PLATFORM_IRQ_HW_NUM		XCHAL_NUM_INTERRUPTS
-#define PLATFORM_IRQ_FIRST_CHILD	PLATFORM_IRQ_HW_NUM
-#define PLATFORM_IRQ_CHILDREN		(LX_MCU_IRQ_B - LX_CQDMA_IRQ0_B + 1)
-
-#define IRQ_EXT_MASK			0x3F0
-
-/* interrupt table */
-#define MTK_DSP_EXT_IRQ0		0
-#define L1_INT_IRQ_B			1 // (INT_LEVEL(1) | IRQ_INVALID)
-#define L1_DSP_TIMER_IRQ0_B		2 // (INT_LEVEL(2) | INTERRUPT_ID(0))
-#define L1_DSP_TIMER_IRQ1_B		3 // (INT_LEVEL(3) | INTERRUPT_ID(1))
-#define L1_DSP_TIMER_IRQ2_B		4 // (INT_LEVEL(4) | INTERRUPT_ID(2))
-#define L1_DSP_TIMER_IRQ3_B		5 // (INT_LEVEL(5) | INTERRUPT_ID(3))
-#define MTK_DSP_EXT_IRQ6		6
-#define MTK_DSP_EXT_IRQ7		7
-#define MTK_DSP_EXT_IRQ8		8
-#define MTK_DSP_EXT_IRQ9		9
-#define MTK_DSP_EXT_IRQ10		10
-#define MTK_DSP_EXT_IRQ11		11
-#define MTK_DSP_EXT_IRQ12		12
-#define MTK_DSP_EXT_IRQ13		13
-#define MTK_DSP_EXT_IRQ14		14
-#define MTK_DSP_EXT_IRQ15		15
-/* HiFi internal interrupts */
-#define MTK_DSP_IRQ_TIMER0		16
-#define MTK_DSP_IRQ_TIMER1		17
-#define MTK_DSP_IRQ_TIMER2		18
-#define MTK_DSP_IRQ_WRITE_ERROR		19
-#define MTK_DSP_IRQ_PROFILING		20
-#define MTK_DSP_IRQ_SOFTWARE0		21
-#define MTK_DSP_IRQ_SOFTWARE1		22
-/* HiFi external interrupts */
-#define MTK_DSP_EXT_INT23		23
-#define MTK_DSP_EXT_INT24		24
-
-/* group 1 cascaded IRQ trigger L1_INT_IRQ_B */
-#define IRQ_EXT_GROUP1_BASE		L1_INT_IRQ_B
-#define LX_CQDMA_IRQ0_B			25 // (INT_LEVEL(1) | INTERRUPT_ID(4))
-#define LX_CQDMA_IRQ1_B			26 // (INT_LEVEL(1) | INTERRUPT_ID(5))
-#define LX_CQDMA_IRQ2_B			27 // (INT_LEVEL(1) | INTERRUPT_ID(6))
-#define LX_UART_IRQ_B			28 // (INT_LEVEL(1) | INTERRUPT_ID(7))
-#define LX_AFE_IRQ_B			29 // (INT_LEVEL(1) | INTERRUPT_ID(8))
-#define LX_MCU_IRQ_B			30 // (INT_LEVEL(1) | INTERRUPT_ID(9))
-
-int mtk_irq_group_id(uint32_t irq);
-
-/* L1_DSP_TIMER_IRQ0_B corresponds to bit# 0 of RG_DSP_IRQ_EN */
-#define IRQ_EXT_BIT_OFFSET		(-2)
-
-/* base_irq = 25; (LX_CQDMA_IRQ0_B - base_irq) corresponds to bit# 4 of RG_DSP_IRQ_EN */
-#define IRQ_EXT_GROUP1_BIT_OFFSET	(4)
-
-#define	RG_DSP_IRQ_EN			DSP_RG_INT_EN_CTL0
-#define	RG_DSP_IRQ_STATUS		DSP_RG_INT_STATUS0
-
-#endif /* __PLATFORM_DRIVERS_INTERRUPT_H__ */
-
-#else
-
-#error "This file shouldn't be included from outside of sof/drivers/interrupt.h"
-
-#endif /* __SOF_DRIVERS_INTERRUPT_H__ */
diff --git a/src/platform/mt8365/include/platform/drivers/mt_reg_base.h b/src/platform/mt8365/include/platform/drivers/mt_reg_base.h
deleted file mode 100644
index 289ab7d256d6..000000000000
--- a/src/platform/mt8365/include/platform/drivers/mt_reg_base.h
+++ /dev/null
@@ -1,138 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2024 MediaTek. All rights reserved.
- *
- * Author: Andrew Perepech <andrew.perepech@mediatek.com>
- */
-
-#ifndef MT_REG_BASE_H
-#define MT_REG_BASE_H
-
-#define DSP_REG_BASE                    (0x1D062000) /* DSPCFG base */
-#define DSP_TIMER_BASE                  (0x1D060000)
-#define DSP_UART0_BASE                  (0x1D061000)
-#define DSP_WDT_BASE                    (0x1D062400)
-#define DSP_IRQ_BASE                    (0x1D063000)
-#define DSP_D_TCM                       (CFG_HIFI4_DTCM_ADDRESS)
-#define DSP_I_TCM                       (CFG_HIFI4_ITCM_ADDRESS)
-#define DSP_DRAM_BASE                   (CFG_HIFI4_DRAM_ADDRESS)
-
-#define DSP_AUDIO_SRAM_BASE             (0x11221000)
-#define DSP_AUDIO_SRAM_SIZE             (0xA000)
-#define DSP_REG_REMAP_BASE              (0x1D060000)
-#define DSP_REG_REMAP_SIZE              (0x8000)
-#define DSP_SYS_REG_BASE                (0x10000000)
-#define DSP_SYS_REG_SIZE                (0x1221000)
-#define DSP_VER_REG_BASE                (0x08000000)
-#define DSP_VER_REG_SIZE                (0x1000)
-
-
-#define DSP_JTAGMUX          (DSP_REG_BASE + 0x0000)
-#define DSP_ALTRESETVEC      (DSP_REG_BASE + 0x0004)
-#define DSP_PDEBUGDATA       (DSP_REG_BASE + 0x0008)
-#define DSP_PDEBUGBUS0       (DSP_REG_BASE + 0x000c)
-#define DSP_PDEBUGBUS1       (DSP_REG_BASE + 0x0010)
-#define DSP_PDEBUGINST       (DSP_REG_BASE + 0x0014)
-#define DSP_PDEBUGLS0STAT    (DSP_REG_BASE + 0x0018)
-#define DSP_PDEBUGLS1STAT    (DSP_REG_BASE + 0x001c)
-#define DSP_PDEBUGPC         (DSP_REG_BASE + 0x0020)
-#define DSP_RESET_SW         (DSP_REG_BASE + 0x0024)
-#define DSP_PFAULTBUS        (DSP_REG_BASE + 0x0028)
-#define DSP_PFAULTINFO       (DSP_REG_BASE + 0x002c)
-#define DSP_GPR00            (DSP_REG_BASE + 0x0030)
-#define DSP_GPR01            (DSP_REG_BASE + 0x0034)
-#define DSP_GPR02            (DSP_REG_BASE + 0x0038)
-#define DSP_GPR03            (DSP_REG_BASE + 0x003c)
-#define DSP_GPR04            (DSP_REG_BASE + 0x0040)
-#define DSP_GPR05            (DSP_REG_BASE + 0x0044)
-#define DSP_GPR06            (DSP_REG_BASE + 0x0048)
-#define DSP_GPR07            (DSP_REG_BASE + 0x004c)
-#define DSP_GPR08            (DSP_REG_BASE + 0x0050)
-#define DSP_GPR09            (DSP_REG_BASE + 0x0054)
-#define DSP_GPR0A            (DSP_REG_BASE + 0x0058)
-#define DSP_GPR0B            (DSP_REG_BASE + 0x005c)
-#define DSP_GPR0C            (DSP_REG_BASE + 0x0060)
-#define DSP_GPR0D            (DSP_REG_BASE + 0x0064)
-#define DSP_GPR0E            (DSP_REG_BASE + 0x0068)
-#define DSP_GPR0F            (DSP_REG_BASE + 0x006c)
-#define DSP_GPR10            (DSP_REG_BASE + 0x0070)
-#define DSP_GPR11            (DSP_REG_BASE + 0x0074)
-#define DSP_GPR12            (DSP_REG_BASE + 0x0078)
-#define DSP_GPR13            (DSP_REG_BASE + 0x007c)
-#define DSP_GPR14            (DSP_REG_BASE + 0x0080)
-#define DSP_GPR15            (DSP_REG_BASE + 0x0084)
-#define DSP_GPR16            (DSP_REG_BASE + 0x0088)
-#define DSP_GPR17            (DSP_REG_BASE + 0x008c)
-#define DSP_GPR18            (DSP_REG_BASE + 0x0090)
-#define DSP_GPR19            (DSP_REG_BASE + 0x0094)
-#define DSP_GPR1A            (DSP_REG_BASE + 0x0098)
-#define DSP_GPR1B            (DSP_REG_BASE + 0x009c)
-#define DSP_GPR1C            (DSP_REG_BASE + 0x00a0)
-#define DSP_GPR1D            (DSP_REG_BASE + 0x00a4)
-#define DSP_GPR1E            (DSP_REG_BASE + 0x00a8)
-#define DSP_GPR1F            (DSP_REG_BASE + 0x00ac)
-#define DSP_TCM_OFFSET       (DSP_REG_BASE + 0x00b0)    /* not used */
-#define DSP_DDR_OFFSET       (DSP_REG_BASE + 0x00b4)    /* not used */
-#define DSP_INTFDSP          (DSP_REG_BASE + 0x00d0)
-#define DSP_INTFDSP_CLR      (DSP_REG_BASE + 0x00d4)
-#define DSP_SRAM_PD_SW1      (DSP_REG_BASE + 0x00d8)
-#define DSP_SRAM_PD_SW2      (DSP_REG_BASE + 0x00dc)
-#define DSP_OCD              (DSP_REG_BASE + 0x00e0)
-#define DSP_RG_DSP_IRQ_POL   (DSP_REG_BASE + 0x00f0)    /* not used */
-#define DSP_DSP_IRQ_EN       (DSP_REG_BASE + 0x00f4)    /* not used */
-#define DSP_DSP_IRQ_LEVEL    (DSP_REG_BASE + 0x00f8)    /* not used */
-#define DSP_DSP_IRQ_STATUS   (DSP_REG_BASE + 0x00fc)    /* not used */
-#define DSP_RG_INT2CIRQ      (DSP_REG_BASE + 0x0114)
-#define DSP_RG_INT_POL_CTL0  (DSP_REG_BASE + 0x0120)
-#define DSP_RG_INT_EN_CTL0   (DSP_REG_BASE + 0x0130)
-#define DSP_RG_INT_LV_CTL0   (DSP_REG_BASE + 0x0140)
-#define DSP_RG_INT_STATUS0   (DSP_REG_BASE + 0x0150)
-#define DSP_PDEBUGSTATUS0    (DSP_REG_BASE + 0x0200)
-#define DSP_PDEBUGSTATUS1    (DSP_REG_BASE + 0x0204)
-#define DSP_PDEBUGSTATUS2    (DSP_REG_BASE + 0x0208)
-#define DSP_PDEBUGSTATUS3    (DSP_REG_BASE + 0x020c)
-#define DSP_PDEBUGSTATUS4    (DSP_REG_BASE + 0x0210)
-#define DSP_PDEBUGSTATUS5    (DSP_REG_BASE + 0x0214)
-#define DSP_PDEBUGSTATUS6    (DSP_REG_BASE + 0x0218)
-#define DSP_PDEBUGSTATUS7    (DSP_REG_BASE + 0x021c)
-#define DSP_DSP2PSRAM_PRIORITY           (DSP_REG_BASE + 0x0220)  /* not used */
-#define DSP_AUDIO_DSP2SPM_INT            (DSP_REG_BASE + 0x0224)
-#define DSP_AUDIO_DSP2SPM_INT_ACK        (DSP_REG_BASE + 0x0228)
-#define DSP_AUDIO_DSP_DEBUG_SEL          (DSP_REG_BASE + 0x022C)
-#define DSP_AUDIO_DSP_EMI_BASE_ADDR      (DSP_REG_BASE + 0x02E0)  /* not used */
-#define DSP_AUDIO_DSP_SHARED_IRAM        (DSP_REG_BASE + 0x02E4)
-#define DSP_AUDIO_DSP_CKCTRL_P2P_CK_CON  (DSP_REG_BASE + 0x02F0)
-#define DSP_RG_SEMAPHORE00   (DSP_REG_BASE + 0x0300)
-#define DSP_RG_SEMAPHORE01   (DSP_REG_BASE + 0x0304)
-#define DSP_RG_SEMAPHORE02   (DSP_REG_BASE + 0x0308)
-#define DSP_RG_SEMAPHORE03   (DSP_REG_BASE + 0x030C)
-#define DSP_RG_SEMAPHORE04   (DSP_REG_BASE + 0x0310)
-#define DSP_RG_SEMAPHORE05   (DSP_REG_BASE + 0x0314)
-#define DSP_RG_SEMAPHORE06   (DSP_REG_BASE + 0x0318)
-#define DSP_RG_SEMAPHORE07   (DSP_REG_BASE + 0x031C)
-#define DSP_RESERVED_0       (DSP_REG_BASE + 0x03F0)
-#define DSP_RESERVED_1       (DSP_REG_BASE + 0x03F4)  /* use for tickless status */
-
-/* Redefinition for using Special registers */
-#define TICKLESS_STATUS_REG  (DSP_RESERVED_1)
-
-/* WDT CONFIGS */
-#define ADSP_WDT_MODE			(DSP_REG_BASE + 0x400 + 0x00)
-#define ADSP_WDT_LENGTH			(DSP_REG_BASE + 0x400 + 0x04)
-#define ADSP_WDT_RESTART		(DSP_REG_BASE + 0x400 + 0x08)
-#define ADSP_WDT_STA			(DSP_REG_BASE + 0x400 + 0x0C)
-#define ADSP_WDT_SWRST			(DSP_REG_BASE + 0x400 + 0x14)
-
-#define ADSP_WDT_SWRST_KEY		0x1209
-#define ADSP_WDT_RESTART_RELOAD		0x1971
-#define ADSP_WDT_LENGTH_KEY		0x8
-
-#define WDT_LENGTH_TIMEOUT(n)	((n) << 5)
-
-/* DSP IPI IRQ */
-#define CPU2DSP_IRQ		BIT(0)
-#define DSP2CPU_IRQ		BIT(1)
-#define DSP2SPM_IRQ_B		BIT(2)
-
-#endif /* MT_REG_BASE_H */
-
diff --git a/src/platform/mt8365/include/platform/drivers/timer.h b/src/platform/mt8365/include/platform/drivers/timer.h
deleted file mode 100644
index 8d389d5da4e0..000000000000
--- a/src/platform/mt8365/include/platform/drivers/timer.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- *
- * Copyright(c) 2024 MediaTek. All rights reserved.
- *
- * Author: Andrew Perepech <andrew.perepech@mediatek.com>
- */
-
-#ifndef __PLATFORM_DRIVERS_TIMER_H__
-#define __PLATFORM_DRIVERS_TIMER_H__
-
-#include <rtos/bit.h>
-#include <platform/drivers/mt_reg_base.h>
-
-
-/*-------timer:ostimer0-------*/
-enum ostimer {
-	OSTIMER0 = 0,
-	OSTIMER1,
-	OSTIMER2,
-	OSTIMER3,
-	NR_TMRS
-};
-
-#define TIMER_CON(n) (DSP_TIMER_BASE + 0x40 + 0x8 * (n))
-#define TIMER_CNT_VAL(n) (DSP_TIMER_BASE + 0x44 + 0x8 * (n))
-
-#define TIMER_ENABLE_BIT	(0x1 << 0)
-#define TIMER_IRQ_ENABLE	(0x1 << 1)
-#define TIMER_IRQ_STA		(0x1 << 4)
-#define TIMER_IRQ_CLEAR		(0x1 << 4)
-
-/**
- * system timer register map
- */
-#define CNTCR           (DSP_TIMER_BASE + 0x00)
-#define CNTSR           (DSP_TIMER_BASE + 0x04)
-#define CNTCV_L         (DSP_TIMER_BASE + 0x08)
-#define CNTCV_H         (DSP_TIMER_BASE + 0x0c)
-#define CNTWACR         (DSP_TIMER_BASE + 0x10)
-#define CNTRACR         (DSP_TIMER_BASE + 0x14)
-#define CNTACR_LOCK     (DSP_TIMER_BASE + 0x18)
-#define CNTFID0         (DSP_TIMER_BASE + 0x20)
-#define CNTFID1         (DSP_TIMER_BASE + 0x24)
-#define CNTFID2         (DSP_TIMER_BASE + 0x28)
-#define CNTFIDE         (DSP_TIMER_BASE + 0x2c)
-
-#define CNT_EN_BIT BIT(0)
-#define CLKSRC_BIT (BIT(8) | BIT(9))
-#define CLKSRC_13M_BIT BIT(8)
-#define COMP_BIT (BIT(10) | BIT(11) | BIT(12))
-#define COMP_20_25_EN_BIT (BIT(11) | BIT(12))
-
-#define CNT_EN          (0x1 << 0)
-#define CNTTVAL_EN      (0x1 << 0)
-#define CNTIRQ_EN       (0x1 << 1)
-#define CNTIRQ_STACLR   (0x1 << 4)
-#define CNTMODE_REPEAT  (0x1 << 8)
-
-
-#define DELAY_TIMER_1US_TICK       (13U) // (13MHz)
-#define DELAY_TIMER_1MS_TICK       (13000U) // (13MHz)
-#define TIME_TO_TICK_US(us) ((us)*DELAY_TIMER_1US_TICK)
-#define TIME_TO_TICK_MS(ms) ((ms)*DELAY_TIMER_1MS_TICK)
-
-#define SYSTICK_TIMER_IRQ           L1_DSP_TIMER_IRQ0_B
-
-
-#endif /* __PLATFORM_DRIVERS_TIMER_H__ */
diff --git a/src/platform/mt8365/include/platform/lib/clk.h b/src/platform/mt8365/include/platform/lib/clk.h
deleted file mode 100644
index beaa2f762bbe..000000000000
--- a/src/platform/mt8365/include/platform/lib/clk.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2024 MediaTek. All rights reserved.
- *
- * Author: Andrew Perepech <andrew.perepech@mediatek.com>
- */
-
-#ifdef __SOF_LIB_CLK_H__
-
-#ifndef __PLATFORM_LIB_CLK_H__
-#define __PLATFORM_LIB_CLK_H__
-
-#include <stdint.h>
-
-struct sof;
-
-#define CPU_DEFAULT_IDX             4
-
-#define CLK_CPU(x)                  (x)
-#define CLK_DEFAULT_CPU_HZ          600000000
-#define CLK_MAX_CPU_HZ              600000000
-#define CLK_SUSPEND_CPU_HZ          26000000
-#define NUM_CLOCKS                  1
-#define NUM_CPU_FREQ                5
-
-void platform_clock_init(struct sof *sof);
-
-#define REG_APMIXDSYS_BASE     0x1000C000
-#define REG_TOPCKGEN_BASE      0x10000000
-
-#define DSPPLL_CON0            (REG_APMIXDSYS_BASE + 0x390)
-#define DSPPLL_CON1            (REG_APMIXDSYS_BASE + 0x394)
-#define DSPPLL_CON2            (REG_APMIXDSYS_BASE + 0x398)
-#define DSPPLL_CON3            (REG_APMIXDSYS_BASE + 0x39C)
-
-#define ULPLL_CON0             (REG_APMIXDSYS_BASE + 0x3B0)
-#define ULPLL_CON1             (REG_APMIXDSYS_BASE + 0x3B4)
-
-#define PLL_BASE_EN            BIT(0)
-#define PLL_PWR_ON             BIT(0)
-#define PLL_ISO_EN             BIT(1)
-
-#define DSPPLL_312MHZ          0
-#define DSPPLL_400MHZ          1
-#define DSPPLL_600MHZ          2
-
-#define CLK_MODE               (REG_TOPCKGEN_BASE + 0x0)
-#define CLK_CFG_UPDATE1        (REG_TOPCKGEN_BASE + 0x8)
-#define CLK_CFG_8              (REG_TOPCKGEN_BASE + 0xC0)
-#define CLK_CFG_8_SET          (REG_TOPCKGEN_BASE + 0xC4)
-#define CLK_CFG_8_CLR          (REG_TOPCKGEN_BASE + 0xC8)
-
-#define CLK_SCP_CFG_1          (REG_TOPCKGEN_BASE + 0x204)
-
-#define CLK_DSP_SEL_26M               0
-#define CLK_DSP_SEL_26M_D_2           1
-#define CLK_DSP_SEL_DSPPLL            2
-#define CLK_DSP_SEL_DSPPLL_D_2        3
-#define CLK_DSP_SEL_DSPPLL_D_4        4
-#define CLK_DSP_SEL_DSPPLL_D_8        5
-
-#define CLK_TOPCKGEN_SEL_PLLGP_26M    1
-#define CLK_TOPCKGEN_SEL_ULPLL_26M    2
-#define CLK_TOPCKGEN_SEL_GPIO_26M     4
-
-enum mux_id_t {
-	MUX_CLK_DSP_SEL = 0,
-	MUX_CLK_TOPCKGEN_26M_SEL,
-	HIFI4DSP_MUX_NUM,
-};
-
-enum mux_26m_t {
-	DCXO_26 = 0,
-	ULPLL_26M,
-};
-
-enum DSP_HW_DSP_CLK {
-	DSP_CLK_13M = 0,
-	DSP_CLK_26M,
-	DSP_CLK_PLL_312M,
-	DSP_CLK_PLL_400M,
-	DSP_CLK_PLL_600M,
-};
-#endif /* __PLATFORM_LIB_CLK_H__ */
-
-#else
-
-#error "This file shouldn't be included from outside of sof/lib/clk.h"
-
-#endif /* __SOF_LIB_CLK_H__ */
diff --git a/src/platform/mt8365/include/platform/lib/cpu.h b/src/platform/mt8365/include/platform/lib/cpu.h
deleted file mode 100644
index 1c72bd51b176..000000000000
--- a/src/platform/mt8365/include/platform/lib/cpu.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2024 MediaTek. All rights reserved.
- *
- * Author: Andrew Perepech <andrew.perepech@mediatek.com>
- */
-
-#ifdef __SOF_LIB_CPU_H__
-
-#ifndef __PLATFORM_LIB_CPU_H__
-#define __PLATFORM_LIB_CPU_H__
-
-/** \brief Id of primary DSP core */
-#define PLATFORM_PRIMARY_CORE_ID 0
-
-#endif /* __PLATFORM_LIB_CPU_H__ */
-
-#else
-
-#error "This file shouldn't be included from outside of sof/lib/cpu.h"
-
-#endif /* __SOF_LIB_CPU_H__ */
diff --git a/src/platform/mt8365/include/platform/lib/dai.h b/src/platform/mt8365/include/platform/lib/dai.h
deleted file mode 100644
index 98fe70955f2f..000000000000
--- a/src/platform/mt8365/include/platform/lib/dai.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2024 MediaTek. All rights reserved.
- *
- * Author: Andrew Perepech <andrew.perepech@mediatek.com>
- */
-
-#ifdef __SOF_LIB_DAI_H__
-
-#ifndef __PLATFORM_LIB_DAI_H__
-#define __PLATFORM_LIB_DAI_H__
-
-#endif /* __PLATFORM_LIB_DAI_H__ */
-
-#else
-
-#error "This file shouldn't be included from outside of sof/lib/dai.h"
-
-#endif /* __SOF_LIB_DAI_H__ */
diff --git a/src/platform/mt8365/include/platform/lib/dma.h b/src/platform/mt8365/include/platform/lib/dma.h
deleted file mode 100644
index 479591ab5daa..000000000000
--- a/src/platform/mt8365/include/platform/lib/dma.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2024 MediaTek. All rights reserved.
- *
- * Author: Andrew Perepech <andrew.perepech@mediatek.com>
- */
-
-#ifdef __SOF_LIB_DMA_H__
-
-#ifndef __PLATFORM_LIB_DMA_H__
-#define __PLATFORM_LIB_DMA_H__
-
-#define PLATFORM_NUM_DMACS 2
-
-/* max number of supported DMA channels */
-#define PLATFORM_MAX_DMA_CHAN 32
-
-#define DMA_ID_AFE_MEMIF 0
-#define DMA_ID_HOST 1
-
-#define dma_chan_irq(dma, chan) dma_irq(dma)
-#define dma_chan_irq_name(dma, chan) dma_irq_name(dma)
-
-#endif /* __PLATFORM_LIB_DMA_H__ */
-
-#else
-
-#error "This file shouldn't be included from outside of sof/lib/dma.h"
-
-#endif /* __SOF_LIB_DMA_H__ */
diff --git a/src/platform/mt8365/include/platform/lib/mailbox.h b/src/platform/mt8365/include/platform/lib/mailbox.h
deleted file mode 100644
index 27f48a72238c..000000000000
--- a/src/platform/mt8365/include/platform/lib/mailbox.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2024 MediaTek. All rights reserved.
- *
- * Author: Andrew Perepech <andrew.perepech@mediatek.com>
- */
-
-#ifdef __SOF_LIB_MAILBOX_H__
-
-#ifndef __PLATFORM_LIB_MAILBOX_H__
-#define __PLATFORM_LIB_MAILBOX_H__
-
-#include <sof/lib/memory.h>
-#include <stddef.h>
-#include <stdint.h>
-
-/*
- * The Window Region on MT8365 SRAM is organised like this :-
- * +--------------------------------------------------------------------------+
- * | Offset              | Region         |  Size                             |
- * +---------------------+----------------+-----------------------------------+
- * | SRAM_TRACE_BASE     | Trace Buffer   |  SRAM_TRACE_SIZE                  |
- * +---------------------+----------------+-----------------------------------+
- * | SRAM_DEBUG_BASE     | Debug data     |  SRAM_DEBUG_SIZE                  |
- * +---------------------+----------------+-----------------------------------+
- * | SRAM_INBOX_BASE     | Inbox          |  SRAM_INBOX_SIZE                  |
- * +---------------------+----------------+-----------------------------------+
- * | SRAM_OUTBOX_BASE    | Outbox         |  SRAM_MAILBOX_SIZE                |
- * +---------------------+----------------+-----------------------------------+
- */
-
-#define MAILBOX_DSPBOX_SIZE SRAM_OUTBOX_SIZE
-#define MAILBOX_DSPBOX_BASE SRAM_OUTBOX_BASE
-#define MAILBOX_DSPBOX_OFFSET SRAM_OUTBOX_OFFSET
-
-#define MAILBOX_HOSTBOX_SIZE SRAM_INBOX_SIZE
-#define MAILBOX_HOSTBOX_BASE SRAM_INBOX_BASE
-#define MAILBOX_HOSTBOX_OFFSET SRAM_INBOX_OFFSET
-
-#define MAILBOX_DEBUG_SIZE SRAM_DEBUG_SIZE
-#define MAILBOX_DEBUG_BASE SRAM_DEBUG_BASE
-#define MAILBOX_DEBUG_OFFSET SRAM_DEBUG_OFFSET
-
-#define MAILBOX_TRACE_SIZE SRAM_TRACE_SIZE
-#define MAILBOX_TRACE_BASE SRAM_TRACE_BASE
-#define MAILBOX_TRACE_OFFSET SRAM_TRACE_OFFSET
-
-#define MAILBOX_EXCEPTION_SIZE SRAM_EXCEPT_SIZE
-#define MAILBOX_EXCEPTION_BASE SRAM_EXCEPT_BASE
-#define MAILBOX_EXCEPTION_OFFSET SRAM_EXCEPT_OFFSET
-
-#define MAILBOX_STREAM_SIZE SRAM_STREAM_SIZE
-#define MAILBOX_STREAM_BASE SRAM_STREAM_BASE
-#define MAILBOX_STREAM_OFFSET SRAM_STREAM_OFFSET
-
-static inline void mailbox_sw_reg_write(size_t offset, uint32_t src)
-{
-	volatile uint32_t *ptr;
-
-	ptr = (volatile uint32_t *)(MAILBOX_DEBUG_BASE + offset);
-	*ptr = src;
-}
-
-static inline uint32_t mailbox_sw_reg_read(size_t offset)
-{
-	volatile uint32_t *ptr;
-
-	ptr = (volatile uint32_t *)(MAILBOX_DEBUG_BASE + offset);
-
-	return *ptr;
-}
-
- #define ADSP_IPI_OP_REQ 0x1
- #define ADSP_IPI_OP_RSP 0x2
-void trigger_irq_to_host_req(void);
-void trigger_irq_to_host_rsp(void);
-
-#endif /* __PLATFORM_LIB_MAILBOX_H__ */
-
-#else
-
-#error "This file shouldn't be included from outside of sof/lib/mailbox.h"
-
-#endif /* __SOF_LIB_MAILBOX_H__ */
diff --git a/src/platform/mt8365/include/platform/lib/memory.h b/src/platform/mt8365/include/platform/lib/memory.h
deleted file mode 100644
index 93bf268c93a2..000000000000
--- a/src/platform/mt8365/include/platform/lib/memory.h
+++ /dev/null
@@ -1,231 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2024 MediaTek. All rights reserved.
- *
- * Author: Andrew Perepech <andrew.perepech@mediatek.com>
- */
-
-#ifdef __SOF_LIB_MEMORY_H__
-
-#ifndef __PLATFORM_LIB_MEMORY_H__
-#define __PLATFORM_LIB_MEMORY_H__
-
-#include <rtos/cache.h>
-#include <xtensa/config/core-isa.h>
-
-#define BOOT_WITH_DRAM /*Use DRAM as SRAM1 for heap related*/
-/* data cache line alignment */
-#define PLATFORM_DCACHE_ALIGN sizeof(void *)
-
-/*
- * +-----------------------------------+-----------------------------+
- * |                                   |    AUDIO_DSP_SHARED_DRAM    |
- * +------------+----------------------+---------+---------+---------+
- * |    DSP     |    Sys     | Size    | 00b     | 01b *** | 11b     |
- * +------------+------------+---------+---------+---------+---------+
- * | 0x40000000 | 0x1e100000 | 0x8000  | iram0_0 | iram0_0 | iram0_0 |
- * | 0x40008000 | 0x1e108000 | 0x8000  | iram0_1 | iram0_1 | ---     |
- * | 0x40010000 | 0x1e110000 | 0x8000  | iram1   | ---     | ---     |
- * +------------+------------+---------+---------+---------+---------+
- * | 0x1e000000 | 0x1e000000 | 0x40000 | dram0   | dram0   | dram0   |
- * | 0x1e040000 | 0x1e040000 | 0x20000 | dram1   | dram1   | dram1   |
- * | 0x1e060000 | 0x1e060000 | 0x8000  | ---     | iram1   | iram1   |
- * | 0x1e068000 | 0x1e068000 | 0x8000  | ---     | ---     | iram0_1 |
- * +------------+------------+---------+---------+---------+---------+
- */
-
-/* BOOT_WITH_DRAM ONLY */
-/* physical DSP addresses */
-#define DRAM_BASE 0x60000000
-#define DRAM_AUDIO_SHARED_SIZE 0x280000
-#define DRAM_SIZE 0x1000000 /*DRAM Size : 16M , need to sync with Host side*/
-
-#define SRAM_TOTAL_SIZE 0x40000 /*256KB DSP SRAM*/
-#define VECTOR_SIZE 0x628
-
-#define SRAM0_BASE DRAM_BASE
-#define SRAM0_SIZE (DRAM_SIZE >> 1)
-#define SRAM1_BASE (DRAM_BASE + SRAM0_SIZE)
-#define SRAM1_SIZE                                                                                 \
-	(DRAM_SIZE - SRAM0_SIZE - DRAM_AUDIO_SHARED_SIZE - UUID_ENTRY_ELF_SIZE -                   \
-	 LOG_ENTRY_ELF_SIZE - EXT_MANIFEST_ELF_SIZE)
-
-#define DMA_SIZE 0x100000
-
-#define UUID_ENTRY_ELF_SIZE 0x6000
-#define LOG_ENTRY_ELF_SIZE 0x200000
-#define EXT_MANIFEST_ELF_SIZE 0x100000
-
-#define UUID_ENTRY_ELF_BASE (SRAM1_BASE + SRAM1_SIZE)
-#define LOG_ENTRY_ELF_BASE (UUID_ENTRY_ELF_BASE + UUID_ENTRY_ELF_SIZE)
-#define EXT_MANIFEST_ELF_BASE (LOG_ENTRY_ELF_BASE + LOG_ENTRY_ELF_SIZE)
-
-/*
- * The Memory Layout on MT8365 are organised like this :-
- *
- * +--------------------------------------------------------------------------+
- * | Offset              | Region         |  Size                             |
- * +---------------------+----------------+-----------------------------------+
- * | XCHAL_RESET_VECTOR0 | DSP Vectors    |  VECTOR_SIZE                      |
- * +---------------------+----------------+-----------------------------------+
- * | SRAM0_BASE          | fw_ready       |  SRAM0_SIZE                       |
- * |                     | RO Data        |                                   |
- * |                     | module_init    |                                   |
- * |                     | Text           |                                   |
- * |                     | Data           |                                   |
- * |                     | BSS            |                                   |
- * +---------------------+----------------+-----------------------------------+
- * | SRAM1_BASE          | MAILBOX        |  SOF_MAILBOX_SIZE                 |
- * +---------------------+----------------+-----------------------------------+
- * | HEAP_SYSTEM_BASE    | System Heap    |  HEAP_SYSTEM_SIZE                 |
- * +---------------------+----------------+-----------------------------------+
- * | HEAP_RUNTIME_BASE   | Runtime Heap   |  HEAP_RUNTIME_SIZE                |
- * +---------------------+----------------+-----------------------------------+
- * | HEAP_BUFFER_BASE    | Module Buffers |  HEAP_BUFFER_SIZE                 |
- * +---------------------+----------------+-----------------------------------+
- * | SOF_STACK_END       | Stack          |  SOF_STACK_SIZE                   |
- * +---------------------+----------------+-----------------------------------+
- * | SOF_STACK_BASE      |                |                                   |
- * +---------------------+----------------+-----------------------------------+
- */
-
-/* Mailbox configuration */
-#define SRAM_OUTBOX_BASE SRAM1_BASE
-#define SRAM_OUTBOX_SIZE 0x1000
-#define SRAM_OUTBOX_OFFSET 0
-
-#define SRAM_INBOX_BASE (SRAM_OUTBOX_BASE + SRAM_OUTBOX_SIZE)
-#define SRAM_INBOX_SIZE 0x1000
-#define SRAM_INBOX_OFFSET SRAM_OUTBOX_SIZE
-
-#define SRAM_DEBUG_BASE (SRAM_INBOX_BASE + SRAM_INBOX_SIZE)
-#define SRAM_DEBUG_SIZE 0x800
-#define SRAM_DEBUG_OFFSET (SRAM_INBOX_OFFSET + SRAM_INBOX_SIZE)
-
-#define SRAM_EXCEPT_BASE (SRAM_DEBUG_BASE + SRAM_DEBUG_SIZE)
-#define SRAM_EXCEPT_SIZE 0x800
-#define SRAM_EXCEPT_OFFSET (SRAM_DEBUG_OFFSET + SRAM_DEBUG_SIZE)
-
-#define SRAM_STREAM_BASE (SRAM_EXCEPT_BASE + SRAM_EXCEPT_SIZE)
-#define SRAM_STREAM_SIZE 0x1000
-#define SRAM_STREAM_OFFSET (SRAM_EXCEPT_OFFSET + SRAM_EXCEPT_SIZE)
-
-#define SRAM_TRACE_BASE (SRAM_STREAM_BASE + SRAM_STREAM_SIZE)
-#define SRAM_TRACE_SIZE 0x1000
-#define SRAM_TRACE_OFFSET (SRAM_STREAM_OFFSET + SRAM_STREAM_SIZE)
-
-/*4K + 4K +2K + 2K + 4K + 4K = 20KB*/
-#define SOF_MAILBOX_SIZE                                                                           \
-	(SRAM_INBOX_SIZE + SRAM_OUTBOX_SIZE + SRAM_DEBUG_SIZE + SRAM_EXCEPT_SIZE +                 \
-	 SRAM_STREAM_SIZE + SRAM_TRACE_SIZE)
-
-/* Heap section sizes for module pool */
-#define HEAP_RT_COUNT8 0
-#define HEAP_RT_COUNT16 48
-#define HEAP_RT_COUNT32 48
-#define HEAP_RT_COUNT64 32
-#define HEAP_RT_COUNT128 32
-#define HEAP_RT_COUNT256 32
-#define HEAP_RT_COUNT512 32
-#define HEAP_RT_COUNT1024 4
-#define HEAP_RT_COUNT2048 2
-#define HEAP_RT_COUNT4096 2
-
-/* Heap section sizes for system runtime heap */
-#define HEAP_SYS_RT_COUNT64 128
-#define HEAP_SYS_RT_COUNT512 16
-#define HEAP_SYS_RT_COUNT1024 8
-
-/* Heap configuration */
-
-#define HEAP_SYSTEM_BASE (SRAM1_BASE + SOF_MAILBOX_SIZE)
-#define HEAP_SYSTEM_SIZE 0x6000
-
-#define HEAP_SYSTEM_0_BASE HEAP_SYSTEM_BASE
-
-#define HEAP_SYS_RUNTIME_BASE (HEAP_SYSTEM_BASE + HEAP_SYSTEM_SIZE)
-/*24KB*/
-#define HEAP_SYS_RUNTIME_SIZE                                                                      \
-	(HEAP_SYS_RT_COUNT64 * 64 + HEAP_SYS_RT_COUNT512 * 512 + HEAP_SYS_RT_COUNT1024 * 1024)
-
-#define HEAP_RUNTIME_BASE (HEAP_SYS_RUNTIME_BASE + HEAP_SYS_RUNTIME_SIZE)
-/*48*(16 +32) + 32*(64 128+256) + 4*(512+1024) + 1*2048 = 24832 = 24.25KB*/
-#define HEAP_RUNTIME_SIZE                                                                          \
-	(HEAP_RT_COUNT8 * 8 + HEAP_RT_COUNT16 * 16 + HEAP_RT_COUNT32 * 32 + HEAP_RT_COUNT64 * 64 + \
-	 HEAP_RT_COUNT128 * 128 + HEAP_RT_COUNT256 * 256 + HEAP_RT_COUNT512 * 512 +                \
-	 HEAP_RT_COUNT1024 * 1024 + HEAP_RT_COUNT2048 * 2048 + HEAP_RT_COUNT4096 * 4096)
-
-#define HEAP_BUFFER_BASE (HEAP_RUNTIME_BASE + HEAP_RUNTIME_SIZE)
-#define HEAP_BUFFER_SIZE                                                                           \
-	(SRAM1_SIZE - SOF_MAILBOX_SIZE - HEAP_RUNTIME_SIZE - SOF_STACK_TOTAL_SIZE -                \
-	 HEAP_SYS_RUNTIME_SIZE - HEAP_SYSTEM_SIZE)
-
-#define HEAP_BUFFER_BLOCK_SIZE 0x100
-#define HEAP_BUFFER_COUNT (HEAP_BUFFER_SIZE / HEAP_BUFFER_BLOCK_SIZE)
-
-#define PLATFORM_HEAP_SYSTEM 1 /* one per core */
-#define PLATFORM_HEAP_SYSTEM_RUNTIME 1 /* one per core */
-#define PLATFORM_HEAP_RUNTIME 1
-#define PLATFORM_HEAP_BUFFER 1
-
-/* Stack configuration */
-#define SOF_STACK_SIZE 0x8000
-#define SOF_STACK_TOTAL_SIZE SOF_STACK_SIZE /*4KB*/
-#define SOF_STACK_BASE (SRAM1_BASE + SRAM1_SIZE)
-#define SOF_STACK_END (SOF_STACK_BASE - SOF_STACK_TOTAL_SIZE)
-
-/* Vector and literal sizes - not in core-isa.h */
-#define SOF_MEM_VECT_LIT_SIZE 0x4
-#define SOF_MEM_VECT_TEXT_SIZE 0x1c
-#define SOF_MEM_VECT_SIZE (SOF_MEM_VECT_TEXT_SIZE + SOF_MEM_VECT_LIT_SIZE)
-
-#define SOF_MEM_RESET_TEXT_SIZE 0x2e0
-#define SOF_MEM_RESET_LIT_SIZE 0x120
-#define SOF_MEM_VECBASE_LIT_SIZE 0x178
-
-#define SOF_MEM_RO_SIZE 0x8
-
-#define HEAP_BUF_ALIGNMENT DCACHE_LINE_SIZE
-
-/** \brief EDF task's default stack size in bytes. */
-#ifdef CONFIG_COMP_GOOGLE_RTC_AUDIO_PROCESSING
-#define PLATFORM_TASK_DEFAULT_STACK_SIZE (12 * 1024)
-#else
-#define PLATFORM_TASK_DEFAULT_STACK_SIZE 3072
-#endif
-
-#if !defined(__ASSEMBLER__) && !defined(LINKER)
-
-struct sof;
-
-void platform_init_memmap(struct sof *sof);
-
-#define uncache_to_cache(address) address
-#define cache_to_uncache(address) address
-#define cache_to_uncache_init(address) address
-#define is_uncached(address) 0
-
-/**
- * \brief Function for keeping shared data synchronized.
- * It's used after usage of data shared by different cores.
- * Such data is dynamically allocated with SOF_MEM_FLAG_SHARED
- * flag. Does nothing, since mt8195 doesn't support SMP.
- */
-
-static inline void *platform_rfree_prepare(void *ptr)
-{
-	return ptr;
-}
-
-#endif
-
-#define host_to_local(addr) (addr)
-#define local_to_host(addr) (addr)
-
-#endif /* __PLATFORM_LIB_MEMORY_H__ */
-
-#else
-
-#error "This file shouldn't be included from outside of sof/lib/memory.h"
-
-#endif /* __SOF_LIB_MEMORY_H__ */
diff --git a/src/platform/mt8365/include/platform/lib/pm_runtime.h b/src/platform/mt8365/include/platform/lib/pm_runtime.h
deleted file mode 100644
index e93410938f30..000000000000
--- a/src/platform/mt8365/include/platform/lib/pm_runtime.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2024 MediaTek. All rights reserved.
- *
- * Author: Andrew Perepech <andrew.perepech@mediatek.com>
- */
-
-#ifdef __SOF_LIB_PM_RUNTIME_H__
-
-#ifndef __PLATFORM_LIB_PM_RUNTIME_H__
-#define __PLATFORM_LIB_PM_RUNTIME_H__
-
-#include <stdint.h>
-
-struct pm_runtime_data;
-
-/**
- * \brief Initializes platform specific runtime power management.
- * \param[in,out] prd Runtime power management data.
- */
-static inline void platform_pm_runtime_init(struct pm_runtime_data *prd)
-{
-}
-
-/**
- * \brief Retrieves platform specific power management resource.
- *
- * \param[in] context Type of power management context.
- * \param[in] index Index of the device.
- * \param[in] flags Flags, set of RPM_...
- */
-static inline void platform_pm_runtime_get(uint32_t context, uint32_t index, uint32_t flags)
-{
-}
-
-/**
- * \brief Releases platform specific power management resource.
- *
- * \param[in] context Type of power management context.
- * \param[in] index Index of the device.
- * \param[in] flags Flags, set of RPM_...
- */
-static inline void platform_pm_runtime_put(uint32_t context, uint32_t index, uint32_t flags)
-{
-}
-
-static inline void platform_pm_runtime_enable(uint32_t context, uint32_t index)
-{
-}
-
-static inline void platform_pm_runtime_disable(uint32_t context, uint32_t index)
-{
-}
-
-static inline bool platform_pm_runtime_is_active(uint32_t context, uint32_t index)
-{
-	return false;
-}
-
-#endif /* __PLATFORM_LIB_PM_RUNTIME_H__ */
-
-#else
-
-#error "This file shouldn't be included from outside of sof/lib/pm_runtime.h"
-
-#endif /* __SOF_LIB_PM_RUNTIME_H__ */
diff --git a/src/platform/mt8365/include/platform/mt8365-afe-common.h b/src/platform/mt8365/include/platform/mt8365-afe-common.h
deleted file mode 100644
index f597f6980da2..000000000000
--- a/src/platform/mt8365/include/platform/mt8365-afe-common.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2024 MediaTek. All rights reserved.
- *
- * Author: Andrew Perepech <andrew.perepech@mediatek.com>
- */
-
-#ifndef _MT_8365_AFE_COMMON_H_
-#define _MT_8365_AFE_COMMON_H_
-
-/* AFE: the abbreviation for Audio Front End  */
-
-enum {
-	MT8365_MEMIF_START,
-	MT8365_MEMIF_DL_START = MT8365_MEMIF_START,
-	MT8365_MEMIF_DL1 = MT8365_MEMIF_DL_START,
-	MT8365_MEMIF_DL2,
-	MT8365_MEMIF_TDM_OUT,
-	MT8365_MEMIF_DL_END,
-	MT8365_MEMIF_UL_START = MT8365_MEMIF_DL_END,
-	MT8365_MEMIF_AWB = MT8365_MEMIF_UL_START,
-	MT8365_MEMIF_VUL,
-	MT8365_MEMIF_VUL2,
-	MT8365_MEMIF_VUL3,
-	MT8365_MEMIF_TDM_IN,
-	MT8365_MEMIF_UL_END,
-	MT8365_MEMIF_END = MT8365_MEMIF_UL_END,
-	MT8365_MEMIF_DL_NUM = (MT8365_MEMIF_DL_END - MT8365_MEMIF_DL_START),
-	MT8365_MEMIF_UL_NUM = (MT8365_MEMIF_UL_END - MT8365_MEMIF_UL_START),
-	MT8365_MEMIF_NUM = (MT8365_MEMIF_END - MT8365_MEMIF_START),
-};
-
-enum {
-	MT8365_AFE_IRQ_1,
-	MT8365_AFE_IRQ_2,
-	MT8365_AFE_IRQ_3,
-	MT8365_AFE_IRQ_4,
-	MT8365_AFE_IRQ_5,
-	MT8365_AFE_IRQ_6,
-	MT8365_AFE_IRQ_7,
-	MT8365_AFE_IRQ_8,
-	MT8365_AFE_IRQ_9,
-	MT8365_AFE_IRQ_10,
-	MT8365_AFE_IRQ_NUM,
-};
-
-enum {
-	MT8365_AFE_IO_INT_ADDA_OUT,
-	MT8365_AFE_IO_2ND_I2S,
-	MT8365_AFE_IO_INT_ADDA_IN,
-	MT8365_AFE_IO_DMIC,
-	MT8365_DAI_NUM,
-};
-
-#endif /* _MT_8365_AFE_COMMON_H_ */
diff --git a/src/platform/mt8365/include/platform/mt8365-afe-regs.h b/src/platform/mt8365/include/platform/mt8365-afe-regs.h
deleted file mode 100644
index 8bd7163434dc..000000000000
--- a/src/platform/mt8365/include/platform/mt8365-afe-regs.h
+++ /dev/null
@@ -1,1207 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2024 MediaTek. All rights reserved.
- *
- * Author: Andrew Perepech <andrew.perepech@mediatek.com>
- */
-
-#ifndef _MT8365_AFE_REGS_H_
-#define _MT8365_AFE_REGS_H_
-
-#define AFE_REG_BASE        0x11220000
-#define AFE_REG_SIZE        0x1000
-#define AFE_SRAM_BASE       0x11221000
-#define AFE_SRAM_SIZE       0xA000
-
-/*****************************************************************************
- *                  R E G I S T E R       D E F I N I T I O N
- *****************************************************************************/
-#define AUDIO_TOP_CON0    (0x0000)
-#define AUDIO_TOP_CON1    (0x0004)
-#define AUDIO_TOP_CON2    (0x0008)
-#define AUDIO_TOP_CON3    (0x000c)
-
-#define AFE_DAC_CON0                     (0x0010)
-#define AFE_DAC_CON1                     (0x0014)
-#define AFE_I2S_CON                      (0x0018)
-#define AFE_CONN0                        (0x0020)
-#define AFE_CONN1                        (0x0024)
-#define AFE_CONN2                        (0x0028)
-#define AFE_CONN3                        (0x002c)
-#define AFE_CONN4                        (0x0030)
-#define AFE_I2S_CON1                     (0x0034)
-#define AFE_I2S_CON2                     (0x0038)
-#define AFE_MRGIF_CON                    (0x003c)
-#define AFE_DL1_BASE                     (0x0040)
-#define AFE_DL1_CUR                      (0x0044)
-#define AFE_DL1_END                      (0x0048)
-#define AFE_I2S_CON3                     (0x004c)
-#define AFE_DL2_BASE                     (0x0050)
-#define AFE_DL2_CUR                      (0x0054)
-#define AFE_DL2_END                      (0x0058)
-#define AFE_CONN5                        (0x005c)
-#define AFE_AWB_BASE                     (0x0070)
-#define AFE_AWB_END                      (0x0078)
-#define AFE_AWB_CUR                      (0x007c)
-#define AFE_VUL_BASE                     (0x0080)
-#define AFE_VUL_END                      (0x0088)
-#define AFE_VUL_CUR                      (0x008c)
-#define AFE_CONN6                        (0x00bc)
-#define AFE_MEMIF_MSB                    (0x00cc)
-#define AFE_MEMIF_MON0                   (0x00d0)
-#define AFE_MEMIF_MON1                   (0x00d4)
-#define AFE_MEMIF_MON2                   (0x00d8)
-#define AFE_MEMIF_MON3                   (0x00dc)
-#define AFE_MEMIF_MON4                   (0x00e0)
-#define AFE_MEMIF_MON5                   (0x00e4)
-#define AFE_MEMIF_MON6                   (0x00e8)
-#define AFE_MEMIF_MON7                   (0x00ec)
-#define AFE_MEMIF_MON8                   (0x00f0)
-#define AFE_MEMIF_MON9                   (0x00f4)
-#define AFE_MEMIF_MON10                  (0x00f8)
-#define AFE_MEMIF_MON11                  (0x00fc)
-#define AFE_ADDA_DL_SRC2_CON0            (0x0108)
-#define AFE_ADDA_DL_SRC2_CON1            (0x010c)
-#define AFE_ADDA_UL_SRC_CON0             (0x0114)
-#define AFE_ADDA_UL_SRC_CON1             (0x0118)
-#define AFE_ADDA_TOP_CON0                (0x0120)
-#define AFE_ADDA_UL_DL_CON0              (0x0124)
-#define AFE_ADDA_SRC_DEBUG               (0x012c)
-#define AFE_ADDA_SRC_DEBUG_MON0          (0x0130)
-#define AFE_ADDA_SRC_DEBUG_MON1          (0x0134)
-#define AFE_ADDA_UL_SRC_MON0             (0x0148)
-#define AFE_ADDA_UL_SRC_MON1             (0x014c)
-#define AFE_SRAM_BOUND                   (0x0170)
-#define AFE_SECURE_CON                   (0x0174)
-#define AFE_SECURE_CONN0                 (0x0178)
-#define AFE_SIDETONE_DEBUG               (0x01d0)
-#define AFE_SIDETONE_MON                 (0x01d4)
-#define AFE_SIDETONE_CON0                (0x01e0)
-#define AFE_SIDETONE_COEFF               (0x01e4)
-#define AFE_SIDETONE_CON1                (0x01e8)
-#define AFE_SIDETONE_GAIN                (0x01ec)
-#define AFE_SGEN_CON0                    (0x01f0)
-#define AFE_SINEGEN_CON_TDM              (0x01f8)
-#define AFE_SINEGEN_CON_TDM_IN           (0x01fc)
-#define AFE_TOP_CON0                     (0x0200)
-#define AFE_BUS_CFG                      (0x0240)
-#define AFE_BUS_MON0                     (0x0244)
-#define AFE_ADDA_PREDIS_CON0             (0x0260)
-#define AFE_ADDA_PREDIS_CON1             (0x0264)
-#define AFE_CONN_MON0                    (0x0280)
-#define AFE_CONN_MON1                    (0x0284)
-#define AFE_CONN_MON2                    (0x0288)
-#define AFE_CONN_MON3                    (0x028c)
-#define AFE_ADDA_IIR_COEF_02_01          (0x0290)
-#define AFE_ADDA_IIR_COEF_04_03          (0x0294)
-#define AFE_ADDA_IIR_COEF_06_05          (0x0298)
-#define AFE_ADDA_IIR_COEF_08_07          (0x029c)
-#define AFE_ADDA_IIR_COEF_10_09          (0x02a0)
-#define AFE_VUL_D2_BASE                  (0x0350)
-#define AFE_VUL_D2_END                   (0x0358)
-#define AFE_VUL_D2_CUR                   (0x035c)
-#define AFE_HDMI_OUT_CON0                (0x0370)
-#define AFE_HDMI_OUT_BASE                (0x0374)
-#define AFE_HDMI_OUT_CUR                 (0x0378)
-#define AFE_HDMI_OUT_END                 (0x037c)
-#define AFE_SPDIF_OUT_CON0               (0x0380)
-#define AFE_SPDIF_OUT_BASE               (0x0384)
-#define AFE_SPDIF_OUT_CUR                (0x0388)
-#define AFE_SPDIF_OUT_END                (0x038c)
-#define AFE_HDMI_CONN0                   (0x0390)
-#define AFE_HDMI_CONN1                   (0x0398)
-#define AFE_CONN_TDMIN_CON               (0x039c)
-#define AFE_IRQ_MCU_CON                  (0x03a0)
-#define AFE_IRQ_MCU_STATUS               (0x03a4)
-#define AFE_IRQ_MCU_CLR                  (0x03a8)
-#define AFE_IRQ_MCU_CNT1                 (0x03ac)
-#define AFE_IRQ_MCU_CNT2                 (0x03b0)
-#define AFE_IRQ_MCU_EN                   (0x03b4)
-#define AFE_IRQ_MCU_MON2                 (0x03b8)
-#define AFE_IRQ_MCU_CNT5                 (0x03bc)
-#define AFE_IRQ1_MCU_CNT_MON             (0x03c0)
-#define AFE_IRQ2_MCU_CNT_MON             (0x03c4)
-#define AFE_IRQ1_MCU_EN_CNT_MON          (0x03c8)
-#define AFE_IRQ5_MCU_CNT_MON             (0x03cc)
-#define AFE_MEMIF_MINLEN                 (0x03d0)
-#define AFE_MEMIF_MAXLEN                 (0x03d4)
-#define AFE_MEMIF_PBUF_SIZE              (0x03d8)
-#define AFE_IRQ_MCU_CNT7                 (0x03dc)
-#define AFE_IRQ7_MCU_CNT_MON             (0x03e0)
-#define AFE_MEMIF_PBUF2_SIZE             (0x03ec)
-#define AFE_APLL_TUNER_CFG               (0x03f0)
-#define AFE_APLL_TUNER_CFG1              (0x03f4)
-#define AFE_IRQ_MCU_CON2                 (0x03f8)
-#define IRQ13_MCU_CNT                    (0x0408)
-#define IRQ13_MCU_CNT_MON                (0x040c)
-#define AFE_GAIN1_CON0                   (0x0410)
-#define AFE_GAIN1_CON1                   (0x0414)
-#define AFE_GAIN1_CON2                   (0x0418)
-#define AFE_GAIN1_CON3                   (0x041c)
-#define AFE_GAIN2_CON0                   (0x0428)
-#define AFE_GAIN2_CON1                   (0x042c)
-#define AFE_GAIN2_CON2                   (0x0430)
-#define AFE_GAIN2_CON3                   (0x0434)
-#define AFE_GAIN2_CUR                    (0x043c)
-#define AFE_CONN11                       (0x0448)
-#define AFE_CONN12                       (0x044c)
-#define AFE_CONN13                       (0x0450)
-#define AFE_CONN14                       (0x0454)
-#define AFE_CONN15                       (0x0458)
-#define AFE_CONN16                       (0x045c)
-#define AFE_CONN7                        (0x0460)
-#define AFE_CONN8                        (0x0464)
-#define AFE_CONN9                        (0x0468)
-#define AFE_CONN10                       (0x046c)
-#define AFE_CONN21                       (0x0470)
-#define AFE_CONN22                       (0x0474)
-#define AFE_CONN23                       (0x0478)
-#define AFE_CONN24                       (0x047c)
-#define AFE_IEC_CFG                      (0x0480)
-#define AFE_IEC_NSNUM                    (0x0484)
-#define AFE_IEC_BURST_INFO               (0x0488)
-#define AFE_IEC_BURST_LEN                (0x048c)
-#define AFE_IEC_NSADR                    (0x0490)
-#define AFE_CONN_RS                      (0x0494)
-#define AFE_CONN_DI                      (0x0498)
-#define AFE_IEC_CHL_STAT0                (0x04a0)
-#define AFE_IEC_CHL_STAT1                (0x04a4)
-#define AFE_IEC_CHR_STAT0                (0x04a8)
-#define AFE_IEC_CHR_STAT1                (0x04ac)
-#define AFE_CONN25                       (0x04b0)
-#define AFE_CONN26                       (0x04b4)
-#define FPGA_CFG2                        (0x04b8)
-#define FPGA_CFG3                        (0x04bc)
-#define FPGA_CFG0                        (0x04c0)
-#define FPGA_CFG1                        (0x04c4)
-#define AFE_SRAM_DELSEL_CON0             (0x04f0)
-#define AFE_SRAM_DELSEL_CON1             (0x04f4)
-#define AFE_SRAM_DELSEL_CON2             (0x04f8)
-#define FPGA_CFG4                        (0x04fc)
-#define AFE_TDM_GASRC4_ASRC_2CH_CON0     (0x0500)
-#define AFE_TDM_GASRC4_ASRC_2CH_CON1     (0x0504)
-#define AFE_TDM_GASRC4_ASRC_2CH_CON2     (0x0508)
-#define AFE_TDM_GASRC4_ASRC_2CH_CON3     (0x050c)
-#define AFE_TDM_GASRC4_ASRC_2CH_CON4     (0x0510)
-#define AFE_TDM_GASRC4_ASRC_2CH_CON5     (0x0514)
-#define AFE_TDM_GASRC4_ASRC_2CH_CON6     (0x0518)
-#define AFE_TDM_GASRC4_ASRC_2CH_CON7     (0x051c)
-#define AFE_TDM_GASRC4_ASRC_2CH_CON8     (0x0520)
-#define AFE_TDM_GASRC4_ASRC_2CH_CON9     (0x0524)
-#define AFE_TDM_GASRC4_ASRC_2CH_CON10    (0x0528)
-#define AFE_TDM_GASRC4_ASRC_2CH_CON12    (0x0530)
-#define AFE_TDM_GASRC4_ASRC_2CH_CON13    (0x0534)
-#define PCM_INTF_CON2                    (0x0538)
-#define PCM2_INTF_CON                    (0x053c)
-#define AFE_APB_MON                      (0x0540)
-#define AFE_CONN34                       (0x0544)
-#define AFE_TDM_CON1                     (0x0548)
-#define AFE_TDM_CON2                     (0x054c)
-#define PCM_INTF_CON1                    (0x0550)
-#define AFE_SECURE_MASK_CONN47_1         (0x0554)
-#define AFE_SECURE_MASK_CONN48_1         (0x0558)
-#define AFE_SECURE_MASK_CONN49_1         (0x055c)
-#define AFE_SECURE_MASK_CONN50_1         (0x0560)
-#define AFE_SECURE_MASK_CONN51_1         (0x0564)
-#define AFE_SECURE_MASK_CONN52_1         (0x0568)
-#define AFE_SECURE_MASK_CONN53_1         (0x056c)
-#define AFE_SE_SECURE_CON                (0x0570)
-#define AFE_TDM_IN_CON1                  (0x0588)
-#define AFE_TDM_IN_CON2                  (0x058c)
-#define AFE_TDM_IN_MON1                  (0x0590)
-#define AFE_TDM_IN_MON2                  (0x0594)
-#define AFE_TDM_IN_MON3                  (0x0598)
-#define AFE_DMIC0_UL_SRC_CON0            (0x05b4)
-#define AFE_DMIC0_UL_SRC_CON1            (0x05b8)
-#define AFE_DMIC0_SRC_DEBUG              (0x05bc)
-#define AFE_DMIC0_SRC_DEBUG_MON0         (0x05c0)
-#define AFE_DMIC0_UL_SRC_MON0            (0x05c8)
-#define AFE_DMIC0_UL_SRC_MON1            (0x05cc)
-#define AFE_DMIC0_IIR_COEF_02_01         (0x05d0)
-#define AFE_DMIC0_IIR_COEF_04_03         (0x05d4)
-#define AFE_DMIC0_IIR_COEF_06_05         (0x05d8)
-#define AFE_DMIC0_IIR_COEF_08_07         (0x05dc)
-#define AFE_DMIC0_IIR_COEF_10_09         (0x05e0)
-#define AFE_DMIC1_UL_SRC_CON0            (0x0620)
-#define AFE_DMIC1_UL_SRC_CON1            (0x0624)
-#define AFE_DMIC1_SRC_DEBUG              (0x0628)
-#define AFE_DMIC1_SRC_DEBUG_MON0         (0x062c)
-#define AFE_DMIC1_UL_SRC_MON0            (0x0634)
-#define AFE_DMIC1_UL_SRC_MON1            (0x0638)
-#define AFE_DMIC1_IIR_COEF_02_01         (0x063c)
-#define AFE_DMIC1_IIR_COEF_04_03         (0x0640)
-#define AFE_DMIC1_IIR_COEF_06_05         (0x0644)
-#define AFE_DMIC1_IIR_COEF_08_07         (0x0648)
-#define AFE_DMIC1_IIR_COEF_10_09         (0x064c)
-#define AFE_SECURE_MASK_CONN39_1         (0x068c)
-#define AFE_SECURE_MASK_CONN40_1         (0x0690)
-#define AFE_SECURE_MASK_CONN41_1         (0x0694)
-#define AFE_SECURE_MASK_CONN42_1         (0x0698)
-#define AFE_SECURE_MASK_CONN43_1         (0x069c)
-#define AFE_SECURE_MASK_CONN44_1         (0x06a0)
-#define AFE_SECURE_MASK_CONN45_1         (0x06a4)
-#define AFE_SECURE_MASK_CONN46_1         (0x06a8)
-#define AFE_TDM_GASRC1_ASRC_2CH_CON0     (0x06c0)
-#define AFE_TDM_GASRC1_ASRC_2CH_CON1     (0x06c4)
-#define AFE_TDM_GASRC1_ASRC_2CH_CON2     (0x06c8)
-#define AFE_TDM_GASRC1_ASRC_2CH_CON3     (0x06cc)
-#define AFE_TDM_GASRC1_ASRC_2CH_CON4     (0x06d0)
-#define AFE_TDM_GASRC1_ASRC_2CH_CON5     (0x06d4)
-#define AFE_TDM_GASRC1_ASRC_2CH_CON6     (0x06d8)
-#define AFE_TDM_GASRC1_ASRC_2CH_CON7     (0x06dc)
-#define AFE_TDM_GASRC1_ASRC_2CH_CON8     (0x06e0)
-#define AFE_TDM_GASRC1_ASRC_2CH_CON9     (0x06e4)
-#define AFE_TDM_GASRC1_ASRC_2CH_CON10    (0x06e8)
-#define AFE_TDM_GASRC1_ASRC_2CH_CON12    (0x06f0)
-#define AFE_TDM_GASRC1_ASRC_2CH_CON13    (0x06f4)
-#define AFE_TDM_ASRC_CON0                (0x06f8)
-#define AFE_TDM_GASRC2_ASRC_2CH_CON0     (0x0700)
-#define AFE_TDM_GASRC2_ASRC_2CH_CON1     (0x0704)
-#define AFE_TDM_GASRC2_ASRC_2CH_CON2     (0x0708)
-#define AFE_TDM_GASRC2_ASRC_2CH_CON3     (0x070c)
-#define AFE_TDM_GASRC2_ASRC_2CH_CON4     (0x0710)
-#define AFE_TDM_GASRC2_ASRC_2CH_CON5     (0x0714)
-#define AFE_TDM_GASRC2_ASRC_2CH_CON6     (0x0718)
-#define AFE_TDM_GASRC2_ASRC_2CH_CON7     (0x071c)
-#define AFE_TDM_GASRC2_ASRC_2CH_CON8     (0x0720)
-#define AFE_TDM_GASRC2_ASRC_2CH_CON9     (0x0724)
-#define AFE_TDM_GASRC2_ASRC_2CH_CON10    (0x0728)
-#define AFE_TDM_GASRC2_ASRC_2CH_CON12    (0x0730)
-#define AFE_TDM_GASRC2_ASRC_2CH_CON13    (0x0734)
-#define AFE_TDM_GASRC3_ASRC_2CH_CON0     (0x0740)
-#define AFE_TDM_GASRC3_ASRC_2CH_CON1     (0x0744)
-#define AFE_TDM_GASRC3_ASRC_2CH_CON2     (0x0748)
-#define AFE_TDM_GASRC3_ASRC_2CH_CON3     (0x074c)
-#define AFE_TDM_GASRC3_ASRC_2CH_CON4     (0x0750)
-#define AFE_TDM_GASRC3_ASRC_2CH_CON5     (0x0754)
-#define AFE_TDM_GASRC3_ASRC_2CH_CON6     (0x0758)
-#define AFE_TDM_GASRC3_ASRC_2CH_CON7     (0x075c)
-#define AFE_TDM_GASRC3_ASRC_2CH_CON8     (0x0760)
-#define AFE_TDM_GASRC3_ASRC_2CH_CON9     (0x0764)
-#define AFE_TDM_GASRC3_ASRC_2CH_CON10    (0x0768)
-#define AFE_TDM_GASRC3_ASRC_2CH_CON12    (0x0770)
-#define AFE_TDM_GASRC3_ASRC_2CH_CON13    (0x0774)
-#define AFE_DMIC2_UL_SRC_CON0            (0x0780)
-#define AFE_DMIC2_UL_SRC_CON1            (0x0784)
-#define AFE_DMIC2_SRC_DEBUG              (0x0788)
-#define AFE_DMIC2_SRC_DEBUG_MON0         (0x078c)
-#define AFE_DMIC2_UL_SRC_MON0            (0x0794)
-#define AFE_DMIC2_UL_SRC_MON1            (0x0798)
-#define AFE_DMIC2_IIR_COEF_02_01         (0x079c)
-#define AFE_DMIC2_IIR_COEF_04_03         (0x07a0)
-#define AFE_DMIC2_IIR_COEF_06_05         (0x07a4)
-#define AFE_DMIC2_IIR_COEF_08_07         (0x07a8)
-#define AFE_DMIC2_IIR_COEF_10_09         (0x07ac)
-#define AFE_DMIC3_UL_SRC_CON0            (0x07ec)
-#define AFE_DMIC3_UL_SRC_CON1            (0x07f0)
-#define AFE_DMIC3_SRC_DEBUG              (0x07f4)
-#define AFE_DMIC3_SRC_DEBUG_MON0         (0x07f8)
-#define AFE_DMIC3_UL_SRC_MON0            (0x0800)
-#define AFE_DMIC3_UL_SRC_MON1            (0x0804)
-#define AFE_DMIC3_IIR_COEF_02_01         (0x0808)
-#define AFE_DMIC3_IIR_COEF_04_03         (0x080c)
-#define AFE_DMIC3_IIR_COEF_06_05         (0x0810)
-#define AFE_DMIC3_IIR_COEF_08_07         (0x0814)
-#define AFE_DMIC3_IIR_COEF_10_09         (0x0818)
-#define AFE_SECURE_MASK_CONN25_1         (0x0858)
-#define AFE_SECURE_MASK_CONN26_1         (0x085c)
-#define AFE_SECURE_MASK_CONN27_1         (0x0860)
-#define AFE_SECURE_MASK_CONN28_1         (0x0864)
-#define AFE_SECURE_MASK_CONN29_1         (0x0868)
-#define AFE_SECURE_MASK_CONN30_1         (0x086c)
-#define AFE_SECURE_MASK_CONN31_1         (0x0870)
-#define AFE_SECURE_MASK_CONN32_1         (0x0874)
-#define AFE_SECURE_MASK_CONN33_1         (0x0878)
-#define AFE_SECURE_MASK_CONN34_1         (0x087c)
-#define AFE_SECURE_MASK_CONN35_1         (0x0880)
-#define AFE_SECURE_MASK_CONN36_1         (0x0884)
-#define AFE_SECURE_MASK_CONN37_1         (0x0888)
-#define AFE_SECURE_MASK_CONN38_1         (0x088c)
-#define AFE_IRQ_MCU_SCP_EN               (0x0890)
-#define AFE_IRQ_MCU_DSP_EN               (0x0894)
-#define AFE_IRQ3_MCU_CNT_MON             (0x0898)
-#define AFE_IRQ4_MCU_CNT_MON             (0x089c)
-#define AFE_IRQ8_MCU_CNT_MON             (0x08a0)
-#define AFE_IRQ_MCU_CNT3                 (0x08a4)
-#define AFE_IRQ_MCU_CNT4                 (0x08a8)
-#define AFE_IRQ_MCU_CNT8                 (0x08ac)
-#define AFE_IRQ_MCU_CNT11                (0x08b0)
-#define AFE_IRQ_MCU_CNT12                (0x08b4)
-#define AFE_IRQ11_MCU_CNT_MON            (0x08b8)
-#define AFE_IRQ12_MCU_CNT_MON            (0x08bc)
-#define AFE_VUL3_BASE                    (0x08c0)
-#define AFE_VUL3_CUR                     (0x08c4)
-#define AFE_VUL3_END                     (0x08c8)
-#define AFE_VUL3_BASE_MSB                (0x08d0)
-#define AFE_VUL3_END_MSB                 (0x08d4)
-#define AFE_IRQ10_MCU_CNT_MON            (0x08d8)
-#define AFE_IRQ_MCU_CNT10                (0x08dc)
-#define AFE_IRQ_ACC1_CNT                 (0x08e0)
-#define AFE_IRQ_ACC2_CNT                 (0x08e4)
-#define AFE_IRQ_ACC1_CNT_MON1            (0x08e8)
-#define AFE_IRQ_ACC2_CNT_MON             (0x08ec)
-#define AFE_TSF_CON                      (0x08f0)
-#define AFE_TSF_MON                      (0x08f4)
-#define AFE_IRQ_ACC1_CNT_MON2            (0x08f8)
-#define AFE_SPDIFIN_CFG0                 (0x0900)
-#define AFE_SPDIFIN_CFG1                 (0x0904)
-#define AFE_SPDIFIN_CHSTS1               (0x0908)
-#define AFE_SPDIFIN_CHSTS2               (0x090c)
-#define AFE_SPDIFIN_CHSTS3               (0x0910)
-#define AFE_SPDIFIN_CHSTS4               (0x0914)
-#define AFE_SPDIFIN_CHSTS5               (0x0918)
-#define AFE_SPDIFIN_CHSTS6               (0x091c)
-#define AFE_SPDIFIN_DEBUG1               (0x0920)
-#define AFE_SPDIFIN_DEBUG2               (0x0924)
-#define AFE_SPDIFIN_DEBUG3               (0x0928)
-#define AFE_SPDIFIN_DEBUG4               (0x092c)
-#define AFE_SPDIFIN_EC                   (0x0930)
-#define AFE_SPDIFIN_CKLOCK_CFG           (0x0934)
-#define AFE_SPDIFIN_BR                   (0x093c)
-#define AFE_SPDIFIN_BR_DBG1              (0x0940)
-#define AFE_SPDIFIN_INT_EXT              (0x0948)
-#define AFE_SPDIFIN_INT_EXT2             (0x094c)
-#define SPDIFIN_FREQ_INFO                (0x0950)
-#define SPDIFIN_FREQ_INFO_2              (0x0954)
-#define SPDIFIN_FREQ_INFO_3              (0x0958)
-#define SPDIFIN_FREQ_STATUS              (0x095c)
-#define SPDIFIN_USERCODE1                (0x0960)
-#define SPDIFIN_USERCODE2                (0x0964)
-#define SPDIFIN_USERCODE3                (0x0968)
-#define SPDIFIN_USERCODE4                (0x096c)
-#define SPDIFIN_USERCODE5                (0x0970)
-#define SPDIFIN_USERCODE6                (0x0974)
-#define SPDIFIN_USERCODE7                (0x0978)
-#define SPDIFIN_USERCODE8                (0x097c)
-#define SPDIFIN_USERCODE9                (0x0980)
-#define SPDIFIN_USERCODE10               (0x0984)
-#define SPDIFIN_USERCODE11               (0x0988)
-#define SPDIFIN_USERCODE12               (0x098c)
-#define SPDIFIN_MEMIF_CON0               (0x0990)
-#define SPDIFIN_BASE_ADR                 (0x0994)
-#define SPDIFIN_END_ADR                  (0x0998)
-#define SPDIFIN_APLL_TUNER_CFG           (0x09a0)
-#define SPDIFIN_APLL_TUNER_CFG1          (0x09a4)
-#define SPDIFIN_APLL2_TUNER_CFG          (0x09a8)
-#define SPDIFIN_APLL2_TUNER_CFG1         (0x09ac)
-#define SPDIFIN_TYPE_DET                 (0x09b0)
-#define MPHONE_MULTI_CON0                (0x09b4)
-#define SPDIFIN_CUR_ADR                  (0x09b8)
-#define AFE_SINEGEN_CON_SPDIFIN          (0x09bc)
-#define AFE_HDMI_IN_2CH_CON0             (0x09c0)
-#define AFE_HDMI_IN_2CH_BASE             (0x09c4)
-#define AFE_HDMI_IN_2CH_END              (0x09c8)
-#define AFE_HDMI_IN_2CH_CUR              (0x09cc)
-#define AFE_MEMIF_BUF_MON0               (0x09d0)
-#define AFE_MEMIF_BUF_MON1               (0x09d4)
-#define AFE_MEMIF_BUF_MON2               (0x09d8)
-#define AFE_MEMIF_BUF_MON3               (0x09dc)
-#define AFE_MEMIF_BUF_MON6               (0x09e8)
-#define AFE_MEMIF_BUF_MON7               (0x09ec)
-#define AFE_MEMIF_BUF_MON8               (0x09f0)
-#define AFE_MEMIF_BUF_MON10              (0x09f8)
-#define AFE_MEMIF_BUF_MON11              (0x09fc)
-#define SYSTOP_STC_CONFIG                (0x0a00)
-#define AUDIO_STC_STATUS                 (0x0a04)
-#define SYSTOP_W_STC_H                   (0x0a08)
-#define SYSTOP_W_STC_L                   (0x0a0c)
-#define SYSTOP_R_STC_H                   (0x0a10)
-#define SYSTOP_R_STC_L                   (0x0a14)
-#define AUDIO_W_STC_H                    (0x0a18)
-#define AUDIO_W_STC_L                    (0x0a1c)
-#define AUDIO_R_STC_H                    (0x0a20)
-#define AUDIO_R_STC_L                    (0x0a24)
-#define SYSTOP_W_STC2_H                  (0x0a28)
-#define SYSTOP_W_STC2_L                  (0x0a2c)
-#define SYSTOP_R_STC2_H                  (0x0a30)
-#define SYSTOP_R_STC2_L                  (0x0a34)
-#define AUDIO_W_STC2_H                   (0x0a38)
-#define AUDIO_W_STC2_L                   (0x0a3c)
-#define AUDIO_R_STC2_H                   (0x0a40)
-#define AUDIO_R_STC2_L                   (0x0a44)
-
-#define AFE_CONN17                       (0x0a48)
-#define AFE_CONN18                       (0x0a4c)
-#define AFE_CONN19                       (0x0a50)
-#define AFE_CONN20                       (0x0a54)
-#define AFE_CONN27                       (0x0a58)
-#define AFE_CONN28                       (0x0a5c)
-#define AFE_CONN29                       (0x0a60)
-#define AFE_CONN30                       (0x0a64)
-#define AFE_CONN31                       (0x0a68)
-#define AFE_CONN32                       (0x0a6c)
-#define AFE_CONN33                       (0x0a70)
-#define AFE_CONN35                       (0x0a74)
-#define AFE_CONN36                       (0x0a78)
-#define AFE_CONN37                       (0x0a7c)
-#define AFE_CONN38                       (0x0a80)
-#define AFE_CONN39                       (0x0a84)
-#define AFE_CONN40                       (0x0a88)
-#define AFE_CONN41                       (0x0a8c)
-#define AFE_CONN42                       (0x0a90)
-#define AFE_CONN44                       (0x0a94)
-#define AFE_CONN45                       (0x0a98)
-#define AFE_CONN46                       (0x0a9c)
-#define AFE_CONN47                       (0x0aa0)
-#define AFE_CONN_24BIT                   (0x0aa4)
-#define AFE_CONN0_1                      (0x0aa8)
-#define AFE_CONN1_1                      (0x0aac)
-#define AFE_CONN2_1                      (0x0ab0)
-#define AFE_CONN3_1                      (0x0ab4)
-#define AFE_CONN4_1                      (0x0ab8)
-#define AFE_CONN5_1                      (0x0abc)
-#define AFE_CONN6_1                      (0x0ac0)
-#define AFE_CONN7_1                      (0x0ac4)
-#define AFE_CONN8_1                      (0x0ac8)
-#define AFE_CONN9_1                      (0x0acc)
-#define AFE_CONN10_1                     (0x0ad0)
-#define AFE_CONN11_1                     (0x0ad4)
-#define AFE_CONN12_1                     (0x0ad8)
-#define AFE_CONN13_1                     (0x0adc)
-#define AFE_CONN14_1                     (0x0ae0)
-#define AFE_CONN15_1                     (0x0ae4)
-#define AFE_CONN16_1                     (0x0ae8)
-#define AFE_CONN17_1                     (0x0aec)
-#define AFE_CONN18_1                     (0x0af0)
-#define AFE_CONN19_1                     (0x0af4)
-#define AFE_CONN43                       (0x0af8)
-#define AFE_CONN43_1                     (0x0afc)
-#define AFE_CONN21_1                     (0x0b00)
-#define AFE_CONN22_1                     (0x0b04)
-#define AFE_CONN23_1                     (0x0b08)
-#define AFE_CONN24_1                     (0x0b0c)
-#define AFE_CONN25_1                     (0x0b10)
-#define AFE_CONN26_1                     (0x0b14)
-#define AFE_CONN27_1                     (0x0b18)
-#define AFE_CONN28_1                     (0x0b1c)
-#define AFE_CONN29_1                     (0x0b20)
-#define AFE_CONN30_1                     (0x0b24)
-#define AFE_CONN31_1                     (0x0b28)
-#define AFE_CONN32_1                     (0x0b2c)
-#define AFE_CONN33_1                     (0x0b30)
-#define AFE_CONN34_1                     (0x0b34)
-#define AFE_CONN35_1                     (0x0b38)
-#define AFE_CONN36_1                     (0x0b3c)
-#define AFE_CONN37_1                     (0x0b40)
-#define AFE_CONN38_1                     (0x0b44)
-#define AFE_CONN39_1                     (0x0b48)
-#define AFE_CONN40_1                     (0x0b4c)
-#define AFE_CONN41_1                     (0x0b50)
-#define AFE_CONN42_1                     (0x0b54)
-#define AFE_CONN44_1                     (0x0b58)
-#define AFE_CONN45_1                     (0x0b5c)
-#define AFE_CONN46_1                     (0x0b60)
-#define AFE_CONN47_1                     (0x0b64)
-#define AFE_CONN_RS_1                    (0x0b68)
-#define AFE_CONN_DI_1                    (0x0b6c)
-#define AFE_CONN_24BIT_1                 (0x0b70)
-#define AFE_GAIN1_CUR                    (0x0b78)
-#define AFE_CONN20_1                     (0x0b7c)
-#define AFE_DL1_BASE_MSB                 (0x0b80)
-#define AFE_DL1_END_MSB                  (0x0b84)
-#define AFE_DL2_BASE_MSB                 (0x0b88)
-#define AFE_DL2_END_MSB                  (0x0b8c)
-#define AFE_AWB_BASE_MSB                 (0x0b90)
-#define AFE_AWB_END_MSB                  (0x0b94)
-#define AFE_VUL_BASE_MSB                 (0x0ba0)
-#define AFE_VUL_END_MSB                  (0x0ba4)
-#define AFE_VUL_D2_BASE_MSB              (0x0ba8)
-#define AFE_VUL_D2_END_MSB               (0x0bac)
-#define AFE_HDMI_OUT_BASE_MSB            (0x0bb8)
-#define AFE_HDMI_OUT_END_MSB             (0x0bbc)
-#define AFE_HDMI_IN_2CH_BASE_MSB         (0x0bc0)
-#define AFE_HDMI_IN_2CH_END_MSB          (0x0bc4)
-#define AFE_SPDIF_OUT_BASE_MSB           (0x0bc8)
-#define AFE_SPDIF_OUT_END_MSB            (0x0bcc)
-#define SPDIFIN_BASE_MSB                 (0x0bd0)
-#define SPDIFIN_END_MSB                  (0x0bd4)
-#define AFE_DL1_CUR_MSB                  (0x0bd8)
-#define AFE_DL2_CUR_MSB                  (0x0bdc)
-#define AFE_AWB_CUR_MSB                  (0x0be8)
-#define AFE_VUL_CUR_MSB                  (0x0bf8)
-#define AFE_VUL_D2_CUR_MSB               (0x0c04)
-#define AFE_HDMI_OUT_CUR_MSB             (0x0c0c)
-#define AFE_HDMI_IN_2CH_CUR_MSB          (0x0c10)
-#define AFE_SPDIF_OUT_CUR_MSB            (0x0c14)
-#define SPDIFIN_CUR_MSB                  (0x0c18)
-#define AFE_CONN_REG                     (0x0c20)
-#define AFE_SECURE_MASK_CONN14_1         (0x0c24)
-#define AFE_SECURE_MASK_CONN15_1         (0x0c28)
-#define AFE_SECURE_MASK_CONN16_1         (0x0c2c)
-#define AFE_SECURE_MASK_CONN17_1         (0x0c30)
-#define AFE_SECURE_MASK_CONN18_1         (0x0c34)
-#define AFE_SECURE_MASK_CONN19_1         (0x0c38)
-#define AFE_SECURE_MASK_CONN20_1         (0x0c3c)
-#define AFE_SECURE_MASK_CONN21_1         (0x0c40)
-#define AFE_SECURE_MASK_CONN22_1         (0x0c44)
-#define AFE_SECURE_MASK_CONN23_1         (0x0c48)
-#define AFE_SECURE_MASK_CONN24_1         (0x0c4c)
-#define AFE_ADDA_DL_SDM_DCCOMP_CON       (0x0c50)
-#define AFE_ADDA_DL_SDM_TEST             (0x0c54)
-#define AFE_ADDA_DL_DC_COMP_CFG0         (0x0c58)
-#define AFE_ADDA_DL_DC_COMP_CFG1         (0x0c5c)
-#define AFE_ADDA_DL_SDM_FIFO_MON         (0x0c60)
-#define AFE_ADDA_DL_SRC_LCH_MON          (0x0c64)
-#define AFE_ADDA_DL_SRC_RCH_MON          (0x0c68)
-#define AFE_ADDA_DL_SDM_OUT_MON          (0x0c6c)
-#define AFE_ADDA_DL_SDM_DITHER_CON       (0x0c70)
-
-#define AFE_VUL3_CUR_MSB                 (0x0c78)
-#define AFE_ASRC_2CH_CON0                (0x0c80)
-#define AFE_ASRC_2CH_CON1                (0x0c84)
-#define AFE_ASRC_2CH_CON2                (0x0c88)
-#define AFE_ASRC_2CH_CON3                (0x0c8c)
-#define AFE_ASRC_2CH_CON4                (0x0c90)
-#define AFE_ASRC_2CH_CON5                (0x0c94)
-#define AFE_ASRC_2CH_CON6                (0x0c98)
-#define AFE_ASRC_2CH_CON7                (0x0c9c)
-#define AFE_ASRC_2CH_CON8                (0x0ca0)
-#define AFE_ASRC_2CH_CON9                (0x0ca4)
-#define AFE_ASRC_2CH_CON10               (0x0ca8)
-#define AFE_ASRC_2CH_CON12               (0x0cb0)
-#define AFE_ASRC_2CH_CON13               (0x0cb4)
-
-#define AFE_PCM_TX_ASRC_2CH_CON0         (0x0cc0)
-#define AFE_PCM_TX_ASRC_2CH_CON1         (0x0cc4)
-#define AFE_PCM_TX_ASRC_2CH_CON2         (0x0cc8)
-#define AFE_PCM_TX_ASRC_2CH_CON3         (0x0ccc)
-#define AFE_PCM_TX_ASRC_2CH_CON4         (0x0cd0)
-#define AFE_PCM_TX_ASRC_2CH_CON5         (0x0cd4)
-#define AFE_PCM_TX_ASRC_2CH_CON6         (0x0cd8)
-#define AFE_PCM_TX_ASRC_2CH_CON7         (0x0cdc)
-#define AFE_PCM_TX_ASRC_2CH_CON8         (0x0ce0)
-#define AFE_PCM_TX_ASRC_2CH_CON9         (0x0ce4)
-#define AFE_PCM_TX_ASRC_2CH_CON10        (0x0ce8)
-#define AFE_PCM_TX_ASRC_2CH_CON12        (0x0cf0)
-#define AFE_PCM_TX_ASRC_2CH_CON13        (0x0cf4)
-#define AFE_PCM_RX_ASRC_2CH_CON0         (0x0d00)
-#define AFE_PCM_RX_ASRC_2CH_CON1         (0x0d04)
-#define AFE_PCM_RX_ASRC_2CH_CON2         (0x0d08)
-#define AFE_PCM_RX_ASRC_2CH_CON3         (0x0d0c)
-#define AFE_PCM_RX_ASRC_2CH_CON4         (0x0d10)
-#define AFE_PCM_RX_ASRC_2CH_CON5         (0x0d14)
-#define AFE_PCM_RX_ASRC_2CH_CON6         (0x0d18)
-#define AFE_PCM_RX_ASRC_2CH_CON7         (0x0d1c)
-#define AFE_PCM_RX_ASRC_2CH_CON8         (0x0d20)
-#define AFE_PCM_RX_ASRC_2CH_CON9         (0x0d24)
-#define AFE_PCM_RX_ASRC_2CH_CON10        (0x0d28)
-#define AFE_PCM_RX_ASRC_2CH_CON12        (0x0d30)
-#define AFE_PCM_RX_ASRC_2CH_CON13        (0x0d34)
-
-#define AFE_ADDA_PREDIS_CON2             (0x0d40)
-#define AFE_ADDA_PREDIS_CON3             (0x0d44)
-#define AFE_SECURE_MASK_CONN4_1          (0x0d48)
-#define AFE_SECURE_MASK_CONN5_1          (0x0d4c)
-#define AFE_SECURE_MASK_CONN6_1          (0x0d50)
-#define AFE_SECURE_MASK_CONN7_1          (0x0d54)
-#define AFE_SECURE_MASK_CONN8_1          (0x0d58)
-#define AFE_SECURE_MASK_CONN9_1          (0x0d5c)
-#define AFE_SECURE_MASK_CONN10_1         (0x0d60)
-#define AFE_SECURE_MASK_CONN11_1         (0x0d64)
-#define AFE_SECURE_MASK_CONN12_1         (0x0d68)
-#define AFE_SECURE_MASK_CONN13_1         (0x0d6c)
-#define AFE_MEMIF_MON12                  (0x0d70)
-#define AFE_MEMIF_MON13                  (0x0d74)
-#define AFE_MEMIF_MON14                  (0x0d78)
-#define AFE_MEMIF_MON15                  (0x0d7c)
-#define AFE_SECURE_MASK_CONN42           (0x0dbc)
-#define AFE_SECURE_MASK_CONN43           (0x0dc0)
-#define AFE_SECURE_MASK_CONN44           (0x0dc4)
-#define AFE_SECURE_MASK_CONN45           (0x0dc8)
-#define AFE_SECURE_MASK_CONN46           (0x0dcc)
-#define AFE_HD_ENGEN_ENABLE              (0x0dd0)
-#define AFE_SECURE_MASK_CONN47           (0x0dd4)
-#define AFE_SECURE_MASK_CONN48           (0x0dd8)
-#define AFE_SECURE_MASK_CONN49           (0x0ddc)
-#define AFE_SECURE_MASK_CONN50           (0x0de0)
-#define AFE_SECURE_MASK_CONN51           (0x0de4)
-#define AFE_SECURE_MASK_CONN52           (0x0de8)
-#define AFE_SECURE_MASK_CONN53           (0x0dec)
-#define AFE_SECURE_MASK_CONN0_1          (0x0df0)
-#define AFE_SECURE_MASK_CONN1_1          (0x0df4)
-#define AFE_SECURE_MASK_CONN2_1          (0x0df8)
-#define AFE_SECURE_MASK_CONN3_1          (0x0dfc)
-
-#define AFE_ADDA_MTKAIF_CFG0             (0x0e00)
-#define AFE_ADDA_MTKAIF_SYNCWORD_CFG     (0x0e14)
-#define AFE_ADDA_MTKAIF_RX_CFG0          (0x0e20)
-#define AFE_ADDA_MTKAIF_RX_CFG1          (0x0e24)
-#define AFE_ADDA_MTKAIF_RX_CFG2          (0x0e28)
-#define AFE_ADDA_MTKAIF_MON0             (0x0e34)
-#define AFE_ADDA_MTKAIF_MON1             (0x0e38)
-#define AFE_AUD_PAD_TOP                  (0x0e40)
-
-#define AFE_CM1_CON4                     (0x0e48)
-#define AFE_CM2_CON4                     (0x0e4c)
-#define AFE_CM1_CON0                     (0x0e50)
-#define AFE_CM1_CON1                     (0x0e54)
-#define AFE_CM1_CON2                     (0x0e58)
-#define AFE_CM1_CON3                     (0x0e5c)
-#define AFE_CM2_CON0                     (0x0e60)
-#define AFE_CM2_CON1                     (0x0e64)
-#define AFE_CM2_CON2                     (0x0e68)
-#define AFE_CM2_CON3                     (0x0e6c)
-#define AFE_CM2_CONN0                    (0x0e70)
-#define AFE_CM2_CONN1                    (0x0e74)
-#define AFE_CM2_CONN2                    (0x0e78)
-
-#define AFE_GENERAL1_ASRC_2CH_CON0       (0x0e80)
-#define AFE_GENERAL1_ASRC_2CH_CON1       (0x0e84)
-#define AFE_GENERAL1_ASRC_2CH_CON2       (0x0e88)
-#define AFE_GENERAL1_ASRC_2CH_CON3       (0x0e8c)
-#define AFE_GENERAL1_ASRC_2CH_CON4       (0x0e90)
-#define AFE_GENERAL1_ASRC_2CH_CON5       (0x0e94)
-#define AFE_GENERAL1_ASRC_2CH_CON6       (0x0e98)
-#define AFE_GENERAL1_ASRC_2CH_CON7       (0x0e9c)
-#define AFE_GENERAL1_ASRC_2CH_CON8       (0x0ea0)
-#define AFE_GENERAL1_ASRC_2CH_CON9       (0x0ea4)
-#define AFE_GENERAL1_ASRC_2CH_CON10      (0x0ea8)
-#define AFE_GENERAL1_ASRC_2CH_CON12      (0x0eb0)
-#define AFE_GENERAL1_ASRC_2CH_CON13      (0x0eb4)
-#define GENERAL_ASRC_MODE                (0x0eb8)
-#define GENERAL_ASRC_EN_ON               (0x0ebc)
-
-#define AFE_CONN48                       (0x0ec0)
-#define AFE_CONN49                       (0x0ec4)
-#define AFE_CONN50                       (0x0ec8)
-#define AFE_CONN51                       (0x0ecc)
-#define AFE_CONN52                       (0x0ed0)
-#define AFE_CONN53                       (0x0ed4)
-#define AFE_CONN48_1                     (0x0ee0)
-#define AFE_CONN49_1                     (0x0ee4)
-#define AFE_CONN50_1                     (0x0ee8)
-#define AFE_CONN51_1                     (0x0eec)
-#define AFE_CONN52_1                     (0x0ef0)
-#define AFE_CONN53_1                     (0x0ef4)
-
-#define AFE_GENERAL2_ASRC_2CH_CON0       (0x0f00)
-#define AFE_GENERAL2_ASRC_2CH_CON1       (0x0f04)
-#define AFE_GENERAL2_ASRC_2CH_CON2       (0x0f08)
-#define AFE_GENERAL2_ASRC_2CH_CON3       (0x0f0c)
-#define AFE_GENERAL2_ASRC_2CH_CON4       (0x0f10)
-#define AFE_GENERAL2_ASRC_2CH_CON5       (0x0f14)
-#define AFE_GENERAL2_ASRC_2CH_CON6       (0x0f18)
-#define AFE_GENERAL2_ASRC_2CH_CON7       (0x0f1c)
-#define AFE_GENERAL2_ASRC_2CH_CON8       (0x0f20)
-#define AFE_GENERAL2_ASRC_2CH_CON9       (0x0f24)
-#define AFE_GENERAL2_ASRC_2CH_CON10      (0x0f28)
-#define AFE_GENERAL2_ASRC_2CH_CON12      (0x0f30)
-#define AFE_GENERAL2_ASRC_2CH_CON13      (0x0f34)
-
-#define AFE_SECURE_MASK_CONN28           (0x0f48)
-#define AFE_SECURE_MASK_CONN29           (0x0f4c)
-#define AFE_SECURE_MASK_CONN30           (0x0f50)
-#define AFE_SECURE_MASK_CONN31           (0x0f54)
-#define AFE_SECURE_MASK_CONN32           (0x0f58)
-#define AFE_SECURE_MASK_CONN33           (0x0f5c)
-#define AFE_SECURE_MASK_CONN34           (0x0f60)
-#define AFE_SECURE_MASK_CONN35           (0x0f64)
-#define AFE_SECURE_MASK_CONN36           (0x0f68)
-#define AFE_SECURE_MASK_CONN37           (0x0f6c)
-#define AFE_SECURE_MASK_CONN38           (0x0f70)
-#define AFE_SECURE_MASK_CONN39           (0x0f74)
-#define AFE_SECURE_MASK_CONN40           (0x0f78)
-#define AFE_SECURE_MASK_CONN41           (0x0f7c)
-#define AFE_SIDEBAND0                    (0x0f80)
-#define AFE_SIDEBAND1                    (0x0f84)
-#define AFE_SECURE_SIDEBAND0             (0x0f88)
-#define AFE_SECURE_SIDEBAND1             (0x0f8c)
-#define AFE_SECURE_MASK_CONN0            (0x0f90)
-#define AFE_SECURE_MASK_CONN1            (0x0f94)
-#define AFE_SECURE_MASK_CONN2            (0x0f98)
-#define AFE_SECURE_MASK_CONN3            (0x0f9c)
-#define AFE_SECURE_MASK_CONN4            (0x0fa0)
-#define AFE_SECURE_MASK_CONN5            (0x0fa4)
-#define AFE_SECURE_MASK_CONN6            (0x0fa8)
-#define AFE_SECURE_MASK_CONN7            (0x0fac)
-#define AFE_SECURE_MASK_CONN8            (0x0fb0)
-#define AFE_SECURE_MASK_CONN9            (0x0fb4)
-#define AFE_SECURE_MASK_CONN10           (0x0fb8)
-#define AFE_SECURE_MASK_CONN11           (0x0fbc)
-#define AFE_SECURE_MASK_CONN12           (0x0fc0)
-#define AFE_SECURE_MASK_CONN13           (0x0fc4)
-#define AFE_SECURE_MASK_CONN14           (0x0fc8)
-#define AFE_SECURE_MASK_CONN15           (0x0fcc)
-#define AFE_SECURE_MASK_CONN16           (0x0fd0)
-#define AFE_SECURE_MASK_CONN17           (0x0fd4)
-#define AFE_SECURE_MASK_CONN18           (0x0fd8)
-#define AFE_SECURE_MASK_CONN19           (0x0fdc)
-#define AFE_SECURE_MASK_CONN20           (0x0fe0)
-#define AFE_SECURE_MASK_CONN21           (0x0fe4)
-#define AFE_SECURE_MASK_CONN22           (0x0fe8)
-#define AFE_SECURE_MASK_CONN23           (0x0fec)
-#define AFE_SECURE_MASK_CONN24           (0x0ff0)
-#define AFE_SECURE_MASK_CONN25           (0x0ff4)
-#define AFE_SECURE_MASK_CONN26           (0x0ff8)
-#define AFE_SECURE_MASK_CONN27           (0x0ffc)
-
-#define MAX_REGISTER			AFE_SECURE_MASK_CONN27
-
-#define AFE_IRQ_STATUS_BITS		0x3ff
-
-/* AUDIO_TOP_CON0 (0x0000) */
-#define AUD_TCON0_PDN_TML			BIT(27)
-#define AUD_TCON0_PDN_DAC_PREDIS	BIT(26)
-#define AUD_TCON0_PDN_DAC			BIT(25)
-#define AUD_TCON0_PDN_ADC			BIT(24)
-#define AUD_TCON0_PDN_TDM_IN		BIT(23)
-#define AUD_TCON0_PDN_TDM_OUT		BIT(22)
-#define AUD_TCON0_PDN_SPDIF			BIT(21)
-#define AUD_TCON0_PDN_APLL_TUNER	BIT(19)
-#define AUD_TCON0_PDN_APLL2_TUNER	BIT(18)
-#define AUD_TCON0_PDN_INTDIR		BIT(15)
-#define AUD_TCON0_PDN_24M			BIT(9)
-#define AUD_TCON0_PDN_22M			BIT(8)
-#define AUD_TCON0_PDN_I2S_IN		BIT(6)
-#define AUD_TCON0_PDN_AFE			BIT(2)
-
-/* AUDIO_TOP_CON1 (0x0004) */
-#define AUD_TCON1_PDN_TDM_ASRC			BIT(15)
-#define AUD_TCON1_PDN_GENERAL2_ASRC		BIT(14)
-#define AUD_TCON1_PDN_GENERAL1_ASRC		BIT(13)
-#define AUD_TCON1_PDN_CONNSYS_I2S_ASRC	BIT(12)
-#define AUD_TCON1_PDN_DMIC3_ADC			BIT(11)
-#define AUD_TCON1_PDN_DMIC2_ADC			BIT(10)
-#define AUD_TCON1_PDN_DMIC1_ADC			BIT(9)
-#define AUD_TCON1_PDN_DMIC0_ADC			BIT(8)
-#define AUD_TCON1_PDN_I2S4_BCLK			BIT(7)
-#define AUD_TCON1_PDN_I2S3_BCLK			BIT(6)
-#define AUD_TCON1_PDN_I2S2_BCLK			BIT(5)
-#define AUD_TCON1_PDN_I2S1_BCLK			BIT(4)
-
-/* AUDIO_TOP_CON3 (0x000C) */
-#define AUD_TCON3_HDMI_BCK_INV		BIT(3)
-
-/* AFE_I2S_CON (0x0018) */
-#define AFE_I2S_CON_PHASE_SHIFT_FIX	BIT(31)
-#define AFE_I2S_CON_FROM_IO_MUX		BIT(28)
-#define AFE_I2S_CON_LOW_JITTER_CLK	BIT(12)
-#define AFE_I2S_CON_RATE(x)		(((x) & 0xf) << 8)
-#define AFE_I2S_CON_FORMAT_I2S		BIT(3)
-#define AFE_I2S_CON_SRC_SLAVE		BIT(2)
-
-/* AFE_ASRC_2CH_CON0 */
-#define ONE_HEART_MASK (0x1 << 31)
-#define CHSET_STR_CLR (0x1<<4)
-#define ASM_ON_MASK     (0x1<<0)
-#define ASM_ON     (0x1<<0)
-
-/* CON2 */
-#define O16BIT_MASK     (0x1<<19)
-#define CLR_IIR_HISTORY_MASK (0x1<<17)
-#define CLR_IIR_HISTORY      (0x1<<17)
-#define IS_MONO_MASK    (0x1<<16)
-#define IIR_EN_MASK     (0x1<<11)
-#define IIR_EN          (0x1<<11)
-#define IIR_DIS         (0x0<<11)
-#define IIR_STAGE_MASK  (0x7<<8)
-#define IIR_STAGE_8     (0x7<<8)
-
-/* CON5 */
-#define CALI_CYCLE_MASK (0xFFFF << 16)
-#define CALI_64_CYCLE (0x3F << 16)
-#define CALI_96_CYCLE (0x5F << 16)
-#define CALI_441_CYCLE (0x1B8 << 16)
-
-#define CALI_AUTORST_MASK (0x1 << 15)
-#define CALI_AUTORST_ENABLE (0x1 << 15)
-#define CALI_AUTORST_DISABLE (0x0 << 15)
-
-#define AUTO_TUNE_FREQ5_MASK (0x1 << 12)
-#define AUTO_TUNE_FREQ5_ENABLE (0x1 << 12)
-#define AUTO_TUNE_FREQ5_DISABLE (0x0 << 12)
-
-#define COMP_FREQ_RES_MASK (0x1 << 11)
-#define COMP_FREQ_RES_ENABLE (0x1 << 11)
-
-#define CALI_SEL_MASK (0x3 << 8)
-#define CALI_SEL_00 (0x0 << 8)
-#define CALI_SEL_01 (0x1 << 8)
-
-#define CALI_BP_DGL_MASK (0x1 << 7)
-#define CALI_BP_DGL_BYPASS (0x1 << 7)
-
-#define AUTO_TUNE_FREQ4_MASK (0x1 << 3)
-#define AUTO_TUNE_FREQ4_ENABLE (0x1 << 3)
-#define AUTO_TUNE_FREQ4_DISABLE (0x0 << 3)
-
-#define CALI_AUTO_RESTART_MASK (0x1 << 2)
-#define CALI_AUTO_RESTART_ENABLE (0x1 << 2)
-
-#define CALI_USE_FREQ_OUT_MASK (0x1 << 1)
-#define CALI_USE_FREQ (0x1 << 1)
-#define CALI_USE_PERIOD (0x0 << 1)
-
-#define CALI_ON_MASK (0x1 << 0)
-#define CALI_ON (0x1 << 0)
-#define CALI_OFF (0x0 << 0)
-
-
-#define AFE_I2S_CON_WLEN_32BIT		BIT(1)
-#define AFE_I2S_CON_EN			BIT(0)
-
-#define AFE_CONN3_I03_O03_S		BIT(3)
-#define AFE_CONN4_I04_O04_S		BIT(4)
-#define AFE_CONN4_I03_O04_S		BIT(3)
-
-/* AFE_I2S_CON1 (0x0034) */
-#define AFE_I2S_CON1_I2S2_TO_PAD	(1 << 18)
-#define AFE_I2S_CON1_TDMOUT_TO_PAD	(0 << 18)
-#define AFE_I2S_CON1_TDMOUT_MUX_MASK	GENMASK(18, 18)
-#define AFE_I2S_CON1_LOW_JITTER_CLK	BIT(12)
-#define AFE_I2S_CON1_RATE(x)		(((x) & 0xf) << 8)
-#define AFE_I2S_CON1_FORMAT_I2S		BIT(3)
-#define AFE_I2S_CON1_WLEN_32BIT		BIT(1)
-#define AFE_I2S_CON1_EN			BIT(0)
-
-/* AFE_I2S_CON2 (0x0038) */
-#define AFE_I2S_CON2_LOW_JITTER_CLK	BIT(12)
-#define AFE_I2S_CON2_RATE(x)		(((x) & 0xf) << 8)
-#define AFE_I2S_CON2_FORMAT_I2S		BIT(3)
-#define AFE_I2S_CON2_WLEN_32BIT		BIT(1)
-#define AFE_I2S_CON2_EN			BIT(0)
-
-/* AFE_I2S_CON3 (0x004C) */
-#define AFE_I2S_CON3_LOW_JITTER_CLK	BIT(12)
-#define AFE_I2S_CON3_RATE(x)		(((x) & 0xf) << 8)
-#define AFE_I2S_CON3_FORMAT_I2S		BIT(3)
-#define AFE_I2S_CON3_WLEN_32BIT		BIT(1)
-#define AFE_I2S_CON3_EN			BIT(0)
-
-/* AFE_ADDA_DL_SRC2_CON0 (0x0108) */
-#define AFE_ADDA_DL_8X_UPSAMPLE		(BIT(25) | BIT(24))
-#define AFE_ADDA_DL_MUTE_OFF		(BIT(12) | BIT(11))
-#define AFE_ADDA_DL_VOICE_DATA		BIT(5)
-#define AFE_ADDA_DL_DEGRADE_GAIN	BIT(1)
-
-/* AFE_ADDA_UL_DL_CON0 */
-#define AFE_ADDA_UL_DL_ADDA_AFE_ON_MASK		BIT(0)
-#define AFE_ADDA_UL_DL_ADDA_AFE_ON		(1 << 0)
-#define AFE_ADDA_UL_DL_ADDA_AFE_OFF		(0 << 0)
-#define AFE_ADDA_UL_DL_DMIC_CLKDIV_ON_MASK	BIT(1)
-#define AFE_ADDA_UL_DL_DMIC_CLKDIV_ON	(1 << 1)
-#define AFE_ADDA_UL_DL_DMIC_CLKDIV_OFF	(0 << 1)
-
-/* AFE_SINEGEN_CON0 (0x01f0) */
-#define AFE_SINEGEN_CON0_EN			BIT(26)
-#define AFE_SINEGEN_CON0_IN_OUT_SEL		BIT(27)
-#define AFE_SINEGEN_CON0_MODE_MASK		GENMASK(31, 28)
-#define AFE_SINEGEN_CON0_AMP_DIV_CH2_MASK	GENMASK(19, 17)
-#define AFE_SINEGEN_CON0_AMP_DIV_CH1_MASK	GENMASK(7, 5)
-#define AFE_SINEGEN_CON0_AMP_DIV_CH2(x)	(((x) & 0x7) << 17)
-#define AFE_SINEGEN_CON0_AMP_DIV_CH1(x)	(((x) & 0x7) << 5)
-#define AFE_SINEGEN_CON0_FREQ_DIV_CH2_MASK	GENMASK(16, 12)
-#define AFE_SINEGEN_CON0_FREQ_DIV_CH1_MASK	GENMASK(4, 0)
-#define AFE_SINEGEN_CON0_FREQ_DIV_CH2(x)	(((x) & 0x1f) << 12)
-#define AFE_SINEGEN_CON0_FREQ_DIV_CH1(x)	(((x) & 0x1f) << 0)
-#define AFE_SINEGEN_CON0_TIMING_CH2_MASK	GENMASK(23, 20)
-#define AFE_SINEGEN_CON0_TIMING_CH1_MASK	GENMASK(11, 8)
-#define AFE_SINEGEN_CON0_TIMING_CH2(x)		(((x) & 0xf) << 20)
-#define AFE_SINEGEN_CON0_TIMING_CH1(x)		(((x) & 0xf) << 8)
-#define AFE_SINEGEN_CON0_TIMING_8K			(0)
-#define AFE_SINEGEN_CON0_TIMING_11D025K		(1)
-#define AFE_SINEGEN_CON0_TIMING_12K			(2)
-#define AFE_SINEGEN_CON0_TIMING_16K			(4)
-#define AFE_SINEGEN_CON0_TIMING_22D05K		(5)
-#define AFE_SINEGEN_CON0_TIMING_24K			(6)
-#define AFE_SINEGEN_CON0_TIMING_32K			(8)
-#define AFE_SINEGEN_CON0_TIMING_44D1K		(9)
-#define AFE_SINEGEN_CON0_TIMING_48K			(10)
-#define AFE_SINEGEN_CON0_TIMING_88D2K		(11)
-#define AFE_SINEGEN_CON0_TIMING_96K			(12)
-#define AFE_SINEGEN_CON0_TIMING_176D4K		(13)
-#define AFE_SINEGEN_CON0_TIMING_192K		(14)
-
-/* AFE_HDMI_OUT_CON0 (0x0370) */
-#define AFE_HDMI_OUT_CON0_CH_MASK	GENMASK(7, 4)
-
-/* AFE_HDMI_CONN0 (0x0390) */
-#define AFE_HDMI_CONN0_O35_I35		(0x7 << 21)
-#define AFE_HDMI_CONN0_O34_I34		(0x6 << 18)
-#define AFE_HDMI_CONN0_O33_I33		(0x5 << 15)
-#define AFE_HDMI_CONN0_O32_I32		(0x4 << 12)
-#define AFE_HDMI_CONN0_O31_I30		(0x2 << 9)
-#define AFE_HDMI_CONN0_O31_I31		(0x3 << 9)
-#define AFE_HDMI_CONN0_O30_I31		(0x3 << 6)
-#define AFE_HDMI_CONN0_O30_I30		(0x2 << 6)
-#define AFE_HDMI_CONN0_O29_I29		(0x1 << 3)
-#define AFE_HDMI_CONN0_O28_I28		(0x0 << 0)
-
-/* AFE_CONN_TDMIN_CON (0x039c) */
-#define AFE_CONN_TDMIN_O41_I41		(0x1 << 3)
-#define AFE_CONN_TDMIN_O41_I40		(0x0 << 3)
-#define AFE_CONN_TDMIN_O40_I41		(0x1 << 0)
-#define AFE_CONN_TDMIN_O40_I40		(0x0 << 0)
-#define AFE_CONN_TDMIN_CON0_MASK	GENMASK(5, 0)
-
-/* AFE_APLL_TUNER_CFG (0x03f0) */
-#define AFE_APLL_TUNER_CFG_MASK	GENMASK(15, 1)
-#define AFE_APLL_TUNER_CFG_EN_MASK	GENMASK(0, 0)
-
-/* AFE_APLL_TUNER_CFG1 (0x03f4) */
-#define AFE_APLL_TUNER_CFG1_MASK	GENMASK(15, 1)
-#define AFE_APLL_TUNER_CFG1_EN_MASK	GENMASK(0, 0)
-
-/* AFE_TDM_CON1 (0x0548) */
-#define AFE_TDM_CON1_LRCK_WIDTH(x)	(((x) - 1) << 24)
-#define AFE_TDM_CON1_32_BCK_CYCLES	(0x2 << 12)
-#define AFE_TDM_CON1_16_BCK_CYCLES	(0x0 << 12)
-#define AFE_TDM_CON1_8CH_PER_SDATA	(0x2 << 10)
-#define AFE_TDM_CON1_4CH_PER_SDATA	(0x1 << 10)
-#define AFE_TDM_CON1_2CH_PER_SDATA	(0x0 << 10)
-#define AFE_TDM_CON1_WLEN_32BIT		BIT(9)
-#define AFE_TDM_CON1_WLEN_16BIT		BIT(8)
-#define AFE_TDM_CON1_MSB_ALIGNED	BIT(4)
-#define AFE_TDM_CON1_1_BCK_DELAY	BIT(3)
-#define AFE_TDM_CON1_LRCK_INV		BIT(2)
-#define AFE_TDM_CON1_EN			BIT(0)
-
-/* AFE_TDM_CON2 (0x054c) */
-#define AFE_TDM_CON2_SOUT_MASK		GENMASK(14, 0)
-
-/* PCM_INTF_CON1 (0x0550) */
-#define PCM_INTF_CON1_EXT_MODEM			(1 << 17)
-#define PCM_INTF_CON1_16BIT			(0 << 16)
-#define PCM_INTF_CON1_24BIT			(1 << 16)
-#define PCM_INTF_CON1_32BCK			(0 << 14)
-#define PCM_INTF_CON1_64BCK			(1 << 14)
-#define PCM_INTF_CON1_MASTER_MODE		(0 << 5)
-#define PCM_INTF_CON1_SLAVE_MODE		(1 << 5)
-#define PCM_INTF_CON1_FS_8K			(0 << 3)
-#define PCM_INTF_CON1_FS_16K			(1 << 3)
-#define PCM_INTF_CON1_FS_32K			(2 << 3)
-#define PCM_INTF_CON1_FS_48K			(3 << 3)
-#define PCM_INTF_CON1_SYNC_LEN(x)		(((x) - 1) << 9)
-#define PCM_INTF_CON1_FORMAT(x)			((x) << 1)
-#define PCM_INTF_CON1_SYNC_OUT_INV		BIT(23)
-#define PCM_INTF_CON1_BCLK_OUT_INV		BIT(22)
-#define PCM_INTF_CON1_SYNC_IN_INV		BIT(21)
-#define PCM_INTF_CON1_BCLK_IN_INV		BIT(20)
-#define PCM_INTF_CON1_BYPASS_ASRC		BIT(6)
-#define PCM_INTF_CON1_EN			BIT(0)
-#define PCM_INTF_CON1_CONFIG_MASK		(0xf3fffe)
-
-/* AFE_TDM_IN_CON1 (0x0588) */
-#define AFE_TDM_IN_CON1_LRCK_WIDTH(x)		(((x) - 1) << 24)
-#define AFE_TDM_IN_CON1_FAST_LRCK_CYCLE_32BCK	(0x2 << 16)
-#define AFE_TDM_IN_CON1_FAST_LRCK_CYCLE_16BCK	(0x0 << 16)
-#define AFE_TDM_IN_CON1_8CH_PER_SDATA		(0x2 << 12)
-#define AFE_TDM_IN_CON1_4CH_PER_SDATA		(0x1 << 12)
-#define AFE_TDM_IN_CON1_2CH_PER_SDATA		(0x0 << 12)
-#define AFE_TDM_IN_CON1_WLEN_32BIT		(0x3 << 8)
-#define AFE_TDM_IN_CON1_WLEN_24BIT		(0x2 << 8)
-#define AFE_TDM_IN_CON1_WLEN_16BIT		(0x1 << 8)
-#define AFE_TDM_IN_CON1_I2S			BIT(3)
-#define AFE_TDM_IN_CON1_LRCK_INV		BIT(2)
-#define AFE_TDM_IN_CON1_BCK_INV			BIT(1)
-#define AFE_TDM_IN_CON1_EN			BIT(0)
-
-/* AFE_TDM_IN_CON2 (0x058c) */
-#define AFE_TDM_IN_CON2_DISABLE_CH01		BIT(0)
-#define AFE_TDM_IN_CON2_DISABLE_CH23		BIT(1)
-#define AFE_TDM_IN_CON2_DISABLE_CH45		BIT(2)
-#define AFE_TDM_IN_CON2_DISABLE_CH67		BIT(3)
-
-/* AFE_DMIC0_UL_SRC_CON0 (0x05b4)
- * AFE_DMIC0_UL_SRC_CON0 (0x0620)
- * AFE_DMIC0_UL_SRC_CON0 (0x0780)
- * AFE_DMIC0_UL_SRC_CON0 (0x07ec)
- */
-#define DMIC_TOP_CON_DMIC_TWO_WIRE_MODE			BIT(23)
-#define DMIC_TOP_CON_DMIC_CK_PHASE_SEL_CH2(x)		((x) << 24)
-#define DMIC_TOP_CON_DMIC_CK_PHASE_SEL_CH1(x)		((x) << 27)
-#define DMIC_TOP_CON_DMIC_CH2_ON_MASK			BIT(22)
-#define DMIC_TOP_CON_DMIC_CH2_ON			(1 << 22)
-#define DMIC_TOP_CON_DMIC_CH2_OFF			(0 << 22)
-#define DMIC_TOP_CON_DMIC_CH1_ON_MASK			BIT(21)
-#define DMIC_TOP_CON_DMIC_CH1_ON			(1 << 21)
-#define DMIC_TOP_CON_DMIC_CH1_OFF			(0 << 21)
-#define DMIC_TOP_CON_DMIC_VOICE_MODE_8K			(0 << 17)
-#define DMIC_TOP_CON_DMIC_VOICE_MODE_16K		(1 << 17)
-#define DMIC_TOP_CON_DMIC_VOICE_MODE_32K		(2 << 17)
-#define DMIC_TOP_CON_DMIC_VOICE_MODE_48K		(3 << 17)
-#define DMIC_TOP_CON_DMIC_NO_LOW_POWER_MODE		(0 << 14)
-#define DMIC_TOP_CON_DMIC_LOW_POWER_MODE(x)		((x) << 14)
-#define DMIC_TOP_CON_DMIC_IIR_ON			BIT(10)
-#define DMIC_TOP_CON_DMIC_INPUT_MODE(x)			((x) << 5)
-#define DMIC_TOP_CON_DMIC_IIR_MODE(x)			((x) << 7)
-#define DMIC_TOP_CON_DMIC_SDM3_LEVEL_MODE		BIT(1)
-#define DMIC_TOP_CON_DMIC_SRC_ON_MASK			BIT(0)
-#define DMIC_TOP_CON_DMIC_SRC_ON			(1 << 0)
-#define DMIC_TOP_CON_DMIC_SRC_OFF			(0 << 0)
-#define DMIC_TOP_CON_DMIC_SDM3_DE_SELECT		(0 << 1)
-#define DMIC_TOP_CON_CONFIG_MASK			(0x3f8ed7a6)
-
-/* AFE_TDM_ASRC_CON0  (0x06f8)*/
-#define TDM_ASRC_OUT_MODE(x)		((x) << 4)
-#define TDM_ASRC_OUT_MODE_MASK		GENMASK(7, 4)
-#define TDM_ASRC_OUT_SEL			BIT(2)
-#define TDM_ASRC_OUT_SEL_TO_CM1		(0 << 2)
-#define TDM_ASRC_OUT_SEL_TO_CM2		(1 << 2)
-#define TDM_ASRC_IN_SEL_FROM_TDMIN	(0 << 1)
-#define TDM_ASRC_IN_SEL_FROM_TDMOUT	(1 << 1)
-#define TDM_ASRC_IN_SEL_MASK		BIT(1)
-#define TDM_ASRC_EN_ON		BIT(0)
-
-/* AFE_CONN_24BIT (0x0AA4) */
-#define AFE_CONN_24BIT_O10		BIT(10)
-#define AFE_CONN_24BIT_O09		BIT(9)
-#define AFE_CONN_24BIT_O06		BIT(6)
-#define AFE_CONN_24BIT_O05		BIT(5)
-#define AFE_CONN_24BIT_O04		BIT(4)
-#define AFE_CONN_24BIT_O03		BIT(3)
-#define AFE_CONN_24BIT_O02		BIT(2)
-#define AFE_CONN_24BIT_O01		BIT(1)
-#define AFE_CONN_24BIT_O00		BIT(0)
-
-/* AFE_HD_ENGEN_ENABLE */
-#define AFE_22M_PLL_EN		BIT(0)
-#define AFE_22M_PLL_ON		(1 << 0)
-#define AFE_22M_PLL_OFF		(0 << 0)
-#define AFE_24M_PLL_EN		BIT(1)
-#define AFE_24M_PLL_ON		(1 << 1)
-#define AFE_24M_PLL_OFF		(0 << 1)
-
-/* AFE_GAIN1_CON0 (0x0410) */
-#define AFE_GAIN1_CON0_EN_MASK		GENMASK(0, 0)
-#define AFE_GAIN1_CON0_MODE_MASK	GENMASK(7, 4)
-#define AFE_GAIN1_CON0_SAMPLE_PER_STEP_MASK	GENMASK(15, 8)
-
-/* AFE_GAIN1_CON1 (0x0414) */
-#define AFE_GAIN1_CON1_MASK		GENMASK(19, 0)
-
-/* AFE_GAIN1_CUR (0x0B78) */
-#define AFE_GAIN1_CUR_MASK		GENMASK(19, 0)
-
-/* AFE_CM1_CON0 (0x0e50) */
-/* AFE_CM2_CON0 (0x0e60) */
-#define CM_AFE_CM_CH_NUM(x)				(((x) - 1) << 0)
-#define CM_AFE_CM_CH_NUM_MASK			GENMASK(3, 0)
-#define CM_AFE_CM_ON					BIT(4)
-#define CM_AFE_CM_OFF					(0 << 4)
-#define CM_AFE_CM_START_DATA(x)			((x) << 8)
-#define CM_AFE_CM_START_DATA_MASK		GENMASK(11, 8)
-
-#define CM_AFE_CM1_VUL_SEL_CM1_OUTPUT	(0 << 12)
-#define CM_AFE_CM1_VUL_SEL_O17_O18		(1 << 12)
-#define CM_AFE_CM1_VUL_SEL				BIT(12)
-#define CM_AFE_CM1_IN_MODE(x)			((x) << 16)
-#define CM_AFE_CM1_IN_MODE_MASK			GENMASK(19, 16)
-#define CM_AFE_CM2_TDM_SEL_CM2_OUTPUT	(1 << 12)
-#define CM_AFE_CM2_TDM_SEL_TDM			(0 << 12)
-#define CM_AFE_CM2_TDM_SEL				BIT(12)
-#define CM_AFE_CM2_CLK_SEL_24M			(0 << 13)
-#define CM_AFE_CM2_CLK_SEL_22M			(1 << 13)
-#define CM_AFE_CM2_CLK_SEL				BIT(13)
-#define CM_AFE_CM2_GASRC1_OUT_SEL		BIT(17)
-#define CM_AFE_CM2_GASRC2_OUT_SEL		BIT(16)
-#define GASRC1_OUT_TO_TDM_OUT_EN		(0 << 17)
-#define GASRC1_OUT_TO_ENGEN_OUT_EN		(1 << 17)
-#define GASRC2_OUT_TO_TDM_OUT_EN		(0 << 16)
-#define GASRC2_OUT_TO_ENGEN_OUT_EN		(1 << 16)
-
-/* AFE_CM2_CONN* */
-#define CM2_AFE_CM2_CONN_CFG1(x)		((x) << 0)
-#define CM2_AFE_CM2_CONN_CFG1_MASK		GENMASK(4, 0)
-#define CM2_AFE_CM2_CONN_CFG2(x)		((x) << 5)
-#define CM2_AFE_CM2_CONN_CFG2_MASK		GENMASK(9, 5)
-#define CM2_AFE_CM2_CONN_CFG3(x)		((x) << 10)
-#define CM2_AFE_CM2_CONN_CFG3_MASK		GENMASK(14, 10)
-#define CM2_AFE_CM2_CONN_CFG4(x)		((x) << 15)
-#define CM2_AFE_CM2_CONN_CFG4_MASK		GENMASK(19, 15)
-#define CM2_AFE_CM2_CONN_CFG5(x)		((x) << 20)
-#define CM2_AFE_CM2_CONN_CFG5_MASK		GENMASK(24, 20)
-#define CM2_AFE_CM2_CONN_CFG6(x)		((x) << 25)
-#define CM2_AFE_CM2_CONN_CFG6_MASK		GENMASK(29, 25)
-#define CM2_AFE_CM2_CONN_CFG7(x)		((x) << 0)
-#define CM2_AFE_CM2_CONN_CFG7_MASK		GENMASK(4, 0)
-#define CM2_AFE_CM2_CONN_CFG8(x)		((x) << 5)
-#define CM2_AFE_CM2_CONN_CFG8_MASK		GENMASK(9, 5)
-#define CM2_AFE_CM2_CONN_CFG9(x)		((x) << 10)
-#define CM2_AFE_CM2_CONN_CFG9_MASK		GENMASK(14, 10)
-#define CM2_AFE_CM2_CONN_CFG10(x)		((x) << 15)
-#define CM2_AFE_CM2_CONN_CFG10_MASK		GENMASK(19, 15)
-#define CM2_AFE_CM2_CONN_CFG11(x)		((x) << 20)
-#define CM2_AFE_CM2_CONN_CFG11_MASK		GENMASK(24, 20)
-#define CM2_AFE_CM2_CONN_CFG12(x)		((x) << 25)
-#define CM2_AFE_CM2_CONN_CFG12_MASK		GENMASK(29, 25)
-#define CM2_AFE_CM2_CONN_CFG13(x)		((x) << 0)
-#define CM2_AFE_CM2_CONN_CFG13_MASK		GENMASK(4, 0)
-#define CM2_AFE_CM2_CONN_CFG14(x)		((x) << 5)
-#define CM2_AFE_CM2_CONN_CFG14_MASK		GENMASK(9, 5)
-#define CM2_AFE_CM2_CONN_CFG15(x)		((x) << 10)
-#define CM2_AFE_CM2_CONN_CFG15_MASK		GENMASK(14, 10)
-#define CM2_AFE_CM2_CONN_CFG16(x)		((x) << 15)
-#define CM2_AFE_CM2_CONN_CFG16_MASK		GENMASK(19, 15)
-
-/* AFE_CM1_CON* */
-#define CM_AFE_CM_UPDATE_CNT1(x)		(((x) & (0xffff)) << 0)
-#define CM_AFE_CM_UPDATE_CNT2(x)		(((x) & (0xffff)) << 16)
-#define CM_AFE_CM_UPDATE_CNT1_MASK		GENMASK(15, 0)
-#define CM_AFE_CM_UPDATE_CNT2_MASK		GENMASK(31, 16)
-#define CM_AFE_CM_UPDATE_CNT_MASK		GENMASK(31, 0)
-
-/* AFE_CM2_CON0 (0x0e60)*/
-#define GASRC_ASRC1_OUT_EN_SEL BIT(17)
-#define GASRC_ASRC2_OUT_EN_SEL BIT(16)
-
-
-/* AFE_GENERAL1_ASRC_2CH_CON0 (0x0e80)
- * AFE_GENERAL2_ASRC_2CH_CON0 (0x0f00)
- */
-#define GASRC_CON0_CHSET0_CLR_IIR_HISTORY	BIT(17)
-#define GASRC_NEW_CON0_CHSET0_OFS_SEL_MASK	GENMASK(15, 14)
-#define GASRC_NEW_CON0_CHSET0_OFS_SEL_TX		(0 << 14)
-#define GASRC_NEW_CON0_CHSET0_OFS_SEL_RX		(1 << 14)
-#define GASRC_NEW_CON0_CHSET0_IFS_SEL_MASK	GENMASK(13, 12)
-#define GASRC_NEW_CON0_CHSET0_IFS_SEL_TX		(3 << 12)
-#define GASRC_NEW_CON0_CHSET0_IFS_SEL_RX		(2 << 12)
-#define GASRC_CON0_CHSET_IIR_EN		BIT(11)
-#define GASRC_CON0_CHSET_IIR_STAGE(x)	((x) << 8)
-#define GASRC_CON0_CHSET_IIR_STAGE_MASK	GENMASK(10, 8)
-#define GASRC_CON0_CHSET_STR_CLR		BIT(4)
-#define GASRC_CON0_COEFF_SRAM_CTRL		BIT(1)
-#define GASRC_CON0_ASM_ON				BIT(0)
-
-/* GENERAL_ASRC_MODE (0x0eb8) */
-#define GASRC_MODE_GASRC1_IN_MODE(x)	(((x) & 0xf) << 0)
-#define GASRC_MODE_GASRC2_IN_MODE(x)	(((x) & 0xf) << 8)
-#define GASRC_MODE_GASRC1_IN_MODE_MASK	GENMASK(3, 0)
-#define GASRC_MODE_GASRC2_IN_MODE_MASK	GENMASK(11, 8)
-#define GASRC_MODE_GASRC1_OUT_MODE(x)	(((x) & 0xf) << 4)
-#define GASRC_MODE_GASRC2_OUT_MODE(x)	(((x) & 0xf) << 12)
-#define GASRC_MODE_GASRC1_OUT_MODE_MASK	GENMASK(7, 4)
-#define GASRC_MODE_GASRC2_OUT_MODE_MASK	GENMASK(15, 12)
-
-/* GENERAL_ASRC_EN_ON (0x0ebc) */
-#define GASRC_EN_ON_MASK(x)	(0x1 << (x))
-#define GASRC_EN_ON(x)		(0x1 << (x))
-#define GASRC_EN_OFF(x)		(0x0 << (x))
-
-/* AFE_GENERAL1_ASRC_2CH_CON5 (0x0e94)
- * AFE_GENERAL2_ASRC_2CH_CON5 (0x0f14)
- */
-#define GASRC_CON5_CALI_CYCLE_MASK GENMASK(31, 16)
-#define GASRC_CON5_CALI_64_CYCLE (0x3F << 16)
-#define GASRC_CON5_CALI_96_CYCLE (0x5F << 16)
-#define GASRC_CON5_CALI_441_CYCLE (0x1B8 << 16)
-#define GASRC_CON5_CALI_AUTORST_ENABLE BIT(15)
-#define GASRC_CON5_AUTO_TUNE_FREQ5_ENABLE	BIT(12)
-#define GASRC_CON5_AUTO_TUNE_FREQ5_DISABLE	(0x0 << 12)
-#define GASRC_CON5_COMP_FREQ_RES_ENABLE		BIT(11)
-#define GASRC_CON5_CALI_BP_DGL_BYPASS	BIT(7)
-#define GASRC_CON5_AUTO_TUNE_FREQ4_ENABLE	 BIT(3)
-#define GASRC_CON5_AUTO_TUNE_FREQ4_DISABLE	(0x0 << 3)
-#define GASRC_CON5_CALI_AUTO_RESTART_ENABLE	BIT(2)
-#define GASRC_CON5_CALI_USE_FREQ	BIT(1)
-#define GASRC_CON5_CALI_USE_PERIOD	(0x0 << 1)
-#define GASRC_CON5_CALI_ON	BIT(0)
-#define GASRC_CON5_CALI_OFF	(0x0 << 0)
-#define GASRC_CON5_CALI_SEL_MASK	GENMASK(9, 8)
-#define GASRC_CON5_CALI_SEL_00	(0x0 << 8)
-#define GASRC_CON5_CALI_SEL_01	(0x1 << 8)
-
-/* AFE_TDM_GASRC*_ASRC_2CH_CON0 */
-#define TDM_ASRC_CON0_ONE_HEART			BIT(31)
-
-#endif /* _MT8365_AFE_REGS_H_ */
diff --git a/src/platform/mt8365/include/platform/platform.h b/src/platform/mt8365/include/platform/platform.h
deleted file mode 100644
index c447312c16a5..000000000000
--- a/src/platform/mt8365/include/platform/platform.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2024 MediaTek. All rights reserved.
- *
- * Author: Andrew Perepech <andrew.perepech@mediatek.com>
- */
-
-#ifdef __SOF_PLATFORM_H__
-
-#ifndef __PLATFORM_PLATFORM_H__
-#define __PLATFORM_PLATFORM_H__
-
-#if !defined(__ASSEMBLER__) && !defined(LINKER)
-
-#include <sof/lib/mailbox.h>
-#include <stddef.h>
-#include <stdint.h>
-
-struct ll_schedule_domain;
-struct timer;
-
-#define PLATFORM_DEFAULT_CLOCK CLK_CPU(0)
-#define LPSRAM_SIZE 16384
-
-/* Host page size */
-#define HOST_PAGE_SIZE 4096
-#define PLATFORM_PAGE_TABLE_SIZE 256
-
-/* pipeline IRQ */
-#define PLATFORM_SCHEDULE_IRQ MTK_DSP_IRQ_SOFTWARE0
-#define PLATFORM_SCHEDULE_IRQ_NAME NULL
-
-/* Platform stream capabilities */
-#define PLATFORM_MAX_CHANNELS 4
-#define PLATFORM_MAX_STREAMS 5
-
-/* local buffer size of DMA tracing */
-#define DMA_TRACE_LOCAL_SIZE HOST_PAGE_SIZE
-
-/* trace bytes flushed during panic */
-#define DMA_FLUSH_TRACE_SIZE (MAILBOX_TRACE_SIZE >> 2)
-
-/* the interval of DMA trace copying */
-#define DMA_TRACE_PERIOD 500000
-
-/*
- * the interval of reschedule DMA trace copying in special case like half
- * fullness of local DMA trace buffer
- */
-#define DMA_TRACE_RESCHEDULE_TIME 100
-
-/* DSP default delay in cycles */
-#define PLATFORM_DEFAULT_DELAY 12
-
-#define SRAM_REG_FW_STATUS	0x4
-#define SRAM_REG_OP_CPU2DSP	0x8
-#define SRAM_REG_OP_DSP2CPU	0xC
-
-/* Platform defined panic code */
-static inline void platform_panic(uint32_t p)
-{
-	/* Store the error code in the debug box so the
-	 * application processor can pick it up. Takes up 4 bytes
-	 * from the debug box.
-	 */
-	mailbox_sw_reg_write(SRAM_REG_FW_STATUS, p);
-
-	/* Notify application processor */
-	trigger_irq_to_host_req();
-}
-
-/**
- * \brief Platform specific CPU entering idle.
- * May be power-optimized using platform specific capabilities.
- * @param level Interrupt level.
- */
-void platform_wait_for_interrupt(int level);
-
-extern intptr_t _module_init_start;
-extern intptr_t _module_init_end;
-#endif
-
-#endif /* __PLATFORM_PLATFORM_H__ */
-
-#else
-
-#error "This file shouldn't be included from outside of sof/platform.h"
-
-#endif /* __SOF_PLATFORM_H__ */
diff --git a/src/platform/mt8365/include/platform/trace/trace.h b/src/platform/mt8365/include/platform/trace/trace.h
deleted file mode 100644
index 63122335e650..000000000000
--- a/src/platform/mt8365/include/platform/trace/trace.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Copyright(c) 2024 MediaTek. All rights reserved.
- *
- * Author: Andrew Perepech <andrew.perepech@mediatek.com>
- */
-
-#ifdef __SOF_TRACE_TRACE_H__
-
-#ifndef __PLATFORM_TRACE_TRACE_H__
-#define __PLATFORM_TRACE_TRACE_H__
-
-#include <sof/lib/mailbox.h>
-#include <sof/lib/memory.h>
-#include <sof/lib/io.h>
-#include <platform/drivers/mt_reg_base.h>
-
-#define platform_trace_point(__x)
-
-#endif /* __PLATFORM_TRACE_TRACE_H__ */
-
-#else
-
-#error "This file shouldn't be included from outside of sof/trace/trace.h"
-
-#endif /* __SOF_TRACE_TRACE_H__ */
diff --git a/src/platform/mt8365/lib/CMakeLists.txt b/src/platform/mt8365/lib/CMakeLists.txt
deleted file mode 100644
index ef71f8eea6cd..000000000000
--- a/src/platform/mt8365/lib/CMakeLists.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-
-add_local_sources(sof
-	clk.c
-	dma.c
-	memory.c
-	dai.c
-)
diff --git a/src/platform/mt8365/lib/clk.c b/src/platform/mt8365/lib/clk.c
deleted file mode 100644
index 5907ef96d477..000000000000
--- a/src/platform/mt8365/lib/clk.c
+++ /dev/null
@@ -1,189 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-/*
- * Copyright(c) 2024 MediaTek. All rights reserved.
- *
- * Author: Andrew Perepech <andrew.perepech@mediatek.com>
- */
-
-#include <sof/common.h>
-#include <rtos/clk.h>
-#include <sof/lib/cpu.h>
-#include <sof/lib/memory.h>
-#include <sof/lib/notifier.h>
-#include <sof/lib/uuid.h>
-#include <rtos/wait.h>
-#include <rtos/sof.h>
-#include <sof/trace/trace.h>
-
-SOF_DEFINE_REG_UUID(clkdrv_mt8365);
-
-/* unused with Zephyr, generates no output */
-DECLARE_TR_CTX(clkdrv_tr, SOF_UUID(clkdrv_mt8365_uuid), LOG_LEVEL_INFO);
-
-static int dsppll_enable;  /* default no adsp clock*/
-static int adsp_clock;
-
-const struct freq_table platform_cpu_freq[] = {
-	{ 13000000, 13000},
-	{ 26000000, 13000},
-	{ 312000000, 13000},
-	{ 400000000, 13000},
-	{ 600000000, 13000},
-};
-
-const uint32_t cpu_freq_enc[] = {
-	13000000,
-	26000000,
-	0x83180000,
-	0x820F6276,
-	0x821713B1,
-};
-
-STATIC_ASSERT(ARRAY_SIZE(platform_cpu_freq) == NUM_CPU_FREQ,
-	      invalid_number_of_cpu_frequencies);
-
-static struct clock_info platform_clocks_info[NUM_CLOCKS];
-
-static inline void clk_setl(uint32_t addr, uint32_t val)
-{
-	io_reg_write(addr, io_reg_read(addr) | (val));
-}
-
-static inline void clk_clrl(uint32_t addr, uint32_t val)
-{
-	io_reg_write(addr, io_reg_read(addr) & ~(val));
-}
-
-static inline int dsp_clk_value_convert(int value)
-{
-	int ret;
-
-	switch (value) {
-	case DSP_CLK_13M:
-		ret = CLK_DSP_SEL_26M_D_2;
-		break;
-	case DSP_CLK_26M:
-		ret = CLK_DSP_SEL_26M;
-		break;
-	case DSP_CLK_PLL_312M:
-	case DSP_CLK_PLL_400M:
-	case DSP_CLK_PLL_600M:
-		ret = CLK_DSP_SEL_DSPPLL;
-		break;
-	default:
-		ret = CLK_DSP_SEL_26M;
-		break;
-	}
-
-	return ret;
-}
-
-static void clk_dsppll_enable(void)
-{
-	tr_dbg(&clkdrv_tr, "entry");
-
-	clk_setl(DSPPLL_CON3, PLL_PWR_ON);
-	wait_delay_us(1);
-	clk_clrl(DSPPLL_CON3, PLL_ISO_EN);
-	wait_delay_us(1);
-	clk_setl(DSPPLL_CON0, PLL_BASE_EN);
-	wait_delay_us(20);
-	dsppll_enable = 1;
-
-}
-
-static void clk_dsppll_disable(void)
-{
-	tr_dbg(&clkdrv_tr, "entry");
-
-	clk_clrl(DSPPLL_CON0, PLL_BASE_EN);
-	wait_delay_us(1);
-	clk_setl(DSPPLL_CON3, PLL_ISO_EN);
-	wait_delay_us(1);
-	clk_clrl(DSPPLL_CON3, PLL_PWR_ON);
-	dsppll_enable = 0;
-}
-
-static int dsppll_get_enable(void)
-{
-	tr_dbg(&clkdrv_tr, "dsppll_enable=%d.\n", dsppll_enable);
-
-	return dsppll_enable;
-}
-
-static int set_mux_sel(enum mux_id_t mux_id, uint32_t value)
-{
-	switch (mux_id) {
-	case MUX_CLK_DSP_SEL:
-		io_reg_update_bits(CLK_CFG_8_CLR, (0x7 << 24), (0x7 << 24));
-		io_reg_update_bits(CLK_CFG_8_SET, (0x7 << 24), (value << 24));
-		io_reg_write(CLK_CFG_UPDATE1, 0x8);
-
-		tr_dbg(&clkdrv_tr, "adspclk_mux=%x, CLK_CFG_8=0x%08x\n",
-		       value, io_reg_read(CLK_CFG_8));
-		break;
-	default:
-		tr_dbg(&clkdrv_tr, "error: unknown mux_id (%d)\n", mux_id);
-		break;
-	}
-
-	return 0;
-}
-
-static int clock_platform_set_dsp_freq(int clock, int freq_idx)
-{
-	uint32_t enc = cpu_freq_enc[freq_idx];
-	int clk_mux;
-	int adsp_clk_req = platform_cpu_freq[freq_idx].freq;
-
-	if (adsp_clock == adsp_clk_req)
-		return 0;
-
-	tr_info(&clkdrv_tr, "clock_platform_set_cpu_freq %d\n", adsp_clk_req);
-
-	/* convert res manager value to driver map */
-	clk_mux = dsp_clk_value_convert(freq_idx);
-
-	if (enc > 26000000) {
-		/* adsp pll */
-		if (!dsppll_get_enable()) {
-			clk_dsppll_enable();
-			set_mux_sel(MUX_CLK_DSP_SEL, clk_mux);
-		}
-		/* set adsp pll clock */
-		io_reg_update_bits(DSPPLL_CON1, 0xffffffff, enc);
-	} else {
-		/* clk26m */
-		if (dsppll_get_enable()) {
-			set_mux_sel(MUX_CLK_DSP_SEL, clk_mux);
-			clk_dsppll_disable();
-		}
-	}
-
-	adsp_clock = adsp_clk_req;
-
-	return 0;
-}
-
-void platform_clock_init(struct sof *sof)
-{
-	int i;
-
-	sof->clocks = platform_clocks_info;
-
-	for (i = 0; i < CONFIG_CORE_COUNT; i++) {
-		sof->clocks[i] = (struct clock_info){
-			.freqs_num = NUM_CPU_FREQ,
-			.freqs = platform_cpu_freq,
-			.default_freq_idx = CPU_DEFAULT_IDX,
-			.current_freq_idx = CPU_DEFAULT_IDX,
-			.notification_id = NOTIFIER_ID_CPU_FREQ,
-			.notification_mask = NOTIFIER_TARGET_CORE_MASK(i),
-			.set_freq = clock_platform_set_dsp_freq,
-		};
-	}
-
-	adsp_clock = 0;
-	dsppll_enable = 0;
-	clock_set_freq(CLK_CPU(cpu_get_id()), CLK_MAX_CPU_HZ);
-}
diff --git a/src/platform/mt8365/lib/dai.c b/src/platform/mt8365/lib/dai.c
deleted file mode 100644
index 522952996d75..000000000000
--- a/src/platform/mt8365/lib/dai.c
+++ /dev/null
@@ -1,71 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-/*
- * Copyright(c) 2024 MediaTek. All rights reserved.
- *
- * Author: Andrew Perepech <andrew.perepech@mediatek.com>
- */
-
-#include <sof/common.h>
-#include <sof/lib/dai.h>
-#include <sof/lib/memory.h>
-#include <rtos/sof.h>
-#include <rtos/spinlock.h>
-#include <ipc/dai.h>
-#include <ipc/stream.h>
-
-#include <sof/drivers/afe-dai.h>
-#include <mt8365-afe-common.h>
-
-/*	MEMIF specified IRQs set in the Linux driver:
- *
- *	[MT8365_AFE_MEMIF_DL1] = MT8365_AFE_IRQ1,
- *	[MT8365_AFE_MEMIF_DL2] = MT8365_AFE_IRQ2,
- *	[MT8365_AFE_MEMIF_TDM_OUT] = MT8365_AFE_IRQ5,
- *	// [MT8365_AFE_MEMIF_SPDIF_OUT] = MT8365_AFE_IRQ6,
- *	[MT8365_AFE_MEMIF_AWB] = MT8365_AFE_IRQ3,
- *	[MT8365_AFE_MEMIF_VUL] = MT8365_AFE_IRQ4,
- *	[MT8365_AFE_MEMIF_VUL2] = MT8365_AFE_IRQ7,
- *	[MT8365_AFE_MEMIF_VUL3] = MT8365_AFE_IRQ8,
- *	// [MT8365_AFE_MEMIF_SPDIF_IN] = MT8365_AFE_IRQ9,
- *	[MT8365_AFE_MEMIF_TDM_IN] = MT8365_AFE_IRQ10,
- */
-
-static int afe_dai_handshake[MT8365_DAI_NUM] = {
-	AFE_HANDSHAKE(MT8365_AFE_IO_INT_ADDA_OUT, MT8365_AFE_IRQ_1, MT8365_MEMIF_DL1),
-	AFE_HANDSHAKE(MT8365_AFE_IO_2ND_I2S, MT8365_AFE_IRQ_2, MT8365_MEMIF_DL2),
-	AFE_HANDSHAKE(MT8365_AFE_IO_INT_ADDA_IN, MT8365_AFE_IRQ_3, MT8365_MEMIF_AWB),
-	AFE_HANDSHAKE(MT8365_AFE_IO_DMIC, MT8365_AFE_IRQ_4, MT8365_MEMIF_VUL),
-};
-
-static struct dai afe_dai[MT8365_DAI_NUM];
-
-const struct dai_type_info dti[] = {
-	{
-		.type = SOF_DAI_MEDIATEK_AFE,
-		.dai_array = afe_dai,
-		.num_dais = ARRAY_SIZE(afe_dai),
-	},
-};
-
-const struct dai_info lib_dai = {
-	.dai_type_array = dti,
-	.num_dai_types = ARRAY_SIZE(dti),
-};
-
-int dai_init(struct sof *sof)
-{
-	int i;
-
-	/* initialize spin locks early to enable ref counting */
-	for (i = 0; i < ARRAY_SIZE(afe_dai); i++) {
-		k_spinlock_init(&afe_dai[i].lock);
-		afe_dai[i].index = AFE_HS_GET_DAI(afe_dai_handshake[i]);
-		afe_dai[i].drv = &afe_dai_driver;
-		/* TODO, fifo[0] change to target playback or capture */
-		afe_dai[i].plat_data.fifo[0].handshake = afe_dai_handshake[i];
-	}
-
-	sof->dai_info = &lib_dai;
-
-	return 0;
-}
diff --git a/src/platform/mt8365/lib/dma.c b/src/platform/mt8365/lib/dma.c
deleted file mode 100644
index d80c81723676..000000000000
--- a/src/platform/mt8365/lib/dma.c
+++ /dev/null
@@ -1,59 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-/*
- * Copyright(c) 2024 MediaTek. All rights reserved.
- *
- * Author: Andrew Perepech <andrew.perepech@mediatek.com>
- */
-
-#include <sof/common.h>
-#include <sof/drivers/afe-memif.h>
-#include <rtos/interrupt.h>
-#include <sof/lib/dma.h>
-#include <sof/lib/memory.h>
-#include <rtos/sof.h>
-#include <rtos/spinlock.h>
-
-#include <mt8365-afe-regs.h>
-#include <mt8365-afe-common.h>
-
-extern const struct dma_ops dummy_dma_ops;
-
-static struct dma dma[PLATFORM_NUM_DMACS] = {
-{
-	.plat_data = {
-		.id		= DMA_ID_HOST,
-		.dir		= DMA_DIR_HMEM_TO_LMEM | DMA_DIR_LMEM_TO_HMEM,
-		.devs		= DMA_DEV_HOST,
-		.channels	= 16,
-	},
-	.ops	= &dummy_dma_ops,
-},
-{
-	.plat_data = {
-		.id		= DMA_ID_AFE_MEMIF,
-		.dir		= DMA_DIR_MEM_TO_DEV | DMA_DIR_DEV_TO_MEM,
-		.devs		= DMA_DEV_AFE_MEMIF,
-		.base		= AFE_REG_BASE,
-		.channels	= MT8365_MEMIF_NUM,
-	},
-	.ops	= &memif_ops,
-},
-};
-
-static const struct dma_info lib_dma = {
-	.dma_array = cache_to_uncache_init((struct dma *)dma),
-	.num_dmas = ARRAY_SIZE(dma)
-};
-
-int dmac_init(struct sof *sof)
-{
-	int i;
-
-	/* early lock initialization for ref counting */
-	for (i = 0; i < ARRAY_SIZE(dma); i++)
-		k_spinlock_init(&dma[i].lock);
-
-	sof->dma_info = &lib_dma;
-
-	return 0;
-}
diff --git a/src/platform/mt8365/lib/memory.c b/src/platform/mt8365/lib/memory.c
deleted file mode 100644
index e64eef957742..000000000000
--- a/src/platform/mt8365/lib/memory.c
+++ /dev/null
@@ -1,101 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-/*
- * Copyright(c) 2024 MediaTek. All rights reserved.
- *
- * Author: Andrew Perepech <andrew.perepech@mediatek.com>
- */
-
-#include <sof/common.h>
-#include <sof/lib/mm_heap.h>
-#include <sof/lib/memory.h>
-#include <rtos/sof.h>
-#include <ipc/topology.h>
-
-/* Heap blocks for system runtime */
-static struct block_hdr sys_rt_block64[HEAP_SYS_RT_COUNT64];
-static struct block_hdr sys_rt_block512[HEAP_SYS_RT_COUNT512];
-static struct block_hdr sys_rt_block1024[HEAP_SYS_RT_COUNT1024];
-
-/* Heap memory for system runtime */
-static struct block_map sys_rt_heap_map[] = {
-	BLOCK_DEF(64, HEAP_SYS_RT_COUNT64, sys_rt_block64),
-	BLOCK_DEF(512, HEAP_SYS_RT_COUNT512, sys_rt_block512),
-	BLOCK_DEF(1024, HEAP_SYS_RT_COUNT1024, sys_rt_block1024),
-};
-
-/* Heap blocks for modules */
-static struct block_hdr mod_block16[HEAP_RT_COUNT16];
-static struct block_hdr mod_block32[HEAP_RT_COUNT32];
-static struct block_hdr mod_block64[HEAP_RT_COUNT64];
-static struct block_hdr mod_block128[HEAP_RT_COUNT128];
-static struct block_hdr mod_block256[HEAP_RT_COUNT256];
-static struct block_hdr mod_block512[HEAP_RT_COUNT512];
-static struct block_hdr mod_block1024[HEAP_RT_COUNT1024];
-static struct block_hdr mod_block2048[HEAP_RT_COUNT2048];
-static struct block_hdr mod_block4096[HEAP_RT_COUNT4096];
-
-/* Heap memory map for modules */
-static struct block_map rt_heap_map[] = {
-	BLOCK_DEF(16, HEAP_RT_COUNT16, mod_block16),
-	BLOCK_DEF(32, HEAP_RT_COUNT32, mod_block32),
-	BLOCK_DEF(64, HEAP_RT_COUNT64, mod_block64),
-	BLOCK_DEF(128, HEAP_RT_COUNT128, mod_block128),
-	BLOCK_DEF(256, HEAP_RT_COUNT256, mod_block256),
-	BLOCK_DEF(512, HEAP_RT_COUNT512, mod_block512),
-	BLOCK_DEF(1024, HEAP_RT_COUNT1024, mod_block1024),
-	BLOCK_DEF(2048, HEAP_RT_COUNT2048, mod_block2048),
-	BLOCK_DEF(4096, HEAP_RT_COUNT4096, mod_block4096),
-};
-
-/* Heap blocks for buffers */
-static struct block_hdr buf_block[HEAP_BUFFER_COUNT];
-
-/* Heap memory map for buffers */
-static struct block_map buf_heap_map[] = {
-	BLOCK_DEF(HEAP_BUFFER_BLOCK_SIZE, HEAP_BUFFER_COUNT, buf_block),
-};
-
-static struct mm memmap = {
-	.system[0] = {
-		.heap = HEAP_SYSTEM_BASE,
-		.size = HEAP_SYSTEM_SIZE,
-		.info = {.free = HEAP_SYSTEM_SIZE,},
-		.caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_CACHE |
-			SOF_MEM_CAPS_DMA,
-	},
-	.system_runtime[0] = {
-		.blocks = ARRAY_SIZE(sys_rt_heap_map),
-		.map = sys_rt_heap_map,
-		.heap = HEAP_SYS_RUNTIME_BASE,
-		.size = HEAP_SYS_RUNTIME_SIZE,
-		.info = {.free = HEAP_SYS_RUNTIME_SIZE,},
-		.caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_CACHE |
-			SOF_MEM_CAPS_DMA,
-	},
-	.runtime[0] = {
-		.blocks = ARRAY_SIZE(rt_heap_map),
-		.map = rt_heap_map,
-		.heap = HEAP_RUNTIME_BASE,
-		.size = HEAP_RUNTIME_SIZE,
-		.info = {.free = HEAP_RUNTIME_SIZE,},
-		.caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_CACHE |
-			SOF_MEM_CAPS_DMA,
-	},
-	.buffer[0] = {
-		.blocks = ARRAY_SIZE(buf_heap_map),
-		.map = buf_heap_map,
-		.heap = HEAP_BUFFER_BASE,
-		.size = HEAP_BUFFER_SIZE,
-		.info = {.free = HEAP_BUFFER_SIZE,},
-		.caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_CACHE |
-			SOF_MEM_CAPS_DMA,
-	},
-	.total = {.free = HEAP_SYSTEM_SIZE + HEAP_SYS_RUNTIME_SIZE +
-			HEAP_RUNTIME_SIZE + HEAP_BUFFER_SIZE,},
-};
-
-void platform_init_memmap(struct sof *sof)
-{
-	/* memmap has been initialized statically as a part of .data */
-	sof->memory_map = &memmap;
-}
diff --git a/src/platform/mt8365/mt8365.x.in b/src/platform/mt8365/mt8365.x.in
deleted file mode 100644
index fdf588d33e4f..000000000000
--- a/src/platform/mt8365/mt8365.x.in
+++ /dev/null
@@ -1,492 +0,0 @@
-/*
- * Linker Script for mt8365 MediaTek
- *
- * This script is run through the GNU C preprocessor to align the memory
- * offsets with headers.
- *
- * Use spaces for formatting as cpp ignore tab sizes.
- */
-
-#include <sof/lib/memory.h>
-#include <xtensa/config/core-isa.h>
-
-OUTPUT_ARCH(xtensa)
-
-MEMORY
-{
-  vector_reset_text :
-        org = XCHAL_RESET_VECTOR0_PADDR,
-        len = SOF_MEM_RESET_TEXT_SIZE
-  vector_reset_lit :
-        org = XCHAL_RESET_VECTOR0_PADDR + SOF_MEM_RESET_TEXT_SIZE,
-        len = SOF_MEM_RESET_LIT_SIZE
-  vector_base_text :
-        org = XCHAL_VECBASE_RESET_PADDR,
-        len = SOF_MEM_VECBASE_LIT_SIZE
-  vector_int2_lit :
-        org = XCHAL_INTLEVEL2_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
-        len = SOF_MEM_VECT_LIT_SIZE
-  vector_int2_text :
-        org = XCHAL_INTLEVEL2_VECTOR_PADDR,
-        len = SOF_MEM_VECT_TEXT_SIZE
-  vector_int3_lit :
-        org = XCHAL_INTLEVEL3_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
-        len = SOF_MEM_VECT_LIT_SIZE
-  vector_int3_text :
-        org = XCHAL_INTLEVEL3_VECTOR_PADDR,
-        len = SOF_MEM_VECT_TEXT_SIZE
-  vector_int4_lit :
-        org = XCHAL_INTLEVEL4_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
-        len = SOF_MEM_VECT_LIT_SIZE
-  vector_int4_text :
-        org = XCHAL_INTLEVEL4_VECTOR_PADDR,
-        len = SOF_MEM_VECT_TEXT_SIZE
-  vector_kernel_lit :
-        org = XCHAL_KERNEL_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
-        len = SOF_MEM_VECT_LIT_SIZE
-  vector_kernel_text :
-        org = XCHAL_KERNEL_VECTOR_PADDR,
-        len = SOF_MEM_VECT_TEXT_SIZE
-  vector_user_lit :
-        org = XCHAL_USER_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
-        len = SOF_MEM_VECT_LIT_SIZE
-  vector_user_text :
-        org = XCHAL_USER_VECTOR_PADDR,
-        len = SOF_MEM_VECT_TEXT_SIZE
-  vector_double_lit :
-        org = XCHAL_DOUBLEEXC_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
-        len = SOF_MEM_VECT_LIT_SIZE
-  vector_double_text :
-        org = XCHAL_DOUBLEEXC_VECTOR_PADDR,
-        len = SOF_MEM_VECT_TEXT_SIZE
-  sof_sram :
-        org = SRAM0_BASE,
-        len = SRAM0_SIZE
-  system_heap :
-        org = HEAP_SYSTEM_BASE,
-        len = HEAP_SYSTEM_SIZE
-  system_runtime_heap :
-        org = HEAP_SYS_RUNTIME_BASE,
-        len = HEAP_SYS_RUNTIME_SIZE
-  runtime_heap :
-        org = HEAP_RUNTIME_BASE,
-        len = HEAP_RUNTIME_SIZE
-  buffer_heap :
-        org = HEAP_BUFFER_BASE,
-        len = HEAP_BUFFER_SIZE
-  sof_stack :
-        org = SOF_STACK_END,
-        len = SOF_STACK_BASE - SOF_STACK_END
-  static_uuid_entries_seg (!ari) :
-        org = UUID_ENTRY_ELF_BASE,
-        len = UUID_ENTRY_ELF_SIZE
-  static_log_entries_seg (!ari) :
-        org = LOG_ENTRY_ELF_BASE,
-        len = LOG_ENTRY_ELF_SIZE
-  fw_metadata_seg (!ari) :
-        org = EXT_MANIFEST_ELF_BASE,
-        len = EXT_MANIFEST_ELF_SIZE
-}
-
-PHDRS
-{
-  vector_reset_text_phdr PT_LOAD;
-  vector_reset_lit_phdr PT_LOAD;
-  vector_base_text_phdr PT_LOAD;
-  vector_base_lit_phdr PT_LOAD;
-  vector_int2_text_phdr PT_LOAD;
-  vector_int2_lit_phdr PT_LOAD;
-  vector_int3_text_phdr PT_LOAD;
-  vector_int3_lit_phdr PT_LOAD;
-  vector_int4_text_phdr PT_LOAD;
-  vector_int4_lit_phdr PT_LOAD;
-  vector_kernel_text_phdr PT_LOAD;
-  vector_kernel_lit_phdr PT_LOAD;
-  vector_user_text_phdr PT_LOAD;
-  vector_user_lit_phdr PT_LOAD;
-  vector_double_text_phdr PT_LOAD;
-  vector_double_lit_phdr PT_LOAD;
-  sof_sram_phdr PT_LOAD;
-  system_heap_phdr PT_LOAD;
-  system_runtime_heap_phdr PT_LOAD;
-  runtime_heap_phdr PT_LOAD;
-  buffer_heap_phdr PT_LOAD;
-  sof_stack_phdr PT_LOAD;
-  static_uuid_entries_phdr PT_NOTE;
-  static_log_entries_phdr PT_NOTE;
-  metadata_entries_phdr PT_NOTE;
-}
-
-/*  Default entry point:  */
-ENTRY(_ResetVector)
-_rom_store_table = 0;
-
-/* ABI0 does not use Window base */
-PROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR);
-
-/* Various memory-map dependent cache attribute settings: */
-_memmap_cacheattr_wb_base = 0x00000100;
-_memmap_cacheattr_wt_base = 0x00000300;
-_memmap_cacheattr_bp_base = 0x00000400;
-_memmap_cacheattr_unused_mask = 0xFFFFF0FF;
-_memmap_cacheattr_wb_trapnull = 0x44444140;
-_memmap_cacheattr_wba_trapnull = 0x44444140;
-_memmap_cacheattr_wbna_trapnull = 0x44444240;
-_memmap_cacheattr_wt_trapnull = 0x44444340;
-_memmap_cacheattr_bp_trapnull = 0x44444440;
-_memmap_cacheattr_wb_strict = 0x00000100;
-_memmap_cacheattr_wt_strict = 0x00000300;
-_memmap_cacheattr_bp_strict = 0x00000400;
-_memmap_cacheattr_wb_allvalid = 0x44444144;
-_memmap_cacheattr_wt_allvalid = 0x44444344;
-_memmap_cacheattr_bp_allvalid = 0x44444444;
-PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);
-
-_EXT_MAN_ALIGN_ = 16;
-EXTERN(ext_man_fw_ver)
-
-SECTIONS
-{
-  .ResetVector.text : ALIGN(4)
-  {
-    _ResetVector_text_start = ABSOLUTE(.);
-    KEEP (*(.ResetVector.text))
-    _ResetVector_text_end = ABSOLUTE(.);
-  } >vector_reset_text :vector_reset_text_phdr
-
-  .ResetVector.literal : ALIGN(4)
-  {
-    _ResetVector_literal_start = ABSOLUTE(.);
-    *(.ResetVector.literal)
-    _ResetVector_literal_end = ABSOLUTE(.);
-  } >vector_reset_lit :vector_reset_lit_phdr
-
-  .WindowVectors.text : ALIGN(4)
-  {
-    _WindowVectors_text_start = ABSOLUTE(.);
-    KEEP (*(.WindowVectors.text))
-    _WindowVectors_text_end = ABSOLUTE(.);
-  } >vector_base_text :vector_base_text_phdr
-
-  .Level2InterruptVector.literal : ALIGN(4)
-  {
-    _Level2InterruptVector_literal_start = ABSOLUTE(.);
-    *(.Level2InterruptVector.literal)
-    _Level2InterruptVector_literal_end = ABSOLUTE(.);
-  } >vector_int2_lit :vector_int2_lit_phdr
-
-  .Level2InterruptVector.text : ALIGN(4)
-  {
-    _Level2InterruptVector_text_start = ABSOLUTE(.);
-    KEEP (*(.Level2InterruptVector.text))
-    _Level2InterruptVector_text_end = ABSOLUTE(.);
-  } >vector_int2_text :vector_int2_text_phdr
-
-  .Level3InterruptVector.literal : ALIGN(4)
-  {
-    _Level3InterruptVector_literal_start = ABSOLUTE(.);
-    *(.Level3InterruptVector.literal)
-    _Level3InterruptVector_literal_end = ABSOLUTE(.);
-  } >vector_int3_lit :vector_int3_lit_phdr
-
-  .Level3InterruptVector.text : ALIGN(4)
-  {
-    _Level3InterruptVector_text_start = ABSOLUTE(.);
-    KEEP (*(.Level3InterruptVector.text))
-    _Level3InterruptVector_text_end = ABSOLUTE(.);
-  } >vector_int3_text :vector_int3_text_phdr
-
-  .DebugExceptionVector.literal : ALIGN(4)
-  {
-    _DebugExceptionVector_literal_start = ABSOLUTE(.);
-    *(.DebugExceptionVector.literal)
-    _DebugExceptionVector_literal_end = ABSOLUTE(.);
-  } >vector_int4_lit :vector_int4_lit_phdr
-
-  .DebugExceptionVector.text : ALIGN(4)
-  {
-    _DebugExceptionVector_text_start = ABSOLUTE(.);
-    KEEP (*(.DebugExceptionVector.text))
-    _DebugExceptionVector_text_end = ABSOLUTE(.);
-  } >vector_int4_text :vector_int4_text_phdr
-
-  .KernelExceptionVector.literal : ALIGN(4)
-  {
-    _KernelExceptionVector_literal_start = ABSOLUTE(.);
-    *(.KernelExceptionVector.literal)
-    _KernelExceptionVector_literal_end = ABSOLUTE(.);
-  } >vector_kernel_lit :vector_kernel_lit_phdr
-
-  .KernelExceptionVector.text : ALIGN(4)
-  {
-    _KernelExceptionVector_text_start = ABSOLUTE(.);
-    KEEP (*(.KernelExceptionVector.text))
-    _KernelExceptionVector_text_end = ABSOLUTE(.);
-  } >vector_kernel_text :vector_kernel_text_phdr
-
-  .UserExceptionVector.literal : ALIGN(4)
-  {
-    _UserExceptionVector_literal_start = ABSOLUTE(.);
-    *(.UserExceptionVector.literal)
-    _UserExceptionVector_literal_end = ABSOLUTE(.);
-  } >vector_user_lit :vector_user_lit_phdr
-
-  .UserExceptionVector.text : ALIGN(4)
-  {
-    _UserExceptionVector_text_start = ABSOLUTE(.);
-    KEEP (*(.UserExceptionVector.text))
-    _UserExceptionVector_text_end = ABSOLUTE(.);
-  } >vector_user_text :vector_user_text_phdr
-
-  .DoubleExceptionVector.literal : ALIGN(4)
-  {
-    _DoubleExceptionVector_literal_start = ABSOLUTE(.);
-    *(.DoubleExceptionVector.literal)
-    _DoubleExceptionVector_literal_end = ABSOLUTE(.);
-  } >vector_double_lit :vector_double_lit_phdr
-
-  .DoubleExceptionVector.text : ALIGN(4)
-  {
-    _DoubleExceptionVector_text_start = ABSOLUTE(.);
-    KEEP (*(.DoubleExceptionVector.text))
-    _DoubleExceptionVector_text_end = ABSOLUTE(.);
-  } >vector_double_text :vector_double_text_phdr
-
-  .fw_ready : ALIGN(4)
-  {
-    KEEP (*(.fw_ready))
-    KEEP (*(.fw_ready_metadata))
-  } >sof_sram :sof_sram_phdr
-
-  .rodata : ALIGN(4)
-  {
-    _rodata_start = ABSOLUTE(.);
-    *(.rodata)
-    *(.rodata.*)
-    *(.gnu.linkonce.r.*)
-    *(.rodata1)
-    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);
-    KEEP (*(.xt_except_table))
-    KEEP (*(.gcc_except_table))
-    *(.gnu.linkonce.e.*)
-    *(.gnu.version_r)
-    KEEP (*(.eh_frame))
-    /*  C++ constructor and destructor tables, properly ordered:  */
-    KEEP (*crtbegin.o(.ctors))
-    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
-    KEEP (*(SORT(.ctors.*)))
-    KEEP (*(.ctors))
-    KEEP (*crtbegin.o(.dtors))
-    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
-    KEEP (*(SORT(.dtors.*)))
-    KEEP (*(.dtors))
-    /*  C++ exception handlers table:  */
-    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);
-    *(.xt_except_desc)
-    *(.gnu.linkonce.h.*)
-    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
-    *(.xt_except_desc_end)
-    *(.dynamic)
-    *(.gnu.version_d)
-    . = ALIGN(4);		/* this table MUST be 4-byte aligned */
-    _bss_table_start = ABSOLUTE(.);
-    LONG(_bss_start)
-    LONG(_bss_end)
-    _bss_table_end = ABSOLUTE(.);
-    _rodata_end = ABSOLUTE(.);
-  } >sof_sram :sof_sram_phdr
-
-  .module_init : ALIGN(4)
-  {
-   _module_init_start = ABSOLUTE(.);
-    *(*.initcall)
-    _module_init_end = ABSOLUTE(.);
-  } >sof_sram :sof_sram_phdr
-
-  .text : ALIGN(4)
-  {
-    _stext = .;
-    _text_start = ABSOLUTE(.);
-    *(.entry.text)
-    *(.init.literal)
-    KEEP(*(.init))
-    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
-    *(.fini.literal)
-    KEEP(*(.fini))
-    *(.gnu.version)
-    _text_end = ABSOLUTE(.);
-    _etext = .;
-  } >sof_sram :sof_sram_phdr
-
-  .reset.rodata : ALIGN(4)
-  {
-    _reset_rodata_start = ABSOLUTE(.);
-    *(.reset.rodata)
-    _reset_rodata_end = ABSOLUTE(.);
-  } >sof_sram :sof_sram_phdr
-
-
-  .data : ALIGN(4)
-  {
-    _data_start = ABSOLUTE(.);
-    *(.data)
-    *(.data.*)
-    *(.gnu.linkonce.d.*)
-    KEEP(*(.gnu.linkonce.d.*personality*))
-    *(.data1)
-    *(.sdata)
-    *(.sdata.*)
-    *(.gnu.linkonce.s.*)
-    *(.sdata2)
-    *(.sdata2.*)
-    *(.gnu.linkonce.s2.*)
-    KEEP(*(.jcr))
-    _trace_ctx_start = ABSOLUTE(.);
-    *(.trace_ctx)
-    _trace_ctx_end = ABSOLUTE(.);
-    _data_end = ABSOLUTE(.);
-  } >sof_sram :sof_sram_phdr
-
-  .lit4 : ALIGN(4)
-  {
-    _lit4_start = ABSOLUTE(.);
-    *(*.lit4)
-    *(.lit4.*)
-    *(.gnu.linkonce.lit4.*)
-    _lit4_end = ABSOLUTE(.);
-  } >sof_sram :sof_sram_phdr
-
-  .bss (NOLOAD) : ALIGN(8)
-  {
-    . = ALIGN (8);
-    _bss_start = ABSOLUTE(.);
-    *(.dynsbss)
-    *(.sbss)
-    *(.sbss.*)
-    *(.gnu.linkonce.sb.*)
-    *(.scommon)
-    *(.sbss2)
-    *(.sbss2.*)
-    *(.gnu.linkonce.sb2.*)
-    *(.dynbss)
-    *(.bss)
-    *(.bss.*)
-    *(.gnu.linkonce.b.*)
-    *(COMMON)
-    . = ALIGN (8);
-    _bss_end = ABSOLUTE(.);
-  } >sof_sram :sof_sram_phdr
-
-  /* stack */
-  _end = SOF_STACK_END;
-  PROVIDE(end = SOF_STACK_END);
-  _stack_sentry = SOF_STACK_END;
-  __stack = SOF_STACK_BASE;
-
-  .debug  0 :  { *(.debug) }
-  .line  0 :  { *(.line) }
-  .debug_srcinfo  0 :  { *(.debug_srcinfo) }
-  .debug_sfnames  0 :  { *(.debug_sfnames) }
-  .debug_aranges  0 :  { *(.debug_aranges) }
-  .debug_pubnames  0 :  { *(.debug_pubnames) }
-  .debug_info  0 :  { *(.debug_info) }
-  .debug_abbrev  0 :  { *(.debug_abbrev) }
-  .debug_line  0 :  { *(.debug_line) }
-  .debug_frame  0 :  { *(.debug_frame) }
-  .debug_str  0 :  { *(.debug_str) }
-  .debug_loc  0 :  { *(.debug_loc) }
-  .debug_macinfo  0 :  { *(.debug_macinfo) }
-  .debug_weaknames  0 :  { *(.debug_weaknames) }
-  .debug_funcnames  0 :  { *(.debug_funcnames) }
-  .debug_typenames  0 :  { *(.debug_typenames) }
-  .debug_varnames  0 :  { *(.debug_varnames) }
-
-  .xt.insn 0 :
-  {
-    KEEP (*(.xt.insn))
-    KEEP (*(.gnu.linkonce.x.*))
-  }
-  .xt.prop 0 :
-  {
-    KEEP (*(.xt.prop))
-    KEEP (*(.xt.prop.*))
-    KEEP (*(.gnu.linkonce.prop.*))
-  }
-  .xt.lit 0 :
-  {
-    KEEP (*(.xt.lit))
-    KEEP (*(.xt.lit.*))
-    KEEP (*(.gnu.linkonce.p.*))
-  }
-  .xt.profile_range 0 :
-  {
-    KEEP (*(.xt.profile_range))
-    KEEP (*(.gnu.linkonce.profile_range.*))
-  }
-  .xt.profile_ranges 0 :
-  {
-    KEEP (*(.xt.profile_ranges))
-    KEEP (*(.gnu.linkonce.xt.profile_ranges.*))
-  }
-  .xt.profile_files 0 :
-  {
-    KEEP (*(.xt.profile_files))
-    KEEP (*(.gnu.linkonce.xt.profile_files.*))
-  }
-
-  .system_heap (NOLOAD) : ALIGN(8)
-  {
-    . = ALIGN (32);
-    _system_heap_start = ABSOLUTE(.);
-    . = . + HEAP_SYSTEM_SIZE;
-    _system_heap_end = ABSOLUTE(.);
-  } >system_heap :system_heap_phdr
-
-  .system_runtime_heap (NOLOAD) : ALIGN(8)
-  {
-    . = ALIGN (HEAP_BUF_ALIGNMENT);
-    _system_runtime_heap_start = ABSOLUTE(.);
-    . = . + HEAP_SYS_RUNTIME_SIZE;
-    _system_runtime_heap_end = ABSOLUTE(.);
-  } >system_runtime_heap :system_runtime_heap_phdr
-
-  .runtime_heap (NOLOAD) : ALIGN(8)
-  {
-    . = ALIGN (32);
-    _runtime_heap_start = ABSOLUTE(.);
-    . = . + HEAP_RUNTIME_SIZE;
-    _runtime_heap_end = ABSOLUTE(.);
-  } >runtime_heap :runtime_heap_phdr
-
-  .buffer_heap (NOLOAD) : ALIGN(8)
-  {
-    . = ALIGN (HEAP_BUF_ALIGNMENT);
-    _buffer_heap_start = ABSOLUTE(.);
-    . = . + HEAP_BUFFER_SIZE;
-    _buffer_heap_end = ABSOLUTE(.);
-  } >buffer_heap :buffer_heap_phdr
-
-  .sof_stack (NOLOAD) : ALIGN(8)
-  {
-    . = ALIGN (4096);
-    _sof_stack_start = ABSOLUTE(.);
-    . = . + SOF_STACK_TOTAL_SIZE;
-    _sof_stack_end = ABSOLUTE(.);
-  } >sof_stack :sof_stack_phdr
-
-  .static_uuid_entries (COPY) : ALIGN(1024)
-  {
-    *(*.static_uuids)
-  } > static_uuid_entries_seg :static_uuid_entries_phdr
-
-  .static_log_entries (COPY) : ALIGN(1024)
-  {
-    *(*.static_log*)
-  } > static_log_entries_seg :static_log_entries_phdr
-
-  .fw_metadata (COPY) : ALIGN(1024)
-  {
-    KEEP (*(.fw_metadata))
-    . = ALIGN(_EXT_MAN_ALIGN_);
-  } >fw_metadata_seg :metadata_entries_phdr
-}
diff --git a/src/platform/mt8365/platform.c b/src/platform/mt8365/platform.c
deleted file mode 100644
index 93e617cdebbf..000000000000
--- a/src/platform/mt8365/platform.c
+++ /dev/null
@@ -1,221 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-/*
- * Copyright(c) 2024 MediaTek. All rights reserved.
- *
- * Author: Andrew Perepech <andrew.perepech@mediatek.com>
- */
-
-#include <errno.h>
-#include <ipc/dai.h>
-#include <ipc/header.h>
-#include <ipc/info.h>
-#include <kernel/abi.h>
-#include <kernel/ext_manifest.h>
-#include <platform/drivers/timer.h>
-#include <rtos/clk.h>
-#include <rtos/timer.h>
-#include <rtos/interrupt.h>
-#include <sof/compiler_info.h>
-#include <sof/debug/debug.h>
-#include <sof/drivers/edma.h>
-#include <sof/ipc/msg.h>
-#include <sof/fw-ready-metadata.h>
-#include <sof/lib/agent.h>
-#include <sof/lib/cpu.h>
-#include <sof/lib/dai.h>
-#include <sof/lib/dma.h>
-#include <sof/lib/mailbox.h>
-#include <sof/lib/memory.h>
-#include <sof/lib/mm_heap.h>
-#include <sof/platform.h>
-#include <sof/schedule/edf_schedule.h>
-#include <sof/schedule/ll_schedule.h>
-#include <sof/schedule/ll_schedule_domain.h>
-#include <rtos/sof.h>
-#include <sof/trace/dma-trace.h>
-#include <sof_versions.h>
-#include <stdint.h>
-#include <xtensa/hal.h>
-
-struct sof;
-
-static const struct sof_ipc_fw_ready ready
-	__section(".fw_ready") = {
-	.hdr = {
-		.cmd = SOF_IPC_FW_READY,
-		.size = sizeof(struct sof_ipc_fw_ready),
-	},
-	/* dspbox is for DSP initiated IPC, hostbox is for host initiated IPC */
-	.version = {
-		.hdr.size = sizeof(struct sof_ipc_fw_version),
-		.micro = SOF_MICRO,
-		.minor = SOF_MINOR,
-		.major = SOF_MAJOR,
-		.tag = SOF_TAG,
-		.abi_version = SOF_ABI_VERSION,
-		.src_hash = SOF_SRC_HASH,
-	},
-	.flags = DEBUG_SET_FW_READY_FLAGS,
-};
-
-#define NUM_MTK_WINDOWS 6
-
-const struct ext_man_windows xsram_window
-		__aligned(EXT_MAN_ALIGN) __section(".fw_metadata") __unused = {
-	.hdr = {
-		.type = EXT_MAN_ELEM_WINDOW,
-		.elem_size = ALIGN_UP_COMPILE(sizeof(struct ext_man_windows), EXT_MAN_ALIGN),
-	},
-	.window = {
-		.ext_hdr	= {
-			.hdr.cmd = SOF_IPC_FW_READY,
-			.hdr.size = sizeof(struct sof_ipc_window),
-			.type	= SOF_IPC_EXT_WINDOW,
-		},
-		.num_windows	= NUM_MTK_WINDOWS,
-		.window	= {
-			{
-				.type	= SOF_IPC_REGION_UPBOX,
-				.id	= 0,	/* map to host window 0 */
-				.flags	= 0,
-				.size	= MAILBOX_DSPBOX_SIZE,
-				.offset	= MAILBOX_DSPBOX_OFFSET,
-			},
-			{
-				.type	= SOF_IPC_REGION_DOWNBOX,
-				.id	= 0,	/* map to host window 0 */
-				.flags	= 0,
-				.size	= MAILBOX_HOSTBOX_SIZE,
-				.offset	= MAILBOX_HOSTBOX_OFFSET,
-			},
-			{
-				.type	= SOF_IPC_REGION_DEBUG,
-				.id	= 0,	/* map to host window 0 */
-				.flags	= 0,
-				.size	= MAILBOX_DEBUG_SIZE,
-				.offset	= MAILBOX_DEBUG_OFFSET,
-			},
-			{
-				.type	= SOF_IPC_REGION_TRACE,
-				.id	= 0,	/* map to host window 0 */
-				.flags	= 0,
-				.size	= MAILBOX_TRACE_SIZE,
-				.offset	= MAILBOX_TRACE_OFFSET,
-			},
-			{
-				.type	= SOF_IPC_REGION_STREAM,
-				.id	= 0,	/* map to host window 0 */
-				.flags	= 0,
-				.size	= MAILBOX_STREAM_SIZE,
-				.offset	= MAILBOX_STREAM_OFFSET,
-			},
-			{
-				.type	= SOF_IPC_REGION_EXCEPTION,
-				.id	= 0,	/* map to host window 0 */
-				.flags	= 0,
-				.size	= MAILBOX_EXCEPTION_SIZE,
-				.offset	= MAILBOX_EXCEPTION_OFFSET,
-			},
-		},
-	}
-};
-
-static struct timer timer_shared = {
-	.id = OSTIMER0,
-	.irq = SYSTICK_TIMER_IRQ,
-};
-
-/* Override the default MPU setup. This table matches the memory map
- * of the 'sample_controller' core and will need to be modified for
- * other cores.
- * NOTE: This table sets up all of external memory as shared uncached.
- * For best results, edit the LSP memory map to create a separate
- * section in shared memory, place all sections that need to be uncached
- * into that section, and only map that section uncached. See README
- * for more details.
- */
-const struct xthal_MPU_entry __xt_mpu_init_table[] __section(".ResetVector.text") = {
-	XTHAL_MPU_ENTRY(0x00000000, 1, XTHAL_AR_RWXrwx, XTHAL_MEM_DEVICE),		// infra
-	XTHAL_MPU_ENTRY(0x40020000, 1, XTHAL_AR_RWXrwx, XTHAL_MEM_WRITEBACK),		// vectors
-	XTHAL_MPU_ENTRY(0x40060000, 1, XTHAL_AR_NONE, XTHAL_MEM_DEVICE),		// unused
-	XTHAL_MPU_ENTRY(0x60000000, 1, XTHAL_AR_RWXrwx, XTHAL_MEM_WRITEBACK),		// DSP FW
-	XTHAL_MPU_ENTRY(0x60800000, 1, XTHAL_AR_RWXrwx, XTHAL_MEM_NON_CACHEABLE),	// shared
-	XTHAL_MPU_ENTRY(0x61000000, 1, XTHAL_AR_NONE, XTHAL_MEM_DEVICE),		// unused
-};
-
-const unsigned int __xt_mpu_init_table_size __section(".ResetVector.text") =
-	ARRAY_SIZE(__xt_mpu_init_table);
-
-int platform_boot_complete(uint32_t boot_message)
-{
-	mailbox_dspbox_write(0, &ready, sizeof(ready));
-
-	/* now interrupt host to tell it we are done booting */
-	trigger_irq_to_host_req();
-
-	return 0;
-}
-
-int platform_init(struct sof *sof)
-{
-	int ret;
-
-	mailbox_sw_reg_write(SRAM_REG_FW_STATUS, 0);
-	mailbox_sw_reg_write(SRAM_REG_OP_CPU2DSP, 0);
-	mailbox_sw_reg_write(SRAM_REG_OP_DSP2CPU, 0);
-
-	sof->platform_timer = &timer_shared;
-	sof->cpu_timers = sof->platform_timer;
-
-	platform_interrupt_init();
-	platform_clock_init(sof);
-
-	scheduler_init_edf();
-
-	/* init low latency domains and schedulers */
-	sof->platform_timer_domain = timer_domain_init(sof->platform_timer, PLATFORM_DEFAULT_CLOCK);
-	scheduler_init_ll(sof->platform_timer_domain);
-
-	platform_timer_start(sof->platform_timer);
-	sa_init(sof, CONFIG_SYSTICK_PERIOD);
-
-	/* init DMA */
-	ret = dmac_init(sof);
-	if (ret < 0)
-		return -ENODEV;
-
-	/* Init platform domain */
-	sof->platform_dma_domain = dma_multi_chan_domain_init(&sof->dma_info->dma_array[0], 1,
-							      PLATFORM_DEFAULT_CLOCK, false);
-	scheduler_init_ll(sof->platform_dma_domain);
-
-	/* initialize the host IPC mechanims */
-	ipc_init(sof);
-
-	ret = dai_init(sof);
-	if (ret < 0)
-		return ret;
-
-#if CONFIG_TRACE
-	/* Initialize DMA for Trace*/
-	trace_point(TRACE_BOOT_PLATFORM_DMA_TRACE);
-	dma_trace_init_complete(sof->dmat);
-#endif
-
-	/* show heap status */
-	heap_trace_all(1);
-
-	return 0;
-}
-
-int platform_context_save(struct sof *sof)
-{
-	clock_set_freq(CLK_CPU(cpu_get_id()), CLK_DEFAULT_CPU_HZ);
-	return 0;
-}
-
-void platform_wait_for_interrupt(int level)
-{
-	arch_wait_for_interrupt(level);
-}
-
diff --git a/src/platform/posix/base_fw_platform.c b/src/platform/posix/base_fw_platform.c
deleted file mode 100644
index 79bf0d9b33ca..000000000000
--- a/src/platform/posix/base_fw_platform.c
+++ /dev/null
@@ -1,58 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-//
-// Copyright(c) 2024 Intel Corporation.
-//
-// Author: Kai Vehmanen <kai.vehmanen@linux.intel.com>
-
-#include <stdint.h>
-#include <stddef.h>
-#include <ipc4/error_status.h>
-#include <ipc4/base_fw_platform.h>
-
-int platform_basefw_fw_config(uint32_t *data_offset, char *data)
-{
-	*data_offset = 0;
-
-	return 0;
-}
-
-int platform_basefw_hw_config(uint32_t *data_offset, char *data)
-{
-	*data_offset = 0;
-
-	return 0;
-}
-
-struct sof_man_fw_desc *platform_base_fw_get_manifest(void)
-{
-	struct sof_man_fw_desc *desc = NULL;
-
-	return desc;
-}
-
-int platform_basefw_modules_info_get(uint32_t *data_offset, char *data)
-{
-	*data_offset = 0;
-
-	return 0;
-}
-
-int platform_basefw_get_large_config(struct comp_dev *dev,
-				     uint32_t param_id,
-				     bool first_block,
-				     bool last_block,
-				     uint32_t *data_offset,
-				     char *data)
-{
-	return -EINVAL;
-}
-
-int platform_basefw_set_large_config(struct comp_dev *dev,
-				     uint32_t param_id,
-				     bool first_block,
-				     bool last_block,
-				     uint32_t data_offset,
-				     const char *data)
-{
-	return IPC4_UNKNOWN_MESSAGE_TYPE;
-}
diff --git a/src/platform/qemu_xtensa/CMakeLists.txt b/src/platform/qemu_xtensa/CMakeLists.txt
deleted file mode 100644
index 8688947cf0c6..000000000000
--- a/src/platform/qemu_xtensa/CMakeLists.txt
+++ /dev/null
@@ -1,3 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-
-add_local_sources(sof platform.c)
diff --git a/test/cmocka/CMakeLists.txt b/test/cmocka/CMakeLists.txt
index 5e3591df6a61..288282d11457 100644
--- a/test/cmocka/CMakeLists.txt
+++ b/test/cmocka/CMakeLists.txt
@@ -4,24 +4,9 @@ include(ExternalProject)
 
 add_library(cmocka STATIC IMPORTED)
 
-# Default use XCC unless user asks for GCC
-if(BUILD_UNIT_TESTS_HOST)
-	set(UT_CC_CONFIG ${CMAKE_CURRENT_SOURCE_DIR}/cmocka-host-gcc-toolchain.cmake)
-	set(UT_TOOLCHAIN "")
-	# TODO: add an option to support valgrind.
-	# In the mean time use scripts/run-mocks.sh for valgrind.
-	set(SIMULATOR "")
-elseif(BUILD_UNIT_TESTS_XTENSA_GCC)
-	# GCC xtensa build for future Qemu.
-	set(UT_CC_CONFIG ${CMAKE_CURRENT_SOURCE_DIR}/cmocka-xtensa-gcc-toolchain.cmake)
-	set(UT_TOOLCHAIN "-DTOOLCHAIN=${TOOLCHAIN}")
-	set(SIMULATOR xt-run --exit_with_target_code)
-else()
-	# xtensa XCC build for xt-run.
-	set(UT_CC_CONFIG ${CMAKE_CURRENT_SOURCE_DIR}/cmocka-xtensa-xt-toolchain.cmake)
-	set(UT_TOOLCHAIN "")
-	set(SIMULATOR xt-run --exit_with_target_code)
-endif()
+# TODO: add an option to support valgrind.
+# In the mean time use scripts/run-mocks.sh for valgrind.
+set(UT_CC_CONFIG ${CMAKE_CURRENT_SOURCE_DIR}/cmocka-host-gcc-toolchain.cmake)
 
 if(DEFINED CMOCKA_DIRECTORY)
 	# Prebuilt Cmocka lib
@@ -44,7 +29,6 @@ else()
 			-DWITH_EXAMPLES=OFF
 			-DWITH_POSITION_INDEPENDENT_CODE=OFF
 			-DWITH_TINY_CONFIG=ON
-			${UT_TOOLCHAIN}
 		BUILD_BYPRODUCTS "${cmocka_binary_directory}/src/libcmocka-static.a"
 		INSTALL_COMMAND ""
 	)
@@ -62,7 +46,6 @@ if(CONFIG_CAVS)
 elseif(CONFIG_ACE)
 	target_include_directories(sof_options INTERFACE ${PROJECT_SOURCE_DIR}/src/platform/intel/ace/include)
 endif()
-target_include_directories(sof_options INTERFACE ${PROJECT_SOURCE_DIR}/src/arch/xtos-wrapper/include)
 
 # linker script, just for log entries
 set(memory_mock_lds_in ${PROJECT_SOURCE_DIR}/test/cmocka/memory_mock.x.in)
@@ -78,19 +61,11 @@ add_custom_command(OUTPUT ${memory_mock_lds_out}
 )
 
 add_custom_target(ld_script_memory_mock DEPENDS ${memory_mock_lds_out})
-SET(arch_src ${PROJECT_SOURCE_DIR}/src/arch/xtensa/idc.c)
 add_library(common_mock STATIC ${PROJECT_SOURCE_DIR}/test/cmocka/src/common_mocks.c)
 add_dependencies(common_mock cmocka)
 target_include_directories(common_mock PRIVATE ${CMOCKA_INCLUDE_DIR})
 target_link_libraries(common_mock PRIVATE sof_options)
 target_link_libraries(common_mock PRIVATE m)
-
-# xtensa GCC require some extra options to link
-if(BUILD_UNIT_TESTS_XTENSA_GCC)
-	target_link_libraries(common_mock PRIVATE gcc)
-	target_link_libraries(common_mock PRIVATE c)
-	target_link_libraries(common_mock PRIVATE -nostdlib)
-endif()
 link_libraries(common_mock)
 sof_append_relative_path_definitions(common_mock)
 
@@ -113,12 +88,11 @@ function(cmocka_test test_name)
 	# Enable features those would be disabled in some platforms
 	target_compile_definitions(${test_name} PRIVATE -DCONFIG_NUMBERS_NORM -DCONFIG_NUMBERS_VECTOR_FIND)
 
-	# Skip running alloc test on HOST until it's fixed (it passes and is run
-	# with xt-run)
-	if( "alloc" STREQUAL "${test_name}" AND BUILD_UNIT_TESTS_HOST)
+	# Skip running alloc test until it's fixed on the host
+	if( "alloc" STREQUAL "${test_name}")
 		message(WARNING "SKIP alloc test on HOST, built but not run")
 	else()
-		add_test(NAME ${test_name} COMMAND ${SIMULATOR} ${test_name})
+		add_test(NAME ${test_name} COMMAND ${test_name})
 	endif()
 
 	sof_append_relative_path_definitions(${test_name})
diff --git a/test/cmocka/cmocka-xtensa-gcc-toolchain.cmake b/test/cmocka/cmocka-xtensa-gcc-toolchain.cmake
deleted file mode 100644
index 32183a37c82f..000000000000
--- a/test/cmocka/cmocka-xtensa-gcc-toolchain.cmake
+++ /dev/null
@@ -1,33 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-
-message(STATUS "Preparing Xtensa GCC toolchain using ${TOOLCHAIN}")
-
-set(CROSS_COMPILE "${TOOLCHAIN}-")
-
-set(CMAKE_SYSTEM_NAME Generic)
-set(CMAKE_SYSTEM_VERSION 1)
-
-set(CMAKE_ASM_COMPILER_FORCED 1)
-set(CMAKE_C_COMPILER_FORCED 1)
-
-set(CMAKE_ASM_COMPILER_ID GNU)
-set(CMAKE_C_COMPILER_ID GNU)
-
-set(CMAKE_C_COMPILER 	${CROSS_COMPILE}gcc)
-
-# required for checking flags
-set(CMAKE_REQUIRED_FLAGS "-nostdlib")
-
-find_program(CMAKE_LD NAMES "${CROSS_COMPILE}ld" PATHS ENV PATH NO_DEFAULT_PATH)
-find_program(CMAKE_AR NAMES "${CROSS_COMPILE}ar" PATHS ENV PATH NO_DEFAULT_PATH)
-find_program(CMAKE_OBJCOPY NAMES "${CROSS_COMPILE}objcopy" PATHS ENV PATH NO_DEFAULT_PATH)
-find_program(CMAKE_OBJDUMP NAMES "${CROSS_COMPILE}objdump" PATHS ENV PATH NO_DEFAULT_PATH)
-
-set(CMAKE_FIND_ROOT_PATH  ".")
-set(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER)
-set(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY)
-set(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY)
-
-# Cmocka is written in C99, but for some reason it sets this flag, only on Posix
-# We set up it here, because our system is Generic
-add_definitions("-std=gnu99")
diff --git a/test/cmocka/cmocka-xtensa-xt-toolchain.cmake b/test/cmocka/cmocka-xtensa-xt-toolchain.cmake
deleted file mode 100644
index 81e869aa9e4a..000000000000
--- a/test/cmocka/cmocka-xtensa-xt-toolchain.cmake
+++ /dev/null
@@ -1,30 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-
-message(STATUS "Preparing Xtensa toolchain")
-
-set(CMAKE_SYSTEM_NAME Generic)
-set(CMAKE_SYSTEM_VERSION 1)
-
-set(CMAKE_ASM_COMPILER_FORCED 1)
-set(CMAKE_C_COMPILER_FORCED 1)
-
-set(CMAKE_ASM_COMPILER_ID GNU)
-set(CMAKE_C_COMPILER_ID GNU)
-
-set(CROSS_COMPILE "xt-")
-
-set(CMAKE_C_COMPILER 	${CROSS_COMPILE}xcc)
-
-find_program(CMAKE_LD NAMES "${CROSS_COMPILE}ld" PATHS ENV PATH NO_DEFAULT_PATH)
-find_program(CMAKE_AR NAMES "${CROSS_COMPILE}ar" PATHS ENV PATH NO_DEFAULT_PATH)
-find_program(CMAKE_OBJCOPY NAMES "${CROSS_COMPILE}objcopy" PATHS ENV PATH NO_DEFAULT_PATH)
-find_program(CMAKE_OBJDUMP NAMES "${CROSS_COMPILE}objdump" PATHS ENV PATH NO_DEFAULT_PATH)
-
-set(CMAKE_FIND_ROOT_PATH  ".")
-set(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER)
-set(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY)
-set(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY)
-
-# Cmocka is written in C99, but for some reason it sets this flag, only on Posix
-# We set up it here, because our system is Generic
-add_definitions("-std=gnu99")
diff --git a/src/arch/xtensa/configs/acp_7_0_defconfig b/test/cmocka/configs/acp_7_0_defconfig
similarity index 100%
rename from src/arch/xtensa/configs/acp_7_0_defconfig
rename to test/cmocka/configs/acp_7_0_defconfig
diff --git a/src/arch/xtensa/configs/acp_7_x_defconfig b/test/cmocka/configs/acp_7_x_defconfig
similarity index 100%
rename from src/arch/xtensa/configs/acp_7_x_defconfig
rename to test/cmocka/configs/acp_7_x_defconfig
diff --git a/src/arch/xtensa/configs/imx8_defconfig b/test/cmocka/configs/imx8_defconfig
similarity index 100%
rename from src/arch/xtensa/configs/imx8_defconfig
rename to test/cmocka/configs/imx8_defconfig
diff --git a/src/arch/xtensa/configs/imx8m_defconfig b/test/cmocka/configs/imx8m_defconfig
similarity index 100%
rename from src/arch/xtensa/configs/imx8m_defconfig
rename to test/cmocka/configs/imx8m_defconfig
diff --git a/src/arch/xtensa/configs/imx8ulp_defconfig b/test/cmocka/configs/imx8ulp_defconfig
similarity index 100%
rename from src/arch/xtensa/configs/imx8ulp_defconfig
rename to test/cmocka/configs/imx8ulp_defconfig
diff --git a/src/arch/xtensa/configs/imx8x_defconfig b/test/cmocka/configs/imx8x_defconfig
similarity index 100%
rename from src/arch/xtensa/configs/imx8x_defconfig
rename to test/cmocka/configs/imx8x_defconfig
diff --git a/src/arch/xtensa/configs/mt8188_defconfig b/test/cmocka/configs/mtk_defconfig
similarity index 93%
rename from src/arch/xtensa/configs/mt8188_defconfig
rename to test/cmocka/configs/mtk_defconfig
index b495a2e9a1f0..ec0da0f0114a 100644
--- a/src/arch/xtensa/configs/mt8188_defconfig
+++ b/test/cmocka/configs/mtk_defconfig
@@ -1,4 +1,4 @@
-CONFIG_MT8188=y
+CONFIG_MTK=y
 CONFIG_CORE_COUNT=1
 CONFIG_COMP_VOLUME=y
 CONFIG_COMP_SRC=n
@@ -12,3 +12,4 @@ CONFIG_COMP_MUX=n
 CONFIG_COMP_KPB=n
 CONFIG_COMP_SEL=n
 CONFIG_COMP_ASRC=n
+
diff --git a/src/arch/xtensa/configs/rembrandt_defconfig b/test/cmocka/configs/rembrandt_defconfig
similarity index 100%
rename from src/arch/xtensa/configs/rembrandt_defconfig
rename to test/cmocka/configs/rembrandt_defconfig
diff --git a/src/arch/xtensa/configs/unit_test_defconfig b/test/cmocka/configs/unit_test_defconfig
similarity index 100%
rename from src/arch/xtensa/configs/unit_test_defconfig
rename to test/cmocka/configs/unit_test_defconfig
diff --git a/test/cmocka/src/audio/pipeline/CMakeLists.txt b/test/cmocka/src/audio/pipeline/CMakeLists.txt
index 6ba4fecd4c97..feac1acf209d 100644
--- a/test/cmocka/src/audio/pipeline/CMakeLists.txt
+++ b/test/cmocka/src/audio/pipeline/CMakeLists.txt
@@ -1,22 +1,5 @@
 # SPDX-License-Identifier: BSD-3-Clause
 
-if(CONFIG_MULTICORE AND NOT BUILD_UNIT_TESTS_HOST)
-	SET(arch_src ${PROJECT_SOURCE_DIR}/src/drivers/intel/cavs/idc.c)
-
-	# make small lib for stripping so we don't have to care
-	# about unused missing references
-
-	add_compile_options(-fdata-sections -ffunction-sections)
-	link_libraries(-Wl,--gc-sections)
-
-	add_library(pipeline_lib STATIC ${arch_src})
-	sof_append_relative_path_definitions(pipeline_lib)
-
-	target_link_libraries(pipeline_lib PRIVATE sof_options)
-
-	link_libraries(pipeline_lib)
-endif()
-
 cmocka_test(pipeline_new
 	pipeline_new.c
 	${PROJECT_SOURCE_DIR}/src/math/numbers.c
diff --git a/test/cmocka/src/lib/alloc/CMakeLists.txt b/test/cmocka/src/lib/alloc/CMakeLists.txt
index c9ba91a9a1d7..2ec7c8f606db 100644
--- a/test/cmocka/src/lib/alloc/CMakeLists.txt
+++ b/test/cmocka/src/lib/alloc/CMakeLists.txt
@@ -1,21 +1,9 @@
 # SPDX-License-Identifier: BSD-3-Clause
 
-if(BUILD_UNIT_TESTS_HOST)
-	cmocka_test(alloc
-		alloc.c
-		${PROJECT_SOURCE_DIR}/src/lib/alloc.c
-		${PROJECT_SOURCE_DIR}/src/platform/library/lib/memory.c
-	)
-else()
-	if(CONFIG_CAVS)
-		set(MEMORY_FILE ${PROJECT_SOURCE_DIR}/src/platform/intel/cavs/lib/memory.c)
-	endif()
-	cmocka_test(alloc
-		alloc.c
-		${PROJECT_SOURCE_DIR}/src/lib/alloc.c
-		${PROJECT_SOURCE_DIR}/src/debug/panic.c
-		${MEMORY_FILE}
-	)
-endif()
+cmocka_test(alloc
+	alloc.c
+	${PROJECT_SOURCE_DIR}/src/lib/alloc.c
+	${PROJECT_SOURCE_DIR}/src/platform/library/lib/memory.c
+)
 
 target_include_directories(sof_options INTERFACE ${PROJECT_SOURCE_DIR}/src/platform/intel/cavs/include)
diff --git a/test/test-all-defconfigs.sh b/test/test-all-defconfigs.sh
index aaba127833b8..6060c8de194f 100755
--- a/test/test-all-defconfigs.sh
+++ b/test/test-all-defconfigs.sh
@@ -28,7 +28,7 @@ main()
     local defconfig
 
     # First make sure all configurations build
-    for d in "$SOFTOP"/src/arch/xtensa/configs/*_defconfig; do
+    for d in "$SOFTOP"/test/cmocka/configs/*_defconfig; do
         defconfig=$(basename "$d")
         rebuild_config "$defconfig"
     done
diff --git a/tools/logger/CMakeLists.txt b/tools/logger/CMakeLists.txt
index 8c15dd125739..0566752baaf7 100644
--- a/tools/logger/CMakeLists.txt
+++ b/tools/logger/CMakeLists.txt
@@ -43,9 +43,4 @@ target_include_directories(sof-logger PRIVATE
 	"${SOF_ROOT_SOURCE_DIRECTORY}"
 )
 
-# TODO: logger should not need to include RTOS headers. FIX.
-target_include_directories(sof-logger PRIVATE
-	"${SOF_ROOT_SOURCE_DIRECTORY}/xtos/include"
-)
-
 install(TARGETS sof-logger DESTINATION bin)
diff --git a/tools/plugin/CMakeLists.txt b/tools/plugin/CMakeLists.txt
deleted file mode 100644
index a137a4b7d04c..000000000000
--- a/tools/plugin/CMakeLists.txt
+++ /dev/null
@@ -1,72 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-
-cmake_minimum_required(VERSION 3.13)
-
-project(SOF_PLUGIN C CXX)
-
-include(../../scripts/cmake/misc.cmake)
-include(CheckCCompilerFlag)
-
-set(sof_source_directory "${PROJECT_SOURCE_DIR}/../..")
-set(sof_install_directory "${PROJECT_BINARY_DIR}/sof_ep/install")
-set(sof_binary_directory "${PROJECT_BINARY_DIR}/sof_ep/build")
-
-set(config_h ${sof_binary_directory}/library_autoconfig.h)
-
-set(parser_source_directory "${PROJECT_SOURCE_DIR}/../tplg_parser")
-set(parser_install_dir "${PROJECT_BINARY_DIR}/sof_parser/install")
-
-message("ipc4 build")
-set(tplg_ipc plugin_ipc4_defconfig)
-
-include(ExternalProject)
-
-# External project for SOF library
-ExternalProject_Add(sof_ep
-	DOWNLOAD_COMMAND ""
-	SOURCE_DIR "${sof_source_directory}"
-	PREFIX "${PROJECT_BINARY_DIR}/sof_ep"
-	BINARY_DIR "${sof_binary_directory}"
-	CMAKE_ARGS -DCONFIG_LIBRARY=ON
-		-DCMAKE_INSTALL_PREFIX=${sof_install_directory}
-		-DCMAKE_VERBOSE_MAKEFILE=${CMAKE_VERBOSE_MAKEFILE}
-		-DINIT_CONFIG=${tplg_ipc}
-		-DCONFIG_H_PATH=${config_h}
-		-DCONFIG_LIBRARY_STATIC=ON
-		-DOPTIMIZE_FOR_DEBUG=ON
-	BUILD_ALWAYS 1
-	BUILD_BYPRODUCTS "${sof_install_directory}/lib/libsof.a"
-)
-
-add_library(sof_library STATIC IMPORTED)
-set_target_properties(sof_library PROPERTIES IMPORTED_LOCATION "${sof_install_directory}/lib/libsof.a")
-add_dependencies(sof_library sof_ep)
-
-# External project for topology parser
-ExternalProject_Add(parser_ep
-	SOURCE_DIR "${parser_source_directory}"
-	PREFIX "${PROJECT_BINARY_DIR}/sof_parser"
-	BINARY_DIR "${PROJECT_BINARY_DIR}/sof_parser/build"
-	CMAKE_ARGS -DCONFIG_LIBRARY=ON
-		-DCMAKE_INSTALL_PREFIX=${PROJECT_BINARY_DIR}/sof_parser/install
-		-DCMAKE_VERBOSE_MAKEFILE=${CMAKE_VERBOSE_MAKEFILE}
-		-DCONFIG_LIBRARY_STATIC=ON
-		-DOPTIMIZE_FOR_DEBUG=ON
-	BUILD_ALWAYS 1
-	BUILD_BYPRODUCTS "${parser_install_dir}/lib/libsof_tplg_parser.a"
-)
-
-add_library(sof_parser_lib STATIC IMPORTED)
-set_target_properties(sof_parser_lib PROPERTIES IMPORTED_LOCATION "${parser_install_dir}/lib/libsof_tplg_parser.a")
-add_dependencies(sof_parser_lib parser_ep)
-
-add_subdirectory(alsaconf)
-add_subdirectory(alsaplug)
-add_subdirectory(modules)
-add_subdirectory(pipe)
-
-add_dependencies(asound_module_pcm_sof sof_parser_lib)
-add_dependencies(asound_module_ctl_sof sof_parser_lib)
-
-add_dependencies(sof-pipe sof_mod_shm)
-add_dependencies(sof-pipe sof_mod_alsa)
diff --git a/tools/plugin/README.md b/tools/plugin/README.md
deleted file mode 100644
index 3bdd3bec2155..000000000000
--- a/tools/plugin/README.md
+++ /dev/null
@@ -1,164 +0,0 @@
-# ALSA Plugin
-
-The SOF ALSA plugin allows SOF topologies to be run on the host. The plugin
-is still WIP with many rough edges that need refined before production
-deployment, however the plugin is usable today as a rapid development
-framework for SOF infrastructure and processing.
-
-For an internals overview (process model, data flow, IPC, module loading and
-symbol resolution) see [architecture.md](architecture.md).
-
-### Features
- * aplay & arecord usage working today
- * alsamixer & amixer usage not working today
- * modules are loaded as SO shared libraries.
- * topology is parsed by the plugin and pipelines associated with the requested PCM ID are loaded
- * pipelines run as individual userspace threads
- * pipelines can be pinned to efficency cores
- * pipelines can use realtime priority.
- * alsa sink and alsa source modules available.
- * pipelines can block (non blocking and mmap todo)
-
-### License
-Code is a mixture of LGPL and BSD 3c.
-
-### Usage
-Please build as cmake project, for IPC4 (functional)
-IPC3 is not functional and not supported
-
-```
-cd sof
-cmake -GNinja -B build-plugin/ -S tools/plugin/
-# Build external projects first to avoid build race condition
-# Dropping -GNinja is another (very slow) option.
-cmake --build    build-plugin/ -- sof_ep parser_ep
-cmake --build    build-plugin/
-```
-then (use default ALSA prefix atm)
-
-```
-sudo cmake --install build-plugin/
-
-Make sure to set the LD_LIBRARY_PATH to include directory where the SOF modules are installed
-Ex: "~/work/sof/sof/build-plugin/sof_ep/install/lib:~/work/sof/sof/build-plugin/modules/"
-And set the environment variable SOF_PLUGIN_TOPOLOGY_PATH to point to the directory containing the topology binary
-```
-
-Code can then be run by starting sof-pipe with your desired topology (Ex: sof-plugin.tplg)
-
-```
- ./sof-pipe -T sof-plugin.tplg
-```
-
-At this point the sof-pipe daemon is waiting for IPC. Audio applications can now invoke sof-pipe processing via
-
-```
-aplay -Dsof:plugin:1:default:default:48k2c16b -f dat some48kHz.wav
-```
-The command line is parsed as follows:
-- "sof" is the plugin name
-- "sof-plugin" is the topology name. The "sof-" prefix and ".tplg" suffix will be appended by the plugin
-- "1" is the PCM ID for render/capture
-- "default": The first default is the card name
-- "default": The second default is the device name
-- "48k2c16b" is the config name for 48K, stereo, 16bit
-
-Config name is optional in the command line. When it is not provided, hw_params will be used to
-configure the endpoint. In this case, the command line can be simplified to:
-
-```
-aplay -Dsof:plugin:1:default:default
-```
-
-When using the default device, the command line can be further simplified to:
-
-```
-aplay -Dsof:plugin:1
-```
-
-This renders audio to the sof-pipe daemon using the sof-plugin topology playback PCM ID 1.
-The above example needs to be 48k as example pipe has no SRC/ASRC.
-
-Likewise
-
-```
-arecord -Dsof:plugin:1:default:default:48k2c16b -f dat file.wav
-```
-Will record audio using the plugin topology and PCM ID 1.
-
-Mixer settings can be adjusted for sof-plugin by
-
-```
-alsamixer -Dsof:plugin
-```
-or
-```
-amixer -Dsof:plugin cset numid=1 20
-```
-Bytes control data can be set using sof-ctl as follows:
-
-```
-./sof-ctl -Dsof:plugin -n 4 -r -i 4 -p 2 -s ~/data.txt
-```
-where -n is the numid of the kcontrol, -i is the IPC version, -p is the param ID and -s specifies
-the data in csv format.
-
-Bytes control data can be read using sof-ctl as follows:
-```
-./sof-ctl -Dsof:plugin -n 4 -i 4 -p 2
-```
-where -n is the numid of the kcontrol, -i is the IPC version and -p is the param ID.
-
-Note: Bytes controls must have tlv_read/tlv_write and tlv_callback access.
-
-## Instructions for testing OpenVino noise suppression model with the SOF plugin:
-1. Prepare Open Model Zoo repository:
-
-   - Clone repo:
-     ```
-     git clone --recurse-submodules https://github.com/openvinotoolkit/open_model_zoo.git
-     ```
-
-   - Build demo applications:
-     https://docs.openvino.ai/2023.3/omz_demos.html#a-name-build-demos-linux-a-build-the-demo-applications-on-linux
-
-2. Source OpenVino environment and get OpenCV
-https://www.intel.com/content/www/us/en/developer/tools/openvino-toolkit-download.html
-
-3. Worth building and running the demo noise suppression application in the open model zoo
-repository to make sure OpenVino and OpenCV are configured properly.
-Fetch the model, e.g., `noise-suppression-poconetlike-0001.xml`, by running this demo:
-
-   https://docs.openvino.ai/2023.3/omz_demos_noise_suppression_demo_cpp.html
-
-4. Set environment variable NOISE_SUPPRESSION_MODEL_NAME to point to the model file
-```
-export NOISE_SUPPRESSION_MODEL_NAME=~/open_model_zoo/demos/noise_suppression_demo/cpp/intel/noise-suppression-poconetlike-0001/FP16/noise-suppression-poconetlike-0001.xml
-
-```
-5. Set environment variable OpenVINO_DIR to include CMake files (e.g., OpenVINOConfig.cmake) for building the plugin:
-```
-export OpenVINO_DIR=~/openvino_env/lib/python3.10/site-packages/openvino/cmake
-
-```
-6. Update environment variable LD_LIBRARY_PATH to include necessary directories for the plugin:
-
-```
-export LD_LIBRARY_PATH=~/work/sof/sof/build-plugin/sof_ep/install/lib:~/work/sof/sof/build-plugin/modules/:~/work/sof/sof/build-plugin/modules/ov_noise_suppression/
-```
-
-7. Enable noise suppression by setting NOISE_SUPPRESSION=true in the tplg-targets for the sof-plugin topology
-
-8. Rebuild the plugin: Remove the previous build-build directory and rebuild it by following the usage steps above.
-
-9. Start capture using the following command. This uses the 16K capture from the DMIC from
-PCM hw device 0,7. Currently, only 16K capture is supported but in the future this will be expanded
-to work with 48K capture.
-```
-arecord -Dsof:plugin:1:0:7:16k2c16b -f dat -r 16000 --period-size=2048 file_ns_16k.wav
-```
-
-### TODO Items for single pipeline E2E audio
-Use hw_params instead of hardcoded config
-Add support for 24-bit and 16-bit audio
-Remove duplication of kcontrols when alsamixer is opened/closed repeatedly
\ No newline at end of file
diff --git a/tools/plugin/alsaconf/50-sof.conf b/tools/plugin/alsaconf/50-sof.conf
deleted file mode 100644
index 91566ec28a55..000000000000
--- a/tools/plugin/alsaconf/50-sof.conf
+++ /dev/null
@@ -1,94 +0,0 @@
-# Invoke a SOF pipeline and route it to a sound card or another plugin
-# To use the PCM 0 on the SOF "volume" topology and route it to hw:1,2 then run
-# aplay -Dsof:volume:0,hw,1,2
-# tplg:pipe:[pipe:card:dev:config[pipe:card:dev:config]...]
-#
-# TPLG		SOF topology configuration (mandatory)
-
-pcm.sof {
-	@args [ TPLG ]
-	@args.TPLG {
-		type string
-		default "passthrough"
-	}
-
-	type sof
-	tplg $TPLG
-
-	hint {
-		show {
-			@func refer
-			name defaults.namehint.basic
-		}
-		description "SOF Topology and PCM"
-	}
-
-	config.48k2c16b {
-        rate 48000
-        channels 2
-        format S16_LE
-        period_time 0
-        period_frames 48
-        buffer_time 0
-        buffer_frames 192
-    }
-
-	config.16k2c16b {
-		rate 16000
-		channels 2
-		format S16_LE
-		period_time 0
-		period_frames 2048 # based on the period size needed for Noise suppression module
-		buffer_time 0
-		buffer_frames 8192
-        }
-
-	config.48k8c16b {
-        rate 48000
-        channels 8
-        format S16_LE
-        period_time 0
-        period_frames 1024
-        buffer_time 0
-        buffer_frames 5120
-    }
-
-    config.8k8c16b {
-        rate 8000
-        channels 8
-        format S16_LE
-        period_time 0
-        period_frames 1024
-        buffer_time 0
-        buffer_frames 5120
-    }
-
-    config.48k2c32b {
-        rate 48000
-        channels 2
-        format S32_LE
-        period_time 0
-        period_frames 6000
-        buffer_time 0
-        buffer_frames 24000
-    }
-}
-
-ctl.sof {
-	@args [ TPLG ]
-	@args.TPLG {
-		type string
-		default "passthrough"
-	}
-
-	type sof
-	tplg $TPLG
-
-	hint {
-		show {
-			@func refer
-			name defaults.namehint.basic
-		}
-		description "SOF Topology"
-	}
-}
diff --git a/tools/plugin/alsaconf/CMakeLists.txt b/tools/plugin/alsaconf/CMakeLists.txt
deleted file mode 100644
index 3a58c514f522..000000000000
--- a/tools/plugin/alsaconf/CMakeLists.txt
+++ /dev/null
@@ -1,5 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-
-install(FILES 50-sof.conf DESTINATION /usr/share/alsa/alsa.conf.d)
-# HACK needs to link to above
-install(FILES 50-sof.conf DESTINATION /etc/alsa/conf.d)
diff --git a/tools/plugin/alsaplug/CMakeLists.txt b/tools/plugin/alsaplug/CMakeLists.txt
deleted file mode 100644
index d60104d8245d..000000000000
--- a/tools/plugin/alsaplug/CMakeLists.txt
+++ /dev/null
@@ -1,69 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-
-# PCM ALSA module
-add_library(asound_module_pcm_sof MODULE
-	pcm.c
-	plugin.c
-	../common.c
-	tplg.c
-	tplg_ctl.c
-)
-
-sof_append_relative_path_definitions(asound_module_pcm_sof)
-
-target_include_directories(asound_module_pcm_sof PRIVATE
-	${CMAKE_CURRENT_SOURCE_DIR}
-	${CMAKE_CURRENT_SOURCE_DIR}/..
-	${sof_source_directory}/src/audio)
-
-target_compile_options(asound_module_pcm_sof PRIVATE -DPIC -g -O3 -Wmissing-prototypes
-  -Wno-stringop-truncation -Wimplicit-fallthrough -DCONFIG_LIBRARY -imacros${config_h})
-
-install(TARGETS asound_module_pcm_sof DESTINATION /usr/lib/x86_64-linux-gnu/alsa-lib)
-
-target_link_options(asound_module_pcm_sof PRIVATE -Wl,--export-dynamic,--no-undefined)
-target_link_libraries(asound_module_pcm_sof PRIVATE sof_library)
-target_link_libraries(asound_module_pcm_sof PRIVATE sof_parser_lib)
-target_link_libraries(asound_module_pcm_sof PRIVATE pthread)
-target_link_libraries(asound_module_pcm_sof PRIVATE  -lasound -ldl -lm -lasound -lrt)
-
-target_include_directories(asound_module_pcm_sof PRIVATE ${sof_install_directory}/include)
-target_include_directories(asound_module_pcm_sof PRIVATE ${parser_install_dir}/include)
-
-set_target_properties(asound_module_pcm_sof
-	PROPERTIES
-	INSTALL_RPATH "${sof_install_directory}/alsa-lib"
-	INSTALL_RPATH_USE_LINK_PATH TRUE
-)
-
-# CTL ALSA module
-add_library(asound_module_ctl_sof MODULE
-	ctl.c
-	plugin.c
-	../common.c
-)
-sof_append_relative_path_definitions(asound_module_ctl_sof)
-target_include_directories(asound_module_ctl_sof PRIVATE
-	${CMAKE_CURRENT_SOURCE_DIR}
-	${CMAKE_CURRENT_SOURCE_DIR}/..
-	${sof_source_directory}/src/audio)
-
-target_compile_options(asound_module_ctl_sof PRIVATE -DPIC -g -O3 -Wmissing-prototypes
-  -Wimplicit-fallthrough -Wno-stringop-truncation -Wall -Werror -DCONFIG_LIBRARY -imacros${config_h})
-
-install(TARGETS asound_module_ctl_sof DESTINATION /usr/lib/x86_64-linux-gnu/alsa-lib)
-
-target_link_options(asound_module_ctl_sof PRIVATE -Wl,--export-dynamic,--no-undefined)
-target_link_libraries(asound_module_ctl_sof PRIVATE sof_library)
-target_link_libraries(asound_module_ctl_sof PRIVATE sof_parser_lib)
-target_link_libraries(asound_module_ctl_sof PRIVATE pthread)
-target_link_libraries(asound_module_ctl_sof PRIVATE  -lasound -ldl -lm -lasound -lrt)
-
-target_include_directories(asound_module_ctl_sof PRIVATE ${sof_install_directory}/include)
-target_include_directories(asound_module_ctl_sof PRIVATE ${parser_install_dir}/include)
-
-set_target_properties(asound_module_ctl_sof
-	PROPERTIES
-	INSTALL_RPATH "${sof_install_directory}/alsa-lib"
-	INSTALL_RPATH_USE_LINK_PATH TRUE
-)
diff --git a/tools/plugin/alsaplug/conf.c b/tools/plugin/alsaplug/conf.c
deleted file mode 100644
index 5b259bf6885a..000000000000
--- a/tools/plugin/alsaplug/conf.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/*-*- linux-c -*-*/
-
-/*
- * ALSA <-> SOF Config plugin
- *
- * Copyright(c) 2022 Intel Corporation. All rights reserved.
- *
- * This library is free software; you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as
- * published by the Free Software Foundation; either version 2.1 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, write to the Free
- * Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
- * 02111-1307 USA
- *
- */
-
-#include <stdio.h>
-#include <alsa/asoundlib.h>
-#include "plugin.h"
-
-/* Not actually part of the alsa api....  */
-extern int
-snd_config_hook_load(snd_config_t *root, snd_config_t *config,
-		     snd_config_t **dst, snd_config_t *private_data);
-
-/* manifest file could be loaded as a hook */
-int sofplug_load_hook(snd_config_t *root, snd_config_t *config,
-		      snd_config_t **dst, snd_config_t *private_data)
-{
-	int ret = 0;
-
-	*dst = NULL;
-
-	/* TODO: load hook when SOF ready */
-	return snd_config_hook_load(root, config, dst, private_data);
-}
-
-SND_DLSYM_BUILD_VERSION(sofplug_load_hook,
-			SND_CONFIG_DLSYM_VERSION_HOOK);
diff --git a/tools/plugin/alsaplug/ctl.c b/tools/plugin/alsaplug/ctl.c
deleted file mode 100644
index 85a31177cfca..000000000000
--- a/tools/plugin/alsaplug/ctl.c
+++ /dev/null
@@ -1,845 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-//
-// Copyright(c) 2022 Intel Corporation. All rights reserved.
-//
-// Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
-
-#include <stdio.h>
-#include <sys/poll.h>
-#include <string.h>
-#include <sys/types.h>
-#include <unistd.h>
-#include <stdlib.h>
-#include <sys/wait.h>
-#include <sys/stat.h>
-#include <mqueue.h>
-#include <fcntl.h>
-#include <sys/mman.h>
-#include <semaphore.h>
-#include <assert.h>
-#include <errno.h>
-
-// TODO remove parsing and read ctls from sof-pipe SHM glb context
-#include <ipc/control.h>
-
-#include <alsa/asoundlib.h>
-#include <alsa/control_external.h>
-
-#include "plugin.h"
-#include "common.h"
-
-typedef struct snd_sof_ctl {
-	struct plug_shm_glb_state *glb;
-	snd_ctl_ext_t ext;
-	struct plug_socket_desc ipc;
-	struct plug_shm_desc shm_ctx;
-	int subscribed;
-	int updated[MAX_CTLS];
-
-} snd_sof_ctl_t;
-
-#define CTL_GET_TPLG_HDR(_ctl, _key) \
-		(&_ctl->glb->ctl[_key].mixer_ctl.hdr)
-
-#define CTL_GET_TPLG_MIXER(_ctl, _key) \
-		(&_ctl->glb->ctl[_key].mixer_ctl)
-
-#define CTL_GET_TPLG_ENUM(_ctl, _key) \
-		(&_ctl->glb->ctl[_key].enum_ctl)
-
-#define CTL_GET_TPLG_BYTES(_ctl, _key) \
-		(&_ctl->glb->ctl[_key].bytes_ctl)
-
-static uint32_t mixer_to_ipc(unsigned int value, uint32_t *volume_table, int size)
-{
-	if (value >= size)
-		return volume_table[size - 1];
-
-	return volume_table[value];
-}
-
-static uint32_t ipc_to_mixer(uint32_t value, uint32_t *volume_table, int size)
-{
-	int i;
-
-	for (i = 0; i < size; i++) {
-		if (volume_table[i] >= value)
-			return i;
-	}
-
-	return i - 1;
-}
-
-/* number of ctls */
-static int plug_ctl_elem_count(snd_ctl_ext_t *ext)
-{
-	snd_sof_ctl_t *ctl = ext->private_data;
-
-	/* TODO: get count of elems from topology */
-	return ctl->glb->num_ctls;
-}
-
-static int plug_ctl_elem_list(snd_ctl_ext_t *ext, unsigned int offset, snd_ctl_elem_id_t *id)
-{
-	snd_sof_ctl_t *ctl = ext->private_data;
-	struct snd_soc_tplg_ctl_hdr *hdr;
-
-	if (offset >=  ctl->glb->num_ctls)
-		return -EINVAL;
-
-	hdr = CTL_GET_TPLG_HDR(ctl, offset);
-
-	snd_ctl_elem_id_set_interface(id, SND_CTL_ELEM_IFACE_MIXER);
-	snd_ctl_elem_id_set_name(id, hdr->name);
-
-	return 0;
-}
-
-static snd_ctl_ext_key_t plug_ctl_find_elem(snd_ctl_ext_t *ext, const snd_ctl_elem_id_t *id)
-{
-	snd_sof_ctl_t *ctl = ext->private_data;
-	unsigned int numid;
-
-	numid = snd_ctl_elem_id_get_numid(id);
-
-	if (numid > ctl->glb->num_ctls)
-		return SND_CTL_EXT_KEY_NOT_FOUND;
-
-	return numid - 1;
-}
-
-static int plug_ctl_get_attribute(snd_ctl_ext_t *ext, snd_ctl_ext_key_t key,
-				  int *type, unsigned int *acc, unsigned int *count)
-{
-	snd_sof_ctl_t *ctl = ext->private_data;
-	struct snd_soc_tplg_ctl_hdr *hdr = CTL_GET_TPLG_HDR(ctl, key);
-	struct snd_soc_tplg_mixer_control *mixer_ctl;
-	struct snd_soc_tplg_enum_control *enum_ctl;
-	struct snd_soc_tplg_bytes_control *bytes_ctl;
-	int err = 0;
-
-	switch (hdr->ops.info) {
-	case SND_SOC_TPLG_CTL_VOLSW:
-	case SND_SOC_TPLG_CTL_VOLSW_SX:
-	case SND_SOC_TPLG_CTL_VOLSW_XR_SX:
-		mixer_ctl = (struct snd_soc_tplg_mixer_control *)hdr;
-
-		/* check for type - boolean should be binary values */
-		if (mixer_ctl->max == 1 && mixer_ctl->min == 0)
-			*type = SND_CTL_ELEM_TYPE_BOOLEAN;
-		else
-			*type = SND_CTL_ELEM_TYPE_INTEGER;
-		*count = 2;//mixer_ctl->num_channels; ///// WRONG is 0 !!!
-
-		//printf("mixer %d %d\n", __LINE__, mixer_ctl->num_channels);
-		break;
-	case SND_SOC_TPLG_CTL_ENUM:
-	case SND_SOC_TPLG_CTL_ENUM_VALUE:
-		enum_ctl = (struct snd_soc_tplg_enum_control *)hdr;
-		*type = SND_CTL_ELEM_TYPE_ENUMERATED;
-		*count = enum_ctl->items;
-		break;
-	case SND_SOC_TPLG_CTL_RANGE:
-	case SND_SOC_TPLG_CTL_STROBE:
-		// TODO: ??
-		break;
-	case SND_SOC_TPLG_CTL_BYTES:
-		bytes_ctl = (struct snd_soc_tplg_bytes_control *)hdr;
-		*type = SND_CTL_ELEM_TYPE_BYTES;
-		*count = bytes_ctl->max;
-		break;
-	}
-
-	*acc = hdr->access;
-
-	/* access needs the callback to decode the data */
-	if ((hdr->access & SND_CTL_EXT_ACCESS_TLV_READ) ||
-	    (hdr->access & SND_CTL_EXT_ACCESS_TLV_WRITE))
-		*acc |= SND_CTL_EXT_ACCESS_TLV_CALLBACK;
-	return err;
-}
-
-/*
- * Integer ops
- */
-static int plug_ctl_get_integer_info(snd_ctl_ext_t *ext, snd_ctl_ext_key_t key, long *imin,
-				     long *imax, long *istep)
-{
-	snd_sof_ctl_t *ctl = ext->private_data;
-	struct snd_soc_tplg_ctl_hdr *hdr = CTL_GET_TPLG_HDR(ctl, key);
-	struct snd_soc_tplg_mixer_control *mixer_ctl =
-			CTL_GET_TPLG_MIXER(ctl, key);
-	int err = 0;
-
-	switch (hdr->type) {
-	case SND_SOC_TPLG_CTL_VOLSW:
-	case SND_SOC_TPLG_CTL_VOLSW_SX:
-	case SND_SOC_TPLG_CTL_VOLSW_XR_SX:
-		/* TLV uses the fields differently */
-		if ((hdr->access & SND_CTL_EXT_ACCESS_TLV_READ) ||
-		    (hdr->access & SND_CTL_EXT_ACCESS_TLV_WRITE)) {
-			*istep = mixer_ctl->hdr.tlv.scale.step;
-			*imin = (int32_t)mixer_ctl->hdr.tlv.scale.min;
-			*imax = mixer_ctl->max;
-		} else {
-			*istep = 1;
-			*imin = mixer_ctl->min;
-			*imax = mixer_ctl->max;
-		}
-		break;
-	default:
-		SNDERR("invalid ctl type for integer using key %d", key);
-		err = -EINVAL;
-		break;
-	}
-
-	return err;
-}
-
-static int plug_ctl_read_integer(snd_ctl_ext_t *ext, snd_ctl_ext_key_t key, long *value)
-{
-	snd_sof_ctl_t *ctl = ext->private_data;
-	struct snd_soc_tplg_mixer_control *mixer_ctl = CTL_GET_TPLG_MIXER(ctl, key);
-	struct ipc4_module_large_config config = {{ 0 }};
-	struct ipc4_peak_volume_config *volume;
-	struct ipc4_module_large_config_reply *reply;
-	char *reply_data;
-	void *msg;
-	int reply_data_size, size;
-	int num_data_items;
-	int i, err;
-
-	/* configure the IPC message */
-	plug_ctl_ipc_message(&config, IPC4_VOLUME, sizeof(volume), ctl->glb->ctl[key].module_id,
-			     ctl->glb->ctl[key].instance_id, SOF_IPC4_MOD_LARGE_CONFIG_GET);
-
-	config.extension.r.final_block = 1;
-	config.extension.r.init_block = 1;
-
-	size = sizeof(config);
-	msg = calloc(size, 1);
-	if (!msg)
-		return -ENOMEM;
-
-	/* reply contains both the requested data and the reply status */
-	reply_data_size = sizeof(*reply) + mixer_ctl->num_channels * sizeof(*volume);
-	reply_data = calloc(reply_data_size, 1);
-	if (!reply_data_size) {
-		free(msg);
-		return -ENOMEM;
-	}
-
-	/* send the IPC message */
-	memcpy(msg, &config, sizeof(config));
-	err = plug_ipc_cmd_tx_rx(&ctl->ipc, msg, size, reply_data, reply_data_size);
-	free(msg);
-	if (err < 0) {
-		SNDERR("failed to set volume for control %s\n", mixer_ctl->hdr.name);
-		goto out;
-	}
-
-	reply = (struct ipc4_module_large_config_reply *)reply_data;
-	if (reply->primary.r.status != IPC4_SUCCESS) {
-		SNDERR("volume control %s set failed with status %d\n",
-		       mixer_ctl->hdr.name, reply->primary.r.status);
-		err = -EINVAL;
-		goto out;
-	}
-
-	/* check data sanity */
-	num_data_items = reply->extension.r.data_off_size / sizeof(*volume);
-	if (num_data_items != mixer_ctl->num_channels) {
-		SNDERR("Channel count %d doesn't match the expected value %d\n",
-		       num_data_items, mixer_ctl->num_channels);
-		err = -EINVAL;
-		goto out;
-	}
-
-	/* set the mixer values based on the received data */
-	volume = (struct ipc4_peak_volume_config *)(reply_data + sizeof(*reply));
-	for (i = 0; i < mixer_ctl->num_channels; i++)
-		value[i] = ipc_to_mixer(volume[i].target_volume, ctl->glb->ctl[key].volume_table,
-					mixer_ctl->max + 1);
-out:
-	free(reply_data);
-	return err;
-}
-
-static int plug_ctl_write_integer(snd_ctl_ext_t *ext, snd_ctl_ext_key_t key, long *value)
-{
-	snd_sof_ctl_t *ctl = ext->private_data;
-	struct snd_soc_tplg_mixer_control *mixer_ctl = CTL_GET_TPLG_MIXER(ctl, key);
-	struct ipc4_module_large_config config = {{ 0 }};
-	struct ipc4_peak_volume_config volume;
-	struct ipc4_message_reply reply;
-	bool all_channels_equal = true;
-	uint32_t val;
-	void *msg;
-	int size, err;
-	int i;
-
-	/* set data for IPC */
-	val = value[0];
-	for (i = 1; i < mixer_ctl->num_channels; i++) {
-		if (value[i] != val) {
-			all_channels_equal = false;
-			break;
-		}
-	}
-
-	/*
-	 * if all channels have the same volume, send a single IPC, else, send individual IPCs
-	 * for each channel
-	 */
-	for (i = 0; i < mixer_ctl->num_channels; i++) {
-		if (all_channels_equal) {
-			volume.channel_id = IPC4_ALL_CHANNELS_MASK;
-			volume.target_volume = mixer_to_ipc(val, ctl->glb->ctl[key].volume_table,
-							    mixer_ctl->max + 1);
-		} else {
-			volume.channel_id = i;
-			volume.target_volume = mixer_to_ipc(value[i],
-							    ctl->glb->ctl[key].volume_table,
-							    mixer_ctl->max + 1);
-		}
-
-		/* TODO: get curve duration and type from topology */
-		volume.curve_type = 1;
-		volume.curve_duration = 200000;
-
-		/* configure the IPC message */
-		plug_ctl_ipc_message(&config, IPC4_VOLUME, sizeof(volume),
-				     ctl->glb->ctl[key].module_id, ctl->glb->ctl[key].instance_id,
-				     SOF_IPC4_MOD_LARGE_CONFIG_SET);
-		config.extension.r.final_block = 1;
-		config.extension.r.init_block = 1;
-
-		size = sizeof(config) + sizeof(volume);
-		msg = calloc(size, 1);
-		if (!msg)
-			return -ENOMEM;
-
-		memcpy(msg, &config, sizeof(config));
-		memcpy(msg + sizeof(config), &volume, sizeof(volume));
-
-		/* send the message and check status */
-		err = plug_ipc_cmd_tx_rx(&ctl->ipc, msg, size, &reply, sizeof(reply));
-		free(msg);
-		if (err < 0) {
-			SNDERR("failed to set volume control %s\n", mixer_ctl->hdr.name);
-			return err;
-		}
-
-		if (reply.primary.r.status != IPC4_SUCCESS) {
-			SNDERR("volume control %s set failed with status %d\n",
-			       mixer_ctl->hdr.name, reply.primary.r.status);
-			return -EINVAL;
-		}
-
-		if (all_channels_equal)
-			break;
-	}
-
-	return 0;
-}
-
-/*
- * Enum ops
- */
-static int plug_ctl_get_enumerated_info(snd_ctl_ext_t *ext, snd_ctl_ext_key_t key,
-					unsigned int *items)
-{
-	snd_sof_ctl_t *ctl = ext->private_data;
-	struct snd_soc_tplg_ctl_hdr *hdr = CTL_GET_TPLG_HDR(ctl, key);
-	struct snd_soc_tplg_enum_control *enum_ctl =
-			(struct snd_soc_tplg_enum_control *)hdr;
-	int err = 0;
-
-	switch (hdr->ops.info) {
-	case SND_SOC_TPLG_CTL_ENUM:
-	case SND_SOC_TPLG_CTL_ENUM_VALUE:
-		*items = enum_ctl->items;
-		break;
-	default:
-		SNDERR("invalid ctl type for enum using key %d", key);
-		err = -EINVAL;
-		break;
-	}
-
-	return err;
-}
-
-static int plug_ctl_get_enumerated_name(snd_ctl_ext_t *ext, snd_ctl_ext_key_t key,
-					unsigned int item, char *name, size_t name_max_len)
-{
-	snd_sof_ctl_t *ctl = ext->private_data;
-	struct snd_soc_tplg_ctl_hdr *hdr = CTL_GET_TPLG_HDR(ctl, key);
-	struct snd_soc_tplg_enum_control *enum_ctl =
-			(struct snd_soc_tplg_enum_control *)hdr;
-
-	if (item >= enum_ctl->items) {
-		SNDERR("invalid item %d for enum using key %d\n", item, key);
-		return -EINVAL;
-	}
-
-	strncpy(name, enum_ctl->texts[item], name_max_len);
-	return 0;
-}
-
-static int plug_ctl_read_enumerated(snd_ctl_ext_t *ext, snd_ctl_ext_key_t key,
-				    unsigned int *items)
-{
-	snd_sof_ctl_t *ctl = ext->private_data;
-	struct snd_soc_tplg_enum_control *enum_ctl = CTL_GET_TPLG_ENUM(ctl, key);
-	struct ipc4_module_large_config config = {{ 0 }};
-	struct ipc4_module_large_config_reply *reply;
-	struct sof_ipc4_control_msg_payload *data;
-	char *reply_data;
-	void *msg;
-	int size, reply_data_size;
-	int i, err;
-
-	/* configure the IPC message */
-	plug_ctl_ipc_message(&config, SOF_IPC4_ENUM_CONTROL_PARAM_ID, 0,
-			     ctl->glb->ctl[key].module_id, ctl->glb->ctl[key].instance_id,
-			     SOF_IPC4_MOD_LARGE_CONFIG_GET);
-
-	config.extension.r.final_block = 1;
-	config.extension.r.init_block = 1;
-
-	size = sizeof(config);
-	msg = calloc(size, 1);
-	if (!msg)
-		return -ENOMEM;
-
-	/* reply contains both the requested data and the reply status */
-	reply_data_size = sizeof(*reply) + sizeof(*data) +
-		enum_ctl->num_channels * sizeof(data->chanv[0]);
-	reply_data = calloc(reply_data_size, 1);
-	if (!reply_data_size) {
-		free(msg);
-		return -ENOMEM;
-	}
-
-	/* send the IPC message */
-	memcpy(msg, &config, sizeof(config));
-	err = plug_ipc_cmd_tx_rx(&ctl->ipc, msg, size, reply_data, reply_data_size);
-	free(msg);
-	if (err < 0) {
-		SNDERR("failed to get enum items for control %s\n", enum_ctl->hdr.name);
-		goto out;
-	}
-
-	reply = (struct ipc4_module_large_config_reply *)reply_data;
-	if (reply->primary.r.status != IPC4_SUCCESS) {
-		SNDERR("enum control %s get failed with status %d\n",
-		       enum_ctl->hdr.name, reply->primary.r.status);
-		err = -EINVAL;
-		goto out;
-	}
-
-	/* check data sanity */
-	data = (struct sof_ipc4_control_msg_payload *)(reply_data + sizeof(*reply));
-	if (data->num_elems != enum_ctl->num_channels) {
-		SNDERR("Channel count %d doesn't match the expected value %d for enum ctl %s\n",
-		       data->num_elems, enum_ctl->num_channels, enum_ctl->hdr.name);
-		err = -EINVAL;
-		goto out;
-	}
-
-	/* set the enum items based on the received data */
-	for (i = 0; i < enum_ctl->num_channels; i++)
-		items[i] = data->chanv[i].value;
-out:
-	free(reply_data);
-	return 0;
-}
-
-static int plug_ctl_write_enumerated(snd_ctl_ext_t *ext, snd_ctl_ext_key_t key,
-				     unsigned int *items)
-{
-	snd_sof_ctl_t *ctl = ext->private_data;
-	struct snd_soc_tplg_enum_control *enum_ctl = CTL_GET_TPLG_ENUM(ctl, key);
-	struct ipc4_module_large_config config = {{ 0 }};
-	struct sof_ipc4_control_msg_payload *data;
-	struct ipc4_message_reply reply;
-	void *msg;
-	int data_size, msg_size;
-	int err, i;
-
-	/* size of control data */
-	data_size = enum_ctl->num_channels * sizeof(struct sof_ipc4_ctrl_value_chan) +
-			sizeof(*data);
-
-	/* allocate memory for control data */
-	data = calloc(data_size, 1);
-	if (!data)
-		return -ENOMEM;
-
-	/* set param ID and number of channels */
-	data->id = ctl->glb->ctl[key].index;
-	data->num_elems = enum_ctl->num_channels;
-
-	/* set the enum values */
-	for (i = 0; i < data->num_elems; i++) {
-		data->chanv[i].channel = i;
-		data->chanv[i].value = items[i];
-	}
-
-	/* configure the IPC message */
-	plug_ctl_ipc_message(&config, SOF_IPC4_ENUM_CONTROL_PARAM_ID, data_size,
-			     ctl->glb->ctl[key].module_id, ctl->glb->ctl[key].instance_id,
-			     SOF_IPC4_MOD_LARGE_CONFIG_SET);
-
-	/*
-	 * enum controls can have a maximum of 16 texts/values. So the entire data can be sent
-	 * in a single IPC message
-	 */
-	config.extension.r.final_block = 1;
-	config.extension.r.init_block = 1;
-
-	/* allocate memory for IPC message */
-	msg_size = sizeof(config) + data_size;
-	msg = calloc(msg_size, 1);
-	if (!msg) {
-		free(data);
-		return -ENOMEM;
-	}
-
-	/* set the IPC message data */
-	memcpy(msg, &config, sizeof(config));
-	memcpy(msg + sizeof(config), data, data_size);
-	free(data);
-
-	/* send the message and check status */
-	err = plug_ipc_cmd_tx_rx(&ctl->ipc, msg, msg_size, &reply, sizeof(reply));
-	free(msg);
-	if (err < 0) {
-		SNDERR("failed to set enum control %s\n", enum_ctl->hdr.name);
-		return err;
-	}
-
-	if (reply.primary.r.status != IPC4_SUCCESS) {
-		SNDERR("enum control %s set failed with status %d\n",
-		       enum_ctl->hdr.name, reply.primary.r.status);
-		return -EINVAL;
-	}
-
-	return 0;
-}
-
-/*
- * Bytes ops
- */
-static int plug_ctl_get_bytes_data(snd_sof_ctl_t *ctl, snd_ctl_ext_key_t key,
-				   struct sof_abi_hdr *abi, unsigned int max_bytes)
-{
-	struct snd_soc_tplg_bytes_control *bytes_ctl = CTL_GET_TPLG_BYTES(ctl, key);
-	struct ipc4_module_large_config config = {{ 0 }};
-	struct ipc4_module_large_config_reply *reply;
-	char *reply_data, *data;
-	void *msg;
-	uint32_t data_size;
-	int size, reply_data_size;
-	int err;
-
-	/* configure the IPC message */
-	plug_ctl_ipc_message(&config, abi->type, 0,
-			     ctl->glb->ctl[key].module_id, ctl->glb->ctl[key].instance_id,
-			     SOF_IPC4_MOD_LARGE_CONFIG_GET);
-
-	config.extension.r.final_block = 1;
-	config.extension.r.init_block = 1;
-
-	size = sizeof(config);
-	msg = calloc(size, 1);
-	if (!msg)
-		return -ENOMEM;
-
-	/*
-	 * reply contains both the requested data and the reply status. Allocate enough memory
-	 * for max data
-	 */
-	reply_data_size = sizeof(*reply) + sizeof(*data) + bytes_ctl->max;
-	reply_data = calloc(reply_data_size, 1);
-	if (!reply_data_size) {
-		free(msg);
-		return -ENOMEM;
-	}
-
-	/* send the IPC message */
-	memcpy(msg, &config, sizeof(config));
-	err = plug_ipc_cmd_tx_rx(&ctl->ipc, msg, size, reply_data, reply_data_size);
-	free(msg);
-	if (err < 0) {
-		SNDERR("failed to get bytes data for control %s\n", bytes_ctl->hdr.name);
-		goto out;
-	}
-
-	reply = (struct ipc4_module_large_config_reply *)reply_data;
-	if (reply->primary.r.status != IPC4_SUCCESS) {
-		SNDERR("bytes control %s get failed with status %d\n",
-		       bytes_ctl->hdr.name, reply->primary.r.status);
-		err = -EINVAL;
-		goto out;
-	}
-
-	/* check data sanity */
-	data = (char *)(reply_data + sizeof(*reply));
-	data_size = reply->extension.r.data_off_size;
-	if (data_size > bytes_ctl->max) {
-		SNDERR("received data size %d is larger than max %d for bytes control %s\n",
-		       data_size, bytes_ctl->max, bytes_ctl->hdr.name);
-		err = -EINVAL;
-		goto out;
-	}
-
-	abi->size = data_size;
-
-	if (data_size)
-		memcpy(abi->data, data, MIN(data_size, max_bytes));
-
-	err = data_size;
-out:
-	free(reply_data);
-	return err;
-}
-
-static int plug_ctl_read_bytes(snd_ctl_ext_t *ext, snd_ctl_ext_key_t key,
-			       unsigned char *data, size_t max_bytes)
-{
-	snd_sof_ctl_t *ctl = ext->private_data;
-	struct sof_abi_hdr *abi = (struct sof_abi_hdr *)data;
-	int data_size;
-
-	data_size = plug_ctl_get_bytes_data(ctl, key, abi, max_bytes);
-	if (data_size < 0)
-		return data_size;
-
-	return 0;
-}
-
-static int plug_ctl_write_bytes(snd_ctl_ext_t *ext, snd_ctl_ext_key_t key,
-				unsigned char *data, size_t max_bytes)
-{
-	snd_sof_ctl_t *ctl = ext->private_data;
-	struct snd_soc_tplg_bytes_control *bytes_ctl = CTL_GET_TPLG_BYTES(ctl, key);
-	struct sof_abi_hdr *abi = (struct sof_abi_hdr *)data;
-	int err;
-
-	/* send IPC with kcontrol data */
-	err = plug_send_bytes_data(&ctl->ipc, ctl->glb->ctl[key].module_id,
-				   ctl->glb->ctl[key].instance_id, abi);
-	if (err < 0) {
-		SNDERR("failed to set bytes data for control %s\n", bytes_ctl->hdr.name);
-		return err;
-	}
-
-	return 0;
-}
-
-/* TLV ops used for TLV bytes control callback */
-/* TLV ops used for TLV bytes control callback */
-static int plug_tlv_rw(snd_ctl_ext_t *ext, snd_ctl_ext_key_t key, int op_flag,
-		       unsigned int numid, unsigned int *tlv, unsigned int tlv_size)
-{
-	snd_sof_ctl_t *ctl = ext->private_data;
-	struct snd_soc_tplg_bytes_control *bytes_ctl = CTL_GET_TPLG_BYTES(ctl, key);
-	struct sof_abi_hdr *abi = (struct sof_abi_hdr *)(tlv + 2); /* skip TLV header */
-	int data_size;
-
-	/* only bytes and volume controls have tlv callback set */
-	if (bytes_ctl->hdr.ops.info != SND_SOC_TPLG_CTL_BYTES) {
-		struct snd_soc_tplg_mixer_control *mixer_ctl = CTL_GET_TPLG_MIXER(ctl, key);
-		struct snd_soc_tplg_ctl_hdr *hdr = &mixer_ctl->hdr;
-		struct snd_soc_tplg_ctl_tlv *mixer_tlv = &hdr->tlv;
-
-		/* set the dbscale values */
-		tlv[0] = SND_CTL_TLVT_DB_SCALE;
-		tlv[1] = sizeof(int) * 2;
-		tlv[2] = mixer_tlv->scale.min;
-		tlv[3] = mixer_tlv->scale.mute << 16 | mixer_tlv->scale.step;
-
-		return 0;
-	}
-
-	/* send IPC with kcontrol data if op_flag is > 0 else send IPC to get kcontrol data */
-	if (op_flag) {
-		int err;
-
-		err = plug_send_bytes_data(&ctl->ipc, ctl->glb->ctl[key].module_id,
-					   ctl->glb->ctl[key].instance_id, abi);
-		if (err < 0) {
-			SNDERR("failed to set bytes data for control %s\n", bytes_ctl->hdr.name);
-			return err;
-		}
-
-		return 0;
-	}
-
-	/* read kcontrol data */
-	data_size = plug_ctl_get_bytes_data(ctl, key, abi, tlv_size);
-	if (data_size < 0)
-		return data_size;
-
-	/* set data size and numid */
-	tlv[0] = numid;
-	tlv[1] = data_size + sizeof(*abi);
-
-	return 0;
-}
-
-static void plug_ctl_subscribe_events(snd_ctl_ext_t *ext, int subscribe)
-{
-	snd_sof_ctl_t *ctl = ext->private_data;
-
-	ctl->subscribed = !!(subscribe & SND_CTL_EVENT_MASK_VALUE);
-}
-
-static int plug_ctl_read_event(snd_ctl_ext_t *ext, snd_ctl_elem_id_t *id,
-			       unsigned int *event_mask)
-{
-	snd_sof_ctl_t *ctl = ext->private_data;
-	int numid;
-	int err = 0;
-
-	numid = snd_ctl_elem_id_get_numid(id);
-
-	// TODO: we need a notify() or listening thread to take async/volatile ctl
-	// notifications from sof-pipe and notify userspace via events of the ctl change.
-	if (!ctl->updated[numid - 1] || !ctl->subscribed) {
-		err = -EAGAIN;
-		goto out;
-	}
-
-	*event_mask = SND_CTL_EVENT_MASK_VALUE;
-out:
-	return err;
-}
-
-static int plug_ctl_poll_revents(snd_ctl_ext_t *ext, struct pollfd *pfd,
-				 unsigned int nfds, unsigned short *revents)
-{
-	snd_sof_ctl_t *ctl = ext->private_data;
-	int i;
-
-	*revents = 0;
-
-	for (i = 0; i < ctl->glb->num_ctls; i++) {
-		if (ctl->updated[i]) {
-			*revents = POLLIN;
-			break;
-		}
-	}
-
-	return 0;
-}
-
-static void plug_ctl_close(snd_ctl_ext_t *ext)
-{
-	snd_sof_ctl_t *ctl = ext->private_data;
-
-	/* TODO: munmap */
-	close(ctl->ipc.socket_fd);
-	free(ctl);
-}
-
-static const snd_ctl_ext_callback_t sof_ext_callback = {
-	.elem_count = plug_ctl_elem_count,
-	.elem_list = plug_ctl_elem_list,
-	.find_elem = plug_ctl_find_elem,
-	.get_attribute = plug_ctl_get_attribute,
-	.get_integer_info = plug_ctl_get_integer_info,
-	.read_integer = plug_ctl_read_integer,
-	.write_integer = plug_ctl_write_integer,
-	.get_enumerated_info = plug_ctl_get_enumerated_info,
-	.get_enumerated_name = plug_ctl_get_enumerated_name,
-	.read_enumerated = plug_ctl_read_enumerated,
-	.write_enumerated = plug_ctl_write_enumerated,
-	.read_bytes = plug_ctl_read_bytes,
-	.write_bytes = plug_ctl_write_bytes,
-	.subscribe_events = plug_ctl_subscribe_events,
-	.read_event = plug_ctl_read_event,
-	.poll_revents = plug_ctl_poll_revents,
-	.close = plug_ctl_close,
-};
-
-SND_CTL_PLUGIN_DEFINE_FUNC(sof)
-{
-	snd_sof_plug_t *plug;
-	int err;
-	snd_sof_ctl_t *ctl;
-
-	/* create context */
-	plug = calloc(1, sizeof(*plug));
-	if (!plug)
-		return -ENOMEM;
-
-	ctl = calloc(1, sizeof(*ctl));
-	if (!ctl)
-		return -ENOMEM;
-	plug->module_prv = ctl;
-
-	/* parse the ALSA configuration file for sof plugin */
-	err = plug_parse_conf(plug, name, root, conf, true);
-	if (err < 0) {
-		SNDERR("failed to parse config: %s", strerror(err));
-		goto error;
-	}
-
-	/* init IPC socket name */
-	err = plug_socket_path_init(&ctl->ipc, "sof", "ipc", 0);
-	if (err < 0) {
-		SNDERR("error: invalid name for IPC tx mq %s\n", plug->tplg_file);
-		goto error;
-	}
-
-	err = plug_create_client_socket(&ctl->ipc);
-	if (err < 0) {
-		SNDERR("failed to connect to SOF pipe IPC socket : %s", strerror(err));
-		return -errno;
-	}
-
-	/* create a SHM mapping for low latency stream position */
-	err = plug_shm_init(&ctl->shm_ctx, plug->tplg_file, "ctx", 0);
-	if (err < 0)
-		goto error;
-
-	// TODO: make this open/close per operation for shared access
-	/* create a SHM mapping for low latency stream position */
-	err = plug_shm_open(&ctl->shm_ctx);
-	if (err < 0)
-		goto error;
-
-	/* get global context for kcontrol lookup */
-	ctl->glb = ctl->shm_ctx.addr;
-
-	/* TODO: add some flavour to the names based on the topology */
-	ctl->ext.version = SND_CTL_EXT_VERSION;
-	ctl->ext.card_idx = 0;
-	strncpy(ctl->ext.id, "sof", sizeof(ctl->ext.id) - 1);
-	strncpy(ctl->ext.driver, "SOF plugin",
-		sizeof(ctl->ext.driver) - 1);
-	strncpy(ctl->ext.name, "SOF", sizeof(ctl->ext.name) - 1);
-	strncpy(ctl->ext.mixername, "SOF",
-		sizeof(ctl->ext.mixername) - 1);
-
-	ctl->ext.callback = &sof_ext_callback;
-	ctl->ext.private_data = ctl;
-	ctl->ext.tlv.c = plug_tlv_rw;
-
-	err = snd_ctl_ext_create(&ctl->ext, name, mode);
-	if (err < 0)
-		goto error;
-
-	*handlep = ctl->ext.handle;
-
-	return 0;
-
-error:
-	free(ctl);
-
-	return err;
-}
-
-SND_CTL_PLUGIN_SYMBOL(sof);
diff --git a/tools/plugin/alsaplug/pcm.c b/tools/plugin/alsaplug/pcm.c
deleted file mode 100644
index ed5224c829b5..000000000000
--- a/tools/plugin/alsaplug/pcm.c
+++ /dev/null
@@ -1,1000 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-//
-// Copyright(c) 2022 Intel Corporation. All rights reserved.
-//
-// Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
-
-#include <stdio.h>
-#include <sys/poll.h>
-#include <string.h>
-#include <sys/types.h>
-#include <sys/socket.h>
-#include <sys/un.h>
-#include <unistd.h>
-#include <stdlib.h>
-#include <sys/wait.h>
-#include <sys/stat.h>
-#include <fcntl.h>
-#include <sys/mman.h>
-#include <semaphore.h>
-#include <assert.h>
-#include <errno.h>
-#include <math.h>
-
-#include <alsa/asoundlib.h>
-#include <alsa/pcm_external.h>
-
-#include <rtos/sof.h>
-#include <sof/audio/pipeline.h>
-#include <sof/audio/component.h>
-#include <ipc/stream.h>
-#include <tplg_parser/topology.h>
-
-#include "plugin.h"
-#include "common.h"
-
-typedef struct snd_sof_pcm {
-	snd_pcm_ioplug_t io;
-	size_t frame_size;
-	struct timespec wait_timeout;
-	int capture;
-	int events;
-
-	/* PCM flow control */
-	struct plug_sem_desc ready[TPLG_MAX_PCM_PIPELINES];
-	struct plug_sem_desc done[TPLG_MAX_PCM_PIPELINES];
-
-	struct plug_shm_desc shm_pcm;
-
-	int frame_us;
-} snd_sof_pcm_t;
-
-static int plug_pipeline_set_state(snd_sof_plug_t *plug, int state,
-				   struct ipc4_pipeline_set_state *pipe_state,
-				   struct tplg_pipeline_info *pipe_info,
-				   struct plug_socket_desc *ipc)
-{
-	struct ipc4_message_reply reply = {{ 0 }};
-	int ret;
-
-	pipe_state->primary.r.ppl_id = pipe_info->instance_id;
-
-	ret = plug_ipc_cmd_tx_rx(ipc, pipe_state, sizeof(*pipe_state),
-				 &reply, sizeof(reply));
-	if (ret < 0)
-		SNDERR("failed pipeline %d set state %d\n", pipe_info->instance_id, state);
-
-	return ret;
-}
-
-static int plug_pipelines_set_state(snd_sof_plug_t *plug, int state)
-{
-	snd_sof_pcm_t *pcm = plug->module_prv;
-	struct ipc4_pipeline_set_state pipe_state = {{ 0 }};
-	struct tplg_pipeline_list *pipeline_list;
-	int i;
-
-	if (pcm->capture)
-		pipeline_list = &plug->pcm_info->capture_pipeline_list;
-	else
-		pipeline_list = &plug->pcm_info->playback_pipeline_list;
-
-	pipe_state.primary.r.ppl_state = state;
-	pipe_state.primary.r.type = SOF_IPC4_GLB_SET_PIPELINE_STATE;
-	pipe_state.primary.r.msg_tgt = SOF_IPC4_MESSAGE_TARGET_FW_GEN_MSG;
-	pipe_state.primary.r.rsp = SOF_IPC4_MESSAGE_DIR_MSG_REQUEST;
-
-	/*
-	 * pipeline list is populated starting from the host to DAI. So traverse the list in
-	 * the reverse order for capture to start the source pipeline first.
-	 */
-	if (pcm->capture) {
-		for (i = pipeline_list->count - 1; i >= 0; i--) {
-			struct tplg_pipeline_info *pipe_info = pipeline_list->pipelines[i];
-			int ret;
-
-			ret = plug_pipeline_set_state(plug, state, &pipe_state, pipe_info,
-						      &plug->ipc);
-			if (ret < 0)
-				return ret;
-		}
-
-		return 0;
-	}
-
-	for (i = 0; i < pipeline_list->count; i++) {
-		struct tplg_pipeline_info *pipe_info = pipeline_list->pipelines[i];
-		int ret;
-
-		ret = plug_pipeline_set_state(plug, state, &pipe_state, pipe_info,
-					      &plug->ipc);
-		if (ret < 0)
-			return ret;
-	}
-
-	return 0;
-}
-
-static int plug_pcm_start(snd_pcm_ioplug_t *io)
-{
-	snd_sof_plug_t *plug = io->private_data;
-	snd_sof_pcm_t *pcm = plug->module_prv;
-	struct plug_shm_endpoint *ctx = pcm->shm_pcm.addr;
-	int err;
-
-	switch (ctx->state) {
-	case SOF_PLUGIN_STATE_READY:
-		err = plug_pipelines_set_state(plug, SOF_IPC4_PIPELINE_STATE_RUNNING);
-		if (err < 0)
-			return err;
-		break;
-	case SOF_PLUGIN_STATE_STREAM_RUNNING:
-	{
-		struct tplg_pipeline_list *pipeline_list;
-		int i, delay;
-
-		if (!pcm->capture)
-			break;
-
-		pipeline_list = &plug->pcm_info->capture_pipeline_list;
-
-		/* start the first period copy for capture */
-		for (i = pipeline_list->count - 1; i >= 0; i--) {
-			sem_post(pcm->ready[i].sem);
-
-			/* wait for sof-pipe reader to consume data or timeout */
-			err = clock_gettime(CLOCK_REALTIME, &pcm->wait_timeout);
-			if (err == -1) {
-				SNDERR("write: cant get time: %s", strerror(errno));
-				return -EPIPE;
-			}
-
-			/* work out delay TODO: fix ALSA reader */
-			delay = pcm->frame_us * io->period_size / 500;
-			plug_timespec_add_ms(&pcm->wait_timeout, delay);
-
-			/* wait for sof-pipe writer to produce data or timeout */
-			err = sem_timedwait(pcm->done[i].sem, &pcm->wait_timeout);
-			if (err == -1) {
-				SNDERR("read: waited %d ms for %ld frames fatal timeout: %s",
-				       delay, io->period_size, strerror(errno));
-				return -errno;
-			}
-		}
-	}
-		break;
-	case SOF_PLUGIN_STATE_INIT:
-	case SOF_PLUGIN_STATE_STREAM_ERROR:
-	case SOF_PLUGIN_STATE_DEAD:
-	default:
-		/* some error */
-		SNDERR("pcm start: invalid pipe state: %d", ctx->state);
-		return -EINVAL;
-	}
-
-	return 0;
-}
-
-static int plug_pcm_stop(snd_pcm_ioplug_t *io)
-{
-	snd_sof_plug_t *plug = io->private_data;
-	snd_sof_pcm_t *pcm = plug->module_prv;
-	struct plug_shm_endpoint *ctx = pcm->shm_pcm.addr;
-	int err;
-
-	printf("%s %d state %ld\n", __func__, __LINE__, ctx->state);
-	switch (ctx->state) {
-	case SOF_PLUGIN_STATE_STREAM_ERROR:
-	case SOF_PLUGIN_STATE_STREAM_RUNNING:
-	{
-		err = plug_pipelines_set_state(plug, SOF_IPC4_PIPELINE_STATE_PAUSED);
-		if (err < 0)
-			return err;
-		break;
-	}
-	case SOF_PLUGIN_STATE_READY:
-		/* already stopped */
-		break;
-	case SOF_PLUGIN_STATE_INIT:
-	case SOF_PLUGIN_STATE_DEAD:
-	default:
-		/* some error */
-		SNDERR("pcm stop: invalid pipe state: %d", ctx->state);
-		return -EINVAL;
-	}
-
-	return 0;
-}
-
-/* buffer position up to buffer_size */
-static snd_pcm_sframes_t plug_pcm_pointer(snd_pcm_ioplug_t *io)
-{
-	snd_sof_plug_t *plug = io->private_data;
-	snd_sof_pcm_t *pcm = plug->module_prv;
-	struct plug_shm_endpoint *ctx = pcm->shm_pcm.addr;
-	snd_pcm_sframes_t ptr = 0;
-	int err;
-
-	if (io->state == SND_PCM_STATE_XRUN)
-		return -EPIPE;
-
-	if (io->state != SND_PCM_STATE_RUNNING)
-		return 0;
-
-	switch (ctx->state) {
-	case SOF_PLUGIN_STATE_STREAM_RUNNING:
-	case SOF_PLUGIN_STATE_STREAM_ERROR:
-		if (pcm->capture)
-			ptr =  ctx->wtotal / pcm->frame_size;
-		else
-			ptr =  ctx->rtotal / pcm->frame_size;
-		break;
-	case SOF_PLUGIN_STATE_READY:
-		/* not running */
-		return 0;
-	case SOF_PLUGIN_STATE_INIT:
-	case SOF_PLUGIN_STATE_DEAD:
-	default:
-		/* some error */
-		SNDERR("pointer: invalid pipe state: %d", ctx->state);
-		ptr =  -EPIPE;
-	}
-
-	return ptr;
-}
-
-/* get the delay for the running PCM; optional; since v1.0.1 */
-static int plug_pcm_delay(snd_pcm_ioplug_t *io, snd_pcm_sframes_t *delayp)
-{
-	snd_sof_plug_t *plug = io->private_data;
-	snd_sof_pcm_t *pcm = plug->module_prv;
-	struct plug_shm_endpoint *ctx = pcm->shm_pcm.addr;
-	int err = 0;
-
-	switch (ctx->state) {
-	case SOF_PLUGIN_STATE_STREAM_RUNNING:
-	case SOF_PLUGIN_STATE_READY:
-		// TODO: is capture delay correct here ???
-		if (pcm->capture)
-			*delayp = (ctx->wtotal - ctx->rtotal) / pcm->frame_size;
-		else
-			*delayp = (ctx->rtotal - ctx->wtotal) / pcm->frame_size;
-		/* sanitize delay */
-		if (*delayp < pcm->io.period_size || *delayp > io->buffer_size)
-			*delayp = pcm->io.period_size;
-		return 0;
-	case SOF_PLUGIN_STATE_STREAM_ERROR:
-		snd_pcm_ioplug_set_state(io, SND_PCM_STATE_XRUN);
-		return 0;
-	case SOF_PLUGIN_STATE_INIT:
-	case SOF_PLUGIN_STATE_DEAD:
-	default:
-		/* some error */
-		SNDERR("delay: invalid pipe state: %d", ctx->state);
-		return -EPIPE;
-	}
-}
-
-/* return frames written */
-static snd_pcm_sframes_t plug_pcm_write(snd_pcm_ioplug_t *io, const snd_pcm_channel_area_t *areas,
-					snd_pcm_uframes_t offset, snd_pcm_uframes_t size)
-{
-	snd_sof_plug_t *plug = io->private_data;
-	snd_sof_pcm_t *pcm = plug->module_prv;
-	struct plug_shm_endpoint *ctx = pcm->shm_pcm.addr;
-	struct tplg_pipeline_list *pipeline_list;
-	snd_pcm_sframes_t frames = 0;
-	int i;
-	ssize_t bytes;
-	const char *buf;
-	int err, delay;
-
-	pipeline_list = &plug->pcm_info->playback_pipeline_list;
-
-	/* calculate the buffer position and size from application */
-	buf = (char *)areas->addr + (areas->first + areas->step * offset) / 8;
-	bytes = size * pcm->frame_size;
-
-	/* now check what the pipe has free */
-	bytes = MIN(plug_ep_get_free(ctx), bytes);
-
-	frames = bytes / pcm->frame_size;
-
-	if (frames == 0)
-		return frames;
-
-	/* write audio data to the pipe */
-	memcpy(plug_ep_wptr(ctx), buf, bytes);
-
-	plug_ep_produce(ctx, bytes);
-
-	/* tell the pipelines data is ready starting at the source pipeline */
-	for (i = 0; i < pipeline_list->count; i++) {
-		struct tplg_pipeline_info *pipe_info = pipeline_list->pipelines[i];
-
-		sem_post(pcm->ready[i].sem);
-
-		/* wait for sof-pipe reader to consume data or timeout */
-		err = clock_gettime(CLOCK_REALTIME, &pcm->wait_timeout);
-		if (err == -1) {
-			SNDERR("write: cant get time: %s", strerror(errno));
-			return -EPIPE;
-		}
-
-		/* work out delay */
-		delay = pcm->frame_us * frames / 500;
-		plug_timespec_add_ms(&pcm->wait_timeout, delay);
-
-		/* now block caller on pipeline IO to PCM device */
-		err = sem_timedwait(pcm->done[i].sem, &pcm->wait_timeout);
-		if (err == -1) {
-			SNDERR("write: waited %d ms for %ld frames, fatal timeout: %s",
-			       delay, frames, strerror(errno));
-			return -errno;
-		}
-	}
-
-	return frames;
-}
-
-/* return frames read */
-static snd_pcm_sframes_t plug_pcm_read(snd_pcm_ioplug_t *io, const snd_pcm_channel_area_t *areas,
-				       snd_pcm_uframes_t offset, snd_pcm_uframes_t size)
-{
-	snd_sof_plug_t *plug = io->private_data;
-	snd_sof_pcm_t *pcm = plug->module_prv;
-	snd_pcm_sframes_t frames;
-	struct plug_shm_endpoint *ctx = pcm->shm_pcm.addr;
-	struct tplg_pipeline_list *pipeline_list;
-	ssize_t bytes;
-	char *buf;
-	int err, delay, i;
-
-	pipeline_list = &plug->pcm_info->capture_pipeline_list;
-
-	/* calculate the buffer position and size */
-	buf = (char *)areas->addr + (areas->first + areas->step * offset) / 8;
-	bytes = size * pcm->frame_size;
-
-	/* check what the pipe has avail */
-	bytes = MIN(plug_ep_get_avail(ctx), bytes);
-	frames = bytes / pcm->frame_size;
-
-	if (!frames)
-		return 0;
-
-	/* tell the pipe ready we are ready for next period */
-	for (i = pipeline_list->count - 1; i >= 0; i--) {
-		sem_post(pcm->ready[i].sem);
-
-		/* wait for sof-pipe reader to consume data or timeout */
-		err = clock_gettime(CLOCK_REALTIME, &pcm->wait_timeout);
-		if (err == -1) {
-			SNDERR("write: cant get time: %s", strerror(errno));
-			return -EPIPE;
-		}
-
-		/* work out delay TODO: fix ALSA reader */
-		delay = pcm->frame_us * frames / 500;
-		plug_timespec_add_ms(&pcm->wait_timeout, delay);
-
-		/* wait for sof-pipe writer to produce data or timeout */
-		err = sem_timedwait(pcm->done[i].sem, &pcm->wait_timeout);
-		if (err == -1) {
-			SNDERR("read: waited %d ms for %ld frames fatal timeout: %s",
-			       delay, frames, strerror(errno));
-			return -errno;
-		}
-	}
-
-	/* copy audio data from pipe */
-	memcpy(buf, plug_ep_rptr(ctx), bytes);
-	plug_ep_consume(ctx, bytes);
-
-	return frames;
-}
-
-static int plug_pcm_prepare(snd_pcm_ioplug_t *io)
-{
-	snd_sof_plug_t *plug = io->private_data;
-	snd_sof_pcm_t *pcm = plug->module_prv;
-	struct plug_shm_endpoint *ctx = pcm->shm_pcm.addr;
-	int err = 0;
-
-	ctx->wtotal = 0;
-	ctx->rtotal = 0;
-	ctx->rpos = 0;
-	ctx->rwrap = 0;
-	ctx->wpos = 0;
-	ctx->wwrap = 0;
-
-	/* start the pipeline threads
-	 *
-	 * We do this during prepare so that pipelines can consume/produce
-	 * any start threshold worth of data with the pipeline in a running
-	 * state
-	 */
-	switch (ctx->state) {
-	case SOF_PLUGIN_STATE_INIT:
-		/* set pipelines to PAUSED state to prepare them */
-		err = plug_pipelines_set_state(plug, SOF_IPC4_PIPELINE_STATE_PAUSED);
-		if (err < 0)
-			return err;
-
-		fprintf(stdout, "pipelines complete now\n");
-
-		/* set pipelines to RUNNING state */
-		err = plug_pipelines_set_state(plug, SOF_IPC4_PIPELINE_STATE_RUNNING);
-		if (err < 0)
-			return err;
-		break;
-	case SOF_PLUGIN_STATE_STREAM_ERROR:
-	case SOF_PLUGIN_STATE_DEAD:
-		/* some error */
-		SNDERR("write: invalid pipe state: %d", ctx->state);
-		return -EINVAL;
-	case SOF_PLUGIN_STATE_READY:
-	case SOF_PLUGIN_STATE_STREAM_RUNNING:
-	default:
-		/* do nothing */
-		break;
-	}
-
-	fprintf(stdout, "PCM prepare done\n");
-
-	return err;
-}
-
-static int plug_init_shm_ctx(snd_sof_plug_t *plug, snd_pcm_hw_params_t *params);
-
-static int plug_pcm_hw_params(snd_pcm_ioplug_t *io, snd_pcm_hw_params_t *params)
-{
-	snd_sof_plug_t *plug = io->private_data;
-	snd_sof_pcm_t *pcm = plug->module_prv;
-	struct plug_shm_endpoint *ctx;
-	struct tplg_pipeline_list *pipeline_list;
-	int i, err;
-
-	pcm->frame_size = (snd_pcm_format_physical_width(io->format) * io->channels) / 8;
-
-	plug->period_size = io->period_size;
-
-	/* used for wait timeouts */
-	pcm->frame_us = ceil(1000000.0 / io->rate);
-
-	/* now send IPCs to set up widgets */
-	err = plug_set_up_pipelines(plug, pcm->capture, params);
-	if (err < 0) {
-		fprintf(stderr, "error setting up pipelines\n");
-		return err;
-	}
-
-	if (pcm->capture)
-		pipeline_list = &plug->pcm_info->capture_pipeline_list;
-	else
-		pipeline_list = &plug->pcm_info->playback_pipeline_list;
-
-	/* init and open for PCM ready lock for all pipelines */
-	for (i = 0; i < pipeline_list->count; i++) {
-		struct tplg_pipeline_info *pipe_info = pipeline_list->pipelines[i];
-
-		/* init name for pipeline ready lock */
-		err = plug_lock_init(&pcm->ready[i], plug->tplg_file, "ready",
-				     pipe_info->instance_id);
-		if (err < 0) {
-			SNDERR("error: invalid name for PCM ready lock %s\n",
-			       pipe_info->instance_id);
-			return err;
-		}
-
-		/* init name for pipeline done lock */
-		err = plug_lock_init(&pcm->done[i], plug->tplg_file, "done",
-				     pipe_info->instance_id);
-		if (err < 0) {
-			SNDERR("error: invalid name for PCM done lock %s\n",
-			       pipe_info->instance_id);
-			return err;
-		}
-
-		/* open lock "ready" for pipeline audio data */
-		err = plug_lock_open(&pcm->ready[i]);
-		if (err < 0) {
-			SNDERR("error: failed to open sof-pipe ready lock %s: %s",
-			       pcm->ready[i].name, strerror(err));
-			return -errno;
-		}
-
-		/* open lock "done" for pipeline audio data */
-		err = plug_lock_open(&pcm->done[i]);
-		if (err < 0) {
-			SNDERR("error: failed to open sof-pipe done lock %s: %s",
-			       pcm->done[i].name, strerror(err));
-			return -errno;
-		}
-	}
-
-	/* init PCM shm name */
-	err = plug_shm_init(&pcm->shm_pcm, plug->tplg_file, "pcm", plug->pcm_id);
-	if (err < 0) {
-		SNDERR("error: invalid name for PCM SHM %s\n", plug->tplg_file);
-		return err;
-	}
-
-	/* open audio PCM SHM data endpoint */
-	err = plug_shm_open(&pcm->shm_pcm);
-	if (err < 0) {
-		SNDERR("error: failed to open sof-pipe PCM SHM %s: %s",
-		       pcm->shm_pcm.name, strerror(err));
-		return -errno;
-	}
-
-	/* set up the endpoint configs */
-	err = plug_init_shm_ctx(plug, params);
-	if (err < 0) {
-		SNDERR("error: failed to init sof-pipe ep context: %s:%s",
-		       pcm->shm_pcm.name, strerror(err));
-		return -err;
-	}
-
-	ctx = pcm->shm_pcm.addr;
-	ctx->frame_size = pcm->frame_size;
-
-	/* needs to be set here and NOT in SW params as SW params not
-	 * called in capture flow ?
-	 */
-	ctx->buffer_size = io->buffer_size * ctx->frame_size;
-
-	if (!ctx->buffer_size) {
-		SNDERR("Invalid buffer_size io buffer_size %d ctx->frame_size %d\n",
-		       io->buffer_size, ctx->frame_size);
-		return -EINVAL;
-	}
-
-	fprintf(stdout, "PCM hw_params done\n");
-
-	return 0;
-}
-
-// TODO: why not called for arecord
-static int plug_pcm_sw_params(snd_pcm_ioplug_t *io, snd_pcm_sw_params_t *params)
-{
-	snd_sof_plug_t *plug = io->private_data;
-	snd_sof_pcm_t *pcm = plug->module_prv;
-	snd_pcm_uframes_t start_threshold;
-	struct plug_shm_endpoint *ctx = pcm->shm_pcm.addr;
-	int err;
-
-	/* get the stream start threshold */
-	err = snd_pcm_sw_params_get_start_threshold(params, &start_threshold);
-	if (err < 0) {
-		SNDERR("sw params: failed to get start threshold: %s", strerror(err));
-		return err;
-	}
-
-	/* TODO: this seems to be ignored or overridden by application params ??? */
-	if (start_threshold < io->period_size) {
-		start_threshold = io->period_size;
-		err = snd_pcm_sw_params_set_start_threshold(pcm->io.pcm,
-							    params, start_threshold);
-		if (err < 0) {
-			SNDERR("sw params: failed to set start threshold %d: %s",
-			       start_threshold, strerror(err));
-			return err;
-		}
-	}
-
-	/* keep running as long as we can */
-	err = snd_pcm_sw_params_set_avail_min(pcm->io.pcm, params, 1);
-	if (err < 0) {
-		SNDERR("sw params: failed to set avail min %d: %s", 1, strerror(err));
-		return err;
-	}
-
-	fprintf(stdout, "sw_params done\n");
-
-	return 0;
-}
-
-static int plug_pcm_close(snd_pcm_ioplug_t *io)
-{
-	snd_sof_plug_t *plug = io->private_data;
-	snd_sof_pcm_t *pcm = plug->module_prv;
-	struct plug_shm_glb_state *ctx = plug->glb_ctx.addr;
-	int err = 0;
-
-	printf("%s %d\n", __func__, __LINE__);
-
-	ctx->state = SOF_PLUGIN_STATE_INIT;
-
-	plug_free_topology(plug);
-
-	free(plug->tplg_file);
-	free(plug->module_prv);
-	free(plug);
-
-	return err;
-}
-
-static int plug_pcm_hw_free(snd_pcm_ioplug_t *io)
-{
-	struct tplg_pipeline_list *pipeline_list;
-	snd_sof_plug_t *plug = io->private_data;
-	snd_sof_pcm_t *pcm = plug->module_prv;
-	int ret, i;
-
-	/* reset all pipelines */
-	ret = plug_pipelines_set_state(plug, SOF_IPC4_PIPELINE_STATE_RESET);
-	if (ret < 0) {
-		fprintf(stderr, "failed to reset pipelines\n");
-		return ret;
-	}
-
-	if (pcm->capture)
-		pipeline_list = &plug->pcm_info->capture_pipeline_list;
-	else
-		pipeline_list = &plug->pcm_info->playback_pipeline_list;
-
-	ret = plug_free_pipelines(plug, pipeline_list, pcm->capture);
-
-	close(pcm->shm_pcm.fd);
-	close(plug->glb_ctx.fd);
-
-	for (i = 0; i < pipeline_list->count; i++) {
-		struct tplg_pipeline_info *pipe_info = pipeline_list->pipelines[i];
-
-		sem_close(pcm->ready[pipe_info->instance_id].sem);
-		sem_close(pcm->done[pipe_info->instance_id].sem);
-	}
-	close(plug->ipc.socket_fd);
-
-	return 0;
-}
-
-static const snd_pcm_ioplug_callback_t sof_playback_callback = {
-	.start = plug_pcm_start,
-	.stop = plug_pcm_stop,
-	.pointer = plug_pcm_pointer,
-	.transfer = plug_pcm_write,
-	.delay = plug_pcm_delay,
-	.prepare = plug_pcm_prepare,
-	.hw_params = plug_pcm_hw_params,
-	.hw_free = plug_pcm_hw_free,
-	.sw_params = plug_pcm_sw_params,
-	.close = plug_pcm_close,
-};
-
-static const snd_pcm_ioplug_callback_t sof_capture_callback = {
-	.start = plug_pcm_start,
-	.stop = plug_pcm_stop,
-	.pointer = plug_pcm_pointer,
-	.transfer = plug_pcm_read,
-	.delay = plug_pcm_delay,
-	.prepare = plug_pcm_prepare,
-	.hw_params = plug_pcm_hw_params,
-	.sw_params = plug_pcm_sw_params,
-	.hw_free = plug_pcm_hw_free,
-	.close = plug_pcm_close,
-};
-
-static const snd_pcm_access_t access_list[] = {
-	SND_PCM_ACCESS_RW_INTERLEAVED
-};
-
-static const unsigned int formats[] = {
-	SND_PCM_FORMAT_S16_LE,
-	SND_PCM_FORMAT_FLOAT_LE,
-	SND_PCM_FORMAT_S32_LE,
-	SND_PCM_FORMAT_S24_LE,
-};
-
-/*
- * Set HW constraints for the SOF plugin. This needs to be quite unrestrictive atm
- * as we really need to parse topology before the HW constraints can be narrowed
- * to a range that will work with the specified pipeline.
- * TODO: Align with topology.
- */
-static int plug_hw_constraint(snd_sof_plug_t *plug)
-{
-	snd_sof_pcm_t *pcm = plug->module_prv;
-	snd_pcm_ioplug_t *io = &pcm->io;
-	int err;
-
-	err = snd_pcm_ioplug_set_param_list(io, SND_PCM_IOPLUG_HW_ACCESS,
-					    ARRAY_SIZE(access_list),
-					    access_list);
-	if (err < 0) {
-		SNDERR("constraints: failed to set access: %s", strerror(err));
-		return err;
-	}
-
-	err = snd_pcm_ioplug_set_param_list(io, SND_PCM_IOPLUG_HW_FORMAT,
-					    ARRAY_SIZE(formats), formats);
-	if (err < 0) {
-		SNDERR("constraints: failed to set format: %s", strerror(err));
-		return err;
-	}
-
-	err =
-	    snd_pcm_ioplug_set_param_minmax(io, SND_PCM_IOPLUG_HW_CHANNELS,
-					    1, 8);
-	if (err < 0) {
-		SNDERR("constraints: failed to set channels: %s", strerror(err));
-		return err;
-	}
-
-	err = snd_pcm_ioplug_set_param_minmax(io, SND_PCM_IOPLUG_HW_RATE,
-					      1, 192000);
-	if (err < 0) {
-		SNDERR("constraints: failed to set rate: %s", strerror(err));
-		return err;
-	}
-
-	err =
-	    snd_pcm_ioplug_set_param_minmax(io,
-					    SND_PCM_IOPLUG_HW_BUFFER_BYTES,
-					    1, 4 * 1024 * 1024);
-	if (err < 0) {
-		SNDERR("constraints: failed to set buffer bytes: %s", strerror(err));
-		return err;
-	}
-
-	err =
-	    snd_pcm_ioplug_set_param_minmax(io,
-					    SND_PCM_IOPLUG_HW_PERIOD_BYTES,
-					    128, 2 * 1024 * 1024);
-	if (err < 0) {
-		SNDERR("constraints: failed to set period bytes: %s", strerror(err));
-		return err;
-	}
-
-	err =
-	    snd_pcm_ioplug_set_param_minmax(io, SND_PCM_IOPLUG_HW_PERIODS, 1, 4);
-	if (err < 0) {
-		SNDERR("constraints: failed to set period count: %s", strerror(err));
-		return err;
-	}
-
-	return 0;
-}
-
-/*
- * Register the plugin with ALSA and make available for use.
- * TODO: setup all audio params
- * TODO: setup polling fd for RW or mmap IOs
- */
-static int plug_create(snd_sof_plug_t *plug, snd_pcm_t **pcmp, const char *name,
-		       snd_pcm_stream_t stream, int mode)
-{
-	snd_sof_pcm_t *pcm = plug->module_prv;
-	int err;
-
-	pcm->io.version = SND_PCM_IOPLUG_VERSION;
-	pcm->io.name = "ALSA <-> SOF PCM I/O Plugin";
-	pcm->io.poll_fd = pcm->shm_pcm.fd;
-	pcm->io.poll_events = POLLIN;
-	pcm->io.mmap_rw = 0;
-
-	if (stream == SND_PCM_STREAM_PLAYBACK)
-		pcm->io.callback = &sof_playback_callback;
-	else
-		pcm->io.callback = &sof_capture_callback;
-
-	pcm->io.private_data = plug;
-
-	/* create the plugin */
-	err = snd_pcm_ioplug_create(&pcm->io, name, stream, mode);
-	if (err < 0) {
-		SNDERR("failed to register plugin %s: %s\n", name, strerror(err));
-		return err;
-	}
-
-	/* set the HW constrainst */
-	err = plug_hw_constraint(plug);
-	if (err < 0) {
-		snd_pcm_ioplug_delete(&pcm->io);
-		return err;
-	}
-
-	*pcmp = pcm->io.pcm;
-	return 0;
-}
-
-static int plug_init_shm_ctx(snd_sof_plug_t *plug, snd_pcm_hw_params_t *params)
-{
-	struct plug_shm_glb_state *glb = plug->glb_ctx.addr;
-	struct endpoint_hw_config *ep;
-	struct plug_cmdline_item *ci;
-	struct plug_config *pc;
-	int i, j;
-
-	glb->num_ep_configs = 0;
-
-	for (i = 0; i < plug->num_cmdline; i++) {
-		bool found = false;
-
-		if (glb->num_ep_configs >= NUM_EP_CONFIGS - 1) {
-			SNDERR("error: too many endpoint configs\n");
-			return -EINVAL;
-		}
-
-		ci = &plug->cmdline[i];
-
-		for (j = 0; j < plug->num_configs; j++) {
-			pc = &plug->config[j];
-			if (strcmp(pc->name, ci->config_name))
-				continue;
-
-			ep = &glb->ep_config[glb->num_ep_configs++];
-			ep->buffer_frames = pc->buffer_frames;
-			ep->buffer_time = pc->buffer_time;
-			ep->channels = pc->channels;
-			ep->format = pc->format;
-			ep->period_frames = pc->period_frames;
-			ep->period_time = pc->period_time;
-			ep->rate = pc->rate;
-			strncpy(ep->config_name, ci->config_name, sizeof(ep->config_name));
-			found = true;
-			break;
-		}
-
-		/* use hw_params if no matching config found or config missing in command line */
-		if (!found) {
-			unsigned int channels, rate, dir, buffer_time, period_time;
-			snd_pcm_uframes_t buffer_size, period_size;
-			snd_pcm_format_t format;
-
-			snd_pcm_hw_params_get_channels(params, &channels);
-			snd_pcm_hw_params_get_rate(params, &rate, &dir);
-			snd_pcm_hw_params_get_buffer_size(params, &buffer_size);
-			snd_pcm_hw_params_get_period_size(params, &period_size, &dir);
-			snd_pcm_hw_params_get_buffer_time(params, &buffer_time, &dir);
-			snd_pcm_hw_params_get_period_time(params, &period_time, &dir);
-			snd_pcm_hw_params_get_format(params, &format);
-
-			ep = &glb->ep_config[glb->num_ep_configs++];
-			ep->buffer_frames = buffer_size;
-			ep->buffer_time = buffer_time;
-			ep->channels = channels;
-			ep->format = format;
-			ep->period_frames = period_size;
-			ep->period_time = period_time;
-			ep->rate = rate;
-		}
-
-		ep->pipeline = ci->pcm;
-		strncpy(ep->card_name, ci->card_name, sizeof(ep->card_name));
-		strncpy(ep->dev_name, ci->dev_name, sizeof(ep->dev_name));
-	}
-
-	return 0;
-}
-
-/*
- * Complete parent initialisation.
- * 1. Check if pipe already ready by opening SHM context and IPC.
- * 2. TODO: check context state and load topology is needed for core.
- */
-static int plug_init_sof_pipe(snd_sof_plug_t *plug, snd_pcm_t **pcmp,
-			      const char *name, snd_pcm_stream_t stream, int mode)
-{
-	snd_sof_pcm_t *pcm = plug->module_prv;
-	struct plug_shm_glb_state *ctx;
-	struct timespec delay;
-	int err, i;
-
-	/* initialize widget, route and pcm lists */
-	list_init(&plug->widget_list);
-	list_init(&plug->route_list);
-	list_init(&plug->pcm_list);
-
-	plug->tplg.tplg_file = plug->tplg_file;
-
-	/* plugin only works with IPC4 */
-	plug->tplg.ipc_major = 4;
-
-	/* init global status hsm name */
-	err = plug_shm_init(&plug->glb_ctx, plug->tplg_file, "ctx", 0);
-	if (err < 0) {
-		SNDERR("error: invalid name for global SHM %s\n", plug->tplg_file);
-		return err;
-	}
-
-	/* open the global context via SHM */
-	plug->glb_ctx.size = 128 * 1024;
-	err = plug_shm_open(&plug->glb_ctx);
-	if (err < 0) {
-		SNDERR("error: failed to open plugin context: %s:%s",
-		       plug->glb_ctx.name, strerror(err));
-		return err;
-	}
-
-	/* parse topology file */
-	err = plug_parse_topology(plug);
-	if (err < 0) {
-		fprintf(stderr, "error parsing topology %s\n", plug->tplg.tplg_file);
-		return err;
-	}
-
-	fprintf(stdout, "topology parsing complete\n");
-
-	/* init IPC message queue name */
-	err = plug_socket_path_init(&plug->ipc, "sof", "ipc", 0);
-	if (err < 0) {
-		SNDERR("error: invalid name for IPC socket %s\n", plug->tplg_file);
-		return err;
-	}
-
-	err = plug_create_client_socket(&plug->ipc);
-	if (err < 0) {
-		SNDERR("failed to connect to SOF pipe IPC socket : %s", strerror(err));
-		return -errno;
-	}
-
-	/* now register the plugin */
-	err = plug_create(plug, pcmp, name, stream, mode);
-	if (err < 0) {
-		SNDERR("failed to create plugin: %s", strerror(err));
-		return -errno;
-	}
-
-	return 0;
-}
-
-/*
- * ALSA PCM plugin entry point.
- */
-SND_PCM_PLUGIN_DEFINE_FUNC(sof)
-{
-	snd_sof_plug_t *plug;
-	snd_sof_pcm_t *pcm;
-	int err;
-
-	fprintf(stdout, "This code is WIP. Cmd args & config will possible change over time\n");
-	fprintf(stdout, "\nThe 50-sonf.conf file is parsed for PCM configurations which can\n");
-	fprintf(stdout, "be mapped on the cmd line to pipeline endpoints.\n");
-	fprintf(stdout, "\ni.e. aplay -Dsof:<topology>:<pcm id><card>:<device>:<config> file.wav\n");
-	fprintf(stdout, "\nwhich can be used as\n");
-	fprintf(stdout, "\ne.g. aplay -Dsof:bdw-nocodec:1:default:default:48k2c16b -f dat ~/audiodump.wav\n\n");
-
-	/* create context */
-	plug = calloc(1, sizeof(*plug));
-	if (!plug)
-		return -ENOMEM;
-
-	pcm = calloc(1, sizeof(*pcm));
-	if (!pcm) {
-		free(plug);
-		return -ENOMEM;
-	}
-	plug->module_prv = pcm;
-
-	if (stream == SND_PCM_STREAM_CAPTURE)
-		pcm->capture = 1;
-
-	/* parse the ALSA configuration file for sof plugin */
-	err = plug_parse_conf(plug, name, root, conf, false);
-	if (err < 0) {
-		SNDERR("failed to parse config: %s", strerror(err));
-		goto parse_conf_err;
-	}
-
-	/* now try and connect to the sof-pipe for this topology */
-	err = plug_init_sof_pipe(plug, pcmp, name, stream, mode);
-	if (err < 0) {
-		SNDERR("failed to complete plugin init: %s", strerror(err));
-		goto pipe_error;
-	}
-
-	/* everything is good */
-	return 0;
-
-pipe_error:
-	free(plug->tplg_file);
-parse_conf_err:
-	free(plug->module_prv);
-dev_error:
-	free(plug);
-	return err;
-}
-
-SND_PCM_PLUGIN_SYMBOL(sof);
diff --git a/tools/plugin/alsaplug/plugin.c b/tools/plugin/alsaplug/plugin.c
deleted file mode 100644
index 52bbdcfc70e1..000000000000
--- a/tools/plugin/alsaplug/plugin.c
+++ /dev/null
@@ -1,361 +0,0 @@
-/*-*- linux-c -*-*/
-
-/*
- * ALSA <-> SOF PCM I/O plugin
- *
- * Copyright(c) 2022 Intel Corporation. All rights reserved.
- *
- * This library is free software; you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as
- * published by the Free Software Foundation; either version 2.1 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
- */
-
-#include <stdio.h>
-#include <sys/poll.h>
-#include <string.h>
-#include <sys/types.h>
-#include <unistd.h>
-#include <stddef.h>
-#include <stdlib.h>
-#include <sys/wait.h>
-#include <sys/stat.h>
-#include <fcntl.h>
-#include <sys/mman.h>
-#include <semaphore.h>
-#include <assert.h>
-#include <errno.h>
-#include <alsa/asoundlib.h>
-#include <alsa/pcm_external.h>
-
-#include "plugin.h"
-#include "common.h"
-
-/*
- * Open an existing semaphore using lock object.
- */
-int plug_lock_open(struct plug_sem_desc *lock)
-{
-	lock->sem = sem_open(lock->name, O_RDWR);
-	if (lock->sem == SEM_FAILED) {
-		SNDERR("failed to open semaphore %s: %s\n", lock->name, strerror(errno));
-		return -errno;
-	}
-
-	return 0;
-}
-
-#define itemsize(type, member) sizeof(((type *)0)->member)
-
-static int parse_conf_long(snd_config_t *cfg, void *obj, size_t size)
-{
-	long val;
-
-	if (snd_config_get_integer(cfg, &val) < 0)
-		return -EINVAL;
-
-	*((long *)obj) = val;
-	return 0;
-}
-
-static int parse_conf_str(snd_config_t *cfg, void *obj, size_t size)
-{
-	const char *id;
-
-	if (snd_config_get_id(cfg, &id) < 0)
-		return -EINVAL;
-	strncpy(obj, id, size);
-
-	return 0;
-}
-
-static int parse_conf_format(snd_config_t *cfg, void *obj, size_t size)
-{
-	const char *id;
-
-	if (snd_config_get_string(cfg, &id) < 0)
-		return -EINVAL;
-
-	if (!strcmp("S16_LE", id)) {
-		*((long *)obj) = SND_PCM_FORMAT_S16_LE;
-		return 0;
-	}
-	if (!strcmp("S32_LE", id)) {
-		*((long *)obj) = SND_PCM_FORMAT_S32_LE;
-		return 0;
-	}
-	if (!strcmp("S24_4LE", id)) {
-		*((long *)obj) = SND_PCM_FORMAT_S24_LE;
-		return 0;
-	}
-	if (!strcmp("FLOAT", id)) {
-		*((long *)obj) = SND_PCM_FORMAT_FLOAT_LE;
-		return 0;
-	}
-
-	/* not found */
-	SNDERR("error: cant find format: %s", id);
-	return -EINVAL;
-}
-
-struct config_item {
-	char *name;
-	size_t size;
-	size_t offset;
-	int (*copy)(snd_config_t *cfg, void *obj, size_t size);
-};
-
-struct config_item config_items[] = {
-	{"name", itemsize(struct plug_config, name),
-		offsetof(struct plug_config, name), parse_conf_str},
-	{"rate", itemsize(struct plug_config, rate),
-		offsetof(struct plug_config, rate), parse_conf_long},
-	{"format", itemsize(struct plug_config, format),
-		offsetof(struct plug_config, format), parse_conf_format},
-	{"channels", itemsize(struct plug_config, channels),
-		offsetof(struct plug_config, channels), parse_conf_long},
-	{"period_time", itemsize(struct plug_config, period_time),
-		offsetof(struct plug_config, period_time), parse_conf_long},
-	{"period_frames", itemsize(struct plug_config, period_frames),
-		offsetof(struct plug_config, period_frames), parse_conf_long},
-	{"buffer_time", itemsize(struct plug_config, buffer_time),
-		offsetof(struct plug_config, buffer_time), parse_conf_long},
-	{"buffer_frames", itemsize(struct plug_config, buffer_frames),
-		offsetof(struct plug_config, buffer_frames), parse_conf_long},
-};
-
-static int parse_item(snd_config_t *cfg, const char *id, struct plug_config *dest_cfg)
-{
-	void *dest = dest_cfg;
-	int i;
-
-	for (i = 0; i < ARRAY_SIZE(config_items); i++) {
-		/* does ID match */
-		if (strcmp(id, config_items[i].name))
-			continue;
-
-		/* now get the value */
-		return config_items[i].copy(cfg, dest + config_items[i].offset,
-					    config_items[i].size);
-	}
-
-	/* not found - non fatal */
-	return 0;
-}
-
-static int parse_slave_configs(snd_sof_plug_t *plug, snd_config_t *n)
-{
-	snd_config_iterator_t si1, si2, snext1, snext2;
-	struct plug_config *config;
-	const char *id;
-
-	fprintf(stdout, "Parsing ALSA conf for configs\n");
-
-	snd_config_for_each(si1, snext1, n) {
-		snd_config_t *sn1 = snd_config_iterator_entry(si1);
-
-		config = &plug->config[plug->num_configs];
-
-		/* get config name */
-		if (parse_item(sn1, "name", config) < 0) {
-			SNDERR("error: cant find config name");
-			return -EINVAL;
-		}
-
-		/* now get item values in each config */
-		snd_config_for_each(si2, snext2, sn1) {
-			snd_config_t *sn2 = snd_config_iterator_entry(si2);
-
-			if (snd_config_get_id(sn2, &id) < 0)
-				continue;
-
-			if (parse_item(sn2, id, config) < 0) {
-				SNDERR("error: malformed config:  %s", id);
-				return -EINVAL;
-			}
-		}
-
-		fprintf(stdout, " config %d: %s\n", plug->num_configs,
-			config->name);
-
-		/* next config */
-		plug->num_configs++;
-		if (plug->num_configs >= PLUG_MAX_CONFIG) {
-			SNDERR("error: too many configs");
-			return -EINVAL;
-		}
-	}
-
-	return 0;
-}
-
-/*
- * Parse the client cmdline. Format is
- * tplg:pcm:card:dev:config[dai_pipe:card:dev:config]...]
- */
-static int parse_client_cmdline(snd_sof_plug_t *plug, char *cmdline, bool just_tplg)
-{
-	struct plug_cmdline_item *cmd_item;
-	char *tplg, *next, *card, *dev, *config, *pcm;
-	char *tplg_path = getenv("SOF_PLUGIN_TOPOLOGY_PATH");
-	char tplg_file[128];
-	int ret;
-	int i;
-
-	if (!tplg_path) {
-		SNDERR("Invalid topology path. Please set the SOF_PLUGIN_TOPOLOGY_PATH env variable\n");
-		return -EINVAL;
-	}
-
-	/* get topology file */
-	tplg = strtok_r(cmdline, ":", &next);
-	if (!tplg) {
-		SNDERR("invalid cmdline, cant find topology %s", cmdline);
-		return -EINVAL;
-	}
-
-	/* now convert to filename and add the topology path */
-	ret = snprintf(tplg_file, sizeof(tplg_file), "%ssof-%s.tplg", tplg_path, tplg);
-	if (ret < 0) {
-		SNDERR("invalid cmdline topology file %s", tplg);
-		return -EINVAL;
-	}
-	plug->tplg_file = strdup(tplg_file);
-	if (!plug->tplg_file)
-		return -ENOMEM;
-
-	if (just_tplg)
-		return 0;
-
-	/* get PCM ID */
-	pcm = strtok_r(next, ":", &next);
-	if (!pcm) {
-		SNDERR("invalid cmdline, cant find PCM %s", pcm);
-		return -EINVAL;
-	}
-	plug->pcm_id = atoi(pcm);
-
-	fprintf(stdout, "Parsing cmd line\n");
-
-	cmd_item = &plug->cmdline[plug->num_cmdline];
-	card = strtok_r(next, ":", &next);
-	/* card/dev names and config are all optional */
-	if (!card) {
-		strncpy(cmd_item->card_name, "default", sizeof(cmd_item->card_name));
-		strncpy(cmd_item->dev_name, "default", sizeof(cmd_item->dev_name));
-		fprintf(stdout, "no config name provided, will use hw_params\n");
-	} else {
-		strncpy(cmd_item->card_name, card, sizeof(cmd_item->card_name));
-		dev = strtok_r(next, ":", &next);
-		/* dev name must be provided along with card name */
-		if (!dev) {
-			SNDERR("Invalid dev name\n");
-			return -EINVAL;
-		}
-		strncpy(cmd_item->dev_name, dev, sizeof(cmd_item->dev_name));
-		config = strtok_r(next, ":", &next);
-		/* config name is optional */
-		if (!config)
-			fprintf(stdout, "no config name provided, will use hw_params\n");
-		else
-			strncpy(cmd_item->config_name, config, sizeof(cmd_item->config_name));
-	}
-
-	cmd_item->pcm = atoi(pcm);
-
-	/*
-	 * dev name is special, we cant use "," in the command line
-	 * so need to replace it with a "." and then later change it
-	 * back to ","
-	 */
-	for (i = 0; i < sizeof(cmd_item->dev_name); i++) {
-		if (cmd_item->dev_name[i] != '.')
-			continue;
-		cmd_item->dev_name[i] = ',';
-		break;
-	}
-
-	fprintf(stdout, " cmd %d: for pcm %d uses %s with PCM %s:%s\n",
-		plug->num_cmdline, cmd_item->pcm, cmd_item->config_name,
-		cmd_item->card_name, cmd_item->dev_name);
-
-	plug->num_cmdline++;
-
-	printf("plug: topology file %s with pipe %ld\n", plug->tplg_file, plug->tplg_pipeline);
-	return 0;
-}
-
-/*
- * Parse the ALSA conf for the SOF plugin and construct the command line options
- * to be passed into the SOF pipe executable.
- * TODO: verify all args
- * TODO: validate all args.
- * TODO: contruct sof pipe cmd line.
- */
-int plug_parse_conf(snd_sof_plug_t *plug, const char *name, snd_config_t *root,
-		    snd_config_t *conf, bool just_tplg)
-{
-	snd_config_iterator_t i, next;
-	const char *tplg = NULL;
-
-	/*
-	 * The topology filename and topology PCM need to be passed in.
-	 * i.e. aplay -Dsof:tplg:pcm:[card:dev:config]...]
-	 */
-	snd_config_for_each(i, next, conf) {
-		snd_config_t *n = snd_config_iterator_entry(i);
-		const char *id;
-
-		if (snd_config_get_id(n, &id) < 0)
-			continue;
-
-		/* dont care */
-		if (strcmp(id, "comment") == 0 || strcmp(id, "type") == 0 ||
-		    strcmp(id, "hint") == 0)
-			continue;
-
-		/* client command line topology */
-		if (strcmp(id, "tplg") == 0) {
-			if (snd_config_get_string(n, &tplg) < 0) {
-				SNDERR("Invalid type for %s", id);
-				return -EINVAL;
-			} else if (!*tplg) {
-				tplg = NULL;
-			}
-			continue;
-		}
-
-		/* topology PCM configurations */
-		if (strcmp(id, "config") == 0) {
-			if (parse_slave_configs(plug, n))
-				return -EINVAL;
-			continue;
-		}
-
-		/* not fatal - carry on and verify later */
-		SNDERR("Unknown field %s", id);
-	}
-
-	/* verify mandatory inputs are specified */
-	if (!tplg) {
-		SNDERR("Missing topology topology");
-		return -EINVAL;
-	}
-
-	/* parse the client command line */
-	if (parse_client_cmdline(plug, (char *)tplg, just_tplg)) {
-		SNDERR("invalid sof cmd line");
-		return -EINVAL;
-	}
-
-	return 0;
-}
diff --git a/tools/plugin/alsaplug/plugin.h b/tools/plugin/alsaplug/plugin.h
deleted file mode 100644
index 7f4009267d24..000000000000
--- a/tools/plugin/alsaplug/plugin.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- *
- * Copyright(c) 2022-2023 Intel Corporation. All rights reserved.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#ifndef __SOF_PLUGIN_PLUGIN_H__
-#define __SOF_PLUGIN_PLUGIN_H__
-
-#include <alsa/asoundlib.h>
-#include <sof/list.h>
-#include "common.h"
-
-#include <tplg_parser/topology.h>
-
-#define PLUG_MAX_CONFIG	128
-
-typedef struct snd_sof_plug {
-	/* conf data */
-	char *device;
-
-	/* topology info */
-	char *tplg_file;
-	long tplg_pipeline; // HACK, use configs
-
-	/* number of configurations in plugin conf */
-	struct plug_config config[PLUG_MAX_CONFIG];
-	int num_configs;
-
-	/* command line arguments */
-	struct plug_cmdline_item cmdline[PLUG_MAX_CONFIG];
-	int num_cmdline;
-
-	/* topology */
-	struct tplg_context tplg;
-	struct list_item widget_list;
-	struct list_item route_list;
-	struct list_item pcm_list;
-	struct list_item pipeline_list;
-	int instance_ids[SND_SOC_TPLG_DAPM_LAST];
-	struct plug_socket_desc ipc;
-
-	struct plug_shm_desc glb_ctx;
-
-	int pcm_id;
-	struct tplg_pcm_info *pcm_info;
-
-	snd_pcm_uframes_t period_size;
-
-	void *module_prv;	/* module private data */
-} snd_sof_plug_t;
-
-/*
- * ALSA Conf
- */
-int sofplug_load_hook(snd_config_t *root, snd_config_t *config,
-		      snd_config_t **dst, snd_config_t *private_data);
-
-int plug_parse_conf(snd_sof_plug_t *plug, const char *name,
-		    snd_config_t *root, snd_config_t *conf, bool just_tplg);
-int plug_parse_topology(snd_sof_plug_t *plug);
-int plug_set_up_pipelines(snd_sof_plug_t *plug, int dir, snd_pcm_hw_params_t *params);
-int plug_free_pipelines(snd_sof_plug_t *plug, struct tplg_pipeline_list *pipeline_list, int dir);
-void plug_free_topology(snd_sof_plug_t *plug);
-int plug_kcontrol_cb_new(struct snd_soc_tplg_ctl_hdr *tplg_ctl, void *_comp, void *arg, int index);
-
-#endif
diff --git a/tools/plugin/alsaplug/tplg.c b/tools/plugin/alsaplug/tplg.c
deleted file mode 100644
index 140a0aac91c6..000000000000
--- a/tools/plugin/alsaplug/tplg.c
+++ /dev/null
@@ -1,1560 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-//
-// Copyright(c) 2018 Intel Corporation. All rights reserved.
-//
-// Author: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
-//         Liam Girdwood <liam.r.girdwood@linux.intel.com>
-
-/* Topology loader to set up components and pipeline */
-
-#include <stdio.h>
-#include <sys/poll.h>
-#include <string.h>
-#include <sys/types.h>
-#include <unistd.h>
-#include <stdlib.h>
-#include <sys/wait.h>
-#include <sys/stat.h>
-#include <signal.h>
-#include <fcntl.h>
-#include <sys/mman.h>
-#include <semaphore.h>
-#include <assert.h>
-#include <errno.h>
-#include <dlfcn.h>
-#include <kernel/header.h>
-
-#include <ipc4/error_status.h>
-
-#include <tplg_parser/topology.h>
-#include <tplg_parser/tokens.h>
-
-#include <alsa/asoundlib.h>
-#include <alsa/control_external.h>
-#include <alsa/pcm_external.h>
-
-#include "plugin.h"
-
-#define FILE_READ 0
-#define FILE_WRITE 1
-
-#define MAX_TPLG_OBJECT_SIZE	4096
-
-//#include <sound/asound.h>
-
-/* temporary - current MAXLEN is not define in UAPI header - fix pending */
-#ifndef SNDRV_CTL_ELEM_ID_NAME_MAXLEN
-#define SNDRV_CTL_ELEM_ID_NAME_MAXLEN	44
-#endif
-#include <alsa/sound/asoc.h>
-
-#define SOF_IPC4_FW_PAGE(x) ((((x) + BIT(12) - 1) & ~(BIT(12) - 1)) >> 12)
-#define SOF_IPC4_FW_ROUNDUP(x) (((x) + BIT(6) - 1) & (~(BIT(6) - 1)))
-#define SOF_IPC4_MODULE_INSTANCE_LIST_ITEM_SIZE 12
-#define SOF_IPC4_PIPELINE_OBJECT_SIZE 448
-#define SOF_IPC4_DATA_QUEUE_OBJECT_SIZE 128
-#define SOF_IPC4_LL_TASK_OBJECT_SIZE 72
-#define SOF_IPC4_LL_TASK_LIST_ITEM_SIZE 12
-#define SOF_IPC4_FW_MAX_QUEUE_COUNT 8
-
-static const struct sof_topology_token ipc4_comp_tokens[] = {
-	{SOF_TKN_COMP_IS_PAGES, SND_SOC_TPLG_TUPLE_TYPE_WORD, tplg_token_get_uint32_t,
-		offsetof(struct ipc4_base_module_cfg, is_pages)},
-};
-
-static int plug_parse_ipc4_comp_tokens(snd_sof_plug_t *plug, struct ipc4_base_module_cfg *base_cfg)
-{
-	struct tplg_context *ctx = &plug->tplg;
-	struct tplg_comp_info *comp_info = ctx->current_comp_info;
-	struct snd_soc_tplg_vendor_array *array = &ctx->widget->priv.array[0];
-	int size = ctx->widget->priv.size;
-	int ret;
-
-	ret = sof_parse_token_sets(base_cfg, ipc4_comp_tokens, ARRAY_SIZE(ipc4_comp_tokens),
-				   array, size, 1, 0);
-	if (ret < 0)
-		return ret;
-
-	return sof_parse_tokens(&comp_info->uuid, comp_ext_tokens,
-			       ARRAY_SIZE(comp_ext_tokens), array, size);
-}
-
-static void plug_setup_widget_ipc_msg(struct tplg_comp_info *comp_info)
-{
-	struct ipc4_module_init_instance *module_init = &comp_info->module_init;
-
-	module_init->primary.r.type = SOF_IPC4_MOD_INIT_INSTANCE;
-	module_init->primary.r.module_id = comp_info->module_id;
-	module_init->primary.r.instance_id = comp_info->instance_id;
-	module_init->primary.r.msg_tgt = SOF_IPC4_MESSAGE_TARGET_MODULE_MSG;
-	module_init->primary.r.rsp = SOF_IPC4_MESSAGE_DIR_MSG_REQUEST;
-}
-
-static int plug_aif_in_out(snd_sof_plug_t *plug, int dir)
-{
-	struct tplg_context *ctx = &plug->tplg;
-	struct tplg_comp_info *comp_info = ctx->current_comp_info;
-	int ret;
-
-	ret = tplg_parse_widget_audio_formats(ctx);
-	if (ret < 0)
-		return ret;
-
-	comp_info->ipc_size = sizeof(struct ipc4_base_module_cfg) + sizeof(struct sof_uuid);
-	comp_info->ipc_payload =  calloc(comp_info->ipc_size, 1);
-	if (!comp_info->ipc_payload)
-		return -ENOMEM;
-
-	/* overwrite the topology UUIDs with the SHM module UUID for the host components */
-	if (dir == SOF_IPC_STREAM_PLAYBACK) {
-		struct sof_uuid uuid = {.a = 0xe2b6031c, .b = 0x47e8, .c = 0x11ed,
-					.d = { 0x07, 0xa9, 0x7f, 0x80, 0x1b, 0x6e, 0xfa, 0x6c }};
-		comp_info->module_id = 0x96;
-		plug_setup_widget_ipc_msg(comp_info);
-		comp_info->uuid = uuid;
-	} else {
-		struct sof_uuid uuid = {.a = 0xdabe8814, .b = 0x47e8, .c = 0x11ed,
-					.d = { 0xa5, 0x8b, 0xb3, 0x09, 0x97, 0x4f, 0xec, 0xce }};
-		comp_info->module_id = 0x98;
-		plug_setup_widget_ipc_msg(comp_info);
-		comp_info->uuid = uuid;
-	}
-
-	/* copy uuid to the end of the payload */
-	memcpy(comp_info->ipc_payload + sizeof(struct ipc4_base_module_cfg), &comp_info->uuid,
-	       sizeof(struct sof_uuid));
-
-	return 0;
-}
-
-static int plug_dai_in_out(snd_sof_plug_t *plug, int dir)
-{
-	struct tplg_context *ctx = &plug->tplg;
-	struct tplg_comp_info *comp_info = ctx->current_comp_info;
-	int ret;
-
-	ret = tplg_parse_widget_audio_formats(ctx);
-	if (ret < 0)
-		return ret;
-
-	comp_info->ipc_size = sizeof(struct ipc4_base_module_cfg) + sizeof(struct sof_uuid);
-	comp_info->ipc_payload =  calloc(comp_info->ipc_size, 1);
-	if (!comp_info->ipc_payload)
-		return -ENOMEM;
-
-	/* overwrite the topology UUIDs with the ALSA module UUID for the DAI components */
-	if (dir == SOF_IPC_STREAM_PLAYBACK) {
-		struct sof_uuid uuid = {.a = 0x72cee996, .b = 0x39f2, .c = 0x11ed,
-					.d = { 0xa0, 0x8f, 0x97, 0xfc, 0xc4, 0x2e, 0xaa, 0xeb }};
-
-		comp_info->module_id = 0x97;
-		plug_setup_widget_ipc_msg(comp_info);
-		comp_info->uuid = uuid;
-	} else {
-		struct sof_uuid uuid = {.a = 0x66def9f0, .b = 0x39f2, .c = 0x11ed,
-					.d = { 0xf7, 0x89, 0xaf, 0x98, 0xa6, 0x44, 0x0c, 0xc4 }};
-
-		comp_info->module_id = 0x99;
-		plug_setup_widget_ipc_msg(comp_info);
-		comp_info->uuid = uuid;
-	}
-
-	/* copy uuid to the end of the payload */
-	memcpy(comp_info->ipc_payload + sizeof(struct ipc4_base_module_cfg), &comp_info->uuid,
-	       sizeof(struct sof_uuid));
-
-	return 0;
-}
-
-static int plug_new_src_ipc(snd_sof_plug_t *plug)
-{
-	struct tplg_context *ctx = &plug->tplg;
-	char tplg_object[MAX_TPLG_OBJECT_SIZE] = {0};
-	struct sof_ipc_comp_src *src =
-		(struct sof_ipc_comp_src *)tplg_object;
-	struct snd_soc_tplg_ctl_hdr *tplg_ctl;
-	int ret;
-
-	tplg_ctl = calloc(ctx->hdr->payload_size, 1);
-	if (!tplg_ctl)
-		return -ENOMEM;
-
-	ret = tplg_new_src(ctx, &src->comp, MAX_TPLG_OBJECT_SIZE,
-			   tplg_ctl, ctx->hdr->payload_size);
-	if (ret < 0) {
-		SNDERR("error: failed to create src\n");
-		goto out;
-	}
-
-out:
-	free(tplg_ctl);
-	return ret;
-}
-
-static int plug_new_asrc_ipc(snd_sof_plug_t *plug)
-{
-	struct tplg_context *ctx = &plug->tplg;
-	char tplg_object[MAX_TPLG_OBJECT_SIZE] = {0};
-	struct sof_ipc_comp_asrc *asrc =
-		(struct sof_ipc_comp_asrc *)tplg_object;
-	struct snd_soc_tplg_ctl_hdr *tplg_ctl;
-	int ret;
-
-	tplg_ctl = calloc(ctx->hdr->payload_size, 1);
-	if (!tplg_ctl)
-		return -ENOMEM;
-
-	ret = tplg_new_asrc(ctx, &asrc->comp, MAX_TPLG_OBJECT_SIZE,
-			    tplg_ctl, ctx->hdr->payload_size);
-	if (ret < 0) {
-		SNDERR("error: failed to create PGA\n");
-		goto out;
-	}
-
-out:
-	free(tplg_ctl);
-	return ret;
-}
-
-static int plug_new_mixer(snd_sof_plug_t *plug)
-{
-	struct tplg_context *ctx = &plug->tplg;
-	struct tplg_comp_info *comp_info = ctx->current_comp_info;
-	char tplg_object[MAX_TPLG_OBJECT_SIZE] = {0};
-	struct sof_ipc_comp_mixer *mixer =
-		(struct sof_ipc_comp_mixer *)tplg_object;
-	struct snd_soc_tplg_ctl_hdr *tplg_ctl;
-	int ret;
-
-	tplg_ctl = calloc(ctx->hdr->payload_size, 1);
-	if (!tplg_ctl)
-		return -ENOMEM;
-
-	comp_info->instance_id = plug->instance_ids[SND_SOC_TPLG_DAPM_MIXER]++;
-	comp_info->ipc_size = sizeof(struct ipc4_base_module_cfg) + sizeof(struct sof_uuid);
-	comp_info->ipc_payload = calloc(comp_info->ipc_size, 1);
-	if (!comp_info->ipc_payload)
-		return -ENOMEM;
-
-	ret = tplg_new_mixer(ctx, &mixer->comp, MAX_TPLG_OBJECT_SIZE,
-			     tplg_ctl, ctx->hdr->payload_size);
-	if (ret < 0) {
-		SNDERR("error: failed to create mixer\n");
-		goto out;
-	}
-
-	if (strstr(comp_info->name, "mixin")) {
-		comp_info->module_id = 0x2;
-		plug_setup_widget_ipc_msg(comp_info);
-	} else {
-		comp_info->module_id = 0x3;
-		plug_setup_widget_ipc_msg(comp_info);
-	}
-
-	/* copy uuid to the end of the payload */
-	memcpy(comp_info->ipc_payload + sizeof(struct ipc4_base_module_cfg), &comp_info->uuid,
-	       sizeof(struct sof_uuid));
-out:
-	free(tplg_ctl);
-	return ret;
-}
-
-static int plug_new_pga(snd_sof_plug_t *plug)
-{
-	struct tplg_context *ctx = &plug->tplg;
-	struct tplg_comp_info *comp_info = ctx->current_comp_info;
-	struct ipc4_peak_volume_config volume;
-	struct snd_soc_tplg_ctl_hdr *tplg_ctl;
-	uint32_t uuid_offset;
-	int ret;
-
-	comp_info->ipc_size = sizeof(struct ipc4_peak_volume_config);
-	comp_info->ipc_size += sizeof(struct ipc4_base_module_cfg);
-	uuid_offset = comp_info->ipc_size;
-	comp_info->ipc_size += sizeof(struct sof_uuid);
-	comp_info->ipc_payload = calloc(comp_info->ipc_size, 1);
-	if (!comp_info->ipc_payload)
-		return -ENOMEM;
-
-	/* FIXME: move this to when the widget is actually set up */
-	comp_info->instance_id = plug->instance_ids[SND_SOC_TPLG_DAPM_PGA]++;
-	comp_info->module_id = 0x6;
-
-	tplg_ctl = calloc(ctx->hdr->payload_size, 1);
-	if (!tplg_ctl) {
-		free(comp_info->ipc_payload);
-		return -ENOMEM;
-	}
-
-	ret = tplg_new_pga(ctx, &volume, sizeof(struct ipc4_peak_volume_config),
-			   tplg_ctl, ctx->hdr->payload_size);
-	if (ret < 0) {
-		SNDERR("%s: failed to create PGA\n", __func__);
-		goto out;
-	}
-
-	/* copy volume data to ipc_payload */
-	memcpy(comp_info->ipc_payload + sizeof(struct ipc4_base_module_cfg),
-	       &volume, sizeof(struct ipc4_peak_volume_config));
-
-	/* copy uuid to the end of the payload */
-	memcpy(comp_info->ipc_payload + uuid_offset, &comp_info->uuid, sizeof(struct sof_uuid));
-
-	/* skip kcontrols for now */
-	if (tplg_create_controls(ctx, ctx->widget->num_kcontrols,
-				 tplg_ctl, ctx->hdr->payload_size, comp_info) < 0) {
-		SNDERR("error: loading controls\n");
-		goto out;
-	}
-
-	plug_setup_widget_ipc_msg(comp_info);
-
-	free(tplg_ctl);
-
-	return ret;
-
-out:
-	free(tplg_ctl);
-	free(comp_info->ipc_payload);
-
-	return ret;
-}
-
-static int plug_new_process(snd_sof_plug_t *plug)
-{
-	struct tplg_context *ctx = &plug->tplg;
-	struct tplg_comp_info *comp_info = ctx->current_comp_info;
-	struct ipc4_base_module_cfg basecfg;
-	struct snd_soc_tplg_ctl_hdr *tplg_ctl;
-	int ret;
-
-	ret = tplg_parse_widget_audio_formats(ctx);
-	if (ret < 0)
-		return ret;
-
-	/* only base config supported for now. extn support will be added later */
-	comp_info->ipc_size = sizeof(struct ipc4_base_module_cfg) + sizeof(struct sof_uuid);
-	comp_info->ipc_payload = calloc(comp_info->ipc_size, 1);
-	if (!comp_info->ipc_payload)
-		return -ENOMEM;
-
-	/* FIXME: move this to when the widget is actually set up */
-	comp_info->instance_id = plug->instance_ids[SND_SOC_TPLG_DAPM_EFFECT]++;
-	comp_info->module_id = 0x95;
-
-	plug_setup_widget_ipc_msg(comp_info);
-
-	tplg_ctl = calloc(ctx->hdr->payload_size, 1);
-	if (!tplg_ctl) {
-		free(comp_info->ipc_payload);
-		return -ENOMEM;
-	}
-
-	/* copy uuid to the end of the payload */
-	memcpy(comp_info->ipc_payload + sizeof(struct ipc4_base_module_cfg), &comp_info->uuid,
-	       sizeof(struct sof_uuid));
-
-	/* set up kcontrols */
-	ret = tplg_create_controls(ctx, ctx->widget->num_kcontrols,
-				   tplg_ctl, ctx->hdr->payload_size, comp_info);
-	if (ret  < 0) {
-		SNDERR("failed to create controls for process comp\n");
-		free(comp_info->ipc_payload);
-	}
-
-	free(tplg_ctl);
-	return ret;
-}
-
-static int plug_new_pipeline(snd_sof_plug_t *plug)
-{
-	struct tplg_pipeline_info *pipe_info;
-	struct sof_ipc_pipe_new pipeline = {0};
-	struct snd_soc_tplg_ctl_hdr *tplg_ctl;
-	struct tplg_context *ctx = &plug->tplg;
-	int ret;
-
-	tplg_ctl = calloc(ctx->hdr->payload_size, 1);
-	if (!tplg_ctl)
-		return -ENOMEM;
-
-	pipe_info = calloc(sizeof(struct tplg_pipeline_info), 1);
-	if (!pipe_info) {
-		ret = -ENOMEM;
-		goto out;
-	}
-
-	pipe_info->name = strdup(ctx->widget->name);
-	if (!pipe_info->name) {
-		free(pipe_info);
-		goto out;
-	}
-
-	pipe_info->id = ctx->pipeline_id;
-
-	ret = tplg_new_pipeline(ctx, &pipeline, sizeof(pipeline), tplg_ctl);
-	if (ret < 0) {
-		SNDERR("error: failed to create pipeline\n");
-		free(pipe_info->name);
-		free(pipe_info);
-		goto out;
-	}
-
-	list_item_append(&pipe_info->item, &plug->pipeline_list);
-	tplg_debug("loading pipeline %s\n", pipe_info->name);
-out:
-	free(tplg_ctl);
-	return ret;
-}
-
-static int plug_new_buffer(snd_sof_plug_t *plug)
-{
-	struct ipc4_copier_module_cfg *copier = calloc(sizeof(struct ipc4_copier_module_cfg), 1);
-	struct tplg_context *ctx = &plug->tplg;
-	struct tplg_comp_info *comp_info = ctx->current_comp_info;
-	int ret;
-
-	if (!copier)
-		return -ENOMEM;
-
-	comp_info->ipc_payload = copier;
-
-	ret = tplg_new_buffer(ctx, copier, sizeof(copier), NULL, 0);
-	if (ret < 0) {
-		SNDERR("error: failed to create pipeline\n");
-		free(copier);
-	}
-
-	return ret;
-}
-
-/* Insert new comp info into the list of widgets */
-static inline int plug_insert_comp(snd_sof_plug_t *plug)
-{
-	struct tplg_context *ctx = &plug->tplg;
-	struct tplg_comp_info *comp_info;
-	int comp_id = ctx->comp_id;
-	int ret;
-
-	if (ctx->widget->id == SND_SOC_TPLG_DAPM_SCHEDULER)
-		return 0;
-
-	comp_info = calloc(sizeof(struct tplg_comp_info), 1);
-	if (!comp_info)
-		return -ENOMEM;
-
-	comp_info->name = strdup(ctx->widget->name);
-	if (!comp_info->name) {
-		ret = -ENOMEM;
-		goto err;
-	}
-
-	comp_info->stream_name = strdup(ctx->widget->sname);
-	if (!comp_info->stream_name) {
-		ret = -ENOMEM;
-		goto sname_err;
-	}
-
-	comp_info->id = comp_id;
-	comp_info->type = ctx->widget->id;
-	comp_info->pipeline_id = ctx->pipeline_id;
-	ctx->current_comp_info = comp_info;
-
-	ret = plug_parse_ipc4_comp_tokens(plug, &comp_info->basecfg);
-	if (ret < 0)
-		goto sname_err;
-
-	list_item_append(&comp_info->item, &plug->widget_list);
-
-	tplg_debug("debug: loading comp_id %d: widget %s type %d size %d at offset %ld is_pages %d\n",
-		   comp_id, ctx->widget->name, ctx->widget->id, ctx->widget->size,
-		   ctx->tplg_offset, comp_info->basecfg.is_pages);
-
-	return 0;
-sname_err:
-	free(comp_info->name);
-err:
-	free(comp_info);
-	return ret;
-}
-
-/* load dapm widget */
-static int plug_load_widget(snd_sof_plug_t *plug)
-{
-	struct tplg_context *ctx = &plug->tplg;
-	int ret = 0;
-
-	/* get next widget */
-	ctx->widget = tplg_get_widget(ctx);
-	ctx->widget_size = ctx->widget->size;
-
-	/* insert widget into mapping */
-	ret = plug_insert_comp(plug);
-	if (ret < 0) {
-		SNDERR("plug_load_widget: invalid widget index\n");
-		return ret;
-	}
-
-	/* load widget based on type */
-	switch (ctx->widget->id) {
-	/* load pga widget */
-	case SND_SOC_TPLG_DAPM_PGA:
-		if (plug_new_pga(plug) < 0) {
-			SNDERR("error: load pga\n");
-			ret = -EINVAL;
-			goto exit;
-		}
-		break;
-	case SND_SOC_TPLG_DAPM_AIF_IN:
-		if (plug_aif_in_out(plug, SOF_IPC_STREAM_PLAYBACK) < 0) {
-			SNDERR("error: load AIF IN failed\n");
-			ret = -EINVAL;
-			goto exit;
-		}
-		break;
-	case SND_SOC_TPLG_DAPM_AIF_OUT:
-		if (plug_aif_in_out(plug, SOF_IPC_STREAM_CAPTURE) < 0) {
-			SNDERR("error: load AIF OUT failed\n");
-			ret = -EINVAL;
-			goto exit;
-		}
-		break;
-	case SND_SOC_TPLG_DAPM_DAI_IN:
-		if (plug_dai_in_out(plug, SOF_IPC_STREAM_PLAYBACK) < 0) {
-			SNDERR("error: load filewrite\n");
-			ret = -EINVAL;
-			goto exit;
-		}
-		break;
-	case SND_SOC_TPLG_DAPM_DAI_OUT:
-		if (plug_dai_in_out(plug, SOF_IPC_STREAM_CAPTURE) < 0) {
-			SNDERR("error: load filewrite\n");
-			ret = -EINVAL;
-			goto exit;
-		}
-		break;
-
-	case SND_SOC_TPLG_DAPM_BUFFER:
-		if (plug_new_buffer(plug) < 0) {
-			SNDERR("error: load pipeline\n");
-			ret = -EINVAL;
-			goto exit;
-		}
-		break;
-
-	case SND_SOC_TPLG_DAPM_SCHEDULER:
-		if (plug_new_pipeline(plug) < 0) {
-			SNDERR("error: load pipeline\n");
-			ret = -EINVAL;
-			goto exit;
-		}
-		break;
-	case SND_SOC_TPLG_DAPM_SRC:
-		if (plug_new_src_ipc(plug) < 0) {
-			SNDERR("error: load src\n");
-			ret = -EINVAL;
-			goto exit;
-		}
-		break;
-	case SND_SOC_TPLG_DAPM_ASRC:
-		if (plug_new_asrc_ipc(plug) < 0) {
-			SNDERR("error: load asrc\n");
-			ret = -EINVAL;
-			goto exit;
-		}
-		break;
-
-	case SND_SOC_TPLG_DAPM_MIXER:
-		if (plug_new_mixer(plug) < 0) {
-			SNDERR("error: load mixer\n");
-			ret = -EINVAL;
-			goto exit;
-		}
-		break;
-	case SND_SOC_TPLG_DAPM_EFFECT:
-		if (plug_new_process(plug) < 0) {
-			SNDERR("error: load effect\n");
-			ret = -EINVAL;
-			goto exit;
-		}
-		break;
-
-	/* unsupported widgets */
-	default:
-		tplg_debug("info: Widget %s id %d unsupported and skipped: size %d priv size %d\n",
-			   ctx->widget->name, ctx->widget->id,
-			   ctx->widget->size, ctx->widget->priv.size);
-
-#if 0
-		if (fseek(ctx->file, ctx->widget->priv.size, SEEK_CUR)) {
-			SNDERR("error: fseek unsupported widget\n");
-			ret = -errno;
-			goto exit;
-		}
-		ret = tplg_create_controls(ctx->widget->num_kcontrols, ctx->file, NULL, 0);
-		if (ret < 0) {
-			SNDERR("error: loading controls\n");
-			//goto exit;
-		}
-#endif
-		ret = 0;
-		break;
-	}
-
-	ret = 1;
-
-exit:
-	return ret;
-}
-
-static int plug_register_graph(snd_sof_plug_t *plug, int count)
-{
-	struct tplg_context *ctx = &plug->tplg;
-	int ret = 0;
-	int i;
-
-	for (i = 0; i < count; i++) {
-		ret = tplg_parse_graph(ctx, &plug->widget_list, &plug->route_list);
-		if (ret < 0)
-			return ret;
-	}
-
-	return ret;
-}
-
-static int plug_parse_pcm(snd_sof_plug_t *plug, int count)
-{
-	struct tplg_context *ctx = &plug->tplg;
-	int ret, i;
-
-	for (i = 0; i < count; i++) {
-		ret = tplg_parse_pcm(ctx, &plug->widget_list, &plug->pcm_list);
-		if (ret < 0)
-			return ret;
-	}
-
-	return 0;
-}
-
-static void
-plug_pipeline_update_resource_usage(snd_sof_plug_t *plug, struct tplg_comp_info *comp_info)
-{
-	struct ipc4_base_module_cfg *base_config = &comp_info->basecfg;
-	struct tplg_pipeline_info *pipe_info = comp_info->pipe_info;
-	int task_mem, queue_mem;
-	int ibs, bss, total;
-
-	ibs = base_config->ibs;
-	bss = base_config->is_pages;
-
-	task_mem = SOF_IPC4_PIPELINE_OBJECT_SIZE;
-	task_mem += SOF_IPC4_MODULE_INSTANCE_LIST_ITEM_SIZE + bss;
-
-	/* LL modules */
-	task_mem += SOF_IPC4_FW_ROUNDUP(SOF_IPC4_LL_TASK_OBJECT_SIZE);
-	task_mem += SOF_IPC4_FW_MAX_QUEUE_COUNT * SOF_IPC4_MODULE_INSTANCE_LIST_ITEM_SIZE;
-	task_mem += SOF_IPC4_LL_TASK_LIST_ITEM_SIZE;
-
-	ibs = SOF_IPC4_FW_ROUNDUP(ibs);
-	queue_mem = SOF_IPC4_FW_MAX_QUEUE_COUNT * (SOF_IPC4_DATA_QUEUE_OBJECT_SIZE +  ibs);
-
-	total = SOF_IPC4_FW_PAGE(task_mem + queue_mem);
-
-	pipe_info->mem_usage += total;
-}
-
-static int plug_is_single_format(struct sof_ipc4_pin_format *fmts, int num_formats)
-{
-	struct sof_ipc4_pin_format *fmt = &fmts[0];
-	uint32_t _rate, _channels, _valid_bits;
-	int i;
-
-	_rate = fmt->audio_fmt.sampling_frequency;
-	_channels = fmt->audio_fmt.fmt_cfg & MASK(7, 0);
-	_valid_bits = (fmt->audio_fmt.fmt_cfg & MASK(15, 8)) >> 8;
-	for (i = 1; i < num_formats; i++) {
-		struct sof_ipc4_pin_format *fmt = &fmts[i];
-		uint32_t rate, channels, valid_bits;
-
-		rate = fmt->audio_fmt.sampling_frequency;
-		channels = fmt->audio_fmt.fmt_cfg & MASK(7, 0);
-		valid_bits = (fmt->audio_fmt.fmt_cfg & MASK(15, 8)) >> 8;
-		if (rate != _rate || channels != _channels || valid_bits != _valid_bits)
-			return false;
-	}
-
-	return true;
-}
-
-static int plug_match_audio_format(snd_sof_plug_t *plug, struct tplg_comp_info *comp_info,
-				   snd_pcm_hw_params_t *params)
-{
-	struct sof_ipc4_available_audio_format *available_fmt = &comp_info->available_fmt;
-	struct ipc4_base_module_cfg *base_cfg = &comp_info->basecfg;
-	struct sof_ipc4_pin_format *fmt;
-	snd_pcm_format_t params_format;
-	unsigned int params_channels, params_rate, dir;
-	int params_valid_bits;
-	int i;
-
-	snd_pcm_hw_params_get_channels(params, &params_channels);
-	snd_pcm_hw_params_get_rate(params, &params_rate, &dir);
-	snd_pcm_hw_params_get_format(params, &params_format);
-
-	switch (params_format) {
-	case SND_PCM_FORMAT_S16_LE:
-		params_valid_bits = 16;
-		break;
-	case SND_PCM_FORMAT_S32_LE:
-		params_valid_bits = 32;
-		break;
-	case SND_PCM_FORMAT_S24_LE:
-		params_valid_bits = 24;
-		break;
-	default:
-		break;
-	}
-
-	if (plug_is_single_format(available_fmt->input_pin_fmts,
-				  available_fmt->num_input_formats)) {
-		fmt = &available_fmt->input_pin_fmts[0];
-		goto out;
-	}
-
-	for (i = 0; i < available_fmt->num_input_formats; i++) {
-		uint32_t rate, channels, valid_bits;
-
-		fmt = &available_fmt->input_pin_fmts[i];
-
-		rate = fmt->audio_fmt.sampling_frequency;
-		channels = fmt->audio_fmt.fmt_cfg & MASK(7, 0);
-		valid_bits = (fmt->audio_fmt.fmt_cfg & MASK(15, 8)) >> 8;
-
-		if (rate == params_rate && channels == params_channels &&
-		    valid_bits == params_valid_bits)
-			break;
-	}
-
-	if (i == available_fmt->num_input_formats) {
-		SNDERR("Cannot find matching format for rate %d channels %d valid_bits %d for %s\n",
-		       params_rate, params_channels, params_valid_bits, comp_info->name);
-		return -EINVAL;
-	}
-out:
-
-	base_cfg->audio_fmt.sampling_frequency = fmt->audio_fmt.sampling_frequency;
-	base_cfg->audio_fmt.depth = fmt->audio_fmt.bit_depth;
-	base_cfg->audio_fmt.ch_map = fmt->audio_fmt.ch_map;
-	base_cfg->audio_fmt.ch_cfg = fmt->audio_fmt.ch_cfg;
-	base_cfg->audio_fmt.interleaving_style = fmt->audio_fmt.interleaving_style;
-	base_cfg->audio_fmt.channels_count = fmt->audio_fmt.fmt_cfg & MASK(7, 0);
-	base_cfg->audio_fmt.valid_bit_depth =
-		(fmt->audio_fmt.fmt_cfg & MASK(15, 8)) >> 8;
-	base_cfg->audio_fmt.s_type =
-		(fmt->audio_fmt.fmt_cfg & MASK(23, 16)) >> 16;
-
-	/* Choose ALSA period size for ibs/obs so that the buffer sizes will be set accordingly */
-	base_cfg->ibs = plug->period_size * 2;
-	base_cfg->obs = plug->period_size * 2;
-
-	return 0;
-}
-
-static int plug_set_up_widget_base_config(snd_sof_plug_t *plug, struct tplg_comp_info *comp_info,
-					  snd_pcm_hw_params_t *params)
-{
-	int ret, i;
-
-	/* match audio formats and populate base config */
-	ret = plug_match_audio_format(plug, comp_info, params);
-	if (ret < 0)
-		return ret;
-
-	/* copy the basecfg into the ipc payload */
-	memcpy(comp_info->ipc_payload, &comp_info->basecfg, sizeof(struct ipc4_base_module_cfg));
-
-	return 0;
-}
-
-/* parse topology file and set up pipeline */
-int plug_parse_topology(snd_sof_plug_t *plug)
-
-{
-	struct tplg_context *ctx = &plug->tplg;
-	struct snd_soc_tplg_hdr *hdr;
-	struct list_item *item;
-	char pipeline_string[256] = {0};
-	int i;
-	int ret = 0;
-	FILE *file;
-	size_t size;
-
-	tplg_debug("parsing topology file %s\n", ctx->tplg_file);
-
-	ctx->ctl_arg = plug;
-	ctx->ctl_cb = plug_kcontrol_cb_new;
-
-	/* open topology file */
-	file = fopen(ctx->tplg_file, "rb");
-	if (!file) {
-		SNDERR("error: can't open topology %s : %s\n", ctx->tplg_file, strerror(errno));
-		return -errno;
-	}
-
-	/* file size */
-	if (fseek(file, 0, SEEK_END)) {
-		SNDERR("error: can't seek to end of topology: %s\n", strerror(errno));
-		fclose(file);
-		return -errno;
-	}
-	ctx->tplg_size = ftell(file);
-	if (fseek(file, 0, SEEK_SET)) {
-		SNDERR("error: can't seek to beginning of topology: %s\n", strerror(errno));
-		fclose(file);
-		return -errno;
-	}
-
-	/* load whole topology into memory */
-	ctx->tplg_base = calloc(ctx->tplg_size, 1);
-	if (!ctx->tplg_base) {
-		SNDERR("error: can't alloc buffer for topology %zu bytes\n", ctx->tplg_size);
-		fclose(file);
-		return -ENOMEM;
-	}
-	ret = fread(ctx->tplg_base, ctx->tplg_size, 1, file);
-	if (ret != 1) {
-		SNDERR("error: can't read topology: %s\n",
-		       strerror(errno));
-		fclose(file);
-		return -errno;
-	}
-	fclose(file);
-
-	/* initialize widget, route, pipeline and pcm lists */
-	list_init(&plug->widget_list);
-	list_init(&plug->route_list);
-	list_init(&plug->pcm_list);
-	list_init(&plug->pipeline_list);
-
-	while (ctx->tplg_offset < ctx->tplg_size) {
-		/* read next topology header */
-		hdr = tplg_get_hdr(ctx);
-
-		tplg_debug("type: %x, size: 0x%x count: %d index: %d\n",
-			   hdr->type, hdr->payload_size, hdr->count, hdr->index);
-
-		ctx->hdr = hdr;
-
-		/* parse header and load the next block based on type */
-		switch (hdr->type) {
-		/* load dapm widget */
-		case SND_SOC_TPLG_TYPE_DAPM_WIDGET:
-			tplg_debug("number of DAPM widgets %d\n", hdr->count);
-
-			/* update max pipeline_id */
-			ctx->pipeline_id = hdr->index;
-
-			for (i = 0; i < hdr->count; i++) {
-				ret = plug_load_widget(plug);
-				if (ret < 0) {
-					SNDERR("error: loading widget\n");
-					return ret;
-				}
-				ctx->comp_id++;
-			}
-			break;
-		/* set up component connections from pipeline graph */
-		case SND_SOC_TPLG_TYPE_DAPM_GRAPH:
-			if (plug_register_graph(plug, hdr->count) < 0) {
-				SNDERR("error: pipeline graph\n");
-				return -EINVAL;
-			}
-			break;
-		/* parse PCM info */
-		case SND_SOC_TPLG_TYPE_PCM:
-			ret = plug_parse_pcm(plug, hdr->count);
-			if (ret < 0)
-				goto out;
-			break;
-		default:
-			tplg_debug("%s %d\n", __func__, __LINE__);
-			tplg_skip_hdr_payload(ctx);
-			break;
-		}
-	}
-
-	/* assign pipeline to every widget in the widget list */
-	list_for_item(item, &plug->widget_list) {
-		struct tplg_comp_info *comp_info = container_of(item, struct tplg_comp_info, item);
-		struct list_item *pipe_item;
-
-		list_for_item(pipe_item, &plug->pipeline_list) {
-			struct tplg_pipeline_info *pipe_info;
-
-			pipe_info = container_of(pipe_item, struct tplg_pipeline_info, item);
-			if (pipe_info->id == comp_info->pipeline_id) {
-				comp_info->pipe_info = pipe_info;
-				break;
-			}
-		}
-
-		if (!comp_info->pipe_info) {
-			SNDERR("Error assigning pipeline for %s\n", comp_info->name);
-			return -EINVAL;
-		}
-	}
-out:
-	return ret;
-}
-
-static int plug_set_up_widget_ipc(snd_sof_plug_t *plug, struct tplg_comp_info *comp_info)
-{
-	struct ipc4_module_init_instance *module_init = &comp_info->module_init;
-	struct ipc4_message_reply reply;
-	void *msg;
-	int size, ret;
-
-	module_init->extension.r.param_block_size = comp_info->ipc_size >> 2;
-	module_init->extension.r.ppl_instance_id = comp_info->pipe_info->instance_id;
-
-	size = sizeof(*module_init) + comp_info->ipc_size;
-	msg = calloc(size, 1);
-	if (!msg)
-		return -ENOMEM;
-
-	memcpy(msg, module_init, sizeof(*module_init));
-	memcpy(msg + sizeof(*module_init), comp_info->ipc_payload, comp_info->ipc_size);
-
-	ret = plug_ipc_cmd_tx_rx(&plug->ipc, msg, size, &reply, sizeof(reply));
-	free(msg);
-	if (ret < 0) {
-		SNDERR("error: can't set up widget %s\n", comp_info->name);
-		return ret;
-	}
-
-	if (reply.primary.r.status != IPC4_SUCCESS) {
-		SNDERR("widget %s set up failed with status %d\n",
-		       comp_info->name, reply.primary.r.status);
-		return -EINVAL;
-	}
-	return 0;
-}
-
-static int plug_set_up_pipeline(snd_sof_plug_t *plug, struct tplg_pipeline_info *pipe_info)
-{
-	struct ipc4_pipeline_create msg = {{ 0 }};
-	struct ipc4_message_reply reply;
-	int ret;
-
-	msg.primary.r.type = SOF_IPC4_GLB_CREATE_PIPELINE;
-	msg.primary.r.msg_tgt = SOF_IPC4_MESSAGE_TARGET_FW_GEN_MSG;
-	msg.primary.r.rsp = SOF_IPC4_MESSAGE_DIR_MSG_REQUEST;
-	pipe_info->instance_id = plug->instance_ids[SND_SOC_TPLG_DAPM_SCHEDULER]++;
-	msg.primary.r.instance_id = pipe_info->instance_id;
-	msg.primary.r.ppl_mem_size = pipe_info->mem_usage;
-
-	ret = plug_ipc_cmd_tx_rx(&plug->ipc, &msg, sizeof(msg), &reply, sizeof(reply));
-	if (ret < 0) {
-		SNDERR("error: can't set up pipeline %s\n", pipe_info->name);
-		return ret;
-	}
-
-	if (reply.primary.r.status != IPC4_SUCCESS) {
-		SNDERR("pipeline %s instance ID %d set up failed with status %d\n",
-		       pipe_info->name, pipe_info->instance_id, reply.primary.r.status);
-		return -EINVAL;
-	}
-
-	tplg_debug("pipeline %s instance_id %d mem_usage %d set up\n", pipe_info->name,
-		   pipe_info->instance_id, pipe_info->mem_usage);
-
-	return 0;
-}
-
-static int plug_prepare_widget(snd_sof_plug_t *plug, struct tplg_pcm_info *pcm_info,
-			       struct tplg_comp_info *comp_info, int dir,
-			       snd_pcm_hw_params_t *params)
-{
-	struct tplg_pipeline_list *pipeline_list;
-	int ret, i;
-
-	if (dir)
-		pipeline_list = &pcm_info->capture_pipeline_list;
-	else
-		pipeline_list = &pcm_info->playback_pipeline_list;
-
-	/* populate base config */
-	ret = plug_set_up_widget_base_config(plug, comp_info, params);
-	if (ret < 0)
-		return ret;
-
-	plug_pipeline_update_resource_usage(plug, comp_info);
-
-	/* add pipeline to pcm pipeline_list if needed */
-	for (i = 0; i < pipeline_list->count; i++) {
-		struct tplg_pipeline_info *pipe_info = pipeline_list->pipelines[i];
-
-		if (pipe_info == comp_info->pipe_info)
-			break;
-	}
-
-	if (i == pipeline_list->count) {
-		if (pipeline_list->count >= TPLG_MAX_PCM_PIPELINES) {
-			SNDERR("error: too many pipelines for PCM, max %d\n",
-			       TPLG_MAX_PCM_PIPELINES);
-			return -EINVAL;
-		}
-
-		pipeline_list->pipelines[pipeline_list->count] = comp_info->pipe_info;
-		pipeline_list->count++;
-	}
-
-	tplg_debug("widget %s prepared\n", comp_info->name);
-	return 0;
-}
-
-static int plug_prepare_widgets(snd_sof_plug_t *plug, struct tplg_pcm_info *pcm_info,
-				struct tplg_comp_info *starting_comp_info,
-				struct tplg_comp_info *current_comp_info,
-				snd_pcm_hw_params_t *params)
-{
-	struct list_item *item;
-	int ret;
-
-	/* for playback */
-	list_for_item(item, &plug->route_list) {
-		struct tplg_route_info *route_info = container_of(item, struct tplg_route_info,
-								  item);
-
-		if (route_info->source != current_comp_info)
-			continue;
-
-		/* set up source widget if it is the starting widget */
-		if (starting_comp_info == current_comp_info) {
-			ret = plug_prepare_widget(plug, pcm_info, current_comp_info, 0, params);
-			if (ret < 0)
-				return ret;
-		}
-
-		/* set up the sink widget */
-		ret = plug_prepare_widget(plug, pcm_info, route_info->sink, 0, params);
-		if (ret < 0)
-			return ret;
-
-		/* and then continue down the path */
-		if (route_info->sink->type != SND_SOC_TPLG_DAPM_DAI_IN ||
-		    route_info->sink->type != SND_SOC_TPLG_DAPM_DAI_OUT) {
-			ret = plug_prepare_widgets(plug, pcm_info, starting_comp_info,
-						   route_info->sink, params);
-			if (ret < 0)
-				return ret;
-		}
-	}
-
-	return 0;
-}
-
-static int plug_prepare_widgets_capture(snd_sof_plug_t *plug, struct tplg_pcm_info *pcm_info,
-					struct tplg_comp_info *starting_comp_info,
-					struct tplg_comp_info *current_comp_info,
-					snd_pcm_hw_params_t *params)
-{
-	struct list_item *item;
-	int ret;
-
-	/* for capture */
-	list_for_item(item, &plug->route_list) {
-		struct tplg_route_info *route_info = container_of(item, struct tplg_route_info,
-								  item);
-
-		if (route_info->sink != current_comp_info)
-			continue;
-
-		/* set up sink widget if it is the starting widget */
-		if (starting_comp_info == current_comp_info) {
-			ret = plug_prepare_widget(plug, pcm_info, current_comp_info, 1, params);
-			if (ret < 0)
-				return ret;
-		}
-
-		/* set up the source widget */
-		ret = plug_prepare_widget(plug, pcm_info, route_info->source, 1, params);
-		if (ret < 0)
-			return ret;
-
-		/* and then continue up the path */
-		if (route_info->source->type != SND_SOC_TPLG_DAPM_DAI_IN &&
-		    route_info->source->type != SND_SOC_TPLG_DAPM_DAI_OUT) {
-			ret = plug_prepare_widgets_capture(plug, pcm_info, starting_comp_info,
-							   route_info->source, params);
-			if (ret < 0)
-				return ret;
-		}
-	}
-
-	return 0;
-}
-
-static int plug_set_up_route(snd_sof_plug_t *plug, struct tplg_route_info *route_info)
-{
-	struct tplg_comp_info *src_comp_info = route_info->source;
-	struct tplg_comp_info *sink_comp_info = route_info->sink;
-	struct ipc4_module_bind_unbind bu;
-	struct ipc4_message_reply reply;
-	int ret;
-
-	bu.primary.r.module_id = src_comp_info->module_id;
-	bu.primary.r.instance_id = src_comp_info->instance_id;
-	bu.primary.r.type = SOF_IPC4_MOD_BIND;
-	bu.primary.r.msg_tgt = SOF_IPC4_MESSAGE_TARGET_MODULE_MSG;
-	bu.primary.r.rsp = SOF_IPC4_MESSAGE_DIR_MSG_REQUEST;
-
-	bu.extension.r.dst_module_id = sink_comp_info->module_id;
-	bu.extension.r.dst_instance_id = sink_comp_info->instance_id;
-
-	/* FIXME: assign queue ID for components with multiple inputs/outputs */
-	bu.extension.r.dst_queue = 0;
-	bu.extension.r.src_queue = 0;
-
-	ret = plug_ipc_cmd_tx_rx(&plug->ipc, &bu, sizeof(bu), &reply, sizeof(reply));
-	if (ret < 0) {
-		SNDERR("error: can't set up route %s -> %s\n", src_comp_info->name,
-		       sink_comp_info->name);
-		return ret;
-	}
-
-	if (reply.primary.r.status != IPC4_SUCCESS) {
-		SNDERR("route %s -> %s ID set up failed with status %d\n",
-		       src_comp_info->name, sink_comp_info->name, reply.primary.r.status);
-		return -EINVAL;
-	}
-
-	tplg_debug("route %s -> %s set up\n", src_comp_info->name, sink_comp_info->name);
-
-	return 0;
-}
-
-static int plug_set_up_widget(snd_sof_plug_t *plug, struct tplg_comp_info *comp_info)
-{
-	struct tplg_pipeline_info *pipe_info = comp_info->pipe_info;
-	struct plug_shm_glb_state *glb = plug->glb_ctx.addr;
-	struct plug_shm_ctl *ctl;
-	int ret, i;
-
-	pipe_info->usage_count++;
-
-	/* first set up pipeline if needed, only done once for the first pipeline widget */
-	if (pipe_info->usage_count == 1) {
-		ret = plug_set_up_pipeline(plug, pipe_info);
-		if (ret < 0) {
-			pipe_info->usage_count--;
-			return ret;
-		}
-	}
-
-	/* now set up the widget */
-	ret = plug_set_up_widget_ipc(plug, comp_info);
-	if (ret < 0)
-		return ret;
-
-	/* send kcontrol bytes data */
-	for (i = 0; i < glb->num_ctls; i++) {
-		struct snd_soc_tplg_bytes_control *tplg_bytes;
-		struct sof_abi_hdr *abi;
-		int priv_size;
-
-		ctl = &glb->ctl[i];
-
-		/* send the bytes data from kcontrols associated with current widget */
-		if (ctl->module_id != comp_info->module_id ||
-		    ctl->instance_id != comp_info->instance_id ||
-		    ctl->type != SND_SOC_TPLG_TYPE_BYTES)
-			continue;
-
-		tplg_bytes = &ctl->bytes_ctl;
-		priv_size = tplg_bytes->priv.size;
-		abi = (struct sof_abi_hdr *)ctl->data;
-
-		/* send IPC with kcontrol data */
-		ret = plug_send_bytes_data(&plug->ipc, comp_info->module_id,
-					   comp_info->instance_id, abi);
-		if (ret < 0) {
-			SNDERR("failed to set bytes data for widget %s\n", comp_info->name);
-			return ret;
-		}
-	}
-
-	tplg_debug("widget %s set up\n", comp_info->name);
-
-	return 0;
-}
-
-static int plug_set_up_widgets(snd_sof_plug_t *plug, struct tplg_comp_info *starting_comp_info,
-			       struct tplg_comp_info *current_comp_info)
-{
-	struct list_item *item;
-	int ret;
-
-	/* for playback */
-	list_for_item(item, &plug->route_list) {
-		struct tplg_route_info *route_info = container_of(item, struct tplg_route_info,
-								  item);
-
-		if (route_info->source != current_comp_info)
-			continue;
-
-		/* set up source widget if it is the starting widget */
-		if (starting_comp_info == current_comp_info) {
-			ret = plug_set_up_widget(plug, current_comp_info);
-			if (ret < 0)
-				return ret;
-		}
-
-		/* set up the sink widget */
-		ret = plug_set_up_widget(plug, route_info->sink);
-		if (ret < 0)
-			return ret;
-
-		/* source and sink widgets are up, so set up route now */
-		ret = plug_set_up_route(plug, route_info);
-		if (ret < 0)
-			return ret;
-
-		/* and then continue down the path */
-		if (route_info->sink->type != SND_SOC_TPLG_DAPM_DAI_IN ||
-		    route_info->sink->type != SND_SOC_TPLG_DAPM_DAI_OUT) {
-			ret = plug_set_up_widgets(plug, starting_comp_info, route_info->sink);
-			if (ret < 0)
-				return ret;
-		}
-	}
-
-	return 0;
-}
-
-static int plug_set_up_widgets_capture(snd_sof_plug_t *plug,
-				       struct tplg_comp_info *starting_comp_info,
-				       struct tplg_comp_info *current_comp_info)
-{
-	struct list_item *item;
-	int ret;
-
-	/* for playback */
-	list_for_item(item, &plug->route_list) {
-		struct tplg_route_info *route_info = container_of(item, struct tplg_route_info,
-								  item);
-
-		if (route_info->sink != current_comp_info)
-			continue;
-
-		/* set up source widget if it is the starting widget */
-		if (starting_comp_info == current_comp_info) {
-			ret = plug_set_up_widget(plug, current_comp_info);
-			if (ret < 0)
-				return ret;
-		}
-
-		/* set up the sink widget */
-		ret = plug_set_up_widget(plug, route_info->source);
-		if (ret < 0)
-			return ret;
-
-		/* source and sink widgets are up, so set up route now */
-		ret = plug_set_up_route(plug, route_info);
-		if (ret < 0)
-			return ret;
-
-		/* and then continue down the path */
-		if (route_info->source->type != SND_SOC_TPLG_DAPM_DAI_IN &&
-		    route_info->source->type != SND_SOC_TPLG_DAPM_DAI_OUT) {
-			ret = plug_set_up_widgets_capture(plug, starting_comp_info,
-							  route_info->source);
-			if (ret < 0)
-				return ret;
-		}
-	}
-
-	return 0;
-}
-
-int plug_set_up_pipelines(snd_sof_plug_t *plug, int dir, snd_pcm_hw_params_t *params)
-{
-	struct tplg_comp_info *host = NULL;
-	struct tplg_pcm_info *pcm_info;
-	struct list_item *item;
-	int ret;
-
-	list_for_item(item, &plug->pcm_list) {
-		pcm_info = container_of(item, struct tplg_pcm_info, item);
-
-		if (pcm_info->id == plug->pcm_id) {
-			if (dir)
-				host = pcm_info->capture_host;
-			else
-				host = pcm_info->playback_host;
-			break;
-		}
-	}
-
-	if (!host) {
-		SNDERR("No host component found for PCM ID: %d\n", plug->pcm_id);
-		return -EINVAL;
-	}
-
-	plug->pcm_info = pcm_info;
-
-	if (dir) {
-		ret = plug_prepare_widgets_capture(plug, pcm_info, host, host, params);
-		if (ret < 0)
-			return ret;
-
-		ret = plug_set_up_widgets_capture(plug, host, host);
-		if (ret < 0)
-			return ret;
-
-		tplg_debug("Setting up capture pipelines complete\n");
-
-		return 0;
-	}
-
-	ret = plug_prepare_widgets(plug, pcm_info, host, host, params);
-	if (ret < 0)
-		return ret;
-
-	ret = plug_set_up_widgets(plug, host, host);
-	if (ret < 0)
-		return ret;
-
-	tplg_debug("Setting up playback pipelines complete\n");
-
-	return 0;
-}
-
-static int plug_delete_pipeline(snd_sof_plug_t *plug, struct tplg_pipeline_info *pipe_info)
-{
-	struct ipc4_pipeline_delete msg;
-	struct ipc4_message_reply reply;
-	int ret;
-
-	msg.primary.r.type = SOF_IPC4_GLB_DELETE_PIPELINE;
-	msg.primary.r.msg_tgt = SOF_IPC4_MESSAGE_TARGET_FW_GEN_MSG;
-	msg.primary.r.rsp = SOF_IPC4_MESSAGE_DIR_MSG_REQUEST;
-	msg.primary.r.instance_id = pipe_info->instance_id;
-
-	ret = plug_ipc_cmd_tx_rx(&plug->ipc, &msg, sizeof(msg), &reply, sizeof(reply));
-	if (ret < 0) {
-		SNDERR("error: can't delete pipeline %s\n", pipe_info->name);
-		return ret;
-	}
-
-	if (reply.primary.r.status != IPC4_SUCCESS) {
-		SNDERR("pipeline %s instance ID %d delete failed with status %d\n",
-		       pipe_info->name, pipe_info->instance_id, reply.primary.r.status);
-		return -EINVAL;
-	}
-
-	tplg_debug("pipeline %s instance_id %d freed\n", pipe_info->name,
-		   pipe_info->instance_id);
-
-	return 0;
-}
-
-static int plug_free_route(snd_sof_plug_t *plug, struct tplg_route_info *route_info)
-{
-	struct tplg_comp_info *src_comp_info = route_info->source;
-	struct tplg_comp_info *sink_comp_info = route_info->sink;
-	struct ipc4_module_bind_unbind bu;
-	struct ipc4_message_reply reply;
-	int ret;
-
-	/* only unbind when widgets belong to separate pipelines */
-	if (src_comp_info->pipeline_id == sink_comp_info->pipeline_id)
-		return 0;
-
-	bu.primary.r.module_id = src_comp_info->module_id;
-	bu.primary.r.instance_id = src_comp_info->instance_id;
-	bu.primary.r.type = SOF_IPC4_MOD_UNBIND;
-	bu.primary.r.msg_tgt = SOF_IPC4_MESSAGE_TARGET_MODULE_MSG;
-	bu.primary.r.rsp = SOF_IPC4_MESSAGE_DIR_MSG_REQUEST;
-
-	bu.extension.r.dst_module_id = sink_comp_info->module_id;
-	bu.extension.r.dst_instance_id = sink_comp_info->instance_id;
-
-	/* FIXME: assign queue ID for components with multiple inputs/outputs */
-	bu.extension.r.dst_queue = 0;
-	bu.extension.r.src_queue = 0;
-
-	ret = plug_ipc_cmd_tx_rx(&plug->ipc, &bu, sizeof(bu), &reply, sizeof(reply));
-	if (ret < 0) {
-		SNDERR("error: can't set up route %s -> %s\n", src_comp_info->name,
-		       sink_comp_info->name);
-		return ret;
-	}
-
-	if (reply.primary.r.status != IPC4_SUCCESS) {
-		SNDERR("route %s -> %s ID set up failed with status %d\n",
-		       src_comp_info->name, sink_comp_info->name, reply.primary.r.status);
-		return -EINVAL;
-	}
-
-	tplg_debug("route %s -> %s freed\n", src_comp_info->name, sink_comp_info->name);
-
-	return 0;
-}
-
-static int plug_free_widgets(snd_sof_plug_t *plug, struct tplg_comp_info *starting_comp_info,
-			     struct tplg_comp_info *current_comp_info)
-{
-	struct list_item *item;
-	int ret;
-
-	/* for playback */
-	list_for_item(item, &plug->route_list) {
-		struct tplg_route_info *route_info = container_of(item, struct tplg_route_info,
-								  item);
-
-		if (route_info->source != current_comp_info)
-			continue;
-
-		/* Widgets will be freed when the pipeline is deleted, so just unbind modules */
-		ret = plug_free_route(plug, route_info);
-		if (ret < 0)
-			return ret;
-
-		/* and then continue down the path */
-		if (route_info->sink->type != SND_SOC_TPLG_DAPM_DAI_IN ||
-		    route_info->sink->type != SND_SOC_TPLG_DAPM_DAI_OUT) {
-			ret = plug_free_widgets(plug, starting_comp_info, route_info->sink);
-			if (ret < 0)
-				return ret;
-		}
-	}
-
-	return 0;
-}
-
-static int plug_free_widgets_capture(snd_sof_plug_t *plug,
-				     struct tplg_comp_info *starting_comp_info,
-				     struct tplg_comp_info *current_comp_info)
-{
-	struct list_item *item;
-	int ret;
-
-	/* for playback */
-	list_for_item(item, &plug->route_list) {
-		struct tplg_route_info *route_info = container_of(item, struct tplg_route_info,
-								  item);
-
-		if (route_info->sink != current_comp_info)
-			continue;
-
-		/* Widgets will be freed when the pipeline is deleted, so just unbind modules */
-		ret = plug_free_route(plug, route_info);
-		if (ret < 0)
-			return ret;
-
-		/* and then continue down the path */
-		if (route_info->sink->type != SND_SOC_TPLG_DAPM_DAI_IN &&
-		    route_info->sink->type != SND_SOC_TPLG_DAPM_DAI_OUT) {
-			ret = plug_free_widgets_capture(plug, starting_comp_info,
-							route_info->source);
-			if (ret < 0)
-				return ret;
-		}
-	}
-
-	return 0;
-}
-
-int plug_free_pipelines(snd_sof_plug_t *plug, struct tplg_pipeline_list *pipeline_list, int dir)
-{
-	struct tplg_comp_info *host = NULL;
-	struct tplg_pcm_info *pcm_info;
-	struct list_item *item;
-	int ret, i;
-
-	list_for_item(item, &plug->pcm_list) {
-		pcm_info = container_of(item, struct tplg_pcm_info, item);
-
-		if (pcm_info->id == plug->pcm_id) {
-			if (dir)
-				host = pcm_info->capture_host;
-			else
-				host = pcm_info->playback_host;
-			break;
-		}
-	}
-
-	if (!host) {
-		SNDERR("No host component found for PCM ID: %d\n", plug->pcm_id);
-		return -EINVAL;
-	}
-
-	if (dir) {
-		ret = plug_free_widgets_capture(plug, host, host);
-		if (ret < 0) {
-			SNDERR("failed to free widgets for capture PCM %d\n", plug->pcm_id);
-			return ret;
-		}
-	} else {
-		ret = plug_free_widgets(plug, host, host);
-		if (ret < 0) {
-			SNDERR("failed to free widgets for PCM %d\n", plug->pcm_id);
-			return ret;
-		}
-	}
-
-	for (i = 0; i < pipeline_list->count; i++) {
-		struct tplg_pipeline_info *pipe_info = pipeline_list->pipelines[i];
-
-		ret = plug_delete_pipeline(plug, pipe_info);
-		if (ret < 0)
-			return ret;
-	}
-
-	plug->instance_ids[SND_SOC_TPLG_DAPM_SCHEDULER] = 0;
-	return 0;
-}
-
-void plug_free_topology(snd_sof_plug_t *plug)
-{
-	struct tplg_context *ctx = &plug->tplg;
-	struct list_item *item, *_item;
-
-	list_for_item_safe(item, _item, &plug->pcm_list) {
-		struct tplg_pcm_info *pcm_info = container_of(item, struct tplg_pcm_info, item);
-
-		free(pcm_info->name);
-		free(pcm_info);
-	}
-
-	list_for_item_safe(item, _item, &plug->widget_list) {
-		struct tplg_comp_info *comp_info = container_of(item, struct tplg_comp_info, item);
-		struct sof_ipc4_available_audio_format *available_fmts = &comp_info->available_fmt;
-
-		free(available_fmts->output_pin_fmts);
-		free(available_fmts->input_pin_fmts);
-		free(comp_info->name);
-		free(comp_info->stream_name);
-		free(comp_info->ipc_payload);
-		free(comp_info);
-	}
-
-	list_for_item_safe(item, _item, &plug->route_list) {
-		struct tplg_route_info *route_info = container_of(item, struct tplg_route_info,
-								  item);
-
-		free(route_info);
-	}
-
-	list_for_item_safe(item, _item, &plug->pipeline_list) {
-		struct tplg_pipeline_info *pipe_info = container_of(item, struct tplg_pipeline_info,
-								    item);
-
-		free(pipe_info->name);
-		free(pipe_info);
-	}
-
-	free(ctx->tplg_base);
-	tplg_debug("freed all pipelines, widgets, routes and pcms\n");
-}
diff --git a/tools/plugin/alsaplug/tplg_ctl.c b/tools/plugin/alsaplug/tplg_ctl.c
deleted file mode 100644
index ad2709153806..000000000000
--- a/tools/plugin/alsaplug/tplg_ctl.c
+++ /dev/null
@@ -1,226 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-//
-// Copyright(c) 2024 Intel Corporation. All rights reserved.
-//
-
-/* SOF topology kcontrols */
-
-#include <stdio.h>
-#include <sys/poll.h>
-#include <string.h>
-#include <sys/types.h>
-#include <unistd.h>
-#include <stdlib.h>
-#include <sys/wait.h>
-#include <sys/stat.h>
-#include <fcntl.h>
-#include <sys/mman.h>
-#include <semaphore.h>
-#include <assert.h>
-#include <errno.h>
-#include <math.h>
-
-#include <alsa/asoundlib.h>
-#include <alsa/pcm_external.h>
-
-#include <rtos/sof.h>
-#include <sof/audio/pipeline.h>
-#include <sof/audio/component.h>
-#include <ipc/stream.h>
-#include <tplg_parser/topology.h>
-
-#include "plugin.h"
-#include "common.h"
-
-#define SOF_IPC4_VOL_ZERO_DB	0x7fffffff
-#define VOLUME_FWL      16
-/*
- * Constants used in the computation of linear volume gain
- * from dB gain 20th root of 10 in Q1.16 fixed-point notation
- */
-#define VOL_TWENTIETH_ROOT_OF_TEN	73533
-/* 40th root of 10 in Q1.16 fixed-point notation*/
-#define VOL_FORTIETH_ROOT_OF_TEN	69419
-
-/* 0.5 dB step value in topology TLV */
-#define VOL_HALF_DB_STEP	50
-
-/*
- * Function to truncate an unsigned 64-bit number
- * by x bits and return 32-bit unsigned number. This
- * function also takes care of rounding while truncating
- */
-static uint32_t vol_shift_64(uint64_t i, uint32_t x)
-{
-	if (x == 0)
-		return (uint32_t)i;
-
-	/* do not truncate more than 32 bits */
-	if (x > 32)
-		x = 32;
-
-	return (uint32_t)(((i >> (x - 1)) + 1) >> 1);
-}
-
-/*
- * Function to compute a ** exp where,
- * a is a fractional number represented by a fixed-point integer with a fractional word length
- * of "fwl"
- * exp is an integer
- * fwl is the fractional word length
- * Return value is a fractional number represented by a fixed-point integer with a fractional
- * word length of "fwl"
- */
-static uint32_t vol_pow32(uint32_t a, int exp, uint32_t fwl)
-{
-	int i, iter;
-	uint32_t power = 1 << fwl;
-	unsigned long long numerator;
-
-	/* if exponent is 0, return 1 */
-	if (exp == 0)
-		return power;
-
-	/* determine the number of iterations based on the exponent */
-	if (exp < 0)
-		iter = exp * -1;
-	else
-		iter = exp;
-
-	/* multiply a "iter" times to compute power */
-	for (i = 0; i < iter; i++) {
-		/*
-		 * Product of 2 Qx.fwl fixed-point numbers yields a Q2*x.2*fwl
-		 * Truncate product back to fwl fractional bits with rounding
-		 */
-		power = vol_shift_64((uint64_t)power * a, fwl);
-	}
-
-	if (exp > 0) {
-		/* if exp is positive, return the result */
-		return power;
-	}
-
-	/* if exp is negative, return the multiplicative inverse */
-	numerator = (uint64_t)1 << (fwl << 1);
-	numerator /= power;
-
-	return (uint32_t)numerator;
-}
-
-/*
- * Function to calculate volume gain from TLV data.
- * This function can only handle gain steps that are multiples of 0.5 dB
- */
-static uint32_t vol_compute_gain(uint32_t value, struct snd_soc_tplg_tlv_dbscale *scale)
-{
-	int dB_gain;
-	uint32_t linear_gain;
-	int f_step;
-
-	/* mute volume */
-	if (value == 0 && scale->mute)
-		return 0;
-
-	/* compute dB gain from tlv. tlv_step in topology is multiplied by 100 */
-	dB_gain = (int)scale->min / 100 + (value * scale->step) / 100;
-
-	/* compute linear gain represented by fixed-point int with VOLUME_FWL fractional bits */
-	linear_gain = vol_pow32(VOL_TWENTIETH_ROOT_OF_TEN, dB_gain, VOLUME_FWL);
-
-	/* extract the fractional part of volume step */
-	f_step = scale->step - (scale->step / 100);
-
-	/* if volume step is an odd multiple of 0.5 dB */
-	if (f_step == VOL_HALF_DB_STEP && (value & 1))
-		linear_gain = vol_shift_64((uint64_t)linear_gain * VOL_FORTIETH_ROOT_OF_TEN,
-					   VOLUME_FWL);
-
-	return linear_gain;
-}
-
-/* helper function to add new kcontrols to the list of kcontrols in the global context */
-int plug_kcontrol_cb_new(struct snd_soc_tplg_ctl_hdr *tplg_ctl, void *_comp, void *arg, int index)
-{
-	struct tplg_comp_info *comp_info = _comp;
-	snd_sof_plug_t *plug = arg;
-	struct plug_shm_glb_state *glb = plug->glb_ctx.addr;
-	struct plug_shm_ctl *ctl;
-
-	if (glb->num_ctls >= MAX_CTLS) {
-		SNDERR("Failed to add a new control. Too many controls already\n");
-		return -EINVAL;
-	}
-
-	switch (tplg_ctl->ops.info) {
-	case SND_SOC_TPLG_CTL_VOLSW:
-	case SND_SOC_TPLG_CTL_VOLSW_SX:
-	case SND_SOC_TPLG_CTL_VOLSW_XR_SX:
-	{
-		struct snd_soc_tplg_mixer_control *tplg_mixer =
-			(struct snd_soc_tplg_mixer_control *)tplg_ctl;
-		struct snd_soc_tplg_ctl_tlv *tlv;
-		struct snd_soc_tplg_tlv_dbscale *scale;
-		int i;
-
-		glb->size += sizeof(struct plug_shm_ctl);
-		ctl = &glb->ctl[glb->num_ctls++];
-		ctl->module_id = comp_info->module_id;
-		ctl->instance_id = comp_info->instance_id;
-		ctl->mixer_ctl = *tplg_mixer;
-		ctl->index = index;
-		ctl->type = tplg_ctl->type;
-		tlv = &tplg_ctl->tlv;
-		scale = &tlv->scale;
-
-		/* populate the volume table */
-		for (i = 0; i < tplg_mixer->max + 1 ; i++) {
-			uint32_t val = vol_compute_gain(i, scale);
-
-			/* Can be over Q1.31, need to saturate */
-			uint64_t q31val = ((uint64_t)val) << 15;
-
-			ctl->volume_table[i] = q31val > SOF_IPC4_VOL_ZERO_DB ?
-							SOF_IPC4_VOL_ZERO_DB : q31val;
-		}
-		break;
-	}
-	case SND_SOC_TPLG_CTL_ENUM:
-	case SND_SOC_TPLG_CTL_ENUM_VALUE:
-	{
-		struct snd_soc_tplg_enum_control *tplg_enum =
-			(struct snd_soc_tplg_enum_control *)tplg_ctl;
-
-		glb->size += sizeof(struct plug_shm_ctl);
-		ctl = &glb->ctl[glb->num_ctls++];
-		ctl->module_id = comp_info->module_id;
-		ctl->instance_id = comp_info->instance_id;
-		ctl->enum_ctl = *tplg_enum;
-		ctl->index = index;
-		ctl->type = tplg_ctl->type;
-		break;
-	}
-	case SND_SOC_TPLG_CTL_BYTES:
-	{
-		struct snd_soc_tplg_bytes_control *tplg_bytes =
-			(struct snd_soc_tplg_bytes_control *)tplg_ctl;
-
-		glb->size += sizeof(struct plug_shm_ctl);
-		ctl = &glb->ctl[glb->num_ctls++];
-		ctl->module_id = comp_info->module_id;
-		ctl->instance_id = comp_info->instance_id;
-		ctl->bytes_ctl = *tplg_bytes;
-		ctl->index = index;
-		ctl->type = tplg_ctl->type;
-		memcpy(ctl->data, tplg_bytes->priv.data, tplg_bytes->priv.size);
-		break;
-	}
-	case SND_SOC_TPLG_CTL_RANGE:
-	case SND_SOC_TPLG_CTL_STROBE:
-	default:
-		SNDERR("Invalid ctl type %d\n", tplg_ctl->type);
-		return -EINVAL;
-	}
-
-	return 0;
-}
diff --git a/tools/plugin/architecture.md b/tools/plugin/architecture.md
deleted file mode 100644
index 5276896de3f8..000000000000
--- a/tools/plugin/architecture.md
+++ /dev/null
@@ -1,260 +0,0 @@
-# SOF ALSA Plugin Architecture
-
-This directory contains the SOF ALSA plugin: infrastructure that runs unmodified
-SOF firmware natively on a Linux host, so topologies and processing modules can be
-exercised with `aplay`/`arecord` without a physical DSP.
-
-## Overview
-
-The plugin is split across **two processes** that share the SOF firmware code but
-play different roles:
-
-1. **ALSA client** - the plugin loaded inside the `aplay`/`arecord` application
-   (`libasound_module_pcm_sof.so`). It implements an ALSA `ioplug` device named
-   `sof:...` and moves PCM data to/from the daemon.
-2. **`sof-pipe` daemon** - a standalone process that links the real SOF core
-   (`libsof.a`, built with `CONFIG_LIBRARY`) and actually instantiates and runs
-   pipelines, components and modules.
-
-The two processes communicate over three POSIX IPC channels:
-
-* **Shared memory (SHM)** - an audio ring buffer per PCM, plus a global state
-  block holding endpoint configuration and kcontrols.
-* **Unix domain socket** - the IPC4 message transport (topology setup, pipeline
-  state changes).
-* **POSIX semaphores** - per-pipeline `ready`/`done` flow control.
-
-```mermaid
-graph LR
-  subgraph APP["aplay / arecord"]
-    A[Application] --> B["alsaplug/pcm.c<br/>ioplug device"]
-  end
-  subgraph DAEMON["sof-pipe daemon"]
-    D["pipe/main.c<br/>IPC socket loop"] --> E["pipe/ipc4.c<br/>IPC dispatch + dlopen"]
-    E --> F["pipe/pipeline.c<br/>pipeline threads"]
-    F --> G["libsof.a<br/>SOF core"]
-    F --> H["module .so<br/>loaded via dlopen"]
-  end
-  B <--> |SHM audio ring| H
-  B <--> |Unix socket IPC4| D
-  B <--> |ready/done semaphores| F
-```
-
-## Component Layout
-
-### Shared (`tools/plugin/`)
-
-| File | Responsibility |
-|------|----------------|
-| `common.h` | Structures shared by both processes: `plug_shm_endpoint` (audio ring buffer), `plug_shm_glb_state` (global state, endpoint configs, kcontrols) and the ring-buffer accessor inlines. Defines the shared-memory contract. |
-| `common.c` | Shared SHM, socket, semaphore and timing helpers. |
-
-### ALSA client (`tools/plugin/alsaplug/`)
-
-| File | Responsibility |
-|------|----------------|
-| `plugin.c` | Parses the ALSA configuration and command line (topology name, PCM ID, card/device/config). |
-| `pcm.c` | The `snd_pcm_ioplug` implementation and PCM entry point `SND_PCM_PLUGIN_DEFINE_FUNC(sof)`. Owns `hw_params`, `prepare`, `start`, `transfer`, `pointer` and `stop`. |
-| `conf.c` | ALSA configuration load hook. |
-| `ctl.c` | Separate ALSA ctl (mixer/kcontrol) plugin. |
-| `tplg.c` | Client-side topology parsing; emits the IPCs that instantiate widgets and pipelines. |
-| `tplg_ctl.c` | kcontrol handling derived from the topology. |
-| `plugin.h` | The `snd_sof_plug_t` client context type. |
-
-### Daemon (`tools/plugin/pipe/`)
-
-| File | Responsibility |
-|------|----------------|
-| `main.c` | Daemon entry point: argument parsing, SOF instance creation, global SHM setup, IPC accept loop. |
-| `ipc4.c` | IPC dispatch: the `module_id` to library map, `dlopen` of modules, and the local before/after hooks around the real `ipc_cmd()`. |
-| `pipeline.c` | SOF core initialisation (`pipe_sof_setup`) and the per-pipeline worker threads. |
-| `cpu.c` | CPU affinity and realtime priority helpers. |
-| `pipe.h` | The `sof_pipe` daemon context type. |
-
-### Endpoints and modules (`tools/plugin/modules/`)
-
-| File | Responsibility |
-|------|----------------|
-| `shm.c` | Host endpoint (`shmread`/`shmwrite`): bridges a pipeline buffer to the SHM ring buffer shared with the client. Legacy `comp_driver` component. |
-| `alsa.c` | DAI endpoint (`aplay`/`arecord`): opens a real ALSA device and bridges a pipeline buffer to hardware. Legacy `comp_driver` component. |
-| `ov_noise_suppression/` | An OpenVINO noise-suppression processing module using `module_interface`. Built only when OpenVINO is available. |
-
-## ALSA Integration
-
-The client uses the ALSA external I/O plugin mechanism (`snd_pcm_ioplug`),
-registered through `SND_PCM_PLUGIN_DEFINE_FUNC(sof)`. Playback and capture install
-distinct callback tables; the `transfer` callback is `plug_pcm_write` for playback
-and `plug_pcm_read` for capture.
-
-Hardware constraints advertised by `plug_hw_constraint` are deliberately wide
-(formats S16/S24/S32/FLOAT, 1-8 channels, 1-192 kHz) because the effective
-constraints are only known once the topology has been parsed.
-
-## Startup Sequence
-
-The daemon must be started before any client connects.
-
-```mermaid
-sequenceDiagram
-    participant Cli as ALSA client
-    participant Sock as Unix socket
-    participant Dae as sof-pipe daemon
-    participant Core as SOF core
-
-    Dae->>Core: pipe_sof_setup() builds the SOF instance
-    Dae->>Dae: create global SHM, enter accept() loop
-    Cli->>Cli: parse ALSA conf and topology
-    Cli->>Sock: connect IPC client socket
-    Cli->>Dae: hw_params sends topology setup IPCs
-    Dae->>Core: ipc_cmd() instantiates modules and pipelines
-    Cli->>Dae: prepare transitions pipelines PAUSED then RUNNING
-```
-
-## IPC and Module Loading
-
-The client translates the parsed topology into IPC4 messages sent over the socket.
-The daemon handles each message in `pipe_ipc_do`, which wraps the real core handler
-with local hooks:
-
-```text
-pipe_sof_ipc_cmd_before()   daemon-local actions before the core
-pipe_ipc_message()          ipc_cmd() - the real SOF IPC handler
-pipe_sof_ipc_cmd_after()    daemon-local actions after the core
-```
-
-Key responsibilities of the hooks:
-
-* **`MOD_INIT_INSTANCE` (before)** - `pipe_register_comp` `dlopen`s the module's
-  shared object per a `module_id` to library map. This runs the module's
-  registration constructor before the core instantiates the component.
-* **`GLB_CREATE_PIPELINE` (after)** - allocate a pipeline thread context and its
-  semaphores.
-* **`SET_PIPELINE_STATE = RUNNING` (after)** - start the pipeline worker thread.
-* **`SET_PIPELINE_STATE = PAUSED` (before)** - stop the worker thread.
-* **`GLB_DELETE_PIPELINE` (after)** - free the thread context.
-
-Each connected client is served by its own `handle_ipc_client` thread.
-
-## SOF Instance and Scheduling
-
-`pipe_sof_setup(struct sof *sof)` (called from `main()` with `sof_get()`) brings up
-the same core used on target: component registry (`sys_comp_init`), position
-tracking, notifier, IPC (`ipc_init`) and the LL and EDF schedulers. Only the
-platform layer differs from a real DSP - host threads replace the DSP scheduler,
-a socket replaces the IPC mailbox, and the SHM/ALSA endpoints replace DMA/DAI.
-
-Because there are no DSP interrupts, each pipeline runs as a `pthread`. The worker
-loop waits on the `ready` semaphore, invokes the real `pipeline_copy()`, then posts
-the `done` semaphore:
-
-```c
-do {
-    if (pipeline->status != COMP_STATE_ACTIVE) break;
-    if (pipe_users <= 0) break;
-    pipe_copy_ready(pd);                    /* sem_timedwait(ready) */
-    err = pipeline_copy(pd->pcm_pipeline);  /* real SOF pipeline run */
-    pipe_copy_done(pd);                     /* sem_post(done) */
-} while (1);
-```
-
-`pipeline_copy()` walks the component graph and, for each module, calls into the
-Module Adapter, which invokes the module callback. The semaphores pace one period
-per cycle between the client and the pipeline thread.
-
-## Audio Data Flow
-
-Audio crosses the process boundary through the `plug_shm_endpoint` ring buffer. The
-daemon-side `shm` endpoint maps the same named SHM object as the client, so both
-sides share one ring buffer with read/write positions and wrap counters.
-
-```mermaid
-sequenceDiagram
-    participant App as aplay
-    participant SHM as SHM ring
-    participant Shm as shm endpoint
-    participant Pipe as pipeline
-    participant Alsa as alsa endpoint
-    participant HW as ALSA hw device
-
-    App->>SHM: plug_pcm_write copies PCM into the ring then plug_ep_produce
-    App->>Pipe: sem_post ready
-    Pipe->>Shm: shmread_copy copies the ring into the pipeline buffer
-    Pipe->>Pipe: modules process the period
-    Pipe->>Alsa: aplay_copy writes to hardware via snd_pcm_writei
-    Pipe->>App: sem_post done
-```
-
-Capture is the mirror image: the `alsa` endpoint reads hardware with
-`snd_pcm_readi`, the pipeline processes, the `shm` endpoint writes to the ring
-buffer, and `plug_pcm_read` copies the ring buffer into the application. For
-capture the semaphore order is reversed so the source/DAI pipeline runs first.
-
-## Module Interfaces
-
-A plugin pipeline contains two kinds of component:
-
-* **Endpoints (`shm`, `alsa`)** use the legacy `comp_driver` model
-  (`.ops.copy`, direct `comp_buffer` access). They form the host and DAI
-  boundaries of the pipeline and are not `module_interface` modules.
-* **Processing modules** go through the Module Adapter and `struct
-  module_interface`, exactly as on target. The Module Adapter wraps the pipeline
-  `comp_buffer`s into `sof_source`/`sof_sink` and dispatches the module callback,
-  so a plugin-hosted processing module sees the same contract as firmware.
-
-`ov_noise_suppression` is the only `module_interface` processing module whose
-source lives in this directory. Other processing modules the plugin runs
-(for example `volume` and `mixer`) are built from `src/audio` and loaded as
-shared objects.
-
-## Dynamic Module Loading and Symbol Resolution
-
-Modules are separate shared objects loaded on demand; this section explains how a
-`.so` binds to the already-running core.
-
-A module `.so` exposes no bespoke API. At load time the relevant artefact is an ELF
-constructor emitted by the `DECLARE_MODULE` macro, which calls `comp_register()` to
-add the module's `struct comp_driver` (and, for processing modules, its
-`struct module_interface` via the Module Adapter) to the core's driver list. The
-core later selects the driver by UUID.
-
-`DECLARE_MODULE` expands differently per build configuration:
-
-* `CONFIG_LIBRARY_STATIC` (the core `libsof.a`) - expands to nothing; the core has
-  its infrastructure compiled in directly.
-* `CONFIG_LIBRARY` (the loadable `.so` modules) - expands to an
-  `__attribute__((constructor))` that the dynamic loader runs automatically on
-  `dlopen`.
-* Target DSP builds - place the initcall in a dedicated linker section.
-
-Symbol resolution relies on the ELF global namespace:
-
-1. A module `.so` is not linked against `libsof.a`; its references to core
-   functions (`comp_register`, `rzalloc`, `module_adapter_new`, `source_get_data`,
-   `sink_get_buffer`, and so on) are left undefined.
-2. `sof-pipe` is linked with `-rdynamic` and pulls the whole core in with
-   `-Wl,--whole-archive`, placing every core symbol in the executable's dynamic
-   symbol table.
-3. `dlopen(lib, RTLD_NOW)` resolves the module's undefined symbols against the
-   executable's exported symbols, binding the module to the single core instance
-   created by `pipe_sof_setup()`.
-4. The constructor then runs `comp_register()`, registering into that one core
-   instance.
-
-Static-linking the core into each module would give every `.so` its own private
-copy of the core's globals, so registration would populate a private list the
-daemon never sees. A single core instance in the executable is therefore required.
-
-On the `MOD_INIT_INSTANCE` IPC the daemon `dlopen`s the module before `ipc_cmd()`
-instantiates the component, so the driver is registered by the time the core
-matches it by UUID.
-
-## Synchronization Primitives
-
-| Resource | Type | Role |
-|----------|------|------|
-| SHM `ctx` | `plug_shm_glb_state` | Global state, endpoint configs, kcontrols |
-| SHM `pcm` | `plug_shm_endpoint` | Audio ring buffer, one per PCM |
-| Semaphore `ready` | per pipeline | Producer signals data is available to process |
-| Semaphore `done` | per pipeline | Pipeline signals the period has been processed |
-| Unix socket | stream | IPC4 messages from client to daemon, with reply |
-| `ipc_lock` | `pthread_mutex` | Serializes access to `ipc_cmd()` in the daemon |
diff --git a/tools/plugin/common.c b/tools/plugin/common.c
deleted file mode 100644
index f20cb14e0b0e..000000000000
--- a/tools/plugin/common.c
+++ /dev/null
@@ -1,466 +0,0 @@
-/*-*- linux-c -*-*/
-
-/*
- * ALSA <-> SOF PCM I/O plugin
- *
- * Copyright (c) 2022 by Liam Girdwood <liam.r.girdwood@intel.com>
- *
- * This library is free software; you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as
- * published by the Free Software Foundation; either version 2.1 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
- */
-
-#include <stdio.h>
-#include <string.h>
-#include <sys/types.h>
-#include <sys/socket.h>
-#include <sys/un.h>
-#include <unistd.h>
-#include <stdlib.h>
-#include <assert.h>
-#include <errno.h>
-#include <sys/mman.h>
-#include <sys/stat.h>
-
-#include "common.h"
-
-/*
- * Timing
- */
-void plug_timespec_add_ms(struct timespec *ts, unsigned long ms)
-{
-	long ns;
-	long secs = ms / 1000;
-
-	/* get ms remainder */
-	ms = ms - (secs * 1000);
-	ns = ms * 1000000;
-
-	ts->tv_nsec += ns;
-	if (ts->tv_nsec > 1000000000) {
-		secs++;
-		ts->tv_nsec -= 1000000000;
-	}
-	ts->tv_sec += (secs + DEBUG_TV_SECS);
-}
-
-long plug_timespec_delta_ns(struct timespec *before, struct timespec *after)
-{
-	long ns;
-
-	ns = (after->tv_sec - before->tv_sec) * 1000000000;
-	ns += after->tv_nsec - before->tv_nsec;
-
-	return ns;
-}
-
-static const char *suffix_name(const char *longname)
-{
-	size_t len = strlen(longname);
-	int i = len;
-
-	/* longname name invalid */
-	if (len < 1) {
-		SNDERR("invalid topology long name\n");
-		return NULL;
-	}
-
-	/* find the last '/' in the longname topology path */
-	while (--i >= 0) {
-		if (longname[i] == '/') {
-			i += 1; /* skip / */
-			return &longname[i];
-		}
-	}
-
-	/* no / in topology path, so use full path */
-	return longname;
-}
-
-/*
- * IPC
- *
- * POSIX message queues are used for interprocess IPC messaging.
- */
-
-/*
- * Initialise the IPC object.
- */
-int plug_socket_path_init(struct plug_socket_desc *ipc, const char *tplg, const char *type,
-			  int index)
-{
-	snprintf(ipc->path, NAME_SIZE, "/tmp/%s-%s", tplg, type);
-	return 0;
-}
-
-/*
- * Locking
- *
- * POSIX semaphores are used to block and synchronise audio between
- * different threads and processes.
- */
-
-/*
- * Initialise the lock object.
- */
-int plug_lock_init(struct plug_sem_desc *lock, const char *tplg, const char *type, int index)
-{
-	const char *name = suffix_name(tplg);
-
-	if (!name)
-		return -EINVAL;
-
-	/* semaphores need the leading / */
-	snprintf(lock->name, NAME_SIZE, "/lock-%s-%s-%d", name, type, index);
-
-	return 0;
-}
-
-/*
- * SHM
- *
- * Shared memory is used for audio data and audio context sharing between
- * threads and processes.
- */
-
-/*
- * Initialise the SHM object.
- */
-int plug_shm_init(struct plug_shm_desc *shm, const char *tplg, const char *type, int index)
-{
-	const char *name = suffix_name(tplg);
-
-	if (!name)
-		return -EINVAL;
-
-	snprintf(shm->name, NAME_SIZE, "/shm-%s-%s-%d", name, type, index);
-	shm->size = SHM_SIZE;
-
-	return 0;
-}
-
-/*
- * Open an existing shared memory region using the SHM object.
- */
-int plug_shm_open(struct plug_shm_desc *shm)
-{
-	struct stat status;
-
-	/* open SHM to be used for low latency position */
-	shm->fd = shm_open(shm->name, O_RDWR,
-			   S_IRWXU | S_IRWXG);
-	if (shm->fd < 0) {
-		//SNDERR("failed to open SHM position %s: %s\n",
-		//	shm->name, strerror(errno));
-		return -errno;
-	}
-
-	fstat(shm->fd, &status);
-	/* map it locally for context readback */
-	shm->addr = mmap(NULL, status.st_size, PROT_READ | PROT_WRITE, MAP_SHARED, shm->fd, 0);
-	if (!shm->addr) {
-		SNDERR("failed to mmap SHM position%s: %s\n", shm->name, strerror(errno));
-		return -errno;
-	}
-
-	return 0;
-}
-
-static int plug_socket_timed_wait(struct plug_socket_desc *ipc, fd_set *fds, int timeout_ms,
-				  bool write)
-{
-	struct timeval timeout;
-	int result;
-
-	/* Set the timeout for select */
-	timeout.tv_sec = 0;
-	timeout.tv_usec = timeout_ms * 1000;
-
-	/* now wait for socket to be readable/writable */
-	if (write)
-		result = select(ipc->socket_fd + 1, NULL, fds, NULL, &timeout);
-	else
-		result = select(ipc->socket_fd + 1, fds, NULL, NULL, &timeout);
-
-	if (result == -1) {
-		SNDERR("error waiting for socket to be %s\n", write ? "writable" : "readable");
-		return result;
-	}
-
-	if (result == 0) {
-		SNDERR("IPC Socket %s timeout\n", write ? "write" : "read");
-		return -ETIMEDOUT;
-	}
-
-	/* socket ready for read/write */
-	if (FD_ISSET(ipc->socket_fd, fds))
-		return 0;
-
-	/* socket not ready */
-	return -EINVAL;
-}
-
-static int plug_ipc_cmd_tx(struct plug_socket_desc *ipc, void *msg, size_t len)
-{
-	fd_set write_fds;
-	char mailbox[IPC3_MAX_MSG_SIZE];
-	ssize_t bytes;
-	int err;
-
-	if (len > IPC3_MAX_MSG_SIZE) {
-		SNDERR("ipc: message too big %d\n", len);
-		return -EINVAL;
-	}
-	memset(mailbox, 0, IPC3_MAX_MSG_SIZE);
-	memcpy(mailbox, msg, len);
-
-	/* Wait for the socket to be writable */
-	FD_ZERO(&write_fds);
-	FD_SET(ipc->socket_fd, &write_fds);
-
-	err = plug_socket_timed_wait(ipc, &write_fds, 20, true);
-	if (err < 0)
-		return err;
-
-	bytes = send(ipc->socket_fd, mailbox, IPC3_MAX_MSG_SIZE, 0);
-	if (bytes == -1) {
-		SNDERR("failed to send IPC message : %s\n", strerror(errno));
-		return -errno;
-	}
-
-	return bytes;
-}
-
-static int plug_ipc_cmd_rx(struct plug_socket_desc *ipc, char mailbox[IPC3_MAX_MSG_SIZE])
-{
-	fd_set read_fds;
-	int err;
-
-	/* Wait for the socket to be readable */
-	FD_ZERO(&read_fds);
-	FD_SET(ipc->socket_fd, &read_fds);
-
-	err = plug_socket_timed_wait(ipc, &read_fds, 200, false);
-	if (err < 0)
-		return err;
-
-	memset(mailbox, 0, IPC3_MAX_MSG_SIZE);
-	return recv(ipc->socket_fd, mailbox, IPC3_MAX_MSG_SIZE, 0);
-}
-
-int plug_ipc_cmd_tx_rx(struct plug_socket_desc *ipc, void *msg, size_t len, void *reply,
-		       size_t rlen)
-{
-	char mailbox[IPC3_MAX_MSG_SIZE];
-	ssize_t bytes;
-	int err;
-
-	/* send IPC message */
-	bytes = plug_ipc_cmd_tx(ipc, msg, len);
-	if (bytes == -1) {
-		SNDERR("failed to send IPC message : %s\n", strerror(errno));
-		return -errno;
-	}
-
-	/* wait for response */
-	memset(mailbox, 0, IPC3_MAX_MSG_SIZE);
-	bytes = plug_ipc_cmd_rx(ipc, mailbox);
-	if (bytes == -1) {
-		SNDERR("failed to read IPC message reply %s\n", strerror(errno));
-		return -errno;
-	}
-
-	/* no response or connection lost, try to restablish connection */
-	if (bytes == 0) {
-		close(ipc->socket_fd);
-		err = plug_create_client_socket(ipc);
-		if (err < 0) {
-			SNDERR("failed to reestablish connection to SOF pipe IPC socket : %s",
-			       strerror(err));
-			return -errno;
-		}
-
-		/* send IPC message again */
-		bytes = plug_ipc_cmd_tx(ipc, msg, len);
-		if (bytes == -1) {
-			SNDERR("failed to send IPC message : %s\n", strerror(errno));
-			return -errno;
-		}
-
-		/* wait for response */
-		memset(mailbox, 0, IPC3_MAX_MSG_SIZE);
-		bytes = plug_ipc_cmd_rx(ipc, mailbox);
-		if (bytes == -1) {
-			SNDERR("failed to read IPC message reply %s\n", strerror(errno));
-			return -errno;
-		}
-
-		/* connection lost again, quit now */
-		if (bytes == 0)
-			return -errno;
-	}
-
-	/* do the message work */
-	if (rlen && reply)
-		memcpy(reply, mailbox, rlen);
-
-	return 0;
-}
-
-void plug_ctl_ipc_message(struct ipc4_module_large_config *config, int param_id,
-			  size_t size, uint32_t module_id, uint32_t instance_id,
-			  uint32_t type)
-{
-	config->primary.r.type = type;
-	config->primary.r.msg_tgt = SOF_IPC4_MESSAGE_TARGET_MODULE_MSG;
-	config->primary.r.rsp = SOF_IPC4_MESSAGE_DIR_MSG_REQUEST;
-	config->primary.r.module_id = module_id;
-	config->primary.r.instance_id = instance_id;
-
-	config->extension.r.data_off_size = size;
-	config->extension.r.large_param_id = param_id;
-}
-
-int plug_send_bytes_data(struct plug_socket_desc *ipc, uint32_t module_id, uint32_t instance_id,
-			 struct sof_abi_hdr *abi)
-{
-	struct ipc4_module_large_config config = {{ 0 }};
-	struct ipc4_message_reply reply;
-	void *msg;
-	int msg_size;
-	int err;
-
-	/* configure the IPC message */
-	plug_ctl_ipc_message(&config, abi->type, abi->size, module_id, instance_id,
-			     SOF_IPC4_MOD_LARGE_CONFIG_SET);
-
-	config.extension.r.final_block = 1;
-	config.extension.r.init_block = 1;
-
-	/* allocate memory for IPC message */
-	msg_size = sizeof(config) + abi->size;
-	msg = calloc(msg_size, 1);
-	if (!msg)
-		return -ENOMEM;
-
-	/* set the IPC message data */
-	memcpy(msg, &config, sizeof(config));
-	memcpy(msg + sizeof(config), abi->data, abi->size);
-
-	/* send the message and check status */
-	err = plug_ipc_cmd_tx_rx(ipc, msg, msg_size, &reply, sizeof(reply));
-	free(msg);
-	if (err < 0) {
-		SNDERR("failed to send IPC to set bytes data\n");
-		return err;
-	}
-
-	if (reply.primary.r.status != IPC4_SUCCESS) {
-		SNDERR("IPC failed with status %d\n", reply.primary.r.status);
-		return -EINVAL;
-	}
-
-	return 0;
-}
-
-int plug_socket_create(struct plug_socket_desc *ipc)
-{
-	struct sockaddr_un addr;
-	int sockfd;
-
-	/* Check if the socket path already exists */
-	if (access(ipc->path, F_OK) != -1) {
-		/* If it exists, remove it */
-		if (unlink(ipc->path) == -1) {
-			SNDERR("unlink previous socket file");
-			return -EINVAL;
-		}
-	}
-
-	/* Create the socket */
-	sockfd = socket(AF_UNIX, SOCK_STREAM, 0);
-	if (sockfd == -1) {
-		SNDERR("failed to create new socket");
-		return sockfd;
-	}
-
-	ipc->socket_fd = sockfd;
-
-	memset(&addr, 0, sizeof(addr));
-	addr.sun_family = AF_UNIX;
-	strncpy(addr.sun_path, ipc->path, sizeof(addr.sun_path) - 1);
-
-	/* Bind the socket to the address */
-	if (bind(sockfd, (struct sockaddr *)&addr, sizeof(addr)) == -1) {
-		SNDERR("failed to bind new socket for IPC path\n");
-		close(sockfd);
-		return -EINVAL;
-	}
-
-	if (listen(sockfd, MAX_IPC_CLIENTS) == -1) {
-		SNDERR("failed to listen on socket for IPC\n");
-		return -EINVAL;
-	}
-
-	return 0;
-}
-
-static int set_socket_nonblocking(int sockfd)
-{
-	int flags = fcntl(sockfd, F_GETFL, 0);
-
-	if (flags == -1) {
-		SNDERR("fcntl(F_GETFL) failed");
-		return -EINVAL;
-	}
-
-	flags |= O_NONBLOCK;
-	if (fcntl(sockfd, F_SETFL, flags) == -1) {
-		SNDERR("fcntl(F_SETFL) failed");
-		return -EINVAL;
-	}
-
-	return 0;
-}
-
-int plug_create_client_socket(struct plug_socket_desc *ipc)
-{
-	struct sockaddr_un addr;
-	int sockfd;
-
-	sockfd = socket(AF_UNIX, SOCK_STREAM, 0);
-	if (sockfd == -1) {
-		SNDERR("error: failed to create sof-pipe IPC socket\n");
-		return sockfd;
-	}
-
-	if (set_socket_nonblocking(sockfd) < 0) {
-		close(sockfd);
-		return -EINVAL;
-	}
-	ipc->socket_fd = sockfd;
-
-	memset(&addr, 0, sizeof(addr));
-	addr.sun_family = AF_UNIX;
-	strncpy(addr.sun_path, ipc->path, sizeof(addr.sun_path) - 1);
-
-	/* Connect to the server (non-blocking) */
-	if (connect(sockfd, (struct sockaddr *)&addr, sizeof(addr)) == -1) {
-		if (errno != EINPROGRESS) {
-			SNDERR("failed to connect to ipc socket");
-			return -errno;
-		}
-	}
-
-	return sockfd;
-}
diff --git a/tools/plugin/common.h b/tools/plugin/common.h
deleted file mode 100644
index a64100c397cc..000000000000
--- a/tools/plugin/common.h
+++ /dev/null
@@ -1,328 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- *
- * Copyright(c) 2022-2023 Intel Corporation. All rights reserved.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#ifndef __SOF_PLUGIN_COMMON_H__
-#define __SOF_PLUGIN_COMMON_H__
-
-#include <stdint.h>
-#include <semaphore.h>
-#include <alsa/asoundlib.h>
-#include <ipc/control.h>
-#include <tplg_parser/topology.h>
-
-/* temporary - current MAXLEN is not define in UAPI header - fix pending */
-#ifndef SNDRV_CTL_ELEM_ID_NAME_MAXLEN
-#define SNDRV_CTL_ELEM_ID_NAME_MAXLEN	44
-#endif
-
-#include <alsa/sound/uapi/asoc.h>
-
-#define IPC3_MAX_MSG_SIZE	384
-#define NAME_SIZE	256
-
-#define MAX_CTLS	256
-
-#define MS_TO_US(_msus)	(_msus * 1000)
-#define MS_TO_NS(_msns) (MS_TO_US(_msns * 1000))
-
-#define MS_TO_US(_msus)	(_msus * 1000)
-#define MS_TO_NS(_msns) (MS_TO_US(_msns * 1000))
-
-#define SEM_PERMS (S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP)
-
-#define SHM_SIZE	(4096 * 64)	/* get from topology - and set for context */
-
-#define NUM_EP_CONFIGS		8
-
-#define MAX_IPC_CLIENTS	5
-
-/*
- * Run with valgrind
- * valgrind --trace-children=yes aplay -v -Dsof:blah.tplg,1,hw:1,2  -f dat /dev/zero
- */
-//#define VALGRIND
-#ifdef VALGRIND
-#define DEBUG_TV_SECS	10
-#define DEBUG_RETRIES	1000
-#else
-#define DEBUG_RETRIES	10
-#define DEBUG_TV_SECS	0
-#endif
-
-#define SOF_MAGIC	"sofpipe"
-#define MAX_VOLUME_SIZE 120
-#define MAX_DATA_SIZE	512
-
-enum plugin_state {
-	SOF_PLUGIN_STATE_INIT	= 0,
-	SOF_PLUGIN_STATE_READY	= 1,
-	SOF_PLUGIN_STATE_DEAD	= 2,
-	SOF_PLUGIN_STATE_STREAM_RUNNING	= 3,
-	SOF_PLUGIN_STATE_STREAM_ERROR	= 5,
-};
-
-struct plug_shm_ctl {
-	unsigned int module_id;
-	unsigned int instance_id;
-	unsigned int type;
-	unsigned int volume_table[MAX_VOLUME_SIZE];
-	unsigned int index;
-	char data[MAX_DATA_SIZE];
-	union {
-		struct snd_soc_tplg_mixer_control mixer_ctl;
-		struct snd_soc_tplg_enum_control enum_ctl;
-		struct snd_soc_tplg_bytes_control bytes_ctl;
-	};
-};
-
-/*
- *	config.48k2c {
- *		rate 48000
- *		channels 2
- *		period_time 0
- *		period_frames 6000
- *		buffer_time 0
- *		buffer_frames 24000
- *     }
- */
-struct plug_config {
-	char name[44];
-	unsigned long buffer_frames;
-	unsigned long buffer_time;
-	unsigned long period_frames;
-	unsigned long period_time;
-	int rate;
-	int channels;
-	unsigned long format;
-};
-
-/*
- * :[pcm:card:dev:config[pcm:card:dev:config]...]
- */
-struct plug_cmdline_item {
-	int pcm;
-	char card_name[44];
-	char dev_name[44];
-	char config_name[44];
-};
-
-/*
- * Endpoint pipeline configuration
- */
-struct endpoint_hw_config {
-	int pipeline;
-	char card_name[44];
-	char dev_name[44];
-	char config_name[44];
-	unsigned long buffer_frames;
-	unsigned long buffer_time;
-	unsigned long period_frames;
-	unsigned long period_time;
-	int rate;
-	int channels;
-	unsigned long format;
-};
-
-struct plug_shm_endpoint {
-	char magic[8];			/* SOF_MAGIC */
-	uint64_t state;
-	uint32_t pipeline_id;
-	uint32_t comp_id;
-	uint32_t idx;
-	unsigned long rpos;	/* current position in ring buffer */
-	unsigned long rwrap;
-	unsigned long wpos;	/* current position in ring buffer */
-	unsigned long wwrap;
-	unsigned long buffer_size;		/* buffer size */
-	unsigned long wtotal;		/* total frames copied */
-	unsigned long rtotal;		/* total frames copied */
-	int frame_size;
-	char data[0];		// TODO: align this on SIMD/cache
-};
-
-struct plug_shm_glb_state {
-	char magic[8];			/* SOF_MAGIC */
-	uint64_t size;			/* size of this structure in bytes */
-	uint64_t state;			/* enum plugin_state */
-	struct endpoint_hw_config ep_config[NUM_EP_CONFIGS];
-	int num_ep_configs;
-	uint64_t num_ctls;		/* number of ctls */
-	struct plug_shm_ctl ctl[];
-};
-
-struct plug_shm_desc {
-	/* SHM for stream context sync */
-	int fd;
-	int size;
-	char name[NAME_SIZE];
-	void *addr;
-};
-
-struct plug_socket_desc {
-	int socket_fd;
-	char path[NAME_SIZE];
-};
-
-struct plug_sem_desc {
-	char name[NAME_SIZE];
-	sem_t *sem;
-};
-
-struct plug_ctl_container {
-	struct snd_soc_tplg_ctl_hdr *tplg[MAX_CTLS];
-	int updated[MAX_CTLS];
-	int count;
-};
-
-static inline void *plug_ep_rptr(struct plug_shm_endpoint *ep)
-{
-	return ep->data + ep->rpos;
-}
-
-static inline void *plug_ep_wptr(struct plug_shm_endpoint *ep)
-{
-	return ep->data + ep->wpos;
-}
-
-static inline int plug_ep_wrap_rsize(struct plug_shm_endpoint *ep)
-{
-	return ep->buffer_size - ep->rpos;
-}
-
-static inline int plug_ep_wrap_wsize(struct plug_shm_endpoint *ep)
-{
-	return ep->buffer_size - ep->wpos;
-}
-
-static inline int plug_ep_get_free(struct plug_shm_endpoint *ep)
-{
-	if (ep->rwrap == ep->wwrap) {
-		/* calculate available bytes */
-		if (ep->rpos < ep->wpos)
-			return ep->buffer_size - (ep->wpos - ep->rpos);
-		else
-			return ep->buffer_size;
-	} else {
-		return ep->rpos - ep->wpos;
-	}
-}
-
-static inline int plug_ep_get_avail(struct plug_shm_endpoint *ep)
-{
-	if (ep->rwrap == ep->wwrap) {
-		/* calculate available bytes */
-		if (ep->rpos < ep->wpos)
-			return ep->wpos - ep->rpos;
-		else
-			return 0;
-	} else {
-		return (ep->buffer_size - ep->rpos) + ep->wpos;
-	}
-}
-
-static inline void *plug_ep_consume(struct plug_shm_endpoint *ep, unsigned int bytes)
-{
-	ep->rtotal += bytes;
-	ep->rpos += bytes;
-
-	if (ep->rpos >= ep->buffer_size) {
-		ep->rpos -= ep->buffer_size;
-		ep->rwrap++;
-	}
-
-	return ep->data + ep->rpos;
-}
-
-static inline void *plug_ep_produce(struct plug_shm_endpoint *ep, unsigned int bytes)
-{
-	ep->wtotal += bytes;
-	ep->wpos += bytes;
-
-	if (ep->wpos >= ep->buffer_size) {
-		ep->wpos -= ep->buffer_size;
-		ep->wwrap++;
-	}
-
-	return ep->data + ep->wpos;
-}
-
-/*
- * SHM
- */
-int plug_shm_init(struct plug_shm_desc *shm, const char *tplg, const char *type, int index);
-
-int plug_shm_create(struct plug_shm_desc *shm);
-
-int plug_shm_open(struct plug_shm_desc *shm);
-
-void plug_shm_free(struct plug_shm_desc *shm);
-
-/*
- * IPC
- */
-int plug_socket_path_init(struct plug_socket_desc *ipc, const char *tplg, const char *type,
-			  int index);
-
-void plug_socket_free(struct plug_socket_desc *ipc);
-
-int plug_ipc_cmd_tx_rx(struct plug_socket_desc *ipc, void *msg, size_t len, void *reply,
-		       size_t rlen);
-
-/*
- * Locking
- */
-int plug_lock_create(struct plug_sem_desc *lock);
-
-void plug_lock_free(struct plug_sem_desc *lock);
-
-int plug_lock_init(struct plug_sem_desc *lock, const char *tplg, const char *type, int index);
-
-int plug_lock_open(struct plug_sem_desc *lock);
-
-/*
- * Timing.
- */
-void plug_timespec_add_ms(struct timespec *ts, unsigned long ms);
-
-long plug_timespec_delta_ns(struct timespec *before, struct timespec *after);
-
-/* dump the IPC data - dont print lines of 0s */
-static inline void data_dump(void *vdata, size_t bytes)
-{
-	uint32_t *data = vdata;
-	size_t words = bytes >> 2;
-	int i;
-
-	for (i = 0; i < words; i++) {
-		/* 4 words per line */
-		if (i % 4 == 0) {
-			/* delete lines with all 0s */
-			if (i > 0 && data[i - 3] == 0 && data[i - 2] == 0 &&
-			    data[i - 1] == 0 && data[i - 0] == 0)
-				printf("\r");
-			else
-				printf("\n");
-
-			printf("0x%4.4x: 0x%8.8x", i, data[i]);
-		} else {
-			printf(" 0x%8.8x", data[i]);
-		}
-	}
-	printf("\n");
-}
-
-void plug_ctl_ipc_message(struct ipc4_module_large_config *config, int param_id,
-			  size_t size, uint32_t module_id, uint32_t instance_id,
-			  uint32_t type);
-int plug_send_bytes_data(struct plug_socket_desc *ipc, uint32_t module_id, uint32_t instance_id,
-			 struct sof_abi_hdr *abi);
-
-int plug_socket_create(struct plug_socket_desc *ipc);
-
-int plug_create_client_socket(struct plug_socket_desc *ipc);
-
-#endif
diff --git a/tools/plugin/modules/CMakeLists.txt b/tools/plugin/modules/CMakeLists.txt
deleted file mode 100644
index d737972cde7d..000000000000
--- a/tools/plugin/modules/CMakeLists.txt
+++ /dev/null
@@ -1,59 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-
-# File SHM pipe module
-add_library(sof_mod_shm MODULE
-	shm.c
-)
-sof_append_relative_path_definitions(sof_mod_shm)
-target_include_directories(sof_mod_shm PRIVATE
-	${CMAKE_CURRENT_SOURCE_DIR}
-	${CMAKE_CURRENT_SOURCE_DIR}/..
-	${CMAKE_CURRENT_SOURCE_DIR}/../pipe
-	${sof_source_directory}/src/audio)
-
-target_compile_options(sof_mod_shm PRIVATE -DPIC -g -O3 -Wall -Werror -DCONFIG_LIBRARY -imacros${config_h})
-
-install(TARGETS sof_mod_shm
-		DESTINATION /usr/lib/x86_64-linux-gnu/alsa-lib)
-
-target_link_options(sof_mod_shm PRIVATE -Wl,--export-dynamic)
-
-target_include_directories(sof_mod_shm PRIVATE ${sof_install_directory}/include)
-target_include_directories(sof_mod_shm PRIVATE ${parser_install_dir}/include)
-
-set_target_properties(sof_mod_shm
-	PROPERTIES
-	INSTALL_RPATH "${sof_install_directory}/alsa-lib"
-	INSTALL_RPATH_USE_LINK_PATH TRUE
-)
-
-
-# ALSA SOF pipe module
-add_library(sof_mod_alsa MODULE
-	alsa.c
-)
-sof_append_relative_path_definitions(sof_mod_alsa)
-target_include_directories(sof_mod_alsa PRIVATE
-	${CMAKE_CURRENT_SOURCE_DIR}
-	${CMAKE_CURRENT_SOURCE_DIR}/..
-	${CMAKE_CURRENT_SOURCE_DIR}/../pipe
-	${sof_source_directory}/src/audio)
-
-target_compile_options(sof_mod_alsa PRIVATE -DPIC -g -O3 -Wmissing-prototypes
-  -Wimplicit-fallthrough -Wall -Werror -DCONFIG_LIBRARY -imacros${config_h})
-
-install(TARGETS sof_mod_alsa
-		DESTINATION /usr/lib/x86_64-linux-gnu/alsa-lib)
-
-target_link_options(sof_mod_alsa PRIVATE -Wl,--export-dynamic)
-
-target_include_directories(sof_mod_alsa PRIVATE ${sof_install_directory}/include)
-target_include_directories(sof_mod_alsa PRIVATE ${parser_install_dir}/include)
-
-set_target_properties(sof_mod_alsa
-	PROPERTIES
-	INSTALL_RPATH "${sof_install_directory}/alsa-lib"
-	INSTALL_RPATH_USE_LINK_PATH TRUE
-)
-
-add_subdirectory(ov_noise_suppression)
diff --git a/tools/plugin/modules/alsa.c b/tools/plugin/modules/alsa.c
deleted file mode 100644
index 69442c687136..000000000000
--- a/tools/plugin/modules/alsa.c
+++ /dev/null
@@ -1,788 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-//
-// Copyright(c) 2022 Intel Corporation. All rights reserved.
-
-/* file component for reading/writing pcm samples to/from a file */
-
-#include <stdio.h>
-#include <stdint.h>
-#include <stddef.h>
-#include <stdlib.h>
-#include <errno.h>
-#include <inttypes.h>
-#include <sys/types.h>
-#include <sys/stat.h>
-#include <fcntl.h>
-
-#include <rtos/sof.h>
-#include <sof/list.h>
-#include <sof/audio/stream.h>
-#include <sof/audio/ipc-config.h>
-#include <sof/ipc/driver.h>
-#include <sof/audio/component.h>
-#include <sof/audio/format.h>
-#include <sof/audio/pipeline.h>
-#include <ipc/stream.h>
-#include <ipc/topology.h>
-#include <ipc/dai.h>
-
-#include <alsa/asoundlib.h>
-
-#include "pipe.h"
-
-SOF_DEFINE_REG_UUID(arecord);
-DECLARE_TR_CTX(arecord_tr, SOF_UUID(arecord_uuid), LOG_LEVEL_INFO);
-
-SOF_DEFINE_REG_UUID(aplay);
-DECLARE_TR_CTX(aplay_tr, SOF_UUID(aplay_uuid), LOG_LEVEL_INFO);
-
-static const struct comp_driver comp_arecord;
-static const struct comp_driver comp_aplay;
-
-/* ALSA comp data */
-struct alsa_comp_data {
-	snd_pcm_t *handle;
-	snd_pcm_info_t *info;
-	snd_pcm_hw_params_t *hw_params;
-	snd_pcm_sw_params_t *sw_params;
-	snd_pcm_uframes_t period_frames;
-	snd_pcm_uframes_t buffer_frames;
-	char *pcm_name;
-	struct sof_ipc_stream_params params;
-	struct plug_shm_desc pcm;
-	struct plug_shm_endpoint *ctx;
-	struct plug_shm_desc glb;
-	struct plug_shm_glb_state *glb_ctx;
-	struct endpoint_hw_config *ep_hw;
-#if CONFIG_IPC_MAJOR_4
-	struct ipc4_base_module_cfg base_cfg;
-#endif
-};
-
-static struct endpoint_hw_config *alsa_get_hw_config(struct comp_dev *dev)
-{
-	struct alsa_comp_data *cd = comp_get_drvdata(dev);
-	struct plug_shm_glb_state *glb = cd->glb_ctx;
-
-	if (!glb->num_ep_configs)
-		return NULL;
-
-	return glb->ep_config;
-}
-
-static int alsa_alloc(struct comp_dev *dev)
-{
-	struct alsa_comp_data *cd = comp_get_drvdata(dev);
-	int err;
-
-	/* get ALSA ready */
-	err = snd_pcm_info_malloc(&cd->info);
-	if (err < 0)
-		goto error;
-
-	err = snd_pcm_hw_params_malloc(&cd->hw_params);
-	if (err < 0)
-		goto error;
-
-	err = snd_pcm_sw_params_malloc(&cd->sw_params);
-	if (err < 0)
-		goto error;
-
-	comp_dbg(dev, "open done");
-	return 0;
-
-error:
-	return err;
-}
-
-static int alsa_close(struct comp_dev *dev)
-{
-	struct alsa_comp_data *cd = comp_get_drvdata(dev);
-	int ret = 0;
-
-	comp_dbg(dev, "close");
-	if (cd->handle) {
-		ret = snd_pcm_hw_free(cd->handle);
-		if (ret < 0)
-			comp_err(dev, "error: failed to snd_pcm_hw_free: %s\n", snd_strerror(ret));
-
-		ret = snd_pcm_close(cd->handle);
-		if (ret < 0)
-			comp_err(dev, "error: failed to snd_pcm_close: %s\n", snd_strerror(ret));
-
-		cd->handle = NULL;
-	}
-
-	return ret;
-}
-
-static void alsa_free(struct comp_dev *dev)
-{
-	struct alsa_comp_data *cd = comp_get_drvdata(dev);
-
-	comp_dbg(dev, "alsa_free()");
-
-	snd_pcm_sw_params_free(cd->sw_params);
-	snd_pcm_hw_params_free(cd->hw_params);
-	snd_pcm_info_free(cd->info);
-	plug_shm_free(&cd->pcm);
-	free(cd);
-	free(dev);
-}
-
-static struct comp_dev *alsa_new(const struct comp_driver *drv,
-				 const struct comp_ipc_config *config,
-				 const void *spec)
-{
-#if CONFIG_IPC_MAJOR_4
-	const struct ipc4_base_module_cfg *base_cfg = (struct ipc4_base_module_cfg *)spec;
-#endif
-	struct comp_dev *dev;
-	struct alsa_comp_data *cd;
-	int err;
-
-	dev = comp_alloc(drv, sizeof(*dev));
-	if (!dev)
-		return NULL;
-	dev->ipc_config = *config;
-
-	/* allocate  memory for file comp data */
-	cd = rzalloc(SOF_MEM_FLAG_USER, sizeof(*cd));
-	if (!cd)
-		goto error;
-
-	comp_set_drvdata(dev, cd);
-	memcpy(&cd->base_cfg, base_cfg, sizeof(struct ipc4_base_module_cfg));
-
-	/* use PCM ID to create shm */
-	err = plug_shm_init(&cd->pcm, _sp->topology_name, "pcm", 1);
-	if (err < 0) {
-		comp_err(dev, "Error initializing pcm\n");
-		goto error;
-	}
-
-	// TODO: get the shm size for the buffer using a better method
-	//cd->pcm.size = 128 * 1024;
-
-	/* mmap the SHM PCM */
-	err = plug_shm_open(&cd->pcm);
-	if (err < 0) {
-		comp_err(dev, "Error open pcm shm");
-		goto error;
-	}
-	cd->ctx = cd->pcm.addr;
-
-	err = plug_shm_init(&cd->glb, _sp->topology_name, "ctx", 0);
-	if (err < 0) {
-		comp_err(dev, "Error initializing ctx\n");
-		goto error;
-	}
-
-	// TODO: get the shm size for the buffer using a better method
-	//cd->pcm.size = 128 * 1024;
-
-	/* mmap the GLB ctx */
-	err = plug_shm_open(&cd->glb);
-	if (err < 0) {
-		comp_err(dev, "Error opening glb ctx\n");
-		goto error;
-	}
-	cd->glb_ctx = cd->glb.addr;
-
-	/* alloc alsa context */
-	err = alsa_alloc(dev);
-	if (err < 0) {
-		comp_err(dev, "Error allocating alsa context\n");
-		goto error;
-	}
-
-	return dev;
-
-error:
-	free(cd);
-	free(dev);
-	return NULL;
-}
-
-static struct comp_dev *arecord_new(const struct comp_driver *drv,
-				    const struct comp_ipc_config *config, const void *spec)
-{
-	struct comp_dev *dev;
-	struct alsa_comp_data *cd;
-
-	comp_dbg(dev, "arecord_new()");
-
-	dev = alsa_new(drv, config, spec);
-	if (!dev)
-		return NULL;
-
-	cd = comp_get_drvdata(dev);
-	cd->params.direction = SND_PCM_STREAM_CAPTURE;
-
-	dev->state = COMP_STATE_READY;
-	return dev;
-}
-
-static struct comp_dev *aplay_new(const struct comp_driver *drv,
-				  const struct comp_ipc_config *config,
-				  const void *spec)
-{
-	struct comp_dev *dev;
-	struct alsa_comp_data *cd;
-
-	comp_dbg(dev, "aplay_new()");
-
-	dev = alsa_new(drv, config, spec);
-	if (!dev)
-		return NULL;
-
-	cd = comp_get_drvdata(dev);
-	cd->params.direction = SND_PCM_STREAM_PLAYBACK;
-
-	dev->state = COMP_STATE_READY;
-	return dev;
-}
-
-static int set_params(struct comp_dev *dev)
-{
-	struct alsa_comp_data *cd = comp_get_drvdata(dev);
-	struct sof_ipc_stream_params *params = &cd->params;
-	int frame_fmt;
-	int err;
-
-	err = snd_pcm_open(&cd->handle, cd->pcm_name, cd->params.direction, 0);
-	if (err < 0) {
-		comp_err(dev, "error: cant open PCM %s: %s\n", cd->pcm_name, snd_strerror(err));
-		return err;
-	}
-
-	err = snd_pcm_info(cd->handle, cd->info);
-	if (err < 0) {
-		comp_err(dev, "error: cant get PCM info: %s\n", snd_strerror(err));
-		return err;
-	}
-
-	/* set sample format */
-	switch (params->frame_fmt) {
-	case SOF_IPC_FRAME_S16_LE:
-		frame_fmt = SND_PCM_FORMAT_S16_LE;
-		break;
-	case SOF_IPC_FRAME_S24_4LE:
-		frame_fmt = SND_PCM_FORMAT_S24_LE;
-		break;
-	case SOF_IPC_FRAME_S32_LE:
-		frame_fmt = SND_PCM_FORMAT_S32_LE;
-		break;
-	case SOF_IPC_FRAME_FLOAT:
-		frame_fmt = SND_PCM_FORMAT_FLOAT_LE;
-		break;
-	case SOF_IPC_FRAME_S24_3LE:
-		frame_fmt = SND_PCM_FORMAT_S24_3LE;
-		break;
-	default:
-		comp_err(dev, "error: invalid frame format %d for ALSA PCM\n", params->frame_fmt);
-		return -EINVAL;
-	}
-
-	/* commit playback hw_params and sw_params. Set latency of 10ms to avoid glitches */
-	if (cd->params.direction == SND_PCM_STREAM_PLAYBACK)
-		return snd_pcm_set_params(cd->handle, frame_fmt, SND_PCM_ACCESS_RW_INTERLEAVED,
-					  params->channels, params->rate, 0, 10000);
-
-	/* is sound card HW configuration valid ? */
-	err = snd_pcm_hw_params_any(cd->handle, cd->hw_params);
-	if (err < 0) {
-		comp_err(dev, "error: cant get PCM hw_params: %s\n", snd_strerror(err));
-		return err;
-	}
-
-	/* set interleaved buffer format */
-	err = snd_pcm_hw_params_set_access(cd->handle, cd->hw_params,
-					   SND_PCM_ACCESS_RW_INTERLEAVED);
-	if (err < 0) {
-		comp_err(dev, "error: PCM can't set interleaved: %s\n", snd_strerror(err));
-		return err;
-	}
-
-	err = snd_pcm_hw_params_set_format(cd->handle, cd->hw_params, frame_fmt);
-	if (err < 0) {
-		comp_err(dev, "error: PCM can't set format %d: %s\n",
-			 frame_fmt, snd_strerror(err));
-		return err;
-	}
-
-	/* set number of channels */
-	err = snd_pcm_hw_params_set_channels(cd->handle, cd->hw_params, params->channels);
-	if (err < 0) {
-		comp_err(dev, "error: PCM can't set channels %d: %s\n",
-			 params->channels, snd_strerror(err));
-		return err;
-	}
-
-	/* set sample rate */
-	err = snd_pcm_hw_params_set_rate(cd->handle, cd->hw_params, params->rate, 0);
-	if (err < 0) {
-		comp_err(dev, "error: PCM can't set rate %d: %s\n",
-			 params->rate, snd_strerror(err));
-		return err;
-	}
-
-	/* set period size TODO: get from topology */
-	err = snd_pcm_hw_params_set_period_size(cd->handle, cd->hw_params,
-						cd->period_frames, 0);
-	if (err < 0) {
-		comp_err(dev, "error: PCM can't set period size %ld frames: %s\n",
-			 cd->period_frames, snd_strerror(err));
-		return err;
-	}
-
-	/* set buffer size: TODO: get from topology */
-	err = snd_pcm_hw_params_set_buffer_size_near(cd->handle, cd->hw_params,
-						     &cd->buffer_frames);
-	if (err < 0) {
-		comp_err(dev, "error: PCM can't set buffer size %ld frames: %s\n",
-			 cd->buffer_frames, snd_strerror(err));
-		return err;
-	}
-
-	/* commit the hw params */
-	err = snd_pcm_hw_params(cd->handle, cd->hw_params);
-	if (err < 0) {
-		comp_err(dev, "error: PCM can't commit hw_params: %s\n", snd_strerror(err));
-		snd_pcm_hw_params_dump(cd->hw_params, SND_OUTPUT_STDIO);
-		return err;
-	}
-
-	/* get the initial SW params */
-	err = snd_pcm_sw_params_current(cd->handle, cd->sw_params);
-	if (err < 0) {
-		comp_err(dev, "error: PCM can't get sw params: %s\n", snd_strerror(err));
-		return err;
-	}
-
-	/* set the avail min to the period size */
-	err = snd_pcm_sw_params_set_avail_min(cd->handle, cd->sw_params, cd->period_frames);
-	if (err < 0) {
-		comp_err(dev, "error: PCM can't set avail min: %s\n", snd_strerror(err));
-		return err;
-	}
-
-	/* PCM should start after receiving first periods worth of data */
-	err = snd_pcm_sw_params_set_start_threshold(cd->handle, cd->sw_params, 1);
-	if (err < 0) {
-		comp_err(dev, "error: PCM can't set start threshold: %s\n", snd_strerror(err));
-		return err;
-	}
-
-	/* PCM should stop if only buffer_frame worth of data is available */
-	err = snd_pcm_sw_params_set_stop_threshold(cd->handle, cd->sw_params,
-						   cd->buffer_frames);
-	if (err < 0) {
-		comp_err(dev, "error: PCM can't set stop threshold: %s\n", snd_strerror(err));
-		return err;
-	}
-
-	/* commit the sw params */
-	if (snd_pcm_sw_params(cd->handle, cd->sw_params) < 0) {
-		comp_err(dev, "error: PCM can't commit sw_params: %s\n", snd_strerror(err));
-		snd_pcm_sw_params_dump(cd->sw_params, SND_OUTPUT_STDIO);
-		return err;
-	}
-
-	comp_dbg(dev, "params set");
-	return 0;
-}
-
-static int alsa_dai_get_hw_params(struct comp_dev *dev,
-				  struct sof_ipc_stream_params *params, int dir);
-
-/**
- * \brief Sets file component audio stream parameters.
- * \param[in,out] dev Volume base component device.
- * \param[in] params Audio (PCM) stream parameters (ignored for this component)
- * \return Error code.
- *
- * All done in prepare() since we need to know source and sink component params.
- */
-static int arecord_params(struct comp_dev *dev, struct sof_ipc_stream_params *params)
-{
-	struct comp_buffer *buffer;
-	struct alsa_comp_data *cd = comp_get_drvdata(dev);
-	int ret;
-
-	comp_dbg(dev, "arecord params");
-
-	ret = alsa_dai_get_hw_params(dev, params, cd->params.direction);
-
-	if (params->direction != SND_PCM_STREAM_CAPTURE) {
-		comp_err(dev, "alsa_params(): pcm params invalid direction.");
-		return -EINVAL;
-	}
-
-	/* params can be aligned to match pipeline here */
-	ret = comp_verify_params(dev, 0, params);
-	if (ret < 0) {
-		comp_err(dev, "alsa_params(): pcm params verification failed.");
-		return ret;
-	}
-	memcpy(&cd->params, params, sizeof(*params));
-
-	/* file component sink/source buffer period count */
-	buffer = comp_dev_get_first_data_consumer(dev);
-	audio_buffer_reset(&buffer->audio_buffer);
-
-	comp_dbg(dev, "prepare done ret = %d", ret);
-
-	return 0;
-}
-
-static int aplay_params(struct comp_dev *dev, struct sof_ipc_stream_params *params)
-{
-	struct comp_buffer *buffer;
-	struct alsa_comp_data *cd = comp_get_drvdata(dev);
-	int ret;
-
-	comp_dbg(dev, "aplay params");
-
-	ret = alsa_dai_get_hw_params(dev, params, cd->params.direction);
-
-	if (params->direction != SND_PCM_STREAM_PLAYBACK) {
-		comp_err(dev, "alsa_params(): pcm params invalid direction.");
-		return -EINVAL;
-	}
-
-	/* params can be aligned to match pipeline here */
-	ret = comp_verify_params(dev, 0, params);
-	if (ret < 0) {
-		comp_err(dev, "alsa_params(): pcm params verification failed.");
-		return ret;
-	}
-	memcpy(&cd->params, params, sizeof(*params));
-
-	/* file component sink/source buffer period count */
-	buffer = comp_dev_get_first_data_producer(dev);
-	audio_buffer_reset(&buffer->audio_buffer);
-
-	comp_dbg(dev, "prepare done ret = %d", ret);
-	return 0;
-}
-
-static int alsa_trigger(struct comp_dev *dev, int cmd)
-{
-	int err;
-
-	/* trigger is handled automatically by ALSA start threshold */
-	comp_dbg(dev, "trigger cmd %d", cmd);
-
-	switch (cmd) {
-	case COMP_TRIGGER_PAUSE:
-	case COMP_TRIGGER_STOP:
-		err = alsa_close(dev);
-		if (err < 0) {
-			comp_err(dev, "error: cant stop pipeline");
-			return err;
-		}
-		break;
-	case COMP_TRIGGER_RELEASE:
-	case COMP_TRIGGER_START:
-		err = set_params(dev);
-		if (err < 0) {
-			comp_err(dev, "error: cant stop pipeline");
-			return err;
-		}
-		break;
-	default:
-		break;
-	}
-
-	return comp_set_state(dev, cmd);
-}
-
-/* used to pass standard and bespoke commands (with data) to component */
-static int alsa_cmd(struct comp_dev *dev, int cmd, void *data,
-		    int max_data_size)
-{
-	return 0;
-}
-
-/*
- * copy and process stream samples
- * returns the number of bytes copied
- */
-static int arecord_copy(struct comp_dev *dev)
-{
-	struct alsa_comp_data *cd = comp_get_drvdata(dev);
-	struct comp_buffer *buffer;
-	struct audio_stream *sink;
-	snd_pcm_sframes_t frames;
-	snd_pcm_uframes_t free;
-	snd_pcm_uframes_t total = 0;
-	unsigned int frame_bytes;
-	void *pos;
-
-	switch (dev->state) {
-	case COMP_STATE_ACTIVE:
-		break;
-	default:
-		return -EINVAL;
-	}
-
-	/* file component sink buffer */
-	buffer = comp_dev_get_first_data_consumer(dev);
-	sink = &buffer->stream;
-	pos = sink->w_ptr;
-
-	//FIX: this will fill buffer and higher latency, use period size
-	free = MIN(audio_stream_get_free_frames(sink), cd->period_frames);
-	frame_bytes = audio_stream_frame_bytes(sink);
-
-	while (free) {
-		frames = MIN(free, audio_stream_frames_without_wrap(sink, pos));
-
-		/* read PCM samples from file */
-		frames = snd_pcm_readi(cd->handle, pos, frames);
-		if (frames < 0) {
-			if (frames == -EPIPE) {
-				snd_pcm_prepare(cd->handle);
-				continue;
-			}
-			comp_err(dev, "failed to read: %s: %s\n",
-				 cd->pcm_name, snd_strerror(frames));
-			return frames;
-		}
-
-		free -= frames;
-		pos = audio_stream_wrap(sink, pos + frames * frame_bytes);
-		total += frames;
-	}
-
-	/* update sink buffer pointers */
-	comp_update_buffer_produce(buffer, total * frame_bytes);
-	comp_dbg(dev, "read %d frames", total);
-
-	return 0;
-}
-
-/*
- * copy and process stream samples
- * returns the number of bytes copied
- */
-static int aplay_copy(struct comp_dev *dev)
-{
-	struct alsa_comp_data *cd = comp_get_drvdata(dev);
-	struct comp_buffer *buffer;
-	struct audio_stream *source;
-	snd_pcm_sframes_t frames;
-	snd_pcm_sframes_t avail;
-	snd_pcm_uframes_t total = 0;
-	unsigned int frame_bytes;
-	void *pos;
-
-	switch (dev->state) {
-	case COMP_STATE_ACTIVE:
-		break;
-	default:
-		return -EINVAL;
-	}
-
-	/* file component source buffer */
-	buffer = comp_dev_get_first_data_producer(dev);
-	source = &buffer->stream;
-	pos = source->r_ptr;
-	avail = audio_stream_get_avail_frames(source);
-	frame_bytes = audio_stream_frame_bytes(source);
-
-	while (avail > 0) {
-		frames = MIN(avail, audio_stream_frames_without_wrap(source, pos));
-
-		/* write PCM samples to PCM */
-		frames = snd_pcm_writei(cd->handle, pos, frames);
-		if (frames < 0) {
-			if (frames == -EPIPE) {
-				snd_pcm_prepare(cd->handle);
-				continue;
-			}
-			comp_err(dev, "failed to write: %s: %s\n",
-				 cd->pcm_name, snd_strerror(frames));
-			return frames;
-		}
-		avail -= frames;
-		pos = audio_stream_wrap(source, pos + frames * frame_bytes);
-		total += frames;
-	}
-
-	/* update sink buffer pointers */
-	comp_update_buffer_consume(buffer, total * frame_bytes);
-	comp_dbg(dev, "wrote %d bytes", total * frame_bytes);
-
-	return 0;
-}
-
-static int alsa_prepare(struct comp_dev *dev)
-{
-	int ret = 0;
-
-	comp_dbg(dev, "prepare");
-	ret = comp_set_state(dev, COMP_TRIGGER_PREPARE);
-	if (ret < 0)
-		return ret;
-
-	if (ret == COMP_STATUS_STATE_ALREADY_SET)
-		return PPL_STATUS_PATH_STOP;
-
-	return ret;
-}
-
-static int alsa_reset(struct comp_dev *dev)
-{
-	comp_dbg(dev, "reset");
-
-	comp_set_state(dev, COMP_TRIGGER_RESET);
-
-	return 0;
-}
-
-/*
- * TODO: we pass the DAI topology config back up the pipeline so
- * that upstream/downstream can be configured. Needs to be configured
- * at stream runtime instead of at topology load time.
- */
-static int alsa_dai_get_hw_params(struct comp_dev *dev, struct sof_ipc_stream_params *params,
-				  int dir)
-{
-	struct alsa_comp_data *cd = comp_get_drvdata(dev);
-	struct endpoint_hw_config *ep_hw;
-	char pcm_name[128];
-
-	comp_dbg(dev, "get_hw_params");
-
-	/* get our hw config from cmdline and conf file */
-	ep_hw = alsa_get_hw_config(dev);
-	if (!ep_hw) {
-		comp_err(dev, "error: failed to get hw config %d\n");
-		return -EINVAL;
-	}
-	cd->ep_hw = ep_hw;
-
-	/* PCM name comes from cmd line - "default" dev means dont use dev  */
-	if (!strncmp(cd->ep_hw->dev_name, "default", sizeof(cd->ep_hw->dev_name))) {
-		snprintf(pcm_name, sizeof(pcm_name), "%s", cd->ep_hw->card_name);
-	} else {
-		snprintf(pcm_name, sizeof(pcm_name), "hw:%s,%s",
-			 cd->ep_hw->card_name, cd->ep_hw->dev_name);
-	}
-	cd->pcm_name = strdup(pcm_name);
-	comp_dbg(dev, "using ALSA card %s", cd->pcm_name);
-
-	/* set default config - get from cmdline and plugin config */
-	cd->params.rate = cd->ep_hw->rate;
-	cd->params.channels = cd->ep_hw->channels;
-	cd->buffer_frames = cd->ep_hw->buffer_frames;
-	cd->period_frames = cd->ep_hw->period_frames;
-
-	/* ALSA API uses frames, SOF buffer uses bytes */
-	switch (cd->ep_hw->format) {
-	case SND_PCM_FORMAT_S16_LE:
-		cd->params.frame_fmt = SOF_IPC_FRAME_S16_LE;
-		cd->params.buffer.size = cd->ep_hw->buffer_frames * 2;
-		break;
-	case SND_PCM_FORMAT_S24_LE:
-		cd->params.frame_fmt = SOF_IPC_FRAME_S24_4LE;
-		cd->params.buffer.size = cd->ep_hw->buffer_frames * 4;
-		break;
-	case SND_PCM_FORMAT_S32_LE:
-		cd->params.frame_fmt = SOF_IPC_FRAME_S32_LE;
-		cd->params.buffer.size = cd->ep_hw->buffer_frames * 4;
-		break;
-	case SND_PCM_FORMAT_FLOAT:
-		cd->params.frame_fmt = SOF_IPC_FRAME_FLOAT;
-		cd->params.buffer.size = cd->ep_hw->buffer_frames * 4;
-		break;
-	case SND_PCM_FORMAT_S24_3LE:
-		cd->params.frame_fmt = SOF_IPC_FRAME_S24_3LE;
-		cd->params.buffer.size = cd->ep_hw->buffer_frames * 3;
-		break;
-	default:
-		comp_err(dev, "error: invalid frame format %d for ALSA PCM\n", params->frame_fmt);
-		return -EINVAL;
-	}
-
-	memcpy(params, &cd->params, sizeof(*params));
-
-	comp_dbg(dev, "rate %d", params->rate);
-	comp_dbg(dev, "frame format %d", params->frame_fmt);
-	comp_dbg(dev, "channels %d", params->channels);
-	comp_dbg(dev, "buffer frames %d", cd->buffer_frames);
-	comp_dbg(dev, "period frames %d", cd->period_frames);
-	comp_dbg(dev, "direction %d", params->direction);
-
-	return 0;
-}
-
-static int alsa_get_attribute(struct comp_dev *dev, uint32_t type, void *value)
-{
-	struct alsa_comp_data *cd = comp_get_drvdata(dev);
-
-	switch (type) {
-	case COMP_ATTR_BASE_CONFIG:
-		memcpy_s(value, sizeof(struct ipc4_base_module_cfg),
-			 &cd->base_cfg, sizeof(struct ipc4_base_module_cfg));
-		break;
-	default:
-		return -EINVAL;
-	}
-
-	return 0;
-}
-
-static const struct comp_driver comp_arecord = {
-	.type = SOF_COMP_FILEREAD,
-	.uid = SOF_RT_UUID(arecord_uuid),
-	.tctx	= &arecord_tr,
-	.ops = {
-		.create = arecord_new,
-		.free = alsa_free,
-		.params = arecord_params,
-		.cmd = alsa_cmd,
-		.trigger = alsa_trigger,
-		.copy = arecord_copy,
-		.prepare = alsa_prepare,
-		.reset = alsa_reset,
-		.dai_get_hw_params = alsa_dai_get_hw_params,
-		.get_attribute = alsa_get_attribute,
-	},
-};
-
-static const struct comp_driver comp_aplay = {
-	.type = SOF_COMP_FILEWRITE,
-	.uid = SOF_RT_UUID(aplay_uuid),
-	.tctx	= &aplay_tr,
-	.ops = {
-		.create = aplay_new,
-		.free = alsa_free,
-		.params = aplay_params,
-		.cmd = alsa_cmd,
-		.trigger = alsa_trigger,
-		.copy = aplay_copy,
-		.prepare = alsa_prepare,
-		.reset = alsa_reset,
-		.dai_get_hw_params = alsa_dai_get_hw_params,
-		.get_attribute = alsa_get_attribute,
-	},
-};
-
-static struct comp_driver_info comp_arecord_info = {
-	.drv = &comp_arecord,
-};
-
-static struct comp_driver_info comp_aplay_info = {
-	.drv = &comp_aplay,
-};
-
-static void sys_comp_alsa_init(void)
-{
-	comp_register(&comp_arecord_info);
-	comp_register(&comp_aplay_info);
-}
-
-DECLARE_MODULE(sys_comp_alsa_init);
diff --git a/tools/plugin/modules/ov_noise_suppression/CMakeLists.txt b/tools/plugin/modules/ov_noise_suppression/CMakeLists.txt
deleted file mode 100644
index fcf1439d0510..000000000000
--- a/tools/plugin/modules/ov_noise_suppression/CMakeLists.txt
+++ /dev/null
@@ -1,60 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-
-# Noise suppression module
-find_package(OpenVINO COMPONENTS Runtime)
-
-if(OpenVINO_FOUND)
-add_library(sof_ns_interface STATIC noise_suppression_interface.cpp)
-target_link_libraries(sof_ns_interface PRIVATE -Wl,--export-dynamic)
-target_link_libraries(sof_ns_interface PRIVATE openvino::runtime)
-target_compile_options(sof_ns_interface PRIVATE -fPIC)
-target_include_directories(sof_ns_interface PRIVATE ${sof_source_directory}/src/include)
-target_include_directories(sof_ns_interface PRIVATE ${sof_source_directory}/posix/include)
-target_include_directories(sof_ns_interface PRIVATE ${sof_source_directory}/src/arch/host/include)
-target_include_directories(sof_ns_interface PRIVATE ${sof_source_directory}/src/platform/posix/include)
-set_target_properties(sof_ns_interface PROPERTIES LINKER_LANGUAGE CXX)
-sof_append_relative_path_definitions(sof_ns_interface)
-install(TARGETS sof_ns_interface DESTINATION /usr/lib/x86_64-linux-gnu/alsa-lib)
-
-add_library(sof_ns MODULE noise_suppression.c)
-target_link_libraries(sof_ns PRIVATE sof_ns_interface)
-target_link_libraries(sof_ns PRIVATE -Wl,--export-dynamic)
-sof_append_relative_path_definitions(sof_ns)
-target_compile_options(sof_ns PRIVATE -DPIC -g -O3 -Wall -Werror -DCONFIG_LIBRARY -imacros${config_h})
-install(TARGETS sof_ns DESTINATION /usr/lib/x86_64-linux-gnu/alsa-lib)
-
-target_include_directories(sof_ns PRIVATE
-	${CMAKE_CURRENT_SOURCE_DIR}
-	${CMAKE_CURRENT_SOURCE_DIR}/..
-	${CMAKE_CURRENT_SOURCE_DIR}/../pipe
-	${sof_source_directory}/src/audio)
-
-
-target_link_options(sof_ns PRIVATE -Wl,--export-dynamic)
-target_include_directories(sof_ns PRIVATE ${sof_install_directory}/include)
-target_include_directories(sof_ns PRIVATE ${parser_install_dir}/include)
-
-set_target_properties(sof_ns
-	PROPERTIES
-	INSTALL_RPATH "${sof_install_directory}/alsa-lib"
-	INSTALL_RPATH_USE_LINK_PATH TRUE
-)
-
-# Regression test for the input-shape validation guard. Gated on
-# OpenVINO_FOUND alongside the module itself, so a host without
-# OpenVINO simply skips it.
-add_executable(test_ns_shape_validation test_ns_shape_validation.cpp)
-target_link_libraries(test_ns_shape_validation PRIVATE sof_ns_interface)
-target_include_directories(test_ns_shape_validation PRIVATE
-	${CMAKE_CURRENT_SOURCE_DIR}
-	${sof_source_directory}/src/include
-	${sof_source_directory}/posix/include
-	${sof_source_directory}/src/arch/host/include
-	${sof_source_directory}/src/platform/posix/include)
-set_target_properties(test_ns_shape_validation PROPERTIES LINKER_LANGUAGE CXX)
-
-add_test(NAME ns_shape_zero
-	COMMAND test_ns_shape_validation --dim 0 --dim 480)
-add_test(NAME ns_shape_overflow
-	COMMAND test_ns_shape_validation --dim 9223372036854775807 --dim 1024)
-endif()
diff --git a/tools/plugin/modules/ov_noise_suppression/noise_suppression.c b/tools/plugin/modules/ov_noise_suppression/noise_suppression.c
deleted file mode 100644
index 08c5ecca791d..000000000000
--- a/tools/plugin/modules/ov_noise_suppression/noise_suppression.c
+++ /dev/null
@@ -1,111 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-//
-// Copyright(c) 2024 Intel Corporation. All rights reserved.
-//
-// Author: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
-
-#include <sof/audio/buffer.h>
-#include <sof/audio/format.h>
-#include <sof/audio/module_adapter/module/generic.h>
-#include <sof/audio/pipeline.h>
-#include <rtos/panic.h>
-#include <sof/ipc/msg.h>
-#include <rtos/alloc.h>
-#include <rtos/cache.h>
-#include <rtos/init.h>
-#include <sof/lib/memory.h>
-#include <sof/lib/notifier.h>
-#include <sof/lib/uuid.h>
-#include <sof/list.h>
-#include <rtos/string.h>
-#include <sof/ut.h>
-#include <sof/trace/trace.h>
-#include <user/trace.h>
-#include <errno.h>
-#include <stddef.h>
-#include <stdint.h>
-
-#include "noise_suppression_interface.h"
-
-LOG_MODULE_REGISTER(ns, CONFIG_SOF_LOG_LEVEL);
-
-SOF_DEFINE_REG_UUID(ns);
-
-DECLARE_TR_CTX(ns_comp_tr, SOF_UUID(ns_uuid), LOG_LEVEL_INFO);
-
-static int ns_free(struct processing_module *mod)
-{
-	ns_handle handle = module_get_private_data(mod);
-
-	ov_ns_free(handle);
-	return 0;
-}
-
-static int ns_init(struct processing_module *mod)
-{
-	struct module_data *mod_data = &mod->priv;
-
-	return ov_ns_init(&mod_data->private);
-}
-
-static int
-ns_process(struct processing_module *mod,
-	   struct sof_source **sources, int num_of_sources,
-	   struct sof_sink **sinks, int num_of_sinks)
-{
-	ns_handle handle = module_get_private_data(mod);
-	struct sof_source *source = sources[0];
-	struct sof_sink *sink = sinks[0];
-	const size_t frame_bytes = source_get_frame_bytes(source);
-	struct cir_buf_source src_desc;
-	struct cir_buf_sink snk_desc;
-	size_t buf_size;
-	size_t copy_bytes;
-	size_t frames;
-	int ret;
-
-	frames = source_get_data_frames_available(source);
-	frames = MIN(frames, sink_get_free_frames(sink));
-
-	/* Noise suppression keeps the stream format and channel count, so the
-	 * source and sink consume and produce the same number of bytes.
-	 */
-	copy_bytes = frames * frame_bytes;
-	if (copy_bytes == 0)
-		return 0;
-
-	ret = source_get_data(source, copy_bytes, &src_desc.ptr, &src_desc.buf_start, &buf_size);
-	if (ret)
-		return ret;
-
-	src_desc.buf_end = (const char *)src_desc.buf_start + buf_size;
-
-	ret = sink_get_buffer(sink, copy_bytes, &snk_desc.ptr, &snk_desc.buf_start, &buf_size);
-	if (ret) {
-		source_release_data(source, 0);
-		return ret;
-	}
-
-	snk_desc.buf_end = (char *)snk_desc.buf_start + buf_size;
-
-	ret = ov_ns_process(handle, &src_desc, &snk_desc, frames);
-	if (ret < 0) {
-		source_release_data(source, 0);
-		sink_commit_buffer(sink, 0);
-		return ret;
-	}
-
-	source_release_data(source, ret * frame_bytes);
-	sink_commit_buffer(sink, ret * frame_bytes);
-
-	return 0;
-}
-
-static const struct module_interface ns_interface = {
-	.init = ns_init,
-	.process = ns_process,
-	.free = ns_free
-};
-
-DECLARE_MODULE_ADAPTER(ns_interface, ns_uuid, ns_comp_tr);
-SOF_MODULE_INIT(ns, sys_comp_module_ns_interface_init);
diff --git a/tools/plugin/modules/ov_noise_suppression/noise_suppression_interface.cpp b/tools/plugin/modules/ov_noise_suppression/noise_suppression_interface.cpp
deleted file mode 100644
index fdf068a24442..000000000000
--- a/tools/plugin/modules/ov_noise_suppression/noise_suppression_interface.cpp
+++ /dev/null
@@ -1,189 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-//
-// Copyright(c) 2024 Intel Corporation. All rights reserved.
-//
-// Author: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
-
-
-#include <stddef.h>
-#include <module/module/interface.h>
-#include <sof/audio/audio_stream.h>
-#include <openvino/openvino.hpp>
-
-#include "noise_suppression_interface.h"
-#define NS_MAX_SOURCE_CHANNELS 2
-#define NS_MAX_SHAPE_DIM (1u << 24)
-
-extern "C" {
-	struct ns_data {
-		std::shared_ptr<ov::Model> model;
-		std::vector<std::pair<std::string, std::string>> state_names;
-		ov::InferRequest infer_request[NS_MAX_SOURCE_CHANNELS];
-		ov::Shape inp_shape;
-		int iter;
-	};
-
-	int ov_ns_init(ns_handle *handle) {
-		struct ns_data *nd;
-		ov::OutputVector inputs, outputs;
-		ov::Core core;
-		size_t state_size = 0;
-		const char* model_name = std::getenv("NOISE_SUPPRESSION_MODEL_NAME");
-		std::string device("CPU");
-		int i;
-
-		nd = new ns_data();
-		if(!nd)
-			return -ENOMEM;
-
-		*handle = nd;
-		nd->model = core.read_model(model_name);
-		inputs = nd->model->inputs();
-		outputs = nd->model->outputs();
-
-		/* get state name pairs */
-		for (size_t i = 0; i < inputs.size(); i++) {
-			std::string inp_state_name = inputs[i].get_any_name();
-			if (inp_state_name.find("inp_state_") == std::string::npos)
-			    continue;
-
-			std::string out_state_name(inp_state_name);
-			out_state_name.replace(0, 3, "out");
-
-			/* find corresponding output state */
-			if (outputs.end() == std::find_if(outputs.begin(), outputs.end(), [&out_state_name](const ov::Output<ov::Node>& output) {
-				return output.get_any_name() == out_state_name;
-			}))
-				return -EINVAL;
-
-			nd->state_names.emplace_back(inp_state_name, out_state_name);
-
-			ov::Shape shape = inputs[i].get_shape();
-			size_t tensor_size = std::accumulate(shape.begin(), shape.end(), 1,
-							     std::multiplies<size_t>());
-
-			state_size += tensor_size;
-		}
-
-		if (!state_size)
-			return -EINVAL;
-
-		/*
-		 * query the list of available devices and use NPU if available, otherwise use
-		 * CPU by default
-		 */
-		std::vector<std::string> available_devices = core.get_available_devices();
-		for (auto &s: available_devices) {
-			if (!s.compare("NPU")) {
-				device.assign("NPU");
-				break;
-			}
-		}
-
-		/* save the infer_request objects for each channel separately */
-		ov::CompiledModel compiled_model = core.compile_model(nd->model, device, {});
-		for (i = 0; i < NS_MAX_SOURCE_CHANNELS; i++)
-			nd->infer_request[i] = compiled_model.create_infer_request();
-
-		nd->inp_shape = nd->model->input("input").get_shape();
-		for (auto dim : nd->inp_shape)
-			if (!dim || dim > NS_MAX_SHAPE_DIM)
-				return -EINVAL;
-
-		return 0;
-	}
-
-	void ov_ns_free(ns_handle handle) {
-		struct ns_data *nd = (struct ns_data *)handle;
-
-		delete nd;
-	}
-
-	int ov_ns_process(ns_handle handle,
-			  struct cir_buf_source *source,
-			  struct cir_buf_sink *sink,
-			  size_t frame_count)
-	{
-		struct ns_data *nd = (struct ns_data *)handle;
-		std::vector<float> inp_wave_fp32, out_wave_fp32;
-		/* only 16-bit supported for now */
-		const int16_t *input_data = static_cast<const int16_t *>(source->ptr);
-		int16_t *output_data = static_cast<int16_t *>(sink->ptr);
-		float scale = 1.0f / std::numeric_limits<int16_t>::max();
-
-		/*
-		 * The noise suppression model only supports mono, so process each channel
-		 * separately
-		 */
-		inp_wave_fp32.resize(frame_count, 0);
-		out_wave_fp32.resize(frame_count, 0);
-
-		for (unsigned int ch = 0; ch < NS_MAX_SOURCE_CHANNELS; ch++) {
-			const int16_t *inp = input_data + ch;
-
-			/* split each channel samples and convert to floating point */
-			for (size_t i = 0; i < frame_count; i++) {
-				inp_wave_fp32[i] = static_cast<float>(*inp) * scale;
-
-				inp = static_cast<const int16_t *>(
-					source_cir_buf_wrap(inp + NS_MAX_SOURCE_CHANNELS,
-							    source->buf_start,
-							    source->buf_end));
-			}
-
-			ov::Tensor input_tensor(ov::element::f32, nd->inp_shape,
-						&inp_wave_fp32[0]);
-			nd->infer_request[ch].set_tensor("input", input_tensor);
-
-			for (auto& state_name: nd->state_names) {
-				const std::string& inp_state_name = state_name.first;
-				const std::string& out_state_name = state_name.second;
-				ov::Tensor state_tensor;
-				ov::Shape state_shape;
-
-				state_shape = nd->model->input(inp_state_name).get_shape();
-				for (auto dim : state_shape)
-					if (!dim || dim > NS_MAX_SHAPE_DIM)
-						return -EINVAL;
-				if (nd->iter > 0) {
-					/*
-					 * set input state by corresponding output state from prev
-					 * infer
-					 */
-					state_tensor =
-						nd->infer_request[ch].get_tensor(out_state_name);
-				} else {
-					state_tensor = ov::Tensor(ov::element::f32, state_shape);
-					std::memset(state_tensor.data<float>(), 0,
-						    state_tensor.get_byte_size());
-				}
-				nd->infer_request[ch].set_tensor(inp_state_name, state_tensor);
-			}
-			nd->infer_request[ch].infer();
-
-			/* process output */
-			float* src = nd->infer_request[ch].get_tensor("output").data<float>();
-			float* dst = &out_wave_fp32[0];
-			std::memcpy(dst, src, frame_count * sizeof(float));
-
-			/* convert back to int and write back to output buffer */
-			int16_t *out = output_data + ch;
-			for (size_t i = 0; i < frame_count; i++) {
-				float v = std::clamp(out_wave_fp32[i], -1.0f, +1.0f);
-
-				*out = static_cast<int16_t>(v * std::numeric_limits<int16_t>::max());
-
-				out = static_cast<int16_t *>(
-					cir_buf_wrap(out + NS_MAX_SOURCE_CHANNELS,
-						     sink->buf_start,
-						     sink->buf_end));
-			}
-		}
-
-		nd->iter++;
-
-		/* return frame_count so the input and output buffers can be updated accordingly */
-		return frame_count;
-	}
-} /* extern "C" */
-
diff --git a/tools/plugin/modules/ov_noise_suppression/noise_suppression_interface.h b/tools/plugin/modules/ov_noise_suppression/noise_suppression_interface.h
deleted file mode 100644
index e4fea272d0ca..000000000000
--- a/tools/plugin/modules/ov_noise_suppression/noise_suppression_interface.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- *
- * Copyright(c) 2024 Intel Corporation. All rights reserved.
- *
- * Author: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
- *
- */
-
-#ifndef _NOISE_SUPPRESSION_INTERFACE_H
-#define _NOISE_SUPPRESSION_INTERFACE_H
-
-#include <stddef.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-	struct cir_buf_source;
-	struct cir_buf_sink;
-	typedef void *ns_handle;
-	int ov_ns_init(ns_handle *handle);
-	void ov_ns_free(ns_handle handle);
-	int ov_ns_process(ns_handle handle,
-			  struct cir_buf_source *source,
-			  struct cir_buf_sink *sink,
-			  size_t frame_count);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*_NOISE_SUPPRESSION_INTERFACE_H */
diff --git a/tools/plugin/modules/ov_noise_suppression/test_ns_shape_validation.cpp b/tools/plugin/modules/ov_noise_suppression/test_ns_shape_validation.cpp
deleted file mode 100644
index 35a224581423..000000000000
--- a/tools/plugin/modules/ov_noise_suppression/test_ns_shape_validation.cpp
+++ /dev/null
@@ -1,149 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-//
-// Copyright(c) 2026 Intel Corporation. All rights reserved.
-//
-// Author: Pally Mediratta <mediratta01.pally@gmail.com>
-
-#include <cstdio>
-#include <cstdlib>
-#include <fstream>
-#include <string>
-#include <vector>
-#include <unistd.h>
-
-#include "noise_suppression_interface.h"
-
-static void usage(const char *prog)
-{
-	std::printf(
-"Usage: %s [--model PATH | --dim N [--dim N ...]] [--expect ok|reject]\n"
-"\n"
-"Regression test for the OpenVINO noise-suppression plugin's input-shape\n"
-"validation (commit \"tools: plugin: ov_noise_suppression: validate model\n"
-"input shape dimensions\"). Invokes ov_ns_init() against either:\n"
-"\n"
-"  --model PATH          a caller-supplied OpenVINO model XML file, or\n"
-"  --dim N [--dim N ...] a minimal synthesized model XML built from the\n"
-"                        given input port dimensions and written to a\n"
-"                        temporary file.\n"
-"\n"
-"  --expect ok|reject    expected outcome (default: reject).\n"
-"                        \"ok\":     ov_ns_init() must return 0.\n"
-"                        \"reject\": ov_ns_init() must return non-zero.\n"
-"\n"
-"Returns 0 on PASS, 1 on FAIL, 2 on usage error.\n"
-"\n"
-"Examples:\n"
-"  %s --dim 0 --dim 480                          # zero dim,  expect reject\n"
-"  %s --dim 9223372036854775807 --dim 1024       # overflow,  expect reject\n"
-"  %s --model real_model.xml --expect ok         # real model, expect accept\n",
-		prog, prog, prog, prog);
-}
-
-static int write_mock_model(const std::string &path,
-			    const std::vector<long long> &dims)
-{
-	std::ofstream f(path);
-	if (!f)
-		return -1;
-
-	f << "<?xml version=\"1.0\"?><net><layers>"
-	     "<layer id=\"0\" name=\"input\" type=\"Parameter\">"
-	     "<output><port id=\"0\" precision=\"FP32\">";
-	for (auto d : dims)
-		f << "<dim>" << d << "</dim>";
-	f << "</port></output></layer></layers></net>";
-	return f ? 0 : -1;
-}
-
-int main(int argc, char **argv)
-{
-	std::string model_path;
-	std::vector<long long> dims;
-	bool expect_reject = true;
-
-	for (int i = 1; i < argc; i++) {
-		std::string a = argv[i];
-		if (a == "-h" || a == "--help") {
-			usage(argv[0]);
-			return 0;
-		}
-		if (a == "--model" && i + 1 < argc) {
-			model_path = argv[++i];
-		} else if (a == "--dim" && i + 1 < argc) {
-			dims.push_back(std::strtoll(argv[++i], nullptr, 0));
-		} else if (a == "--expect" && i + 1 < argc) {
-			std::string v = argv[++i];
-			if (v == "ok") {
-				expect_reject = false;
-			} else if (v == "reject") {
-				expect_reject = true;
-			} else {
-				std::fprintf(stderr,
-					     "unknown --expect value: %s\n",
-					     v.c_str());
-				usage(argv[0]);
-				return 2;
-			}
-		} else {
-			std::fprintf(stderr, "unknown or incomplete arg: %s\n",
-				     a.c_str());
-			usage(argv[0]);
-			return 2;
-		}
-	}
-
-	std::string scratch;
-	if (model_path.empty()) {
-		if (dims.empty()) {
-			std::fprintf(stderr,
-				     "must supply --model PATH or one or more --dim N\n");
-			usage(argv[0]);
-			return 2;
-		}
-
-		char tmpl[] = "/tmp/ns_shape_test_XXXXXX.xml";
-		int fd = mkstemps(tmpl, 4);
-		if (fd < 0) {
-			std::perror("mkstemps");
-			return 2;
-		}
-		close(fd);
-		scratch = tmpl;
-		if (write_mock_model(scratch, dims) != 0) {
-			std::fprintf(stderr, "failed to write mock model %s\n",
-				     scratch.c_str());
-			std::remove(scratch.c_str());
-			return 2;
-		}
-		model_path = scratch;
-	}
-
-	struct noise_suppression_data *nd =
-		(struct noise_suppression_data *)std::calloc(1, sizeof(*nd));
-	if (!nd) {
-		std::perror("calloc");
-		if (!scratch.empty())
-			std::remove(scratch.c_str());
-		return 2;
-	}
-
-	int ret = ov_ns_init(nd, model_path.c_str());
-
-	if (!scratch.empty())
-		std::remove(scratch.c_str());
-
-	bool rejected = (ret != 0);
-	bool pass = (rejected == expect_reject);
-
-	std::printf("%s: ov_ns_init() returned %d (%s), expected %s\n",
-		    pass ? "PASS" : "FAIL",
-		    ret,
-		    rejected ? "rejected" : "accepted",
-		    expect_reject ? "reject" : "ok");
-
-	ov_ns_free(nd);
-	std::free(nd);
-
-	return pass ? 0 : 1;
-}
diff --git a/tools/plugin/modules/shm.c b/tools/plugin/modules/shm.c
deleted file mode 100644
index 0ddf297adcd1..000000000000
--- a/tools/plugin/modules/shm.c
+++ /dev/null
@@ -1,445 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-//
-// Copyright(c) 2022 Intel Corporation. All rights reserved.
-
-/* shm component for reading/writing pcm samples to/from a shm */
-
-#include <stdio.h>
-#include <stdint.h>
-#include <stddef.h>
-#include <stdlib.h>
-#include <errno.h>
-#include <inttypes.h>
-#include <sys/types.h>
-#include <sys/stat.h>
-#include <sys/mman.h>
-#include <fcntl.h>
-#include <semaphore.h>
-
-#include <rtos/sof.h>
-#include <sof/list.h>
-#include <sof/audio/stream.h>
-#include <sof/audio/ipc-config.h>
-#include <sof/ipc/driver.h>
-#include <sof/audio/component.h>
-#include <sof/audio/format.h>
-#include <sof/audio/pipeline.h>
-#include <ipc/stream.h>
-#include <ipc/topology.h>
-
-#include "pipe.h"
-
-SOF_DEFINE_REG_UUID(shmread);
-DECLARE_TR_CTX(shmread_tr, SOF_UUID(shmread_uuid), LOG_LEVEL_INFO);
-
-SOF_DEFINE_REG_UUID(shmwrite);
-DECLARE_TR_CTX(shmwrite_tr, SOF_UUID(shmwrite_uuid), LOG_LEVEL_INFO);
-
-static const struct comp_driver comp_shmread;
-static const struct comp_driver comp_shmwrite;
-
-/* shm comp data */
-struct shm_comp_data {
-	/* PCM data */
-	struct plug_shm_desc pcm;
-	struct plug_shm_endpoint *ctx;
-#if CONFIG_IPC_MAJOR_4
-	struct ipc4_base_module_cfg base_cfg;
-#endif
-};
-
-static int shm_process_new(struct comp_dev *dev,
-			   const struct comp_ipc_config *config,
-			   const void *spec)
-{
-	struct shm_comp_data *cd = comp_get_drvdata(dev);
-	struct plug_shm_endpoint *ctx;
-	int ret;
-
-	comp_dbg(dev, "shm new()");
-
-	/* FIXME: use PCM ID to create shm */
-	ret = plug_shm_init(&cd->pcm, _sp->topology_name, "pcm", 1);
-	if (ret < 0)
-		return ret;
-
-	// TODO: get the shm size for the buffer using a better method
-	cd->pcm.size = 128 * 1024;
-
-	/* mmap the SHM PCM */
-	ret = plug_shm_create(&cd->pcm);
-	if (ret < 0)
-		return ret;
-
-	cd->ctx = cd->pcm.addr;
-	ctx = cd->ctx;
-	ctx->buffer_size = cd->pcm.size;
-	memset(ctx, 0, sizeof(*ctx));
-	ctx->comp_id = config->id;
-	ctx->pipeline_id = config->pipeline_id;
-	ctx->state = SOF_PLUGIN_STATE_INIT;
-	dev->state = COMP_STATE_READY;
-
-	return 0;
-}
-
-static void shm_free(struct comp_dev *dev)
-{
-	struct shm_comp_data *cd = comp_get_drvdata(dev);
-
-	cd->ctx = NULL;
-
-	plug_shm_free(&cd->pcm);
-	shm_unlink(cd->pcm.name);
-
-	free(cd);
-	free(dev);
-}
-
-static struct comp_dev *shm_new(const struct comp_driver *drv,
-				const struct comp_ipc_config *config,
-				const void *spec, int direction)
-{
-	struct comp_dev *dev;
-#if CONFIG_IPC_MAJOR_4
-	const struct ipc4_base_module_cfg *base_cfg = (struct ipc4_base_module_cfg *)spec;
-#endif
-	struct shm_comp_data *cd;
-	int err;
-
-	dev = comp_alloc(drv, sizeof(*dev));
-	if (!dev)
-		return NULL;
-	dev->ipc_config = *config;
-
-	/* allocate  memory for shm comp data */
-	cd = rzalloc(SOF_MEM_FLAG_USER, sizeof(*cd));
-	if (!cd)
-		goto error;
-
-	comp_set_drvdata(dev, cd);
-	memcpy(&cd->base_cfg, base_cfg, sizeof(struct ipc4_base_module_cfg));
-
-	dev->direction = direction;
-	err = shm_process_new(dev, config, spec);
-	if (err < 0) {
-		free(cd);
-		free(dev);
-		return NULL;
-	}
-	dev->direction_set = true;
-
-	dev->state = COMP_STATE_READY;
-	return dev;
-
-error:
-	free(dev);
-	return NULL;
-}
-
-static struct comp_dev *shmwrite_new(const struct comp_driver *drv,
-				     const struct comp_ipc_config *config,
-				     const void *spec)
-{
-	return shm_new(drv, config, spec, SOF_IPC_STREAM_PLAYBACK);
-}
-
-static struct comp_dev *shmread_new(const struct comp_driver *drv,
-				    const struct comp_ipc_config *config,
-				    const void *spec)
-{
-	return shm_new(drv, config, spec, SOF_IPC_STREAM_CAPTURE);
-}
-
-/**
- * \brief Sets shm component audio stream parameters.
- * \param[in,out] dev Volume base component device.
- * \param[in] params Audio (PCM) stream parameters (ignored for this component)
- * \return Error code.
- *
- * All done in prepare() since we need to know source and sink component params.
- */
-static int shmread_params(struct comp_dev *dev, struct sof_ipc_stream_params *params)
-{
-	struct shm_comp_data *cd = comp_get_drvdata(dev);
-	struct plug_shm_endpoint *ctx = cd->ctx;
-	int ret;
-
-#if CONFIG_IPC_MAJOR_4
-	ipc4_base_module_cfg_to_stream_params(&cd->base_cfg, params);
-#endif
-
-	comp_err(dev, "forme_fmt %d channels %d", params->frame_fmt, params->channels);
-
-	ret = comp_verify_params(dev, 0, params);
-	if (ret < 0) {
-		comp_err(dev, "shm_params(): pcm params verification failed.");
-		return ret;
-	}
-	ctx->state = SOF_PLUGIN_STATE_READY;
-
-	return 0;
-}
-
-static int shmwrite_params(struct comp_dev *dev, struct sof_ipc_stream_params *params)
-{
-	struct shm_comp_data *cd = comp_get_drvdata(dev);
-	struct plug_shm_endpoint *ctx = cd->ctx;
-	int ret;
-
-	ret = comp_verify_params(dev, 0, params);
-	if (ret < 0) {
-		comp_err(dev, "shm_params(): pcm params verification failed.");
-		return ret;
-	}
-	ctx->state = SOF_PLUGIN_STATE_READY;
-
-	return 0;
-}
-
-static int shm_trigger(struct comp_dev *dev, int cmd)
-{
-	struct shm_comp_data *cd = comp_get_drvdata(dev);
-	struct plug_shm_endpoint *ctx = cd->ctx;
-
-	comp_dbg(dev, "shm_trigger(%d)", cmd);
-
-	switch (cmd) {
-	case COMP_TRIGGER_START:
-	case COMP_TRIGGER_RELEASE:
-		ctx->state = SOF_PLUGIN_STATE_STREAM_RUNNING;
-		break;
-	case COMP_TRIGGER_STOP:
-	case COMP_TRIGGER_PAUSE:
-		ctx->state = SOF_PLUGIN_STATE_READY;
-		break;
-	case COMP_TRIGGER_RESET:
-		ctx->state = SOF_PLUGIN_STATE_INIT;
-		break;
-	case COMP_TRIGGER_XRUN:
-		ctx->state = SOF_PLUGIN_STATE_STREAM_ERROR;
-		break;
-	default:
-		break;
-	}
-
-	return comp_set_state(dev, cmd);
-}
-
-static int shm_cmd(struct comp_dev *dev, int cmd, void *data, int max_data_size)
-{
-	return 0;
-}
-
-/*
- * copy from local SOF buffer to remote SHM buffer
- */
-static int shmread_copy(struct comp_dev *dev)
-{
-	struct shm_comp_data *cd = comp_get_drvdata(dev);
-	struct plug_shm_endpoint *ctx = cd->ctx;
-	struct comp_buffer *buffer;
-	struct audio_stream *source;
-	unsigned int copy_bytes;
-	unsigned int remaining;
-	unsigned int total = 0;
-	void *rptr;
-	void *dest;
-
-	/* local SOF source buffer */
-	buffer = comp_dev_get_first_data_producer(dev);
-	source = &buffer->stream;
-	rptr = source->r_ptr;
-
-	/* remote SHM sink buffer */
-	dest = plug_ep_wptr(ctx);
-
-	/* maximum byte count that can be copied this iteration */
-	remaining = MIN(audio_stream_get_avail_bytes(source), plug_ep_get_free(ctx));
-
-	while (remaining) {
-		/* min bytes from source pipe */
-		copy_bytes = MIN(remaining, plug_ep_wrap_wsize(ctx));
-
-		/* min bytes from source and sink */
-		copy_bytes = MIN(copy_bytes, audio_stream_bytes_without_wrap(source, rptr));
-
-		/* anything to copy ? */
-		if (copy_bytes == 0)
-			break;
-
-		/* copy to local buffer from SHM buffer */
-		memcpy(dest, rptr, copy_bytes);
-
-		/* update SHM pointer with wrap */
-		dest = plug_ep_produce(ctx, copy_bytes);
-
-		/* update local pointers */
-		rptr = audio_stream_wrap(source, rptr + copy_bytes);
-
-		/* update avail and totals */
-		remaining -= copy_bytes;
-		total += copy_bytes;
-	}
-
-	/* update sink buffer pointers */
-	comp_update_buffer_consume(buffer, total);
-	comp_dbg(dev, "wrote %d bytes", total);
-
-	return 0;
-}
-
-/*
- * copy to local SOF buffer from remote SHM buffer
- */
-static int shmwrite_copy(struct comp_dev *dev)
-{
-	struct shm_comp_data *cd = comp_get_drvdata(dev);
-	struct plug_shm_endpoint *ctx = cd->ctx;
-	struct comp_buffer *buffer;
-	struct audio_stream *sink;
-	unsigned int copy_bytes;
-	unsigned int remaining;
-	unsigned int total = 0;
-	void *wptr;
-	void *src;
-
-	/* local SOF sink buffer */
-	buffer = comp_dev_get_first_data_consumer(dev);
-	sink = &buffer->stream;
-	wptr = sink->w_ptr;
-
-	/* remote SHM source buffer */
-	src = plug_ep_rptr(ctx);
-
-	/* maximum byte count that can be copied this iteration */
-	remaining = MIN(audio_stream_get_free_bytes(sink), plug_ep_get_avail(ctx));
-
-	while (remaining > 0) {
-		/* min bytes free bytes in local sink */
-		copy_bytes = MIN(remaining, plug_ep_wrap_rsize(ctx));
-
-		/* min bytes to wrap */
-		copy_bytes = MIN(copy_bytes, audio_stream_bytes_without_wrap(sink, wptr));
-
-		/* nothing to copy ? */
-		if (copy_bytes == 0)
-			break;
-
-		/* copy to SHM from local buffer */
-		memcpy(wptr, src, copy_bytes);
-
-		/* update local pointers */
-		wptr = audio_stream_wrap(sink, wptr + copy_bytes);
-
-		/* update SHM pointer with wrap */
-		src = plug_ep_consume(ctx, copy_bytes);
-
-		/* update avail and totals */
-		remaining -= copy_bytes;
-		total += copy_bytes;
-	}
-
-	/* update sink buffer pointers */
-	comp_update_buffer_produce(buffer, total);
-	comp_dbg(dev, "read %d bytes", total);
-
-	return 0;
-}
-
-static int shm_prepare(struct comp_dev *dev)
-{
-	struct shm_comp_data *cd = comp_get_drvdata(dev);
-	struct plug_shm_endpoint *ctx = cd->ctx;
-	int ret = 0;
-
-	comp_dbg(dev, "shm prepare_copy()");
-
-	ret = comp_set_state(dev, COMP_TRIGGER_PREPARE);
-	if (ret < 0)
-		return ret;
-
-	ctx->state = SOF_PLUGIN_STATE_READY;
-
-	if (ret == COMP_STATUS_STATE_ALREADY_SET)
-		return PPL_STATUS_PATH_STOP;
-
-	return ret;
-}
-
-static int shm_reset(struct comp_dev *dev)
-{
-	struct shm_comp_data *cd = comp_get_drvdata(dev);
-	struct plug_shm_endpoint *ctx = cd->ctx;
-
-	comp_set_state(dev, COMP_TRIGGER_RESET);
-	ctx->state = SOF_PLUGIN_STATE_INIT;
-
-	return 0;
-}
-
-int shm_get_attribute(struct comp_dev *dev, uint32_t type, void *value)
-{
-	struct shm_comp_data *cd = comp_get_drvdata(dev);
-
-	switch (type) {
-	case COMP_ATTR_BASE_CONFIG:
-		memcpy_s(value, sizeof(struct ipc4_base_module_cfg),
-			 &cd->base_cfg, sizeof(struct ipc4_base_module_cfg));
-		break;
-	default:
-		return -EINVAL;
-	}
-
-	return 0;
-}
-
-static const struct comp_driver comp_shmread = {
-	.type = SOF_COMP_HOST,
-	.uid = SOF_RT_UUID(shmread_uuid),
-	.tctx	= &shmread_tr,
-	.ops = {
-		.create = shmread_new,
-		.free = shm_free,
-		.params = shmread_params,
-		.cmd = shm_cmd,
-		.trigger = shm_trigger,
-		.copy = shmread_copy,
-		.prepare = shm_prepare,
-		.reset = shm_reset,
-		.get_attribute = shm_get_attribute,
-	},
-};
-
-static const struct comp_driver comp_shmwrite = {
-	.type = SOF_COMP_HOST,
-	.uid = SOF_RT_UUID(shmwrite_uuid),
-	.tctx	= &shmwrite_tr,
-	.ops = {
-		.create = shmwrite_new,
-		.free = shm_free,
-		.params = shmwrite_params,
-		.cmd = shm_cmd,
-		.trigger = shm_trigger,
-		.copy = shmwrite_copy,
-		.prepare = shm_prepare,
-		.reset = shm_reset,
-		.get_attribute = shm_get_attribute,
-	},
-};
-
-static struct comp_driver_info comp_shmread_info = {
-	.drv = &comp_shmread,
-};
-
-static struct comp_driver_info comp_shmwrite_info = {
-	.drv = &comp_shmwrite,
-};
-
-static void sys_comp_shm_init(void)
-{
-	comp_register(&comp_shmread_info);
-	comp_register(&comp_shmwrite_info);
-}
-
-DECLARE_MODULE(sys_comp_shm_init);
diff --git a/tools/plugin/pipe/CMakeLists.txt b/tools/plugin/pipe/CMakeLists.txt
deleted file mode 100644
index 244fb3199e38..000000000000
--- a/tools/plugin/pipe/CMakeLists.txt
+++ /dev/null
@@ -1,26 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-
-add_executable(sof-pipe
-	main.c
-	cpu.c
-	pipeline.c
-	ipc4.c
-	../common.c
-)
-
-sof_append_relative_path_definitions(sof-pipe)
-
-target_include_directories(sof-pipe PRIVATE
-	${CMAKE_CURRENT_SOURCE_DIR}
-	${CMAKE_CURRENT_SOURCE_DIR}/..
-	${sof_source_directory}/src/audio)
-
-target_compile_options(sof-pipe PRIVATE -DPIC -g -O3 -Wall -Werror -Wno-stringop-truncation -DCONFIG_LIBRARY -imacros${config_h})
-
-target_include_directories(sof-pipe PRIVATE ${sof_install_directory}/include)
-target_include_directories(sof-pipe PRIVATE ${parser_install_dir}/include)
-
-target_link_libraries(sof-pipe PRIVATE -Wl,-whole-archive sof_library -Wl,-no-whole-archive)
-target_link_libraries(sof-pipe PRIVATE sof_parser_lib)
-target_link_libraries(sof-pipe PRIVATE pthread)
-target_link_libraries(sof-pipe PRIVATE  -rdynamic -lasound -ldl -lm -lasound -lrt)
diff --git a/tools/plugin/pipe/cpu.c b/tools/plugin/pipe/cpu.c
deleted file mode 100644
index ea7e5d0645e2..000000000000
--- a/tools/plugin/pipe/cpu.c
+++ /dev/null
@@ -1,186 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-//
-// Copyright(c) 2022 Intel Corporation. All rights reserved.
-//
-// Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
-
-/*
- * SOF pipeline in userspace.
- */
-
-#define _GNU_SOURCE
-
-#include <stdio.h>
-#include <sys/poll.h>
-#include <string.h>
-#include <sys/types.h>
-#include <unistd.h>
-#include <stdlib.h>
-#include <sys/wait.h>
-#include <sys/stat.h>
-#include <fcntl.h>
-#include <sys/mman.h>
-#include <assert.h>
-#include <errno.h>
-#include <pthread.h>
-#include <limits.h>
-#include <dlfcn.h>
-
-#include "common.h"
-#include "pipe.h"
-
-/* read the CPU ID register data on x86 */
-static inline void x86_cpuid(unsigned int *eax, unsigned int *ebx,
-			     unsigned int *ecx, unsigned int *edx)
-{
-	/* data type is passed in on eax (and sometimes ecx) */
-	asm volatile("cpuid"
-		     : "=a" (*eax), "=b" (*ebx), "=c" (*ecx), "=d" (*edx)
-		     : "0" (*eax), "2" (*ecx));
-}
-
-/*
- * Check core type for E cores. If non hybrid then it does not matter.
- */
-static inline int use_this_core(struct sof_pipe *sp)
-{
-	/* CPUID - set eax to 0x1a for hybrid core types */
-	unsigned int eax = 0x1a, ebx = 0, ecx = 0, edx = 0;
-	char core_mask;
-
-	/* get the processor core type we are running on now */
-	x86_cpuid(&eax, &ebx, &ecx, &edx);
-
-	/* core type 0x20 is atom, 0x40 is core */
-	core_mask = (eax >> 24) & 0xFF;
-	switch (core_mask) {
-	case 0x20:
-		fprintf(sp->log, "found E core\n");
-		if (sp->use_E_core)
-			return 1;
-		return 0;
-	case 0x40:
-		fprintf(sp->log, "found P core\n");
-		if (sp->use_P_core)
-			return 1;
-		return 0;
-	default:
-		/* non hybrid arch, just use first core */
-		fprintf(sp->log, "found non hybrid core topology\n");
-		return 1;
-	}
-}
-
-/* sof-pipe needs to be sticky to the current core for low latency */
-int pipe_set_affinity(struct sof_pipe *sp)
-{
-	cpu_set_t cpuset;
-	pthread_t thread;
-	long core_count = sysconf(_SC_NPROCESSORS_ONLN);
-	int i;
-	int err;
-
-	/* Set affinity mask to  core */
-	thread = pthread_self();
-	CPU_ZERO(&cpuset);
-
-	/* find the first E core (usually come after the P cores ?) */
-	for (i = core_count - 1; i >= 0; i--) {
-		CPU_ZERO(&cpuset);
-		CPU_SET(i, &cpuset);
-
-		/* change our core to i */
-		err = pthread_setaffinity_np(thread, sizeof(cpuset), &cpuset);
-		if (err != 0) {
-			fprintf(sp->log, "error: failed to set CPU affinity to core %d: %s\n",
-				i, strerror(err));
-			return err;
-		}
-
-		/* should we use this core ? */
-		if (use_this_core(sp))
-			break;
-	}
-
-	return 0;
-}
-
-/* set ipc thread to low priority */
-int pipe_set_ipc_lowpri(struct sof_pipe *sp)
-{
-	pthread_attr_t attr;
-	struct sched_param param;
-	int err;
-
-	/* attempt to set thread priority - needs suid */
-	fprintf(sp->log, "pipe: set IPC low priority\n");
-
-	err = pthread_attr_init(&attr);
-	if (err < 0) {
-		fprintf(sp->log, "error: can't create thread attr %d %s\n", err, strerror(errno));
-		return err;
-	}
-
-	err = pthread_attr_setschedpolicy(&attr, SCHED_OTHER);
-	if (err < 0) {
-		fprintf(sp->log, "error: can't set thread policy %d %s\n", err, strerror(errno));
-		return err;
-	}
-	param.sched_priority = 0;
-	err = pthread_attr_setschedparam(&attr, &param);
-	if (err < 0) {
-		fprintf(sp->log, "error: can't set thread sched param %d %s\n",
-			err, strerror(errno));
-		return err;
-	}
-
-	return 0;
-}
-
-/* set pipeline to realtime priority */
-int pipe_set_rt(struct sof_pipe *sp)
-{
-	pthread_attr_t attr;
-	struct sched_param param;
-	int err;
-	uid_t uid = getuid();
-	uid_t euid = geteuid();
-
-	/* do we have elevated privileges to attempt RT priority */
-	if (uid < 0 || uid != euid) {
-		/* attempt to set thread priority - needs suid */
-		fprintf(sp->log, "pipe: set RT priority\n");
-
-		err = pthread_attr_init(&attr);
-		if (err < 0) {
-			fprintf(sp->log, "error: can't create thread attr %d %s\n",
-				err, strerror(errno));
-			return err;
-		}
-
-		err = pthread_attr_setschedpolicy(&attr, SCHED_FIFO);
-		if (err < 0) {
-			fprintf(sp->log, "error: can't set thread policy %d %s\n",
-				err, strerror(errno));
-			return err;
-		}
-		param.sched_priority = 80;
-		err = pthread_attr_setschedparam(&attr, &param);
-		if (err < 0) {
-			fprintf(sp->log, "error: can't set thread sched param %d %s\n",
-				err, strerror(errno));
-			return err;
-		}
-		err = pthread_attr_setinheritsched(&attr, PTHREAD_EXPLICIT_SCHED);
-		if (err < 0) {
-			fprintf(sp->log, "error: can't set thread inherit %d %s\n",
-				err, strerror(errno));
-			return err;
-		}
-	} else {
-		fprintf(sp->log, "error: no elevated privileges for RT. uid %d euid %d\n",
-			uid, euid);
-	}
-
-	return 0;
-}
diff --git a/tools/plugin/pipe/ipc4.c b/tools/plugin/pipe/ipc4.c
deleted file mode 100644
index 90157971d05e..000000000000
--- a/tools/plugin/pipe/ipc4.c
+++ /dev/null
@@ -1,426 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-//
-// Copyright(c) 2022 Intel Corporation. All rights reserved.
-//
-// Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
-
-/*
- * SOF pipeline in userspace.
- */
-
-#define _GNU_SOURCE
-
-#include <stdio.h>
-#include <sys/poll.h>
-#include <string.h>
-#include <sys/types.h>
-#include <sys/socket.h>
-#include <unistd.h>
-#include <stdlib.h>
-#include <sys/wait.h>
-#include <sys/stat.h>
-#include <signal.h>
-#include <fcntl.h>
-#include <sys/mman.h>
-#include <semaphore.h>
-#include <assert.h>
-#include <errno.h>
-#include <pthread.h>
-#include <limits.h>
-#include <getopt.h>
-#include <dlfcn.h>
-
-#include <rtos/sof.h>
-#include <rtos/task.h>
-#include <sof/lib/notifier.h>
-#include <sof/ipc/driver.h>
-#include <sof/ipc/topology.h>
-#include <sof/lib/agent.h>
-#include <sof/lib/dai.h>
-#include <sof/lib/dma.h>
-#include <sof/schedule/edf_schedule.h>
-#include <sof/schedule/ll_schedule.h>
-#include <sof/schedule/ll_schedule_domain.h>
-#include <sof/schedule/schedule.h>
-#include <sof/audio/pipeline.h>
-#include <sof/audio/component.h>
-#include <sof/audio/component_ext.h>
-
-#include "common.h"
-#include "pipe.h"
-
-// TODO: take prefix from ALSA prefix
-#define COMP_PREFIX	"./sof_ep/install/lib/libsof_"
-#define COMP_SUFFIX	".so"
-#define UUID_STR_SIZE	32
-
-struct sof_pipe_module_library_map {
-	int module_id;
-	const char *name;
-};
-
-static const struct sof_pipe_module_library_map library_map[] = {
-	{0x6, "libsof_volume.so"},
-	{0x2, "libsof_mixer.so"},
-	{0x3, "libsof_mixer.so"},
-	{0x95, "libsof_ns.so"},
-	/*FIXME: hack for now to set up ALSA and SHM components */
-	{0x96, "libsof_mod_shm.so"}, /* host playback */
-	{0x97, "libsof_mod_alsa.so"}, /* dai playback */
-	{0x98, "libsof_mod_shm.so"}, /* host capture */
-	{0x99, "libsof_mod_alsa.so"}, /* dai capture */
-};
-
-static int pipe_register_comp(struct sof_pipe *sp, uint16_t module_id)
-{
-	const struct sof_pipe_module_library_map *lib;
-	int i;
-
-	/* check if module already loaded */
-	for (i = 0; i < sp->mod_idx; i++) {
-		if (sp->module[i].module_id == module_id)
-			return 0; /* module found and already loaded */
-	}
-
-	for (i = 0; i < ARRAY_SIZE(library_map); i++) {
-		lib = &library_map[i];
-
-		if (module_id == lib->module_id)
-			break;
-	}
-
-	if (i == ARRAY_SIZE(library_map)) {
-		fprintf(stderr, "module ID: %d not supported\n", module_id);
-		return -ENOTSUP;
-	}
-
-	/* not loaded, so load module */
-	sp->module[sp->mod_idx].handle = dlopen(lib->name, RTLD_NOW);
-	if (!sp->module[sp->mod_idx].handle) {
-		fprintf(stderr, "error: cant load module %s: %s\n",
-			lib->name, dlerror());
-		return -errno;
-	}
-
-	sp->mod_idx++;
-
-	return 0;
-}
-
-#define iCS(x) ((x) & SOF_CMD_TYPE_MASK)
-#define iGS(x) ((x) & SOF_GLB_TYPE_MASK)
-
-static int pipe_sof_ipc_cmd_before(struct sof_pipe *sp, void *mailbox, size_t bytes)
-{
-	struct ipc4_message_request *in = mailbox;
-	enum ipc4_message_target target = in->primary.r.msg_tgt;
-	int ret = 0;
-
-	switch (target) {
-	case SOF_IPC4_MESSAGE_TARGET_MODULE_MSG:
-	{
-		uint32_t type = in->primary.r.type;
-
-		switch (type) {
-		case SOF_IPC4_MOD_INIT_INSTANCE:
-		{
-			struct ipc4_module_init_instance *module_init =
-				(struct ipc4_module_init_instance *)in;
-
-			ret = pipe_register_comp(sp, module_init->primary.r.module_id);
-			break;
-		}
-		default:
-			break;
-		}
-		break;
-	}
-	case SOF_IPC4_MESSAGE_TARGET_FW_GEN_MSG:
-	{
-		uint32_t type = in->primary.r.type;
-
-		switch (type) {
-		case SOF_IPC4_GLB_SET_PIPELINE_STATE:
-		{
-			struct ipc4_pipeline_set_state *state;
-			struct ipc_comp_dev *ipc_pipe;
-			struct ipc *ipc = ipc_get();
-			unsigned int pipeline_id;
-
-			state = (struct ipc4_pipeline_set_state *)in;
-			pipeline_id = (unsigned int)state->primary.r.ppl_id;
-
-			if (state->primary.r.ppl_state == SOF_IPC4_PIPELINE_STATE_PAUSED) {
-				ipc_pipe = ipc_get_pipeline_by_id(ipc, pipeline_id);
-				if (!ipc_pipe) {
-					fprintf(stderr, "No pipeline with instance_id = %u",
-						pipeline_id);
-					return -EINVAL;
-				}
-
-				/* stop the pipeline thread */
-				ret = pipe_thread_stop(sp, ipc_pipe->pipeline);
-				if (ret < 0) {
-					printf("error: can't start pipeline %d thread\n",
-					       ipc_pipe->pipeline->comp_id);
-					return ret;
-				}
-			}
-			break;
-		}
-		default:
-			break;
-		}
-		break;
-	}
-	default:
-		fprintf(sp->log, "ipc: unknown command target %u size %ld",
-			target, bytes);
-		ret = -EINVAL;
-		break;
-	}
-
-	return ret;
-}
-
-static int pipe_sof_ipc_cmd_after(struct sof_pipe *sp, void *mailbox, size_t bytes)
-{
-	struct ipc4_message_request *in = mailbox;
-	enum ipc4_message_target target = in->primary.r.msg_tgt;
-	int ret = 0;
-
-	switch (target) {
-	case SOF_IPC4_MESSAGE_TARGET_MODULE_MSG:
-		break;
-	case SOF_IPC4_MESSAGE_TARGET_FW_GEN_MSG:
-	{
-		uint32_t type = in->primary.r.type;
-
-		switch (type) {
-		case SOF_IPC4_GLB_CREATE_PIPELINE:
-		{
-			struct ipc4_pipeline_create *pipe_desc = (struct ipc4_pipeline_create *)in;
-			struct ipc_comp_dev *ipc_pipe;
-			struct ipc *ipc = ipc_get();
-			unsigned int pipeline_id = (unsigned int)pipe_desc->primary.r.instance_id;
-
-			ipc_pipe = ipc_get_pipeline_by_id(ipc, pipeline_id);
-			if (!ipc_pipe) {
-				fprintf(stderr, "No pipeline with instance_id = %u\n",
-					pipeline_id);
-				return -EINVAL;
-			}
-
-			/* create new pipeline thread */
-			ret = pipe_thread_new(sp, ipc_pipe->pipeline);
-			if (ret < 0) {
-				printf("error: can't create pipeline %d thread\n",
-				       ipc_pipe->pipeline->pipeline_id);
-				return ret;
-			}
-			break;
-		}
-		case SOF_IPC4_GLB_SET_PIPELINE_STATE:
-		{
-			struct ipc4_pipeline_set_state *state;
-			struct ipc_comp_dev *ipc_pipe;
-			struct ipc *ipc = ipc_get();
-			unsigned int pipeline_id;
-
-			state = (struct ipc4_pipeline_set_state *)in;
-			pipeline_id = (unsigned int)state->primary.r.ppl_id;
-
-			if (state->primary.r.ppl_state == SOF_IPC4_PIPELINE_STATE_RUNNING) {
-				ipc_pipe = ipc_get_pipeline_by_id(ipc, pipeline_id);
-				if (!ipc_pipe) {
-					fprintf(stderr, "No pipeline with instance_id = %u\n",
-						pipeline_id);
-					return -EINVAL;
-				}
-
-				/* start the pipeline thread */
-				ret = pipe_thread_start(sp, ipc_pipe->pipeline);
-				if (ret < 0) {
-					printf("error: can't start pipeline %d thread\n",
-					       ipc_pipe->pipeline->comp_id);
-					return ret;
-				}
-			}
-			break;
-		}
-		case SOF_IPC4_GLB_DELETE_PIPELINE:
-		{
-			struct ipc4_pipeline_create *pipe_desc = (struct ipc4_pipeline_create *)in;
-			unsigned int pipeline_id = (unsigned int)pipe_desc->primary.r.instance_id;
-
-			/* free pipeline thread */
-			ret = pipe_thread_free(sp, pipeline_id);
-			if (ret < 0) {
-				printf("error: can't free pipeline %d thread\n",
-				       pipeline_id);
-				return ret;
-			}
-
-			break;
-		}
-		default:
-			break;
-		}
-		break;
-	}
-	default:
-		fprintf(sp->log, "ipc: unknown command target %u size %ld",
-			target, bytes);
-		ret = -EINVAL;
-		break;
-	}
-
-	return ret;
-}
-
-int pipe_ipc_do(struct sof_pipe *sp, void *mailbox, size_t bytes)
-{
-	char mailbox_copy[IPC3_MAX_MSG_SIZE] = {0};
-	int err = 0;
-
-	/* preserve mailbox contents for local "after" config */
-	memcpy(mailbox_copy, mailbox, bytes);
-
-	/* some IPCs require pipe to perform actions before core */
-	/* mailbox can be re-written here by local pipe if needed */
-	err = pipe_sof_ipc_cmd_before(sp, mailbox, bytes);
-	if (err < 0) {
-		fprintf(sp->log, "error: local IPC processing failed\n");
-		return err;
-	}
-
-	/* is the IPC local only or do we need send to infra ? */
-	err = pipe_ipc_message(sp, mailbox, bytes);
-	if (err < 0) {
-		fprintf(sp->log, "error: infra IPC processing failed\n");
-		return err;
-	}
-
-	/* some IPCs require pipe to perform actions before core */
-	err = pipe_sof_ipc_cmd_after(sp, mailbox_copy, bytes);
-	if (err < 0) {
-		fprintf(sp->log, "error: local IPC processing failed\n");
-		return err;
-	}
-
-	return err;
-}
-
-static void *handle_ipc_client(void *data)
-{
-	struct sof_pipe *sp = data;
-	struct plug_socket_desc *ipc_socket = &sp->ipc_socket;
-	struct timespec ts;
-	int client_id = sp->new_client_id;
-	int clientfd = sp->client_sock_ids[client_id];
-	char mailbox[IPC3_MAX_MSG_SIZE] = {0};
-	ssize_t ipc_size;
-	int err;
-
-	while (1) {
-		memset(mailbox, 0, IPC3_MAX_MSG_SIZE);
-
-		ipc_size = recv(clientfd, mailbox, IPC3_MAX_MSG_SIZE, 0);
-		if (ipc_size < 0) {
-			fprintf(sp->log, "error: can't read IPC socket %s : %s\n",
-				ipc_socket->path, strerror(errno));
-			break;
-		}
-
-		/* connection lost */
-		if (ipc_size == 0) {
-			close(clientfd);
-			break;
-		}
-
-		/* TODO: properly validate message and continue if garbage */
-		if (*((uint32_t *)mailbox) == 0) {
-			fprintf(sp->log, "sof-pipe: IPC %s garbage read\n", ipc_socket->path);
-			ts.tv_sec = 0;
-			ts.tv_nsec = 20 * 1000 * 1000; /* 20 ms */
-			nanosleep(&ts, NULL);
-			continue;
-		}
-
-		/* do the message work */
-		//data_dump(mailbox, IPC3_MAX_MSG_SIZE);
-		err = pipe_ipc_do(sp, mailbox, ipc_size);
-		if (err < 0)
-			fprintf(sp->log, "error: local IPC processing failed\n");
-
-		/* now return message completion status found in mailbox */
-		err = send(clientfd, mailbox, IPC3_MAX_MSG_SIZE, 0);
-		if (err < 0) {
-			close(clientfd);
-			break;
-		}
-	}
-
-	close(clientfd);
-	sp->client_sock_ids[client_id] = 0;
-	return NULL;
-}
-
-int pipe_ipc_process(struct sof_pipe *sp, struct plug_socket_desc *ipc_socket)
-{
-	pthread_t thread_id;
-	int err;
-
-	/* IPC thread should not preempt processing thread */
-	err = pipe_set_ipc_lowpri(sp);
-	if (err < 0)
-		fprintf(sp->log, "error: cant set PCM IPC thread to low priority");
-
-	/* create the IPC socket */
-	err = plug_socket_create(ipc_socket);
-	if (err < 0) {
-		fprintf(sp->log, "error: can't create TX IPC socket : %s\n",
-			strerror(errno));
-		return -errno;
-	}
-
-	/* let main() know we are ready */
-	fprintf(sp->log, "sof-pipe: IPC %s socket ready\n", ipc_socket->path);
-
-	/* main PCM IPC handling loop */
-	while (1) {
-		int clientfd, i;
-
-		/* Accept a connection from a client */
-		clientfd = accept(ipc_socket->socket_fd, NULL, NULL);
-		if (clientfd == -1) {
-			fprintf(sp->log, "IPC %s socket accept failed\n", ipc_socket->path);
-			return -errno;
-		}
-
-		for (i = 0; i < MAX_IPC_CLIENTS; i++) {
-			if (!sp->client_sock_ids[i]) {
-				sp->client_sock_ids[i] = clientfd;
-				sp->new_client_id = i;
-				break;
-			}
-		}
-
-		/* create a new thread for each new IPC client */
-		if (pthread_create(&thread_id, NULL, handle_ipc_client, sp) != 0) {
-			fprintf(sp->log, "Client IPC thread creation failed");
-			close(clientfd);
-			sp->client_sock_ids[i] = 0;
-			continue;
-		}
-
-		fprintf(sp->log, "Client IPC thread created client id %d\n", clientfd);
-		/* Detach the thread */
-		pthread_detach(thread_id);
-	}
-
-	close(ipc_socket->socket_fd);
-
-	fprintf(sp->log, "***sof-pipe: IPC %s thread finished !!\n", ipc_socket->path);
-	return 0;
-}
diff --git a/tools/plugin/pipe/main.c b/tools/plugin/pipe/main.c
deleted file mode 100644
index 68861fc0af2a..000000000000
--- a/tools/plugin/pipe/main.c
+++ /dev/null
@@ -1,345 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-//
-// Copyright(c) 2022 Intel Corporation. All rights reserved.
-//
-// Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
-
-/*
- * SOF pipeline in userspace.
- */
-
-#define _GNU_SOURCE
-
-#include <stdio.h>
-#include <sys/poll.h>
-#include <string.h>
-#include <sys/types.h>
-#include <unistd.h>
-#include <stdlib.h>
-#include <sys/wait.h>
-#include <sys/stat.h>
-#include <signal.h>
-#include <fcntl.h>
-#include <sys/mman.h>
-#include <semaphore.h>
-#include <assert.h>
-#include <errno.h>
-#include <pthread.h>
-#include <limits.h>
-#include <getopt.h>
-#include <dlfcn.h>
-
-#include "common.h"
-#include "pipe.h"
-
-#define VERSION		"v0.1"
-
-/* global needed for signal handler */
-struct sof_pipe *_sp;
-
-static void shutdown(struct sof_pipe *sp)
-{
-	struct pipethread_data *pipeline_ctx = sp->pipeline_ctx;
-	int i;
-
-	/* free everything */
-	munmap(sp->shm_context.addr, sp->shm_context.size);
-	shm_unlink(sp->shm_context.name);
-
-	/* cancel all threads, free locks and message queues */
-	for (i = 0; i < sp->pipe_thread_count; i++) {
-		struct pipethread_data *pd = &pipeline_ctx[i];
-
-		pthread_cancel(pd->ipc_thread);
-		pthread_cancel(pd->pcm_thread);
-		plug_lock_free(&pd->ready);
-		plug_lock_free(&pd->done);
-	}
-
-	/* free the sof-pipe IPC tx/rx message queues */
-	plug_socket_free(&sp->ipc_socket);
-
-	pthread_mutex_destroy(&sp->ipc_lock);
-
-	fflush(sp->log);
-	fflush(stdout);
-	fflush(stderr);
-}
-
-/* signals from the ALSA PCM plugin or something has gone wrong */
-static void signal_handler(int sig)
-{
-	switch (sig) {
-	case SIGTERM:
-		fprintf(_sp->log, "Pipe caught SIGTERM - shutdown\n");
-		break;
-	case SIGINT:
-		fprintf(_sp->log, "Pipe caught SIGINT - shutdown\n");
-		break;
-	default:
-		fprintf(_sp->log, "Pipe caught signal %d, something went wrong\n", sig);
-		break;
-	}
-	fprintf(_sp->log, "Pipe shutdown signal\n");
-
-	/* try and clean up if we can */
-	shutdown(_sp);
-	exit(EXIT_FAILURE);
-}
-
-static int pipe_init_signals(struct sof_pipe *sp)
-{
-	struct sigaction *action = &sp->action;
-	int err;
-
-	/*
-	 * signals - currently only check for SIGCHLD. TODO: handle more
-	 */
-	sigemptyset(&action->sa_mask);
-	action->sa_handler = signal_handler;
-	err = sigaction(SIGTERM, action, NULL);
-	if (err < 0) {
-		fprintf(sp->log, "failed to register signal action: %s",
-			strerror(errno));
-		return err;
-	}
-
-	err = sigaction(SIGSEGV, action, NULL);
-	if (err < 0) {
-		fprintf(sp->log, "failed to register signal action: %s",
-			strerror(errno));
-		return err;
-	}
-
-	err = sigaction(SIGINT, action, NULL);
-	if (err < 0) {
-		fprintf(sp->log, "failed to register signal action: %s",
-			strerror(errno));
-		return err;
-	}
-
-	return 0;
-}
-
-int pipe_ipc_message(struct sof_pipe *sp, void *mailbox, size_t bytes)
-{
-	struct ipc *ipc = ipc_get();
-
-	/* reply is copied back to mailbox */
-	pthread_mutex_lock(&sp->ipc_lock);
-	memcpy(ipc->comp_data, mailbox, bytes);
-	ipc_cmd(mailbox);
-	memcpy(mailbox, ipc->comp_data, bytes);
-	pthread_mutex_unlock(&sp->ipc_lock);
-
-	return 0;
-}
-
-/*
- * Create and open a new semaphore using the lock object.
- */
-int plug_lock_create(struct plug_sem_desc *lock)
-{
-	/* delete any old stale resources that use our resource name */
-	sem_unlink(lock->name);
-
-	/* RW blocking lock */
-	lock->sem = sem_open(lock->name, O_CREAT | O_RDWR | O_EXCL, SEM_PERMS, 0);
-	if (lock->sem == SEM_FAILED) {
-		SNDERR("failed to create semaphore %s: %s", lock->name, strerror(errno));
-		return -errno;
-	}
-
-	return 0;
-}
-
-/*
- * Free and delete semaphore resourses in lock object.
- */
-void plug_lock_free(struct plug_sem_desc *lock)
-{
-	sem_close(lock->sem);
-	sem_unlink(lock->name);
-}
-
-/*
- * Create and open a new shared memory region using the SHM object.
- */
-int plug_shm_create(struct plug_shm_desc *shm)
-{
-	int err;
-
-	/* delete any old stale resources that use our resource name */
-	shm_unlink(shm->name);
-
-	/* open SHM to be used for low latency position */
-	shm->fd = shm_open(shm->name, O_RDWR | O_CREAT, S_IRWXU | S_IRWXG);
-	if (shm->fd < 0) {
-		SNDERR("failed to create SHM position %s: %s", shm->name, strerror(errno));
-		return -errno;
-	}
-
-	/* set SHM size */
-	err = ftruncate(shm->fd, shm->size);
-	if (err < 0) {
-		SNDERR("failed to truncate SHM position %s: %s", shm->name, strerror(errno));
-		shm_unlink(shm->name);
-		return -errno;
-	}
-
-	/* map it locally for context readback */
-	shm->addr = mmap(NULL, shm->size, PROT_READ | PROT_WRITE, MAP_SHARED, shm->fd, 0);
-	if (!shm->addr) {
-		SNDERR("failed to mmap SHM position%s: %s", shm->name, strerror(errno));
-		shm_unlink(shm->name);
-		return -errno;
-	}
-
-	return 0;
-}
-
-/*
- * Free and delete shared memory region resourses in SHM object.
- */
-void plug_shm_free(struct plug_shm_desc *shm)
-{
-	close(shm->fd);
-	shm_unlink(shm->name);
-}
-
-
-/*
- * Free and delete message queue resources in IPC object.
- */
-void plug_socket_free(struct plug_socket_desc *ipc)
-{
-	unlink(ipc->path);
-}
-
-/*
- * -D ALSA device. e.g.
- * -R realtime (needs parent to set uid)
- * -p Force run on P core
- * -e Force run on E core
- * -t topology name.
- * -L log file (otherwise stdout)
- * -h help
- */
-static void usage(char *name)
-{
-	fprintf(stdout, "Usage: %s -D ALSA device -T topology\n", name);
-}
-
-int main(int argc, char *argv[], char *env[])
-{
-	struct sof_pipe sp = {0};
-	int option = 0;
-	int ret = 0;
-
-	/* default config */
-	sp.log = stdout;
-	sp.alsa_name = "default"; /* default sound device */
-	_sp = &sp;
-
-	/* parse all args */
-	while ((option = getopt(argc, argv, "hD:RpeT:")) != -1) {
-		switch (option) {
-		/* Alsa device  */
-		case 'D':
-			sp.alsa_name = strdup(optarg);
-			break;
-		case 'R':
-			sp.realtime = 1;
-			break;
-		case 'p':
-			sp.use_P_core = 1;
-			sp.use_E_core = 0;
-			break;
-		case 'e':
-			sp.use_E_core = 1;
-			sp.use_P_core = 0;
-			break;
-		case 'T':
-			snprintf(sp.topology_name, NAME_SIZE, "%s", optarg);
-			break;
-
-		/* print usage */
-		default:
-			fprintf(sp.log, "unknown option %c\n", option);
-			__attribute__ ((fallthrough));
-		case 'h':
-			usage(argv[0]);
-			exit(EXIT_SUCCESS);
-		}
-	}
-
-	/* validate cmd line params */
-	if (strlen(sp.topology_name) == 0) {
-		fprintf(sp.log, "error: no IPC topology name specified\n");
-		exit(EXIT_FAILURE);
-	}
-
-	/* global IPC access serialisation mutex */
-	ret = pthread_mutex_init(&sp.ipc_lock, NULL);
-	if (ret < 0) {
-		fprintf(sp.log, "error: cant create mutex %s\n",  strerror(errno));
-		exit(EXIT_FAILURE);
-	}
-
-	fprintf(sp.log, "sof-pipe-%s: using topology %s\n", VERSION, sp.topology_name);
-
-	/* set CPU affinity */
-	if (sp.use_E_core || sp.use_P_core) {
-		ret = pipe_set_affinity(&sp);
-		if (ret < 0)
-			goto out;
-	}
-
-	/* initialize ipc and scheduler */
-	if (pipe_sof_setup(sof_get()) < 0) {
-		fprintf(stderr, "error: pipeline init\n");
-		exit(EXIT_FAILURE);
-	}
-
-	/* global context - plugin clients open this first */
-	ret = plug_shm_init(&sp.shm_context, sp.topology_name, "ctx", 0);
-	if (ret < 0)
-		goto out;
-
-	/* cleanup any lingering global IPC files */
-	shm_unlink(sp.shm_context.name);
-
-	/* make sure we can cleanly shutdown */
-	ret = pipe_init_signals(&sp);
-	if (ret < 0)
-		goto out;
-
-	/* mmap context on successful topology load */
-	ret = plug_shm_create(&sp.shm_context);
-	if (ret < 0)
-		goto out;
-
-	/* now prep the global context for client plugin access */
-	sp.glb = sp.shm_context.addr;
-	memset(sp.glb, 0, sizeof(*sp.glb));
-	sprintf(sp.glb->magic, "%s", SOF_MAGIC);
-	sp.glb->size = sizeof(*sp.glb);
-	sp.glb->state = SOF_PLUGIN_STATE_INIT;
-	sp.tplg.tplg_file = sp.topology_name;
-	sp.tplg.ipc_major = 4; //HACK hard code to v4
-
-	/* sofpipe is now ready */
-	sp.glb->state = SOF_PLUGIN_STATE_INIT;
-
-	ret = plug_socket_path_init(&sp.ipc_socket, "sof", "ipc", 0);
-	if (ret < 0)
-		goto out;
-
-	/* now process IPCs as they arrive from plugins */
-	ret = pipe_ipc_process(&sp, &sp.ipc_socket);
-
-out:
-	fprintf(sp.log, "shutdown main\n");
-	shutdown(&sp);
-	return ret;
-}
diff --git a/tools/plugin/pipe/pipe.h b/tools/plugin/pipe/pipe.h
deleted file mode 100644
index 8f8fb26080ea..000000000000
--- a/tools/plugin/pipe/pipe.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- *
- * Copyright(c) 2022-2023 Intel Corporation. All rights reserved.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#ifndef __SOF_PLUGIN_PIPE_H__
-#define __SOF_PLUGIN_PIPE_H__
-
-#include <stdatomic.h>
-#include <stdint.h>
-#include <pthread.h>
-#include <signal.h>
-
-#include <alsa/asoundlib.h>
-#include <tplg_parser/topology.h>
-#include <tplg_parser/tokens.h>
-#include "common.h"
-
-struct sof_pipe;
-
-#define MAX_MODULE_ID	256
-#define MAX_PIPE_THREADS	128
-#define MAX_PIPELINES	32
-
-struct pipethread_data {
-	pthread_t pcm_thread;
-	pthread_t ipc_thread;
-	struct sof_pipe *sp;
-	struct pipeline *pcm_pipeline;
-	/* PCM flow control */
-	struct plug_sem_desc ready;
-	struct plug_sem_desc done;
-	atomic_int pipe_users;
-};
-
-struct sof_pipe_module {
-	void *handle;
-	char uuid[SOF_UUID_SIZE];
-	int module_id;
-};
-
-struct sof_pipe {
-	const char *alsa_name;
-	char topology_name[NAME_SIZE];
-	int realtime;
-	int use_P_core;
-	int use_E_core;
-	int capture;
-	int file_mode;
-	int pipe_thread_count;
-
-	struct sigaction action;
-
-	/* SHM for stream context sync */
-	struct plug_shm_desc shm_context;
-	struct plug_shm_glb_state *glb;
-
-	FILE *log;
-	pthread_mutex_t ipc_lock;
-	struct tplg_context tplg;
-	struct tplg_comp_info *comp_list;
-	struct list_item widget_list; /* list of widgets */
-	struct list_item route_list; /* list of widget connections */
-	struct list_item pcm_list; /* list of PCMs */
-	int info_elems;
-	int info_index;
-
-	/* IPC */
-	pthread_t ipc_pcm_thread;
-	struct plug_socket_desc ipc_socket; /* queue used by plugin to send IPCs */
-	int client_sock_ids[MAX_IPC_CLIENTS];
-	int client_count;
-	int new_client_id;
-
-	/* module SO handles */
-	struct sof_pipe_module module[MAX_MODULE_ID];
-	int mod_idx;
-
-	/* pipeline context */
-	struct pipethread_data pipeline_ctx[MAX_PIPELINES];
-};
-
-/* global needed for signal handler */
-extern struct sof_pipe *_sp;
-
-int pipe_thread_new(struct sof_pipe *sp, struct pipeline *p);
-int pipe_thread_free(struct sof_pipe *sp, int pipeline_id);
-int pipe_thread_start(struct sof_pipe *sp, struct pipeline *p);
-int pipe_thread_stop(struct sof_pipe *sp, struct pipeline *p);
-int pipe_sof_setup(struct sof *sof);
-int pipe_kcontrol_cb_new(struct snd_soc_tplg_ctl_hdr *tplg_ctl,
-			 void *comp, void *arg);
-
-/* set pipeline to realtime priority */
-int pipe_set_rt(struct sof_pipe *sp);
-
-/* set ipc thread to low priority */
-int pipe_set_ipc_lowpri(struct sof_pipe *sp);
-
-int pipe_ipc_process(struct sof_pipe *sp, struct plug_socket_desc *ipc_socket);
-
-int pipe_ipc_new(struct sof_pipe *sp, int pri, int core);
-void pipe_ipc_free(struct sof_pipe *sp);
-
-int pipe_set_affinity(struct sof_pipe *sp);
-
-int pipe_ipc_message(struct sof_pipe *sp, void *mailbox, size_t bytes);
-
-int pipe_ipc_do(struct sof_pipe *sp, void *mailbox, size_t bytes);
-
-/*
- * Topology
- */
-int plug_parse_topology(struct sof_pipe *sp, struct tplg_context *ctx);
-
-int plug_load_widget(struct sof_pipe *sp, struct tplg_context *ctx);
-
-int plug_register_graph(struct sof_pipe *sp, struct tplg_context *ctx,
-			struct tplg_comp_info *temp_comp_list,
-			char *pipeline_string,
-			int count, int num_comps, int pipeline_id);
-
-#endif
diff --git a/tools/plugin/pipe/pipeline.c b/tools/plugin/pipe/pipeline.c
deleted file mode 100644
index 2985e46d04ad..000000000000
--- a/tools/plugin/pipe/pipeline.c
+++ /dev/null
@@ -1,356 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-//
-// Copyright(c) 2022 Intel Corporation. All rights reserved.
-//
-// Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
-
-/*
- * SOF pipeline in userspace.
- */
-
-#include <stdio.h>
-#include <sys/poll.h>
-#include <string.h>
-#include <sys/types.h>
-#include <unistd.h>
-#include <stdlib.h>
-#include <sys/wait.h>
-#include <sys/stat.h>
-#include <signal.h>
-#include <fcntl.h>
-#include <sys/mman.h>
-#include <semaphore.h>
-#include <assert.h>
-#include <errno.h>
-#include <pthread.h>
-#include <limits.h>
-#include <dlfcn.h>
-
-#include <rtos/sof.h>
-#include <sof/audio/pipeline.h>
-#include <sof/audio/component.h>
-#include <sof/audio/component_ext.h>
-#include <rtos/task.h>
-#include <sof/lib/notifier.h>
-#include <sof/schedule/edf_schedule.h>
-#include <sof/schedule/ll_schedule.h>
-#include <sof/schedule/ll_schedule_domain.h>
-#include <sof/schedule/schedule.h>
-#include <stdatomic.h>
-
-#include "common.h"
-#include "pipe.h"
-
-#define MAX_PIPE_USERS	8
-
-static struct ll_schedule_domain domain = {0};
-
-// TODO: all these steps are probably not needed - i.e we only need IPC and pipeline.
-int pipe_sof_setup(struct sof *sof)
-{
-	/* register modules */
-
-	domain.next_tick = 0;
-
-	/* init components */
-	sys_comp_init(sof);
-
-	/* other necessary initializations, todo: follow better SOF init */
-	pipeline_posn_init(sof);
-	init_system_notify(sof);
-
-	/* init IPC */
-	if (ipc_init(sof) < 0) {
-		fprintf(stderr, "error: IPC init\n");
-		return -EINVAL;
-	}
-
-	/* init LL scheduler */
-	if (scheduler_init_ll(&domain) < 0) {
-		fprintf(stderr, "error: edf scheduler init\n");
-		return -EINVAL;
-	}
-
-	/* init EDF scheduler */
-	if (scheduler_init_edf() < 0) {
-		fprintf(stderr, "error: edf scheduler init\n");
-		return -EINVAL;
-	}
-
-	return 0;
-}
-
-static inline int pipe_copy_ready(struct pipethread_data *pd)
-{
-	struct timespec delay;
-	int err;
-
-	/* get the current time for source delay */
-	err = clock_gettime(CLOCK_REALTIME, &delay);
-	if (err == -1) {
-		fprintf(_sp->log, "shm: cant get time: %s", strerror(errno));
-		return -errno;
-	}
-
-	// TODO get from rate
-	plug_timespec_add_ms(&delay, 2000);
-
-	/* wait for data from source */
-	err = sem_timedwait(pd->ready.sem, &delay);
-	if (err == -1) {
-		fprintf(_sp->log, "%s %d: fatal timeout: %s on %s\n", __FILE__, __LINE__,
-			strerror(errno), pd->ready.name);
-		return -errno;
-	}
-
-	return 0;
-}
-
-static inline void pipe_copy_done(struct pipethread_data *pd)
-{
-	/* tell peer we are done */
-	sem_post(pd->done.sem);
-}
-
-static void *pipe_process_thread(void *arg)
-{
-	struct pipethread_data *pd = arg;
-	int err;
-
-	fprintf(_sp->log, "pipe thread started for pipeline %d\n",
-		pd->pcm_pipeline->pipeline_id);
-
-	do {
-		if (pd->pcm_pipeline->status != COMP_STATE_ACTIVE) {
-			fprintf(_sp->log, "pipe state non active %d\n",
-				pd->pcm_pipeline->status);
-			break;
-		}
-
-		if (pd->pipe_users <= 0) {
-			fprintf(_sp->log, "pipe no users.\n");
-			break;
-		}
-
-		/* wait for pipe to be ready */
-		err = pipe_copy_ready(pd);
-		if (err < 0) {
-			fprintf(_sp->log, "pipe ready timeout on pipeline %d state %d users %d\n",
-				pd->pcm_pipeline->pipeline_id, pd->pcm_pipeline->status,
-				pd->pipe_users);
-			break;
-		}
-
-		/* sink has read data so now generate more it */
-		err = pipeline_copy(pd->pcm_pipeline);
-
-		pipe_copy_done(pd);
-
-		if (err < 0) {
-			fprintf(_sp->log, "pipe thread error %d\n", err);
-			break;
-		} else if (err > 0) {
-			fprintf(_sp->log, "pipe thread complete %d\n", err);
-			break;
-		}
-
-	} while (1);
-
-	fprintf(_sp->log, "pipe complete for pipeline %d\n",
-		pd->pcm_pipeline->pipeline_id);
-	return 0;
-}
-
-static void *pipe_ipc_process_thread(void *arg)
-{
-	struct pipethread_data *pd = arg;
-	int err;
-
-	/* initialise semaphores to default starting value */
-	err = sem_init(pd->done.sem, 1, 0);
-	if (err < 0) {
-		fprintf(_sp->log, "failed to reset DONE: %s\n",
-			strerror(errno));
-		return NULL;
-	}
-	err = sem_init(pd->ready.sem, 1, 0);
-	if (err < 0) {
-		fprintf(_sp->log, "failed to reset READY: %s\n",
-			strerror(errno));
-		return NULL;
-	}
-
-	return NULL;
-}
-
-int pipe_thread_start(struct sof_pipe *sp, struct pipeline *p)
-{
-	struct pipethread_data *pipeline_ctx = sp->pipeline_ctx;
-	struct pipethread_data *pd;
-	int pipeline_id;
-	int ret, pipe_users;
-
-	pipeline_id = p->pipeline_id;
-
-	if (pipeline_id >= MAX_PIPELINES) {
-		fprintf(_sp->log, "error: pipeline ID %d out of range\n", pipeline_id);
-		return -EINVAL;
-	}
-
-	if (!pipeline_ctx[pipeline_id].sp) {
-		fprintf(_sp->log, "error: pipeline ID %d not in use\n", pipeline_id);
-		return -EINVAL;
-	}
-	pd = &pipeline_ctx[pipeline_id];
-
-	/* only create thread if not active */
-	pipe_users = atomic_fetch_add(&pd->pipe_users, 1);
-	if (pipe_users > 0) {
-		fprintf(_sp->log, "pipeline ID %d thread already running %d users\n",
-			pipeline_id, pipe_users);
-		return 0;
-	}
-
-	fprintf(_sp->log, "pipeline ID %d thread not running so starting...\n", pipeline_id);
-
-	/* first user so start the PCM pipeline thread */
-	ret = pthread_create(&pd->pcm_thread, NULL, pipe_process_thread, pd);
-	if (ret < 0) {
-		fprintf(_sp->log, "failed to create PCM thread: %s\n", strerror(errno));
-		return -errno;
-	}
-
-	return ret;
-}
-
-int pipe_thread_stop(struct sof_pipe *sp, struct pipeline *p)
-{
-	struct pipethread_data *pipeline_ctx = sp->pipeline_ctx;
-	struct pipethread_data *pd;
-	int pipeline_id;
-	int ret, pipe_users;
-
-	pipeline_id = p->pipeline_id;
-
-	/* this is called when the pipeline is PAUSED for the first time before RUNNING */
-	if (p->status == COMP_STATE_INIT)
-		return 0;
-
-	if (pipeline_id >= MAX_PIPELINES) {
-		fprintf(_sp->log, "error: pipeline ID %d out of range\n", pipeline_id);
-		return -EINVAL;
-	}
-
-	if (!pipeline_ctx[pipeline_id].sp) {
-		fprintf(_sp->log, "error: pipeline ID %d not in use\n", pipeline_id);
-		return -EINVAL;
-	}
-	pd = &pipeline_ctx[pipeline_id];
-
-	/* only join thread if not active */
-	pipe_users = atomic_fetch_sub(&pd->pipe_users, 1);
-	if (pipe_users != 1) {
-		fprintf(_sp->log, "pipeline ID %d thread has multiple %d users\n",
-			pipeline_id, pipe_users);
-		return 0;
-	}
-
-	fprintf(_sp->log, "pipeline ID %d thread can be stopped...\n", pipeline_id);
-
-	ret = pthread_cancel(pd->pcm_thread);
-	if (ret < 0) {
-		fprintf(_sp->log, "failed to cancel PCM thread: %s\n", strerror(errno));
-		return -errno;
-	}
-
-	return ret;
-}
-
-int pipe_thread_new(struct sof_pipe *sp, struct pipeline *p)
-{
-	struct pipethread_data *pipeline_ctx = sp->pipeline_ctx;
-	struct pipethread_data *pd;
-	int ret;
-
-	if (!p) {
-		fprintf(_sp->log, "error: invalid pipeline\n");
-		return -EINVAL;
-	}
-
-	if (p->pipeline_id >= MAX_PIPELINES) {
-		fprintf(_sp->log, "error: pipeline ID %d out of range\n", p->pipeline_id);
-		return -EINVAL;
-	}
-
-	if (pipeline_ctx[p->pipeline_id].sp) {
-		fprintf(_sp->log, "error: pipeline ID %d in use\n", p->pipeline_id);
-		return -EINVAL;
-	}
-	pd = &pipeline_ctx[p->pipeline_id];
-	pd->sp = _sp;
-	pd->pcm_pipeline = p;
-
-	/* init names of shared resources */
-	ret = plug_lock_init(&pd->ready, _sp->topology_name, "ready", p->pipeline_id);
-	if (ret < 0)
-		return ret;
-
-	ret = plug_lock_init(&pd->done, _sp->topology_name, "done", p->pipeline_id);
-	if (ret)
-		return ret;
-
-	/* open semaphores */
-	ret = plug_lock_create(&pd->ready);
-	if (ret < 0)
-		return ret;
-	ret = plug_lock_create(&pd->done);
-	if (ret < 0)
-		goto lock_err;
-
-	/* start IPC pipeline thread */
-	ret = pthread_create(&pd->ipc_thread, NULL, pipe_ipc_process_thread, pd);
-	if (ret < 0) {
-		fprintf(_sp->log, "failed to create IPC thread: %s\n", strerror(errno));
-		ret = -errno;
-		goto lock2_err;
-	}
-
-	return 0;
-
-lock2_err:
-	plug_lock_free(&pd->done);
-lock_err:
-	plug_lock_free(&pd->ready);
-	return ret;
-}
-
-int pipe_thread_free(struct sof_pipe *sp, int pipeline_id)
-{
-	struct pipethread_data *pipeline_ctx = sp->pipeline_ctx;
-	struct pipethread_data *pd;
-	int err;
-
-	if (pipeline_id >= MAX_PIPELINES) {
-		fprintf(_sp->log, "error: pipeline ID %d out of range\n", pipeline_id);
-		return -EINVAL;
-	}
-
-	if (!pipeline_ctx[pipeline_id].sp) {
-		fprintf(_sp->log, "error: pipeline ID %d not in use\n", pipeline_id);
-		return -EINVAL;
-	}
-
-	pd = &pipeline_ctx[pipeline_id];
-
-	err = pthread_cancel(pd->ipc_thread);
-	if (err < 0) {
-		fprintf(_sp->log, "failed to create IPC thread: %s\n", strerror(errno));
-		return -errno;
-	}
-
-	plug_lock_free(&pd->ready);
-	plug_lock_free(&pd->done);
-
-	pd->sp = NULL;
-	return 0;
-}
diff --git a/tools/probes/CMakeLists.txt b/tools/probes/CMakeLists.txt
index 1b39e6d192db..b38cd965844d 100644
--- a/tools/probes/CMakeLists.txt
+++ b/tools/probes/CMakeLists.txt
@@ -17,7 +17,7 @@ target_include_directories(sof-probes PRIVATE
 
 # TODO: probes should not need to include RTOS headers. FIX.
 target_include_directories(sof-probes PRIVATE
-	"../../xtos/include"
+	"../../posix/include"
 )
 
 install(TARGETS sof-probes DESTINATION bin)
diff --git a/tools/testbench/CMakeLists.txt b/tools/testbench/CMakeLists.txt
index 100dc320debf..d73d20ed2c5b 100644
--- a/tools/testbench/CMakeLists.txt
+++ b/tools/testbench/CMakeLists.txt
@@ -55,7 +55,7 @@ if (supports_implicit_fallthrough)
 endif()
 
 target_compile_options(${testbench} PRIVATE -g -O3 -Wall -Werror -Wmissing-prototypes
-  ${implicit_fallthrough} -DCONFIG_LIBRARY -DCONFIG_LIBRARY_STATIC -imacros${config_h})
+  ${implicit_fallthrough} -DCONFIG_LIBRARY -imacros${config_h})
 
 target_link_libraries(${testbench} PRIVATE -lm)
 
@@ -75,7 +75,6 @@ ExternalProject_Add(sof_ep
 		-DCMAKE_VERBOSE_MAKEFILE=${CMAKE_VERBOSE_MAKEFILE}
 		-DINIT_CONFIG=library_defconfig
 		-DCONFIG_H_PATH=${config_h}
-		-DCONFIG_LIBRARY_STATIC=ON
 	BUILD_ALWAYS 1
 	BUILD_BYPRODUCTS "${sof_install_directory}/lib/libsof.a"
 )
@@ -95,7 +94,6 @@ ExternalProject_Add(parser_ep
 	CMAKE_ARGS
 		-DCMAKE_INSTALL_PREFIX=${PROJECT_BINARY_DIR}/sof_parser/install
 		-DCMAKE_VERBOSE_MAKEFILE=${CMAKE_VERBOSE_MAKEFILE}
-		-DCONFIG_LIBRARY_STATIC=ON
 	BUILD_ALWAYS 1
 	BUILD_BYPRODUCTS "${parser_install_dir}/lib/libsof_tplg_parser.a"
 )
diff --git a/tools/testbench/README.md b/tools/testbench/README.md
index d4030adc426d..82e1630dc771 100644
--- a/tools/testbench/README.md
+++ b/tools/testbench/README.md
@@ -266,7 +266,6 @@ index 1b9483ffe..5c944d292 100644
 +CONFIG_IPC_MAJOR_3=y
 +CONFIG_IPC_MAJOR_4=n
  CONFIG_LIBRARY=y
- CONFIG_LIBRARY_STATIC=y
  CONFIG_MATH_IIR_DF2T=y
 ```
 
diff --git a/tools/topology/topology2/development/sof-plugin.conf b/tools/topology/topology2/development/sof-plugin.conf
deleted file mode 100644
index dcbe68b056de..000000000000
--- a/tools/topology/topology2/development/sof-plugin.conf
+++ /dev/null
@@ -1,347 +0,0 @@
-<searchdir:include>
-<searchdir:include/common>
-<searchdir:include/components>
-<searchdir:include/dais>
-<searchdir:include/pipelines/cavs>
-<searchdir:platform>
-<searchdir:platform/intel>
-
-<vendor-token.conf>
-<manifest.conf>
-<tokens.conf>
-<host-gateway-capture.conf>
-<host-gateway-playback.conf>
-<mixout-gain-dai-copier-playback.conf>
-<host-copier-gain-mixin-playback.conf>
-<io-gateway-capture.conf>
-<io-gateway.conf>
-<data.conf>
-<pcm.conf>
-<pcm_caps.conf>
-<fe_dai.conf>
-<ssp.conf>
-<route.conf>
-<common_definitions.conf>
-<dai-copier.conf>
-<module-copier.conf>
-<gain.conf>
-<pipeline.conf>
-<input_audio_format.conf>
-<output_audio_format.conf>
-<ov_noise_suppression.conf>
-
-Object.Pipeline.io-gateway-capture [
-	{
-		index		10
-		direction	capture
-
-		Object.Widget.dai-copier."1" {
-			dai_index	1
-			dai_type	"SSP"
-			type		dai_out
-			copier_type	"SSP"
-			stream_name	"NoCodec-1"
-			node_type	$I2S_LINK_INPUT_CLASS
-
-			num_input_audio_formats 1
-			Object.Base.input_audio_format [
-				{
-					in_rate			16000
-					in_bit_depth		16
-					in_valid_bit_depth	16
-				}
-			]
-			num_output_audio_formats 1
-			Object.Base.output_audio_format [
-				{
-					out_rate		16000
-					out_bit_depth		16
-					out_valid_bit_depth	16
-				}
-			]
-		}
-	}
-]
-
-Object.Pipeline.host-gateway-capture [
-	{
-		index 	9
-
-		Object.Widget.host-copier.1 {
-			stream_name 'SSP1 Capture'
-			pcm_id 1
-			num_input_audio_formats 1
-			Object.Base.input_audio_format [
-				{
-					in_rate			16000
-					in_bit_depth		16
-					in_valid_bit_depth	16
-				}
-			]
-			num_output_audio_formats 1
-			Object.Base.output_audio_format [
-				{
-					out_rate		16000
-					out_bit_depth		16
-					out_valid_bit_depth	16
-				}
-			]
-		}
-	}
-]
-
-IncludeByKey.PLAYBACK_PROCESS {
-"passthrough"	{
-		Object.Pipeline.io-gateway [
-			{
-				index	4
-				direction	playback
-
-				Object.Widget.dai-copier.1 {
-					dai_index 1
-					dai_type "SSP"
-					copier_type "SSP"
-					stream_name "NoCodec-1"
-					node_type $I2S_LINK_OUTPUT_CLASS
-					num_input_audio_formats 1
-					Object.Base.input_audio_format [
-						{
-							in_bit_depth		16
-							in_valid_bit_depth	16
-						}
-					]
-					num_output_audio_formats 1
-					Object.Base.output_audio_format [
-						{
-							out_bit_depth		16
-							out_valid_bit_depth	16
-						}
-					]
-				}
-			}
-		]
-		Object.Pipeline.host-gateway-playback [
-			{
-				index	3
-				Object.Widget.host-copier.1 {
-					stream_name 'SSP1 Playback'
-					pcm_id 1
-					num_input_audio_formats 1
-					Object.Base.input_audio_format [
-						{
-							in_bit_depth		16
-							in_valid_bit_depth	16
-						}
-					]
-					num_output_audio_formats 1
-					Object.Base.output_audio_format [
-						{
-							out_bit_depth		16
-							out_valid_bit_depth	16
-						}
-					]
-				}
-			}
-		]
-	}
-"mix"	{
-		Object.Pipeline.mixout-gain-dai-copier-playback [
-			{
-				index	4
-
-				Object.Widget.dai-copier.1 {
-					dai_index 1
-					dai_type "SSP"
-					copier_type "SSP"
-					stream_name "NoCodec-1"
-					node_type $I2S_LINK_OUTPUT_CLASS
-					num_input_audio_formats 1
-					Object.Base.input_audio_format [
-						{
-							in_bit_depth		16
-							in_valid_bit_depth	16
-						}
-					]
-					num_output_audio_formats 1
-					Object.Base.output_audio_format [
-						{
-							out_bit_depth		16
-							out_valid_bit_depth	16
-						}
-					]
-				}
-				Object.Widget.gain.1 {
-					curve_type "windows_fade"
-					Object.Control.mixer.1 {
-						name 'Post Mixer PlugPCM Playback Volume'
-					}
-					num_input_audio_formats 1
-					Object.Base.input_audio_format [
-						{
-							in_bit_depth		16
-							in_valid_bit_depth	16
-						}
-					]
-					num_output_audio_formats 1
-					Object.Base.output_audio_format [
-						{
-							out_bit_depth		16
-							out_valid_bit_depth	16
-						}
-					]
-				}
-				Object.Widget.mixout.1 {
-					num_input_audio_formats 1
-					Object.Base.input_audio_format [
-						{
-							in_bit_depth		16
-							in_valid_bit_depth	16
-						}
-					]
-					num_output_audio_formats 1
-					Object.Base.output_audio_format [
-						{
-							out_bit_depth		16
-							out_valid_bit_depth	16
-						}
-					]
-				}
-			}
-		]
-		Object.Pipeline.host-copier-gain-mixin-playback [
-			{
-				index	3
-				Object.Widget.host-copier.1 {
-					stream_name 'SSP1 Playback'
-					pcm_id 1
-					num_input_audio_formats 1
-					Object.Base.input_audio_format [
-						{
-							in_bit_depth		16
-							in_valid_bit_depth	16
-						}
-					]
-					num_output_audio_formats 1
-					Object.Base.output_audio_format [
-						{
-							out_bit_depth		16
-							out_valid_bit_depth	16
-						}
-					]
-				}
-				Object.Widget.gain.1 {
-					curve_type "windows_fade"
-					Object.Control.mixer.1 {
-						name 'Pre Mixer PlugPCM Playback Volume'
-					}
-					num_input_audio_formats 1
-					Object.Base.input_audio_format [
-						{
-							in_bit_depth		16
-							in_valid_bit_depth	16
-						}
-					]
-					num_output_audio_formats 1
-					Object.Base.output_audio_format [
-						{
-							out_bit_depth		16
-							out_valid_bit_depth	16
-						}
-					]
-				}
-				Object.Widget.mixin.1 {
-					num_input_audio_formats 1
-					Object.Base.input_audio_format [
-						{
-							in_bit_depth		16
-							in_valid_bit_depth	16
-						}
-					]
-					num_output_audio_formats 1
-					Object.Base.output_audio_format [
-						{
-							out_bit_depth		16
-							out_valid_bit_depth	16
-						}
-					]
-				}
-			}
-		]
-	}
-}
-
-Object.PCM.pcm [
-	{
-		name	"PluginPCM"
-		id 1
-		direction	"duplex"
-		Object.Base.fe_dai.1 {
-			name	"PluginPlayback"
-		}
-
-		Object.PCM.pcm_caps.1 {
-			direction	"playback"
-			name "SSP1 Playback"
-			formats 'S16_LE'
-		}
-
-		Object.PCM.pcm_caps.2 {
-			direction	"capture"
-			name "SSP1 Capture"
-			formats 'S16_LE'
-		}
-	}
-]
-
-IncludeByKey.NOISE_SUPPRESSION {
-"true" {
-	Object.Widget.ov_ns.1 {
-		index 9
-	}
-	Object.Base.route [
-		{
-			source	"dai-copier.SSP.NoCodec-1.capture"
-			sink	"ov_ns.9.1"
-		}
-		{
-			source "ov_ns.9.1"
-			sink	"host-copier.1.capture"
-		}
-	]
-	}
-"false" {
-	Object.Base.route [
-		{
-			source	"dai-copier.SSP.NoCodec-1.capture"
-			sink	"host-copier.1.capture"
-		}
-	]
-	}
-}
-
-IncludeByKey.PLAYBACK_PROCESS {
-"passthrough" {
-		Object.Base.route [
-			{
-				source	"host-copier.1.playback"
-				sink	"dai-copier.SSP.NoCodec-1.playback"
-			}
-		]
-	}
-"mix"	{
-		Object.Base.route [
-			{
-				source	"host-copier.1.playback"
-				sink	"gain.3.1"
-			}
-			{
-				source	"mixin.3.1"
-				sink	"mixout.4.1"
-			}
-			{
-				source	"gain.4.1"
-				sink	"dai-copier.SSP.NoCodec-1.playback"
-			}
-		]
-	}
-}
diff --git a/tools/topology/topology2/development/tplg-targets.cmake b/tools/topology/topology2/development/tplg-targets.cmake
index faca251d9864..ebd2d9166737 100644
--- a/tools/topology/topology2/development/tplg-targets.cmake
+++ b/tools/topology/topology2/development/tplg-targets.cmake
@@ -355,9 +355,6 @@ PREPROCESS_PLUGINS=nhlt,NHLT_BIN=nhlt-sof-hda-generic-ace1-4ch-mfcc.bin,\
 NUM_DMICS=4,PDM1_MIC_A_ENABLE=1,PDM1_MIC_B_ENABLE=1,DMIC1_RATE=16000,\
 DMIC1_ENABLE=MFCC,DMIC1_MFCC_PARAMS=default"
 
-# Topology for SOF plugin
-"development/sof-plugin\;sof-plugin\;NOISE_SUPPRESSION=false,PLAYBACK_PROCESS=passthrough"
-
 # mtl-rt5650 with AEC but not DTS
 "cavs-rt5682\;sof-mtl-rt5650-google-aec\;PLATFORM=mtl,NUM_DMICS=4,PDM1_MIC_A_ENABLE=1,\
 PDM1_MIC_B_ENABLE=1,DMIC0_PCM_ID=99,PREPROCESS_PLUGINS=nhlt,\
diff --git a/tools/topology/topology2/include/components/ov_noise_suppression.conf b/tools/topology/topology2/include/components/ov_noise_suppression.conf
deleted file mode 100644
index ff06f1fedf6a..000000000000
--- a/tools/topology/topology2/include/components/ov_noise_suppression.conf
+++ /dev/null
@@ -1,81 +0,0 @@
-#
-# OpenVino noise suppression module
-#
-# A noise suppression widget. All attributes defined herein are namespaced
-# by alsatplg to "Object.Widget.ov_ns.N.attribute_name"
-#
-# Usage: this component can be used by declaring int a parent object. i.e.
-#
-# 	Object.Widget.ov_ns."N" {
-#		index	1
-#		no_pm	"true"
-#	}
-#
-# Where N is the unique instance number for ov_ns widget in the same alsaconf node.
-
-Class.Widget."ov_ns" {
-	#
-	# Pipeline ID for the ov_ns widget object
-	#
-	DefineAttribute."index" {}
-
-	#
-	# ov_ns object instance
-	#
-	DefineAttribute."instance" {}
-
-	#include common component definition
-	<include/components/widget-common.conf>
-
-	# Only 16-bit depth format is supported by ov_ns
-	num_input_audio_formats 1
-	num_output_audio_formats 1
-	# 16-bit 16KHz 2ch
-	Object.Base.input_audio_format [
-		{
-			in_rate			16000
-			in_bit_depth            16
-			in_valid_bit_depth      16
-		}
-	]
-	Object.Base.output_audio_format [
-		{
-			out_rate		16000
-			out_bit_depth           16
-			out_valid_bit_depth     16
-		}
-	]
-
-	# Attribute categories
-	attributes {
-		#
-		# The ov_ns widget name would be constructed using the index and instance attributes.
-		# For ex: "ov_ns.1.1" or "ov_ns.10.2" etc.
-		#
-		!constructor [
-			"index"
-			"instance"
-		]
-
-		#
-		# immutable attributes cannot be modified in the object instance
-		#
-		!immutable [
-			"uuid"
-			"type"
-		]
-
-		#
-		# ov_ns widget objects instantiated within the same alsaconf node must have unique
-		# instance attribute
-		#
-		unique	"instance"
-	}
-
-	# Default attribute values for ov_ns widget
-	type 			"effect"
-	uuid 			"a7:71:e6:7a:17:46:09:4a:bf:6d:9d:29:c9:98:db:c1"
-	no_pm			"true"
-	num_input_pins	1
-	num_output_pins	1
-}
diff --git a/tools/tplg_parser/CMakeLists.txt b/tools/tplg_parser/CMakeLists.txt
index 1569284b097d..f7a447a6e6c2 100644
--- a/tools/tplg_parser/CMakeLists.txt
+++ b/tools/tplg_parser/CMakeLists.txt
@@ -11,11 +11,7 @@ set(default_asoc_h "/usr/include/alsa/sound/uapi/asoc.h")
 
 set(sof_source_directory "${PROJECT_SOURCE_DIR}/../..")
 
-if (CONFIG_LIBRARY_STATIC)
-	add_library(sof_tplg_parser STATIC "")
-else()
-	add_library(sof_tplg_parser SHARED "")
-endif()
+add_library(sof_tplg_parser STATIC "")
 
 if (CONFIG_IPC4)
 	set(tplg_ipc CONFIG_IPC_MAJOR_4)
diff --git a/xtos/include/rtos/bit.h b/xtos/include/rtos/bit.h
deleted file mode 100644
index 3dde908c2d6b..000000000000
--- a/xtos/include/rtos/bit.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- *
- * Copyright(c) 2018 Intel Corporation. All rights reserved.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#ifndef __XTOS_RTOS_BIT_H__
-#define __XTOS_RTOS_BIT_H__
-
-#if ASSEMBLY
-#define BIT(b)			(1 << (b))
-#else
-#define BIT(b)			(1UL << (b))
-#endif
-
-#define MASK(b_hi, b_lo)	\
-	(((1ULL << ((b_hi) - (b_lo) + 1ULL)) - 1ULL) << (b_lo))
-#define SET_BIT(b, x)		(((x) & 1) << (b))
-#define SET_BITS(b_hi, b_lo, x)	\
-	(((x) & ((1ULL << ((b_hi) - (b_lo) + 1ULL)) - 1ULL)) << (b_lo))
-#define GET_BIT(b, x) \
-	(((x) & (1ULL << (b))) >> (b))
-#define GET_BITS(b_hi, b_lo, x) \
-	(((x) & MASK(b_hi, b_lo)) >> (b_lo))
-
-#endif /* __XTOS_RTOS_BIT_H__ */
diff --git a/xtos/include/rtos/string_macro.h b/xtos/include/rtos/string_macro.h
deleted file mode 100644
index 76043b2a47c2..000000000000
--- a/xtos/include/rtos/string_macro.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- *
- * Copyright(c) 2024 Intel Corporation. All rights reserved.
- *
- * Author: Baofeng Tian <Baofeng.tian@intel.com>
- */
-
-#ifndef __XTOS_RTOS_STRING_MACRO_H__
-#define __XTOS_RTOS_STRING_MACRO_H__
-
-#define Z_STRINGIFY(x) #x
-#define STRINGIFY(s) Z_STRINGIFY(s)
-
-#define _DO_CONCAT(x, y) x ## y
-#define _CONCAT(x, y) _DO_CONCAT(x, y)
-
-#endif /* __XTOS_RTOS_STRING_MACRO_H__ */
diff --git a/xtos/include/sof/compiler_attributes.h b/xtos/include/sof/compiler_attributes.h
deleted file mode 100644
index d961fa990613..000000000000
--- a/xtos/include/sof/compiler_attributes.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- *
- * Copyright(c) 2019 Intel Corporation. All rights reserved.
- *
- * Author: Karol Trzcinski <karolx.trzcinski@linux.intel.com>
- */
-
-#ifndef __SOF_COMPILER_ATTRIBUTES_H__
-#define __SOF_COMPILER_ATTRIBUTES_H__
-
-#define __sparse_cache
-#define __sparse_force
-
-#ifndef __packed
-#define __packed __attribute__((packed))
-#endif
-
-#ifndef __unused
-#define __unused __attribute__((unused))
-#endif
-
-#ifndef __maybe_unused
-#define __maybe_unused __attribute__((unused))
-#endif
-
-#ifndef __aligned
-#define __aligned(x) __attribute__((__aligned__(x)))
-#endif
-
-#ifndef __section
-#define __section(x) __attribute__((section(x)))
-#endif
-
-/* The fallthrough attribute is supported since GCC 7.0
- * and Clang 10.0.0.
- *
- * Note that Clang sets __GNUC__ == 4 so the GCC version
- * test will not be true here, and must go through
- * the Clang version test.
- */
-#if ((defined(__GNUC__) && (__GNUC__ >= 7)) || \
-     (defined(__clang__) && (__clang_major__ >= 10))) && !defined(__CHECKER__)
-#define COMPILER_FALLTHROUGH __attribute__((fallthrough))
-#else
-#define COMPILER_FALLTHROUGH  /* fallthrough */
-#endif
-
-#endif /* __SOF_COMPILER_ATTRIBUTES_H__ */
diff --git a/zephyr/CMakeLists.txt b/zephyr/CMakeLists.txt
index 48cf07b0b89a..0e5e9749b26b 100644
--- a/zephyr/CMakeLists.txt
+++ b/zephyr/CMakeLists.txt
@@ -67,7 +67,6 @@ function(sof_llext_build module)
 	endif()
 
 	target_include_directories(${module}_llext_lib PRIVATE
-		"${SOF_BASE}/xtos/include"
 		"${SOF_BASE}/src/include"
 		"${SOF_BASE}/tools/rimage/src/include"
 	)
@@ -248,11 +247,6 @@ add_subdirectory(test/)
 # Intel TGL and CAVS 2.5 platforms
 if (CONFIG_SOC_SERIES_INTEL_CAVS_V25)
 
-	# Driver sources
-	zephyr_library_sources_ifdef(CONFIG_INTEL_HDA
-		${SOF_DRIVERS_PATH}/intel/hda/hda-dma.c
-	)
-
 	# Platform sources
 	zephyr_library_sources(
 		${SOF_PLATFORM_PATH}/intel/cavs/platform.c
@@ -298,10 +292,6 @@ if (CONFIG_SOC_SERIES_INTEL_ADSP_ACE)
 		lib/regions_mm.c
 	)
 
-	zephyr_library_sources_ifdef(CONFIG_CAVS_LPS
-		${SOF_PLATFORM_PATH}/intel/ace/lps_wait.c
-	)
-
 	zephyr_library_sources_ifdef(CONFIG_LL_WATCHDOG
 		${SOF_PLATFORM_PATH}/intel/ace/lib/watchdog.c
 	)
@@ -608,10 +598,6 @@ endif()
 
 # Optional SOF sources - depends on Kconfig - WIP
 
-zephyr_library_sources_ifdef(CONFIG_DW_DMA
-	${SOF_DRIVERS_PATH}/dw/dma.c
-)
-
 zephyr_library_sources_ifdef(CONFIG_SOF_BOOT_TEST
        boot_test.c
 )
diff --git a/xtos/include/rtos/interrupt.h b/zephyr/include/rtos/interrupt-legacy.h
similarity index 100%
rename from xtos/include/rtos/interrupt.h
rename to zephyr/include/rtos/interrupt-legacy.h
diff --git a/zephyr/include/rtos/interrupt.h b/zephyr/include/rtos/interrupt.h
index 200d36e4751e..6be9e55ee3c2 100644
--- a/zephyr/include/rtos/interrupt.h
+++ b/zephyr/include/rtos/interrupt.h
@@ -13,7 +13,7 @@
  */
 #if defined(CONFIG_AMD) && !defined(CONFIG_ZEPHYR_NATIVE_DRIVERS)
 /* imx currently has no IRQ driver in Zephyr so we force to xtos IRQ */
-#include "../../../xtos/include/rtos/interrupt.h"
+#include <rtos/interrupt-legacy.h>
 #else
 
 #include <zephyr/device.h>