diff --git a/apps/riscv-tests/isa/rv64uv/vsmul.c b/apps/riscv-tests/isa/rv64uv/vsmul.c
index 0b97f2d4e..e052484d8 100644
--- a/apps/riscv-tests/isa/rv64uv/vsmul.c
+++ b/apps/riscv-tests/isa/rv64uv/vsmul.c
@@ -47,6 +47,86 @@ void TEST_CASE4() {
   VCMP_I8(4, v1, 54, 0, -22);
 }
 
+void TEST_CASE5() {
+  VSET(4, e16, m1);
+  VLOAD_16(v2, 15, 15, -15, -15);
+  VLOAD_16(v3, 0x4000, 0x2000, 0x4000, 0x2000);
+  __asm__ volatile("csrw vxrm, 2");
+  __asm__ volatile("vsmul.vv v1, v2, v3");
+  VCMP_I16(5, v1, 7, 3, -8, -4);
+}
+
+void TEST_CASE6() {
+  VSET(4, e16, m1);
+  VLOAD_16(v2, 15, 15, -15, -15);
+  VLOAD_16(v3, 0x4000, 0x2000, 0x4000, 0x2000);
+  VLOAD_16(v0, 5, 0, 0, 0);
+  VCLEAR(v1);
+  __asm__ volatile("csrw vxrm, 2");
+  __asm__ volatile("vsmul.vv v1, v2, v3, v0.t");
+  VCMP_I16(6, v1, 7, 0, -8, 0);
+}
+
+void TEST_CASE7() {
+  VSET(4, e16, m1);
+  VLOAD_16(v2, 99, 15, -99, -15);
+  int16_t scalar = 0x2000;
+  __asm__ volatile("csrw vxrm, 2");
+  __asm__ volatile("vsmul.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_I16(7, v1, 24, 3, -25, -4);
+}
+
+void TEST_CASE8() {
+  VSET(4, e16, m1);
+  VLOAD_16(v2, 99, 15, -99, -15);
+  int16_t scalar = 0x2000;
+  VLOAD_16(v0, 5, 0, 0, 0);
+  VCLEAR(v1);
+  __asm__ volatile("csrw vxrm, 2");
+  __asm__ volatile("vsmul.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_I16(8, v1, 24, 0, -25, 0);
+}
+
+void TEST_CASE9() {
+  VSET(4, e32, m1);
+  VLOAD_32(v2, 15, 15, -15, -15);
+  VLOAD_32(v3, 0x4000 << 16, 0x2000 << 16, 0x4000 << 16, 0x2000 << 16);
+  __asm__ volatile("csrw vxrm, 2");
+  __asm__ volatile("vsmul.vv v1, v2, v3");
+  VCMP_I32(9, v1, 7, 3, -8, -4);
+}
+
+void TEST_CASE10() {
+  VSET(4, e32, m1);
+  VLOAD_32(v2, 15, 15, -15, -15);
+  VLOAD_32(v3, 0x4000 << 16, 0x2000 << 16, 0x4000 << 16, 0x2000 << 16);
+  VLOAD_32(v0, 5, 0, 0, 0);
+  VCLEAR(v1);
+  __asm__ volatile("csrw vxrm, 2");
+  __asm__ volatile("vsmul.vv v1, v2, v3, v0.t");
+  VCMP_I32(10, v1, 7, 0, -8, 0);
+}
+
+void TEST_CASE11() {
+  VSET(4, e32, m1);
+  VLOAD_32(v2, 99, 15, -99, -15);
+  int32_t scalar = 0x2000 << 16;
+  __asm__ volatile("csrw vxrm, 2");
+  __asm__ volatile("vsmul.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_I32(11, v1, 24, 3, -25, -4);
+}
+
+void TEST_CASE12() {
+  VSET(4, e32, m1);
+  VLOAD_32(v2, 99, 15, -99, -15);
+  int32_t scalar = 0x2000 << 16;
+  VLOAD_32(v0, 5, 0, 0, 0);
+  VCLEAR(v1);
+  __asm__ volatile("csrw vxrm, 2");
+  __asm__ volatile("vsmul.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_I32(12, v1, 24, 0, -25, 0);
+}
+
 int main(void) {
   INIT_CHECK();
   enable_vec();
@@ -55,5 +135,13 @@ int main(void) {
   TEST_CASE2();
   TEST_CASE3();
   TEST_CASE4();
+  TEST_CASE5();
+  TEST_CASE6();
+  TEST_CASE7();
+  TEST_CASE8();
+  TEST_CASE9();
+  TEST_CASE10();
+  TEST_CASE11();
+  TEST_CASE12();
   EXIT_CHECK();
-}
\ No newline at end of file
+}
diff --git a/hardware/src/lane/simd_mul.sv b/hardware/src/lane/simd_mul.sv
index 34de5630f..2a2228d39 100644
--- a/hardware/src/lane/simd_mul.sv
+++ b/hardware/src/lane/simd_mul.sv
@@ -255,7 +255,7 @@ module simd_mul import ara_pkg::*; import rvv_pkg::*; #(
             2'b10: r ='0;
             2'b11: for (int b=0; b<4; b++) r[b] = !mul_res.w32[b][15] & (mul_res.w32[b][14:0] != '0);
           endcase
-          for (int l = 0; l < 4; l++) result_o[16*l +: 16] = (op == VSMUL) ? (mul_res.w32[l] >> 16) + r[l] : mul_res.w32[l][15:0];
+          for (int l = 0; l < 4; l++) result_o[16*l +: 16] = (op == VSMUL) ? (mul_res.w32[l] >> 15) + r[l] : mul_res.w32[l][15:0];
         end
         VMULH,
         VMULHU,