From 735e7c86934e2b5ad5d04f72e6ad55f4b8402286 Mon Sep 17 00:00:00 2001 From: Johannes Pfau Date: Mon, 3 Aug 2026 15:44:34 +0200 Subject: [PATCH 01/48] Don't hardcode ETH toolchain for bootrom compilation The riscv command is not available when building the toolchain using make toolchain. --- Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Makefile b/Makefile index ef4beab..2f588f7 100644 --- a/Makefile +++ b/Makefile @@ -162,7 +162,7 @@ $(SNRT_BOOTINFO_H): $(SCRIPTS_DIR)/generate_bootdata.py $(HJSON_OUT) $(BOOTROM_D $(BOOTROM_DIR)/bootrom.elf $(BOOTROM_DIR)/bootrom.dump $(BOOTROM_DIR)/bootrom.bin: \ $(BOOTROM_DIR)/bootrom.S $(BOOTROM_DIR)/bootdata_bootrom.cc $(BOOTROM_DIR)/bootrom.ld $(SNRT_BOOTINFO_H) - riscv -riscv64-gcc-9.5.0 riscv64-unknown-elf-gcc \ + $(GCC_INSTALL_DIR)/bin/riscv32-unknown-elf-gcc \ -mabi=ilp32 -march=rv32imaf -static -nostartfiles \ -T$(BOOTROM_DIR)/bootrom.ld \ $(BOOTROM_DIR)/bootrom.S \ @@ -170,8 +170,8 @@ $(BOOTROM_DIR)/bootrom.elf $(BOOTROM_DIR)/bootrom.dump $(BOOTROM_DIR)/bootrom.bi -I$(SPATZ_DIR)/hw/ip/snitch_test/src \ -I$(SOFTWARE_DIR)/snRuntime/include \ -o $(BOOTROM_DIR)/bootrom.elf - riscv -riscv64-gcc-9.5.0 riscv64-unknown-elf-objdump -D $(BOOTROM_DIR)/bootrom.elf > $(BOOTROM_DIR)/bootrom.dump - riscv -riscv64-gcc-9.5.0 riscv64-unknown-elf-objcopy -O binary $(BOOTROM_DIR)/bootrom.elf $(BOOTROM_DIR)/bootrom.bin + $(GCC_INSTALL_DIR)/bin/riscv32-unknown-elf-objdump -D $(BOOTROM_DIR)/bootrom.elf > $(BOOTROM_DIR)/bootrom.dump + $(GCC_INSTALL_DIR)/bin/riscv32-unknown-elf-objcopy -O binary $(BOOTROM_DIR)/bootrom.elf $(BOOTROM_DIR)/bootrom.bin $(BOOTROM_DIR)/bootrom.sv: $(BOOTROM_DIR)/bootrom.bin $(BOOTROM_DIR)/bootdata.cc ${PYTHON} $(SCRIPTS_DIR)/generate_bootrom.py \ From dd9c92cfaba61f953768145bff1b6e3464011e0e Mon Sep 17 00:00:00 2001 From: Zexin Fu Date: Tue, 9 Jun 2026 04:41:15 +0200 Subject: [PATCH 02/48] [RTL] cachepool_tile: bank_we/bank_req as direct OR-reduce off the skew-part cascade (shorten data-bank we path tail) --- hardware/src/cachepool_tile.sv | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/hardware/src/cachepool_tile.sv b/hardware/src/cachepool_tile.sv index fde9682..8658ffa 100644 --- a/hardware/src/cachepool_tile.sv +++ b/hardware/src/cachepool_tile.sv @@ -1299,8 +1299,14 @@ module cachepool_tile automatic logic sel_found; automatic int unsigned sel_part_idx; - bank_req[col][bank_sel] = 1'b0; - bank_we[col][bank_sel] = 1'b0; + // Timing (T1.1): bank_we/bank_req are value-identical to direct OR-reduces + // of the part bits (the arbiter always selects a write-part when any + // write exists, else a read-part), so compute them directly off the + // critical path tail (data-bank we -> meta-write clock-gate) instead + // of riding the priority cascade + 4:1 sel_part_idx mux. addr/wdata/ + // be still use the mux. Matches gen_unfolded_data_banks (1303-1304). + bank_we[col][bank_sel] = |part_we[col][bank_sel]; + bank_req[col][bank_sel] = (|part_we[col][bank_sel]) | (|part_req[col][bank_sel]); bank_addr[col][bank_sel] = '0; bank_wdata[col][bank_sel] = '0; bank_be[col][bank_sel] = '0; @@ -1323,8 +1329,6 @@ module cachepool_tile end if (sel_found) begin - bank_req[col][bank_sel] = 1'b1; - bank_we[col][bank_sel] = part_we[col][bank_sel][sel_part_idx]; bank_addr[col][bank_sel] = part_addr[col][bank_sel][sel_part_idx]; bank_wdata[col][bank_sel] = part_wdata[col][bank_sel][sel_part_idx]; bank_be[col][bank_sel] = part_be[col][bank_sel][sel_part_idx]; From d502c980ee701c26ef196aeeb476fbab7ad854e4 Mon Sep 17 00:00:00 2001 From: Zexin Fu Date: Mon, 24 Aug 2026 22:30:44 +0200 Subject: [PATCH 03/48] rlc: multi-user RLC kernel with use-case switching Brings the packet-assembly restructuring and the multi-user extension onto the multi-group kernel, keeping this branch's explicit producer/consumer core lists as the dispatch mechanism. Restructuring (originally from PR #12, Huawei): rlc_send_pkt / ue_status_rpt / pkt_production_and_recycle split out of the consumer loop, per-packet TestDataStru, DFX counters, rate pacing. Multi-user: One rlc_context_t per UE (rlc_ctx[NUM_USERS], sized from the data header's ACTIVE_USER_NUMBER), per-user list locks and per-user SN/ACK state. Producers route each PDCP package to rlc_ctx[user_id]; consumers own a static subset of the entities. NUM_USERS == 1 reduces to the single-entity kernel. Fitted to the core lists rather than replacing them: - a consumer's share of the entities follows its index in consumer_core_ids[], not core_id - PRODUCER_CORE_NUM, so the roles need not be contiguous; - the UE status task runs on producer_core_ids[0] instead of core 0, which need not be a producer; - producers_finished is dropped: producer_done is already the count of producers that have finished. Also: DATAHEADER now actually reaches rlc.c (a hard-coded include shadowed it, so every K-variant compiled the same dataset); the generator emits ACTIVE_USER_NUMBER and a 4-byte-aligned PDU_STRIDE (needed for 810 B PDUs, whose slots would otherwise be misaligned for the vector copies); pacing overflow fixed behind RLC_ENABLE_PACING (default off); optional payload self-check behind RLC_SELF_CHECK. Co-authored-by: zouguoqi --- .../data/data_1_1350_10.h | 6 +- .../data/data_1_1350_100.h | 6 +- .../data/data_1_1350_300.h | 6 +- .../data/data_48_800_1000.h | 2051 +++++++++++++++++ .../data/data_48_800_300.h | 651 ++++++ .../kernel/llist.h | 6 +- .../kernel/mm.h | 5 +- .../kernel/rlc.c | 615 +++-- .../kernel/rlc.h | 89 +- .../main.c | 24 +- .../script/generate_pdcp_pkg.py | 20 +- .../script/pdcp_pkg_48_800_1000.json | 18 + .../script/pdcp_pkg_48_800_300.json | 18 + 13 files changed, 3286 insertions(+), 229 deletions(-) create mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/data/data_48_800_1000.h create mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/data/data_48_800_300.h create mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_48_800_1000.json create mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_48_800_300.json diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/data/data_1_1350_10.h b/software/rlc/multi_producer_single_consumer_double_linked_list/data/data_1_1350_10.h index 77e9288..2c2de1f 100644 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/data/data_1_1350_10.h +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/data/data_1_1350_10.h @@ -20,6 +20,8 @@ #ifndef PDCP_PKG_H #define PDCP_PKG_H +#include + typedef struct { int user_id; unsigned int src_addr; @@ -29,7 +31,9 @@ typedef struct { #define NUM_SRC_SLOTS 12336 #define PDU_SIZE 1360 +#define PDU_STRIDE 1360 #define NUM_PKGS 10 +#define ACTIVE_USER_NUMBER 1 #define NUM_PRODUCER_CORES 2 static const unsigned int producer_core_ids[NUM_PRODUCER_CORES] = {0, 1}; @@ -51,7 +55,7 @@ static const pdcp_pkg_t __attribute__((section(".pdcp_info"), used)) pdcp_pkgs[N { 0, 0xA022D7B0, 0xB022D7B0, 1360 }, }; -static const uint8_t __attribute__((section(".pdcp_src"), used)) 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a/software/rlc/multi_producer_single_consumer_double_linked_list/data/data_1_1350_100.h +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/data/data_1_1350_100.h @@ -20,6 +20,8 @@ #ifndef PDCP_PKG_H #define PDCP_PKG_H +#include + typedef struct { int user_id; unsigned int src_addr; @@ -29,7 +31,9 @@ typedef struct { #define NUM_SRC_SLOTS 12336 #define PDU_SIZE 1360 +#define PDU_STRIDE 1360 #define NUM_PKGS 100 +#define ACTIVE_USER_NUMBER 1 #define NUM_PRODUCER_CORES 2 static const unsigned int producer_core_ids[NUM_PRODUCER_CORES] = {0, 1}; @@ -141,7 +145,7 @@ static const pdcp_pkg_t __attribute__((section(".pdcp_info"), used)) pdcp_pkgs[N { 0, 0xA05BC3E0, 0xB05BC3E0, 1360 }, }; -static const uint8_t __attribute__((section(".pdcp_src"), used)) pdcp_src_data[NUM_SRC_SLOTS][PDU_SIZE] = { +static const uint8_t __attribute__((section(".pdcp_src"), used)) pdcp_src_data[NUM_SRC_SLOTS][PDU_STRIDE] = { [106] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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+#include + typedef struct { int user_id; unsigned int src_addr; @@ -29,7 +31,9 @@ typedef struct { #define NUM_SRC_SLOTS 12336 #define PDU_SIZE 1360 +#define PDU_STRIDE 1360 #define NUM_PKGS 300 +#define ACTIVE_USER_NUMBER 1 #define NUM_PRODUCER_CORES 2 static const unsigned int producer_core_ids[NUM_PRODUCER_CORES] = {0, 1}; @@ -341,7 +345,7 @@ static const pdcp_pkg_t __attribute__((section(".pdcp_info"), used)) pdcp_pkgs[N { 0, 0xA0BB1980, 0xB0BB1980, 1360 }, }; -static const uint8_t __attribute__((section(".pdcp_src"), used)) pdcp_src_data[NUM_SRC_SLOTS][PDU_SIZE] = { +static const uint8_t __attribute__((section(".pdcp_src"), used)) pdcp_src_data[NUM_SRC_SLOTS][PDU_STRIDE] = { [9] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, 0x30, 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0x7F, 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F, 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF }, diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/data/data_48_800_1000.h b/software/rlc/multi_producer_single_consumer_double_linked_list/data/data_48_800_1000.h new file mode 100644 index 0000000..63dec64 --- /dev/null +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/data/data_48_800_1000.h @@ -0,0 +1,2051 @@ + +// Copyright 2025 ETH Zurich and University of Bologna. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// Author: Zexin Fu + +#ifndef PDCP_PKG_H +#define PDCP_PKG_H + +#include + +typedef struct { + int user_id; + unsigned int src_addr; + unsigned int tgt_addr; + unsigned int pkg_length; +} pdcp_pkg_t; + +#define NUM_SRC_SLOTS 20661 +#define PDU_SIZE 810 +#define PDU_STRIDE 812 +#define NUM_PKGS 1000 +#define ACTIVE_USER_NUMBER 48 + +#define NUM_PRODUCER_CORES 2 +static const unsigned int producer_core_ids[NUM_PRODUCER_CORES] = {0, 1}; +#define NUM_CONSUMER_CORES 2 +static const unsigned int consumer_core_ids[NUM_CONSUMER_CORES] = {2, 3}; +#define NUM_RLC_KERNEL_CORES (NUM_PRODUCER_CORES + NUM_CONSUMER_CORES) +static const unsigned int rlc_kernel_core_ids[NUM_RLC_KERNEL_CORES] = {0, 1, 2, 3}; + +static const pdcp_pkg_t __attribute__((section(".pdcp_info"), used)) pdcp_pkgs[NUM_PKGS] = { + { 34, 0xA02D3300, 0xB02D3300, 810 }, + { 24, 0xA00A25C4, 0xB00A25C4, 810 }, + { 29, 0xA06FA8F0, 0xB06FA8F0, 810 }, + { 20, 0xA0636B20, 0xB0636B20, 810 }, + { 12, 0xA05A9F18, 0xB05A9F18, 810 }, + { 44, 0xA038A5D0, 0xB038A5D0, 810 }, + { 15, 0xA0299B28, 0xB0299B28, 810 }, + { 36, 0xA0DD6968, 0xB0DD6968, 810 }, + { 24, 0xA0234980, 0xB0234980, 810 }, + { 14, 0xA0EFBC9C, 0xB0EFBC9C, 810 }, + { 26, 0xA0AB4B2C, 0xB0AB4B2C, 810 }, + { 2, 0xA00CE5EC, 0xB00CE5EC, 810 }, + { 20, 0xA00C17C0, 0xB00C17C0, 810 }, + { 47, 0xA02609A8, 0xB02609A8, 810 }, + { 30, 0xA058C350, 0xB058C350, 810 }, + { 45, 0xA05E7334, 0xB05E7334, 810 }, + { 24, 0xA0CD2B14, 0xB0CD2B14, 810 }, + { 24, 0xA0F46868, 0xB0F46868, 810 }, + { 42, 0xA00AC45C, 0xB00AC45C, 810 }, + { 41, 0xA0E3DAC8, 0xB0E3DAC8, 810 }, + { 9, 0xA050B8C4, 0xB050B8C4, 810 }, + { 31, 0xA0DD3D00, 0xB0DD3D00, 810 }, + { 2, 0xA0AA5098, 0xB0AA5098, 810 }, + { 8, 0xA0597E74, 0xB0597E74, 810 }, + { 32, 0xA0B65ED4, 0xB0B65ED4, 810 }, + { 37, 0xA0EF3DBC, 0xB0EF3DBC, 810 }, + { 21, 0xA070EFA4, 0xB070EFA4, 810 }, + { 6, 0xA002A070, 0xB002A070, 810 }, + { 28, 0xA040D014, 0xB040D014, 810 }, + { 6, 0xA0AB9420, 0xB0AB9420, 810 }, + { 33, 0xA08A233C, 0xB08A233C, 810 }, + { 29, 0xA070CFEC, 0xB070CFEC, 810 }, + { 0, 0xA03F1D88, 0xB03F1D88, 810 }, + { 46, 0xA0576994, 0xB0576994, 810 }, + { 9, 0xA088A69C, 0xB088A69C, 810 }, + { 26, 0xA0297E9C, 0xB0297E9C, 810 }, + { 41, 0xA025A754, 0xB025A754, 810 }, + { 9, 0xA09A3EAC, 0xB09A3EAC, 810 }, + { 4, 0xA02743AC, 0xB02743AC, 810 }, + { 30, 0xA091BEC4, 0xB091BEC4, 810 }, + { 16, 0xA08BA308, 0xB08BA308, 810 }, + { 21, 0xA0F51A08, 0xB0F51A08, 810 }, + { 39, 0xA06B62A4, 0xB06B62A4, 810 }, + { 44, 0xA011A194, 0xB011A194, 810 }, + { 25, 0xA0BA8568, 0xB0BA8568, 810 }, + { 41, 0xA0D9B504, 0xB0D9B504, 810 }, + { 5, 0xA032ACF8, 0xB032ACF8, 810 }, + { 21, 0xA099ACC4, 0xB099ACC4, 810 }, + { 43, 0xA01FFDC8, 0xB01FFDC8, 810 }, + { 34, 0xA0E0200C, 0xB0E0200C, 810 }, + { 24, 0xA0770508, 0xB0770508, 810 }, + { 20, 0xA0FF3974, 0xB0FF3974, 810 }, + { 40, 0xA0FB1C64, 0xB0FB1C64, 810 }, + { 45, 0xA092D2B8, 0xB092D2B8, 810 }, + { 31, 0xA0EA6588, 0xB0EA6588, 810 }, + { 34, 0xA04E0ED0, 0xB04E0ED0, 810 }, + { 2, 0xA01C3CB4, 0xB01C3CB4, 810 }, + { 39, 0xA01298FC, 0xB01298FC, 810 }, + { 4, 0xA05C8464, 0xB05C8464, 810 }, + { 15, 0xA0757BB8, 0xB0757BB8, 810 }, + { 40, 0xA0206348, 0xB0206348, 810 }, + { 43, 0xA05E8310, 0xB05E8310, 810 }, + { 18, 0xA028FFBC, 0xB028FFBC, 810 }, + { 14, 0xA09A51B4, 0xB09A51B4, 810 }, + { 47, 0xA070D970, 0xB070D970, 810 }, + { 5, 0xA0B8148C, 0xB0B8148C, 810 }, + { 27, 0xA0941C98, 0xB0941C98, 810 }, + { 6, 0xA04206EC, 0xB04206EC, 810 }, + { 40, 0xA0964AD8, 0xB0964AD8, 810 }, + { 45, 0xA0903BCC, 0xB0903BCC, 810 }, + { 6, 0xA0550EEC, 0xB0550EEC, 810 }, + { 28, 0xA06C6390, 0xB06C6390, 810 }, + { 10, 0xA01CFB04, 0xB01CFB04, 810 }, + { 44, 0xA0F74EA0, 0xB0F74EA0, 810 }, + { 19, 0xA04578B4, 0xB04578B4, 810 }, + { 1, 0xA0D8DA28, 0xB0D8DA28, 810 }, + { 2, 0xA063619C, 0xB063619C, 810 }, + { 20, 0xA0425638, 0xB0425638, 810 }, + { 3, 0xA0BBAC64, 0xB0BBAC64, 810 }, + { 18, 0xA09A0BEC, 0xB09A0BEC, 810 }, + { 22, 0xA06D973C, 0xB06D973C, 810 }, + { 23, 0xA0E21EB8, 0xB0E21EB8, 810 }, + { 27, 0xA05928D0, 0xB05928D0, 810 }, + { 9, 0xA083A858, 0xB083A858, 810 }, + { 15, 0xA016B2E0, 0xB016B2E0, 810 }, + { 33, 0xA05CFCEC, 0xB05CFCEC, 810 }, + { 26, 0xA00D05A4, 0xB00D05A4, 810 }, + { 36, 0xA0801080, 0xB0801080, 810 }, + { 43, 0xA0A2DE4C, 0xB0A2DE4C, 810 }, + { 11, 0xA06CB2DC, 0xB06CB2DC, 810 }, + { 10, 0xA01ADCA0, 0xB01ADCA0, 810 }, + { 11, 0xA055A72C, 0xB055A72C, 810 }, + { 5, 0xA0E6454C, 0xB0E6454C, 810 }, + { 39, 0xA07FC134, 0xB07FC134, 810 }, + { 24, 0xA0565274, 0xB0565274, 810 }, + { 39, 0xA0CAAD88, 0xB0CAAD88, 810 }, + { 43, 0xA0A0A030, 0xB0A0A030, 810 }, + { 15, 0xA0BA4924, 0xB0BA4924, 810 }, + { 31, 0xA039FF8C, 0xB039FF8C, 810 }, + { 37, 0xA06B88B4, 0xB06B88B4, 810 }, + { 9, 0xA038AF54, 0xB038AF54, 810 }, + { 14, 0xA0641FEC, 0xB0641FEC, 810 }, + { 29, 0xA0E3E778, 0xB0E3E778, 810 }, + { 40, 0xA0DAD27C, 0xB0DAD27C, 810 }, + { 16, 0xA06AAAAC, 0xB06AAAAC, 810 }, + { 29, 0xA0ED5544, 0xB0ED5544, 810 }, + { 16, 0xA0ADEEC8, 0xB0ADEEC8, 810 }, + { 42, 0xA0ECE96C, 0xB0ECE96C, 810 }, + { 0, 0xA0A22654, 0xB0A22654, 810 }, + { 29, 0xA092F59C, 0xB092F59C, 810 }, + { 18, 0xA0590918, 0xB0590918, 810 }, + { 43, 0xA03826F0, 0xB03826F0, 810 }, + { 34, 0xA0CEDDA0, 0xB0CEDDA0, 810 }, + { 10, 0xA0C85C64, 0xB0C85C64, 810 }, + { 4, 0xA024E5D8, 0xB024E5D8, 810 }, + { 28, 0xA0131E34, 0xB0131E34, 810 }, + { 22, 0xA02C8160, 0xB02C8160, 810 }, + { 37, 0xA03E0CC0, 0xB03E0CC0, 810 }, + { 19, 0xA0FEBDC0, 0xB0FEBDC0, 810 }, + { 40, 0xA040F2F8, 0xB040F2F8, 810 }, + { 27, 0xA0AB648C, 0xB0AB648C, 810 }, + { 44, 0xA0F223F4, 0xB0F223F4, 810 }, + { 16, 0xA019C8AC, 0xB019C8AC, 810 }, + { 29, 0xA09C3700, 0xB09C3700, 810 }, + { 19, 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0xA077740C, 0xB077740C, 810 }, + { 41, 0xA059F6FC, 0xB059F6FC, 810 }, + { 21, 0xA0A42E84, 0xB0A42E84, 810 }, + { 8, 0xA062C630, 0xB062C630, 810 }, + { 42, 0xA07C4F6C, 0xB07C4F6C, 810 }, + { 44, 0xA0EC1B40, 0xB0EC1B40, 810 }, + { 47, 0xA095D250, 0xB095D250, 810 }, + { 43, 0xA0C02244, 0xB0C02244, 810 }, + { 33, 0xA0E0B520, 0xB0E0B520, 810 }, + { 5, 0xA0D78D1C, 0xB0D78D1C, 810 }, + { 41, 0xA08B9000, 0xB08B9000, 810 }, + { 42, 0xA0ACBE48, 0xB0ACBE48, 810 }, + { 27, 0xA0DF74C4, 0xB0DF74C4, 810 }, + { 32, 0xA0864BF4, 0xB0864BF4, 810 }, + { 23, 0xA08ED560, 0xB08ED560, 810 }, + { 1, 0xA0B83770, 0xB0B83770, 810 }, + { 23, 0xA06DFCBC, 0xB06DFCBC, 810 }, + { 19, 0xA07C7BD4, 0xB07C7BD4, 810 }, + { 11, 0xA0660EBC, 0xB0660EBC, 810 }, + { 13, 0xA05D9858, 0xB05D9858, 810 }, + { 21, 0xA030FA6C, 0xB030FA6C, 810 }, + { 31, 0xA04E2E88, 0xB04E2E88, 810 }, + { 12, 0xA0801A04, 0xB0801A04, 810 }, + { 14, 0xA030883C, 0xB030883C, 810 }, + { 8, 0xA0D98EF4, 0xB0D98EF4, 810 }, + { 9, 0xA04B2898, 0xB04B2898, 810 }, + { 4, 0xA04DC2B0, 0xB04DC2B0, 810 }, + { 18, 0xA057D898, 0xB057D898, 810 }, + { 6, 0xA0C494F8, 0xB0C494F8, 810 }, + { 32, 0xA0704130, 0xB0704130, 810 }, + { 34, 0xA0EF5D74, 0xB0EF5D74, 810 }, + { 47, 0xA0D4FFB4, 0xB0D4FFB4, 810 }, + { 33, 0xA0F24A04, 0xB0F24A04, 810 }, + { 2, 0xA072E4CC, 0xB072E4CC, 810 }, + { 42, 0xA028D028, 0xB028D028, 810 }, + { 21, 0xA04ECD20, 0xB04ECD20, 810 }, + { 39, 0xA0784564, 0xB0784564, 810 }, + { 8, 0xA05C5B28, 0xB05C5B28, 810 }, + { 38, 0xA092836C, 0xB092836C, 810 }, + { 24, 0xA048D774, 0xB048D774, 810 }, + { 9, 0xA07AB640, 0xB07AB640, 810 }, + { 10, 0xA005BC94, 0xB005BC94, 810 }, + { 11, 0xA03361C4, 0xB03361C4, 810 }, + { 44, 0xA06F5CD0, 0xB06F5CD0, 810 }, + { 39, 0xA0127944, 0xB0127944, 810 }, + { 10, 0xA01620F8, 0xB01620F8, 810 }, + { 46, 0xA0E0A870, 0xB0E0A870, 810 }, + { 28, 0xA0769930, 0xB0769930, 810 }, + { 2, 0xA033420C, 0xB033420C, 810 }, + { 26, 0xA0C74B9C, 0xB0C74B9C, 810 }, + { 23, 0xA029A4AC, 0xB029A4AC, 810 }, + { 43, 0xA004F7EC, 0xB004F7EC, 810 }, + { 46, 0xA0E90EF8, 0xB0E90EF8, 810 }, + { 15, 0xA073705C, 0xB073705C, 810 }, + { 28, 0xA0BE929C, 0xB0BE929C, 810 }, + { 39, 0xA0C25A08, 0xB0C25A08, 810 }, + { 18, 0xA0B2D3AC, 0xB0B2D3AC, 810 }, + { 47, 0xA08A52D0, 0xB08A52D0, 810 }, + { 28, 0xA04AD94C, 0xB04AD94C, 810 }, + { 14, 0xA014DA44, 0xB014DA44, 810 }, + { 34, 0xA06680EC, 0xB06680EC, 810 }, + { 15, 0xA0C1F488, 0xB0C1F488, 810 }, + { 19, 0xA02E5078, 0xB02E5078, 810 }, + { 30, 0xA01A86FC, 0xB01A86FC, 810 }, + { 12, 0xA0A2AEB8, 0xB0A2AEB8, 810 }, + { 23, 0xA0C7A46C, 0xB0C7A46C, 810 }, + { 43, 0xA01E1224, 0xB01E1224, 810 }, + { 36, 0xA0EA42A4, 0xB0EA42A4, 810 }, + { 28, 0xA0FF8BEC, 0xB0FF8BEC, 810 }, + { 29, 0xA015C1D0, 0xB015C1D0, 810 }, + { 18, 0xA03D9764, 0xB03D9764, 810 }, + { 24, 0xA03C9020, 0xB03C9020, 810 }, + { 32, 0xA0E482E4, 0xB0E482E4, 810 }, + { 33, 0xA07B5B30, 0xB07B5B30, 810 }, + { 26, 0xA02294B4, 0xB02294B4, 810 }, + { 10, 0xA064C1B0, 0xB064C1B0, 810 }, + { 12, 0xA030160C, 0xB030160C, 810 }, + { 38, 0xA0E290E8, 0xB0E290E8, 810 }, + { 8, 0xA0A8F6DC, 0xB0A8F6DC, 810 }, + { 16, 0xA0F627A4, 0xB0F627A4, 810 }, + { 3, 0xA0F2043C, 0xB0F2043C, 810 }, + { 41, 0xA0FB12E0, 0xB0FB12E0, 810 }, + { 30, 0xA05BA004, 0xB05BA004, 810 }, + { 23, 0xA0D42804, 0xB0D42804, 810 }, + { 35, 0xA0B6E738, 0xB0B6E738, 810 }, + { 6, 0xA0B3BE64, 0xB0B3BE64, 810 }, + { 45, 0xA078B794, 0xB078B794, 810 }, + { 33, 0xA0EEEE70, 0xB0EEEE70, 810 }, + { 7, 0xA0AE1804, 0xB0AE1804, 810 }, + { 18, 0xA07BF9C8, 0xB07BF9C8, 810 }, + { 5, 0xA0E6DA60, 0xB0E6DA60, 810 }, + { 10, 0xA0FC207C, 0xB0FC207C, 810 }, + { 17, 0xA018721C, 0xB018721C, 810 }, + { 28, 0xA0F78160, 0xB0F78160, 810 }, + { 32, 0xA02847C4, 0xB02847C4, 810 }, + { 9, 0xA0545A20, 0xB0545A20, 810 }, + { 27, 0xA0FDF2C0, 0xB0FDF2C0, 810 }, + { 5, 0xA055AA58, 0xB055AA58, 810 }, + { 14, 0xA06B6F54, 0xB06B6F54, 810 }, + { 28, 0xA020F530, 0xB020F530, 810 }, + { 22, 0xA03FC278, 0xB03FC278, 810 }, + { 1, 0xA0615FC4, 0xB0615FC4, 810 }, + { 26, 0xA0468FD4, 0xB0468FD4, 810 }, + { 3, 0xA0E019B4, 0xB0E019B4, 810 }, + { 25, 0xA01E77A4, 0xB01E77A4, 810 }, + { 32, 0xA03F8C8C, 0xB03F8C8C, 810 }, + { 23, 0xA00113F4, 0xB00113F4, 810 }, + { 15, 0xA0A5DAB8, 0xB0A5DAB8, 810 }, + { 24, 0xA0F11658, 0xB0F11658, 810 }, + { 5, 0xA0BEC888, 0xB0BEC888, 810 }, + { 23, 0xA0763D34, 0xB0763D34, 810 }, + { 14, 0xA00D3EBC, 0xB00D3EBC, 810 }, + { 1, 0xA05DFAAC, 0xB05DFAAC, 810 }, + { 20, 0xA074F680, 0xB074F680, 810 }, + { 6, 0xA072C840, 0xB072C840, 810 }, + { 45, 0xA0B853FC, 0xB0B853FC, 810 }, + { 41, 0xA01CE4D0, 0xB01CE4D0, 810 }, + { 21, 0xA05EC280, 0xB05EC280, 810 }, + { 9, 0xA06B65D0, 0xB06B65D0, 810 }, + { 8, 0xA0FDC32C, 0xB0FDC32C, 810 }, + { 2, 0xA0EF73A8, 0xB0EF73A8, 810 }, + { 18, 0xA0505018, 0xB0505018, 810 }, + { 30, 0xA0AC9838, 0xB0AC9838, 810 }, + { 44, 0xA02E9640, 0xB02E9640, 810 }, + { 8, 0xA0DD16F0, 0xB0DD16F0, 810 }, + { 45, 0xA05B4408, 0xB05B4408, 810 }, + { 30, 0xA03C7D18, 0xB03C7D18, 810 }, + { 28, 0xA06BD800, 0xB06BD800, 810 }, + { 39, 0xA039BCF0, 0xB039BCF0, 810 }, + { 0, 0xA01835D8, 0xB01835D8, 810 }, + { 5, 0xA0435A50, 0xB0435A50, 810 }, + { 1, 0xA07CE154, 0xB07CE154, 810 }, + { 16, 0xA0E716A4, 0xB0E716A4, 810 }, + { 13, 0xA0752C6C, 0xB0752C6C, 810 }, + { 9, 0xA0B24B48, 0xB0B24B48, 810 }, + { 35, 0xA0327A38, 0xB0327A38, 810 }, + { 46, 0xA0BE49A8, 0xB0BE49A8, 810 }, + { 38, 0xA07B7490, 0xB07B7490, 810 }, + { 33, 0xA0A369DC, 0xB0A369DC, 810 }, + { 27, 0xA06E8520, 0xB06E8520, 810 }, + { 7, 0xA0CB2F94, 0xB0CB2F94, 810 }, + { 18, 0xA0DB3B28, 0xB0DB3B28, 810 }, + { 15, 0xA0C878F0, 0xB0C878F0, 810 }, + { 19, 0xA0B1B960, 0xB0B1B960, 810 }, + { 7, 0xA020A5E4, 0xB020A5E4, 810 }, + { 3, 0xA0F2CC10, 0xB0F2CC10, 810 }, + { 15, 0xA0102E78, 0xB0102E78, 810 }, + { 26, 0xA0AF6510, 0xB0AF6510, 810 }, + { 40, 0xA065A610, 0xB065A610, 810 }, + { 39, 0xA00A7E94, 0xB00A7E94, 810 }, + { 29, 0xA0251240, 0xB0251240, 810 }, + { 4, 0xA0E98780, 0xB0E98780, 810 }, + { 7, 0xA0EE5C88, 0xB0EE5C88, 810 }, + { 31, 0xA00869B4, 0xB00869B4, 810 }, + { 38, 0xA06D6AD4, 0xB06D6AD4, 810 }, + { 34, 0xA0E9F358, 0xB0E9F358, 810 }, + { 1, 0xA0105488, 0xB0105488, 810 }, + { 40, 0xA0471E90, 0xB0471E90, 810 }, + { 32, 0xA0BF04CC, 0xB0BF04CC, 810 }, + { 36, 0xA0D2B1BC, 0xB0D2B1BC, 810 }, + { 15, 0xA0B38878, 0xB0B38878, 810 }, + { 45, 0xA070EC78, 0xB070EC78, 810 }, + { 9, 0xA049AF24, 0xB049AF24, 810 }, + { 18, 0xA0EDA490, 0xB0EDA490, 810 }, + { 27, 0xA0B0F7E4, 0xB0B0F7E4, 810 }, + { 0, 0xA0C7A140, 0xB0C7A140, 810 }, + { 39, 0xA02508BC, 0xB02508BC, 810 }, + { 22, 0xA0BED20C, 0xB0BED20C, 810 }, + { 15, 0xA08D428C, 0xB08D428C, 810 }, + { 36, 0xA0A5C7B0, 0xB0A5C7B0, 810 }, + { 26, 0xA087500C, 0xB087500C, 810 }, + { 11, 0xA0825820, 0xB0825820, 810 }, + { 42, 0xA02A7604, 0xB02A7604, 810 }, + { 42, 0xA041489C, 0xB041489C, 810 }, + { 5, 0xA085E674, 0xB085E674, 810 }, + { 33, 0xA0A71E40, 0xB0A71E40, 810 }, + { 23, 0xA0C92764, 0xB0C92764, 810 }, + { 4, 0xA0750330, 0xB0750330, 810 }, + { 33, 0xA0A29558, 0xB0A29558, 810 }, + { 34, 0xA0DF550C, 0xB0DF550C, 810 }, + { 32, 0xA00EE498, 0xB00EE498, 810 }, + { 32, 0xA0B8A674, 0xB0B8A674, 810 }, + { 35, 0xA023BEDC, 0xB023BEDC, 810 }, + { 1, 0xA07FB158, 0xB07FB158, 810 }, + { 24, 0xA0667768, 0xB0667768, 810 }, + { 30, 0xA0833FAC, 0xB0833FAC, 810 }, + { 2, 0xA02F0EC8, 0xB02F0EC8, 810 }, + { 40, 0xA0A41850, 0xB0A41850, 810 }, + { 24, 0xA0D0EC28, 0xB0D0EC28, 810 }, + { 23, 0xA000755C, 0xB000755C, 810 }, + { 16, 0xA0DC48C4, 0xB0DC48C4, 810 }, + { 47, 0xA0BB8FD8, 0xB0BB8FD8, 810 }, + { 1, 0xA0A7C65C, 0xB0A7C65C, 810 }, + { 22, 0xA0160140, 0xB0160140, 810 }, + { 4, 0xA04C2658, 0xB04C2658, 810 }, + { 22, 0xA0D27BD0, 0xB0D27BD0, 810 }, + { 15, 0xA092DF68, 0xB092DF68, 810 }, + { 46, 0xA0FCC898, 0xB0FCC898, 810 }, + { 42, 0xA0CA6168, 0xB0CA6168, 810 }, + { 40, 0xA0FDE93C, 0xB0FDE93C, 810 }, + { 6, 0xA0B37570, 0xB0B37570, 810 }, + { 37, 0xA014F3A4, 0xB014F3A4, 810 }, + { 47, 0xA052A468, 0xB052A468, 810 }, + { 21, 0xA06C69E8, 0xB06C69E8, 810 }, + { 8, 0xA0DEF910, 0xB0DEF910, 810 }, + { 2, 0xA03530DC, 0xB03530DC, 810 }, + { 22, 0xA074F028, 0xB074F028, 810 }, + { 34, 0xA0B1DF70, 0xB0B1DF70, 810 }, + { 21, 0xA0C4CAE4, 0xB0C4CAE4, 810 }, + { 41, 0xA03149B8, 0xB03149B8, 810 }, + { 11, 0xA00BB56C, 0xB00BB56C, 810 }, + { 43, 0xA0FFC830, 0xB0FFC830, 810 }, + { 29, 0xA0F73214, 0xB0F73214, 810 }, + { 44, 0xA06126AC, 0xB06126AC, 810 }, + { 30, 0xA0404ADC, 0xB0404ADC, 810 }, + { 40, 0xA07E2808, 0xB07E2808, 810 }, + { 11, 0xA0DFA12C, 0xB0DFA12C, 810 }, + { 8, 0xA0058D00, 0xB0058D00, 810 }, + { 4, 0xA0E03640, 0xB0E03640, 810 }, + { 45, 0xA0A5A4CC, 0xB0A5A4CC, 810 }, + { 29, 0xA025D6E8, 0xB025D6E8, 810 }, + { 2, 0xA02E0DDC, 0xB02E0DDC, 810 }, + { 18, 0xA0BB56C0, 0xB0BB56C0, 810 }, + { 12, 0xA02FB08C, 0xB02FB08C, 810 }, + { 2, 0xA03E821C, 0xB03E821C, 810 }, + { 12, 0xA0CA54B8, 0xB0CA54B8, 810 }, + { 2, 0xA0767CA4, 0xB0767CA4, 810 }, + { 20, 0xA0CE97D8, 0xB0CE97D8, 810 }, + { 19, 0xA06F00D4, 0xB06F00D4, 810 }, + { 32, 0xA0A8ADE8, 0xB0A8ADE8, 810 }, + { 25, 0xA0C3E358, 0xB0C3E358, 810 }, + { 34, 0xA0BFB66C, 0xB0BFB66C, 810 }, + { 30, 0xA062F298, 0xB062F298, 810 }, + { 16, 0xA0B97174, 0xB0B97174, 810 }, + { 2, 0xA0DFCD94, 0xB0DFCD94, 810 }, + { 41, 0xA03AB784, 0xB03AB784, 810 }, + { 12, 0xA09BBB4C, 0xB09BBB4C, 810 }, + { 18, 0xA04D605C, 0xB04D605C, 810 }, + { 22, 0xA0F357A0, 0xB0F357A0, 810 }, + { 3, 0xA0CE5868, 0xB0CE5868, 810 }, + { 41, 0xA0376BCC, 0xB0376BCC, 810 }, + { 21, 0xA01C5614, 0xB01C5614, 810 }, + { 17, 0xA0A874D0, 0xB0A874D0, 810 }, + { 7, 0xA089FD2C, 0xB089FD2C, 810 }, + { 23, 0xA0CE227C, 0xB0CE227C, 810 }, + { 27, 0xA06C7698, 0xB06C7698, 810 }, + { 25, 0xA0010A70, 0xB0010A70, 810 }, + { 47, 0xA072D4F0, 0xB072D4F0, 810 }, + { 28, 0xA0793674, 0xB0793674, 810 }, + { 24, 0xA0EE4980, 0xB0EE4980, 810 }, + { 21, 0xA0EB6FF8, 0xB0EB6FF8, 810 }, + { 11, 0xA0C6C990, 0xB0C6C990, 810 }, + { 31, 0xA03C53DC, 0xB03C53DC, 810 }, + { 44, 0xA0B54AE0, 0xB0B54AE0, 810 }, + { 31, 0xA0DAA940, 0xB0DAA940, 810 }, + { 23, 0xA0C4A1A8, 0xB0C4A1A8, 810 }, + { 33, 0xA08C1EBC, 0xB08C1EBC, 810 }, + { 17, 0xA086F73C, 0xB086F73C, 810 }, + { 5, 0xA0E0135C, 0xB0E0135C, 810 }, +}; + +static const uint8_t __attribute__((section(".pdcp_src"), used)) pdcp_src_data[NUM_SRC_SLOTS][PDU_STRIDE] = { + [13] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 0x5F, 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F, 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F, 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF, 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0xDF, 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 0x5F, 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F, 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F, 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF, 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 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/dev/null +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/data/data_48_800_300.h @@ -0,0 +1,651 @@ + +// Copyright 2025 ETH Zurich and University of Bologna. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// Author: Zexin Fu + +#ifndef PDCP_PKG_H +#define PDCP_PKG_H + +#include + +typedef struct { + int user_id; + unsigned int src_addr; + unsigned int tgt_addr; + unsigned int pkg_length; +} pdcp_pkg_t; + +#define NUM_SRC_SLOTS 20661 +#define PDU_SIZE 810 +#define PDU_STRIDE 812 +#define NUM_PKGS 300 +#define ACTIVE_USER_NUMBER 48 + +#define NUM_PRODUCER_CORES 2 +static const unsigned int producer_core_ids[NUM_PRODUCER_CORES] = {0, 1}; +#define NUM_CONSUMER_CORES 2 +static const unsigned int consumer_core_ids[NUM_CONSUMER_CORES] = {2, 3}; +#define NUM_RLC_KERNEL_CORES (NUM_PRODUCER_CORES + NUM_CONSUMER_CORES) +static const unsigned int rlc_kernel_core_ids[NUM_RLC_KERNEL_CORES] = {0, 1, 2, 3}; + +static const pdcp_pkg_t __attribute__((section(".pdcp_info"), used)) pdcp_pkgs[NUM_PKGS] = { + { 37, 0xA02D3300, 0xB02D3300, 810 }, + { 38, 0xA00A25C4, 0xB00A25C4, 810 }, + { 2, 0xA06FA8F0, 0xB06FA8F0, 810 }, + { 39, 0xA0636B20, 0xB0636B20, 810 }, + { 5, 0xA05A9F18, 0xB05A9F18, 810 }, + { 26, 0xA038A5D0, 0xB038A5D0, 810 }, + { 42, 0xA0299B28, 0xB0299B28, 810 }, + { 37, 0xA0DD6968, 0xB0DD6968, 810 }, + { 36, 0xA0234980, 0xB0234980, 810 }, + { 33, 0xA0EFBC9C, 0xB0EFBC9C, 810 }, + { 20, 0xA0AB4B2C, 0xB0AB4B2C, 810 }, + { 16, 0xA00CE5EC, 0xB00CE5EC, 810 }, + { 13, 0xA00C17C0, 0xB00C17C0, 810 }, + { 42, 0xA02609A8, 0xB02609A8, 810 }, + { 45, 0xA058C350, 0xB058C350, 810 }, + { 20, 0xA05E7334, 0xB05E7334, 810 }, + { 15, 0xA0CD2B14, 0xB0CD2B14, 810 }, + { 16, 0xA0F46868, 0xB0F46868, 810 }, + { 25, 0xA00AC45C, 0xB00AC45C, 810 }, + { 8, 0xA0E3DAC8, 0xB0E3DAC8, 810 }, + { 42, 0xA050B8C4, 0xB050B8C4, 810 }, + { 41, 0xA0DD3D00, 0xB0DD3D00, 810 }, + { 19, 0xA0AA5098, 0xB0AA5098, 810 }, + { 29, 0xA0597E74, 0xB0597E74, 810 }, + { 20, 0xA0B65ED4, 0xB0B65ED4, 810 }, + { 4, 0xA0EF3DBC, 0xB0EF3DBC, 810 }, + { 0, 0xA070EFA4, 0xB070EFA4, 810 }, + { 29, 0xA002A070, 0xB002A070, 810 }, + { 39, 0xA040D014, 0xB040D014, 810 }, + { 36, 0xA0AB9420, 0xB0AB9420, 810 }, + { 6, 0xA08A233C, 0xB08A233C, 810 }, + { 4, 0xA070CFEC, 0xB070CFEC, 810 }, + { 34, 0xA03F1D88, 0xB03F1D88, 810 }, + { 13, 0xA0576994, 0xB0576994, 810 }, + { 32, 0xA088A69C, 0xB088A69C, 810 }, + { 16, 0xA0297E9C, 0xB0297E9C, 810 }, + { 8, 0xA025A754, 0xB025A754, 810 }, + { 22, 0xA09A3EAC, 0xB09A3EAC, 810 }, + { 4, 0xA02743AC, 0xB02743AC, 810 }, + { 15, 0xA091BEC4, 0xB091BEC4, 810 }, + { 23, 0xA08BA308, 0xB08BA308, 810 }, + { 18, 0xA0F51A08, 0xB0F51A08, 810 }, + { 10, 0xA06B62A4, 0xB06B62A4, 810 }, + { 28, 0xA011A194, 0xB011A194, 810 }, + { 34, 0xA0BA8568, 0xB0BA8568, 810 }, + { 45, 0xA0D9B504, 0xB0D9B504, 810 }, + { 19, 0xA032ACF8, 0xB032ACF8, 810 }, + { 39, 0xA099ACC4, 0xB099ACC4, 810 }, + { 41, 0xA01FFDC8, 0xB01FFDC8, 810 }, + { 33, 0xA0E0200C, 0xB0E0200C, 810 }, + { 0, 0xA0770508, 0xB0770508, 810 }, + { 42, 0xA0FF3974, 0xB0FF3974, 810 }, + { 35, 0xA0FB1C64, 0xB0FB1C64, 810 }, + { 19, 0xA092D2B8, 0xB092D2B8, 810 }, + { 42, 0xA0EA6588, 0xB0EA6588, 810 }, + { 6, 0xA04E0ED0, 0xB04E0ED0, 810 }, + { 8, 0xA01C3CB4, 0xB01C3CB4, 810 }, + { 16, 0xA01298FC, 0xB01298FC, 810 }, + { 7, 0xA05C8464, 0xB05C8464, 810 }, + { 6, 0xA0757BB8, 0xB0757BB8, 810 }, + { 47, 0xA0206348, 0xB0206348, 810 }, + { 35, 0xA05E8310, 0xB05E8310, 810 }, + { 9, 0xA028FFBC, 0xB028FFBC, 810 }, + { 17, 0xA09A51B4, 0xB09A51B4, 810 }, + { 18, 0xA070D970, 0xB070D970, 810 }, + { 38, 0xA0B8148C, 0xB0B8148C, 810 }, + { 13, 0xA0941C98, 0xB0941C98, 810 }, + { 45, 0xA04206EC, 0xB04206EC, 810 }, + { 21, 0xA0964AD8, 0xB0964AD8, 810 }, + { 13, 0xA0903BCC, 0xB0903BCC, 810 }, + { 43, 0xA0550EEC, 0xB0550EEC, 810 }, + { 40, 0xA06C6390, 0xB06C6390, 810 }, + { 16, 0xA01CFB04, 0xB01CFB04, 810 }, + { 32, 0xA0F74EA0, 0xB0F74EA0, 810 }, + { 31, 0xA04578B4, 0xB04578B4, 810 }, + { 16, 0xA0D8DA28, 0xB0D8DA28, 810 }, + { 3, 0xA063619C, 0xB063619C, 810 }, + { 5, 0xA0425638, 0xB0425638, 810 }, + { 40, 0xA0BBAC64, 0xB0BBAC64, 810 }, + { 27, 0xA09A0BEC, 0xB09A0BEC, 810 }, + { 17, 0xA06D973C, 0xB06D973C, 810 }, + { 2, 0xA0E21EB8, 0xB0E21EB8, 810 }, + { 0, 0xA05928D0, 0xB05928D0, 810 }, + { 21, 0xA083A858, 0xB083A858, 810 }, + { 8, 0xA016B2E0, 0xB016B2E0, 810 }, + { 40, 0xA05CFCEC, 0xB05CFCEC, 810 }, + { 16, 0xA00D05A4, 0xB00D05A4, 810 }, + { 10, 0xA0801080, 0xB0801080, 810 }, + { 47, 0xA0A2DE4C, 0xB0A2DE4C, 810 }, + { 28, 0xA06CB2DC, 0xB06CB2DC, 810 }, + { 35, 0xA01ADCA0, 0xB01ADCA0, 810 }, + { 45, 0xA055A72C, 0xB055A72C, 810 }, + { 27, 0xA0E6454C, 0xB0E6454C, 810 }, + { 35, 0xA07FC134, 0xB07FC134, 810 }, + { 0, 0xA0565274, 0xB0565274, 810 }, + { 7, 0xA0CAAD88, 0xB0CAAD88, 810 }, + { 4, 0xA0A0A030, 0xB0A0A030, 810 }, + { 44, 0xA0BA4924, 0xB0BA4924, 810 }, + { 9, 0xA039FF8C, 0xB039FF8C, 810 }, + { 34, 0xA06B88B4, 0xB06B88B4, 810 }, + { 2, 0xA038AF54, 0xB038AF54, 810 }, + { 23, 0xA0641FEC, 0xB0641FEC, 810 }, + { 37, 0xA0E3E778, 0xB0E3E778, 810 }, + { 35, 0xA0DAD27C, 0xB0DAD27C, 810 }, + { 9, 0xA06AAAAC, 0xB06AAAAC, 810 }, + { 27, 0xA0ED5544, 0xB0ED5544, 810 }, + { 8, 0xA0ADEEC8, 0xB0ADEEC8, 810 }, + { 2, 0xA0ECE96C, 0xB0ECE96C, 810 }, + { 19, 0xA0A22654, 0xB0A22654, 810 }, + { 23, 0xA092F59C, 0xB092F59C, 810 }, + { 2, 0xA0590918, 0xB0590918, 810 }, + { 22, 0xA03826F0, 0xB03826F0, 810 }, + { 13, 0xA0CEDDA0, 0xB0CEDDA0, 810 }, + { 43, 0xA0C85C64, 0xB0C85C64, 810 }, + { 15, 0xA024E5D8, 0xB024E5D8, 810 }, + { 42, 0xA0131E34, 0xB0131E34, 810 }, + { 6, 0xA02C8160, 0xB02C8160, 810 }, + { 22, 0xA03E0CC0, 0xB03E0CC0, 810 }, + { 35, 0xA0FEBDC0, 0xB0FEBDC0, 810 }, + { 26, 0xA040F2F8, 0xB040F2F8, 810 }, + { 39, 0xA0AB648C, 0xB0AB648C, 810 }, + { 47, 0xA0F223F4, 0xB0F223F4, 810 }, + { 9, 0xA019C8AC, 0xB019C8AC, 810 }, + { 15, 0xA09C3700, 0xB09C3700, 810 }, + { 10, 0xA09AED20, 0xB09AED20, 810 }, + { 11, 0xA0F1EE08, 0xB0F1EE08, 810 }, + { 26, 0xA0BE070C, 0xB0BE070C, 810 }, + { 1, 0xA0D6D1F8, 0xB0D6D1F8, 810 }, + { 11, 0xA06611E8, 0xB06611E8, 810 }, + { 47, 0xA0E09BC0, 0xB0E09BC0, 810 }, + { 21, 0xA004A8A0, 0xB004A8A0, 810 }, + { 26, 0xA02E800C, 0xB02E800C, 810 }, + { 42, 0xA0DA0124, 0xB0DA0124, 810 }, + { 47, 0xA06C53B4, 0xB06C53B4, 810 }, + { 15, 0xA08A19B8, 0xB08A19B8, 810 }, + { 17, 0xA02D4934, 0xB02D4934, 810 }, + { 10, 0xA07727EC, 0xB07727EC, 810 }, + { 44, 0xA0B08288, 0xB0B08288, 810 }, + { 6, 0xA04034A8, 0xB04034A8, 810 }, + { 24, 0xA0B83444, 0xB0B83444, 810 }, + { 2, 0xA0015038, 0xB0015038, 810 }, + { 30, 0xA06AED48, 0xB06AED48, 810 }, + { 14, 0xA0CB3C44, 0xB0CB3C44, 810 }, + { 12, 0xA0488828, 0xB0488828, 810 }, + { 29, 0xA0CE1C24, 0xB0CE1C24, 810 }, + { 22, 0xA02B3128, 0xB02B3128, 810 }, + { 19, 0xA0FDDC8C, 0xB0FDDC8C, 810 }, + { 14, 0xA07929C4, 0xB07929C4, 810 }, + { 14, 0xA0F73B98, 0xB0F73B98, 810 }, + { 1, 0xA050BF1C, 0xB050BF1C, 810 }, + { 42, 0xA097CDD0, 0xB097CDD0, 810 }, + { 12, 0xA04194BC, 0xB04194BC, 810 }, + { 25, 0xA0DAFBB8, 0xB0DAFBB8, 810 }, + { 21, 0xA0D750D8, 0xB0D750D8, 810 }, + { 17, 0xA0003918, 0xB0003918, 810 }, + { 4, 0xA0F32B38, 0xB0F32B38, 810 }, + { 17, 0xA083987C, 0xB083987C, 810 }, + { 22, 0xA0C65DB8, 0xB0C65DB8, 810 }, + { 41, 0xA007E7A8, 0xB007E7A8, 810 }, + { 32, 0xA02D68EC, 0xB02D68EC, 810 }, + { 25, 0xA0935E48, 0xB0935E48, 810 }, + { 43, 0xA07CD7D0, 0xB07CD7D0, 810 }, + { 34, 0xA0613688, 0xB0613688, 810 }, + { 21, 0xA0178438, 0xB0178438, 810 }, + { 1, 0xA061C870, 0xB061C870, 810 }, + { 7, 0xA0E65854, 0xB0E65854, 810 }, + { 16, 0xA01FF770, 0xB01FF770, 810 }, + { 11, 0xA022C448, 0xB022C448, 810 }, + { 37, 0xA0C54CF0, 0xB0C54CF0, 810 }, + { 16, 0xA01C16A4, 0xB01C16A4, 810 }, + { 2, 0xA0D84514, 0xB0D84514, 810 }, + { 6, 0xA0330C20, 0xB0330C20, 810 }, + { 38, 0xA0342014, 0xB0342014, 810 }, + { 27, 0xA0C0F6C8, 0xB0C0F6C8, 810 }, + { 22, 0xA0DF3554, 0xB0DF3554, 810 }, + { 46, 0xA04307D8, 0xB04307D8, 810 }, + { 20, 0xA06B9BBC, 0xB06B9BBC, 810 }, + { 27, 0xA0D639B8, 0xB0D639B8, 810 }, + { 38, 0xA0F64430, 0xB0F64430, 810 }, + { 32, 0xA0ABCA0C, 0xB0ABCA0C, 810 }, + { 7, 0xA055FCD0, 0xB055FCD0, 810 }, + { 24, 0xA0DAF234, 0xB0DAF234, 810 }, + { 36, 0xA051A9D4, 0xB051A9D4, 810 }, + { 12, 0xA07E8D88, 0xB07E8D88, 810 }, + { 16, 0xA0A1FD18, 0xB0A1FD18, 810 }, + { 2, 0xA0979B10, 0xB0979B10, 810 }, + { 45, 0xA0B1DC44, 0xB0B1DC44, 810 }, + { 27, 0xA0D21FD4, 0xB0D21FD4, 810 }, + { 0, 0xA0B74CB8, 0xB0B74CB8, 810 }, + { 33, 0xA031207C, 0xB031207C, 810 }, + { 34, 0xA064A524, 0xB064A524, 810 }, + { 43, 0xA05B3758, 0xB05B3758, 810 }, + { 46, 0xA019FE98, 0xB019FE98, 810 }, + { 47, 0xA0894208, 0xB0894208, 810 }, + { 47, 0xA008896C, 0xB008896C, 810 }, + { 42, 0xA0EED83C, 0xB0EED83C, 810 }, + { 12, 0xA0E0E188, 0xB0E0E188, 810 }, + { 23, 0xA05D6BF0, 0xB05D6BF0, 810 }, + { 27, 0xA0EEE818, 0xB0EEE818, 810 }, + { 4, 0xA0596840, 0xB0596840, 810 }, + { 42, 0xA002E964, 0xB002E964, 810 }, + { 21, 0xA01CD1C8, 0xB01CD1C8, 810 }, + { 39, 0xA017E68C, 0xB017E68C, 810 }, + { 20, 0xA05CF03C, 0xB05CF03C, 810 }, + { 42, 0xA01B5B80, 0xB01B5B80, 810 }, + { 7, 0xA00CBFDC, 0xB00CBFDC, 810 }, + { 46, 0xA08625E4, 0xB08625E4, 810 }, + { 19, 0xA01CC1EC, 0xB01CC1EC, 810 }, + { 32, 0xA0D0BC94, 0xB0D0BC94, 810 }, + { 19, 0xA0609E48, 0xB0609E48, 810 }, + { 42, 0xA0710F5C, 0xB0710F5C, 810 }, + { 26, 0xA0C513D8, 0xB0C513D8, 810 }, + { 20, 0xA056FA90, 0xB056FA90, 810 }, + { 25, 0xA0DAEBDC, 0xB0DAEBDC, 810 }, + { 44, 0xA035B614, 0xB035B614, 810 }, + { 18, 0xA0E7D4F4, 0xB0E7D4F4, 810 }, + { 35, 0xA0E9F02C, 0xB0E9F02C, 810 }, + { 8, 0xA0BFE600, 0xB0BFE600, 810 }, + { 12, 0xA062A678, 0xB062A678, 810 }, + { 26, 0xA0C005B8, 0xB0C005B8, 810 }, + { 42, 0xA0A54278, 0xB0A54278, 810 }, + { 24, 0xA04D4D54, 0xB04D4D54, 810 }, + { 43, 0xA0264918, 0xB0264918, 810 }, + { 47, 0xA02759E0, 0xB02759E0, 810 }, + { 11, 0xA0AEFF90, 0xB0AEFF90, 810 }, + { 39, 0xA08FD64C, 0xB08FD64C, 810 }, + { 36, 0xA0ABF674, 0xB0ABF674, 810 }, + { 19, 0xA0A6E528, 0xB0A6E528, 810 }, + { 25, 0xA0BD9B34, 0xB0BD9B34, 810 }, + { 35, 0xA015FE14, 0xB015FE14, 810 }, + { 0, 0xA027F220, 0xB027F220, 810 }, + { 19, 0xA0189B58, 0xB0189B58, 810 }, + { 18, 0xA0A3768C, 0xB0A3768C, 810 }, + { 13, 0xA089C0E8, 0xB089C0E8, 810 }, + { 27, 0xA02C5B50, 0xB02C5B50, 810 }, + { 37, 0xA064F144, 0xB064F144, 810 }, + { 38, 0xA04DC908, 0xB04DC908, 810 }, + { 41, 0xA04D3720, 0xB04D3720, 810 }, + { 20, 0xA0D9BB5C, 0xB0D9BB5C, 810 }, + { 29, 0xA0B62290, 0xB0B62290, 810 }, + { 28, 0xA038E86C, 0xB038E86C, 810 }, + { 28, 0xA0AB4800, 0xB0AB4800, 810 }, + { 43, 0xA04A7D50, 0xB04A7D50, 810 }, + { 13, 0xA07115B4, 0xB07115B4, 810 }, + { 32, 0xA0BBD274, 0xB0BBD274, 810 }, + { 30, 0xA06569CC, 0xB06569CC, 810 }, + { 47, 0xA01E9A88, 0xB01E9A88, 810 }, + { 10, 0xA0B3E7A0, 0xB0B3E7A0, 810 }, + { 42, 0xA0DF6E6C, 0xB0DF6E6C, 810 }, + { 5, 0xA027BF60, 0xB027BF60, 810 }, + { 18, 0xA01487CC, 0xB01487CC, 810 }, + { 32, 0xA0DB776C, 0xB0DB776C, 810 }, + { 42, 0xA005FC04, 0xB005FC04, 810 }, + { 40, 0xA025DD40, 0xB025DD40, 810 }, + { 39, 0xA05FF62C, 0xB05FF62C, 810 }, + { 21, 0xA043838C, 0xB043838C, 810 }, + { 5, 0xA0A4FFDC, 0xB0A4FFDC, 810 }, + { 15, 0xA0C52A0C, 0xB0C52A0C, 810 }, + { 43, 0xA0C36DFC, 0xB0C36DFC, 810 }, + { 19, 0xA056C7D0, 0xB056C7D0, 810 }, + { 14, 0xA0A2D19C, 0xB0A2D19C, 810 }, + { 12, 0xA017CD2C, 0xB017CD2C, 810 }, + { 9, 0xA042D518, 0xB042D518, 810 }, + { 1, 0xA099DC58, 0xB099DC58, 810 }, + { 2, 0xA000DE08, 0xB000DE08, 810 }, + { 15, 0xA09E81CC, 0xB09E81CC, 810 }, + { 30, 0xA06BAB98, 0xB06BAB98, 810 }, + { 39, 0xA0B8B97C, 0xB0B8B97C, 810 }, + { 4, 0xA073CF84, 0xB073CF84, 810 }, + { 29, 0xA0ABBD5C, 0xB0ABBD5C, 810 }, + { 26, 0xA0E1A304, 0xB0E1A304, 810 }, + { 40, 0xA0C595E4, 0xB0C595E4, 810 }, + { 36, 0xA03ED7C0, 0xB03ED7C0, 810 }, + { 12, 0xA04D1768, 0xB04D1768, 810 }, + { 45, 0xA07874F8, 0xB07874F8, 810 }, + { 44, 0xA05860FC, 0xB05860FC, 810 }, + { 24, 0xA017BD50, 0xB017BD50, 810 }, + { 31, 0xA0EB23D8, 0xB0EB23D8, 810 }, + { 25, 0xA0DC1F88, 0xB0DC1F88, 810 }, + { 15, 0xA018BE3C, 0xB018BE3C, 810 }, + { 9, 0xA07F5230, 0xB07F5230, 810 }, + { 41, 0xA01734EC, 0xB01734EC, 810 }, + { 44, 0xA0145B64, 0xB0145B64, 810 }, + { 0, 0xA0ED2C08, 0xB0ED2C08, 810 }, + { 6, 0xA0C19234, 0xB0C19234, 810 }, + { 27, 0xA0CC26FC, 0xB0CC26FC, 810 }, + { 14, 0xA0D7A024, 0xB0D7A024, 810 }, + { 11, 0xA03FE888, 0xB03FE888, 810 }, + { 44, 0xA0171534, 0xB0171534, 810 }, + { 33, 0xA0CE2C00, 0xB0CE2C00, 810 }, + { 29, 0xA020862C, 0xB020862C, 810 }, + { 3, 0xA04B718C, 0xB04B718C, 810 }, + { 35, 0xA01BD0DC, 0xB01BD0DC, 810 }, + { 15, 0xA0F19538, 0xB0F19538, 810 }, + { 7, 0xA01B9498, 0xB01B9498, 810 }, + { 29, 0xA05F7DA4, 0xB05F7DA4, 810 }, + { 8, 0xA0A3EBE8, 0xB0A3EBE8, 810 }, + { 29, 0xA030AB20, 0xB030AB20, 810 }, + { 42, 0xA0E74964, 0xB0E74964, 810 }, + { 33, 0xA063F384, 0xB063F384, 810 }, +}; + +static const uint8_t __attribute__((section(".pdcp_src"), used)) pdcp_src_data[NUM_SRC_SLOTS][PDU_STRIDE] = { + [18] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 0x5F, 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F, 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F, 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF, 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0xDF, 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 0x5F, 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F, 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F, 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF, 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0xDF, 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 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0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 0x5F, 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F, 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F, 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF, 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0xDF, 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 0x5F, 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F, 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F, 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x00, 0x00 }, +}; + +#endif // PDCP_PKG_H diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/llist.h b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/llist.h index 62d4bcb..f4b81d4 100644 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/llist.h +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/llist.h @@ -20,6 +20,7 @@ #define LLIST_H #include +#include #include "printf_lock.h" #include "mcs_lock.h" // #include "spin_lock.h" @@ -30,8 +31,8 @@ typedef volatile int spinlock_t __attribute__((aligned(4))); spinlock_t tosend_llist_lock __attribute__((section(".data"))); spinlock_t sent_llist_lock __attribute__((section(".data"))); -static _Atomic mcs_lock_t tosend_llist_lock_2 __attribute__((aligned(4))) __attribute__((section(".data"))); -static _Atomic mcs_lock_t sent_llist_lock_2 __attribute__((aligned(4))) __attribute__((section(".data"))); +/* Per-user mcs locks (tosend_llist_lock_2[NUM_USERS] / sent_llist_lock_2[NUM_USERS]) + are declared in rlc.h, where NUM_USERS is visible. */ static inline void spin_lock(spinlock_t *lock, int cycle) { while (__sync_lock_test_and_set(lock, 1)) { delay(cycle);} @@ -63,6 +64,7 @@ typedef struct Node { void *tgt; /* Pointer to the address to move the payload data to */ size_t data_size; /* Size of the payload in bytes */ spinlock_t lock; /* Perโ€‘node lock (0: unlocked, 1: locked) */ + uint32_t user_id; /* Owning RLC entity / UE (instrumentation + multi-user routing) */ } Node; /* Doublyโ€‘linked list structure for storing Node pointers. diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/mm.h b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/mm.h index c680467..d01ebd2 100644 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/mm.h +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/mm.h @@ -25,7 +25,10 @@ // #define PAGE_SIZE (1024) /* Fixed size of each memory page in bytes */ #define PAGE_SIZE (sizeof(Node)) /* Fixed size of each memory page in bytes */ -#define BUFFER_SIZE (PAGE_SIZE * 1024) /* memory pool size in byte */ +#ifndef MM_POOL_PAGES +#define MM_POOL_PAGES 1024 /* live nodes are bounded by min(NUM_PKGS, MM_POOL_PAGES) */ +#endif +#define BUFFER_SIZE (PAGE_SIZE * MM_POOL_PAGES) /* memory pool size in byte */ static uint32_t bulk_buffer[BUFFER_SIZE / sizeof(uint32_t)] __attribute__((section(".dram"))) diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.c b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.c index 8ea7ebd..842e46c 100644 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.c +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.c @@ -36,10 +36,24 @@ #include #include "printf.h" #include "printf_lock.h" -#include "../data/data_1_1350_100.h" +/* Data header comes from the build (-DDATAHEADER, see CMakeLists). main.c + includes it before this file; the guard below is a self-sufficiency + fallback for standalone compilation of rlc.c. Never hard-code a specific + header here: it would shadow DATAHEADER for every variant (include guard + PDCP_PKG_H is shared by all generated headers). */ +#ifndef PDCP_PKG_H +#include DATAHEADER +#endif + #include #include "benchmark.h" +// volatile: these structs model memory traffic (status indications/reports); +// their loaded values are intentionally unused, so without volatile the +// compiler would optimize the loads away (PR #12 review). +volatile DlschInd dlsch_ind __attribute__((section(".data"))); +volatile UeStateRpt ue_status_rpt_content __attribute__((section(".data"))); + static inline size_t memdiff32(const void *a, const void *b, size_t len_bytes) { const uint8_t *p = (const uint8_t *)a; const uint8_t *q = (const uint8_t *)b; @@ -99,77 +113,59 @@ static inline void memprint32(const void *a, const void *b, size_t len_bytes) { } -void self_check(pdcp_pkg_t *meta, int size) { +/* self_check compares src vs tgt payloads after the run. Two byte ranges are + excluded: [0,4) holds the RLC SN written over the tgt header word, and + [64,128) is rewritten on the SRC side by rlc_send_pkt AFTER the payload copy + (traffic modeling), so tgt legitimately has the pre-rewrite content there. */ +#ifdef RLC_SELF_CHECK +void self_check(const pdcp_pkg_t *meta, int size) { uint32_t core_id = snrt_cluster_core_idx(); + int npass = 0, nfail = 0; for (int i = 0; i < size; i++) { - unsigned int src_addr = meta[i].src_addr; - unsigned int tgt_addr = meta[i].tgt_addr; - unsigned int pkg_length = meta[i].pkg_length; - - void *src = (const void *)(uintptr_t)src_addr; - void *tgt = (const void *)(uintptr_t)tgt_addr; - - memprint32(src, tgt, pkg_length); - size_t idx = memdiff32(src, tgt, pkg_length); - // size_t idx = meta; - if (idx == pkg_length) { - // Exactly equal - // DEBUG_PRINTF_LOCK_ACQUIRE(&printf_lock); - // DEBUG_PRINTF("[core %u][self test] pass pkg_num = %d, src_addr=0x%x, tgt_addr=0x%x, pkg_length=%d\n", - // core_id, - // i, - // src_addr, - // tgt_addr, - // pkg_length - // ); - // DEBUG_PRINTF_LOCK_RELEASE(&printf_lock); + const uint8_t *src = (const uint8_t *)(uintptr_t)meta[i].src_addr; + const uint8_t *tgt = (const uint8_t *)(uintptr_t)meta[i].tgt_addr; + size_t len = meta[i].pkg_length; + size_t first_bad = len; /* len == match */ + for (size_t off = 4; off < len && first_bad == len; off++) { + if (off >= 64 && off < 128) continue; /* post-copy src rewrite, see above */ + if (src[off] != tgt[off]) first_bad = off; + } + if (first_bad == len) { + npass++; } else { - // Mismatch at byte offset `idx` + nfail++; DEBUG_PRINTF_LOCK_ACQUIRE(&printf_lock); - DEBUG_PRINTF("[core %u][self test] fail pkg_num = %d, src_addr=0x%x, tgt_addr=0x%x, pkg_length=%d\n", - core_id, - i, - src_addr, - tgt_addr, - pkg_length - ); + DEBUG_PRINTF("[core %u][self test] FAIL pkg_num = %d user = %d, first mismatch @%d\n", + core_id, i, meta[i].user_id, (int)first_bad); DEBUG_PRINTF_LOCK_RELEASE(&printf_lock); } } + DEBUG_PRINTF_LOCK_ACQUIRE(&printf_lock); + DEBUG_PRINTF("[core %u][self test] SUMMARY: %d/%d pass, %d fail\n", core_id, npass, size, nfail); + DEBUG_PRINTF_LOCK_RELEASE(&printf_lock); } +#endif +/* Initialize RLC entity `rlcId` (one entity per UE). Global/shared resources + (pdcp_pkd_ptr, its lock, producer_done, rlc_ctx_lock) are initialized once + in main(), not here. */ void rlc_init(const unsigned int rlcId, const unsigned int cellId, mm_context_t *mm_ctx) { - rlc_ctx.rlcId = rlcId; - rlc_ctx.cellId = cellId; - rlc_ctx.pollPdu = 32; - rlc_ctx.pollByte = 25000; - rlc_ctx.pduWithoutPoll = 0; - rlc_ctx.byteWithoutPoll = 0; - rlc_ctx.vtNextAck = 0; - rlc_ctx.vtNext = 0; + rlc_context_t *ctx = &rlc_ctx[rlcId]; + ctx->rlcId = rlcId; + ctx->cellId = cellId; + ctx->pollPdu = 32; + ctx->pollByte = 25000; + ctx->pduWithoutPoll = 0; + ctx->byteWithoutPoll = 0; + ctx->vtNextAck = 0; + ctx->vtNext = 0; // Initialize the linked lists - list_init(&rlc_ctx.list); - list_init(&rlc_ctx.sent_list); + list_init(&ctx->list); + list_init(&ctx->sent_list); // Set the memory management context - rlc_ctx.mm_ctx = mm_ctx; - - // Initialize PDCP package pointer and lock - pdcp_pkd_ptr = 0; - // pdcp_pkd_ptr_lock = 0; - mcs_lock_init(&pdcp_pkd_ptr_lock); - - // Initialize producer done flag - producer_done = 0; - producers_finished = 0; - - rlc_ctx_lock = 0; - - // DEBUG_PRINTF_LOCK_ACQUIRE(&printf_lock); - // DEBUG_PRINTF("[core %u][rlc_init] RLC context initialized for RLC ID %u, Cell ID %u\n", - // snrt_cluster_core_idx(), rlcId, cellId); - // DEBUG_PRINTF_LOCK_RELEASE(&printf_lock); + ctx->mm_ctx = mm_ctx; } int __attribute__((noinline)) pdcp_receive_pkg(const unsigned int core_id, volatile int *lock) { @@ -224,86 +220,235 @@ int __attribute__((noinline)) pdcp_receive_pkg(const unsigned int core_id, volat */ #define PACKET_SIZE (PAGE_SIZE - sizeof(Node)) -/* Consumer behavior (runs on cores listed in consumer_core_ids) */ -static void consumer(const unsigned int core_id) { - while (1) { - Node *node = list_pop_front(&tosend_llist_lock_2, &rlc_ctx.list); - if (node != 0) { - // DEBUG_PRINTF_LOCK_ACQUIRE(&printf_lock); - // DEBUG_PRINTF("Consumer (core %u): processing node %p, data_size = %zu, data_src = 0x%x, data_tgt = 0x%x, @mcycle = %d\n", - // core_id, (void *)node, node->data_size, node->data, node->tgt, benchmark_get_cycle()); - // DEBUG_PRINTF_LOCK_RELEASE(&printf_lock); - - // delay(100); /* Simulate processing delay */ - - uint32_t timer_mv_0, timer_mv_1; - // timer_mv_0 = benchmark_get_cycle(); - // vector_memcpy32_m4_opt(node->tgt, node->data, node->data_size); - // vector_memcpy32_m8_opt(node->tgt, node->data, node->data_size); - // scalar_memcpy32_32bit_unrolled(node->tgt, node->data, node->data_size); - // vector_memcpy32_m8_m4_general_opt(node->tgt, node->data, node->data_size); - // vector_memcpy32_1360B_opt(node->tgt, node->data); - // Atomically allocate a unique RLC sequence number for this PDU and - // use it as the header. fetch_add returns the pre-increment value, - // so each consumer gets a distinct SN (safe for multiple consumers). - uint32_t sn = atomic_fetch_add_explicit(&rlc_ctx.vtNext, 1, memory_order_relaxed); - vector_memcpy32_1360B_opt_with_header(node->tgt, node->data, sn); - // timer_mv_1 = benchmark_get_cycle(); - - // Update the RLC stats atomically (shared across multiple consumers). - atomic_fetch_add_explicit(&rlc_ctx.pduWithoutPoll, 1, memory_order_relaxed); - atomic_fetch_add_explicit(&rlc_ctx.byteWithoutPoll, node->data_size, memory_order_relaxed); - - - // DEBUG_PRINTF_LOCK_ACQUIRE(&printf_lock); - // DEBUG_PRINTF("Consumer (core %u): move node %p from data_src = 0x%x to data_tgt = 0x%x, data_size = %zu, cyc = %d, bw = %dB/1000cyc\n", - // core_id, (void *)node, node->data, node->tgt, node->data_size, - // (timer_mv_1 - timer_mv_0), - // (node->data_size * 1000 / (timer_mv_1 - timer_mv_0))); - // DEBUG_PRINTF_LOCK_RELEASE(&printf_lock); - - // Add the node to the sent list - list_push_back(&sent_llist_lock_2, &rlc_ctx.sent_list, node); - - // Simulate receiving ACK from UE after certain sent pkgs, and we assume the ACK_SN is rlc_ctx.vtNextAck+2 - if (rlc_ctx.sent_list.sduNum >= 10000) { - uint32_t vtNextAck = atomic_load_explicit(&rlc_ctx.vtNextAck, memory_order_relaxed); - int ACK_SN = vtNextAck + 2; // Assume each time ack 2 sent pkgs - // DEBUG_PRINTF_LOCK_ACQUIRE(&printf_lock); - // DEBUG_PRINTF("[core %u][consumer] pollPdu=%d, pollByte=%d, sent_list.sduNum=%d, sent_list.sduBytes=%d\n", - // core_id, rlc_ctx.pollPdu, rlc_ctx.pollByte, - // rlc_ctx.sent_list.sduNum, rlc_ctx.sent_list.sduBytes); - // DEBUG_PRINTF_LOCK_RELEASE(&printf_lock); - - for (int i = vtNextAck; i < ACK_SN; i++) { - Node *sent_node = list_pop_front(&sent_llist_lock_2, &rlc_ctx.sent_list); - if (sent_node != NULL) { - // DEBUG_PRINTF_LOCK_ACQUIRE(&printf_lock); - // DEBUG_PRINTF("[core %u][consumer] pop sent_list, ACK_SN=%d, SN=%d, sent node %p, data_size=%zu\n", - // core_id, ACK_SN, i, (void *)sent_node, sent_node->data_size); - // DEBUG_PRINTF_LOCK_RELEASE(&printf_lock); - } else { - DEBUG_PRINTF_LOCK_ACQUIRE(&printf_lock); - DEBUG_PRINTF("[core %u][consumer] ERROR: pop sent_list, ACK_SN=%d, SN=%d, but sent_node is NULL\n", - core_id, ACK_SN, i); - DEBUG_PRINTF_LOCK_RELEASE(&printf_lock); - } - mm_free(sent_node); // Free the sent node memory +// -- Producer / consumer core sets -- +// The generated data header is authoritative: producer_core_ids[] and +// consumer_core_ids[] name the cores that run the kernel, so the roles can be +// spread over specific tiles/groups rather than being forced into contiguous +// ranges. PRODUCER_CORE_NUM / CONSUMER_CORE_NUM remain as build-time knobs +// for headers generated before the lists existed, and as the pacing divisor. +#ifndef NUM_PRODUCER_CORES +#define NUM_PRODUCER_CORES PRODUCER_CORE_NUM +static const unsigned int producer_core_ids[NUM_PRODUCER_CORES] = {0, 1}; +#endif +#ifndef NUM_CONSUMER_CORES +#define NUM_CONSUMER_CORES CONSUMER_CORE_NUM +static const unsigned int consumer_core_ids[NUM_CONSUMER_CORES] = {2, 3}; +#endif +#ifndef PRODUCER_CORE_NUM +#define PRODUCER_CORE_NUM NUM_PRODUCER_CORES +#endif +#ifndef CONSUMER_CORE_NUM +#define CONSUMER_CORE_NUM NUM_CONSUMER_CORES +#endif + +/* Returns 1 if core_id appears in the given id list. */ +static int core_in_list(const unsigned int core_id, const unsigned int *ids, unsigned int n) { + for (unsigned int i = 0; i < n; i++) { + if (ids[i] == core_id) return 1; + } + return 0; +} + +/* Position of core_id within a list, or the list length if absent. Consumers + use their index here (not core_id - PRODUCER_CORE_NUM) to pick their share of + the RLC entities, so the partition follows the list rather than assuming the + consumer cores are contiguous. */ +static unsigned int core_index_in_list(const unsigned int core_id, const unsigned int *ids, + unsigned int n) { + for (unsigned int i = 0; i < n; i++) { + if (ids[i] == core_id) return i; + } + return n; +} + +#define CPU_FREQENCY 1000000000 // 1GHz +#define OUTPUT_DATARATE 7000000 +#define INPUT_DATARATE 7000000 + +/* Per-iteration pacing budget. RLC_ENABLE_PACING=1: correct 64-bit math + (intended INPUT/OUTPUT_DATARATE pacing). =0 (default): the legacy int32 + expression โ€” it overflows (e.g. 2*1360*1e9 wraps to 1285701632 -> 183 cyc), + which makes pacing nearly inert, but tiny delays still fire on iterations + shorter than the wrapped value, so keep it verbatim for TC1 parity. */ +#if RLC_ENABLE_PACING +#define RLC_TOTAL_CYCLE(ncore, rate) ((uint32_t)(((uint64_t)(ncore) * PDU_SIZE * CPU_FREQENCY) / (rate))) +#else +#define RLC_TOTAL_CYCLE(ncore, rate) ((uint32_t)((ncore) * PDU_SIZE * CPU_FREQENCY / (rate))) +#endif + +void ue_status_rpt(const unsigned int core_id) +{ + // Simulate receiving ACK from UE after certain sent pkgs, per RLC entity. + // ACK_SN is ctx->vtNextAck+2. Core 0 scans all users each call (single + // writer per entity; striping across producer cores is a future option). + for (unsigned int u = 0; u < NUM_USERS; u++) { + rlc_context_t *ctx = &rlc_ctx[u]; + if (ctx->sent_list.sduNum >= 2) { + char head = ue_status_rpt_content.stateRpt[0]; + char head1 = ue_status_rpt_content.stateRpt[1]; + char head2 = ue_status_rpt_content.stateRpt[2]; + uint32_t vtNextAck = atomic_load_explicit(&ctx->vtNextAck, memory_order_relaxed); + int ACK_SN = vtNextAck + 2; // Assume each time ack 2 sent pkgs + + for (int i = vtNextAck; i < ACK_SN; i++) { + char ack = ue_status_rpt_content.stateRpt[16 + ACK_SN - i]; + Node *sent_node = list_pop_front((spinlock_t *)&sent_llist_lock_2[u], &ctx->sent_list); + if (sent_node != NULL) { + // DEBUG_PRINTF_LOCK_ACQUIRE(&printf_lock); + // DEBUG_PRINTF("[core %u][consumer] pop sent_list, ACK_SN=%d, SN=%d, sent node %p, data_size=%zu\n", + // core_id, ACK_SN, i, (void *)sent_node, sent_node->data_size); + // DEBUG_PRINTF_LOCK_RELEASE(&printf_lock); + } else { + DEBUG_PRINTF_LOCK_ACQUIRE(&printf_lock); + DEBUG_PRINTF("[core %u][consumer] ERROR: pop sent_list, ACK_SN=%d, SN=%d, but sent_node is NULL\n", + core_id, ACK_SN, i); + DEBUG_PRINTF_LOCK_RELEASE(&printf_lock); } - atomic_store_explicit(&rlc_ctx.vtNextAck, ACK_SN, memory_order_relaxed); // Update the next ACK sequence number + mm_free(sent_node); // Free the sent node memory } - } else { - if (atomic_load_explicit(&producer_done, memory_order_relaxed) == 1) { - // If producer is done and the list is empty, exit the loop - break; + ctx->acksn = ACK_SN; + ctx->nackcount = 0; + ctx->parseindex++; + atomic_store_explicit(&ctx->vtNextAck, ACK_SN, memory_order_relaxed); // Update the next ACK sequence number + for (uint32_t i = 0; i < 16; i++) { + ctx->dlDelayInfo[i] = 300; } - // delay(10); /* Wait briefly if list is empty */ } } } -/* Producer behavior (runs on cores listed in producer_core_ids) */ -static void producer(const unsigned int core_id) { +/* Pop one node from entity ctx's to-send list and assemble/send its PDU. + Returns 1 if a node was processed, 0 if the list was empty. */ +static int rlc_send_pkt(const unsigned int core_id, rlc_context_t *ctx, TestDataStru *testData) +{ + const unsigned int u = (unsigned int)(ctx - rlc_ctx); // lock-free user index + Node *node = list_pop_front((spinlock_t *)&tosend_llist_lock_2[u], &ctx->list); + if (node == 0) { + return 0; + } +#ifdef RLC_NODE_GUARD + if (((uintptr_t)node->data & 0xFF000000) != 0xA0000000 || + ((uintptr_t)node->tgt & 0xFF000000) != 0xB0000000 || + node->data_size != PDU_SIZE || node->user_id != u) { + printf_lock_acquire(&printf_lock); + printf("[GUARD][core %u] BAD NODE u=%u node=%p user=%u data=0x%x tgt=0x%x size=%u cyc=%d\n", + core_id, u, (void *)node, node->user_id, + (unsigned int)(uintptr_t)node->data, (unsigned int)(uintptr_t)node->tgt, + (unsigned int)node->data_size, benchmark_get_cycle()); + printf_lock_release(&printf_lock); + } +#endif + // DEBUG_PRINTF_LOCK_ACQUIRE(&printf_lock); + // DEBUG_PRINTF("Consumer (core %u): processing node %p, data_size = %zu, data_src = 0x%x, data_tgt = 0x%x, @mcycle = %d\n", + // core_id, (void *)node, node->data_size, node->data, node->tgt, benchmark_get_cycle()); + // DEBUG_PRINTF_LOCK_RELEASE(&printf_lock); + + // delay(100); /* Simulate processing delay */ + + uint32_t timer_mv_0, timer_mv_1; + // timer_mv_0 = benchmark_get_cycle(); + // vector_memcpy32_m4_opt(node->tgt, node->data, node->data_size); + // vector_memcpy32_m8_opt(node->tgt, node->data, node->data_size); + // scalar_memcpy32_32bit_unrolled(node->tgt, node->data, node->data_size); + // vector_memcpy32_m8_m4_general_opt(node->tgt, node->data, node->data_size); + // vector_memcpy32_1360B_opt(node->tgt, node->data); + // Atomically allocate a unique RLC sequence number for this PDU from + // the OWNING entity (SNs are per-RLC-entity) and use it as the header. + uint32_t sn = atomic_fetch_add_explicit(&ctx->vtNext, 1, memory_order_relaxed); +#if (PDU_SIZE == 1360) + vector_memcpy32_1360B_opt_with_header(node->tgt, node->data, sn); +#else + // Generic path (e.g. 810-byte PDUs): word-vector copy (bases are + // 4-aligned by PDU_STRIDE; the tail switch handles the odd bytes), + // then the SN overwrites the first header word of the target. + vector_memcpy32_m8_m4_general_opt(node->tgt, node->data, node->data_size); + *(volatile uint32_t *)node->tgt = sn; +#endif + // timer_mv_1 = benchmark_get_cycle(); + + // Update the RLC stats atomically (shared across multiple consumers). + atomic_fetch_add_explicit(&ctx->pduWithoutPoll, 1, memory_order_relaxed); + atomic_fetch_add_explicit(&ctx->byteWithoutPoll, node->data_size, memory_order_relaxed); + ctx->sendPduNum +=1; + ctx->sendPduBytes += node->data_size; + atomic_fetch_add_explicit(&ctx->tbsize, (node->data_size + 10), memory_order_relaxed); + /* read one cacheline from node mem */ + RcvPktHeader tmp = *(RcvPktHeader *)node->data; + /* write 64B to node mem */ + vector_memcpy32_m4_opt(((RcvPktHeader *)node->data + 1), &tmp, sizeof(RcvPktHeader)); + ctx->pdcpcount++; + atomic_fetch_add_explicit(&ctx->rlcthrp, node->data_size, memory_order_relaxed); + atomic_fetch_add_explicit(&ctx->dlPduNum, 1, memory_order_relaxed); + atomic_fetch_add_explicit(&ctx->sduBytes, (0 - node->data_size), memory_order_relaxed); + atomic_fetch_add_explicit(&ctx->sduNum, (-1), memory_order_relaxed); + testData->sduNum = ctx->sduNum; + testData->rlcDpbPduCnt = ctx->pdcpcount; + testData->sudBytes = ctx->sduBytes; + testData->totalPdlLen = ctx->tbsize; + /* write one cacheline data to rlc_entity */ + for (uint32_t i = 0; i < 16; i++) { + ctx->rlcOm[i] = 20; + } + // DEBUG_PRINTF_LOCK_ACQUIRE(&printf_lock); + // DEBUG_PRINTF("Consumer (core %u): move node %p from data_src = 0x%x to data_tgt = 0x%x, data_size = %zu, cyc = %d, bw = %dB/1000cyc\n", + // core_id, (void *)node, node->data, node->tgt, node->data_size, + // (timer_mv_1 - timer_mv_0), + // (node->data_size * 1000 / (timer_mv_1 - timer_mv_0))); + // DEBUG_PRINTF_LOCK_RELEASE(&printf_lock); + + // Add the node to the sent list + list_push_back((spinlock_t *)&sent_llist_lock_2[u], &ctx->sent_list, node); + return 1; +} + +/* Consumer behavior: static user partition + round-robin scan, one node per + (paced) iteration. Consumer c (index within the consumer group) owns users + {u : u % stride == c % stride} with stride = min(CONSUMER_CORE_NUM, + NUM_USERS); at NUM_USERS == 1 stride is 1, so all consumers share user 0 โ€” + exactly the single-user behavior. The scan always issues the pop attempt + (no sduNum pre-check) to keep the idle lock traffic of the baseline. + Rate-limited so the aggregate consumer throughput equals OUTPUT_DATARATE + when pacing is enabled. */ +static void consumer(const unsigned int core_id) { + const unsigned int c = core_index_in_list(core_id, consumer_core_ids, + NUM_CONSUMER_CORES); + const unsigned int stride = (CONSUMER_CORE_NUM < NUM_USERS) ? CONSUMER_CORE_NUM : NUM_USERS; + const unsigned int first = c % stride; /* first owned user */ + unsigned int cursor = first; + uint32_t total_cycle = RLC_TOTAL_CYCLE(CONSUMER_CORE_NUM, OUTPUT_DATARATE); + while (1) { + uint32_t start_timecycle = benchmark_get_cycle(); + TestDataStru dfx = {0}; + dfx.dlschInd = dlsch_ind; + /* round-robin over owned users; send at most one PDU per iteration */ + unsigned int u = cursor; + int sent = 0; + do { + sent = rlc_send_pkt(core_id, &rlc_ctx[u], &dfx); + if (!sent) { u += stride; if (u >= NUM_USERS) u = first; } + } while (!sent && u != cursor); + if (sent) { u += stride; if (u >= NUM_USERS) u = first; cursor = u; } + uint32_t end_timecycle = benchmark_get_cycle(); + /* calculate delay interval */ + uint32_t interval = end_timecycle - start_timecycle; + rlc_ctx[first].pktdelay = interval; + uint32_t delayCycle = (total_cycle >= interval) ? (total_cycle - interval) : 0; + delay(delayCycle); + + /* Exit when all producers are done and every owned list is drained */ + if (atomic_load_explicit(&producer_done, memory_order_relaxed) >= PRODUCER_CORE_NUM) { + int drained = 1; + for (unsigned int v = first; v < NUM_USERS; v += stride) { + if (rlc_ctx[v].list.sduNum != 0) { drained = 0; break; } + } + if (drained) break; + } + } +} + +/* Producer behavior (runs on cores other than 0) */ +/* Returns 0 on success, -1 when no more packages available. */ +static int producer(const unsigned int core_id) { // DEBUG_PRINTF_LOCK_ACQUIRE(&printf_lock); // DEBUG_PRINTF("Producer (core %u): pdcp_src_data[0][0] = %d, pdcp_src_data[3657][500] = %d, pdcp_src_data[%d-1][%d-1] = %d, @mcycle = %d\n", // core_id, @@ -315,88 +460,148 @@ static void producer(const unsigned int core_id) { // benchmark_get_cycle()); // DEBUG_PRINTF_LOCK_RELEASE(&printf_lock); int new_pdcp_pkg_ptr = pdcp_receive_pkg(core_id, &pdcp_pkd_ptr_lock); - while (new_pdcp_pkg_ptr >= 0) { - // DEBUG_PRINTF_LOCK_ACQUIRE(&printf_lock); - // DEBUG_PRINTF("Producer (core %u): pdcp_receive_pkg id = %d, user_id = %d, pkg_length = %d, src_addr = 0x%x, tgt_addr = 0x%x\n", - // core_id, - // new_pdcp_pkg_ptr, - // pdcp_pkgs[new_pdcp_pkg_ptr].user_id, - // pdcp_pkgs[new_pdcp_pkg_ptr].pkg_length, - // pdcp_pkgs[new_pdcp_pkg_ptr].src_addr, - // pdcp_pkgs[new_pdcp_pkg_ptr].tgt_addr); - // DEBUG_PRINTF_LOCK_RELEASE(&printf_lock); + if (new_pdcp_pkg_ptr < 0) { + return -1; // No more packages + } + /* Route the package to its owning RLC entity (one per UE). */ + const unsigned int uid = (unsigned int)pdcp_pkgs[new_pdcp_pkg_ptr].user_id; + rlc_context_t *ctx = &rlc_ctx[uid]; + ctx->latestSduPktRxCycle = benchmark_get_cycle(); +#ifdef RLC_NODE_GUARD + if (uid >= NUM_USERS || + (pdcp_pkgs[new_pdcp_pkg_ptr].src_addr & 0xFF000000) != 0xA0000000 || + (pdcp_pkgs[new_pdcp_pkg_ptr].tgt_addr & 0xFF000000) != 0xB0000000) { + printf_lock_acquire(&printf_lock); + printf("[GUARD][core %u] BAD DESCRIPTOR idx=%d uid=%u src=0x%x tgt=0x%x cyc=%d\n", + core_id, new_pdcp_pkg_ptr, uid, + pdcp_pkgs[new_pdcp_pkg_ptr].src_addr, pdcp_pkgs[new_pdcp_pkg_ptr].tgt_addr, + benchmark_get_cycle()); + printf_lock_release(&printf_lock); + } +#endif - Node *node = (Node *)mm_alloc(); - if (!node) { + // DEBUG_PRINTF_LOCK_ACQUIRE(&printf_lock); + // DEBUG_PRINTF("Producer (core %u): pdcp_receive_pkg id = %d, user_id = %d, pkg_length = %d, src_addr = 0x%x, tgt_addr = 0x%x\n", + // core_id, + // new_pdcp_pkg_ptr, + // pdcp_pkgs[new_pdcp_pkg_ptr].user_id, + // pdcp_pkgs[new_pdcp_pkg_ptr].pkg_length, + // pdcp_pkgs[new_pdcp_pkg_ptr].src_addr, + // pdcp_pkgs[new_pdcp_pkg_ptr].tgt_addr); + // DEBUG_PRINTF_LOCK_RELEASE(&printf_lock); - DEBUG_PRINTF_LOCK_ACQUIRE(&printf_lock); - DEBUG_PRINTF("Producer (core %u): Out of memory\n", core_id); - DEBUG_PRINTF_LOCK_RELEASE(&printf_lock); - delay(200); /* Delay before retrying */ - continue; - } + Node *node = (Node *)mm_alloc(); + if (!node) { - uint32_t timer_body_0, timer_body_1; + DEBUG_PRINTF_LOCK_ACQUIRE(&printf_lock); + DEBUG_PRINTF("Producer (core %u): Out of memory\n", core_id); + DEBUG_PRINTF_LOCK_RELEASE(&printf_lock); - // timer_body_0 = benchmark_get_cycle(); - /* Initialize the node header */ - node->lock = 0; - node->prev = 0; - node->next = 0; - /* Set the payload pointer immediately after the Node structure */ + delay(200); /* Delay before retrying */ + return 0; /* Not done, just out of memory temporarily */ + } + + uint32_t timer_body_0, timer_body_1; + + // timer_body_0 = benchmark_get_cycle(); + /* Initialize the node header */ + node->lock = 0; + node->prev = 0; + node->next = 0; + node->user_id = uid; + /* Set the payload pointer immediately after the Node structure */ + if (new_pdcp_pkg_ptr >= 0) { node->data = (void *)((uint8_t *)(pdcp_pkgs[new_pdcp_pkg_ptr].src_addr)); node->tgt = (void *)((uint8_t *)(pdcp_pkgs[new_pdcp_pkg_ptr].tgt_addr)); node->data_size = pdcp_pkgs[new_pdcp_pkg_ptr].pkg_length; - // timer_body_1 = benchmark_get_cycle(); + /* read one cacheline from node mem */ + RcvPktHeader tmp = *(RcvPktHeader *)node->data; + unsigned int pingflag = ctx->pingFlag; + atomic_store_explicit(&ctx->pingFlag, pingflag, memory_order_relaxed); + atomic_store_explicit(&ctx->recvMaxByte, node->data_size, memory_order_relaxed); + RcvPktHeader *pt = (RcvPktHeader *)((char *)node->data + sizeof(RcvPktHeader)); + /* write 64B data to Node */ + vector_memcpy32_m4_opt((pt + 1), &tmp, sizeof(RcvPktHeader)); + atomic_fetch_add_explicit(&ctx->sduNumCong, 1, memory_order_relaxed); + atomic_store_explicit(&ctx->sudCongState, 1, memory_order_relaxed); + atomic_fetch_add_explicit(&ctx->pktdelayEnqueFlag, 1, memory_order_relaxed); + } + // timer_body_1 = benchmark_get_cycle(); - // DEBUG_PRINTF_LOCK_ACQUIRE(&printf_lock); - // DEBUG_PRINTF("[core %u][bd fill_node] mm_alloc: node = %p, data = 0x%x, tgt = 0x%x, data_size = %zu, bd=%d\n", - // core_id, - // (void *)node, - // node->data, - // node->tgt, - // node->data_size, - // (timer_body_1 - timer_body_0) - // ); - // DEBUG_PRINTF_LOCK_RELEASE(&printf_lock); + // DEBUG_PRINTF_LOCK_ACQUIRE(&printf_lock); + // DEBUG_PRINTF("[core %u][bd fill_node] mm_alloc: node = %p, data = 0x%x, tgt = 0x%x, data_size = %zu, bd=%d\n", + // core_id, + // (void *)node, + // node->data, + // node->tgt, + // node->data_size, + // (timer_body_1 - timer_body_0) + // ); + // DEBUG_PRINTF_LOCK_RELEASE(&printf_lock); - // /* Zero-initialize the payload using our custom mm_memset */ - // mm_memset(node->data, 0, PACKET_SIZE); - /* Append the node to the shared linked list */ - list_push_back(&tosend_llist_lock_2, &rlc_ctx.list, node); + // /* Zero-initialize the payload using our custom mm_memset */ + // mm_memset(node->data, 0, PACKET_SIZE); + /* Append the node to the owning entity's to-send list */ + list_push_back((spinlock_t *)&tosend_llist_lock_2[uid], &ctx->list, node); + atomic_fetch_add_explicit(&ctx->sduBytes, node->data_size, memory_order_relaxed); + atomic_fetch_add_explicit(&ctx->sduNum, 1, memory_order_relaxed); + atomic_fetch_add_explicit(&ctx->recvPdcpPduBytes, node->data_size, memory_order_relaxed); + ctx->lastRcvOrSubmitDataCyc = benchmark_get_cycle() - ctx->latestSduPktRxCycle; - DEBUG_PRINTF_LOCK_ACQUIRE(&printf_lock); - DEBUG_PRINTF("Producer (core %u): added node %p, size = %d, src_addr = 0x%x, tgt_addr = 0x%x\n", - core_id, - (void *)node, - node->data_size, - node->data, - node->tgt); - DEBUG_PRINTF_LOCK_RELEASE(&printf_lock); + atomic_fetch_add_explicit(&ctx->rcvPktNum, 1, memory_order_relaxed); + atomic_fetch_add_explicit(&ctx->rcvPktLength, node->data_size, memory_order_relaxed); + atomic_fetch_add_explicit(&ctx->enQuePktNum, 1, memory_order_relaxed); + atomic_fetch_add_explicit(&ctx->enQuePktLength, node->data_size, memory_order_relaxed); - // Get the pointer to the next PDCP package - new_pdcp_pkg_ptr = pdcp_receive_pkg(core_id, &pdcp_pkd_ptr_lock); - // delay(200); /* Delay between node productions */ - } + DEBUG_PRINTF_LOCK_ACQUIRE(&printf_lock); + DEBUG_PRINTF("Producer (core %u): added node %p, size = %d, src_addr = 0x%x, tgt_addr = 0x%x\n", + core_id, + (void *)node, + node->data_size, + node->data, + node->tgt); + DEBUG_PRINTF_LOCK_RELEASE(&printf_lock); - // Only signal producer_done once every producer core has finished -- - // with multiple producers, the first one to finish must not make the - // consumer(s) exit while other producers are still enqueuing work. - if (atomic_fetch_add_explicit(&producers_finished, 1, memory_order_relaxed) + 1 - == NUM_PRODUCER_CORES) { - atomic_store_explicit(&producer_done, 1, memory_order_relaxed); - } + // delay(200); /* Delay between node productions */ + return 0; } -/* Returns 1 if core_id appears in the given id list. */ -static int core_in_list(const unsigned int core_id, const unsigned int *ids, unsigned int n) { - for (unsigned int i = 0; i < n; i++) { - if (ids[i] == core_id) return 1; +static void pkt_production_and_recycle(const unsigned int core_id) +{ + uint32_t total_cycle = RLC_TOTAL_CYCLE(PRODUCER_CORE_NUM, INPUT_DATARATE); + int this_core_done = 0; + while (1) { + uint32_t start_timecycle = benchmark_get_cycle(); + if (!this_core_done) { + if (producer(core_id) < 0) { + this_core_done = 1; + atomic_fetch_add_explicit(&producer_done, 1, memory_order_relaxed); + } + } + /* UE status report runs on exactly one core -- the first producer in + the list, not core 0: with explicit core lists core 0 need not be a + producer at all, and gating on it would drop the ACK task entirely. */ + if (core_id == producer_core_ids[0]) { + ue_status_rpt(core_id); + } + uint32_t end_timecycle = benchmark_get_cycle(); + /* calculate delay interval */ + uint32_t interval = end_timecycle - start_timecycle; + uint32_t delayCycle = (total_cycle >= interval) ? (total_cycle - interval) : 0; + delay(delayCycle); + + /* Exit only when THIS core has finished producing AND all other + producers are also done. Without the `this_core_done` guard a + slow core would abandon its in-flight work the moment enough + OTHER cores happened to finish first. */ + if (this_core_done && + atomic_load_explicit(&producer_done, memory_order_relaxed) >= PRODUCER_CORE_NUM) { + break; + } } - return 0; } /* cluster_entry() dispatches behavior based on core_id: cores listed in @@ -412,18 +617,24 @@ void cluster_entry(const unsigned int core_id) { } const int is_consumer = core_in_list(core_id, consumer_core_ids, NUM_CONSUMER_CORES); - const int is_producer = !is_consumer && core_in_list(core_id, producer_core_ids, NUM_PRODUCER_CORES); + const int is_producer = !is_consumer && core_in_list(core_id, producer_core_ids, + NUM_PRODUCER_CORES); - if (is_consumer) { + if (is_producer) { + pkt_production_and_recycle(core_id); + } else if (is_consumer) { consumer(core_id); - } else if (is_producer) { - producer(core_id); - } - /* else: idle core for this run -- falls straight through to the - shared barrier below. */ + } /* else: idle core for this run, falls through to the barrier */ snrt_cluster_hw_barrier(); // this can trigger Misaligned Load exception +#ifdef RLC_SELF_CHECK + /* All sends are complete and tgt buffers are stable here. */ + if (core_id == 0) { + self_check(pdcp_pkgs, NUM_PKGS); + } +#endif + if(core_id == 0) { stop_kernel(); } diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.h b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.h index e848947..dc74187 100644 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.h +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.h @@ -29,6 +29,49 @@ #define CACHE_LINE_SIZE 64 // Cache line size in bytes, typically 64 bytes +/* ---- Multi-user / use-case configuration ---------------------------------- + NUM_USERS = number of RLC entities (one per UE). Comes from the generated + data header (ACTIVE_USER_NUMBER); headers generated before the multi-user + extension don't define it, so fall back to the TC1 single-user case. */ +#ifndef ACTIVE_USER_NUMBER +#define ACTIVE_USER_NUMBER 1 +#endif +#define NUM_USERS ACTIVE_USER_NUMBER + +/* Rate pacing. 0 (default): legacy int32 expression, wraps and makes pacing + inert โ€” preserved verbatim so TC1 numbers are bit-identical to the + pre-extension baseline. 1: 64-bit math, pacing actually engages at + INPUT/OUTPUT_DATARATE. */ +#ifndef RLC_ENABLE_PACING +#define RLC_ENABLE_PACING 0 +#endif + +/* Per-user list locks (indexed by RLC entity / user id). */ +static _Atomic mcs_lock_t tosend_llist_lock_2[NUM_USERS] __attribute__((aligned(4))) __attribute__((section(".data"))); +static _Atomic mcs_lock_t sent_llist_lock_2[NUM_USERS] __attribute__((aligned(4))) __attribute__((section(".data"))); + + +typedef struct { + char data[CACHE_LINE_SIZE]; +} RcvPktHeader; + +typedef struct { + char content[CACHE_LINE_SIZE / 2]; +} DlschInd; + +typedef struct { + DlschInd dlschInd; + char reserve[2 * CACHE_LINE_SIZE - sizeof(DlschInd) - 4 * sizeof(uint32_t)]; + uint32_t sduNum; + uint32_t sudBytes; + uint32_t totalPdlLen; + uint32_t rlcDpbPduCnt; +} TestDataStru; + +typedef struct { + char stateRpt[2048]; +} UeStateRpt; + /* rlc_context_t maintains the state of the RLC kernel, including: - rlcId: Unique identifier for the RLC entity. @@ -68,9 +111,22 @@ typedef struct { _Atomic unsigned int pollByte __attribute__((aligned(4))); _Atomic unsigned int pduWithoutPoll __attribute__((aligned(4))); /* Indicates the total number of PDUs that are not polled. */ _Atomic unsigned int byteWithoutPoll __attribute__((aligned(4))); /* Indicates the total bytes of PDUs that are not polled. */ - - // unsigned int sduNum; /* Number of sdus to be sent */ - // unsigned int sduBytes; /* Number of sdus bytes to be sent */ + _Atomic unsigned int pingFlag __attribute__((aligned(4))); + _Atomic unsigned int recvMaxByte __attribute__((aligned(4))); + _Atomic unsigned int sduNumCong __attribute__((aligned(4))); + _Atomic unsigned int sudCongState __attribute__((aligned(4))); + _Atomic unsigned int pktdelayEnqueFlag __attribute__((aligned(4))); + unsigned int latestSduPktRxCycle __attribute__((aligned(4))); + _Atomic unsigned int recvPdcpPduBytes __attribute__((aligned(4))); + unsigned int lastRcvOrSubmitDataCyc __attribute__((aligned(4))); + _Atomic unsigned int sduNum; /* Number of sdus to be sent */ + _Atomic unsigned int sduBytes; /* Number of sdus bytes to be sent */ + + char Reserve0[CACHE_LINE_SIZE-16] __attribute__((aligned(4))); /* Reserved for future use, pieced into a cacheline */ + _Atomic unsigned int rcvPktNum __attribute__((aligned(4))); + _Atomic unsigned int rcvPktLength __attribute__((aligned(4))); + _Atomic unsigned int enQuePktNum __attribute__((aligned(4))); + _Atomic unsigned int enQuePktLength __attribute__((aligned(4))); // void *sduLinkHdr; /* First SDU to be sent */ // void *sduLinkTail; /* Last SDU to be sent */ LinkedList list __attribute__((aligned(4))); @@ -78,17 +134,33 @@ typedef struct { _Atomic unsigned int vtNextAck __attribute__((aligned(4))); /* First SN to be confirmed */ _Atomic unsigned int vtNext __attribute__((aligned(4))); /* Next Available RLCSN */ - // unsigned int sendPduNum; /* Number of pdus to be confirmed */ - // unsigned int sendPduBytes; /* Number of pdus to be confirmed */ + _Atomic unsigned int tbsize; + unsigned int pdcpcount; + unsigned int sendPduNum; /* Number of pdus to be confirmed */ + unsigned int sendPduBytes; /* Number of pdus to be confirmed */ + unsigned int pktdelay; + _Atomic unsigned int rlcthrp; + _Atomic unsigned int dlPduNum; + char Reserve3[CACHE_LINE_SIZE-36] __attribute__((aligned(4))); + unsigned int rlcOm[16]; + unsigned int dlDelayInfo[16]; + // void *waitAckLinkHdr; /* First SDU to be confirmed */ // void *waitAckLinkTail; /* Last SDU to be confirmed */ LinkedList sent_list __attribute__((aligned(4))); - char Reserve2[CACHE_LINE_SIZE-2-sizeof(LinkedList)] __attribute__((aligned(4))); /* Reserved for future use, pieced into a cacheline */ + unsigned int acksn; + unsigned int nackcount; + unsigned int parseindex; + unsigned int rsv3; + char Reserve2[CACHE_LINE_SIZE-16-sizeof(LinkedList)] __attribute__((aligned(4))); /* Reserved for future use, pieced into a cacheline */ mm_context_t *mm_ctx __attribute__((aligned(4))); } rlc_context_t; -rlc_context_t rlc_ctx __attribute__((section(".data"))); +/* One RLC entity per UE. 64-byte alignment gives every entity its own cache + lines (no inter-entity false sharing); at NUM_USERS == 1 the layout is + identical to the single-entity kernel. */ +rlc_context_t rlc_ctx[NUM_USERS] __attribute__((aligned(CACHE_LINE_SIZE))) __attribute__((section(".data"))); /* rlc_init() initializes the RLC context for the given RLC ID and cell ID. It sets the initial values for pollPdu, pollByte, pduWithoutPoll, byteWithoutPoll, @@ -120,7 +192,8 @@ _Atomic(uint32_t) producer_done __attribute__((section(".data"))); /* Number of producer cores that have finished; producer_done is only set once this reaches NUM_PRODUCER_CORES, so multiple producers don't cause the consumer(s) to exit early when just the first one finishes. */ -_Atomic(uint32_t) producers_finished __attribute__((section(".data"))); +/* producers_finished is not needed: `producer_done` below is itself the + count of producers that have finished (see pkt_production_and_recycle). */ spinlock_t rlc_ctx_lock __attribute__((section(".data"))); diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/main.c b/software/rlc/multi_producer_single_consumer_double_linked_list/main.c index 135a5f8..773238c 100644 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/main.c +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/main.c @@ -16,6 +16,10 @@ // Author: Zexin Fu +#include +/* DATAHEADER must be included before the kernel sources so that rlc.c/rlc.h + see NUM_PKGS / PDU_SIZE / ACTIVE_USER_NUMBER (rlc.c has a guarded fallback). */ +#include DATAHEADER #include "kernel/printf_lock.c" #include "kernel/mm.c" #include "kernel/rlc.c" @@ -26,7 +30,6 @@ #include "printf.h" #include "kernel/printf_lock.h" #include "mcs_lock.h" -#include DATAHEADER #define L1LineWidth (512/8) // 512 bits @@ -54,18 +57,25 @@ int main(void) { // Initialize memory management context mm_init(); - // Initialize the RLC context - rlc_init(0, 0, &mm_ctx); + // Initialize all RLC entities (one per UE) + for (unsigned int u = 0; u < NUM_USERS; u++) { + rlc_init(u, 0, &mm_ctx); + } - // // Initialize the linked list for receiving queue - // list_init(&rlc_ctx.list); + // Initialize shared/global resources (single producer-descriptor stream) + pdcp_pkd_ptr = 0; + mcs_lock_init(&pdcp_pkd_ptr_lock); + producer_done = 0; + rlc_ctx_lock = 0; // Initialize locks mm_lock = 0; tosend_llist_lock = 0; sent_llist_lock = 0; - mcs_lock_init(&tosend_llist_lock_2); - mcs_lock_init(&sent_llist_lock_2); + for (unsigned int u = 0; u < NUM_USERS; u++) { + mcs_lock_init(&tosend_llist_lock_2[u]); + mcs_lock_init(&sent_llist_lock_2[u]); + } } // debug_printf_locked("[core %u] pre snrt_cluster_hw_barrier()\n", core_id); diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/script/generate_pdcp_pkg.py b/software/rlc/multi_producer_single_consumer_double_linked_list/script/generate_pdcp_pkg.py index 6ef9992..f6695a7 100755 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/script/generate_pdcp_pkg.py +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/script/generate_pdcp_pkg.py @@ -109,7 +109,11 @@ def main(): # PDU configuration pdu_size = hdr_len + pkg_len - num_src_slots = src_len // pdu_size + # Slot stride: slots must stay 4-byte aligned or the word/vector payload + # copies in the kernel trap on misaligned bases (e.g. 810-byte PDUs). + # The copy length stays pdu_size; padding [pdu_size, pdu_stride) is zero. + pdu_stride = (pdu_size + 3) & ~3 + num_src_slots = src_len // pdu_stride num_pkgs = min(int(cfg.get('total_pkg_number', num_src_slots)), num_src_slots) # Cores that actually run the RLC kernel. Defaults preserve the @@ -135,10 +139,10 @@ def main(): # assemble metadata and data buffer entries = [] - pdu_buf = [[0] * pdu_size for _ in range(num_src_slots)] + pdu_buf = [[0] * pdu_stride for _ in range(num_src_slots)] for uid, slot in zip((random.randrange(active_users) for _ in range(num_pkgs)), slots): - src_addr = src_base + slot * pdu_size - tgt_addr = tgt_base + slot * pdu_size + src_addr = src_base + slot * pdu_stride + tgt_addr = tgt_base + slot * pdu_stride entries.append((uid, src_addr, tgt_addr, pdu_size)) data = slot for i in range(hdr_len, pdu_size): @@ -153,6 +157,8 @@ def main(): h.write('#ifndef PDCP_PKG_H\n') h.write('#define PDCP_PKG_H\n\n') + h.write('#include \n\n') + # type definition h.write('typedef struct {\n') h.write(' int user_id;\n') @@ -164,7 +170,9 @@ def main(): # constants h.write(f'#define NUM_SRC_SLOTS {num_src_slots}\n') h.write(f'#define PDU_SIZE {pdu_size}\n') - h.write(f'#define NUM_PKGS {num_pkgs}\n\n') + h.write(f'#define PDU_STRIDE {pdu_stride}\n') + h.write(f'#define NUM_PKGS {num_pkgs}\n') + h.write(f'#define ACTIVE_USER_NUMBER {active_users}\n\n') # Producer/consumer core selection: any cluster core id not listed # in either array stays idle for this kernel. @@ -186,7 +194,7 @@ def main(): # src data in its own section so .pdcp_src can be located at src_base h.write('static const uint8_t __attribute__((section(".pdcp_src"), used)) ' - 'pdcp_src_data[NUM_SRC_SLOTS][PDU_SIZE] = {\n') + 'pdcp_src_data[NUM_SRC_SLOTS][PDU_STRIDE] = {\n') for slot in range(num_src_slots): if args.fill_zero: row = ', '.join(f'0x{b:02X}' for b in pdu_buf[slot]) diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_48_800_1000.json b/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_48_800_1000.json new file mode 100644 index 0000000..78a6d02 --- /dev/null +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_48_800_1000.json @@ -0,0 +1,18 @@ +{ + "active_user_number": 48, + "pkg_length": 800, + "pdcp_header_length": 10, + "src_addr": "0xA0000000", + "src_length": 16777216, + "tgt_addr": "0xB0000000", + "tgt_length": 16777216, + "total_pkg_number": 1000, + "producer_cores": [ + 0, + 1 + ], + "consumer_cores": [ + 2, + 3 + ] +} diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_48_800_300.json b/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_48_800_300.json new file mode 100644 index 0000000..2f5dfaf --- /dev/null +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_48_800_300.json @@ -0,0 +1,18 @@ +{ + "active_user_number": 48, + "pkg_length": 800, + "pdcp_header_length": 10, + "src_addr": "0xA0000000", + "src_length": 16777216, + "tgt_addr": "0xB0000000", + "tgt_length": 16777216, + "total_pkg_number": 300, + "producer_cores": [ + 0, + 1 + ], + "consumer_cores": [ + 2, + 3 + ] +} From e19293e035c7908bb0ed9af0559841cee7db8d58 Mon Sep 17 00:00:00 2001 From: Zexin Fu Date: Mon, 24 Aug 2026 22:54:03 +0200 Subject: [PATCH 04/48] rlc: fix role dispatch when the data header has no core lists The fallback declared producer_core_ids[NUM_PRODUCER_CORES] = {0, 1}: with a larger PRODUCER_CORE_NUM the array reads past its initializers, so every core above the second dispatches as neither producer nor consumer and the run goes silently idle. Headers generated before the core lists existed hit this as soon as the P/C counts are swept. Derive contiguous ranges in that mode instead of declaring an array, and route both modes through rlc_is_producer / rlc_is_consumer / rlc_consumer_index / rlc_status_core so the entity partition and the status task follow whichever mode is active. --- .../kernel/rlc.c | 76 ++++++++++++++----- 1 file changed, 58 insertions(+), 18 deletions(-) diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.c b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.c index 842e46c..9b8b4a8 100644 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.c +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.c @@ -226,21 +226,27 @@ int __attribute__((noinline)) pdcp_receive_pkg(const unsigned int core_id, volat // spread over specific tiles/groups rather than being forced into contiguous // ranges. PRODUCER_CORE_NUM / CONSUMER_CORE_NUM remain as build-time knobs // for headers generated before the lists existed, and as the pacing divisor. -#ifndef NUM_PRODUCER_CORES -#define NUM_PRODUCER_CORES PRODUCER_CORE_NUM -static const unsigned int producer_core_ids[NUM_PRODUCER_CORES] = {0, 1}; -#endif -#ifndef NUM_CONSUMER_CORES -#define NUM_CONSUMER_CORES CONSUMER_CORE_NUM -static const unsigned int consumer_core_ids[NUM_CONSUMER_CORES] = {2, 3}; -#endif +#if defined(NUM_PRODUCER_CORES) && defined(NUM_CONSUMER_CORES) +/* The data header names the cores explicitly. */ +#define RLC_CORE_LISTS 1 #ifndef PRODUCER_CORE_NUM #define PRODUCER_CORE_NUM NUM_PRODUCER_CORES #endif #ifndef CONSUMER_CORE_NUM #define CONSUMER_CORE_NUM NUM_CONSUMER_CORES #endif +#else +/* Header predates the core lists: fall back to contiguous ranges -- cores + [0, PRODUCER_CORE_NUM) produce and the next CONSUMER_CORE_NUM consume. + Deriving the ranges instead of declaring a fixed id array matters: the array + form would need a literal initializer per core count, and a short one (say + {0,1}) paired with a large PRODUCER_CORE_NUM would read past its + initializers and dispatch silently wrong. */ +#define NUM_PRODUCER_CORES PRODUCER_CORE_NUM +#define NUM_CONSUMER_CORES CONSUMER_CORE_NUM +#endif +#if RLC_CORE_LISTS /* Returns 1 if core_id appears in the given id list. */ static int core_in_list(const unsigned int core_id, const unsigned int *ids, unsigned int n) { for (unsigned int i = 0; i < n; i++) { @@ -249,10 +255,7 @@ static int core_in_list(const unsigned int core_id, const unsigned int *ids, uns return 0; } -/* Position of core_id within a list, or the list length if absent. Consumers - use their index here (not core_id - PRODUCER_CORE_NUM) to pick their share of - the RLC entities, so the partition follows the list rather than assuming the - consumer cores are contiguous. */ +/* Position of core_id within a list, or the list length if absent. */ static unsigned int core_index_in_list(const unsigned int core_id, const unsigned int *ids, unsigned int n) { for (unsigned int i = 0; i < n; i++) { @@ -260,6 +263,45 @@ static unsigned int core_index_in_list(const unsigned int core_id, const unsigne } return n; } +#endif + +/* Role of a core, and a consumer's position among the consumers. The position + is what selects that consumer's share of the RLC entities, so it must follow + the core list when there is one and the contiguous range otherwise. */ +static inline int rlc_is_consumer(const unsigned int core_id) { +#if RLC_CORE_LISTS + return core_in_list(core_id, consumer_core_ids, NUM_CONSUMER_CORES); +#else + return (core_id >= PRODUCER_CORE_NUM) && + (core_id < PRODUCER_CORE_NUM + CONSUMER_CORE_NUM); +#endif +} + +static inline int rlc_is_producer(const unsigned int core_id) { +#if RLC_CORE_LISTS + return !rlc_is_consumer(core_id) && + core_in_list(core_id, producer_core_ids, NUM_PRODUCER_CORES); +#else + return core_id < PRODUCER_CORE_NUM; +#endif +} + +static inline unsigned int rlc_consumer_index(const unsigned int core_id) { +#if RLC_CORE_LISTS + return core_index_in_list(core_id, consumer_core_ids, NUM_CONSUMER_CORES); +#else + return core_id - PRODUCER_CORE_NUM; +#endif +} + +/* The core that runs the UE status task: the first producer, whichever it is. */ +static inline unsigned int rlc_status_core(void) { +#if RLC_CORE_LISTS + return producer_core_ids[0]; +#else + return 0; +#endif +} #define CPU_FREQENCY 1000000000 // 1GHz #define OUTPUT_DATARATE 7000000 @@ -410,8 +452,7 @@ static int rlc_send_pkt(const unsigned int core_id, rlc_context_t *ctx, TestData Rate-limited so the aggregate consumer throughput equals OUTPUT_DATARATE when pacing is enabled. */ static void consumer(const unsigned int core_id) { - const unsigned int c = core_index_in_list(core_id, consumer_core_ids, - NUM_CONSUMER_CORES); + const unsigned int c = rlc_consumer_index(core_id); const unsigned int stride = (CONSUMER_CORE_NUM < NUM_USERS) ? CONSUMER_CORE_NUM : NUM_USERS; const unsigned int first = c % stride; /* first owned user */ unsigned int cursor = first; @@ -584,7 +625,7 @@ static void pkt_production_and_recycle(const unsigned int core_id) /* UE status report runs on exactly one core -- the first producer in the list, not core 0: with explicit core lists core 0 need not be a producer at all, and gating on it would drop the ACK task entirely. */ - if (core_id == producer_core_ids[0]) { + if (core_id == rlc_status_core()) { ue_status_rpt(core_id); } uint32_t end_timecycle = benchmark_get_cycle(); @@ -616,9 +657,8 @@ void cluster_entry(const unsigned int core_id) { start_kernel(); } - const int is_consumer = core_in_list(core_id, consumer_core_ids, NUM_CONSUMER_CORES); - const int is_producer = !is_consumer && core_in_list(core_id, producer_core_ids, - NUM_PRODUCER_CORES); + const int is_consumer = rlc_is_consumer(core_id); + const int is_producer = rlc_is_producer(core_id); if (is_producer) { pkt_production_and_recycle(core_id); From e599df75912d0199da8ed71b887aea22b51d759e Mon Sep 17 00:00:00 2001 From: zexifu Date: Mon, 7 Sep 2026 18:17:12 +0200 Subject: [PATCH 05/48] [RTL] add insitu_cache_ooc_wrapper: OOC timing harness for one L1 cache ctrl Synthesis-only; never instantiated by the design. Replicates one `cb` slice of cachepool_tile.sv -- one cachepool_cache_ctrl, its tag/meta and folded data SRAM macros, and the skew-column grant logic -- with every block port registered. It exists so the backend can iterate on the cache critical path with a small OOC Fusion Compiler run instead of a full group run. Both ends of that path are SRAM macro pins and the cross-way arm goes through the tile's skew-column arbiter, so the harness has to contain the macros and the grant logic; a controller on its own would cut the loop at the block boundary. Keep in sync with cachepool_tile.sv's gen_l1_cache_ctrl slice. --- hardware/src/insitu_cache_ooc_wrapper.sv | 424 +++++++++++++++++++++++ 1 file changed, 424 insertions(+) create mode 100644 hardware/src/insitu_cache_ooc_wrapper.sv diff --git a/hardware/src/insitu_cache_ooc_wrapper.sv b/hardware/src/insitu_cache_ooc_wrapper.sv new file mode 100644 index 0000000..7d82a16 --- /dev/null +++ b/hardware/src/insitu_cache_ooc_wrapper.sv @@ -0,0 +1,424 @@ +// Copyright 2026 ETH Zurich and University of Bologna. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Author: Zexin Fu, ETH Zurich +// +// ----------------------------------------------------------------------------- +// Out-of-context (OOC) timing harness for ONE L1 cache controller slice. +// ----------------------------------------------------------------------------- +// This is a SYNTHESIS-ONLY block. It is never instantiated by the design; it +// exists so the backend can run a small, fast Fusion Compiler job on exactly +// the logic that owns the design's critical path, instead of re-running a whole +// group (16 tiles x 4 cores + NoC) for every RTL experiment. +// +// Post-placement analysis of cachepool_group_noc_wrapper (1 GHz, ssgnp 0.675V +// -40C) showed that ~91% of the design TNS sits on the L1 tag/meta SRAM pins, +// and that the WNS path is a single SAME-CYCLE loop: +// +// meta SRAM Q -> insitu_cache_decoder -> Cache_FSM -> tcdm_data_bank_we_o +// -> any_other_write_in_col -> l1_data_bank_gnt -> i_access_ctrl_for_meta +// -> tcdm_meta_bank_req_o -> meta SRAM address / CEB / clock-gate enable +// +// Both ends of that loop are SRAM macro pins, and the cross-way arm runs +// through the tile's skew-column arbiter. So the harness must contain the +// controller AND its macros AND the grant logic -- a controller alone would cut +// the loop at the block boundary and measure nothing. +// +// Contents (one `cb` slice of cachepool_tile.sv, copied verbatim): +// * 1 x cachepool_cache_ctrl (the logic under test) +// * NumTagBankPerCtrl meta/tag SRAM macros (loop start AND end) +// * the folded/skewed data SRAM macros (tcdm_data_bank_we_o source) +// * any_other_write_in_col + grant propagation (the cross-way arm) +// +// Every block-boundary port is registered inside, so in2reg/reg2out paths +// cannot mask the internal SRAM->SRAM loop: after synthesis the only paths that +// matter are reg2reg and SRAM2SRAM, which is exactly what we want to measure. +// +// KEEP IN SYNC WITH cachepool_tile.sv. The bank/grant code below is a copy of +// the `gen_l1_cache_ctrl` slice; if that changes, change it here too or the OOC +// numbers stop tracking the real design. +// ----------------------------------------------------------------------------- + +module insitu_cache_ooc_wrapper + import cachepool_pkg::*; +#( + /// Folded data bank configuration -- mirror of cachepool_tile.sv. + parameter bit UseFoldedDataBanks = 1'b1, + parameter int unsigned FoldWayGroup = 0, + parameter bit UseHashWaySelect = 1'b1, + parameter bit UseForwardingBuffer = 1'b1, + parameter type impl_in_t = logic, + // Dependent, do not override. + localparam int unsigned NumPorts = NrTCDMPortsPerCore, + localparam int unsigned DataWidth = SpatzDataWidth, + localparam type addr_t = logic [L1AddrWidth-1:0], + localparam type word_t = logic [DataWidth-1:0], + localparam type strb_t = logic [DataWidth/8-1:0], + localparam type tag_data_t = logic [L1TagDataWidth-1:0], + localparam type tcdm_bank_addr_t = logic [$clog2(L1NumSet)-1:0] +) ( + input logic clk_i, + input logic rst_ni, + + // Sync / flush control + input logic cache_sync_valid_i, + output logic cache_sync_ready_o, + input logic [1:0] cache_sync_insn_i, + input tcdm_bank_addr_t bank_depth_for_SPM_i, + + // Core side + input logic [NumPorts-1:0] core_req_valid_i, + output logic [NumPorts-1:0] core_req_ready_o, + input addr_t [NumPorts-1:0] core_req_addr_i, + input tcdm_user_t [NumPorts-1:0] core_req_meta_i, + input logic [NumPorts-1:0] core_req_write_i, + input word_t [NumPorts-1:0] core_req_wdata_i, + input strb_t [NumPorts-1:0] core_req_wstrb_i, + output logic [NumPorts-1:0] core_resp_valid_o, + input logic [NumPorts-1:0] core_resp_ready_i, + output logic [NumPorts-1:0] core_resp_write_o, + output word_t [NumPorts-1:0] core_resp_data_o, + output tcdm_user_t [NumPorts-1:0] core_resp_meta_o, + + // Refill side + output cache_refill_req_chan_t refill_req_o, + output burst_req_t refill_burst_o, + output logic refill_req_valid_o, + input logic refill_req_ready_i, + input cache_refill_rsp_chan_t refill_rsp_i, + input logic refill_rsp_valid_i, + output logic refill_rsp_ready_o +); + + // --------------------------------------------------------------------------- + // Local parameters -- copied from cachepool_tile.sv so the macro geometry and + // the skew mapping are bit-for-bit the ones in the placed netlist. + // --------------------------------------------------------------------------- + localparam int unsigned NumWordPerLine = L1LineWidth / DataWidth; + localparam bit UseSkewedFolded = UseFoldedDataBanks && (L1AssoPerCtrl > 1); + localparam int unsigned DefaultFoldWayGroup = (L1AssoPerCtrl >= 4) ? 4 : 2; + localparam int unsigned EffectiveFoldWayGroup = UseSkewedFolded ? + ((FoldWayGroup == 0) ? DefaultFoldWayGroup : FoldWayGroup) : L1AssoPerCtrl; + localparam int unsigned NumWayGroups = L1AssoPerCtrl / EffectiveFoldWayGroup; + localparam int unsigned PartSplit = UseSkewedFolded ? EffectiveFoldWayGroup : 1; + localparam int unsigned NumDataBankPerWay = NumDataBankPerCtrl / L1AssoPerCtrl; + localparam int unsigned WordsPerPart = NumWordPerLine / PartSplit; + localparam int unsigned BankDataWidth = DataWidth * WordsPerPart; + localparam int unsigned BankByteCount = BankDataWidth / 8; + localparam int unsigned FoldedDataDepth = (L1CacheWayEntry / L1BankFactor) * PartSplit; + localparam int unsigned EffectiveCoalFactor = UseSkewedFolded ? 1 : L1CoalFactor; + + // --------------------------------------------------------------------------- + // Registered block boundary. + // --------------------------------------------------------------------------- + logic sync_valid_q, sync_ready_d; + logic [1:0] sync_insn_q; + tcdm_bank_addr_t spm_depth_q; + + logic [NumPorts-1:0] req_valid_q, req_ready_d, req_write_q; + addr_t [NumPorts-1:0] req_addr_q; + tcdm_user_t [NumPorts-1:0] req_meta_q; + word_t [NumPorts-1:0] req_wdata_q; + strb_t [NumPorts-1:0] req_wstrb_q; + + logic [NumPorts-1:0] rsp_valid_d, rsp_ready_q, rsp_write_d; + word_t [NumPorts-1:0] rsp_data_d; + tcdm_user_t [NumPorts-1:0] rsp_meta_d; + + cache_refill_req_chan_t rfl_req_d; + burst_req_t rfl_burst_d; + logic rfl_req_valid_d, rfl_req_ready_q; + cache_refill_rsp_chan_t rfl_rsp_q; + logic rfl_rsp_valid_q, rfl_rsp_ready_d; + + always_ff @(posedge clk_i or negedge rst_ni) begin : proc_boundary_regs + if (!rst_ni) begin + sync_valid_q <= '0; sync_insn_q <= '0; spm_depth_q <= '0; + req_valid_q <= '0; req_addr_q <= '0; req_meta_q <= '0; + req_write_q <= '0; req_wdata_q <= '0; req_wstrb_q <= '0; + rsp_ready_q <= '0; + rfl_req_ready_q <= '0; rfl_rsp_q <= '0; rfl_rsp_valid_q <= '0; + cache_sync_ready_o <= '0; core_req_ready_o <= '0; + core_resp_valid_o <= '0; core_resp_write_o <= '0; + core_resp_data_o <= '0; core_resp_meta_o <= '0; + refill_req_o <= '0; refill_burst_o <= '0; refill_req_valid_o <= '0; + refill_rsp_ready_o <= '0; + end else begin + // inputs -> internal + sync_valid_q <= cache_sync_valid_i; + sync_insn_q <= cache_sync_insn_i; + spm_depth_q <= bank_depth_for_SPM_i; + req_valid_q <= core_req_valid_i; + req_addr_q <= core_req_addr_i; + req_meta_q <= core_req_meta_i; + req_write_q <= core_req_write_i; + req_wdata_q <= core_req_wdata_i; + req_wstrb_q <= core_req_wstrb_i; + rsp_ready_q <= core_resp_ready_i; + rfl_req_ready_q <= refill_req_ready_i; + rfl_rsp_q <= refill_rsp_i; + rfl_rsp_valid_q <= refill_rsp_valid_i; + // internal -> outputs + cache_sync_ready_o <= sync_ready_d; + core_req_ready_o <= req_ready_d; + core_resp_valid_o <= rsp_valid_d; + core_resp_write_o <= rsp_write_d; + core_resp_data_o <= rsp_data_d; + core_resp_meta_o <= rsp_meta_d; + refill_req_o <= rfl_req_d; + refill_burst_o <= rfl_burst_d; + refill_req_valid_o <= rfl_req_valid_d; + refill_rsp_ready_o <= rfl_rsp_ready_d; + end + end + + // --------------------------------------------------------------------------- + // Bank interface nets (same names/shapes as cachepool_tile.sv, minus [cb]). + // --------------------------------------------------------------------------- + logic [L1AssoPerCtrl-1:0][L1BankFactor-1:0] l1_tag_bank_req; + logic [L1AssoPerCtrl-1:0][L1BankFactor-1:0] l1_tag_bank_we; + tcdm_bank_addr_t [L1AssoPerCtrl-1:0][L1BankFactor-1:0] l1_tag_bank_addr; + tag_data_t [L1AssoPerCtrl-1:0][L1BankFactor-1:0] l1_tag_bank_wdata; + logic [L1AssoPerCtrl-1:0][L1BankFactor-1:0] l1_tag_bank_be; + tag_data_t [L1AssoPerCtrl-1:0][L1BankFactor-1:0] l1_tag_bank_rdata; + + logic [L1AssoPerCtrl-1:0][NumDataBankPerWay-1:0] l1_data_bank_req; + logic [L1AssoPerCtrl-1:0][NumDataBankPerWay-1:0] l1_data_bank_we; + tcdm_bank_addr_t [L1AssoPerCtrl-1:0][NumDataBankPerWay-1:0] l1_data_bank_addr; + word_t [L1AssoPerCtrl-1:0][NumDataBankPerWay-1:0] l1_data_bank_wdata; + logic [L1AssoPerCtrl-1:0][NumDataBankPerWay-1:0][DataWidth/8-1:0] l1_data_bank_be; + word_t [L1AssoPerCtrl-1:0][NumDataBankPerWay-1:0] l1_data_bank_rdata; + logic [L1AssoPerCtrl-1:0][NumDataBankPerWay-1:0] l1_data_bank_gnt; + + // --------------------------------------------------------------------------- + // The DUT. Parameters copied from the cachepool_tile.sv instantiation. + // --------------------------------------------------------------------------- + cachepool_cache_ctrl #( + .NumPorts (NumPorts ), + .CoalExtFactor (EffectiveCoalFactor ), + .AddrWidth (L1AddrWidth ), + .WordWidth (DataWidth ), + .ByteWidth (8 ), + .TagWidth (L1TagDataWidth ), + .NumCacheEntry (L1NumEntryPerCtrl ), + .CacheLineWidth (L1LineWidth ), + .SetAssociativity (L1AssoPerCtrl ), + .DataPartSplit (PartSplit ), + .UseHashWaySelect (UseHashWaySelect ), + .UseForwardingBuffer (UseForwardingBuffer ), + .BankFactor (L1BankFactor ), + .RefillDataWidth (RefillDataWidth ), + .core_meta_t (tcdm_user_t ), + .impl_in_t (impl_in_t ), + .refill_req_t (cache_refill_req_chan_t), + .refill_rsp_t (cache_refill_rsp_chan_t), + .burst_req_t (burst_req_t ) + ) i_l1_controller ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + .cache_sync_valid_i (sync_valid_q ), + .cache_sync_ready_o (sync_ready_d ), + .cache_sync_insn_i (sync_insn_q ), + .bank_depth_for_SPM_i (spm_depth_q ), + + .core_req_valid_i (req_valid_q ), + .core_req_ready_o (req_ready_d ), + .core_req_addr_i (req_addr_q ), + .core_req_meta_i (req_meta_q ), + .core_req_write_i (req_write_q ), + .core_req_wdata_i (req_wdata_q ), + .core_req_wstrb_i (req_wstrb_q ), + + .core_resp_valid_o (rsp_valid_d ), + .core_resp_ready_i (rsp_ready_q ), + .core_resp_write_o (rsp_write_d ), + .core_resp_data_o (rsp_data_d ), + .core_resp_meta_o (rsp_meta_d ), + + .refill_req_o (rfl_req_d ), + .refill_burst_o (rfl_burst_d ), + .refill_req_valid_o (rfl_req_valid_d), + .refill_req_ready_i (rfl_req_ready_q), + .refill_rsp_i (rfl_rsp_q ), + .refill_rsp_valid_i (rfl_rsp_valid_q), + .refill_rsp_ready_o (rfl_rsp_ready_d), + + .impl_i ('0 ), + + .tcdm_tag_bank_req_o (l1_tag_bank_req ), + .tcdm_tag_bank_we_o (l1_tag_bank_we ), + .tcdm_tag_bank_addr_o (l1_tag_bank_addr ), + .tcdm_tag_bank_wdata_o (l1_tag_bank_wdata), + .tcdm_tag_bank_be_o (l1_tag_bank_be ), + .tcdm_tag_bank_rdata_i (l1_tag_bank_rdata), + + .tcdm_data_bank_req_o (l1_data_bank_req ), + .tcdm_data_bank_we_o (l1_data_bank_we ), + .tcdm_data_bank_addr_o (l1_data_bank_addr ), + .tcdm_data_bank_wdata_o(l1_data_bank_wdata), + .tcdm_data_bank_be_o (l1_data_bank_be ), + .tcdm_data_bank_rdata_i(l1_data_bank_rdata), + .tcdm_data_bank_gnt_i (l1_data_bank_gnt ) + ); + + // --------------------------------------------------------------------------- + // Meta / tag SRAM macros -- verbatim from cachepool_tile.sv. + // These are BOTH the launch point and the capture point of the critical loop. + // --------------------------------------------------------------------------- + for (genvar w = 0; w < L1AssoPerCtrl; w++) begin : gen_tag_ways + for (genvar j = 0; j < L1BankFactor; j++) begin : gen_tag_banks + tc_sram_impl #( + .NumWords (L1CacheWayEntry/L1BankFactor), + .DataWidth ($bits(tag_data_t) ), + .ByteWidth ($bits(tag_data_t) ), + .NumPorts (1 ), + .Latency (1 ), + .SimInit ("zeros" ), + .impl_in_t (impl_in_t ) + ) i_meta_bank ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + .impl_i ('0 ), + .impl_o (/* unused */ ), + .req_i (l1_tag_bank_req [w][j]), + .we_i (l1_tag_bank_we [w][j]), + .addr_i (l1_tag_bank_addr [w][j]), + .wdata_i(l1_tag_bank_wdata[w][j]), + .be_i (l1_tag_bank_be [w][j]), + .rdata_o(l1_tag_bank_rdata[w][j]) + ); + end + end + + // --------------------------------------------------------------------------- + // Folded / skewed data SRAM macros + the cross-way grant logic -- + // verbatim from cachepool_tile.sv (gen_folded_data_banks), [cb] removed. + // --------------------------------------------------------------------------- + if (UseSkewedFolded) begin : gen_folded_data_banks + typedef logic [$clog2(FoldedDataDepth)-1:0] folded_bank_addr_t; + + logic [L1AssoPerCtrl-1:0][L1BankFactor-1:0] bank_req; + logic [L1AssoPerCtrl-1:0][L1BankFactor-1:0] bank_we; + folded_bank_addr_t [L1AssoPerCtrl-1:0][L1BankFactor-1:0] bank_addr; + logic [L1AssoPerCtrl-1:0][L1BankFactor-1:0][BankDataWidth-1:0] bank_wdata; + logic [L1AssoPerCtrl-1:0][L1BankFactor-1:0][BankByteCount-1:0] bank_be; + logic [L1AssoPerCtrl-1:0][L1BankFactor-1:0][BankDataWidth-1:0] bank_rdata; + + logic [L1AssoPerCtrl-1:0][L1BankFactor-1:0][PartSplit-1:0] part_req; + logic [L1AssoPerCtrl-1:0][L1BankFactor-1:0][PartSplit-1:0] part_we; + folded_bank_addr_t [L1AssoPerCtrl-1:0][L1BankFactor-1:0][PartSplit-1:0] part_addr; + logic [L1AssoPerCtrl-1:0][L1BankFactor-1:0][PartSplit-1:0][BankDataWidth-1:0] part_wdata; + logic [L1AssoPerCtrl-1:0][L1BankFactor-1:0][PartSplit-1:0][BankByteCount-1:0] part_be; + + logic [L1AssoPerCtrl-1:0][L1AssoPerCtrl-1:0][L1BankFactor-1:0] any_other_write_in_col; + always_comb begin + for (int wW = 0; wW < L1AssoPerCtrl; wW++) begin + for (int col = 0; col < L1AssoPerCtrl; col++) begin + for (int bsel = 0; bsel < L1BankFactor; bsel++) begin + any_other_write_in_col[wW][col][bsel] = 1'b0; + for (int pp = 0; pp < PartSplit; pp++) begin + int unsigned mapped_way; + mapped_way = + (col / EffectiveFoldWayGroup) * EffectiveFoldWayGroup + + ((col - pp + EffectiveFoldWayGroup) % EffectiveFoldWayGroup); + if (mapped_way != wW) begin + any_other_write_in_col[wW][col][bsel] |= part_we[col][bsel][pp]; + end + end + end + end + end + end + + for (genvar group = 0; group < NumWayGroups; group++) begin : gen_skew_groups + for (genvar way = 0; way < EffectiveFoldWayGroup; way++) begin : gen_skew_ways + localparam int unsigned WayIdx = group * EffectiveFoldWayGroup + way; + for (genvar part = 0; part < PartSplit; part++) begin : gen_skew_parts + localparam int unsigned ColIdx = + group * EffectiveFoldWayGroup + ((way + part) % EffectiveFoldWayGroup); + for (genvar bank_sel = 0; bank_sel < L1BankFactor; bank_sel++) begin : gen_skew_banks + localparam int unsigned BankBase = bank_sel * NumWordPerLine + part * WordsPerPart; + assign part_req[ColIdx][bank_sel][part] = + |l1_data_bank_req[WayIdx][BankBase +: WordsPerPart]; + assign part_we[ColIdx][bank_sel][part] = + |l1_data_bank_we [WayIdx][BankBase +: WordsPerPart]; + assign part_addr[ColIdx][bank_sel][part] = + folded_bank_addr_t'((l1_data_bank_addr[WayIdx][BankBase] * PartSplit) + part); + + for (genvar w = 0; w < WordsPerPart; w++) begin : gen_part_words + localparam int unsigned FlatIdx = BankBase + w; + assign part_wdata[ColIdx][bank_sel][part][w*DataWidth +: DataWidth] = + l1_data_bank_wdata[WayIdx][FlatIdx]; + assign part_be[ColIdx][bank_sel][part][w*(DataWidth/8) +: (DataWidth/8)] = + l1_data_bank_be[WayIdx][FlatIdx]; + assign l1_data_bank_rdata[WayIdx][FlatIdx] = + bank_rdata[ColIdx][bank_sel][w*DataWidth +: DataWidth]; + assign l1_data_bank_gnt[WayIdx][FlatIdx] = + l1_data_bank_we[WayIdx][FlatIdx] + | ~any_other_write_in_col[WayIdx][ColIdx][bank_sel]; + end + end + end + end + end + + always_comb begin : select_skewed_part + for (int col = 0; col < L1AssoPerCtrl; col++) begin + for (int bank_sel = 0; bank_sel < L1BankFactor; bank_sel++) begin + automatic logic sel_found; + automatic int unsigned sel_part_idx; + bank_we[col][bank_sel] = |part_we[col][bank_sel]; + bank_req[col][bank_sel] = (|part_we[col][bank_sel]) | (|part_req[col][bank_sel]); + bank_addr[col][bank_sel] = '0; + bank_wdata[col][bank_sel]= '0; + bank_be[col][bank_sel] = '0; + sel_found = 1'b0; + sel_part_idx = 0; + for (int part = 0; part < PartSplit; part++) begin + if (part_we[col][bank_sel][part] && !sel_found) begin + sel_found = 1'b1; sel_part_idx = part; + end + end + if (!sel_found) begin + for (int part = 0; part < PartSplit; part++) begin + if (part_req[col][bank_sel][part] && !sel_found) begin + sel_found = 1'b1; sel_part_idx = part; + end + end + end + if (sel_found) begin + bank_addr [col][bank_sel] = part_addr [col][bank_sel][sel_part_idx]; + bank_wdata[col][bank_sel] = part_wdata[col][bank_sel][sel_part_idx]; + bank_be [col][bank_sel] = part_be [col][bank_sel][sel_part_idx]; + end + end + end + end + + for (genvar col = 0; col < L1AssoPerCtrl; col++) begin : gen_skew_cols + for (genvar bank_sel = 0; bank_sel < L1BankFactor; bank_sel++) begin : gen_skew_col_banks + tc_sram_impl #( + .NumWords (FoldedDataDepth), + .DataWidth (BankDataWidth ), + .ByteWidth (8 ), + .NumPorts (1 ), + .Latency (1 ), + .SimInit ("zeros" ) + ) i_data_bank ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + .impl_i ('0 ), + .impl_o (/* unused */), + .req_i (bank_req [col][bank_sel]), + .we_i (bank_we [col][bank_sel]), + .addr_i (bank_addr [col][bank_sel]), + .wdata_i(bank_wdata[col][bank_sel]), + .be_i (bank_be [col][bank_sel]), + .rdata_o(bank_rdata[col][bank_sel]) + ); + end + end + end + +endmodule From 87ecc8b3560b74d1e59f36af03203cbefcdf06fa Mon Sep 17 00:00:00 2001 From: Zexin Fu Date: Tue, 8 Sep 2026 03:46:40 +0200 Subject: [PATCH 06/48] rlc: AM transport-block assembly (DL) and reassembly (UL) Downlink: 38.322 AMD/STATUS PDU codec, plan/execute split so the serial part (SN order, poll counters, segment boundaries) touches no payload, owner-planned grants, TTI-structured consumer loop. Uplink: scan / reassemble / deliver. The scan is serial by construction -- an AMD header is 3 or 5 bytes depending on SI, so PDU i+1's offset needs PDU i parsed. Fixes found while building the receive side: - SN identifies the SDU, not the PDU: all segments of one SDU share the SN, SO distinguishes them. Both planners advanced it per PDU, so a continuation segment got a fresh SN and a conforming receiver saw an unfillable hole. - UL phase barriers were never armed: snrt_cluster_partial_barrier needs the tile participation mask programmed from rlc_init(), before main's startup hw barrier. Without it the phases silently overlap. - Partial barriers are synchronisation events, not memory fences; fence both sides so the scan buffer is published before it is read. - seen[]/complete[] were uint8_t[64], one cache line written concurrently at byte granularity by every consumer. Now word-sized. - rx_next_highest was a read-modify-write on shared state in the parallel phase; moved to the serial phase. Host tests: planner 589728 checks, uplink 16109 checks (each TB reassembled once whole and once N-way sliced, compared), 0 failures. Legacy loadable image unchanged, bit-exact. --- .../data/data_12_1350_24.h | 99 ++ .../data/data_16_1350_24.h | 99 ++ .../data/data_1_1350_100_p1c1.h | 251 +++++ .../data/data_1_1350_100_p1c3.h | 251 +++++ .../data/data_1_1350_4.h | 59 ++ .../data/data_24_1350_24.h | 99 ++ .../data/data_256_800_300.h | 644 ++++++++++++ .../data/data_32_1350_24.h | 99 ++ .../data/data_48_1350_24.h | 99 ++ .../data/data_48_1350_8.h | 67 ++ .../data/data_8_1350_24.h | 99 ++ .../data/data_8_1350_8.h | 67 ++ .../kernel/llist.c | 50 + .../kernel/llist.h | 45 + .../kernel/rlc.c | 106 +- .../kernel/rlc_am.c | 947 ++++++++++++++++++ .../kernel/rlc_am.h | 306 ++++++ .../kernel/rlc_copy.h | 57 ++ .../kernel/rlc_pdu.h | 184 ++++ .../kernel/rlc_plan.c | 676 +++++++++++++ .../kernel/rlc_plan.h | 200 ++++ .../kernel/rlc_ul.c | 225 +++++ .../kernel/rlc_ul.h | 189 ++++ .../kernel/rlc_ul_drv.c | 336 +++++++ .../kernel/rlc_ul_drv.h | 38 + .../script/pdcp_pkg_12_1350_24.json | 22 + .../script/pdcp_pkg_16_1350_24.json | 22 + .../script/pdcp_pkg_1_1350_100_p1c1.json | 36 + .../script/pdcp_pkg_1_1350_4.json | 22 + .../script/pdcp_pkg_24_1350_24.json | 22 + .../script/pdcp_pkg_256_800_300.json | 10 + .../script/pdcp_pkg_32_1350_24.json | 22 + .../script/pdcp_pkg_48_1350_24.json | 22 + .../script/pdcp_pkg_48_1350_8.json | 22 + .../script/pdcp_pkg_8_1350_24.json | 22 + .../script/pdcp_pkg_8_1350_8.json | 22 + .../test/test_rlc_plan.c | 231 +++++ .../test/test_rlc_ul.c | 204 ++++ 38 files changed, 5970 insertions(+), 1 deletion(-) create mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/data/data_12_1350_24.h create mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/data/data_16_1350_24.h create mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/data/data_1_1350_100_p1c1.h create mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/data/data_1_1350_100_p1c3.h create mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/data/data_1_1350_4.h create mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/data/data_24_1350_24.h create mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/data/data_256_800_300.h create mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/data/data_32_1350_24.h create mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/data/data_48_1350_24.h create mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/data/data_48_1350_8.h create mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/data/data_8_1350_24.h create mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/data/data_8_1350_8.h create mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.c create mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.h create mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_copy.h create mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_pdu.h create mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_plan.c create mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_plan.h create mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_ul.c create mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_ul.h create mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_ul_drv.c create mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_ul_drv.h create mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_12_1350_24.json create mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_16_1350_24.json create mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_1_1350_100_p1c1.json create mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_1_1350_4.json create mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_24_1350_24.json create mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_256_800_300.json create mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_32_1350_24.json create mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_48_1350_24.json create mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_48_1350_8.json create mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_8_1350_24.json create mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_8_1350_8.json create mode 100644 software/tests/multi_producer_single_consumer_double_linked_list/test/test_rlc_plan.c create mode 100644 software/tests/multi_producer_single_consumer_double_linked_list/test/test_rlc_ul.c diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/data/data_12_1350_24.h b/software/rlc/multi_producer_single_consumer_double_linked_list/data/data_12_1350_24.h new file mode 100644 index 0000000..e852b77 --- /dev/null +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/data/data_12_1350_24.h @@ -0,0 +1,99 @@ + +// Copyright 2025 ETH Zurich and University of Bologna. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// Author: Zexin Fu + +#ifndef PDCP_PKG_H +#define PDCP_PKG_H + +#include + +typedef struct { + int user_id; + unsigned int src_addr; + unsigned int tgt_addr; + unsigned int pkg_length; +} pdcp_pkg_t; + +#define NUM_SRC_SLOTS 12336 +#define PDU_SIZE 1360 +#define PDU_STRIDE 1360 +#define NUM_PKGS 24 +#define ACTIVE_USER_NUMBER 12 + +#define NUM_PRODUCER_CORES 2 +static const unsigned int producer_core_ids[NUM_PRODUCER_CORES] = {0, 1}; +#define NUM_CONSUMER_CORES 2 +static const unsigned int consumer_core_ids[NUM_CONSUMER_CORES] = {2, 3}; +#define NUM_RLC_KERNEL_CORES (NUM_PRODUCER_CORES + NUM_CONSUMER_CORES) +static const unsigned int rlc_kernel_core_ids[NUM_RLC_KERNEL_CORES] = {0, 1, 2, 3}; + +static const pdcp_pkg_t __attribute__((section(".pdcp_info"), used)) pdcp_pkgs[NUM_PKGS] = { + { 8, 0xA0D965C0, 0xB0D965C0, 1360 }, + { 3, 0xA025DA00, 0xB025DA00, 1360 }, + { 11, 0xA0087CD0, 0xB0087CD0, 1360 }, + { 10, 0xA0FC1D90, 0xB0FC1D90, 1360 }, + { 11, 0xA05D8220, 0xB05D8220, 1360 }, + { 8, 0xA05341C0, 0xB05341C0, 1360 }, + { 6, 0xA04BE3D0, 0xB04BE3D0, 1360 }, + { 3, 0xA02F7060, 0xB02F7060, 1360 }, + { 7, 0xA0FA64A0, 0xB0FA64A0, 1360 }, + { 9, 0xA022D7B0, 0xB022D7B0, 1360 }, + { 4, 0xA0E613B0, 0xB0E613B0, 1360 }, + { 0, 0xA0FBD330, 0xB0FBD330, 1360 }, + { 2, 0xA0B96B30, 0xB0B96B30, 1360 }, + { 11, 0xA01D8D00, 0xB01D8D00, 1360 }, + { 6, 0xA0C8C120, 0xB0C8C120, 1360 }, + { 5, 0xA08F7000, 0xB08F7000, 1360 }, + { 4, 0xA00ACA80, 0xB00ACA80, 1360 }, + { 2, 0xA00A2080, 0xB00A2080, 1360 }, + { 3, 0xA01FDAB0, 0xB01FDAB0, 1360 }, + { 5, 0xA04A5560, 0xB04A5560, 1360 }, + { 1, 0xA04F15F0, 0xB04F15F0, 1360 }, + { 1, 0xA0ABCE30, 0xB0ABCE30, 1360 }, + { 6, 0xA0CCAD30, 0xB0CCAD30, 1360 }, + { 1, 0xA00901A0, 0xB00901A0, 1360 }, +}; + +static const uint8_t __attribute__((section(".pdcp_src"), used)) pdcp_src_data[NUM_SRC_SLOTS][PDU_STRIDE] = { + [409] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF, 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0xDF, 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF, 0x00, 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writing, software +// distributed under the License distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// Author: Zexin Fu + +#ifndef PDCP_PKG_H +#define PDCP_PKG_H + +#include + +typedef struct { + int user_id; + unsigned int src_addr; + unsigned int tgt_addr; + unsigned int pkg_length; +} pdcp_pkg_t; + +#define NUM_SRC_SLOTS 12336 +#define PDU_SIZE 1360 +#define PDU_STRIDE 1360 +#define NUM_PKGS 24 +#define ACTIVE_USER_NUMBER 16 + +#define NUM_PRODUCER_CORES 2 +static const unsigned int producer_core_ids[NUM_PRODUCER_CORES] = {0, 1}; +#define NUM_CONSUMER_CORES 2 +static const unsigned int consumer_core_ids[NUM_CONSUMER_CORES] = {2, 3}; +#define NUM_RLC_KERNEL_CORES (NUM_PRODUCER_CORES + NUM_CONSUMER_CORES) +static const unsigned int rlc_kernel_core_ids[NUM_RLC_KERNEL_CORES] = {0, 1, 2, 3}; + +static const pdcp_pkg_t __attribute__((section(".pdcp_info"), used)) pdcp_pkgs[NUM_PKGS] = { + { 6, 0xA0D965C0, 0xB0D965C0, 1360 }, + { 13, 0xA025DA00, 0xB025DA00, 1360 }, + { 7, 0xA0087CD0, 0xB0087CD0, 1360 }, + { 14, 0xA0FC1D90, 0xB0FC1D90, 1360 }, + { 8, 0xA05D8220, 0xB05D8220, 1360 }, + { 0, 0xA05341C0, 0xB05341C0, 1360 }, + { 5, 0xA04BE3D0, 0xB04BE3D0, 1360 }, + { 13, 0xA02F7060, 0xB02F7060, 1360 }, + { 10, 0xA0FA64A0, 0xB0FA64A0, 1360 }, + { 8, 0xA022D7B0, 0xB022D7B0, 1360 }, + { 4, 0xA0E613B0, 0xB0E613B0, 1360 }, + { 6, 0xA0FBD330, 0xB0FBD330, 1360 }, + { 10, 0xA0B96B30, 0xB0B96B30, 1360 }, + { 3, 0xA01D8D00, 0xB01D8D00, 1360 }, + { 2, 0xA0C8C120, 0xB0C8C120, 1360 }, + { 12, 0xA08F7000, 0xB08F7000, 1360 }, + { 3, 0xA00ACA80, 0xB00ACA80, 1360 }, + { 11, 0xA00A2080, 0xB00A2080, 1360 }, + { 11, 0xA01FDAB0, 0xB01FDAB0, 1360 }, + { 8, 0xA04A5560, 0xB04A5560, 1360 }, + { 1, 0xA04F15F0, 0xB04F15F0, 1360 }, + { 14, 0xA0ABCE30, 0xB0ABCE30, 1360 }, + { 3, 0xA0CCAD30, 0xB0CCAD30, 1360 }, + { 12, 0xA00901A0, 0xB00901A0, 1360 }, +}; + +static const uint8_t __attribute__((section(".pdcp_src"), used)) pdcp_src_data[NUM_SRC_SLOTS][PDU_STRIDE] = { + [409] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF, 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0xDF, 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 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0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA }, +}; + +#endif // PDCP_PKG_H diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/data/data_1_1350_100_p1c1.h b/software/rlc/multi_producer_single_consumer_double_linked_list/data/data_1_1350_100_p1c1.h new file mode 100644 index 0000000..db75cba --- /dev/null +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/data/data_1_1350_100_p1c1.h @@ -0,0 +1,251 @@ + +// Copyright 2025 ETH Zurich and University of Bologna. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// Author: Zexin Fu + +#ifndef PDCP_PKG_H +#define PDCP_PKG_H + +#include + +typedef struct { + int user_id; + unsigned int src_addr; + unsigned int tgt_addr; + unsigned int pkg_length; +} pdcp_pkg_t; + +#define NUM_SRC_SLOTS 12336 +#define PDU_SIZE 1360 +#define PDU_STRIDE 1360 +#define NUM_PKGS 100 +#define ACTIVE_USER_NUMBER 1 + +#define NUM_PRODUCER_CORES 1 +static const unsigned int producer_core_ids[NUM_PRODUCER_CORES] = {0}; +#define NUM_CONSUMER_CORES 1 +static const unsigned int consumer_core_ids[NUM_CONSUMER_CORES] = {1}; +#define NUM_RLC_KERNEL_CORES (NUM_PRODUCER_CORES + NUM_CONSUMER_CORES) +static const unsigned int rlc_kernel_core_ids[NUM_RLC_KERNEL_CORES] = {0, 1}; + +static const pdcp_pkg_t __attribute__((section(".pdcp_info"), used)) pdcp_pkgs[NUM_PKGS] = { + { 0, 0xA0D965C0, 0xB0D965C0, 1360 }, + { 0, 0xA025DA00, 0xB025DA00, 1360 }, + { 0, 0xA0087CD0, 0xB0087CD0, 1360 }, + { 0, 0xA0FC1D90, 0xB0FC1D90, 1360 }, + { 0, 0xA05D8220, 0xB05D8220, 1360 }, + { 0, 0xA05341C0, 0xB05341C0, 1360 }, + { 0, 0xA04BE3D0, 0xB04BE3D0, 1360 }, + { 0, 0xA02F7060, 0xB02F7060, 1360 }, + { 0, 0xA0FA64A0, 0xB0FA64A0, 1360 }, + { 0, 0xA022D7B0, 0xB022D7B0, 1360 }, + { 0, 0xA0E613B0, 0xB0E613B0, 1360 }, + { 0, 0xA0FBD330, 0xB0FBD330, 1360 }, + { 0, 0xA0B96B30, 0xB0B96B30, 1360 }, + { 0, 0xA01D8D00, 0xB01D8D00, 1360 }, + { 0, 0xA0C8C120, 0xB0C8C120, 1360 }, + { 0, 0xA08F7000, 0xB08F7000, 1360 }, + { 0, 0xA00ACA80, 0xB00ACA80, 1360 }, + { 0, 0xA00A2080, 0xB00A2080, 1360 }, + { 0, 0xA01FDAB0, 0xB01FDAB0, 1360 }, + { 0, 0xA04A5560, 0xB04A5560, 1360 }, + { 0, 0xA04F15F0, 0xB04F15F0, 1360 }, + { 0, 0xA0ABCE30, 0xB0ABCE30, 1360 }, + { 0, 0xA0CCAD30, 0xB0CCAD30, 1360 }, + { 0, 0xA00901A0, 0xB00901A0, 1360 }, + { 0, 0xA0BED070, 0xB0BED070, 1360 }, + { 0, 0xA04396D0, 0xB04396D0, 1360 }, + { 0, 0xA0F370F0, 0xB0F370F0, 1360 }, + { 0, 0xA0DCF230, 0xB0DCF230, 1360 }, + { 0, 0xA0EE70A0, 0xB0EE70A0, 1360 }, + { 0, 0xA0B94600, 0xB0B94600, 1360 }, + { 0, 0xA08EA0D0, 0xB08EA0D0, 1360 }, + { 0, 0xA04AEF70, 0xB04AEF70, 1360 }, + { 0, 0xA098B6B0, 0xB098B6B0, 1360 }, + { 0, 0xA0C856E0, 0xB0C856E0, 1360 }, + { 0, 0xA05E9110, 0xB05E9110, 1360 }, + { 0, 0xA0023320, 0xB0023320, 1360 }, + { 0, 0xA0364430, 0xB0364430, 1360 }, + { 0, 0xA0ED5C60, 0xB0ED5C60, 1360 }, + { 0, 0xA08FAFC0, 0xB08FAFC0, 1360 }, + { 0, 0xA073ABE0, 0xB073ABE0, 1360 }, + { 0, 0xA05E7680, 0xB05E7680, 1360 }, + { 0, 0xA034DAF0, 0xB034DAF0, 1360 }, + { 0, 0xA0493130, 0xB0493130, 1360 }, + { 0, 0xA0726D20, 0xB0726D20, 1360 }, + { 0, 0xA022BD20, 0xB022BD20, 1360 }, + { 0, 0xA01F85B0, 0xB01F85B0, 1360 }, + { 0, 0xA0812900, 0xB0812900, 1360 }, + { 0, 0xA020DF00, 0xB020DF00, 1360 }, + { 0, 0xA07A0AD0, 0xB07A0AD0, 1360 }, + { 0, 0xA074EFF0, 0xB074EFF0, 1360 }, + { 0, 0xA0CD41F0, 0xB0CD41F0, 1360 }, + { 0, 0xA059EB10, 0xB059EB10, 1360 }, + { 0, 0xA00EC130, 0xB00EC130, 1360 }, + { 0, 0xA0F816F0, 0xB0F816F0, 1360 }, + { 0, 0xA09C3330, 0xB09C3330, 1360 }, + { 0, 0xA0B64E50, 0xB0B64E50, 1360 }, + { 0, 0xA02A7010, 0xB02A7010, 1360 }, + { 0, 0xA080AED0, 0xB080AED0, 1360 }, + { 0, 0xA01ACA70, 0xB01ACA70, 1360 }, + { 0, 0xA0BBAE40, 0xB0BBAE40, 1360 }, + { 0, 0xA063ABF0, 0xB063ABF0, 1360 }, + { 0, 0xA0D5B970, 0xB0D5B970, 1360 }, + { 0, 0xA0D24790, 0xB0D24790, 1360 }, + { 0, 0xA07AF490, 0xB07AF490, 1360 }, + { 0, 0xA0C44AF0, 0xB0C44AF0, 1360 }, + { 0, 0xA0415E60, 0xB0415E60, 1360 }, + { 0, 0xA0EF8A30, 0xB0EF8A30, 1360 }, + { 0, 0xA017A2F0, 0xB017A2F0, 1360 }, + { 0, 0xA00F9060, 0xB00F9060, 1360 }, + { 0, 0xA0E0D3A0, 0xB0E0D3A0, 1360 }, + { 0, 0xA04D7790, 0xB04D7790, 1360 }, + { 0, 0xA0626290, 0xB0626290, 1360 }, + { 0, 0xA01B1F70, 0xB01B1F70, 1360 }, + { 0, 0xA04F25E0, 0xB04F25E0, 1360 }, + { 0, 0xA02252E0, 0xB02252E0, 1360 }, + { 0, 0xA08138F0, 0xB08138F0, 1360 }, + { 0, 0xA05E8120, 0xB05E8120, 1360 }, + { 0, 0xA09A2540, 0xB09A2540, 1360 }, + { 0, 0xA0D821B0, 0xB0D821B0, 1360 }, + { 0, 0xA07C08D0, 0xB07C08D0, 1360 }, + { 0, 0xA0374880, 0xB0374880, 1360 }, + { 0, 0xA07DDC50, 0xB07DDC50, 1360 }, + { 0, 0xA078C6C0, 0xB078C6C0, 1360 }, + { 0, 0xA0473880, 0xB0473880, 1360 }, + { 0, 0xA0E3DB40, 0xB0E3DB40, 1360 }, + { 0, 0xA05AC4E0, 0xB05AC4E0, 1360 }, + { 0, 0xA0EE9B20, 0xB0EE9B20, 1360 }, + { 0, 0xA0E866B0, 0xB0E866B0, 1360 }, + { 0, 0xA0DC52D0, 0xB0DC52D0, 1360 }, + { 0, 0xA0184250, 0xB0184250, 1360 }, + { 0, 0xA0CF1AC0, 0xB0CF1AC0, 1360 }, + { 0, 0xA0D7E1F0, 0xB0D7E1F0, 1360 }, + { 0, 0xA03A2AF0, 0xB03A2AF0, 1360 }, + { 0, 0xA0B599B0, 0xB0B599B0, 1360 }, + { 0, 0xA0F7E720, 0xB0F7E720, 1360 }, + { 0, 0xA0533720, 0xB0533720, 1360 }, + { 0, 0xA0378D90, 0xB0378D90, 1360 }, + { 0, 0xA09D2790, 0xB09D2790, 1360 }, + { 0, 0xA080FE80, 0xB080FE80, 1360 }, + { 0, 0xA05BC3E0, 0xB05BC3E0, 1360 }, +}; + +static const uint8_t __attribute__((section(".pdcp_src"), used)) pdcp_src_data[NUM_SRC_SLOTS][PDU_STRIDE] = { + [106] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F, 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F, 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF, 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0xDF, 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 0x5F, 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F, 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F, 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF, 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0xDF, 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 0x5F, 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F, 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F, 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF, 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0xDF, 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 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0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F, 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F, 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA }, +}; + +#endif // PDCP_PKG_H diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/data/data_1_1350_100_p1c3.h b/software/rlc/multi_producer_single_consumer_double_linked_list/data/data_1_1350_100_p1c3.h new file mode 100644 index 0000000..29b5c8c --- /dev/null +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/data/data_1_1350_100_p1c3.h @@ -0,0 +1,251 @@ + +// Copyright 2025 ETH Zurich and University of Bologna. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// Author: Zexin Fu + +#ifndef PDCP_PKG_H +#define PDCP_PKG_H + +#include + +typedef struct { + int user_id; + unsigned int src_addr; + unsigned int tgt_addr; + unsigned int pkg_length; +} pdcp_pkg_t; + +#define NUM_SRC_SLOTS 12336 +#define PDU_SIZE 1360 +#define PDU_STRIDE 1360 +#define NUM_PKGS 100 +#define ACTIVE_USER_NUMBER 1 + +#define NUM_PRODUCER_CORES 1 +static const unsigned int producer_core_ids[NUM_PRODUCER_CORES] = {0}; +#define NUM_CONSUMER_CORES 3 +static const unsigned int consumer_core_ids[NUM_CONSUMER_CORES] = {1, 2, 3}; +#define NUM_RLC_KERNEL_CORES (NUM_PRODUCER_CORES + NUM_CONSUMER_CORES) +static const unsigned int rlc_kernel_core_ids[NUM_RLC_KERNEL_CORES] = {0, 1, 2, 3}; + +static const pdcp_pkg_t __attribute__((section(".pdcp_info"), used)) pdcp_pkgs[NUM_PKGS] = { + { 0, 0xA0D965C0, 0xB0D965C0, 1360 }, + { 0, 0xA025DA00, 0xB025DA00, 1360 }, + { 0, 0xA0087CD0, 0xB0087CD0, 1360 }, + { 0, 0xA0FC1D90, 0xB0FC1D90, 1360 }, + { 0, 0xA05D8220, 0xB05D8220, 1360 }, + { 0, 0xA05341C0, 0xB05341C0, 1360 }, + { 0, 0xA04BE3D0, 0xB04BE3D0, 1360 }, + { 0, 0xA02F7060, 0xB02F7060, 1360 }, + { 0, 0xA0FA64A0, 0xB0FA64A0, 1360 }, + { 0, 0xA022D7B0, 0xB022D7B0, 1360 }, + { 0, 0xA0E613B0, 0xB0E613B0, 1360 }, + { 0, 0xA0FBD330, 0xB0FBD330, 1360 }, + { 0, 0xA0B96B30, 0xB0B96B30, 1360 }, + { 0, 0xA01D8D00, 0xB01D8D00, 1360 }, + { 0, 0xA0C8C120, 0xB0C8C120, 1360 }, + { 0, 0xA08F7000, 0xB08F7000, 1360 }, + { 0, 0xA00ACA80, 0xB00ACA80, 1360 }, + { 0, 0xA00A2080, 0xB00A2080, 1360 }, + { 0, 0xA01FDAB0, 0xB01FDAB0, 1360 }, + { 0, 0xA04A5560, 0xB04A5560, 1360 }, + { 0, 0xA04F15F0, 0xB04F15F0, 1360 }, + { 0, 0xA0ABCE30, 0xB0ABCE30, 1360 }, + { 0, 0xA0CCAD30, 0xB0CCAD30, 1360 }, + { 0, 0xA00901A0, 0xB00901A0, 1360 }, + { 0, 0xA0BED070, 0xB0BED070, 1360 }, + { 0, 0xA04396D0, 0xB04396D0, 1360 }, + { 0, 0xA0F370F0, 0xB0F370F0, 1360 }, + { 0, 0xA0DCF230, 0xB0DCF230, 1360 }, + { 0, 0xA0EE70A0, 0xB0EE70A0, 1360 }, + { 0, 0xA0B94600, 0xB0B94600, 1360 }, + { 0, 0xA08EA0D0, 0xB08EA0D0, 1360 }, + { 0, 0xA04AEF70, 0xB04AEF70, 1360 }, + { 0, 0xA098B6B0, 0xB098B6B0, 1360 }, + { 0, 0xA0C856E0, 0xB0C856E0, 1360 }, + { 0, 0xA05E9110, 0xB05E9110, 1360 }, + { 0, 0xA0023320, 0xB0023320, 1360 }, + { 0, 0xA0364430, 0xB0364430, 1360 }, + { 0, 0xA0ED5C60, 0xB0ED5C60, 1360 }, + { 0, 0xA08FAFC0, 0xB08FAFC0, 1360 }, + { 0, 0xA073ABE0, 0xB073ABE0, 1360 }, + { 0, 0xA05E7680, 0xB05E7680, 1360 }, + { 0, 0xA034DAF0, 0xB034DAF0, 1360 }, + { 0, 0xA0493130, 0xB0493130, 1360 }, + { 0, 0xA0726D20, 0xB0726D20, 1360 }, + { 0, 0xA022BD20, 0xB022BD20, 1360 }, + { 0, 0xA01F85B0, 0xB01F85B0, 1360 }, + { 0, 0xA0812900, 0xB0812900, 1360 }, + { 0, 0xA020DF00, 0xB020DF00, 1360 }, + { 0, 0xA07A0AD0, 0xB07A0AD0, 1360 }, + { 0, 0xA074EFF0, 0xB074EFF0, 1360 }, + { 0, 0xA0CD41F0, 0xB0CD41F0, 1360 }, + { 0, 0xA059EB10, 0xB059EB10, 1360 }, + { 0, 0xA00EC130, 0xB00EC130, 1360 }, + { 0, 0xA0F816F0, 0xB0F816F0, 1360 }, + { 0, 0xA09C3330, 0xB09C3330, 1360 }, + { 0, 0xA0B64E50, 0xB0B64E50, 1360 }, + { 0, 0xA02A7010, 0xB02A7010, 1360 }, + { 0, 0xA080AED0, 0xB080AED0, 1360 }, + { 0, 0xA01ACA70, 0xB01ACA70, 1360 }, + { 0, 0xA0BBAE40, 0xB0BBAE40, 1360 }, + { 0, 0xA063ABF0, 0xB063ABF0, 1360 }, + { 0, 0xA0D5B970, 0xB0D5B970, 1360 }, + { 0, 0xA0D24790, 0xB0D24790, 1360 }, + { 0, 0xA07AF490, 0xB07AF490, 1360 }, + { 0, 0xA0C44AF0, 0xB0C44AF0, 1360 }, + { 0, 0xA0415E60, 0xB0415E60, 1360 }, + { 0, 0xA0EF8A30, 0xB0EF8A30, 1360 }, + { 0, 0xA017A2F0, 0xB017A2F0, 1360 }, + { 0, 0xA00F9060, 0xB00F9060, 1360 }, + { 0, 0xA0E0D3A0, 0xB0E0D3A0, 1360 }, + { 0, 0xA04D7790, 0xB04D7790, 1360 }, + { 0, 0xA0626290, 0xB0626290, 1360 }, + { 0, 0xA01B1F70, 0xB01B1F70, 1360 }, + { 0, 0xA04F25E0, 0xB04F25E0, 1360 }, + { 0, 0xA02252E0, 0xB02252E0, 1360 }, + { 0, 0xA08138F0, 0xB08138F0, 1360 }, + { 0, 0xA05E8120, 0xB05E8120, 1360 }, + { 0, 0xA09A2540, 0xB09A2540, 1360 }, + { 0, 0xA0D821B0, 0xB0D821B0, 1360 }, + { 0, 0xA07C08D0, 0xB07C08D0, 1360 }, + { 0, 0xA0374880, 0xB0374880, 1360 }, + { 0, 0xA07DDC50, 0xB07DDC50, 1360 }, + { 0, 0xA078C6C0, 0xB078C6C0, 1360 }, + { 0, 0xA0473880, 0xB0473880, 1360 }, + { 0, 0xA0E3DB40, 0xB0E3DB40, 1360 }, + { 0, 0xA05AC4E0, 0xB05AC4E0, 1360 }, + { 0, 0xA0EE9B20, 0xB0EE9B20, 1360 }, + { 0, 0xA0E866B0, 0xB0E866B0, 1360 }, + { 0, 0xA0DC52D0, 0xB0DC52D0, 1360 }, + { 0, 0xA0184250, 0xB0184250, 1360 }, + { 0, 0xA0CF1AC0, 0xB0CF1AC0, 1360 }, + { 0, 0xA0D7E1F0, 0xB0D7E1F0, 1360 }, + { 0, 0xA03A2AF0, 0xB03A2AF0, 1360 }, + { 0, 0xA0B599B0, 0xB0B599B0, 1360 }, + { 0, 0xA0F7E720, 0xB0F7E720, 1360 }, + { 0, 0xA0533720, 0xB0533720, 1360 }, + { 0, 0xA0378D90, 0xB0378D90, 1360 }, + { 0, 0xA09D2790, 0xB09D2790, 1360 }, + { 0, 0xA080FE80, 0xB080FE80, 1360 }, + { 0, 0xA05BC3E0, 0xB05BC3E0, 1360 }, +}; + +static const uint8_t __attribute__((section(".pdcp_src"), used)) pdcp_src_data[NUM_SRC_SLOTS][PDU_STRIDE] = { + [106] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F, 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F, 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF, 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0xDF, 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 0x5F, 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F, 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F, 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF, 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0xDF, 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 0x5F, 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F, 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F, 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF, 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0xDF, 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 0x5F, 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F, 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F, 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF, 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0xDF, 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 0x5F, 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F, 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F, 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF, 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0xDF, 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50, 0x51, 0x52, 0x53, 0x54, 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b/software/rlc/multi_producer_single_consumer_double_linked_list/data/data_1_1350_4.h new file mode 100644 index 0000000..3591e07 --- /dev/null +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/data/data_1_1350_4.h @@ -0,0 +1,59 @@ + +// Copyright 2025 ETH Zurich and University of Bologna. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// Author: Zexin Fu + +#ifndef PDCP_PKG_H +#define PDCP_PKG_H + +#include + +typedef struct { + int user_id; + unsigned int src_addr; + unsigned int tgt_addr; + unsigned int pkg_length; +} pdcp_pkg_t; + +#define NUM_SRC_SLOTS 12336 +#define PDU_SIZE 1360 +#define PDU_STRIDE 1360 +#define NUM_PKGS 4 +#define ACTIVE_USER_NUMBER 1 + +#define NUM_PRODUCER_CORES 2 +static const unsigned int producer_core_ids[NUM_PRODUCER_CORES] = {0, 1}; +#define NUM_CONSUMER_CORES 2 +static const unsigned int consumer_core_ids[NUM_CONSUMER_CORES] = {2, 3}; +#define NUM_RLC_KERNEL_CORES (NUM_PRODUCER_CORES + NUM_CONSUMER_CORES) +static const unsigned int rlc_kernel_core_ids[NUM_RLC_KERNEL_CORES] = {0, 1, 2, 3}; + +static const pdcp_pkg_t __attribute__((section(".pdcp_info"), used)) pdcp_pkgs[NUM_PKGS] = { + { 0, 0xA0D965C0, 0xB0D965C0, 1360 }, + { 0, 0xA025DA00, 0xB025DA00, 1360 }, + { 0, 0xA0087CD0, 0xB0087CD0, 1360 }, + { 0, 0xA0FC1D90, 0xB0FC1D90, 1360 }, +}; + +static const uint8_t __attribute__((section(".pdcp_src"), used)) pdcp_src_data[NUM_SRC_SLOTS][PDU_STRIDE] = { + [409] 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b/software/rlc/multi_producer_single_consumer_double_linked_list/data/data_24_1350_24.h new file mode 100644 index 0000000..a236581 --- /dev/null +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/data/data_24_1350_24.h @@ -0,0 +1,99 @@ + +// Copyright 2025 ETH Zurich and University of Bologna. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// Author: Zexin Fu + +#ifndef PDCP_PKG_H +#define PDCP_PKG_H + +#include + +typedef struct { + int user_id; + unsigned int src_addr; + unsigned int tgt_addr; + unsigned int pkg_length; +} pdcp_pkg_t; + +#define NUM_SRC_SLOTS 12336 +#define PDU_SIZE 1360 +#define PDU_STRIDE 1360 +#define NUM_PKGS 24 +#define ACTIVE_USER_NUMBER 24 + +#define NUM_PRODUCER_CORES 2 +static const unsigned int producer_core_ids[NUM_PRODUCER_CORES] = {0, 1}; +#define NUM_CONSUMER_CORES 2 +static const unsigned int consumer_core_ids[NUM_CONSUMER_CORES] = {2, 3}; +#define NUM_RLC_KERNEL_CORES (NUM_PRODUCER_CORES + NUM_CONSUMER_CORES) +static const unsigned int rlc_kernel_core_ids[NUM_RLC_KERNEL_CORES] = {0, 1, 2, 3}; + +static const pdcp_pkg_t __attribute__((section(".pdcp_info"), used)) pdcp_pkgs[NUM_PKGS] = { + { 17, 0xA0D965C0, 0xB0D965C0, 1360 }, + { 6, 0xA025DA00, 0xB025DA00, 1360 }, + { 22, 0xA0087CD0, 0xB0087CD0, 1360 }, + { 20, 0xA0FC1D90, 0xB0FC1D90, 1360 }, + { 22, 0xA05D8220, 0xB05D8220, 1360 }, + { 17, 0xA05341C0, 0xB05341C0, 1360 }, + { 13, 0xA04BE3D0, 0xB04BE3D0, 1360 }, + { 7, 0xA02F7060, 0xB02F7060, 1360 }, + { 14, 0xA0FA64A0, 0xB0FA64A0, 1360 }, + { 18, 0xA022D7B0, 0xB022D7B0, 1360 }, + { 8, 0xA0E613B0, 0xB0E613B0, 1360 }, + { 0, 0xA0FBD330, 0xB0FBD330, 1360 }, + { 5, 0xA0B96B30, 0xB0B96B30, 1360 }, + { 22, 0xA01D8D00, 0xB01D8D00, 1360 }, + { 13, 0xA0C8C120, 0xB0C8C120, 1360 }, + { 10, 0xA08F7000, 0xB08F7000, 1360 }, + { 8, 0xA00ACA80, 0xB00ACA80, 1360 }, + { 4, 0xA00A2080, 0xB00A2080, 1360 }, + { 6, 0xA01FDAB0, 0xB01FDAB0, 1360 }, + { 10, 0xA04A5560, 0xB04A5560, 1360 }, + { 3, 0xA04F15F0, 0xB04F15F0, 1360 }, + { 2, 0xA0ABCE30, 0xB0ABCE30, 1360 }, + { 12, 0xA0CCAD30, 0xB0CCAD30, 1360 }, + { 3, 0xA00901A0, 0xB00901A0, 1360 }, +}; + +static const uint8_t __attribute__((section(".pdcp_src"), used)) pdcp_src_data[NUM_SRC_SLOTS][PDU_STRIDE] = { + [409] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, 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b/software/rlc/multi_producer_single_consumer_double_linked_list/data/data_256_800_300.h @@ -0,0 +1,644 @@ + +// Copyright 2025 ETH Zurich and University of Bologna. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// Author: Zexin Fu + +#ifndef PDCP_PKG_H +#define PDCP_PKG_H + +#include + +typedef struct { + int user_id; + unsigned int src_addr; + unsigned int tgt_addr; + unsigned int pkg_length; +} pdcp_pkg_t; + +#define NUM_SRC_SLOTS 20661 +#define PDU_SIZE 810 +#define PDU_STRIDE 812 +#define NUM_PKGS 300 +#define ACTIVE_USER_NUMBER 256 + +static const pdcp_pkg_t __attribute__((section(".pdcp_info"), used)) pdcp_pkgs[NUM_PKGS] = { + { 20, 0xA02D3300, 0xB02D3300, 810 }, + { 41, 0xA00A25C4, 0xB00A25C4, 810 }, + { 214, 0xA06FA8F0, 0xB06FA8F0, 810 }, + { 161, 0xA0636B20, 0xB0636B20, 810 }, + { 133, 0xA05A9F18, 0xB05A9F18, 810 }, + { 104, 0xA038A5D0, 0xB038A5D0, 810 }, + { 160, 0xA0299B28, 0xB0299B28, 810 }, + { 122, 0xA0DD6968, 0xB0DD6968, 810 }, + { 135, 0xA0234980, 0xB0234980, 810 }, + { 202, 0xA0EFBC9C, 0xB0EFBC9C, 810 }, + { 67, 0xA0AB4B2C, 0xB0AB4B2C, 810 }, + { 153, 0xA00CE5EC, 0xB00CE5EC, 810 }, + { 234, 0xA00C17C0, 0xB00C17C0, 810 }, + { 161, 0xA02609A8, 0xB02609A8, 810 }, + { 37, 0xA058C350, 0xB058C350, 810 }, + { 4, 0xA05E7334, 0xB05E7334, 810 }, + { 234, 0xA0CD2B14, 0xB0CD2B14, 810 }, + { 51, 0xA0F46868, 0xB0F46868, 810 }, + { 37, 0xA00AC45C, 0xB00AC45C, 810 }, + { 109, 0xA0E3DAC8, 0xB0E3DAC8, 810 }, + { 135, 0xA050B8C4, 0xB050B8C4, 810 }, + { 67, 0xA0DD3D00, 0xB0DD3D00, 810 }, + { 178, 0xA0AA5098, 0xB0AA5098, 810 }, + { 35, 0xA0597E74, 0xB0597E74, 810 }, + { 125, 0xA0B65ED4, 0xB0B65ED4, 810 }, + { 189, 0xA0EF3DBC, 0xB0EF3DBC, 810 }, + { 145, 0xA070EFA4, 0xB070EFA4, 810 }, + { 80, 0xA002A070, 0xB002A070, 810 }, + { 224, 0xA040D014, 0xB040D014, 810 }, + { 154, 0xA0AB9420, 0xB0AB9420, 810 }, + { 4, 0xA08A233C, 0xB08A233C, 810 }, + { 153, 0xA070CFEC, 0xB070CFEC, 810 }, + { 53, 0xA03F1D88, 0xB03F1D88, 810 }, + { 68, 0xA0576994, 0xB0576994, 810 }, + { 135, 0xA088A69C, 0xB088A69C, 810 }, + { 59, 0xA0297E9C, 0xB0297E9C, 810 }, + { 54, 0xA025A754, 0xB025A754, 810 }, + { 79, 0xA09A3EAC, 0xB09A3EAC, 810 }, + { 139, 0xA02743AC, 0xB02743AC, 810 }, + { 144, 0xA091BEC4, 0xB091BEC4, 810 }, + { 107, 0xA08BA308, 0xB08BA308, 810 }, + { 175, 0xA0F51A08, 0xB0F51A08, 810 }, + { 104, 0xA06B62A4, 0xB06B62A4, 810 }, + { 135, 0xA011A194, 0xB011A194, 810 }, + { 250, 0xA0BA8568, 0xB0BA8568, 810 }, + { 128, 0xA0D9B504, 0xB0D9B504, 810 }, + { 26, 0xA032ACF8, 0xB032ACF8, 810 }, + { 47, 0xA099ACC4, 0xB099ACC4, 810 }, + { 216, 0xA01FFDC8, 0xB01FFDC8, 810 }, + { 141, 0xA0E0200C, 0xB0E0200C, 810 }, + { 22, 0xA0770508, 0xB0770508, 810 }, + { 1, 0xA0FF3974, 0xB0FF3974, 810 }, + { 170, 0xA0FB1C64, 0xB0FB1C64, 810 }, + { 66, 0xA092D2B8, 0xB092D2B8, 810 }, + { 134, 0xA0EA6588, 0xB0EA6588, 810 }, + { 82, 0xA04E0ED0, 0xB04E0ED0, 810 }, + { 226, 0xA01C3CB4, 0xB01C3CB4, 810 }, + { 218, 0xA01298FC, 0xB01298FC, 810 }, + { 4, 0xA05C8464, 0xB05C8464, 810 }, + { 57, 0xA0757BB8, 0xB0757BB8, 810 }, + { 38, 0xA0206348, 0xB0206348, 810 }, + { 76, 0xA05E8310, 0xB05E8310, 810 }, + { 18, 0xA028FFBC, 0xB028FFBC, 810 }, + { 189, 0xA09A51B4, 0xB09A51B4, 810 }, + { 75, 0xA070D970, 0xB070D970, 810 }, + { 220, 0xA0B8148C, 0xB0B8148C, 810 }, + { 65, 0xA0941C98, 0xB0941C98, 810 }, + { 21, 0xA04206EC, 0xB04206EC, 810 }, + { 157, 0xA0964AD8, 0xB0964AD8, 810 }, + { 186, 0xA0903BCC, 0xB0903BCC, 810 }, + { 20, 0xA0550EEC, 0xB0550EEC, 810 }, + { 183, 0xA06C6390, 0xB06C6390, 810 }, + { 107, 0xA01CFB04, 0xB01CFB04, 810 }, + { 127, 0xA0F74EA0, 0xB0F74EA0, 810 }, + { 52, 0xA04578B4, 0xB04578B4, 810 }, + { 181, 0xA0D8DA28, 0xB0D8DA28, 810 }, + { 208, 0xA063619C, 0xB063619C, 810 }, + { 79, 0xA0425638, 0xB0425638, 810 }, + { 121, 0xA0BBAC64, 0xB0BBAC64, 810 }, + { 83, 0xA09A0BEC, 0xB09A0BEC, 810 }, + { 90, 0xA06D973C, 0xB06D973C, 810 }, + { 211, 0xA0E21EB8, 0xB0E21EB8, 810 }, + { 12, 0xA05928D0, 0xB05928D0, 810 }, + { 91, 0xA083A858, 0xB083A858, 810 }, + { 170, 0xA016B2E0, 0xB016B2E0, 810 }, + { 210, 0xA05CFCEC, 0xB05CFCEC, 810 }, + { 127, 0xA00D05A4, 0xB00D05A4, 810 }, + { 136, 0xA0801080, 0xB0801080, 810 }, + { 81, 0xA0A2DE4C, 0xB0A2DE4C, 810 }, + { 55, 0xA06CB2DC, 0xB06CB2DC, 810 }, + { 195, 0xA01ADCA0, 0xB01ADCA0, 810 }, + { 19, 0xA055A72C, 0xB055A72C, 810 }, + { 240, 0xA0E6454C, 0xB0E6454C, 810 }, + { 113, 0xA07FC134, 0xB07FC134, 810 }, + { 102, 0xA0565274, 0xB0565274, 810 }, + { 235, 0xA0CAAD88, 0xB0CAAD88, 810 }, + { 179, 0xA0A0A030, 0xB0A0A030, 810 }, + { 156, 0xA0BA4924, 0xB0BA4924, 810 }, + { 116, 0xA039FF8C, 0xB039FF8C, 810 }, + { 114, 0xA06B88B4, 0xB06B88B4, 810 }, + { 12, 0xA038AF54, 0xB038AF54, 810 }, + { 98, 0xA0641FEC, 0xB0641FEC, 810 }, + { 204, 0xA0E3E778, 0xB0E3E778, 810 }, + { 168, 0xA0DAD27C, 0xB0DAD27C, 810 }, + { 142, 0xA06AAAAC, 0xB06AAAAC, 810 }, + { 35, 0xA0ED5544, 0xB0ED5544, 810 }, + { 142, 0xA0ADEEC8, 0xB0ADEEC8, 810 }, + { 179, 0xA0ECE96C, 0xB0ECE96C, 810 }, + { 204, 0xA0A22654, 0xB0A22654, 810 }, + { 169, 0xA092F59C, 0xB092F59C, 810 }, + { 14, 0xA0590918, 0xB0590918, 810 }, + { 59, 0xA03826F0, 0xB03826F0, 810 }, + { 133, 0xA0CEDDA0, 0xB0CEDDA0, 810 }, + { 91, 0xA0C85C64, 0xB0C85C64, 810 }, + { 135, 0xA024E5D8, 0xB024E5D8, 810 }, + { 19, 0xA0131E34, 0xB0131E34, 810 }, + { 55, 0xA02C8160, 0xB02C8160, 810 }, + { 222, 0xA03E0CC0, 0xB03E0CC0, 810 }, + { 176, 0xA0FEBDC0, 0xB0FEBDC0, 810 }, + { 160, 0xA040F2F8, 0xB040F2F8, 810 }, + { 223, 0xA0AB648C, 0xB0AB648C, 810 }, + { 59, 0xA0F223F4, 0xB0F223F4, 810 }, + { 197, 0xA019C8AC, 0xB019C8AC, 810 }, + { 97, 0xA09C3700, 0xB09C3700, 810 }, + { 130, 0xA09AED20, 0xB09AED20, 810 }, + { 22, 0xA0F1EE08, 0xB0F1EE08, 810 }, + { 223, 0xA0BE070C, 0xB0BE070C, 810 }, + { 0, 0xA0D6D1F8, 0xB0D6D1F8, 810 }, + { 100, 0xA06611E8, 0xB06611E8, 810 }, + { 186, 0xA0E09BC0, 0xB0E09BC0, 810 }, + { 220, 0xA004A8A0, 0xB004A8A0, 810 }, + { 35, 0xA02E800C, 0xB02E800C, 810 }, + { 169, 0xA0DA0124, 0xB0DA0124, 810 }, + { 160, 0xA06C53B4, 0xB06C53B4, 810 }, + { 63, 0xA08A19B8, 0xB08A19B8, 810 }, + { 153, 0xA02D4934, 0xB02D4934, 810 }, + { 158, 0xA07727EC, 0xB07727EC, 810 }, + { 209, 0xA0B08288, 0xB0B08288, 810 }, + { 167, 0xA04034A8, 0xB04034A8, 810 }, + { 206, 0xA0B83444, 0xB0B83444, 810 }, + { 151, 0xA0015038, 0xB0015038, 810 }, + { 65, 0xA06AED48, 0xB06AED48, 810 }, + { 98, 0xA0CB3C44, 0xB0CB3C44, 810 }, + { 215, 0xA0488828, 0xB0488828, 810 }, + { 194, 0xA0CE1C24, 0xB0CE1C24, 810 }, + { 89, 0xA02B3128, 0xB02B3128, 810 }, + { 154, 0xA0FDDC8C, 0xB0FDDC8C, 810 }, + { 207, 0xA07929C4, 0xB07929C4, 810 }, + { 0, 0xA0F73B98, 0xB0F73B98, 810 }, + { 155, 0xA050BF1C, 0xB050BF1C, 810 }, + { 146, 0xA097CDD0, 0xB097CDD0, 810 }, + { 107, 0xA04194BC, 0xB04194BC, 810 }, + { 220, 0xA0DAFBB8, 0xB0DAFBB8, 810 }, + { 164, 0xA0D750D8, 0xB0D750D8, 810 }, + { 238, 0xA0003918, 0xB0003918, 810 }, + { 226, 0xA0F32B38, 0xB0F32B38, 810 }, + { 226, 0xA083987C, 0xB083987C, 810 }, + { 109, 0xA0C65DB8, 0xB0C65DB8, 810 }, + { 242, 0xA007E7A8, 0xB007E7A8, 810 }, + { 86, 0xA02D68EC, 0xB02D68EC, 810 }, + { 43, 0xA0935E48, 0xB0935E48, 810 }, + { 145, 0xA07CD7D0, 0xB07CD7D0, 810 }, + { 171, 0xA0613688, 0xB0613688, 810 }, + { 47, 0xA0178438, 0xB0178438, 810 }, + { 120, 0xA061C870, 0xB061C870, 810 }, + { 158, 0xA0E65854, 0xB0E65854, 810 }, + { 115, 0xA01FF770, 0xB01FF770, 810 }, + { 101, 0xA022C448, 0xB022C448, 810 }, + { 75, 0xA0C54CF0, 0xB0C54CF0, 810 }, + { 12, 0xA01C16A4, 0xB01C16A4, 810 }, + { 23, 0xA0D84514, 0xB0D84514, 810 }, + { 125, 0xA0330C20, 0xB0330C20, 810 }, + { 243, 0xA0342014, 0xB0342014, 810 }, + { 37, 0xA0C0F6C8, 0xB0C0F6C8, 810 }, + { 233, 0xA0DF3554, 0xB0DF3554, 810 }, + { 212, 0xA04307D8, 0xB04307D8, 810 }, + { 99, 0xA06B9BBC, 0xB06B9BBC, 810 }, + { 196, 0xA0D639B8, 0xB0D639B8, 810 }, + { 253, 0xA0F64430, 0xB0F64430, 810 }, + { 204, 0xA0ABCA0C, 0xB0ABCA0C, 810 }, + { 124, 0xA055FCD0, 0xB055FCD0, 810 }, + { 75, 0xA0DAF234, 0xB0DAF234, 810 }, + { 2, 0xA051A9D4, 0xB051A9D4, 810 }, + { 54, 0xA07E8D88, 0xB07E8D88, 810 }, + { 217, 0xA0A1FD18, 0xB0A1FD18, 810 }, + { 112, 0xA0979B10, 0xB0979B10, 810 }, + { 90, 0xA0B1DC44, 0xB0B1DC44, 810 }, + { 237, 0xA0D21FD4, 0xB0D21FD4, 810 }, + { 25, 0xA0B74CB8, 0xB0B74CB8, 810 }, + { 127, 0xA031207C, 0xB031207C, 810 }, + { 62, 0xA064A524, 0xB064A524, 810 }, + { 233, 0xA05B3758, 0xB05B3758, 810 }, + { 68, 0xA019FE98, 0xB019FE98, 810 }, + { 237, 0xA0894208, 0xB0894208, 810 }, + { 162, 0xA008896C, 0xB008896C, 810 }, + { 226, 0xA0EED83C, 0xB0EED83C, 810 }, + { 218, 0xA0E0E188, 0xB0E0E188, 810 }, + { 228, 0xA05D6BF0, 0xB05D6BF0, 810 }, + { 81, 0xA0EEE818, 0xB0EEE818, 810 }, + { 243, 0xA0596840, 0xB0596840, 810 }, + { 230, 0xA002E964, 0xB002E964, 810 }, + { 132, 0xA01CD1C8, 0xB01CD1C8, 810 }, + { 126, 0xA017E68C, 0xB017E68C, 810 }, + { 141, 0xA05CF03C, 0xB05CF03C, 810 }, + { 248, 0xA01B5B80, 0xB01B5B80, 810 }, + { 122, 0xA00CBFDC, 0xB00CBFDC, 810 }, + { 140, 0xA08625E4, 0xB08625E4, 810 }, + { 225, 0xA01CC1EC, 0xB01CC1EC, 810 }, + { 39, 0xA0D0BC94, 0xB0D0BC94, 810 }, + { 146, 0xA0609E48, 0xB0609E48, 810 }, + { 120, 0xA0710F5C, 0xB0710F5C, 810 }, + { 139, 0xA0C513D8, 0xB0C513D8, 810 }, + { 171, 0xA056FA90, 0xB056FA90, 810 }, + { 163, 0xA0DAEBDC, 0xB0DAEBDC, 810 }, + { 41, 0xA035B614, 0xB035B614, 810 }, + { 70, 0xA0E7D4F4, 0xB0E7D4F4, 810 }, + { 77, 0xA0E9F02C, 0xB0E9F02C, 810 }, + { 118, 0xA0BFE600, 0xB0BFE600, 810 }, + { 196, 0xA062A678, 0xB062A678, 810 }, + { 78, 0xA0C005B8, 0xB0C005B8, 810 }, + { 109, 0xA0A54278, 0xB0A54278, 810 }, + { 32, 0xA04D4D54, 0xB04D4D54, 810 }, + { 212, 0xA0264918, 0xB0264918, 810 }, + { 208, 0xA02759E0, 0xB02759E0, 810 }, + { 169, 0xA0AEFF90, 0xB0AEFF90, 810 }, + { 238, 0xA08FD64C, 0xB08FD64C, 810 }, + { 212, 0xA0ABF674, 0xB0ABF674, 810 }, + { 31, 0xA0A6E528, 0xB0A6E528, 810 }, + { 105, 0xA0BD9B34, 0xB0BD9B34, 810 }, + { 215, 0xA015FE14, 0xB015FE14, 810 }, + { 199, 0xA027F220, 0xB027F220, 810 }, + { 10, 0xA0189B58, 0xB0189B58, 810 }, + { 194, 0xA0A3768C, 0xB0A3768C, 810 }, + { 244, 0xA089C0E8, 0xB089C0E8, 810 }, + { 3, 0xA02C5B50, 0xB02C5B50, 810 }, + { 180, 0xA064F144, 0xB064F144, 810 }, + { 152, 0xA04DC908, 0xB04DC908, 810 }, + { 199, 0xA04D3720, 0xB04D3720, 810 }, + { 214, 0xA0D9BB5C, 0xB0D9BB5C, 810 }, + { 112, 0xA0B62290, 0xB0B62290, 810 }, + { 249, 0xA038E86C, 0xB038E86C, 810 }, + { 112, 0xA0AB4800, 0xB0AB4800, 810 }, + { 139, 0xA04A7D50, 0xB04A7D50, 810 }, + { 223, 0xA07115B4, 0xB07115B4, 810 }, + { 248, 0xA0BBD274, 0xB0BBD274, 810 }, + { 14, 0xA06569CC, 0xB06569CC, 810 }, + { 199, 0xA01E9A88, 0xB01E9A88, 810 }, + { 172, 0xA0B3E7A0, 0xB0B3E7A0, 810 }, + { 207, 0xA0DF6E6C, 0xB0DF6E6C, 810 }, + { 84, 0xA027BF60, 0xB027BF60, 810 }, + { 239, 0xA01487CC, 0xB01487CC, 810 }, + { 65, 0xA0DB776C, 0xB0DB776C, 810 }, + { 13, 0xA005FC04, 0xB005FC04, 810 }, + { 201, 0xA025DD40, 0xB025DD40, 810 }, + { 13, 0xA05FF62C, 0xB05FF62C, 810 }, + { 42, 0xA043838C, 0xB043838C, 810 }, + { 219, 0xA0A4FFDC, 0xB0A4FFDC, 810 }, + { 69, 0xA0C52A0C, 0xB0C52A0C, 810 }, + { 236, 0xA0C36DFC, 0xB0C36DFC, 810 }, + { 93, 0xA056C7D0, 0xB056C7D0, 810 }, + { 25, 0xA0A2D19C, 0xB0A2D19C, 810 }, + { 133, 0xA017CD2C, 0xB017CD2C, 810 }, + { 194, 0xA042D518, 0xB042D518, 810 }, + { 167, 0xA099DC58, 0xB099DC58, 810 }, + { 108, 0xA000DE08, 0xB000DE08, 810 }, + { 232, 0xA09E81CC, 0xB09E81CC, 810 }, + { 167, 0xA06BAB98, 0xB06BAB98, 810 }, + { 172, 0xA0B8B97C, 0xB0B8B97C, 810 }, + { 194, 0xA073CF84, 0xB073CF84, 810 }, + { 142, 0xA0ABBD5C, 0xB0ABBD5C, 810 }, + { 215, 0xA0E1A304, 0xB0E1A304, 810 }, + { 129, 0xA0C595E4, 0xB0C595E4, 810 }, + { 41, 0xA03ED7C0, 0xB03ED7C0, 810 }, + { 240, 0xA04D1768, 0xB04D1768, 810 }, + { 9, 0xA07874F8, 0xB07874F8, 810 }, + { 26, 0xA05860FC, 0xB05860FC, 810 }, + { 179, 0xA017BD50, 0xB017BD50, 810 }, + { 114, 0xA0EB23D8, 0xB0EB23D8, 810 }, + { 35, 0xA0DC1F88, 0xB0DC1F88, 810 }, + { 20, 0xA018BE3C, 0xB018BE3C, 810 }, + { 15, 0xA07F5230, 0xB07F5230, 810 }, + { 126, 0xA01734EC, 0xB01734EC, 810 }, + { 102, 0xA0145B64, 0xB0145B64, 810 }, + { 10, 0xA0ED2C08, 0xB0ED2C08, 810 }, + { 78, 0xA0C19234, 0xB0C19234, 810 }, + { 122, 0xA0CC26FC, 0xB0CC26FC, 810 }, + { 64, 0xA0D7A024, 0xB0D7A024, 810 }, + { 242, 0xA03FE888, 0xB03FE888, 810 }, + { 58, 0xA0171534, 0xB0171534, 810 }, + { 111, 0xA0CE2C00, 0xB0CE2C00, 810 }, + { 238, 0xA020862C, 0xB020862C, 810 }, + { 131, 0xA04B718C, 0xB04B718C, 810 }, + { 188, 0xA01BD0DC, 0xB01BD0DC, 810 }, + { 85, 0xA0F19538, 0xB0F19538, 810 }, + { 58, 0xA01B9498, 0xB01B9498, 810 }, + { 83, 0xA05F7DA4, 0xB05F7DA4, 810 }, + { 159, 0xA0A3EBE8, 0xB0A3EBE8, 810 }, + { 55, 0xA030AB20, 0xB030AB20, 810 }, + { 13, 0xA0E74964, 0xB0E74964, 810 }, + { 159, 0xA063F384, 0xB063F384, 810 }, +}; + +static const uint8_t __attribute__((section(".pdcp_src"), used)) pdcp_src_data[NUM_SRC_SLOTS][PDU_STRIDE] = { + [18] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 0x5F, 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F, 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F, 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF, 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0xDF, 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 0x5F, 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F, 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F, 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF, 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0xDF, 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 0x5F, 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F, 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F, 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF, 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0xDF, 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, 0x30, 0x31, 0x00, 0x00 }, + [70] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 0x5F, 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F, 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F, 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF, 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0xDF, 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 0x5F, 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F, 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F, 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF, 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0xDF, 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 0x5F, 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F, 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F, 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, 0xB0, 0xB1, 0xB2, 0xB3, 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License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// Author: Zexin Fu + +#ifndef PDCP_PKG_H +#define PDCP_PKG_H + +#include + +typedef struct { + int user_id; + unsigned int src_addr; + unsigned int tgt_addr; + unsigned int pkg_length; +} pdcp_pkg_t; + +#define NUM_SRC_SLOTS 12336 +#define PDU_SIZE 1360 +#define PDU_STRIDE 1360 +#define NUM_PKGS 24 +#define ACTIVE_USER_NUMBER 32 + +#define NUM_PRODUCER_CORES 2 +static const unsigned int producer_core_ids[NUM_PRODUCER_CORES] = {0, 1}; +#define NUM_CONSUMER_CORES 2 +static const unsigned int consumer_core_ids[NUM_CONSUMER_CORES] = {2, 3}; +#define NUM_RLC_KERNEL_CORES (NUM_PRODUCER_CORES + NUM_CONSUMER_CORES) +static const unsigned int rlc_kernel_core_ids[NUM_RLC_KERNEL_CORES] = {0, 1, 2, 3}; + +static const pdcp_pkg_t __attribute__((section(".pdcp_info"), used)) pdcp_pkgs[NUM_PKGS] = { + { 12, 0xA0D965C0, 0xB0D965C0, 1360 }, + { 26, 0xA025DA00, 0xB025DA00, 1360 }, + { 14, 0xA0087CD0, 0xB0087CD0, 1360 }, + { 28, 0xA0FC1D90, 0xB0FC1D90, 1360 }, + { 17, 0xA05D8220, 0xB05D8220, 1360 }, + { 0, 0xA05341C0, 0xB05341C0, 1360 }, + { 10, 0xA04BE3D0, 0xB04BE3D0, 1360 }, + { 27, 0xA02F7060, 0xB02F7060, 1360 }, + { 21, 0xA0FA64A0, 0xB0FA64A0, 1360 }, + { 17, 0xA022D7B0, 0xB022D7B0, 1360 }, + { 9, 0xA0E613B0, 0xB0E613B0, 1360 }, + { 13, 0xA0FBD330, 0xB0FBD330, 1360 }, + { 21, 0xA0B96B30, 0xB0B96B30, 1360 }, + { 6, 0xA01D8D00, 0xB01D8D00, 1360 }, + { 5, 0xA0C8C120, 0xB0C8C120, 1360 }, + { 24, 0xA08F7000, 0xB08F7000, 1360 }, + { 6, 0xA00ACA80, 0xB00ACA80, 1360 }, + { 22, 0xA00A2080, 0xB00A2080, 1360 }, + { 22, 0xA01FDAB0, 0xB01FDAB0, 1360 }, + { 16, 0xA04A5560, 0xB04A5560, 1360 }, + { 2, 0xA04F15F0, 0xB04F15F0, 1360 }, + { 29, 0xA0ABCE30, 0xB0ABCE30, 1360 }, + { 7, 0xA0CCAD30, 0xB0CCAD30, 1360 }, + { 24, 0xA00901A0, 0xB00901A0, 1360 }, +}; + +static const uint8_t __attribute__((section(".pdcp_src"), used)) pdcp_src_data[NUM_SRC_SLOTS][PDU_STRIDE] = { + [409] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF, 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0xDF, 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 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under the License distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// Author: Zexin Fu + +#ifndef PDCP_PKG_H +#define PDCP_PKG_H + +#include + +typedef struct { + int user_id; + unsigned int src_addr; + unsigned int tgt_addr; + unsigned int pkg_length; +} pdcp_pkg_t; + +#define NUM_SRC_SLOTS 12336 +#define PDU_SIZE 1360 +#define PDU_STRIDE 1360 +#define NUM_PKGS 24 +#define ACTIVE_USER_NUMBER 48 + +#define NUM_PRODUCER_CORES 2 +static const unsigned int producer_core_ids[NUM_PRODUCER_CORES] = {0, 1}; +#define NUM_CONSUMER_CORES 2 +static const unsigned int consumer_core_ids[NUM_CONSUMER_CORES] = {2, 3}; +#define NUM_RLC_KERNEL_CORES (NUM_PRODUCER_CORES + NUM_CONSUMER_CORES) +static const unsigned int rlc_kernel_core_ids[NUM_RLC_KERNEL_CORES] = {0, 1, 2, 3}; + +static const pdcp_pkg_t __attribute__((section(".pdcp_info"), used)) pdcp_pkgs[NUM_PKGS] = { + { 35, 0xA0D965C0, 0xB0D965C0, 1360 }, + { 12, 0xA025DA00, 0xB025DA00, 1360 }, + { 45, 0xA0087CD0, 0xB0087CD0, 1360 }, + { 41, 0xA0FC1D90, 0xB0FC1D90, 1360 }, + { 44, 0xA05D8220, 0xB05D8220, 1360 }, + { 34, 0xA05341C0, 0xB05341C0, 1360 }, + { 26, 0xA04BE3D0, 0xB04BE3D0, 1360 }, + { 14, 0xA02F7060, 0xB02F7060, 1360 }, + { 28, 0xA0FA64A0, 0xB0FA64A0, 1360 }, + { 37, 0xA022D7B0, 0xB022D7B0, 1360 }, + { 17, 0xA0E613B0, 0xB0E613B0, 1360 }, + { 0, 0xA0FBD330, 0xB0FBD330, 1360 }, + { 10, 0xA0B96B30, 0xB0B96B30, 1360 }, + { 44, 0xA01D8D00, 0xB01D8D00, 1360 }, + { 27, 0xA0C8C120, 0xB0C8C120, 1360 }, + { 21, 0xA08F7000, 0xB08F7000, 1360 }, + { 17, 0xA00ACA80, 0xB00ACA80, 1360 }, + { 9, 0xA00A2080, 0xB00A2080, 1360 }, + { 13, 0xA01FDAB0, 0xB01FDAB0, 1360 }, + { 21, 0xA04A5560, 0xB04A5560, 1360 }, + { 6, 0xA04F15F0, 0xB04F15F0, 1360 }, + { 5, 0xA0ABCE30, 0xB0ABCE30, 1360 }, + { 24, 0xA0CCAD30, 0xB0CCAD30, 1360 }, + { 6, 0xA00901A0, 0xB00901A0, 1360 }, +}; + +static const uint8_t __attribute__((section(".pdcp_src"), used)) pdcp_src_data[NUM_SRC_SLOTS][PDU_STRIDE] = { + [409] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF, 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0xDF, 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 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0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA }, +}; + +#endif // PDCP_PKG_H diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/data/data_48_1350_8.h b/software/rlc/multi_producer_single_consumer_double_linked_list/data/data_48_1350_8.h new file mode 100644 index 0000000..ad5e8a7 --- /dev/null +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/data/data_48_1350_8.h @@ -0,0 +1,67 @@ + +// Copyright 2025 ETH Zurich and University of Bologna. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// Author: Zexin Fu + +#ifndef PDCP_PKG_H +#define PDCP_PKG_H + +#include + +typedef struct { + int user_id; + unsigned int src_addr; + unsigned int tgt_addr; + unsigned int pkg_length; +} pdcp_pkg_t; + +#define NUM_SRC_SLOTS 12336 +#define PDU_SIZE 1360 +#define PDU_STRIDE 1360 +#define NUM_PKGS 8 +#define ACTIVE_USER_NUMBER 48 + +#define NUM_PRODUCER_CORES 2 +static const unsigned int producer_core_ids[NUM_PRODUCER_CORES] = {0, 1}; +#define NUM_CONSUMER_CORES 2 +static const unsigned int consumer_core_ids[NUM_CONSUMER_CORES] = {2, 3}; +#define NUM_RLC_KERNEL_CORES (NUM_PRODUCER_CORES + NUM_CONSUMER_CORES) +static const unsigned int rlc_kernel_core_ids[NUM_RLC_KERNEL_CORES] = {0, 1, 2, 3}; + +static const pdcp_pkg_t __attribute__((section(".pdcp_info"), used)) pdcp_pkgs[NUM_PKGS] = { + { 47, 0xA0D965C0, 0xB0D965C0, 1360 }, + { 6, 0xA025DA00, 0xB025DA00, 1360 }, + { 43, 0xA0087CD0, 0xB0087CD0, 1360 }, + { 47, 0xA0FC1D90, 0xB0FC1D90, 1360 }, + { 34, 0xA05D8220, 0xB05D8220, 1360 }, + { 5, 0xA05341C0, 0xB05341C0, 1360 }, + { 37, 0xA04BE3D0, 0xB04BE3D0, 1360 }, + { 27, 0xA02F7060, 0xB02F7060, 1360 }, +}; + +static const uint8_t __attribute__((section(".pdcp_src"), used)) pdcp_src_data[NUM_SRC_SLOTS][PDU_STRIDE] = { + [409] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF, 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0xDF, 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 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// PDCP_PKG_H diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/data/data_8_1350_24.h b/software/rlc/multi_producer_single_consumer_double_linked_list/data/data_8_1350_24.h new file mode 100644 index 0000000..a7ba30e --- /dev/null +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/data/data_8_1350_24.h @@ -0,0 +1,99 @@ + +// Copyright 2025 ETH Zurich and University of Bologna. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// Author: Zexin Fu + +#ifndef PDCP_PKG_H +#define PDCP_PKG_H + +#include + +typedef struct { + int user_id; + unsigned int src_addr; + unsigned int tgt_addr; + unsigned int pkg_length; +} pdcp_pkg_t; + +#define NUM_SRC_SLOTS 12336 +#define PDU_SIZE 1360 +#define PDU_STRIDE 1360 +#define NUM_PKGS 24 +#define ACTIVE_USER_NUMBER 8 + +#define NUM_PRODUCER_CORES 2 +static const unsigned int producer_core_ids[NUM_PRODUCER_CORES] = {0, 1}; +#define NUM_CONSUMER_CORES 2 +static const unsigned int consumer_core_ids[NUM_CONSUMER_CORES] = {2, 3}; +#define NUM_RLC_KERNEL_CORES (NUM_PRODUCER_CORES + NUM_CONSUMER_CORES) +static const unsigned int rlc_kernel_core_ids[NUM_RLC_KERNEL_CORES] = {0, 1, 2, 3}; + +static const pdcp_pkg_t __attribute__((section(".pdcp_info"), used)) pdcp_pkgs[NUM_PKGS] = { + { 3, 0xA0D965C0, 0xB0D965C0, 1360 }, + { 6, 0xA025DA00, 0xB025DA00, 1360 }, + { 3, 0xA0087CD0, 0xB0087CD0, 1360 }, + { 7, 0xA0FC1D90, 0xB0FC1D90, 1360 }, + { 4, 0xA05D8220, 0xB05D8220, 1360 }, + { 0, 0xA05341C0, 0xB05341C0, 1360 }, + { 2, 0xA04BE3D0, 0xB04BE3D0, 1360 }, + { 6, 0xA02F7060, 0xB02F7060, 1360 }, + { 5, 0xA0FA64A0, 0xB0FA64A0, 1360 }, + { 4, 0xA022D7B0, 0xB022D7B0, 1360 }, + { 2, 0xA0E613B0, 0xB0E613B0, 1360 }, + { 3, 0xA0FBD330, 0xB0FBD330, 1360 }, + { 5, 0xA0B96B30, 0xB0B96B30, 1360 }, + { 1, 0xA01D8D00, 0xB01D8D00, 1360 }, + { 1, 0xA0C8C120, 0xB0C8C120, 1360 }, + { 6, 0xA08F7000, 0xB08F7000, 1360 }, + { 1, 0xA00ACA80, 0xB00ACA80, 1360 }, + { 5, 0xA00A2080, 0xB00A2080, 1360 }, + { 5, 0xA01FDAB0, 0xB01FDAB0, 1360 }, + { 4, 0xA04A5560, 0xB04A5560, 1360 }, + { 0, 0xA04F15F0, 0xB04F15F0, 1360 }, + { 7, 0xA0ABCE30, 0xB0ABCE30, 1360 }, + { 1, 0xA0CCAD30, 0xB0CCAD30, 1360 }, + { 6, 0xA00901A0, 0xB00901A0, 1360 }, +}; + +static const uint8_t __attribute__((section(".pdcp_src"), used)) pdcp_src_data[NUM_SRC_SLOTS][PDU_STRIDE] = { + [409] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 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b/software/rlc/multi_producer_single_consumer_double_linked_list/data/data_8_1350_8.h new file mode 100644 index 0000000..0783b6d --- /dev/null +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/data/data_8_1350_8.h @@ -0,0 +1,67 @@ + +// Copyright 2025 ETH Zurich and University of Bologna. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// Author: Zexin Fu + +#ifndef PDCP_PKG_H +#define PDCP_PKG_H + +#include + +typedef struct { + int user_id; + unsigned int src_addr; + unsigned int tgt_addr; + unsigned int pkg_length; +} pdcp_pkg_t; + +#define NUM_SRC_SLOTS 12336 +#define PDU_SIZE 1360 +#define PDU_STRIDE 1360 +#define NUM_PKGS 8 +#define ACTIVE_USER_NUMBER 8 + +#define NUM_PRODUCER_CORES 2 +static const unsigned int producer_core_ids[NUM_PRODUCER_CORES] = {0, 1}; +#define NUM_CONSUMER_CORES 2 +static const unsigned int consumer_core_ids[NUM_CONSUMER_CORES] = {2, 3}; +#define NUM_RLC_KERNEL_CORES (NUM_PRODUCER_CORES + NUM_CONSUMER_CORES) +static const unsigned int rlc_kernel_core_ids[NUM_RLC_KERNEL_CORES] = {0, 1, 2, 3}; + +static const pdcp_pkg_t __attribute__((section(".pdcp_info"), used)) pdcp_pkgs[NUM_PKGS] = { + { 1, 0xA0D965C0, 0xB0D965C0, 1360 }, + { 1, 0xA025DA00, 0xB025DA00, 1360 }, + { 6, 0xA0087CD0, 0xB0087CD0, 1360 }, + { 0, 0xA0FC1D90, 0xB0FC1D90, 1360 }, + { 0, 0xA05D8220, 0xB05D8220, 1360 }, + { 1, 0xA05341C0, 0xB05341C0, 1360 }, + { 3, 0xA04BE3D0, 0xB04BE3D0, 1360 }, + { 3, 0xA02F7060, 0xB02F7060, 1360 }, +}; + +static const uint8_t __attribute__((section(".pdcp_src"), used)) pdcp_src_data[NUM_SRC_SLOTS][PDU_STRIDE] = { + [409] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF, 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0xDF, 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 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0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 0x5F, 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F, 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F, 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA }, +}; + +#endif // PDCP_PKG_H diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/llist.c b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/llist.c index f6edc27..28b5977 100644 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/llist.c +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/llist.c @@ -109,6 +109,56 @@ void list_push_back(spinlock_t *llist_lock, LinkedList *list, volatile Node *nod // DEBUG_PRINTF_LOCK_RELEASE(&printf_lock); } +/* Only built for the AM path: emitting it unconditionally would shift every + address in the legacy binary and perturb its cycle baseline. */ +#if defined(RLC_TB_MODE) && (RLC_TB_MODE == 1) +unsigned int list_peek_n(spinlock_t *llist_lock, LinkedList *list, Node **out, + unsigned int max) { + unsigned int n = 0; +#ifdef USE_MCS_LOCK + mcs_lock_acquire(llist_lock, 10); +#else + spin_lock(llist_lock, 10); +#endif + for (Node *p = list->head; p != NULL && n < max; p = p->next) { + out[n++] = p; + } +#ifdef USE_MCS_LOCK + mcs_lock_release(llist_lock, 10); +#else + spin_unlock(llist_lock, 10); +#endif + return n; +} +#endif /* RLC_TB_MODE == AM */ + +#if defined(RLC_TB_MODE) && (RLC_TB_MODE == 1) +unsigned int list_peek_budget(spinlock_t *llist_lock, LinkedList *list, + Node **out, unsigned int max, unsigned int budget, + unsigned int overhead) { + unsigned int n = 0; + unsigned int acc = 0; +#ifdef USE_MCS_LOCK + mcs_lock_acquire(llist_lock, 10); +#else + spin_lock(llist_lock, 10); +#endif + for (Node *p = list->head; p != NULL && n < max; p = p->next) { + out[n++] = p; + acc += overhead + (unsigned int)p->data_size; + /* The node that crosses the budget is kept: it is the one the planner + may segment. Anything past it cannot appear in this grant. */ + if (acc >= budget) break; + } +#ifdef USE_MCS_LOCK + mcs_lock_release(llist_lock, 10); +#else + spin_unlock(llist_lock, 10); +#endif + return n; +} +#endif /* RLC_TB_MODE == AM */ + Node *list_pop_front(spinlock_t *llist_lock, LinkedList *list) { uint32_t core_id = snrt_cluster_core_idx(); uint32_t timer_ac_lock_0, timer_ac_lock_1; diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/llist.h b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/llist.h index f4b81d4..5f94a6a 100644 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/llist.h +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/llist.h @@ -65,6 +65,15 @@ typedef struct Node { size_t data_size; /* Size of the payload in bytes */ spinlock_t lock; /* Perโ€‘node lock (0: unlocked, 1: locked) */ uint32_t user_id; /* Owning RLC entity / UE (instrumentation + multi-user routing) */ +#if defined(RLC_TB_MODE) && (RLC_TB_MODE == 1) + /* AM only: SN of this SDU's final segment, stamped when the SDU is fully + transmitted. A STATUS PDU may only release the SDU once every segment + it was split into has been acknowledged, and with segmentation the SDU + count and the SN count diverge -- so the SN has to travel with the node. + Guarded so the legacy build keeps its exact Node layout, which sets + PAGE_SIZE and hence the whole memory-pool geometry. */ + uint32_t last_sn; +#endif } Node; /* Doublyโ€‘linked list structure for storing Node pointers. @@ -97,6 +106,42 @@ void list_push_back(spinlock_t *llist_lock, LinkedList *list, volatile Node *nod */ Node *list_pop_front(spinlock_t *llist_lock, LinkedList *list); +/* + list_peek_n() walks up to `max` nodes from the head without removing any, + writing them into `out`. Returns how many were written. + + The AM grant planner needs to look ahead over several queued SDUs to decide + where the grant boundary and the segment split fall, but it must not detach + them: a partially transmitted SDU has to stay at the head of the list until + its last segment is sent. Popping and re-inserting would need a push_front + and would reorder against concurrent producers. +*/ +/* `1` is RLC_TB_MODE_AM (rlc_am.h). Spelled numerically because llist.h is + pulled in via mm.h before that header is seen, so the symbolic name is not + yet defined here; RLC_TB_MODE itself always comes from the build (-D), so + every translation unit agrees regardless of include order. */ +#if defined(RLC_TB_MODE) && (RLC_TB_MODE == 1) +unsigned int list_peek_n(spinlock_t *llist_lock, LinkedList *list, Node **out, + unsigned int max); + +/* + list_peek_budget() is list_peek_n() that stops once the walked SDUs can no + longer fit in `budget` bytes, counting `overhead` bytes of header per SDU. + It includes the first node that overflows -- that one is the segmentation + candidate -- and then stops. + + Walking the queue is a dependent pointer chase, one cache miss per node, and + it is the dominant serial cost of a planning attempt (measured: it is where + RTL spends essentially all of its time in rlc_am_try_plan). Gathering + `max` nodes when the grant can only hold a handful wastes that cost + proportionally -- at an 8 KiB grant and 1360-byte SDUs it is 128 nodes + walked to plan 6. +*/ +unsigned int list_peek_budget(spinlock_t *llist_lock, LinkedList *list, + Node **out, unsigned int max, unsigned int budget, + unsigned int overhead); +#endif + /* list_remove() removes a specific Node from anywhere in the list. This function adjusts the pointers of neighboring nodes appropriately. diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.c b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.c index 9b8b4a8..7fffcc9 100644 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.c +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.c @@ -26,6 +26,11 @@ // #define USE_MCS_LOCK_2 #include "rlc.h" +#include "rlc_am.h" /* RLC_TB_MODE and the AM entity API (impl included below) */ +#include "rlc_ul.h" /* RLC_UL_MODE and the uplink API (impl included below) */ +#if RLC_UL_MODE +#include "rlc_ul_drv.h" /* rlc_ul_init() must be reachable from rlc_init() below */ +#endif #include "mm.h" #include "llist.c" #include "data_move_vec.c" @@ -166,6 +171,17 @@ void rlc_init(const unsigned int rlcId, const unsigned int cellId, mm_context_t // Set the memory management context ctx->mm_ctx = mm_ctx; + +#if RLC_TB_MODE == RLC_TB_MODE_AM + rlc_am_init(rlcId); +#endif +#if RLC_UL_MODE + /* Uplink init must happen HERE, not lazily on entry to the consumer: it + programmes the cluster tile participation mask, and main.c's startup + snrt_cluster_hw_barrier() right after this is the resync point the + partial-barrier API requires before that mask can be relied on. */ + if (rlcId == 0u) rlc_ul_init(); +#endif } int __attribute__((noinline)) pdcp_receive_pkg(const unsigned int core_id, volatile int *lock) { @@ -294,6 +310,19 @@ static inline unsigned int rlc_consumer_index(const unsigned int core_id) { #endif } +/* The number of consumers that actually exist. + + CONSUMER_CORE_NUM is a build define and may exceed the length of the data + header's consumer_core_ids list, which is what dispatch really follows. Any + arithmetic that partitions work *across consumers* must use this, not the + define: sizing a partition by the define while only the listed cores exist + leaves the surplus shares with no core to claim them. */ +#if RLC_CORE_LISTS +#define RLC_ACTUAL_CONSUMERS NUM_CONSUMER_CORES +#else +#define RLC_ACTUAL_CONSUMERS CONSUMER_CORE_NUM +#endif + /* The core that runs the UE status task: the first producer, whichever it is. */ static inline unsigned int rlc_status_core(void) { #if RLC_CORE_LISTS @@ -303,6 +332,21 @@ static inline unsigned int rlc_status_core(void) { #endif } +/* AM transport-block assembly. Included here, after the core-role helpers, so + rlc_ctx[], the per-user list locks and rlc_consumer_index() are in scope. */ +#if RLC_TB_MODE == RLC_TB_MODE_AM +#include "rlc_am.c" +#endif + +/* Uplink. Needs the same helpers, plus consumer_core_ids for the partial + barrier -- hence the core-list requirement. */ +#if RLC_UL_MODE +#if !RLC_CORE_LISTS +#error "RLC_UL_MODE needs RLC_CORE_LISTS: the UL barrier set comes from consumer_core_ids" +#endif +#include "rlc_ul_drv.c" +#endif + #define CPU_FREQENCY 1000000000 // 1GHz #define OUTPUT_DATARATE 7000000 #define INPUT_DATARATE 7000000 @@ -320,6 +364,15 @@ static inline unsigned int rlc_status_core(void) { void ue_status_rpt(const unsigned int core_id) { +#if RLC_TB_MODE == RLC_TB_MODE_AM + /* AM builds and parses a real STATUS PDU and releases SDUs by SN. The + legacy model below acknowledges a fixed two *nodes* per pass and + advances vtNextAck by two, which stops meaning anything once + segmentation makes the SDU count and the SN count diverge. */ + (void)core_id; + rlc_am_status(); + return; +#else // Simulate receiving ACK from UE after certain sent pkgs, per RLC entity. // ACK_SN is ctx->vtNextAck+2. Core 0 scans all users each call (single // writer per entity; striping across producer cores is a future option). @@ -357,6 +410,7 @@ void ue_status_rpt(const unsigned int core_id) } } } +#endif /* RLC_TB_MODE */ } /* Pop one node from entity ctx's to-send list and assemble/send its PDU. @@ -451,6 +505,44 @@ static int rlc_send_pkt(const unsigned int core_id, rlc_context_t *ctx, TestData (no sduNum pre-check) to keep the idle lock traffic of the baseline. Rate-limited so the aggregate consumer throughput equals OUTPUT_DATARATE when pacing is enabled. */ +#if RLC_UL_MODE +/* Uplink mode: the consumer set runs receive/reassemble/deliver slots instead + of downlink assembly. Producers still run their normal path -- they are the + source of the payload the uplink harness retransmits. */ +static void consumer(const unsigned int core_id) { rlc_ul_consumer(core_id); } +#elif RLC_TB_MODE == RLC_TB_MODE_AM +static void consumer(const unsigned int core_id) { + /* Grant-based assembly: plan (owner) + execute (all cores) + commit. */ +#if RLC_AM_TTI && RLC_CORE_LISTS + /* TTI-structured: the three phases are separated by a partial barrier over + the consumer set, so a helper with nothing to do blocks rather than + sweeping the entity list. Requires explicit core lists, which is where + the barrier participant set comes from. */ +#ifdef RLC_SELF_CHECK + printf_lock_acquire(&printf_lock); + printf("[AM] core %u: consumer idx=%u (TTI mode)\n", core_id, + rlc_consumer_index(core_id)); + printf_lock_release(&printf_lock); +#endif + rlc_am_consumer_tti(core_id); + return; +#endif +#ifdef RLC_SELF_CHECK + printf_lock_acquire(&printf_lock); + printf("[AM] core %u: consumer idx=%u\n", core_id, + rlc_consumer_index(core_id)); + printf_lock_release(&printf_lock); +#endif + while (1) { + rlc_am_step(core_id); + if (atomic_load_explicit(&producer_done, memory_order_relaxed) >= + PRODUCER_CORE_NUM && + rlc_am_idle()) { + break; + } + } +} +#else static void consumer(const unsigned int core_id) { const unsigned int c = rlc_consumer_index(core_id); const unsigned int stride = (CONSUMER_CORE_NUM < NUM_USERS) ? CONSUMER_CORE_NUM : NUM_USERS; @@ -486,6 +578,7 @@ static void consumer(const unsigned int core_id) { } } } +#endif /* RLC_TB_MODE */ /* Producer behavior (runs on cores other than 0) */ /* Returns 0 on success, -1 when no more packages available. */ @@ -587,6 +680,10 @@ static int producer(const unsigned int core_id) { // mm_memset(node->data, 0, PACKET_SIZE); /* Append the node to the owning entity's to-send list */ list_push_back((spinlock_t *)&tosend_llist_lock_2[uid], &ctx->list, node); +#if (RLC_TB_MODE == RLC_TB_MODE_AM) && RLC_AM_WORKQ + /* Announce the entity so an owner picks it up without scanning. */ + rlc_am_mark_ready(uid); +#endif atomic_fetch_add_explicit(&ctx->sduBytes, node->data_size, memory_order_relaxed); atomic_fetch_add_explicit(&ctx->sduNum, 1, memory_order_relaxed); atomic_fetch_add_explicit(&ctx->recvPdcpPduBytes, node->data_size, memory_order_relaxed); @@ -668,7 +765,14 @@ void cluster_entry(const unsigned int core_id) { snrt_cluster_hw_barrier(); // this can trigger Misaligned Load exception -#ifdef RLC_SELF_CHECK +#if RLC_TB_MODE == RLC_TB_MODE_AM + /* The legacy self_check compares the per-descriptor destinations, which + the AM path never writes -- it assembles transport blocks instead, and + those are checked at commit time by rlc_am_verify_grant(). */ + if (core_id == 0) { + rlc_am_report(); + } +#elif defined(RLC_SELF_CHECK) /* All sends are complete and tgt buffers are stable here. */ if (core_id == 0) { self_check(pdcp_pkgs, NUM_PKGS); diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.c b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.c new file mode 100644 index 0000000..492f9b5 --- /dev/null +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.c @@ -0,0 +1,947 @@ +// Copyright 2025 ETH Zurich and University of Bologna. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// Author: Zexin Fu + +/* RLC AM downlink execute stage. See rlc_am.h for the ownership model. + + Included from rlc.c after the core-role helpers, so rlc_ctx[], the per-user + list locks and rlc_consumer_index() are all in scope. */ + +#ifndef RLC_AM_C +#define RLC_AM_C + +#include "rlc_am.h" +#include "rlc_plan.c" + +/* One plan buffer per consumer core rather than per entity: a core plans at + most one grant at a time, and every entity has exactly one owner, so + indexing by the owner's consumer index needs no allocator. + (~5.6 KiB each at RLC_MAX_PDUS_PER_GRANT = 128.) */ +#ifndef RLC_AM_MAX_CONSUMERS +#define RLC_AM_MAX_CONSUMERS RLC_ACTUAL_CONSUMERS +#endif + +static rlc_plan_t rlc_am_plan_pool[RLC_AM_MAX_CONSUMERS] + __attribute__((aligned(CACHE_LINE_SIZE))) __attribute__((section(".data"))); + +/* Written only by the owning consumer, read by the reporter after the barrier. */ +/* The plan pool is indexed by consumer, not by entity, so a consumer that owns + several entities shares ONE rlc_plan_t across all of them. Executors read + e->plan for the whole life of a grant, so an owner that planned a second + entity while the first grant was still open would overwrite a live plan + underneath them. Rather than grow the pool to one buffer per entity (48 x + ~7 KiB at TC2), an owner holds at most one open grant at a time and must + commit it before planning another. Costs grant-level parallelism per owner; + correctness is not negotiable and the buffer growth is. */ +#define RLC_AM_NO_ENTITY 0xFFFFFFFFu +static uint32_t rlc_am_open_entity[RLC_AM_MAX_TRACKED_CONSUMERS] + __attribute__((section(".data"))); + +#if RLC_AM_TTI +/* Consensus state. Only consumer 0 writes rlc_am_stop; everyone reads it + after a barrier, so all consumers leave the loop on the same TTI. A + consumer that exited while others were still in a barrier would hang + them, so the decision cannot be taken independently. */ +static _Atomic uint32_t rlc_am_stop; +static uint32_t rlc_am_ttis; +/* Per-owner round-robin cursor over the entities it owns. */ +static uint32_t rlc_am_rr[RLC_AM_MAX_TRACKED_CONSUMERS]; + +#endif + +static uint32_t rlc_am_steps[RLC_AM_MAX_TRACKED_CONSUMERS] + __attribute__((section(".data"))); +static uint32_t rlc_am_last_u[RLC_AM_MAX_TRACKED_CONSUMERS] + __attribute__((section(".data"))); +static uint32_t rlc_am_sweeps[RLC_AM_MAX_TRACKED_CONSUMERS] + __attribute__((section(".data"))); + +/* The pad lives INSIDE the same object as the entity array. A separate static + does not work: the linker is free to place it after rlc_am_ent (it did), so + the addresses would not move at all. Enclosing both in one struct makes the + offset a language guarantee rather than a linker accident. */ +#if RLC_LAYOUT_PAD +static struct { + volatile char pad[RLC_LAYOUT_PAD]; + rlc_am_entity_t ent[NUM_USERS]; +} rlc_am_blk __attribute__((aligned(CACHE_LINE_SIZE))) + __attribute__((section(".data"))); +#define rlc_am_ent (rlc_am_blk.ent) +#else +static rlc_am_entity_t rlc_am_ent[NUM_USERS] + __attribute__((aligned(CACHE_LINE_SIZE))) __attribute__((section(".data"))); +#endif + +#if RLC_PLAN_VERIFY +static rlc_plan_t rlc_am_plan_ref[RLC_AM_MAX_CONSUMERS] + __attribute__((aligned(CACHE_LINE_SIZE))) __attribute__((section(".data"))); +static _Atomic uint32_t rlc_am_plan_bad; +#endif + +#if RLC_AM_WORKQ +/* Two bitmaps, one bit per entity: + ready -- has queued data and no grant open (an owner should plan it) + active -- a grant is open (any core can help execute it) + A step walks set bits instead of all entities, so its cost tracks the work + in flight rather than the entity count. Words that are zero are skipped + whole, which is what makes 4800 mostly-idle entities affordable. */ +#define RLC_AM_BM_WORDS (((NUM_USERS) + 31u) / 32u) +static _Atomic uint32_t rlc_am_bm_ready[RLC_AM_BM_WORDS]; +static _Atomic uint32_t rlc_am_bm_active[RLC_AM_BM_WORDS]; + +static inline void rlc_am_bm_set(_Atomic uint32_t *bm, uint32_t u) { + atomic_fetch_or_explicit(&bm[u >> 5], 1u << (u & 31u), memory_order_release); +} +static inline void rlc_am_bm_clr(_Atomic uint32_t *bm, uint32_t u) { + atomic_fetch_and_explicit(&bm[u >> 5], ~(1u << (u & 31u)), + memory_order_release); +} +static inline int rlc_am_bm_empty(const _Atomic uint32_t *bm) { + for (uint32_t w = 0u; w < RLC_AM_BM_WORDS; w++) + if (atomic_load_explicit(&bm[w], memory_order_acquire)) return 0; + return 1; +} + +void rlc_am_mark_ready(uint32_t u) { rlc_am_bm_set(rlc_am_bm_ready, u); } +#endif /* RLC_AM_WORKQ */ + +/* Which consumer index owns entity u -- the same static partition the legacy + consumer uses, so ownership and the existing round-robin agree. */ +/* Every entity must map to a consumer that exists, so the partition is sized + by RLC_ACTUAL_CONSUMERS rather than by the CONSUMER_CORE_NUM define. Using + the define orphans every entity whose owner index exceeds the real consumer + count -- those entities are never planned, never drain, and rlc_am_idle() + never goes true, which hangs the run rather than corrupting it. */ +static inline uint32_t rlc_am_owner_idx(uint32_t u) { + const uint32_t ncons = RLC_ACTUAL_CONSUMERS; + const uint32_t stride = (ncons < NUM_USERS) ? ncons : NUM_USERS; + return u % stride; +} + +#ifdef RLC_SELF_CHECK +/* Defined near the report at the end of this file; called from the plan and + commit paths above it. */ +static void rlc_am_poison(rlc_am_entity_t *e, uint32_t len); +static void rlc_am_verify_grant(uint32_t u); +#endif + +/* ------------------------------------------------------------------------ */ +/* Byte-granular payload copy */ +/* ------------------------------------------------------------------------ */ + +/* rlc_memcpy8() lives in rlc_copy.h: the uplink harness needs the same copy, + and neither direction owns it. */ +#include "rlc_copy.h" + +/* ------------------------------------------------------------------------ */ + +/* Set when the consumer set spans tiles while the transport-block arena is + tile-private -- see the comment on RLC_AM_ALLOW_CROSS_TILE_TB. */ +static uint32_t rlc_am_cross_tile_unsafe; + +void rlc_am_init(uint32_t u) { + if (u == 0u) { + for (uint32_t k = 0u; k < RLC_AM_MAX_TRACKED_CONSUMERS; k++) + rlc_am_open_entity[k] = RLC_AM_NO_ENTITY; + +#if RLC_AM_TTI + /* Programme which tiles take part in the consumer partial barrier. Must be + done from exactly one core; main.c's startup snrt_cluster_hw_barrier() + is the resync point the API requires before the mask is relied on. */ + { + const uint32_t cpt0 = snrt_cluster_core_per_tile(); + uint32_t tm_lo = 0u, tm_hi = 0u; + for (uint32_t i = 0u; i < RLC_ACTUAL_CONSUMERS; i++) { + const uint32_t t = (uint32_t)consumer_core_ids[i] / cpt0; + if (t < 32u) tm_lo |= 1u << t; else tm_hi |= 1u << (t - 32u); + } + snrt_barrier_set_tile_mask(tm_lo, tm_hi); + for (uint32_t k = 0u; k < RLC_AM_MAX_TRACKED_CONSUMERS; k++) rlc_am_rr[k] = 0u; + atomic_store_explicit(&rlc_am_stop, 0u, memory_order_relaxed); + rlc_am_ttis = 0u; + } +#endif + + /* Executors share one transport block, so they must share a tile while + that arena is private. Checked once, loudly: getting this wrong loses + payload writes with no other symptom. */ + rlc_am_cross_tile_unsafe = 0u; +#if !RLC_AM_ALLOW_CROSS_TILE_TB + { + const uint32_t cpt = snrt_cluster_core_per_tile(); + uint32_t tile0 = 0u, spans = 0u; + for (uint32_t i = 0u; i < RLC_ACTUAL_CONSUMERS; i++) { + const uint32_t t = (uint32_t)consumer_core_ids[i] / cpt; + if (i == 0u) tile0 = t; + else if (t != tile0) spans = 1u; + } + if (spans) { + rlc_am_cross_tile_unsafe = 1u; + printf_lock_acquire(&printf_lock); + printf("[AM][FATAL] consumers span tiles but the transport-block arena " + "at 0x%x is tile-private: executors on different tiles would " + "write to different copies and payload writes would be lost. " + "Move the arena below the l1d_addr boundary, or confine an " + "entity's executors to the owner's tile.\n", + (unsigned)RLC_TB_BASE); + printf_lock_release(&printf_lock); + } + } +#endif + } + rlc_am_entity_t *e = &rlc_am_ent[u]; + e->so_next = 0u; + e->plan = &rlc_am_plan_pool[rlc_am_owner_idx(u)]; + e->tb = (uint8_t *)(uintptr_t)(RLC_TB_BASE + u * RLC_TB_STRIDE); + e->n = 0u; + e->tb_used = 0u; + atomic_store_explicit(&e->gen, 0u, memory_order_relaxed); + atomic_store_explicit(&e->claim, 0u, memory_order_relaxed); + atomic_store_explicit(&e->done, 0u, memory_order_relaxed); + e->partial = 0u; + e->plan_calls = 0u; + e->peek_empty = 0u; + e->plan_zero = 0u; + e->plan_ok = 0u; + e->peek_done = 0u; + e->poison_done = 0u; + e->published = 0u; + e->peek_max = 0u; + e->verify_sn = 0u; + e->verify_so = 0u; + e->verify_mask = 0u; + e->verify_bad_idx = 0u; + e->verify_have_bad = 0u; + e->verify_align_bad = 0u; + e->verify_align_ok = 0u; + e->verify_pay_bad = 0u; + e->verify_pay_checked = 0u; + e->verify_first_byte = 0xFFFFFFFFu; + e->grants = 0u; + e->pdus = 0u; + e->segments = 0u; + e->polls = 0u; +} + +/* --- owner: gather + plan + publish -------------------------------------- */ + +/* Returns 1 if a grant was opened. */ +static int rlc_am_try_plan(uint32_t u) { + rlc_am_entity_t *e = &rlc_am_ent[u]; + rlc_context_t *ctx = &rlc_ctx[u]; + rlc_plan_t *plan = e->plan; + + /* Look ahead over the queue without detaching anything: a partially sent + SDU must stay at the head until its final segment goes out. */ + e->plan_calls++; + /* Peek straight into the plan's own node array. A local Node*[128] would put + 512 B on the stack, and Snitch stacks are small -- this keeps the frame + flat and saves a copy. */ + Node **peek = (Node **)plan->sdu_node; + /* Walk only as far as the grant can reach. The queue walk is a dependent + pointer chase and dominates the planning attempt, so gathering the full + RLC_MAX_PDUS_PER_GRANT when the grant holds a handful of SDUs multiplies + that cost for nothing. Charging the minimum header per SDU keeps the + bound conservative -- a segmented lead SDU carries a larger header, so + the walk can only ever stop later than strictly necessary, never early. */ + const uint32_t avail = list_peek_budget( + (spinlock_t *)&tosend_llist_lock_2[u], &ctx->list, peek, + RLC_MAX_PDUS_PER_GRANT, RLC_GRANT_BYTES + e->so_next, RLC_AMD_HDR_MIN); + e->peek_done++; /* distinguishes "blocked in the peek" from "peek was empty" */ + if (avail > e->peek_max) e->peek_max = avail; + if (avail == 0u) { e->peek_empty++; return 0; } + + for (uint32_t i = 0u; i < avail; i++) { + plan->sdu_data[i] = peek[i]->data; + plan->sdu_len[i] = (uint32_t)peek[i]->data_size; + } + plan->n_avail = avail; + + const rlc_plan_in_t in = { + .grant_bytes = RLC_GRANT_BYTES, + .sn_base = atomic_load_explicit(&ctx->vtNext, memory_order_relaxed), + .so_first = e->so_next, + .poll_pdu = atomic_load_explicit(&ctx->pollPdu, memory_order_relaxed), + .poll_byte = atomic_load_explicit(&ctx->pollByte, memory_order_relaxed), + .pdu_without_poll = + atomic_load_explicit(&ctx->pduWithoutPoll, memory_order_relaxed), + .byte_without_poll = + atomic_load_explicit(&ctx->byteWithoutPoll, memory_order_relaxed), + /* the peek saw the whole queue only if it did not hit the cap */ + .queue_drained = (avail < RLC_MAX_PDUS_PER_GRANT), + }; + rlc_plan_out_t out; +#if RLC_PLAN_VERIFY + uint32_t bad = 0u; + const uint32_t n = rlc_plan_compute_checked( + plan, &rlc_am_plan_ref[rlc_am_owner_idx(u)], &in, &out, &bad); + if (bad) atomic_fetch_add_explicit(&rlc_am_plan_bad, bad, memory_order_relaxed); +#else + const uint32_t n = rlc_plan_compute(plan, &in, &out); +#endif + if (n == 0u) { e->plan_zero++; return 0; } + e->plan_ok++; + + /* Stash what commit needs; it must not re-run the planner. */ + e->n = n; + e->tb_used = plan->tb_used; + e->partial = out.partial; + e->so_next = out.so_next; + atomic_store_explicit(&ctx->vtNext, out.sn_next, memory_order_relaxed); + atomic_store_explicit(&ctx->pduWithoutPoll, out.pdu_without_poll, + memory_order_relaxed); + atomic_store_explicit(&ctx->byteWithoutPoll, out.byte_without_poll, + memory_order_relaxed); + +#ifdef RLC_SELF_CHECK + rlc_am_poison(e, plan->tb_used); +#endif + e->poison_done++; + + /* Publish: counters reset first, generation last (release). */ + atomic_store_explicit(&e->claim, 0u, memory_order_relaxed); + atomic_store_explicit(&e->done, 0u, memory_order_relaxed); + atomic_store_explicit(&e->gen, + atomic_load_explicit(&e->gen, memory_order_relaxed) + 1u, + memory_order_release); + e->published++; +#if RLC_AM_WORKQ + rlc_am_bm_set(rlc_am_bm_active, u); +#endif + e->grants++; + return 1; +} + +/* --- any core: claim and execute ----------------------------------------- */ + +static void rlc_am_execute_range(rlc_am_entity_t *e, uint32_t lo, uint32_t hi) { + const rlc_plan_t *p = e->plan; + for (uint32_t i = lo; i < hi; i++) { + uint8_t *dst = e->tb + p->tb_off[i]; + rlc_amd_hdr_write(dst, p->sn[i], p->si[i], p->poll[i], p->so[i]); + const uint8_t *src = (const uint8_t *)p->sdu_data[i] + p->so[i]; +#if RLC_DL_EXEC == RLC_DL_EXEC_COPY + rlc_memcpy8(dst + p->hdr_len[i], src, p->seg_len[i]); +#else + /* No payload movement: hand a descriptor to whatever drains the TB. */ + rlc_sgl_t *g = &e->sgl[i]; + g->hdr = dst; + g->hdr_len = p->hdr_len[i]; + g->src = (void *)src; + g->len = p->seg_len[i]; +#endif + } +} + +/* Claim and run one chunk of entity u's open grant. Returns PDUs executed. */ +static uint32_t rlc_am_help(uint32_t u) { + rlc_am_entity_t *e = &rlc_am_ent[u]; + if ((atomic_load_explicit(&e->gen, memory_order_acquire) & 1u) == 0u) return 0; + + const uint32_t lo = atomic_fetch_add_explicit(&e->claim, RLC_AM_CLAIM_CHUNK, + memory_order_relaxed); + /* Read n *after* claiming: if the owner closed this grant and opened the + next one in between, the claim landed on the new counter and n must be + the new one too. plan/tb are written before the generation is bumped, so + they are consistent with whichever grant the claim belongs to. */ + const uint32_t n = e->n; + if (lo >= n) return 0; + + uint32_t hi = lo + RLC_AM_CLAIM_CHUNK; + if (hi > n) hi = n; + rlc_am_execute_range(e, lo, hi); + atomic_fetch_add_explicit(&e->done, hi - lo, memory_order_release); + return hi - lo; +} + +/* --- owner: commit -------------------------------------------------------- */ + +/* Retire a finished grant: move fully-transmitted SDUs to the sent list and + fold the grant into the entity counters. Only the owner runs this. */ +static void rlc_am_commit(uint32_t u) { + rlc_am_entity_t *e = &rlc_am_ent[u]; + rlc_context_t *ctx = &rlc_ctx[u]; + const rlc_plan_t *p = e->plan; + const uint32_t n = e->n; + const uint32_t partial = e->partial; + + /* Every SDU finished by this grant leaves the queue, in order, stamped with + the SN of its final segment -- the STATUS path needs that to know when the + SDU is fully acknowledged. The trailing segment's SDU stays at the head + with e->so_next recording how much of it has gone out. */ + uint32_t retire = 0u; + for (uint32_t i = 0u; i < n; i++) { + if (!p->last_seg[i]) continue; + Node *node = list_pop_front((spinlock_t *)&tosend_llist_lock_2[u], + &ctx->list); + if (node == NULL) { + DEBUG_PRINTF_LOCK_ACQUIRE(&printf_lock); + DEBUG_PRINTF("[AM][u %u] commit: queue shorter than plan at %u\n", u, i); + DEBUG_PRINTF_LOCK_RELEASE(&printf_lock); + break; + } + node->last_sn = p->sn[i]; + list_push_back((spinlock_t *)&sent_llist_lock_2[u], &ctx->sent_list, node); + retire++; + } + + uint32_t bytes = 0u, polls = 0u, segs = 0u; + for (uint32_t i = 0u; i < n; i++) { + bytes += p->seg_len[i]; + polls += p->poll[i]; + segs += (p->si[i] != RLC_SI_FULL); + } + atomic_fetch_add_explicit(&ctx->dlPduNum, n, memory_order_relaxed); + atomic_fetch_add_explicit(&ctx->rlcthrp, bytes, memory_order_relaxed); + atomic_fetch_add_explicit(&ctx->tbsize, e->tb_used, memory_order_relaxed); + atomic_fetch_add_explicit(&ctx->sduNum, -(int32_t)retire, memory_order_relaxed); + atomic_fetch_add_explicit(&ctx->sduBytes, (uint32_t)(0u - bytes), + memory_order_relaxed); + ctx->sendPduNum += n; + ctx->sendPduBytes += bytes; + e->pdus += n; + e->polls += polls; + e->segments += segs; + +#ifdef RLC_SELF_CHECK + rlc_am_verify_grant(u); +#endif + + e->n = 0u; + /* Close the grant (generation back to even). */ + atomic_store_explicit(&e->gen, + atomic_load_explicit(&e->gen, memory_order_relaxed) + 1u, + memory_order_release); +#if RLC_AM_WORKQ + rlc_am_bm_clr(rlc_am_bm_active, u); + /* Anything left -- queued SDUs, or a segment mid-flight -- re-arms the + entity so it is picked up again without a scan. */ + if (ctx->list.sduNum != 0 || e->so_next != 0u) { + rlc_am_bm_set(rlc_am_bm_ready, u); + } +#endif +} + + +/* ------------------------------------------------------------------------ */ +/* TTI-structured consumer loop */ +/* ------------------------------------------------------------------------ */ +#if RLC_AM_TTI + +/* Entities owned by consumer index `me`, in order: me, me+stride, me+2*stride... + (owner_idx(u) == u % stride, so the owned set is an arithmetic progression). */ +static inline uint32_t rlc_am_owned_count(uint32_t me) { + const uint32_t ncons = RLC_ACTUAL_CONSUMERS; + const uint32_t stride = (ncons < NUM_USERS) ? ncons : NUM_USERS; + if (me >= stride) return 0u; /* more consumers than entities: pure helper */ + return (NUM_USERS - me + stride - 1u) / stride; +} +static inline uint32_t rlc_am_owned_at(uint32_t me, uint32_t k) { + const uint32_t ncons = RLC_ACTUAL_CONSUMERS; + const uint32_t stride = (ncons < NUM_USERS) ? ncons : NUM_USERS; + return me + k * stride; +} + +/* Phase 1: each owner opens at most ONE grant. + + The plan pool is indexed by consumer, so an owner holds one plan buffer and + therefore one open grant at a time. A TTI is consequently "one grant + opportunity per OWNER", not per entity -- entities are served round-robin, + so each gets a turn every ceil(owned/1) TTIs. The agreed cross-engine metric + is bytes/cycle and does not depend on how a TTI is defined, so this changes + the reporting granularity only. */ +static void rlc_am_plan_phase(uint32_t me) { + const uint32_t trk = (me < RLC_AM_MAX_TRACKED_CONSUMERS) ? me : 0u; + const uint32_t n = rlc_am_owned_count(me); + if (n == 0u) return; + if (rlc_am_open_entity[trk] != RLC_AM_NO_ENTITY) return; + + for (uint32_t k = 0u; k < n; k++) { + const uint32_t idx = (rlc_am_rr[trk] + k) % n; + const uint32_t u = rlc_am_owned_at(me, idx); + if (atomic_load_explicit(&rlc_am_ent[u].gen, memory_order_acquire) & 1u) continue; + if (rlc_am_try_plan(u)) { + rlc_am_open_entity[trk] = u; + rlc_am_rr[trk] = (idx + 1u) % n; /* next TTI starts at the following one */ + return; + } + } + rlc_am_rr[trk] = (rlc_am_rr[trk] + 1u) % n; /* nothing to plan; still advance */ +} + +/* Phase 2: everyone drains every open grant. Terminates when no chunk is left + to claim -- a core may still be finishing a claimed chunk, which the barrier + after this phase covers. */ +static uint32_t rlc_am_execute_phase(void) { + uint32_t total = 0u, worked; + do { + worked = 0u; + for (uint32_t u = 0u; u < NUM_USERS; u++) worked += rlc_am_help(u); + total += worked; + } while (worked != 0u); + return total; +} + +/* Phase 3: owners retire. Safe without checking `done` because the barrier + between execute and commit already guarantees every chunk has completed -- + the counter is kept as a cross-check rather than as the synchronisation. */ +static void rlc_am_commit_phase(uint32_t me) { + const uint32_t trk = (me < RLC_AM_MAX_TRACKED_CONSUMERS) ? me : 0u; + const uint32_t u = rlc_am_open_entity[trk]; + if (u == RLC_AM_NO_ENTITY) return; + if ((atomic_load_explicit(&rlc_am_ent[u].gen, memory_order_acquire) & 1u) == 0u) return; + rlc_am_commit(u); + rlc_am_open_entity[trk] = RLC_AM_NO_ENTITY; +} + +void rlc_am_consumer_tti(uint32_t core_id) { + const uint32_t me = rlc_consumer_index(core_id); + /* Tile-local participant mask. O(n), computed once on entry, never in the + loop. Every consumer in a tile derives the same value independently. */ + const uint32_t mask = + snrt_cluster_partial_barrier_mask(consumer_core_ids, RLC_ACTUAL_CONSUMERS); + + while (1) { +#if RLC_TTI_CYCLES + const uint32_t tti_start = benchmark_get_cycle(); +#endif + rlc_am_plan_phase(me); + snrt_cluster_partial_barrier(mask); /* helpers BLOCK here, not polling */ + + rlc_am_execute_phase(); + snrt_cluster_partial_barrier(mask); + + rlc_am_commit_phase(me); + snrt_cluster_partial_barrier(mask); + + if (me == 0u) { + rlc_am_ttis++; + atomic_store_explicit(&rlc_am_stop, + (atomic_load_explicit(&producer_done, memory_order_relaxed) >= + PRODUCER_CORE_NUM && rlc_am_idle()) ? 1u : 0u, + memory_order_release); + } + snrt_cluster_partial_barrier(mask); + if (atomic_load_explicit(&rlc_am_stop, memory_order_acquire)) break; + +#if RLC_TTI_CYCLES + { /* pad to the scaled TTI so the run has a wallclock-flavoured cadence */ + const uint32_t used = benchmark_get_cycle() - tti_start; + if (used < (uint32_t)RLC_TTI_CYCLES) delay((uint32_t)RLC_TTI_CYCLES - used); + } +#endif + } +} +#endif /* RLC_AM_TTI */ + +/* ------------------------------------------------------------------------ */ +/* Transport-block self-check */ +/* ------------------------------------------------------------------------ */ + +#ifdef RLC_SELF_CHECK +static _Atomic uint32_t rlc_am_verify_errors; +static _Atomic uint32_t rlc_am_verify_grants; + +/* Mark each planned PDU's header bytes before publishing, so a chunk that no + core ever executed decodes as the fill pattern rather than as whatever the + previous grant left behind. + + Only the header bytes, not the whole grant: filling all of tb_used meant + 8192 single-byte stores to DRAM per grant, which was slow enough to stall + the owner for the rest of the run (observed on GVSoC as a second grant that + planned but never published). The payload has its own byte-exact comparison + in the verifier, so poisoning it added cost without adding coverage. */ +#define RLC_TB_POISON 0xA5u +static void rlc_am_poison(rlc_am_entity_t *e, uint32_t len) { + const rlc_plan_t *p = e->plan; + (void)len; + for (uint32_t i = 0u; i < e->n; i++) { + uint8_t *h = e->tb + p->tb_off[i]; + for (uint32_t b = 0u; b < p->hdr_len[i]; b++) h[b] = RLC_TB_POISON; + } + asm volatile("fence" ::: "memory"); +} + +/* Decode the assembled block and check it against the plan that produced it. + This validates the *execute* stage -- that every chunk actually ran, wrote + its header at the offset the planner assigned, and copied the right payload + bytes. The host test cannot see any of that: it never runs concurrently and + never touches memory. */ +/* Bit positions in rlc_am_entity_t::verify_mask. */ +#define RLC_VB_TB_OFF (1u << 0) +#define RLC_VB_SN (1u << 1) +#define RLC_VB_SI (1u << 2) +#define RLC_VB_POLL (1u << 3) +#define RLC_VB_SO (1u << 4) +#define RLC_VB_HDRLEN (1u << 5) +#define RLC_VB_SN_SEQ (1u << 6) +#define RLC_VB_PAYLOAD (1u << 7) +#define RLC_VB_TB_USED (1u << 8) +#define RLC_VB_SN_CONT (1u << 9) +#define RLC_VB_SO_CONT (1u << 10) +#define RLC_VB_POISON (1u << 11) /* header still reads as the fill pattern */ + +static void rlc_am_verify_grant(uint32_t u) { + rlc_am_entity_t *e = &rlc_am_ent[u]; + const rlc_plan_t *p = e->plan; + uint32_t off = 0u, bad = 0u, mask = 0u; + +#define RLC_VB(cond, bit) \ + do { \ + if (cond) { \ + bad++; \ + mask |= (bit); \ + if (!e->verify_have_bad) { e->verify_have_bad = 1u; e->verify_bad_idx = i; } \ + } \ + } while (0) + + for (uint32_t i = 0u; i < e->n; i++) { + rlc_amd_hdr_t hd; + rlc_amd_hdr_read(e->tb + off, &hd); + + /* An untouched header still carries the pre-publish fill, which says the + chunk was never executed rather than executed wrongly. */ + RLC_VB(e->tb[off] == RLC_TB_POISON && e->tb[off + 1u] == RLC_TB_POISON, + RLC_VB_POISON); + RLC_VB(off != p->tb_off[i], RLC_VB_TB_OFF); + RLC_VB(hd.sn != p->sn[i], RLC_VB_SN); + RLC_VB(hd.si != p->si[i], RLC_VB_SI); + RLC_VB(hd.poll != p->poll[i], RLC_VB_POLL); + RLC_VB(hd.so != p->so[i], RLC_VB_SO); + RLC_VB(hd.hdr_len != p->hdr_len[i], RLC_VB_HDRLEN); + /* Sequence numbers must be consecutive across the whole block. */ + RLC_VB(i > 0u && hd.sn != ((p->sn[i - 1u] + 1u) & RLC_SN_MASK), + RLC_VB_SN_SEQ); + +#if RLC_DL_EXEC == RLC_DL_EXEC_COPY + { + const uint8_t *src = (const uint8_t *)p->sdu_data[i] + p->so[i]; + const uint8_t *dst = e->tb + off + hd.hdr_len; + const uint32_t algn = (uint32_t)((uintptr_t)dst & 3u); + uint32_t mism = 0u, firstb = 0u; + for (uint32_t b = 0u; b < p->seg_len[i]; b++) { + if (dst[b] != src[b]) { mism = 1u; firstb = b; break; } + } + e->verify_pay_checked++; + if (mism) { + e->verify_pay_bad++; + e->verify_align_bad |= (1u << algn); + if (firstb < e->verify_first_byte) e->verify_first_byte = firstb; + } else { + e->verify_align_ok |= (1u << algn); + } + RLC_VB(mism != 0u, RLC_VB_PAYLOAD); + } +#endif + off += p->hdr_len[i] + p->seg_len[i]; + } + { + const uint32_t i = e->n; + RLC_VB(off != e->tb_used, RLC_VB_TB_USED); + } + + /* Continuity with the previous grant: the block must resume exactly where + the last one stopped, both in SN and in segment offset. */ + if (e->n) { + const uint32_t i = 0u; + RLC_VB(p->sn[0] != e->verify_sn, RLC_VB_SN_CONT); + RLC_VB(p->so[0] != e->verify_so, RLC_VB_SO_CONT); + e->verify_sn = (p->sn[0] + e->n) & RLC_SN_MASK; + e->verify_so = e->so_next; + } +#undef RLC_VB + e->verify_mask |= mask; + + atomic_fetch_add_explicit(&rlc_am_verify_grants, 1u, memory_order_relaxed); + if (bad) { + atomic_fetch_add_explicit(&rlc_am_verify_errors, bad, memory_order_relaxed); + printf_lock_acquire(&printf_lock); + printf("[AM-SB][u %u] grant %u: %u mismatches (n=%u tb_used=%u)\n", u, + e->grants, bad, e->n, e->tb_used); + printf_lock_release(&printf_lock); + } +} +#endif /* RLC_SELF_CHECK */ + +/* ------------------------------------------------------------------------ */ +/* STATUS PDU (TS 38.322 ยง6.2.2.5) */ +/* ------------------------------------------------------------------------ */ + +/* One STATUS PDU buffer per entity. Built and then parsed back on every + status pass so the encode/decode cost is part of the measurement. */ +static uint8_t rlc_am_status_buf[NUM_USERS][RLC_STATUS_HDR_LEN + 4u] + __attribute__((aligned(4))) __attribute__((section(".data"))); + +void rlc_am_status(void) { + for (uint32_t u = 0u; u < NUM_USERS; u++) { + rlc_context_t *ctx = &rlc_ctx[u]; + + /* The modelled UE acknowledges everything up to RLC_AM_ACK_LAG PDUs + behind the transmitter. ACK_SN is the first *not* acknowledged SN. */ + const uint32_t vt_next = + atomic_load_explicit(&ctx->vtNext, memory_order_relaxed); + const uint32_t vt_ack = + atomic_load_explicit(&ctx->vtNextAck, memory_order_relaxed); + if (!rlc_sn_lt(vt_ack, vt_next)) continue; + + uint32_t ack_sn = (vt_next - RLC_AM_ACK_LAG) & RLC_SN_MASK; + if (rlc_sn_lt(ack_sn, vt_ack)) continue; /* nothing new to acknowledge */ + + /* Build it, then decode it -- the parse is the part a receiver pays for, + and it is what the legacy model skipped entirely. */ + uint8_t *buf = rlc_am_status_buf[u]; + rlc_status_hdr_write(buf, ack_sn, /*e1=*/0u); + uint32_t got_ack_sn, got_e1; + rlc_status_hdr_read(buf, &got_ack_sn, &got_e1); + if (got_ack_sn != ack_sn) { + printf_lock_acquire(&printf_lock); + printf("[AM-SB][u %u] STATUS round-trip: wrote %u read %u\n", u, ack_sn, + got_ack_sn); + printf_lock_release(&printf_lock); +#ifdef RLC_SELF_CHECK + atomic_fetch_add_explicit(&rlc_am_verify_errors, 1u, memory_order_relaxed); +#endif + } + + /* Release every SDU whose final segment is below ACK_SN. Because SDUs are + retired in order, their last_sn values are monotonic, so the first node + that is not acknowledged ends the scan. */ + uint32_t freed = 0u; + while (1) { + Node *head = NULL; + if (list_peek_n((spinlock_t *)&sent_llist_lock_2[u], &ctx->sent_list, + &head, 1u) == 0u) { + break; + } + if (!rlc_sn_lt(head->last_sn, got_ack_sn)) break; + Node *node = list_pop_front((spinlock_t *)&sent_llist_lock_2[u], + &ctx->sent_list); + if (node == NULL) break; + mm_free(node); + freed++; + } + + atomic_store_explicit(&ctx->vtNextAck, got_ack_sn, memory_order_relaxed); + ctx->acksn = got_ack_sn; + ctx->nackcount = 0u; + if (freed) ctx->parseindex++; + } +} + +void rlc_am_report(void) { + uint32_t grants = 0u, pdus = 0u, segs = 0u, polls = 0u; + for (uint32_t u = 0u; u < NUM_USERS; u++) { + grants += rlc_am_ent[u].grants; + pdus += rlc_am_ent[u].pdus; + segs += rlc_am_ent[u].segments; + polls += rlc_am_ent[u].polls; + } + printf_lock_acquire(&printf_lock); + printf("[AM] entities=%u grants=%u pdus=%u segments=%u polls=%u grant_bytes=%u\n", + (unsigned)NUM_USERS, grants, pdus, segs, polls, + (unsigned)RLC_GRANT_BYTES); + /* Dispatch shape: the *_CORE_NUM macros come from the build, the NUM_*_CORES + from the generated data header. They are allowed to disagree, but the + lists are what actually decide who produces and who consumes. */ + for (uint32_t k = 0u; k < RLC_AM_MAX_TRACKED_CONSUMERS; k++) { + if (!rlc_am_steps[k] && !rlc_am_last_u[k]) continue; + printf("[AM] consumer %u: steps=%u completed_sweeps=%u last_entity=%u/%u\n", + k, rlc_am_steps[k], rlc_am_sweeps[k], rlc_am_last_u[k], + (unsigned)NUM_USERS); + } + if (rlc_am_cross_tile_unsafe) { + printf("[AM] cross-tile transport block: UNSAFE -> results are not " + "trustworthy\n"); + } + printf("[AM] layout: sizeof(entity)=%u pad=%u ent@%p ctx@%p\n", + (unsigned)sizeof(rlc_am_entity_t), (unsigned)RLC_LAYOUT_PAD, + (void *)&rlc_am_ent[0], (void *)&rlc_ctx[0]); + printf("[AM] zero-vl vsetvli events: %u\n", + (unsigned)atomic_load_explicit(&rlc_vec_zero_vl, memory_order_relaxed)); +#if RLC_AM_TTI + { + uint32_t bytes = 0u; + for (uint32_t u = 0u; u < NUM_USERS; u++) + bytes += atomic_load_explicit(&rlc_ctx[u].rlcthrp, memory_order_relaxed); + printf("[AM] ttis=%u payload_bytes=%u tti_cycles=%u (one TTI = one grant " + "opportunity per OWNER; bytes/cycle = payload_bytes / kernel_cycles)\n", + rlc_am_ttis, bytes, (unsigned)RLC_TTI_CYCLES); + } +#endif + printf("[AM] dispatch: producers=%u(list %u) consumers=%u(list %u) workq=%u\n", + (unsigned)PRODUCER_CORE_NUM, (unsigned)NUM_PRODUCER_CORES, + (unsigned)CONSUMER_CORE_NUM, (unsigned)NUM_CONSUMER_CORES, + (unsigned)RLC_AM_WORKQ); + for (uint32_t u = 0u; u < NUM_USERS; u++) { + const rlc_am_entity_t *e = &rlc_am_ent[u]; + printf("[AM] u%u: plan_calls=%u peek_empty=%u peek_max=%u plan_zero=%u " + "peek_done=%u plan_ok=%u poison=%u published=%u grants=%u | tosend=%d sent=%d " + "so_next=%u gen=%u\n", + u, e->plan_calls, e->peek_empty, e->peek_max, e->plan_zero, + e->peek_done, e->plan_ok, e->poison_done, e->published, e->grants, + rlc_ctx[u].list.sduNum, rlc_ctx[u].sent_list.sduNum, e->so_next, + (unsigned)atomic_load_explicit(&rlc_am_ent[u].gen, + memory_order_relaxed)); + /* If rlc_am_init never ran, plan is NULL -- and sdu_node is the first + member of rlc_plan_t, so the queue look-ahead would write to address 0 + and still return a plausible count. Print the pointers so that is + visible rather than inferred. */ + printf("[AM] u%u: plan=%p tb=%p pool0=%p ent=%p n=%u tb_used=%u\n", u, + (void *)e->plan, (void *)e->tb, (void *)&rlc_am_plan_pool[0], + (void *)e, e->n, e->tb_used); + } +#if RLC_PLAN_VERIFY + { + const uint32_t pb = + atomic_load_explicit(&rlc_am_plan_bad, memory_order_relaxed); + printf("[AM] plan vector-vs-reference mismatches: %u -> %s\n", pb, + pb ? "FAIL" : "PASS"); + } +#endif +#ifdef RLC_SELF_CHECK + { + const uint32_t ve = + atomic_load_explicit(&rlc_am_verify_errors, memory_order_relaxed); + const uint32_t vg = + atomic_load_explicit(&rlc_am_verify_grants, memory_order_relaxed); + printf("[AM] transport-block check: %u grants, %u mismatches -> %s\n", vg, + ve, ve ? "FAIL" : "PASS"); + for (uint32_t u = 0u; u < NUM_USERS; u++) { + const rlc_am_entity_t *e = &rlc_am_ent[u]; + if (!e->verify_mask) continue; + printf("[AM] u%u: payload %u/%u PDUs bad | align_bad=0x%x align_ok=0x%x " + "first_diff_byte=%d | copy=%s\n", + u, e->verify_pay_bad, e->verify_pay_checked, e->verify_align_bad, + e->verify_align_ok, + (e->verify_first_byte == 0xFFFFFFFFu) ? -1 + : (int)e->verify_first_byte, + RLC_DL_COPY_SCALAR ? "scalar" : "e8/m8-vector"); + printf("[AM] u%u: verify_mask=0x%x first_bad_pdu=%u " + "[bit0 tb_off,1 sn,2 si,3 poll,4 so,5 hdr_len,6 sn_seq," + "7 payload,8 tb_used,9 sn_cont,10 so_cont,11 poison]\n", + u, e->verify_mask, e->verify_bad_idx); + } + } +#endif + printf_lock_release(&printf_lock); +} + +/* ------------------------------------------------------------------------ */ + +uint32_t rlc_am_step(uint32_t core_id) { + const uint32_t me = rlc_consumer_index(core_id); + uint32_t worked = 0u; + const uint32_t trk = (me < RLC_AM_MAX_TRACKED_CONSUMERS) ? me : 0u; + rlc_am_steps[trk]++; + +#if RLC_AM_WORKQ + /* Owner pass: plan the entities this core owns that have announced work. */ + for (uint32_t w = 0u; w < RLC_AM_BM_WORDS; w++) { + uint32_t bits = atomic_load_explicit(&rlc_am_bm_ready[w], + memory_order_acquire); + while (bits) { + const uint32_t b = (uint32_t)__builtin_ctz(bits); + bits &= bits - 1u; + const uint32_t u = (w << 5) + b; + if (u >= NUM_USERS || rlc_am_owner_idx(u) != me) continue; + rlc_am_last_u[trk] = u; + if (rlc_am_open_entity[trk] != RLC_AM_NO_ENTITY) continue; + if (atomic_load_explicit(&rlc_am_ent[u].gen, memory_order_acquire) & 1u) + continue; + /* Clear before looking: a producer that enqueues in between sets the bit + again, so the notification cannot be lost -- only repeated. */ + rlc_am_bm_clr(rlc_am_bm_ready, u); + if (rlc_am_try_plan(u)) { + rlc_am_open_entity[trk] = u; + } else { + /* Nothing planned but work remains (e.g. the grant cannot hold even a + header): re-arm, or the entity would stall unnoticed. */ + if (rlc_ctx[u].list.sduNum != 0 || rlc_am_ent[u].so_next != 0u) { + rlc_am_bm_set(rlc_am_bm_ready, u); + } + } + } + } + + /* Helper pass: any core executes any open grant. */ + for (uint32_t w = 0u; w < RLC_AM_BM_WORDS; w++) { + uint32_t bits = atomic_load_explicit(&rlc_am_bm_active[w], + memory_order_acquire); + while (bits) { + const uint32_t b = (uint32_t)__builtin_ctz(bits); + bits &= bits - 1u; + const uint32_t u = (w << 5) + b; + if (u >= NUM_USERS) continue; + worked += rlc_am_help(u); + rlc_am_entity_t *e = &rlc_am_ent[u]; + if (rlc_am_owner_idx(u) == me && + (atomic_load_explicit(&e->gen, memory_order_acquire) & 1u) && + atomic_load_explicit(&e->done, memory_order_acquire) >= e->n) { + rlc_am_commit(u); + if (rlc_am_open_entity[trk] == u) rlc_am_open_entity[trk] = RLC_AM_NO_ENTITY; + worked++; + } + } + } + rlc_am_sweeps[trk]++; + return worked; +#else + for (uint32_t u = 0u; u < NUM_USERS; u++) { + rlc_am_last_u[trk] = u; + rlc_am_entity_t *e = &rlc_am_ent[u]; + /* Exactly one consumer index owns each entity. At NUM_USERS == 1 that is + consumer 0; every other consumer is a helper, which is precisely what + makes single-entity peak rate reachable. */ + const int owner = (rlc_am_owner_idx(u) == me); + + if (owner && rlc_am_open_entity[trk] == RLC_AM_NO_ENTITY && + (atomic_load_explicit(&e->gen, memory_order_acquire) & 1u) == 0u) { + if (rlc_am_try_plan(u)) rlc_am_open_entity[trk] = u; + } + + /* Any core helps any open grant, owned or not. */ + worked += rlc_am_help(u); + + if (owner && (atomic_load_explicit(&e->gen, memory_order_acquire) & 1u) && + atomic_load_explicit(&e->done, memory_order_acquire) >= e->n) { + rlc_am_commit(u); + if (rlc_am_open_entity[trk] == u) rlc_am_open_entity[trk] = RLC_AM_NO_ENTITY; + worked++; + } + } + rlc_am_sweeps[trk]++; /* only reached if the whole sweep completed */ + return worked; +#endif /* RLC_AM_WORKQ */ +} + +int rlc_am_idle(void) { +#if RLC_AM_WORKQ + /* Both bitmaps clear means nothing is queued and nothing is in flight: a + producer enqueueing would have set ready, a grant would have set active. */ + return rlc_am_bm_empty(rlc_am_bm_ready) && rlc_am_bm_empty(rlc_am_bm_active); +#else + for (uint32_t u = 0u; u < NUM_USERS; u++) { + if (atomic_load_explicit(&rlc_am_ent[u].gen, memory_order_acquire) & 1u) + return 0; + if (rlc_ctx[u].list.sduNum != 0) return 0; + if (rlc_am_ent[u].so_next != 0u) return 0; + } + return 1; +#endif +} + +#endif /* RLC_AM_C */ diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.h b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.h new file mode 100644 index 0000000..c23edb3 --- /dev/null +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.h @@ -0,0 +1,306 @@ +// Copyright 2025 ETH Zurich and University of Bologna. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// Author: Zexin Fu + +/* RLC AM downlink: transport-block assembly on top of the grant planner. + + Ownership model ("owner-plans"): every RLC entity has one owner core, given + by the same static partition the legacy consumer already uses. The owner + gathers the queue, plans the grant, and publishes the plan; then *any* + consumer core -- owner included -- claims chunks of that plan and executes + them in parallel. The owner commits once all chunks report done. + + That split is what keeps single-entity peak rate reachable: at NUM_USERS==1 + there is one owner and C-1 helpers all filling the same transport block, + into byte offsets the planner already fixed, with no lock and no ordering + constraint between them. */ + +#ifndef RLC_AM_H +#define RLC_AM_H + +#include +#include + +#include "rlc_pdu.h" +#include "rlc_plan.h" + +/* --- build-time selection ------------------------------------------------ */ + +/* Downlink model. LEGACY keeps the original "copy each SDU to a destination + fixed at generation time" behaviour bit-for-bit, which is both the + regression baseline and -- since CachePool instantiates no DMA -- the only + thing in this kernel that generates payload DRAM traffic. */ +#define RLC_TB_MODE_LEGACY 0 +#define RLC_TB_MODE_AM 1 +#ifndef RLC_TB_MODE +#define RLC_TB_MODE RLC_TB_MODE_LEGACY +#endif + +/* Execute back-end. COPY moves the payload into the transport block. SGL only + produces a scatter-gather descriptor per PDU, which is what a real + accelerator would hand to a DMA. Same plan either way, so the two are + directly comparable. */ +#define RLC_DL_EXEC_COPY 0 +#define RLC_DL_EXEC_SGL 1 +#ifndef RLC_DL_EXEC +#define RLC_DL_EXEC RLC_DL_EXEC_COPY +#endif + +/* Copy the payload with scalar byte stores instead of the e8/m8 vector copy. + Isolation knob: a protocol-accurate AMD header is 3 or 5 bytes, so the + payload destination inside the transport block is at an arbitrary byte + offset, and whether a vector unit handles an unaligned base at LMUL=8 is + exactly the thing in question. If the scalar copy is clean and the vector + copy is not, the copy is at fault; if both fail, the offsets feeding them + are. */ +#ifndef RLC_DL_COPY_SCALAR +#define RLC_DL_COPY_SCALAR 0 +#endif + +/* Bytes granted per entity per scheduling opportunity. A real TTI scheduler + replaces this (F6); until then it is a fixed knob. */ +#ifndef RLC_GRANT_BYTES +#define RLC_GRANT_BYTES 8192u +#endif + +/* The transport block is shared by every core that executes a grant. That is + only sound while those cores can see each other's writes to it. + + RLC_TB_BASE is above the l1d_addr boundary (default 0xA000_0000), so the + arena is classified PRIVATE -- and private banks are tile-local and not + visible to remote tiles (see the README, "Cache Partitioning"). With + main.c's l1d_part(num_cores_per_tile) every bank is private, so executors + on different tiles would write into *different* copies of the transport + block and the owner would only ever verify its own tile's half. + + Every configuration run so far is safe by accident: the data headers list + consumers {2,3} or {1}, all inside tile 0. It breaks silently the moment a + consumer list spans tiles, which is exactly what scaling executors means. + rlc_am_init() therefore checks this at startup and fails loudly. + + Two ways out when we do scale: move the arena below the boundary so it is + cluster-shared, or confine an entity's executors to the owner's tile (which + is also the tile-local placement the GVSoC-side design argues for). Until + one is chosen, set this to 1 only if you have made the arena visible + cluster-wide by other means. */ +#ifndef RLC_AM_ALLOW_CROSS_TILE_TB +#define RLC_AM_ALLOW_CROSS_TILE_TB 0 +#endif + +/* Transport-block arena. One TB per entity, carved from the target window + that the legacy path used for per-descriptor destinations. */ +#ifndef RLC_TB_BASE +#define RLC_TB_BASE 0xB0000000u +#endif +#ifndef RLC_TB_STRIDE +#define RLC_TB_STRIDE RLC_GRANT_BYTES +#endif + +/* TTI-structured consumer loop. + + 1 = plan / execute / commit run as three phases separated by a partial + hardware barrier over the consumer set. Helpers **block in the barrier** + instead of sweeping the entity list looking for work. + + That is the fix for the dominant cost measured on RTL: a helper was doing + 463 sweeps for a single grant, and enabling the bitmap work queue did not + rescue it, because cheapening each sweep does not stop the polling. With + this, a consumer that has nothing to do consumes nothing. + + It also gives the agreed cross-engine metric its unit of time: + ONE TTI = ONE GRANT OPPORTUNITY PER ENTITY + primary metric = bytes/cycle = (payload bytes) / (kernel cycles) + 0 keeps the original free-running loop for A/B comparison. */ +#ifndef RLC_AM_TTI +#define RLC_AM_TTI 1 +#endif + +/* Optional wallclock-flavoured pacing: pad each TTI to this many cycles. + 0 = unpaced (run flat out). 5000 is the agreed scaled TTI -- a 1:100 + scaling of 500 us at 1 GHz -- chosen so neither engine has to simulate + 500,000 cycles per data point. */ +#ifndef RLC_TTI_CYCLES +#define RLC_TTI_CYCLES 0 +#endif + +/* How far behind the transmitter the modelled UE acknowledges, in PDUs. The + kernel receives ACKs only (no NACK, no retransmission), so a fixed lag is + the whole feedback model -- but the STATUS PDU is really built and really + parsed, so its cost is measured rather than assumed away. */ +#ifndef RLC_AM_ACK_LAG +#define RLC_AM_ACK_LAG 4u +#endif + +/* Pad rlc_am_entity_t out to a full cache line, removing false sharing between + adjacent entities' atomics. + + Default ON: measured, and it removes a real defect. The struct is 124 B on + rv32, so without this the array packs entities at 124 B and neighbours share + cache lines -- and it holds gen/claim/done, the atomics every executing core + hammers. Which entities collide depends on the index (entity u starts at + 124u). Costs 4 B per entity. */ +#ifndef RLC_AM_ENT_PADDED +#define RLC_AM_ENT_PADDED 1 +#endif + +/* Dummy .data inserted ahead of the entity arrays, purely to shift every + subsequent address without changing any structure. Separates "the layout + moved" from "false sharing was removed" -- the two differ only in whether + the padding is inside the struct or in front of it. */ +#ifndef RLC_LAYOUT_PAD +#define RLC_LAYOUT_PAD 0 +#endif + +/* Work queue. 0 (default): every core visits every entity each step, which is + fine at 1..48 entities but is O(NUM_USERS) per step and does not survive + TC3's 4800. 1: entities announce themselves through two bitmaps, so a step + costs O(entities that actually have work). + + Default ON. The base AM path is validated on hardware (RTL transport-block + check passes end to end), and the scan-every-entity alternative was measured + to be untenable: 8 entities x 8 packets could not finish an hour of RTL even + with this enabled, because helpers poll. Without it, cost scales with the + entity count on every step. */ +#ifndef RLC_AM_WORKQ +#define RLC_AM_WORKQ 1 +#endif + +/* PDUs claimed per atomic operation by an executing core. Small enough to + balance a lopsided grant, large enough that the claim is not the cost. */ +#ifndef RLC_AM_CLAIM_CHUNK +#define RLC_AM_CLAIM_CHUNK 4u +#endif + +/* --- scatter-gather output (RLC_DL_EXEC_SGL) ----------------------------- */ + +typedef struct { + void *hdr; /* assembled RLC header inside the TB */ + uint32_t hdr_len; + void *src; /* payload source, already offset by SO */ + uint32_t len; +} rlc_sgl_t; + +/* --- per-entity assembly state ------------------------------------------- */ + +typedef struct { + /* Segmentation cursor: bytes of the SDU at the head of the to-send list + that have already been transmitted. Non-zero means that SDU stays queued + and its remainder leads the next grant. */ + uint32_t so_next; + + /* Published grant. `gen` is odd while a grant is open; plan/tb/n are + written before it is bumped and stay stable until the grant closes. */ + rlc_plan_t *plan; + uint8_t *tb; + uint32_t n; + uint32_t tb_used; + uint32_t partial; /* last planned PDU is a segment, its SDU stays */ + _Atomic uint32_t gen; + _Atomic uint32_t claim; /* next PDU index to hand out */ + _Atomic uint32_t done; /* PDUs finished */ + +#if RLC_DL_EXEC == RLC_DL_EXEC_SGL + rlc_sgl_t sgl[RLC_MAX_PDUS_PER_GRANT]; +#endif + + /* Cross-grant continuity expectations for the transport-block self-check: + the SN and segment offset the next grant must start from. */ + uint32_t verify_sn; + uint32_t verify_so; + + /* Which transport-block checks failed, as a bitmask, plus the first PDU + index that failed. Carried in the entity and printed from the summary so + the diagnosis does not depend on a per-grant printf surviving. */ + uint32_t verify_mask; + uint32_t verify_bad_idx; + uint32_t verify_have_bad; + /* Payload-mismatch detail: which destination alignments failed (bit a set + means a PDU whose payload started at addr%4 == a compared wrong), how many + PDUs compared wrong vs were checked, and the first differing byte offset. + If only the misaligned alignments appear, the copy is alignment-sensitive. */ + uint32_t verify_align_bad; + uint32_t verify_align_ok; + uint32_t verify_pay_bad; + uint32_t verify_pay_checked; + uint32_t verify_first_byte; + + /* instrumentation. Only the owner writes these, so no atomics needed. */ + uint32_t plan_calls; /* owner reached the plan attempt */ + uint32_t peek_empty; /* ... and the queue look-ahead returned 0 */ + uint32_t plan_zero; /* ... queue had SDUs but nothing was planned */ + uint32_t plan_ok; /* planner returned n > 0 */ + uint32_t peek_done; /* the queue look-ahead returned (vs still in it) */ + uint32_t poison_done; /* got past the pre-publish poison */ + uint32_t published; /* generation bumped, grant is live */ + uint32_t peek_max; /* largest look-ahead seen */ + uint32_t grants; + uint32_t pdus; + uint32_t segments; + uint32_t polls; +} +#if RLC_AM_ENT_PADDED +/* Pad each entity to a whole cache line. + + rlc_am_entity_t is 124 B on rv32 -- not a multiple of 64 -- so despite the + array being cache-line aligned, adjacent entities share lines. The struct + holds gen/claim/done, the atomics that every executing core hammers, so two + owners working on neighbouring entities ping-pong the same line. Which + entities collide depends on the index (entity u starts at 124u), which makes + the behaviour depend on entity count for a reason that has nothing to do + with the protocol. */ +__attribute__((aligned(CACHE_LINE_SIZE))) +#endif +rlc_am_entity_t; + +/* Per-consumer progress, indexed by consumer index. Distinguishes "the step + loop ran once" from "the step loop is stuck partway through the entity + sweep": steps counts completed sweeps, last_u the highest entity reached. */ +#ifndef RLC_AM_MAX_TRACKED_CONSUMERS +#define RLC_AM_MAX_TRACKED_CONSUMERS 16 +#endif + +/* Reset the AM state of one entity. Called from rlc_init(). */ +void rlc_am_init(uint32_t u); + +/* One step of the AM consumer for this core: plan an owned entity if it has + no grant open, and help execute whatever grants are open. Returns the + number of PDUs this core executed. */ +uint32_t rlc_am_step(uint32_t core_id); + +/* True once every entity is drained and no grant is open. */ +int rlc_am_idle(void); + +#if RLC_AM_WORKQ +/* Announce that entity u has data to send. Called by producers after they + enqueue, and by commit when an entity still has work left over. */ +void rlc_am_mark_ready(uint32_t u); +#endif + +/* Build a STATUS PDU for every entity, parse it back, and release the SDUs it + acknowledges. Runs on the status core, replacing the legacy fixed + "acknowledge two nodes" model. */ +void rlc_am_status(void); + +/* TTI-structured consumer entry point. Returns when every producer has + finished and every entity is drained. */ +void rlc_am_consumer_tti(uint32_t core_id); + +/* Print the AM summary (grants, PDUs, segments, polls) and, when the checks + are compiled in, the verdict. Call on one core after the final barrier. */ +void rlc_am_report(void); + +#endif /* RLC_AM_H */ diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_copy.h b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_copy.h new file mode 100644 index 0000000..55d8001 --- /dev/null +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_copy.h @@ -0,0 +1,57 @@ +// Copyright 2025 ETH Zurich and University of Bologna. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// Author: Zexin Fu + +/* Byte-granular payload copy, shared by the downlink TB assembler and the + uplink harness. Kept in its own header because both directions need it and + neither owns it. */ + +#ifndef RLC_COPY_H +#define RLC_COPY_H + +#include + +#ifndef RLC_DL_COPY_SCALAR +#define RLC_DL_COPY_SCALAR 0 +#endif + +/* A protocol-accurate AMD header is 3 or 5 bytes, so the payload inside the + transport block starts at an arbitrary byte offset -- the word-aligned + vector copies the legacy path uses cannot be applied here. (The legacy path + only got away with them because its placeholder header was a padded 10 + bytes and every destination was slot-aligned.) e8 elements need no more + than byte alignment, so this copies at m8: VLEN/8 * 8 = 512 B per pass at + VLEN=512. */ +static void rlc_memcpy8(uint8_t *dst, const uint8_t *src, uint32_t n) { +#if RLC_DL_COPY_SCALAR + for (uint32_t b = 0u; b < n; b++) dst[b] = src[b]; + asm volatile("fence" ::: "memory"); +#else + uint32_t i = 0; + while (i < n) { + uint32_t vl; + asm volatile("vsetvli %0, %1, e8, m8, ta, ma" : "=r"(vl) : "r"(n - i)); + if (vl == 0u) break; /* see RLC_VEC_GUARD in rlc_plan.c */ + asm volatile("vle8.v v8, (%0)" ::"r"(src + i) : "memory"); + asm volatile("vse8.v v8, (%0)" ::"r"(dst + i) : "memory"); + i += vl; + } + asm volatile("fence" ::: "memory"); +#endif +} + +#endif /* RLC_COPY_H */ diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_pdu.h b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_pdu.h new file mode 100644 index 0000000..42a7c86 --- /dev/null +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_pdu.h @@ -0,0 +1,184 @@ +// Copyright 2025 ETH Zurich and University of Bologna. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// Author: Zexin Fu + +/* RLC AM PDU formats -- 3GPP TS 38.322 ยง6.2.2.4 (AMD PDU) and ยง6.2.2.5 + (STATUS PDU). + + The legacy kernel wrote a bare 32-bit sequence number into a 10-byte + placeholder header. That is enough to make the payload copy measurable but + it models none of the constraints that make RLC hard to parallelise: the + header carries the poll bit (a cumulative, order-dependent decision) and the + segmentation info + segment offset (which depend on the running grant fill). + This header emits the real thing. + + All fields are packed big-endian / network bit order, so serialisation is + byte-by-byte rather than a word store. */ + +#ifndef RLC_PDU_H +#define RLC_PDU_H + +#include + +/* SN length. TS 38.322 allows 12 or 18 bits for AM; the kernel has always + assumed 18 (matching the Huawei DP test cases). */ +#ifndef RLC_SN_BITS +#define RLC_SN_BITS 18 +#endif + +#if (RLC_SN_BITS != 12) && (RLC_SN_BITS != 18) +#error "RLC AM supports only a 12- or 18-bit SN" +#endif + +#define RLC_SN_MASK ((1u << RLC_SN_BITS) - 1u) + +/* Sequence numbers live in a modulo-2^RLC_SN_BITS space, so ordering is + comparison against half the window rather than plain <. */ +static inline int rlc_sn_lt(uint32_t a, uint32_t b) { + return (int)(((b - a) & RLC_SN_MASK) != 0u) && + (((b - a) & RLC_SN_MASK) < ((RLC_SN_MASK + 1u) >> 1)); +} + +/* D/C field (ยง6.2.3.1) */ +#define RLC_DC_CONTROL 0u +#define RLC_DC_DATA 1u + +/* SI field (ยง6.2.3.4) */ +#define RLC_SI_FULL 0u /* complete SDU, no segmentation */ +#define RLC_SI_FIRST 1u /* first segment of an SDU */ +#define RLC_SI_LAST 2u /* last segment of an SDU */ +#define RLC_SI_MIDDLE 3u /* neither the first nor the last */ + +/* SO is present only when the segment does not start at offset 0, i.e. for + the LAST and MIDDLE segments (ยง6.2.2.4). */ +#define RLC_SI_HAS_SO(si) (((si) == RLC_SI_LAST) || ((si) == RLC_SI_MIDDLE)) + +#if RLC_SN_BITS == 18 +/* Oct1: D/C | P | SI(2) | R | R | SN[17:16] + Oct2: SN[15:8] + Oct3: SN[7:0] */ +#define RLC_AMD_HDR_MIN 3u +#else +/* Oct1: D/C | P | SI(2) | SN[11:8] + Oct2: SN[7:0] */ +#define RLC_AMD_HDR_MIN 2u +#endif +#define RLC_AMD_HDR_SO 2u /* SO(16) */ +#define RLC_AMD_HDR_MAX (RLC_AMD_HDR_MIN + RLC_AMD_HDR_SO) + +/* Header length implied by an SI value. Kept branch-free: the planner + evaluates this for every PDU in a grant. */ +static inline uint32_t rlc_amd_hdr_len(uint32_t si) { + return RLC_AMD_HDR_MIN + (RLC_SI_HAS_SO(si) ? RLC_AMD_HDR_SO : 0u); +} + +/* Serialise one AMD PDU header at p. Returns the number of bytes written. */ +static inline uint32_t rlc_amd_hdr_write(uint8_t *p, uint32_t sn, uint32_t si, + uint32_t poll, uint32_t so) { + sn &= RLC_SN_MASK; +#if RLC_SN_BITS == 18 + p[0] = (uint8_t)((RLC_DC_DATA << 7) | ((poll & 1u) << 6) | + ((si & 3u) << 4) | ((sn >> 16) & 0x3u)); + p[1] = (uint8_t)((sn >> 8) & 0xFFu); + p[2] = (uint8_t)(sn & 0xFFu); +#else + p[0] = (uint8_t)((RLC_DC_DATA << 7) | ((poll & 1u) << 6) | + ((si & 3u) << 4) | ((sn >> 8) & 0xFu)); + p[1] = (uint8_t)(sn & 0xFFu); +#endif + if (RLC_SI_HAS_SO(si)) { + p[RLC_AMD_HDR_MIN + 0] = (uint8_t)((so >> 8) & 0xFFu); + p[RLC_AMD_HDR_MIN + 1] = (uint8_t)(so & 0xFFu); + return RLC_AMD_HDR_MIN + RLC_AMD_HDR_SO; + } + return RLC_AMD_HDR_MIN; +} + +/* Parse an AMD PDU header. Mirrors rlc_amd_hdr_write; used by the self-check + to decode an assembled transport block back into a PDU sequence. */ +typedef struct { + uint32_t sn; + uint32_t si; + uint32_t poll; + uint32_t so; + uint32_t hdr_len; +} rlc_amd_hdr_t; + +static inline void rlc_amd_hdr_read(const uint8_t *p, rlc_amd_hdr_t *h) { + h->poll = (p[0] >> 6) & 1u; + h->si = (p[0] >> 4) & 3u; +#if RLC_SN_BITS == 18 + h->sn = (((uint32_t)p[0] & 0x3u) << 16) | ((uint32_t)p[1] << 8) | p[2]; +#else + h->sn = (((uint32_t)p[0] & 0xFu) << 8) | p[1]; +#endif + if (RLC_SI_HAS_SO(h->si)) { + h->so = ((uint32_t)p[RLC_AMD_HDR_MIN] << 8) | p[RLC_AMD_HDR_MIN + 1]; + h->hdr_len = RLC_AMD_HDR_MIN + RLC_AMD_HDR_SO; + } else { + h->so = 0u; + h->hdr_len = RLC_AMD_HDR_MIN; + } +} + +/* ---- STATUS PDU (ยง6.2.2.5) -------------------------------------------- + Groundwork for replacing the hardcoded "ACK two PDUs" model with a real + status report. Under the ACK-only assumption the NACK list stays empty, but + the build/parse cost is then modelled rather than assumed away. */ + +#define RLC_CPT_STATUS 0u + +#if RLC_SN_BITS == 18 +#define RLC_STATUS_HDR_LEN 3u /* D/C|CPT(3)|ACK_SN[17:14] | [13:6] | [5:0]|E1|R */ +#else +#define RLC_STATUS_HDR_LEN 2u /* D/C|CPT(3)|ACK_SN[11:8] | [7:0] ... + E1|R */ +#endif + +/* Serialise a STATUS PDU header with the given ACK_SN. e1 = 1 when at least + one NACK_SN record follows. Returns bytes written. */ +static inline uint32_t rlc_status_hdr_write(uint8_t *p, uint32_t ack_sn, + uint32_t e1) { + ack_sn &= RLC_SN_MASK; +#if RLC_SN_BITS == 18 + p[0] = (uint8_t)((RLC_DC_CONTROL << 7) | ((RLC_CPT_STATUS & 7u) << 4) | + ((ack_sn >> 14) & 0xFu)); + p[1] = (uint8_t)((ack_sn >> 6) & 0xFFu); + p[2] = (uint8_t)(((ack_sn & 0x3Fu) << 2) | ((e1 & 1u) << 1)); + return 3u; +#else + p[0] = (uint8_t)((RLC_DC_CONTROL << 7) | ((RLC_CPT_STATUS & 7u) << 4) | + ((ack_sn >> 8) & 0xFu)); + p[1] = (uint8_t)(ack_sn & 0xFFu); + p[2] = (uint8_t)((e1 & 1u) << 7); + return 3u; +#endif +} + +static inline uint32_t rlc_status_hdr_read(const uint8_t *p, uint32_t *ack_sn, + uint32_t *e1) { +#if RLC_SN_BITS == 18 + *ack_sn = (((uint32_t)p[0] & 0xFu) << 14) | ((uint32_t)p[1] << 6) | + ((uint32_t)p[2] >> 2); + *e1 = (p[2] >> 1) & 1u; +#else + *ack_sn = (((uint32_t)p[0] & 0xFu) << 8) | p[1]; + *e1 = (p[2] >> 7) & 1u; +#endif + return 3u; +} + +#endif /* RLC_PDU_H */ diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_plan.c b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_plan.c new file mode 100644 index 0000000..c1158b2 --- /dev/null +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_plan.c @@ -0,0 +1,676 @@ +// Copyright 2025 ETH Zurich and University of Bologna. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// Author: Zexin Fu + +/* RLC AM grant planner -- see rlc_plan.h for the role of this stage. + + Two implementations live here: + rlc_plan_compute_scalar() the reference / specification + rlc_plan_compute_vector() the RVV version actually used + + The vector version exists because the plan stage, although logically + serial, is almost entirely *data-parallel arithmetic* once the queue has + been walked: + + - the transport-block offsets are an inclusive prefix sum of PDU lengths + - the SN assignment is base + lane index + - the segment boundary is "first lane whose running sum exceeds the grant" + - the poll positions are threshold crossings of two running counters + + Prefix sums and first-crossing searches both map onto RVV. Spatz decodes no + vid.v / viota.m / vcpop.m, so lane indices come from a static table and + first-set-lane is done with a masked merge against a sentinel followed by + an unsigned min-reduction. */ + +#ifndef RLC_PLAN_C +#define RLC_PLAN_C + +#include + +#include "rlc_plan.h" + +/* Counts vsetvli results of zero. Declared outside the vector guard so the + scalar build can report it (always 0 there) without a second #if. */ +_Atomic uint32_t rlc_vec_zero_vl; + +/* The planner's primitives -- prefix sum, first-crossing search, and a few + elementwise maps -- have two implementations with identical semantics: RVV + under RLC_PLAN_VECTOR, plain C otherwise. The scan-based planner that uses + them is built either way, so -DRLC_PLAN_VECTOR=0 yields a pure-C + translation unit whose *algorithm* is the same one that runs on target. + test/test_rlc_plan.c exploits that to diff the scan planner against the + reference planner on the host, leaving only RVV codegen to be checked on + hardware (RLC_PLAN_VERIFY). */ +/* RVV forms. Compiled whenever any primitive is vectorised. */ +#if RLC_PLAN_VECTOR + +/* ------------------------------------------------------------------------ */ +/* RVV helpers */ +/* ------------------------------------------------------------------------ */ + +/* Lane indices. Spatz has no vid.v, so the iota comes from memory. Sized to + RLC_MAX_PDUS_PER_GRANT, which bounds every vector length used here. */ +static const uint32_t rlc_iota[RLC_MAX_PDUS_PER_GRANT] __attribute__((aligned(64))) = { + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, + 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, + 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, + 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, + 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, + 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, + 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, + 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, +}; + +#define RLC_VEC_NONE 0xFFFFFFFFu + +/* Every vector loop below advances by the vl that vsetvli returns. A vl of 0 + would therefore spin forever -- the worst possible symptom, because it + presents as a silent hang with no state to inspect. vsetvli must not return + 0 for a non-zero AVL with a legal vtype, so this can only fire on a broken + decoder or an unsupported vtype, but the cost of the check is one branch + per chunk and it converts a hang into an observable counter. */ +/* Deliberately NOT wrapped in do{}while(0): the break must escape the caller's + chunk loop, and inside a do-while wrapper it would escape only the wrapper + and spin anyway. Only ever used as a statement directly inside those loops. */ +#define RLC_VEC_GUARD(vl) \ + if ((vl) == 0u) { \ + atomic_fetch_add_explicit(&rlc_vec_zero_vl, 1u, memory_order_relaxed); \ + break; \ + } + +/* Snitch's scalar LSU and Spatz's vector LSU are independent, so a scalar + access can bypass an outstanding vector access to the same address. Every + scalar<->vector handoff on the plan arrays is bracketed by a fence, which + drains both (this is what snrt_fence() emits; spelled out here so the + planner stays independent of snRuntime and can be exercised standalone). */ +#define RLC_VEC_FENCE() asm volatile("fence" ::: "memory") + +/* dst[0..n) = inclusive prefix sum of src[0..n). + Hillis-Steele log-scan inside each vector chunk, scalar carry across chunks: + ceil(log2(vl)) vector adds per chunk instead of vl scalar adds. */ +static void __attribute__((unused)) rlc_vec_prefix_sum_u32_rvv(uint32_t *dst, const uint32_t *src, + uint32_t n) { + uint32_t carry = 0; + uint32_t i = 0; + RLC_VEC_FENCE(); + while (i < n) { + uint32_t vl; + asm volatile("vsetvli %0, %1, e32, m4, ta, ma" : "=r"(vl) : "r"(n - i)); + RLC_VEC_GUARD(vl); + asm volatile("vle32.v v8, (%0)" ::"r"(src + i) : "memory"); + /* v8 <- inclusive scan of v8 */ + for (uint32_t ofs = 1; ofs < vl; ofs <<= 1) { + /* vslideup leaves lanes [0,ofs) untouched, so zero the destination + first -- those lanes must contribute nothing to the sum. */ + asm volatile("vmv.v.i v16, 0"); + asm volatile("vslideup.vx v16, v8, %0" ::"r"(ofs)); + asm volatile("vadd.vv v8, v8, v16"); + } + asm volatile("vadd.vx v8, v8, %0" ::"r"(carry)); + asm volatile("vse32.v v8, (%0)" ::"r"(dst + i) : "memory"); + /* Carry into the next chunk is the last lane. Taken out of the vector + register rather than re-read from dst[] -- a scalar load here would + race the vector store that has just been issued. */ + asm volatile("vslidedown.vx v16, v8, %0" ::"r"(vl - 1)); + asm volatile("vmv.x.s %0, v16" : "=r"(carry)); + i += vl; + } + RLC_VEC_FENCE(); +} + +/* Smallest i in [start,n) with val[i] > thr, or n if there is none. + Masked merge of the lane index against a sentinel, then an unsigned + min-reduction -- Spatz decodes neither vfirst.m nor viota.m. */ +static uint32_t __attribute__((unused)) rlc_vec_first_gt_u32_rvv(const uint32_t *val, uint32_t start, + uint32_t n, uint32_t thr) { + uint32_t i = start; + RLC_VEC_FENCE(); + while (i < n) { + uint32_t vl; + uint32_t lane; + asm volatile("vsetvli %0, %1, e32, m4, ta, ma" : "=r"(vl) : "r"(n - i)); + RLC_VEC_GUARD(vl); + asm volatile("vle32.v v8, (%0)" ::"r"(val + i) : "memory"); + asm volatile("vle32.v v12, (%0)" ::"r"(rlc_iota) : "memory"); + asm volatile("vmsgtu.vx v0, v8, %0" ::"r"(thr)); + asm volatile("vmv.v.x v16, %0" ::"r"(RLC_VEC_NONE)); + asm volatile("vmerge.vvm v16, v16, v12, v0"); + asm volatile("vmv.s.x v24, %0" ::"r"(RLC_VEC_NONE)); + asm volatile("vredminu.vs v24, v16, v24"); + asm volatile("vmv.x.s %0, v24" : "=r"(lane)); + if (lane != RLC_VEC_NONE) { + RLC_VEC_FENCE(); + return i + lane; + } + i += vl; + } + RLC_VEC_FENCE(); + return n; +} + +/* dst[0..n) = (base + i) & mask */ +static void __attribute__((unused)) rlc_vec_iota_add_u32_rvv(uint32_t *dst, uint32_t base, uint32_t mask, + uint32_t n) { + uint32_t i = 0; + RLC_VEC_FENCE(); + while (i < n) { + uint32_t vl; + asm volatile("vsetvli %0, %1, e32, m4, ta, ma" : "=r"(vl) : "r"(n - i)); + RLC_VEC_GUARD(vl); + asm volatile("vle32.v v8, (%0)" ::"r"(rlc_iota) : "memory"); + asm volatile("vadd.vx v8, v8, %0" ::"r"(base + i)); + asm volatile("vand.vx v8, v8, %0" ::"r"(mask)); + asm volatile("vse32.v v8, (%0)" ::"r"(dst + i) : "memory"); + i += vl; + } + RLC_VEC_FENCE(); +} + +/* dst[0..n) = a[0..n) - b[0..n) */ +static void __attribute__((unused)) rlc_vec_sub_u32_rvv(uint32_t *dst, const uint32_t *a, const uint32_t *b, + uint32_t n) { + uint32_t i = 0; + RLC_VEC_FENCE(); + while (i < n) { + uint32_t vl; + asm volatile("vsetvli %0, %1, e32, m4, ta, ma" : "=r"(vl) : "r"(n - i)); + RLC_VEC_GUARD(vl); + asm volatile("vle32.v v8, (%0)" ::"r"(a + i) : "memory"); + asm volatile("vle32.v v12, (%0)" ::"r"(b + i) : "memory"); + asm volatile("vsub.vv v8, v8, v12"); + asm volatile("vse32.v v8, (%0)" ::"r"(dst + i) : "memory"); + i += vl; + } + RLC_VEC_FENCE(); +} + +/* dst[0..n) = a[0..n) - imm */ +static void __attribute__((unused)) rlc_vec_subx_u32_rvv(uint32_t *dst, const uint32_t *a, uint32_t imm, + uint32_t n) { + uint32_t i = 0; + RLC_VEC_FENCE(); + while (i < n) { + uint32_t vl; + asm volatile("vsetvli %0, %1, e32, m4, ta, ma" : "=r"(vl) : "r"(n - i)); + RLC_VEC_GUARD(vl); + asm volatile("vle32.v v8, (%0)" ::"r"(a + i) : "memory"); + asm volatile("vsub.vx v8, v8, %0" ::"r"(imm)); + asm volatile("vse32.v v8, (%0)" ::"r"(dst + i) : "memory"); + i += vl; + } + RLC_VEC_FENCE(); +} + +/* dst[0..n) = a[0..n) + imm */ +static void __attribute__((unused)) rlc_vec_addx_u32_rvv(uint32_t *dst, const uint32_t *a, uint32_t imm, + uint32_t n) { + uint32_t i = 0; + RLC_VEC_FENCE(); + while (i < n) { + uint32_t vl; + asm volatile("vsetvli %0, %1, e32, m4, ta, ma" : "=r"(vl) : "r"(n - i)); + RLC_VEC_GUARD(vl); + asm volatile("vle32.v v8, (%0)" ::"r"(a + i) : "memory"); + asm volatile("vadd.vx v8, v8, %0" ::"r"(imm)); + asm volatile("vse32.v v8, (%0)" ::"r"(dst + i) : "memory"); + i += vl; + } + RLC_VEC_FENCE(); +} + +/* dst[0..n) = val */ +static void __attribute__((unused)) rlc_vec_fill_u32_rvv(uint32_t *dst, uint32_t val, uint32_t n) { + uint32_t i = 0; + RLC_VEC_FENCE(); + while (i < n) { + uint32_t vl; + asm volatile("vsetvli %0, %1, e32, m4, ta, ma" : "=r"(vl) : "r"(n - i)); + RLC_VEC_GUARD(vl); + asm volatile("vmv.v.x v8, %0" ::"r"(val)); + asm volatile("vse32.v v8, (%0)" ::"r"(dst + i) : "memory"); + i += vl; + } + RLC_VEC_FENCE(); +} + +#endif /* RLC_PLAN_VECTOR */ + +/* Plain-C twins. Always compiled: they are the host build's implementation + and the fallback for every primitive whose bit is clear. */ + +#define RLC_VEC_NONE_C 0xFFFFFFFFu + +static void __attribute__((unused)) rlc_vec_prefix_sum_u32_c(uint32_t *dst, const uint32_t *src, + uint32_t n) { + uint32_t acc = 0u; + for (uint32_t i = 0u; i < n; i++) { acc += src[i]; dst[i] = acc; } +} + +static uint32_t __attribute__((unused)) rlc_vec_first_gt_u32_c(const uint32_t *val, uint32_t start, + uint32_t n, uint32_t thr) { + for (uint32_t i = start; i < n; i++) + if (val[i] > thr) return i; + return n; +} + +static void __attribute__((unused)) rlc_vec_iota_add_u32_c(uint32_t *dst, uint32_t base, uint32_t mask, + uint32_t n) { + for (uint32_t i = 0u; i < n; i++) dst[i] = (base + i) & mask; +} + +static void __attribute__((unused)) rlc_vec_sub_u32_c(uint32_t *dst, const uint32_t *a, const uint32_t *b, + uint32_t n) { + for (uint32_t i = 0u; i < n; i++) dst[i] = a[i] - b[i]; +} + +static void __attribute__((unused)) rlc_vec_subx_u32_c(uint32_t *dst, const uint32_t *a, uint32_t imm, + uint32_t n) { + for (uint32_t i = 0u; i < n; i++) dst[i] = a[i] - imm; +} + +static void __attribute__((unused)) rlc_vec_addx_u32_c(uint32_t *dst, const uint32_t *a, uint32_t imm, + uint32_t n) { + for (uint32_t i = 0u; i < n; i++) dst[i] = a[i] + imm; +} + +static void __attribute__((unused)) rlc_vec_fill_u32_c(uint32_t *dst, uint32_t val, uint32_t n) { + for (uint32_t i = 0u; i < n; i++) dst[i] = val; +} + + +/* ---- per-primitive dispatch ------------------------------------------- */ +/* Each selects its RVV form or its C twin independently, so RLC_PLAN_VECTOR + can isolate one primitive at a time. */ + +static inline void rlc_vec_prefix_sum_u32(uint32_t *d, const uint32_t *s, uint32_t n) { +#if RLC_VEC_SCAN + rlc_vec_prefix_sum_u32_rvv(d, s, n); +#else + rlc_vec_prefix_sum_u32_c(d, s, n); +#endif +} +static inline uint32_t rlc_vec_first_gt_u32(const uint32_t *v, uint32_t st, uint32_t n, uint32_t t) { +#if RLC_VEC_SEARCH + return rlc_vec_first_gt_u32_rvv(v, st, n, t); +#else + return rlc_vec_first_gt_u32_c(v, st, n, t); +#endif +} +static inline void rlc_vec_iota_add_u32(uint32_t *d, uint32_t b, uint32_t m, uint32_t n) { +#if RLC_VEC_MAPS + rlc_vec_iota_add_u32_rvv(d, b, m, n); +#else + rlc_vec_iota_add_u32_c(d, b, m, n); +#endif +} +static inline void rlc_vec_sub_u32(uint32_t *d, const uint32_t *a, const uint32_t *b, uint32_t n) { +#if RLC_VEC_MAPS + rlc_vec_sub_u32_rvv(d, a, b, n); +#else + rlc_vec_sub_u32_c(d, a, b, n); +#endif +} +static inline void rlc_vec_subx_u32(uint32_t *d, const uint32_t *a, uint32_t i, uint32_t n) { +#if RLC_VEC_MAPS + rlc_vec_subx_u32_rvv(d, a, i, n); +#else + rlc_vec_subx_u32_c(d, a, i, n); +#endif +} +static inline void rlc_vec_addx_u32(uint32_t *d, const uint32_t *a, uint32_t i, uint32_t n) { +#if RLC_VEC_MAPS + rlc_vec_addx_u32_rvv(d, a, i, n); +#else + rlc_vec_addx_u32_c(d, a, i, n); +#endif +} +static inline void rlc_vec_fill_u32(uint32_t *d, uint32_t v, uint32_t n) { +#if RLC_VEC_MAPS + rlc_vec_fill_u32_rvv(d, v, n); +#else + rlc_vec_fill_u32_c(d, v, n); +#endif +} + + + +/* ------------------------------------------------------------------------ */ +/* Shared tail: the poll decision */ +/* ------------------------------------------------------------------------ */ + +/* TS 38.322 ยง5.3.3.2: on every AMD PDU carrying an SDU or SDU segment, + PDU_WITHOUT_POLL and BYTE_WITHOUT_POLL advance; crossing pollPDU or + pollByte sets the P bit and resets both counters. A poll is also sent when + the transmission buffer runs empty. + + Two properties make this cheap to vectorise: + - between two polls the PDU counter is a pure lane offset, so the next + PDU-threshold crossing is closed-form, no search needed; + - the byte counter is the prefix sum of seg_len, so the next + byte-threshold crossing is one first-greater-than search. + The loop therefore runs once per poll event, not once per PDU. */ +static void rlc_plan_polls_vector(rlc_plan_t *plan, const rlc_plan_in_t *in, + uint32_t n, uint32_t *pwp_io, + uint32_t *bwp_io) { + uint32_t pwp = *pwp_io; + uint32_t bwp = *bwp_io; + uint32_t start = 0; + + rlc_vec_fill_u32(plan->poll, 0u, n); + rlc_vec_prefix_sum_u32(plan->bcum, plan->seg_len, n); + + while (start < n) { + /* PDU-count crossing: pwp + (i - start + 1) >= poll_pdu */ + uint32_t i_pdu = n; + if (in->poll_pdu != 0u) { + uint32_t need = (in->poll_pdu > pwp) ? (in->poll_pdu - pwp) : 1u; + i_pdu = start + need - 1u; + if (i_pdu >= n) i_pdu = n; + } + /* Byte-count crossing: bwp + (bcum[i] - base) >= poll_byte, i.e. the + first bcum[i] strictly greater than (poll_byte - bwp - 1 + base). */ + uint32_t i_byte = n; + if (in->poll_byte != 0u) { + uint32_t base = (start == 0u) ? 0u : plan->bcum[start - 1u]; + if (bwp >= in->poll_byte) { + i_byte = start; + } else { + uint32_t thr = in->poll_byte - bwp - 1u + base; + i_byte = rlc_vec_first_gt_u32(plan->bcum, start, n, thr); + } + } + uint32_t k = (i_pdu < i_byte) ? i_pdu : i_byte; + if (k >= n) break; + plan->poll[k] = 1u; + pwp = 0u; + bwp = 0u; + start = k + 1u; + } + + /* Account for the PDUs after the last poll. */ + if (n > 0u) { + uint32_t base = (start == 0u) ? 0u : plan->bcum[start - 1u]; + pwp += (n - start); + bwp += plan->bcum[n - 1u] - base; + } + *pwp_io = pwp; + *bwp_io = bwp; +} + +/* ------------------------------------------------------------------------ */ +/* Scalar reference */ +/* ------------------------------------------------------------------------ */ + +uint32_t rlc_plan_compute_scalar(rlc_plan_t *plan, const rlc_plan_in_t *in, + rlc_plan_out_t *out) { + const uint32_t G = in->grant_bytes; + uint32_t cum = 0u; + uint32_t sn = in->sn_base; + uint32_t pwp = in->pdu_without_poll; + uint32_t bwp = in->byte_without_poll; + uint32_t n = 0u; + uint32_t partial = 0u; + uint32_t so_next = 0u; + + for (uint32_t i = 0u; i < plan->n_avail && n < RLC_MAX_PDUS_PER_GRANT; i++) { + /* Only the first entry can continue a partially transmitted SDU. */ + const uint32_t seg_so = (i == 0u) ? in->so_first : 0u; + const uint32_t remaining = plan->sdu_len[i] - seg_so; + /* Header length depends only on whether SO is present, and SO is present + exactly when this PDU does not start at offset 0 -- independent of + whether the PDU also ends up segmented. */ + const uint32_t hdr = (seg_so == 0u) ? RLC_AMD_HDR_MIN : RLC_AMD_HDR_MAX; + + if (cum + hdr >= G) break; /* no room for a header plus a payload byte */ + const uint32_t room = G - cum - hdr; + + uint32_t seg_len, si, last; + if (remaining <= room) { + seg_len = remaining; + si = (seg_so == 0u) ? RLC_SI_FULL : RLC_SI_LAST; + last = 1u; + } else { + seg_len = room; + si = (seg_so == 0u) ? RLC_SI_FIRST : RLC_SI_MIDDLE; + last = 0u; + } + + plan->sn[n] = sn & RLC_SN_MASK; + plan->so[n] = seg_so; + plan->seg_len[n] = seg_len; + plan->si[n] = si; + plan->hdr_len[n] = hdr; + plan->tb_off[n] = cum; + plan->last_seg[n] = last; + + /* Poll counters (ยง5.3.3.2). */ + pwp += 1u; + bwp += seg_len; + uint32_t p = 0u; + if (in->poll_pdu != 0u && pwp >= in->poll_pdu) { + p = 1u; + } else if (in->poll_byte != 0u && bwp >= in->poll_byte) { + p = 1u; + } + if (p) { + pwp = 0u; + bwp = 0u; + } + plan->poll[n] = p; + + cum += hdr + seg_len; + sn++; + n++; + + if (!last) { + /* The grant is exactly full by construction; the SDU remainder waits. */ + partial = 1u; + so_next = seg_so + seg_len; + break; + } + } + + /* A poll is also triggered when the buffer runs empty (ยง5.3.3.2). */ + if (n > 0u && in->queue_drained && !partial && !plan->poll[n - 1u]) { + plan->poll[n - 1u] = 1u; + pwp = 0u; + bwp = 0u; + } + + plan->n = n; + plan->tb_used = cum; + /* The SN identifies the SDU, not the PDU: every segment of one SDU carries + the same SN, with SO distinguishing them (TS 38.322 6.2.2.4). So a grant + whose last PDU is a segment leaves that SDU's SN still in use, and the + next grant's leading segment must reuse it -- advancing here would open a + hole the receiver can never fill, because the missing SN is never sent. */ + out->sn_next = (in->sn_base + n - partial) & RLC_SN_MASK; + out->pdu_without_poll = pwp; + out->byte_without_poll = bwp; + out->so_next = so_next; + out->partial = partial; + return n; +} + +/* ------------------------------------------------------------------------ */ +/* Scan-based planner (RVV primitives when RLC_PLAN_VECTOR) */ +/* ------------------------------------------------------------------------ */ + +uint32_t rlc_plan_compute_vector(rlc_plan_t *plan, const rlc_plan_in_t *in, + rlc_plan_out_t *out) { + const uint32_t G = in->grant_bytes; + uint32_t n_avail = plan->n_avail; + if (n_avail > RLC_MAX_PDUS_PER_GRANT) n_avail = RLC_MAX_PDUS_PER_GRANT; + + if (n_avail == 0u) { + plan->n = 0u; + plan->tb_used = 0u; + out->sn_next = in->sn_base & RLC_SN_MASK; + out->pdu_without_poll = in->pdu_without_poll; + out->byte_without_poll = in->byte_without_poll; + out->so_next = 0u; + out->partial = 0u; + return 0u; + } + + /* 1. Provisional PDU lengths, assuming every SDU is sent whole. Only lane 0 + can carry an SO, so the vector pass uses the common header length and + lane 0 is corrected afterwards. */ + rlc_vec_addx_u32(plan->pdu_len, plan->sdu_len, RLC_AMD_HDR_MIN, n_avail); + const uint32_t hdr0 = (in->so_first == 0u) ? RLC_AMD_HDR_MIN : RLC_AMD_HDR_MAX; + plan->pdu_len[0] = plan->sdu_len[0] - in->so_first + hdr0; + + /* 2. Running transport-block fill. */ + rlc_vec_prefix_sum_u32(plan->cum, plan->pdu_len, n_avail); + + /* 3. First PDU that overflows the grant -- the segmentation candidate. */ + const uint32_t k = rlc_vec_first_gt_u32(plan->cum, 0u, n_avail, G); + + uint32_t n, partial = 0u, so_next = 0u; + if (k >= n_avail) { + n = n_avail; /* the whole gathered queue fits */ + } else { + const uint32_t base = (k == 0u) ? 0u : plan->cum[k - 1u]; + const uint32_t hdr_k = (k == 0u) ? hdr0 : RLC_AMD_HDR_MIN; + if (base + hdr_k < G) { + n = k + 1u; /* PDU k is carried as a segment */ + partial = 1u; + } else { + n = k; /* not even a header fits; PDU k waits for the next grant */ + } + } + + if (n == 0u) { + plan->n = 0u; + plan->tb_used = 0u; + out->sn_next = in->sn_base & RLC_SN_MASK; + out->pdu_without_poll = in->pdu_without_poll; + out->byte_without_poll = in->byte_without_poll; + out->so_next = 0u; + out->partial = 0u; + return 0u; + } + + /* 4. Fields that are uniform across the plan, then the lane-0 and + segmented-tail corrections. */ + rlc_vec_subx_u32(plan->seg_len, plan->pdu_len, RLC_AMD_HDR_MIN, n); + rlc_vec_fill_u32(plan->hdr_len, RLC_AMD_HDR_MIN, n); + rlc_vec_fill_u32(plan->si, RLC_SI_FULL, n); + rlc_vec_fill_u32(plan->so, 0u, n); + rlc_vec_fill_u32(plan->last_seg, 1u, n); + + /* tb_off is the exclusive scan, i.e. cum - pdu_len. */ + rlc_vec_sub_u32(plan->tb_off, plan->cum, plan->pdu_len, n); + + /* SN is base + lane. */ + rlc_vec_iota_add_u32(plan->sn, in->sn_base, RLC_SN_MASK, n); + + /* Lane 0 continues a segmented SDU. */ + if (in->so_first != 0u) { + plan->hdr_len[0] = hdr0; + plan->so[0] = in->so_first; + plan->seg_len[0] = plan->pdu_len[0] - hdr0; + plan->si[0] = RLC_SI_LAST; /* refined below if it is segmented again */ + } + + /* The trailing PDU is truncated to fill the grant exactly. */ + if (partial) { + const uint32_t j = n - 1u; + const uint32_t base = (j == 0u) ? 0u : plan->cum[j - 1u]; + const uint32_t hdr_j = plan->hdr_len[j]; + plan->tb_off[j] = base; + plan->seg_len[j] = G - base - hdr_j; + plan->si[j] = (plan->so[j] == 0u) ? RLC_SI_FIRST : RLC_SI_MIDDLE; + plan->last_seg[j] = 0u; + so_next = plan->so[j] + plan->seg_len[j]; + plan->tb_used = G; + } else { + plan->tb_used = plan->cum[n - 1u]; + } + + /* 5. Poll bits over the final seg_len values. */ + uint32_t pwp = in->pdu_without_poll; + uint32_t bwp = in->byte_without_poll; + rlc_plan_polls_vector(plan, in, n, &pwp, &bwp); + + if (in->queue_drained && !partial && !plan->poll[n - 1u]) { + plan->poll[n - 1u] = 1u; + pwp = 0u; + bwp = 0u; + } + + plan->n = n; + /* See the note in rlc_plan_compute_scalar(): SN is per SDU, so a trailing + segment does not consume one. */ + out->sn_next = (in->sn_base + n - partial) & RLC_SN_MASK; + out->pdu_without_poll = pwp; + out->byte_without_poll = bwp; + out->so_next = so_next; + out->partial = partial; + return n; +} + +/* ------------------------------------------------------------------------ */ + +uint32_t rlc_plan_compute_checked(rlc_plan_t *plan, rlc_plan_t *ref, + const rlc_plan_in_t *in, rlc_plan_out_t *out, + uint32_t *nbad) { + rlc_plan_out_t ref_out; + uint32_t bad = 0u; + + /* The reference needs the same gathered inputs. */ + ref->n_avail = plan->n_avail; + for (uint32_t i = 0u; i < plan->n_avail; i++) ref->sdu_len[i] = plan->sdu_len[i]; + + const uint32_t n_ref = rlc_plan_compute_scalar(ref, in, &ref_out); + const uint32_t n_vec = rlc_plan_compute_vector(plan, in, out); + + if (n_ref != n_vec) { + bad++; + } else { + for (uint32_t i = 0u; i < n_vec; i++) { + if (plan->sn[i] != ref->sn[i]) bad++; + if (plan->tb_off[i] != ref->tb_off[i]) bad++; + if (plan->seg_len[i] != ref->seg_len[i]) bad++; + if (plan->so[i] != ref->so[i]) bad++; + if (plan->si[i] != ref->si[i]) bad++; + if (plan->poll[i] != ref->poll[i]) bad++; + if (plan->hdr_len[i] != ref->hdr_len[i]) bad++; + if (plan->last_seg[i] != ref->last_seg[i]) bad++; + } + } + if (plan->tb_used != ref->tb_used) bad++; + if (out->sn_next != ref_out.sn_next) bad++; + if (out->pdu_without_poll != ref_out.pdu_without_poll) bad++; + if (out->byte_without_poll != ref_out.byte_without_poll) bad++; + if (out->so_next != ref_out.so_next) bad++; + if (out->partial != ref_out.partial) bad++; + + if (nbad) *nbad = bad; + return n_vec; +} + +uint32_t rlc_plan_compute(rlc_plan_t *plan, const rlc_plan_in_t *in, + rlc_plan_out_t *out) { +#if RLC_PLAN_IMPL + return rlc_plan_compute_vector(plan, in, out); +#else + return rlc_plan_compute_scalar(plan, in, out); +#endif +} + +#endif /* RLC_PLAN_C */ diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_plan.h b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_plan.h new file mode 100644 index 0000000..b5c5c9d --- /dev/null +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_plan.h @@ -0,0 +1,200 @@ +// Copyright 2025 ETH Zurich and University of Bologna. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// Author: Zexin Fu + +/* Grant planning for the RLC AM downlink. + + Everything in RLC that is genuinely serial -- SN order, the cumulative poll + counters, and the segment boundary that depends on the running grant fill -- + is confined to this planning step, which touches no payload at all. It + produces a fully-determined descriptor per output PDU, including the byte + offset of that PDU inside the transport block. + + The execute step is then embarrassingly parallel: N cores take disjoint + slices of the plan and write headers plus payload into offsets that are + already decided. No shared cursor, no locks, no ordering constraint. + + Layout is struct-of-arrays: the planner's inner loops are vectorised (RVV, + see rlc_plan.c) and the execute phase reads contiguous slices, so SoA wins + on both sides. */ + +#ifndef RLC_PLAN_H +#define RLC_PLAN_H + +#include +#include "rlc_pdu.h" + +/* Pad rlc_plan_t out to a whole cache line. Default OFF so the default build + stays byte-comparable with the frozen sets the GVSoC side is running + against; turning it on mid-investigation would confound every result with + an uncontrolled change. Now default ON: pool entries are indexed by CONSUMER, + so pool[0] and pool[1] are written by different cores, and without padding + rlc_plan_t is 7180 B (7180 % 64 = 12) so adjacent entries straddle a shared + line -- a write-write ping-pong on the hottest path in the planner. Costs + 52 B per entry. */ +#ifndef RLC_PLAN_PADDED +#define RLC_PLAN_PADDED 1 +#endif + +/* Upper bound on PDUs produced from one grant. A grant that would yield more + is truncated (the remainder stays queued for the next grant), so this is a + memory/latency knob, not a correctness limit. */ +#ifndef RLC_MAX_PDUS_PER_GRANT +#define RLC_MAX_PDUS_PER_GRANT 128 +#endif + +/* Which planner rlc_plan_compute() dispatches to: + 0 = the scalar reference (rlc_plan_compute_scalar) + 1 = the scan planner (rlc_plan_compute_vector) [default] */ +#ifndef RLC_PLAN_IMPL +#define RLC_PLAN_IMPL 1 +#endif + +/* Which of the scan planner's primitives use RVV, as a bitmask. Each + primitive has an RVV form and a plain-C twin with identical semantics, so + this bisects a vector-execution problem down to a single primitive without + needing a PC trace. 0 = every primitive in plain C (also what the host + build uses, since it cannot assemble RVV at all). */ +#define RLC_VEC_BIT_MAPS 1u /* iota_add, sub, subx, addx, fill */ +#define RLC_VEC_BIT_SCAN 2u /* prefix_sum -- Hillis-Steele log-scan */ +#define RLC_VEC_BIT_SEARCH 4u /* first_gt -- masked merge + vredminu.vs */ + +/* Default is MAPS|SCAN, deliberately NOT SEARCH. + + Spatz decodes the vector integer compares and vmerge but does not implement + either in its datapath: VMSGTU appears in spatz_decoder.sv (mapped to + spatz_req.op = VMSGTU) and in the op enum, and VMERGE appears in the enum + only -- neither is handled in spatz_simd_lane.sv, spatz_ipu.sv or + spatz_vfu.sv, whose integer ops are VADD, VSUB, VAND, VOR, VXOR, VMIN(U), + VMAX(U), the VMUL, VDIV and VREM families, VSLL, VSRL, VSRA, VMACC, + VMADD, VADC, VSBC, VMADC and VMSBC. + + That makes the first-crossing search unusable on this hardware, and in a + nastier way than an illegal instruction: the RTL *decodes* it, so there is + no trap -- it would simply produce a wrong mask silently. Every other + primitive maps onto an op that is implemented (the vmv forms decode to + VSLIDEUP, vmv.x.s to VADD, vredminu.vs to VMINU with the reduction FSM), so + only the search is affected. It stays on its C twin, which costs little: + the searches are short and the prefix sum is where the work is. + + Set to 7 to re-enable it on hardware that implements the compares. */ +#ifndef RLC_PLAN_VECTOR +#define RLC_PLAN_VECTOR (RLC_VEC_BIT_MAPS | RLC_VEC_BIT_SCAN) +#endif + +#define RLC_VEC_MAPS (RLC_PLAN_VECTOR & RLC_VEC_BIT_MAPS) +#define RLC_VEC_SCAN (RLC_PLAN_VECTOR & RLC_VEC_BIT_SCAN) +#define RLC_VEC_SEARCH (RLC_PLAN_VECTOR & RLC_VEC_BIT_SEARCH) + +/* Run both planners on every grant and compare, reporting any divergence. + Off by default -- it doubles the planning cost. */ +#ifndef RLC_PLAN_VERIFY +#define RLC_PLAN_VERIFY 0 +#endif + +/* All fields are u32 even where a u16 would do: keeping one element width + lets the whole planner run at e32 without SEW changes or widening ops. */ +typedef struct { + /* --- filled by the gather step (serial pointer chase over the queue) --- */ + void *sdu_data[RLC_MAX_PDUS_PER_GRANT]; /* payload base of the source SDU */ + void *sdu_node[RLC_MAX_PDUS_PER_GRANT]; /* owning list Node */ + uint32_t sdu_len [RLC_MAX_PDUS_PER_GRANT]; /* full length of that SDU */ + + /* --- computed by rlc_plan_compute() ----------------------------------- */ + uint32_t sn [RLC_MAX_PDUS_PER_GRANT]; /* RLC sequence number */ + uint32_t tb_off [RLC_MAX_PDUS_PER_GRANT]; /* byte offset of hdr inside TB */ + uint32_t seg_len [RLC_MAX_PDUS_PER_GRANT]; /* payload bytes in this PDU */ + uint32_t so [RLC_MAX_PDUS_PER_GRANT]; /* segment offset into the SDU */ + uint32_t si [RLC_MAX_PDUS_PER_GRANT]; /* RLC_SI_* */ + uint32_t poll [RLC_MAX_PDUS_PER_GRANT]; /* P bit */ + uint32_t hdr_len [RLC_MAX_PDUS_PER_GRANT]; /* 3 or 5 (18-bit SN) */ + uint32_t last_seg[RLC_MAX_PDUS_PER_GRANT]; /* 1 = SDU fully sent by this PDU */ + + /* --- planner scratch, held per-plan so concurrent planners never share -- */ + uint32_t pdu_len[RLC_MAX_PDUS_PER_GRANT]; /* hdr + payload of each PDU */ + uint32_t cum [RLC_MAX_PDUS_PER_GRANT]; /* inclusive scan of pdu_len */ + uint32_t bcum [RLC_MAX_PDUS_PER_GRANT]; /* inclusive scan of seg_len */ + + uint32_t n_avail; /* SDUs gathered */ + uint32_t n; /* PDUs planned (<= n_avail) */ + uint32_t tb_used; /* bytes of the grant consumed */ +} +#if RLC_PLAN_PADDED +/* Pad to a whole cache line. + + Without this rlc_plan_t is 7180 B on rv32 -- 7180 % 64 = 12 -- so adjacent + entries of rlc_am_plan_pool[] straddle a shared line. Pool entries are + indexed by CONSUMER, so pool[0] and pool[1] are written by different cores, + and the planner writes essentially the whole buffer per grant (three prefix + sums plus every SoA field). That puts two cores in a write-write ping-pong + on the boundary line on the hottest path in the planner. + + 64 rather than CACHE_LINE_SIZE: this header is also compiled by the host + unit test, which does not include rlc.h. */ +__attribute__((aligned(64))) +#endif +rlc_plan_t; + +/* Inputs to the planner. Passing these explicitly rather than an rlc_context_t + keeps the arithmetic decoupled from the entity/list types, so the planner + can be exercised standalone. */ +typedef struct { + uint32_t grant_bytes; /* size of this grant / transport block */ + uint32_t sn_base; /* ctx->vtNext */ + uint32_t so_first; /* bytes of plan->sdu[0] already transmitted */ + uint32_t poll_pdu; /* ctx->pollPdu (pollPDU, ยง5.3.3.2) */ + uint32_t poll_byte; /* ctx->pollByte (pollByte, ยง5.3.3.2) */ + uint32_t pdu_without_poll; /* running PDU_WITHOUT_POLL */ + uint32_t byte_without_poll; /* running BYTE_WITHOUT_POLL */ + uint32_t queue_drained; /* 1 if the gather emptied the to-send queue */ +} rlc_plan_in_t; + +/* Entity state the planner advances. The caller writes these back to the + entity after the plan is committed. */ +typedef struct { + uint32_t sn_next; /* new ctx->vtNext */ + uint32_t pdu_without_poll; + uint32_t byte_without_poll; + uint32_t so_next; /* bytes of the trailing SDU already sent; + 0 when no SDU is left partially transmitted */ + uint32_t partial; /* 1 if the last planned PDU is a segment */ +} rlc_plan_out_t; + +/* Turn n_avail gathered SDUs into a PDU plan that fits grant_bytes. + Returns the number of PDUs planned (also left in plan->n). */ +uint32_t rlc_plan_compute(rlc_plan_t *plan, const rlc_plan_in_t *in, + rlc_plan_out_t *out); + +/* Scalar reference implementation -- the specification of the above. Always + built so RLC_PLAN_VERIFY can diff the two. */ +uint32_t rlc_plan_compute_scalar(rlc_plan_t *plan, const rlc_plan_in_t *in, + rlc_plan_out_t *out); + +/* The scan-based planner -- prefix sums and threshold searches, vectorised + when RLC_PLAN_VECTOR. This is what rlc_plan_compute() dispatches to. */ +uint32_t rlc_plan_compute_vector(rlc_plan_t *plan, const rlc_plan_in_t *in, + rlc_plan_out_t *out); + +/* Run both planners on the same input and compare every output field. + `ref` is caller-supplied scratch (no hidden statics, so concurrent planners + stay independent). Returns the number of mismatching fields; the plan left + in `plan` is the vector one. Only built when RLC_PLAN_VERIFY is set. */ +uint32_t rlc_plan_compute_checked(rlc_plan_t *plan, rlc_plan_t *ref, + const rlc_plan_in_t *in, rlc_plan_out_t *out, + uint32_t *nbad); + +#endif /* RLC_PLAN_H */ diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_ul.c b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_ul.c new file mode 100644 index 0000000..c4071a1 --- /dev/null +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_ul.c @@ -0,0 +1,225 @@ +// Copyright 2025 ETH Zurich and University of Bologna. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// Author: Zexin Fu + +/* RLC AM uplink. See rlc_ul.h for the phase structure and why the scan is + the serial fraction. Written so it compiles standalone on the host, which + is what test/test_rlc_ul.c exercises. */ + +#ifndef RLC_UL_C +#define RLC_UL_C + +#include "rlc_ul.h" + +/* Payload reads land here so they cannot be optimised away. Written once per + reassembled range rather than per byte, so the sharing is negligible and the + benign race between cores costs nothing -- it exists only to make the loads + observable to the compiler. */ +volatile uint32_t rlc_ul_payload_sink; + +#ifndef RLC_UL_SLOT +#define RLC_UL_SLOT(sn) ((sn) & (RLC_UL_WINDOW - 1u)) +#endif + +void rlc_ul_entity_init(rlc_ul_entity_t *e) { + e->rx_next = 0u; + e->rx_next_highest = 0u; + for (uint32_t i = 0u; i < RLC_UL_WINDOW; i++) { + e->recv[i] = 0u; + e->total[i] = 0u; + e->seen[i] = 0u; + e->complete[i] = 0u; + } + e->delivered = 0u; + e->delivered_bytes = 0u; + e->reassembled = 0u; + e->dup = 0u; + e->out_of_window = 0u; + e->status_due = 0u; +} + +/* ------------------------------------------------------------------------ */ +/* Scan -- the serial phase */ +/* ------------------------------------------------------------------------ */ + +uint32_t rlc_ul_scan(rlc_ul_scan_t *s, const uint8_t *tb, uint32_t tb_len) { + uint32_t off = 0u; + s->n = 0u; + s->bytes = 0u; + s->truncated = 0u; + s->overflow = 0u; + s->polls = 0u; + s->max_sn = 0u; + s->have_sn = 0u; + + while (off + RLC_UL_MAC_HDR <= tb_len) { + /* MAC subheader: total length of the RLC PDU that follows. */ + const uint32_t plen = + ((uint32_t)tb[off] << 8) | (uint32_t)tb[off + 1u]; + off += RLC_UL_MAC_HDR; + + if (plen == 0u) break; /* padding / end of the block */ + if (off + plen > tb_len) { s->truncated = 1u; break; } + if (plen < RLC_AMD_HDR_MIN) { s->truncated = 1u; break; } + + /* The header must be parsed to know its own length: SO is present only + for LAST/MIDDLE, and SI lives inside the first byte. This is what + forces the walk to be sequential. */ + rlc_amd_hdr_t h; + rlc_amd_hdr_read(tb + off, &h); + if (h.hdr_len > plen) { s->truncated = 1u; break; } + + if (s->n >= RLC_UL_MAX_PDUS) { s->overflow = 1u; break; } + + rlc_ul_pdu_t *p = &s->pdu[s->n]; + p->payload = tb + off + h.hdr_len; + p->sn = h.sn; + p->so = h.so; + p->seg_len = plen - h.hdr_len; + p->si = (uint8_t)h.si; + p->poll = (uint8_t)h.poll; + p->hdr_len = (uint8_t)h.hdr_len; + p->_pad = 0u; + + s->bytes += p->seg_len; + s->polls += p->poll; + /* Highest SN in this TB, kept here because the scan already walks every + PDU in order -- the parallel phase must not maintain it (see + rlc_ul_note_highest). */ + if (!s->have_sn || ((p->sn - s->max_sn) & RLC_SN_MASK) < RLC_UL_WINDOW) { + s->max_sn = p->sn; + s->have_sn = 1u; + } + s->n++; + off += plen; + } + return s->n; +} + +/* ------------------------------------------------------------------------ */ +/* Reassemble -- the parallel phase */ +/* ------------------------------------------------------------------------ */ + +/* Fold [lo,hi) into the entity. + + Concurrency: two cores running different slices can legitimately hold + segments of the SAME SDU -- a middle and a last segment can both appear in + one transport block -- so `recv` is accumulated atomically. `total` is a + plain store because exactly one PDU per SDU carries SI FULL or LAST and so + there is exactly one writer, and it writes the same value either way. + + Completion is deliberately NOT decided here. Deciding "recv == total" in + this phase races: one core can add the final bytes while another is still + storing `total`, and neither observation sees the SDU as complete. It is + computed in rlc_ul_deliver(), which is serial and runs after a barrier, so + the check sees a settled state. That keeps this phase free of any + read-modify-write on shared control state. */ +void rlc_ul_reassemble_range(rlc_ul_entity_t *e, const rlc_ul_scan_t *s, + uint32_t lo, uint32_t hi) { + if (hi > s->n) hi = s->n; + for (uint32_t i = lo; i < hi; i++) { + const rlc_ul_pdu_t *p = &s->pdu[i]; + + /* Reception window: [rx_next, rx_next + RLC_UL_WINDOW). */ + const uint32_t ahead = (p->sn - e->rx_next) & RLC_SN_MASK; + if (ahead >= RLC_UL_WINDOW) { + __atomic_fetch_add(&e->out_of_window, 1u, __ATOMIC_RELAXED); + continue; + } + + const uint32_t slot = RLC_UL_SLOT(p->sn); + if (e->complete[slot]) { + __atomic_fetch_add(&e->dup, 1u, __ATOMIC_RELAXED); + continue; + } + + e->seen[slot] = 1u; + + /* A FULL or LAST segment is the one that reveals the SDU's total length: + its offset plus its own payload is the whole SDU. */ + if (p->si == RLC_SI_FULL || p->si == RLC_SI_LAST) { + e->total[slot] = p->so + p->seg_len; + } + +#if RLC_UL_EXEC == RLC_UL_EXEC_COPY + /* Move the bytes so the memory system sees a receiver's traffic. There is + no per-SDU landing buffer here: the accounting is what reassembly needs, + and a real receiver would DMA payload elsewhere. Reading it is enough to + generate the loads; the sum defeats dead-code elimination. */ + { + uint32_t acc = 0u; + for (uint32_t b = 0u; b < p->seg_len; b++) acc += p->payload[b]; + rlc_ul_payload_sink += acc; + } +#endif + + __atomic_fetch_add(&e->recv[slot], p->seg_len, __ATOMIC_RELAXED); + __atomic_fetch_add(&e->reassembled, 1u, __ATOMIC_RELAXED); + + if (p->poll) e->status_due = 1u; + } +} + +/* ------------------------------------------------------------------------ */ +/* Deliver -- serial, in order */ +/* ------------------------------------------------------------------------ */ + +/* RX_Next_Highest = highest received SN + 1 (ยง5.2.2.2). Serial by design: the + parallel phase used to do this as a read-modify-write on shared state, which + loses updates when two cores read the same old value. No decision depends on + it, so it moves here rather than becoming an atomic. */ +void rlc_ul_note_highest(rlc_ul_entity_t *e, const rlc_ul_scan_t *s) { + if (!s->have_sn) return; + const uint32_t nh = (s->max_sn + 1u) & RLC_SN_MASK; + if (((nh - e->rx_next_highest) & RLC_SN_MASK) < RLC_UL_WINDOW) + e->rx_next_highest = nh; +} + +uint32_t rlc_ul_deliver(rlc_ul_entity_t *e) { + uint32_t n = 0u; + while (1) { + const uint32_t slot = RLC_UL_SLOT(e->rx_next); + if (!e->seen[slot]) break; + const uint32_t tot = e->total[slot]; + if (tot == 0u || e->recv[slot] < tot) break; /* still has holes */ + + e->complete[slot] = 1u; + e->delivered++; + e->delivered_bytes += tot; + n++; + + /* Retire the slot before rx_next passes it, so the window can wrap. */ + e->seen[slot] = 0u; + e->complete[slot] = 0u; + e->recv[slot] = 0u; + e->total[slot] = 0u; + e->rx_next = (e->rx_next + 1u) & RLC_SN_MASK; + } + return n; +} + +/* ------------------------------------------------------------------------ */ +/* STATUS */ +/* ------------------------------------------------------------------------ */ + +/* ACK_SN is the first SN not yet received in order, i.e. rx_next. Under the + ACK-only assumption there are no NACK records, so E1 is 0. */ +uint32_t rlc_ul_build_status(const rlc_ul_entity_t *e, uint8_t *buf) { + return rlc_status_hdr_write(buf, e->rx_next, 0u); +} + +#endif /* RLC_UL_C */ diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_ul.h b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_ul.h new file mode 100644 index 0000000..76496dc --- /dev/null +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_ul.h @@ -0,0 +1,189 @@ +// Copyright 2025 ETH Zurich and University of Bologna. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// Author: Zexin Fu + +/* RLC AM uplink -- receive, reassemble, deliver (TS 38.322 ยง5.2.2, ยง5.3.2). + + Structurally the mirror of the downlink, and for the same reason: the part + that is unavoidably serial is isolated so the rest can run in parallel. + + DL: gather (serial pointer chase) -> plan (serial arithmetic) -> execute (parallel) + UL: scan (serial header walk) -> reassemble (parallel) -> deliver (serial, in-order) + + **The UL scan is serial for a structural reason, not an implementation one.** + An AMD PDU header is 3 or 5 bytes depending on whether SO is present, and SO + presence depends on SI, which is *inside* the header. So PDU i+1's offset + cannot be computed without parsing PDU i. That is the UL's Amdahl fraction, + and it is the quantity worth measuring -- the same role the gather plays on + the downlink. + + MAC framing: each PDU is preceded by a 2-byte big-endian length giving + header+payload bytes, modelling the MAC subheader that carries L. Without + it the RLC layer cannot find PDU boundaries at all -- an AMD PDU has no + length field of its own. Assuming MAC has already demultiplexed the TB to a + single UE is the simplification agreed with the GVSoC-side design: the + TB<->UE map is 1:1 and known from the protocol, so spending UL budget + rediscovering it would model the wrong thing. + + Payload policy follows the same argument as the DL scatter-gather back-end: + RLC does not need to touch payload bytes to reassemble, it needs to account + for them. RLC_UL_EXEC selects whether we move the bytes (so the memory + system sees representative traffic) or only account (what a real receiver + with a DMA would do). */ + +#ifndef RLC_UL_H +#define RLC_UL_H + +#include +#include "rlc_pdu.h" + +/* Uplink on/off. Independent of RLC_TB_MODE: the UL path can be exercised + without the DL grant machinery. */ +#ifndef RLC_UL_MODE +#define RLC_UL_MODE 0 +#endif + +/* COPY moves each segment into the reassembly buffer, so the memory system + sees the traffic a real receiver's DMA would generate. COUNT only accounts + for the bytes -- headers are still parsed, payload is never touched, which + is what a receiver that hands payload to a DMA actually does. */ +#define RLC_UL_EXEC_COPY 0 +#define RLC_UL_EXEC_COUNT 1 +#ifndef RLC_UL_EXEC +#define RLC_UL_EXEC RLC_UL_EXEC_COPY +#endif + +/* Upper bound on PDUs scanned from one transport block. */ +#ifndef RLC_UL_MAX_PDUS +#define RLC_UL_MAX_PDUS 128 +#endif + +/* Reassembly window, in SDUs. Must be a power of two -- SN maps to a slot by + masking, so a non-power-of-two would need a modulo in the hot path. */ +#ifndef RLC_UL_WINDOW +#define RLC_UL_WINDOW 64 +#endif +#if (RLC_UL_WINDOW & (RLC_UL_WINDOW - 1)) != 0 +#error "RLC_UL_WINDOW must be a power of two" +#endif + +/* MAC subheader: 2-byte big-endian length of the RLC PDU that follows. */ +#define RLC_UL_MAC_HDR 2u + +/* One scanned PDU. Struct-of-arrays is not used here (unlike the DL plan) + because the reassemble phase reads whole records rather than sweeping one + field, and there is no vectorised arithmetic over them. */ +typedef struct { + const uint8_t *payload; /* into the transport block, not copied */ + uint32_t sn; + uint32_t so; /* segment offset within the SDU */ + uint32_t seg_len; /* payload bytes carried */ + uint8_t si; /* RLC_SI_* */ + uint8_t poll; /* P bit -- a STATUS report is due */ + uint8_t hdr_len; /* 3 or 5 */ + uint8_t _pad; +} rlc_ul_pdu_t; + +typedef struct { + rlc_ul_pdu_t pdu[RLC_UL_MAX_PDUS]; + uint32_t n; /* PDUs scanned */ + uint32_t bytes; /* payload bytes across them */ + uint32_t truncated; /* TB ended mid-PDU -- malformed */ + uint32_t overflow; /* more PDUs in the TB than RLC_UL_MAX_PDUS */ + uint32_t polls; /* PDUs with P set */ + uint32_t max_sn; /* highest SN in this TB, for RX_Next_Highest */ + uint32_t have_sn; /* 0 when the TB carried no PDU at all */ +} rlc_ul_scan_t; + +/* Cache line, for separating state written in the parallel phase from state + written in the serial phases. Matches CACHE_LINE_SIZE on the target; the + host build only needs it to be a plausible line so the layout is the same + shape being tested. */ +#ifndef RLC_UL_LINE +#define RLC_UL_LINE 64 +#endif + +/* Per-entity receive state (TS 38.322 ยง5.2.2 state variables). + + **Every field written during the parallel reassemble phase is word-sized and + word-aligned.** An earlier version used `uint8_t seen[64]` / `complete[64]`, + which put the whole window in ONE cache line and had three consumers issuing + concurrent *byte* stores into it. Sub-word stores from different cores into + the same line are exactly the case a partial-strobe path can drop, so a lost + `seen[slot]` silently costs an SDU -- and it costs more of them the more + cores are running, which is indistinguishable from a coherence bug unless + you know to look here. Word stores to distinct words have no such exposure. + + The three regions are line-separated because they have different writers: + serial-phase state is written only by the delivering core, the parallel + counters are hit by every core with an atomic RMW every segment, and mixing + them means each RMW invalidates the line holding the serial state. */ +typedef struct { + /* --- serial phase only: written by the delivering core --- */ + uint32_t rx_next; /* SN of the oldest SDU still awaited */ + uint32_t rx_next_highest; /* highest SN received + 1 */ + uint32_t delivered; /* SDUs delivered in order */ + uint32_t delivered_bytes; + uint8_t _pad0[RLC_UL_LINE - 4u * sizeof(uint32_t)]; + + /* --- parallel phase: accumulated by every core --- */ + uint32_t reassembled; /* segments folded in */ + uint32_t dup; /* segment for an already-complete SN */ + uint32_t out_of_window; + uint32_t status_due; /* poll seen since the last STATUS */ + uint8_t _pad1[RLC_UL_LINE - 4u * sizeof(uint32_t)]; + + /* --- reassembly window, indexed by SN & (RLC_UL_WINDOW-1) --- */ + uint32_t recv[RLC_UL_WINDOW]; /* payload bytes accumulated for that SN */ + uint32_t total[RLC_UL_WINDOW]; /* full SDU length, known once the last + segment arrives; 0 until then */ + uint32_t seen[RLC_UL_WINDOW]; /* slot in use for the current window */ + uint32_t complete[RLC_UL_WINDOW]; +} rlc_ul_entity_t; + +/* Walk a transport block and describe every PDU in it. Touches only the MAC + length fields and the RLC headers -- never payload. Returns the PDU count + (also left in s->n). */ +uint32_t rlc_ul_scan(rlc_ul_scan_t *s, const uint8_t *tb, uint32_t tb_len); + +/* Fold scanned PDUs [lo,hi) into the entity's reassembly state. Slices are + disjoint and different cores may run different slices concurrently, so long + as no two slices carry the same SN -- see rlc_ul_reassemble_range()'s + comment on why the scan guarantees that in practice and what to do when it + does not. */ +void rlc_ul_reassemble_range(rlc_ul_entity_t *e, const rlc_ul_scan_t *s, + uint32_t lo, uint32_t hi); + +/* Fold a scanned TB's highest SN into RX_Next_Highest (ยง5.2.2.2). Serial: the + parallel phase used to do this with a read-modify-write on shared state, + which is a genuine lost-update race -- two cores can both read the old value + and both store, dropping the higher. It is bookkeeping no decision depends + on, so the fix is to take it out of the parallel phase rather than to make + it atomic. */ +void rlc_ul_note_highest(rlc_ul_entity_t *e, const rlc_ul_scan_t *s); + +/* Deliver every in-order complete SDU starting at rx_next, advancing it. + Returns how many were delivered. */ +uint32_t rlc_ul_deliver(rlc_ul_entity_t *e); + +/* Build a STATUS PDU acknowledging everything below rx_next. Returns bytes + written. */ +uint32_t rlc_ul_build_status(const rlc_ul_entity_t *e, uint8_t *buf); + +void rlc_ul_entity_init(rlc_ul_entity_t *e); + +#endif /* RLC_UL_H */ diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_ul_drv.c b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_ul_drv.c new file mode 100644 index 0000000..8cb3f71 --- /dev/null +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_ul_drv.c @@ -0,0 +1,336 @@ +// Copyright 2025 ETH Zurich and University of Bologna. +// +// SPDX-License-Identifier: Apache-2.0 +// +// SPDX-License-Identifier: Apache-2.0 +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// Author: Zexin Fu + +/* Target-side driver for the RLC AM uplink. + + Kept separate from rlc_ul.c so that file stays free of snRuntime and can be + compiled and exercised on the host (test/test_rlc_ul.c does exactly that). + Everything here is harness: it manufactures the uplink transport blocks a + MAC would hand up, then drives the real scan / reassemble / deliver path. + + Slot structure mirrors the downlink TTI, and for the same reason -- a + helper with nothing to do must block, not poll: + + [ one core builds a TB and SCANS it ] serial by construction + --------- partial barrier --------- + [ every consumer REASSEMBLES a slice ] parallel + --------- partial barrier --------- + [ one core DELIVERS in order, emits STATUS ] serial by definition + --------- partial barrier --------- + + The scan is the uplink's Amdahl fraction: an AMD header is 3 or 5 bytes + depending on SI, so PDU i+1's offset needs PDU i parsed. Measuring how fast + one core can scan against how many cores can reassemble is the uplink + analogue of the downlink's gather-versus-execute question. */ + +#ifndef RLC_UL_DRV_C +#define RLC_UL_DRV_C + +#include "rlc_copy.h" +#include "rlc_ul.h" +#include "rlc_ul_drv.h" +#include "rlc_ul.c" + +/* Uplink transport blocks land here. Same arena reasoning as the downlink TB: + above the l1d_addr boundary, so tile-private -- which is sound only while + the consumers sharing it are co-tiled. rlc_am_init()'s cross-tile guard + covers the same constraint and fires for both directions. */ +#ifndef RLC_UL_TB_BASE +#define RLC_UL_TB_BASE 0xB0800000u +#endif +#ifndef RLC_UL_TB_BYTES +#define RLC_UL_TB_BYTES 8192u +#endif + +/* How many uplink SDUs the harness feeds in, per entity. */ +#ifndef RLC_UL_SDUS +#define RLC_UL_SDUS 64u +#endif + +static rlc_ul_entity_t rlc_ul_ent[NUM_USERS] + __attribute__((aligned(CACHE_LINE_SIZE))) __attribute__((section(".data"))); +static rlc_ul_scan_t rlc_ul_scan_buf __attribute__((aligned(CACHE_LINE_SIZE))) + __attribute__((section(".data"))); +static uint8_t rlc_ul_status_buf[RLC_STATUS_HDR_LEN + 4u] + __attribute__((aligned(4))) __attribute__((section(".data"))); + +/* Harness transmit cursor, shared: which SDU and which byte within it. */ +static uint32_t rlc_ul_cur_sdu; +static uint32_t rlc_ul_cur_so; +static uint32_t rlc_ul_cur_sn; +static uint32_t rlc_ul_slots; +static uint32_t rlc_ul_tb_bytes; +static uint32_t rlc_ul_status_pdus; + +/* Set by consumer 0 once the stream is exhausted; every consumer reads it + after a barrier, so the loop exits on the same slot everywhere. */ +static _Atomic uint32_t rlc_ul_stop __attribute__((aligned(CACHE_LINE_SIZE))) + __attribute__((section(".data"))); + +/* Phase barrier. + + snrt_cluster_partial_barrier() is documented as "a plain volatile store": it + is a synchronisation event, not a memory fence. Consumer 0 writes the scan + buffer in phase 1 and the other consumers read it in phase 2, so without an + explicit fence on both sides the readers may see a partially published + buffer even though the barrier did exactly what it promised. Fence before, + to publish this phase's writes; fence after, to see everyone else's. */ +static inline void rlc_ul_barrier(uint32_t mask) { + asm volatile("fence" ::: "memory"); + snrt_cluster_partial_barrier(mask); + asm volatile("fence" ::: "memory"); +} + +/* Per-phase cycle accounting. build/scan/deliver run on consumer 0 only; + reassemble is per-core, because the point of the measurement is how the + parallel phase compares against the serial scan it cannot overlap with. + Padded to a cache line so the per-core accumulators do not false-share. */ +typedef struct { + uint32_t cyc; + uint8_t pad[CACHE_LINE_SIZE - sizeof(uint32_t)]; +} rlc_ul_cyc_t; +static rlc_ul_cyc_t rlc_ul_cyc_reasm[RLC_ACTUAL_CONSUMERS] + __attribute__((aligned(CACHE_LINE_SIZE))) __attribute__((section(".data"))); +static uint32_t rlc_ul_cyc_build, rlc_ul_cyc_scan, rlc_ul_cyc_deliver; + +/* Set once the cluster tile-participation mask has been programmed. The phase + barriers are meaningless until it has been, and a barrier that returns + immediately does not fail loudly -- it silently lets the phases overlap. So + the consumer checks this and says so rather than producing quiet garbage. + + **Atomic, in .data, and fenced -- not a plain static.** The first version of + this flag was a plain `static uint32_t`, which lands in .sbss and is written + by core 0 in rlc_init() then read by the consumers after + snrt_cluster_hw_barrier(). Nothing in that sequence makes the store visible: + the hardware barrier is a synchronisation event, not a memory fence, and a + non-atomic store carries no ordering of its own. The store executed and the + load executed and they still disagreed -- consumers read 0 and every build + tripped its own guard. Release/acquire plus an explicit fence is what + actually publishes it. The same reasoning applies to any startup state one + core computes for the others to read. */ +static _Atomic uint32_t rlc_ul_barrier_armed + __attribute__((aligned(CACHE_LINE_SIZE))) __attribute__((section(".data"))); +static _Atomic uint32_t rlc_ul_tile_mask __attribute__((section(".data"))); + +void rlc_ul_init(void) { + /* Step 1 of the partial-barrier API: programme which tiles take part. Must + run from exactly one core BEFORE main.c's startup snrt_cluster_hw_barrier(), + which is the resync point the API requires -- the cluster barrier FSM + samples this mask live when the first participating tile arrives. + rlc_am_init() does the same thing for the downlink; the uplink needs it + for exactly the same reason and originally did not have it. */ + { + const uint32_t cpt = snrt_cluster_core_per_tile(); + uint32_t tm_lo = 0u, tm_hi = 0u; + for (uint32_t i = 0u; i < RLC_ACTUAL_CONSUMERS; i++) { + const uint32_t t = (uint32_t)consumer_core_ids[i] / cpt; + if (t < 32u) tm_lo |= 1u << t; else tm_hi |= 1u << (t - 32u); + } + snrt_barrier_set_tile_mask(tm_lo, tm_hi); + atomic_store_explicit(&rlc_ul_tile_mask, tm_lo, memory_order_relaxed); + /* Release, then fence: the consumers read this without holding any lock, + and main.c's snrt_cluster_hw_barrier() right after rlc_init() does not + order memory on its own. */ + atomic_store_explicit(&rlc_ul_barrier_armed, 1u, memory_order_release); + asm volatile("fence" ::: "memory"); + } + atomic_store_explicit(&rlc_ul_stop, 0u, memory_order_relaxed); + for (uint32_t u = 0u; u < NUM_USERS; u++) rlc_ul_entity_init(&rlc_ul_ent[u]); + rlc_ul_cur_sdu = 0u; + rlc_ul_cur_so = 0u; + rlc_ul_cur_sn = 0u; + rlc_ul_slots = 0u; + rlc_ul_tb_bytes = 0u; + rlc_ul_status_pdus = 0u; + rlc_ul_cyc_build = 0u; + rlc_ul_cyc_scan = 0u; + rlc_ul_cyc_deliver = 0u; + for (uint32_t i = 0u; i < RLC_ACTUAL_CONSUMERS; i++) rlc_ul_cyc_reasm[i].cyc = 0u; +} + +/* Every uplink SDU is one PDU_SIZE payload taken from the PDCP source region, + so the harness generates realistic traffic without needing its own dataset. + Returns TB length in bytes, 0 when the stream is exhausted. */ +static uint32_t rlc_ul_build_tb(uint8_t *tb, uint32_t cap) { + uint32_t len = 0u; + while (rlc_ul_cur_sdu < RLC_UL_SDUS) { + const uint32_t sdu_len = PDU_SIZE; + const uint8_t *src = (const uint8_t *)(uintptr_t)pdcp_pkgs[rlc_ul_cur_sdu % + NUM_PKGS].src_addr; + const uint32_t remaining = sdu_len - rlc_ul_cur_so; + const uint32_t si_full = (rlc_ul_cur_so == 0u) ? RLC_SI_FULL : RLC_SI_LAST; + const uint32_t hdr = rlc_amd_hdr_len(si_full); + + if (len + RLC_UL_MAC_HDR + hdr + 1u > cap) break; + const uint32_t room = cap - len - RLC_UL_MAC_HDR - hdr; + + uint32_t si, seg; + if (remaining <= room) { seg = remaining; si = si_full; } + else { seg = room; si = (rlc_ul_cur_so == 0u) ? RLC_SI_FIRST : RLC_SI_MIDDLE; } + + const uint32_t hl = rlc_amd_hdr_len(si); + uint8_t *p = tb + len; + p[0] = (uint8_t)(((hl + seg) >> 8) & 0xFFu); + p[1] = (uint8_t)((hl + seg) & 0xFFu); + /* Poll on the last segment of every 4th SDU, so the STATUS path runs. */ + const uint32_t poll = (si == RLC_SI_FULL || si == RLC_SI_LAST) + ? ((rlc_ul_cur_sdu % 4u) == 3u) + : 0u; + rlc_amd_hdr_write(p + RLC_UL_MAC_HDR, rlc_ul_cur_sn, si, poll, + rlc_ul_cur_so); + rlc_memcpy8(p + RLC_UL_MAC_HDR + hl, src + rlc_ul_cur_so, seg); + len += RLC_UL_MAC_HDR + hl + seg; + + if (si == RLC_SI_FULL || si == RLC_SI_LAST) { + /* SDU finished: only now does the SN advance. */ + rlc_ul_cur_sn = (rlc_ul_cur_sn + 1u) & RLC_SN_MASK; + rlc_ul_cur_sdu++; + rlc_ul_cur_so = 0u; + } else { + rlc_ul_cur_so += seg; + break; /* TB full by construction */ + } + } + return len; +} + +static int rlc_ul_done(void) { return rlc_ul_cur_sdu >= RLC_UL_SDUS; } + +/* One uplink slot, run by every consumer. Entity 0 only: the harness feeds a + single stream, which is what the scan-versus-reassemble split is measured + on. Multi-entity uplink reuses these phases under the ownership map the + downlink already has. */ +static void rlc_ul_slot(uint32_t me, uint32_t bar_mask) { + uint8_t *tb = (uint8_t *)(uintptr_t)RLC_UL_TB_BASE; + + /* --- phase 1: build + scan (serial by construction) --- */ + if (me == 0u) { + const uint32_t t0 = benchmark_get_cycle(); + const uint32_t len = rlc_ul_build_tb(tb, RLC_UL_TB_BYTES); + const uint32_t t1 = benchmark_get_cycle(); + rlc_ul_tb_bytes += len; + if (len) rlc_ul_scan(&rlc_ul_scan_buf, tb, len); + else rlc_ul_scan_buf.n = 0u; + const uint32_t t2 = benchmark_get_cycle(); + rlc_ul_cyc_build += t1 - t0; + rlc_ul_cyc_scan += t2 - t1; + rlc_ul_slots++; + } + rlc_ul_barrier(bar_mask); + + /* --- phase 2: reassemble (parallel, disjoint slices) --- */ + { + const uint32_t t0 = benchmark_get_cycle(); + const uint32_t n = rlc_ul_scan_buf.n; + const uint32_t ncons = RLC_ACTUAL_CONSUMERS; + const uint32_t step = (n + ncons - 1u) / (ncons ? ncons : 1u); + const uint32_t lo = me * step; + if (step && lo < n) { + uint32_t hi = lo + step; + if (hi > n) hi = n; + rlc_ul_reassemble_range(&rlc_ul_ent[0], &rlc_ul_scan_buf, lo, hi); + } + rlc_ul_cyc_reasm[me].cyc += benchmark_get_cycle() - t0; + } + rlc_ul_barrier(bar_mask); + + /* --- phase 3: deliver in order + STATUS (serial by definition) --- */ + if (me == 0u) { + const uint32_t t0 = benchmark_get_cycle(); + rlc_ul_note_highest(&rlc_ul_ent[0], &rlc_ul_scan_buf); + rlc_ul_deliver(&rlc_ul_ent[0]); + if (rlc_ul_ent[0].status_due) { + rlc_ul_build_status(&rlc_ul_ent[0], rlc_ul_status_buf); + rlc_ul_ent[0].status_due = 0u; + rlc_ul_status_pdus++; + } + rlc_ul_cyc_deliver += benchmark_get_cycle() - t0; + if (rlc_ul_done() && rlc_ul_scan_buf.n == 0u) + atomic_store_explicit(&rlc_ul_stop, 1u, memory_order_relaxed); + } + rlc_ul_barrier(bar_mask); +} + +static void rlc_ul_report(void) { + const rlc_ul_entity_t *e = &rlc_ul_ent[0]; + const uint32_t want = RLC_UL_SDUS * (uint32_t)PDU_SIZE; + printf_lock_acquire(&printf_lock); + printf("[UL] barrier tile_mask=0x%x local_mask=0x%x armed=%u\n", + (uint32_t)atomic_load_explicit(&rlc_ul_tile_mask, memory_order_relaxed), + snrt_cluster_partial_barrier_mask(consumer_core_ids, + RLC_ACTUAL_CONSUMERS), + (uint32_t)atomic_load_explicit(&rlc_ul_barrier_armed, + memory_order_relaxed)); + printf("[UL] slots=%u tb_bytes=%u segments=%u polls_ack=%u exec=%s\n", + rlc_ul_slots, rlc_ul_tb_bytes, e->reassembled, rlc_ul_status_pdus, + (RLC_UL_EXEC == RLC_UL_EXEC_COPY) ? "copy" : "count"); + printf("[UL] delivered=%u/%u bytes=%u/%u rx_next=%u dup=%u oow=%u\n", + e->delivered, (unsigned)RLC_UL_SDUS, e->delivered_bytes, want, + e->rx_next, e->dup, e->out_of_window); + { + uint32_t rmax = 0u, rsum = 0u; + for (uint32_t i = 0u; i < RLC_ACTUAL_CONSUMERS; i++) { + rsum += rlc_ul_cyc_reasm[i].cyc; + if (rlc_ul_cyc_reasm[i].cyc > rmax) rmax = rlc_ul_cyc_reasm[i].cyc; + } + /* The scan is the uplink's Amdahl fraction: it cannot overlap the + reassemble that consumes its output, so serial/(serial+parallel) bounds + what more cores can buy. build is harness cost, reported so it can be + subtracted rather than silently counted as protocol work. */ + printf("[UL] cyc build=%u scan=%u reasm_max=%u reasm_sum=%u deliver=%u\n", + rlc_ul_cyc_build, rlc_ul_cyc_scan, rmax, rsum, rlc_ul_cyc_deliver); + printf("[UL] serial=%u parallel=%u cons=%u\n", + rlc_ul_cyc_scan + rlc_ul_cyc_deliver, rmax, + (unsigned)RLC_ACTUAL_CONSUMERS); + } + printf("[UL] check: %s\n", + (e->delivered == RLC_UL_SDUS && e->out_of_window == 0u && + e->delivered_bytes == want) + ? "PASS" + : "FAIL"); + printf_lock_release(&printf_lock); +} + +/* Uplink consumer entry point: replaces the downlink consumer body when + RLC_UL_MODE is set. Lazily initialised by consumer 0 before the first + barrier, so rlc_init() needs no uplink hook. */ +void rlc_ul_consumer(uint32_t core_id) { + const uint32_t me = rlc_consumer_index(core_id); + const uint32_t mask = + snrt_cluster_partial_barrier_mask(consumer_core_ids, RLC_ACTUAL_CONSUMERS); + /* rlc_ul_init() ran in rlc_init(), before the startup hw barrier. If it did + not, every phase barrier below is a no-op and the phases silently overlap: + reassemble reads a scan buffer still being written, and deliver runs before + the segments it needs have been folded in. That failure mode produces + plausible-looking short delivery rather than an error, so say so. */ + if (!atomic_load_explicit(&rlc_ul_barrier_armed, memory_order_acquire)) { + if (me == 0u) { + printf_lock_acquire(&printf_lock); + printf("[UL] FATAL: tile participation mask never programmed -- the " + "phase barriers are no-ops. rlc_ul_init() must run in rlc_init().\n"); + printf_lock_release(&printf_lock); + } + return; + } + while (!atomic_load_explicit(&rlc_ul_stop, memory_order_relaxed)) + rlc_ul_slot(me, mask); + if (me == 0u) rlc_ul_report(); +} + +#endif /* RLC_UL_DRV_C */ diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_ul_drv.h b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_ul_drv.h new file mode 100644 index 0000000..ceade3e --- /dev/null +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_ul_drv.h @@ -0,0 +1,38 @@ +// Copyright 2025 ETH Zurich and University of Bologna. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// Author: Zexin Fu + +/* Target-side uplink driver entry points. Declared separately from the + implementation (rlc_ul_drv.c) because rlc_init() must call rlc_ul_init() + and is defined earlier in the same translation unit. */ + +#ifndef RLC_UL_DRV_H +#define RLC_UL_DRV_H + +#include + +/* MUST be called from exactly one core, from rlc_init(), i.e. BEFORE main.c's + startup snrt_cluster_hw_barrier(). It programs the cluster tile + participation mask, and that barrier is the resync point the partial-barrier + API requires before the mask can be relied on. Doing it later -- lazily on + entry to rlc_ul_consumer() -- leaves the phase barriers unprogrammed. */ +void rlc_ul_init(void); + +/* Uplink consumer entry point: receive/reassemble/deliver slots. */ +void rlc_ul_consumer(uint32_t core_id); + +#endif /* RLC_UL_DRV_H */ diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_12_1350_24.json b/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_12_1350_24.json new file mode 100644 index 0000000..ce9df14 --- /dev/null +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_12_1350_24.json @@ -0,0 +1,22 @@ +// Copyright 2025 ETH Zurich and University of Bologna. +// SPDX-License-Identifier: Apache-2.0 +// Author: Zexin Fu + +// Multi-entity AM case sized to complete on RTL. +// +// TC2 (48 users, 300 packets) cannot reach EOC at the ~52 cycles/s the AM path +// simulates at. Eight entities over 24 packets still exercises everything TC2 +// does that TC1 does not -- several entities per owner, the one-open-grant +// rule, and the ownership partition -- at a twentieth of the work. +{ + "active_user_number": 12, + "pkg_length": 1350, + "pdcp_header_length": 10, + "src_addr": "0xA0000000", + "src_length": 16777216, + "tgt_addr": "0xB0000000", + "tgt_length": 16777216, + "total_pkg_number": 24, + "producer_cores": [0, 1], + "consumer_cores": [2, 3] +} diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_16_1350_24.json b/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_16_1350_24.json new file mode 100644 index 0000000..bdd979d --- /dev/null +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_16_1350_24.json @@ -0,0 +1,22 @@ +// Copyright 2025 ETH Zurich and University of Bologna. +// SPDX-License-Identifier: Apache-2.0 +// Author: Zexin Fu + +// Multi-entity AM case sized to complete on RTL. +// +// TC2 (48 users, 300 packets) cannot reach EOC at the ~52 cycles/s the AM path +// simulates at. Eight entities over 24 packets still exercises everything TC2 +// does that TC1 does not -- several entities per owner, the one-open-grant +// rule, and the ownership partition -- at a twentieth of the work. +{ + "active_user_number": 16, + "pkg_length": 1350, + "pdcp_header_length": 10, + "src_addr": "0xA0000000", + "src_length": 16777216, + "tgt_addr": "0xB0000000", + "tgt_length": 16777216, + "total_pkg_number": 24, + "producer_cores": [0, 1], + "consumer_cores": [2, 3] +} diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_1_1350_100_p1c1.json b/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_1_1350_100_p1c1.json new file mode 100644 index 0000000..dddfff6 --- /dev/null +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_1_1350_100_p1c1.json @@ -0,0 +1,36 @@ +// Copyright 2025 ETH Zurich and University of Bologna. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// Author: Zexin Fu + +// TC1 with a single producer and a single consumer. +// +// Dispatch follows these lists, not the PRODUCER_CORE_NUM/CONSUMER_CORE_NUM +// build defines, so a genuine one-consumer run needs its own header rather +// than an override. Its purpose is to be the C=1 control: anything that +// reproduces here is not a concurrency bug. +{ + "active_user_number": 1, + "pkg_length": 1350, + "pdcp_header_length": 10, + "src_addr": "0xA0000000", + "src_length": 16777216, + "tgt_addr": "0xB0000000", + "tgt_length": 16777216, + "total_pkg_number": 100, + "producer_cores": [0], + "consumer_cores": [1] +} diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_1_1350_4.json b/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_1_1350_4.json new file mode 100644 index 0000000..a5cdf97 --- /dev/null +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_1_1350_4.json @@ -0,0 +1,22 @@ +// Copyright 2025 ETH Zurich and University of Bologna. +// SPDX-License-Identifier: Apache-2.0 +// Author: Zexin Fu + +// Multi-entity AM case sized to complete on RTL. +// +// TC2 (48 users, 300 packets) cannot reach EOC at the ~52 cycles/s the AM path +// simulates at. Eight entities over 24 packets still exercises everything TC2 +// does that TC1 does not -- several entities per owner, the one-open-grant +// rule, and the ownership partition -- at a twentieth of the work. +{ + "active_user_number": 1, + "pkg_length": 1350, + "pdcp_header_length": 10, + "src_addr": "0xA0000000", + "src_length": 16777216, + "tgt_addr": "0xB0000000", + "tgt_length": 16777216, + "total_pkg_number": 4, + "producer_cores": [0, 1], + "consumer_cores": [2, 3] +} diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_24_1350_24.json b/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_24_1350_24.json new file mode 100644 index 0000000..b8601ee --- /dev/null +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_24_1350_24.json @@ -0,0 +1,22 @@ +// Copyright 2025 ETH Zurich and University of Bologna. +// SPDX-License-Identifier: Apache-2.0 +// Author: Zexin Fu + +// Multi-entity AM case sized to complete on RTL. +// +// TC2 (48 users, 300 packets) cannot reach EOC at the ~52 cycles/s the AM path +// simulates at. Eight entities over 24 packets still exercises everything TC2 +// does that TC1 does not -- several entities per owner, the one-open-grant +// rule, and the ownership partition -- at a twentieth of the work. +{ + "active_user_number": 24, + "pkg_length": 1350, + "pdcp_header_length": 10, + "src_addr": "0xA0000000", + "src_length": 16777216, + "tgt_addr": "0xB0000000", + "tgt_length": 16777216, + "total_pkg_number": 24, + "producer_cores": [0, 1], + "consumer_cores": [2, 3] +} diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_256_800_300.json b/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_256_800_300.json new file mode 100644 index 0000000..59366fa --- /dev/null +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_256_800_300.json @@ -0,0 +1,10 @@ +{ + "active_user_number": 256, + "pkg_length": 800, + "pdcp_header_length": 10, + "src_addr": "0xA0000000", + "src_length": 16777216, + "tgt_addr": "0xB0000000", + "tgt_length": 16777216, + "total_pkg_number": 300 +} diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_32_1350_24.json b/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_32_1350_24.json new file mode 100644 index 0000000..08317aa --- /dev/null +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_32_1350_24.json @@ -0,0 +1,22 @@ +// Copyright 2025 ETH Zurich and University of Bologna. +// SPDX-License-Identifier: Apache-2.0 +// Author: Zexin Fu + +// Multi-entity AM case sized to complete on RTL. +// +// TC2 (48 users, 300 packets) cannot reach EOC at the ~52 cycles/s the AM path +// simulates at. Eight entities over 24 packets still exercises everything TC2 +// does that TC1 does not -- several entities per owner, the one-open-grant +// rule, and the ownership partition -- at a twentieth of the work. +{ + "active_user_number": 32, + "pkg_length": 1350, + "pdcp_header_length": 10, + "src_addr": "0xA0000000", + "src_length": 16777216, + "tgt_addr": "0xB0000000", + "tgt_length": 16777216, + "total_pkg_number": 24, + "producer_cores": [0, 1], + "consumer_cores": [2, 3] +} diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_48_1350_24.json b/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_48_1350_24.json new file mode 100644 index 0000000..50a44bd --- /dev/null +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_48_1350_24.json @@ -0,0 +1,22 @@ +// Copyright 2025 ETH Zurich and University of Bologna. +// SPDX-License-Identifier: Apache-2.0 +// Author: Zexin Fu + +// 48 entities at M8's tiny packet count: isolates entity count from workload. +// +// TC2 (48 users, 300 packets) cannot reach EOC at the ~52 cycles/s the AM path +// simulates at. Eight entities over 24 packets still exercises everything TC2 +// does that TC1 does not -- several entities per owner, the one-open-grant +// rule, and the ownership partition -- at a twentieth of the work. +{ + "active_user_number": 48, + "pkg_length": 1350, + "pdcp_header_length": 10, + "src_addr": "0xA0000000", + "src_length": 16777216, + "tgt_addr": "0xB0000000", + "tgt_length": 16777216, + "total_pkg_number": 24, + "producer_cores": [0, 1], + "consumer_cores": [2, 3] +} diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_48_1350_8.json b/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_48_1350_8.json new file mode 100644 index 0000000..424d2d7 --- /dev/null +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_48_1350_8.json @@ -0,0 +1,22 @@ +// Copyright 2025 ETH Zurich and University of Bologna. +// SPDX-License-Identifier: Apache-2.0 +// Author: Zexin Fu + +// Multi-entity AM case sized to complete on RTL. +// +// TC2 (48 users, 300 packets) cannot reach EOC at the ~52 cycles/s the AM path +// simulates at. Eight entities over 24 packets still exercises everything TC2 +// does that TC1 does not -- several entities per owner, the one-open-grant +// rule, and the ownership partition -- at a twentieth of the work. +{ + "active_user_number": 48, + "pkg_length": 1350, + "pdcp_header_length": 10, + "src_addr": "0xA0000000", + "src_length": 16777216, + "tgt_addr": "0xB0000000", + "tgt_length": 16777216, + "total_pkg_number": 8, + "producer_cores": [0, 1], + "consumer_cores": [2, 3] +} diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_8_1350_24.json b/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_8_1350_24.json new file mode 100644 index 0000000..30ee957 --- /dev/null +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_8_1350_24.json @@ -0,0 +1,22 @@ +// Copyright 2025 ETH Zurich and University of Bologna. +// SPDX-License-Identifier: Apache-2.0 +// Author: Zexin Fu + +// Multi-entity AM case sized to complete on RTL. +// +// TC2 (48 users, 300 packets) cannot reach EOC at the ~52 cycles/s the AM path +// simulates at. Eight entities over 24 packets still exercises everything TC2 +// does that TC1 does not -- several entities per owner, the one-open-grant +// rule, and the ownership partition -- at a twentieth of the work. +{ + "active_user_number": 8, + "pkg_length": 1350, + "pdcp_header_length": 10, + "src_addr": "0xA0000000", + "src_length": 16777216, + "tgt_addr": "0xB0000000", + "tgt_length": 16777216, + "total_pkg_number": 24, + "producer_cores": [0, 1], + "consumer_cores": [2, 3] +} diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_8_1350_8.json b/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_8_1350_8.json new file mode 100644 index 0000000..4ebc9b7 --- /dev/null +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_8_1350_8.json @@ -0,0 +1,22 @@ +// Copyright 2025 ETH Zurich and University of Bologna. +// SPDX-License-Identifier: Apache-2.0 +// Author: Zexin Fu + +// Multi-entity AM case sized to complete on RTL. +// +// TC2 (48 users, 300 packets) cannot reach EOC at the ~52 cycles/s the AM path +// simulates at. Eight entities over 24 packets still exercises everything TC2 +// does that TC1 does not -- several entities per owner, the one-open-grant +// rule, and the ownership partition -- at a twentieth of the work. +{ + "active_user_number": 8, + "pkg_length": 1350, + "pdcp_header_length": 10, + "src_addr": "0xA0000000", + "src_length": 16777216, + "tgt_addr": "0xB0000000", + "tgt_length": 16777216, + "total_pkg_number": 8, + "producer_cores": [0, 1], + "consumer_cores": [2, 3] +} diff --git a/software/tests/multi_producer_single_consumer_double_linked_list/test/test_rlc_plan.c b/software/tests/multi_producer_single_consumer_double_linked_list/test/test_rlc_plan.c new file mode 100644 index 0000000..a772d50 --- /dev/null +++ b/software/tests/multi_producer_single_consumer_double_linked_list/test/test_rlc_plan.c @@ -0,0 +1,231 @@ +// Copyright 2025 ETH Zurich and University of Bologna. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// Author: Zexin Fu + +/* Host-side unit test for the RLC AM grant planner. + + The scalar planner is the specification that the RVV implementation is + checked against on target (RLC_PLAN_VERIFY), so it is worth validating on + its own, away from any simulator. This drives a multi-grant stream over a + queue of SDUs and checks the structural invariants plus an independent + model of the poll counters and of SDU reassembly. + + Build and run: + gcc -DRLC_PLAN_VECTOR=0 -O2 -I../kernel test_rlc_plan.c -o /tmp/t && /tmp/t +*/ + +#include +#include +#include + +#include "../kernel/rlc_plan.c" + +#define MAX_SDUS 4096 + +static uint32_t rng_state = 12345u; +static uint32_t rnd(uint32_t lo, uint32_t hi) { /* inclusive */ + rng_state = rng_state * 1103515245u + 12345u; + return lo + (rng_state >> 8) % (hi - lo + 1u); +} + +static int failures = 0; +static long checks = 0; + +#define CHECK(cond, fmt, ...) \ + do { \ + checks++; \ + if (!(cond)) { \ + failures++; \ + if (failures <= 20) \ + printf(" FAIL %s:%d: " fmt "\n", __func__, __LINE__, ##__VA_ARGS__);\ + } \ + } while (0) + +/* One stream: a queue of SDUs drained by a sequence of grants. */ +static void run_stream(const char *name, uint32_t n_sdus, uint32_t sdu_lo, + uint32_t sdu_hi, uint32_t grant_lo, uint32_t grant_hi, + uint32_t poll_pdu, uint32_t poll_byte) { + static rlc_plan_t plan; + static uint32_t sdu_len[MAX_SDUS]; + static uint32_t sent_off[MAX_SDUS]; /* independent reassembly model */ + + for (uint32_t i = 0; i < n_sdus; i++) { + sdu_len[i] = rnd(sdu_lo, sdu_hi); + sent_off[i] = 0; + } + + uint32_t head = 0; /* first SDU still (partly) queued */ + uint32_t so_first = 0; /* bytes of SDU[head] already transmitted */ + uint32_t sn_base = rnd(0, RLC_SN_MASK); + uint32_t pwp = 0, bwp = 0; /* planner-reported counters */ + uint32_t m_pwp = 0, m_bwp = 0; /* independent poll model */ + uint32_t grants = 0, pdus = 0; + + while (head < n_sdus && grants < 100000u) { + const uint32_t grant = rnd(grant_lo, grant_hi); + + /* --- gather, exactly as the kernel will do it from the list --- */ + uint32_t avail = n_sdus - head; + if (avail > RLC_MAX_PDUS_PER_GRANT) avail = RLC_MAX_PDUS_PER_GRANT; + plan.n_avail = avail; + for (uint32_t i = 0; i < avail; i++) plan.sdu_len[i] = sdu_len[head + i]; + + rlc_plan_in_t in = { + .grant_bytes = grant, + .sn_base = sn_base, + .so_first = so_first, + .poll_pdu = poll_pdu, + .poll_byte = poll_byte, + .pdu_without_poll = pwp, + .byte_without_poll = bwp, + .queue_drained = (avail == n_sdus - head), + }; + rlc_plan_out_t out; + /* Runs the scan planner (the one that is vectorised on target) and diffs + every output field against the reference planner. */ + static rlc_plan_t ref; + uint32_t nbad = 0; + const uint32_t n = rlc_plan_compute_checked(&plan, &ref, &in, &out, &nbad); + CHECK(nbad == 0, "grant %u: scan planner diverges from reference in %u " + "fields (n=%u grant=%u so_first=%u)", grants, nbad, n, grant, + so_first); + grants++; + + CHECK(n <= avail, "n=%u > avail=%u", n, avail); + CHECK(plan.tb_used <= grant, "tb_used=%u > grant=%u", plan.tb_used, grant); + + if (n == 0) { + /* Only legal if even a minimal header plus one byte cannot fit. */ + const uint32_t hdr = (so_first == 0) ? RLC_AMD_HDR_MIN : RLC_AMD_HDR_MAX; + CHECK(grant <= hdr, "empty plan with grant=%u hdr=%u", grant, hdr); + sn_base = out.sn_next; + pwp = out.pdu_without_poll; + bwp = out.byte_without_poll; + continue; + } + + /* SN is per SDU: it restarts from this grant's base each time, and a + trailing segment does not consume one, so the next grant's leading + segment reuses the same SN. */ + uint32_t sn_expect = sn_base; + uint32_t off = 0; + for (uint32_t i = 0; i < n; i++) { + const uint32_t q = head + i; + + /* structure */ + CHECK(plan.tb_off[i] == off, "grant %u pdu %u: tb_off=%u want %u", grants, + i, plan.tb_off[i], off); + CHECK(plan.hdr_len[i] == rlc_amd_hdr_len(plan.si[i]), + "pdu %u: hdr_len=%u si=%u", i, plan.hdr_len[i], plan.si[i]); + CHECK(plan.seg_len[i] >= 1u, "pdu %u: empty payload", i); + CHECK(plan.sn[i] == (sn_expect & RLC_SN_MASK), "pdu %u: sn=%u want %u", i, + plan.sn[i], sn_expect & RLC_SN_MASK); + sn_expect = (sn_expect + 1u) & RLC_SN_MASK; + + /* SI / SO / last_seg consistency */ + const int has_so = (plan.so[i] != 0); + const int si_has_so = RLC_SI_HAS_SO(plan.si[i]); + CHECK(has_so == si_has_so, "pdu %u: so=%u but si=%u", i, plan.so[i], + plan.si[i]); + const int is_last = + (plan.si[i] == RLC_SI_FULL || plan.si[i] == RLC_SI_LAST); + CHECK((uint32_t)is_last == plan.last_seg[i], "pdu %u: si=%u last_seg=%u", + i, plan.si[i], plan.last_seg[i]); + CHECK(plan.last_seg[i] || i == n - 1u, + "pdu %u of %u is a non-final segment", i, n); + + /* reassembly: segments of one SDU must be contiguous and complete */ + CHECK(plan.so[i] == sent_off[q], "sdu %u: so=%u want %u", q, plan.so[i], + sent_off[q]); + sent_off[q] += plan.seg_len[i]; + CHECK(sent_off[q] <= sdu_len[q], "sdu %u: overrun %u > %u", q, + sent_off[q], sdu_len[q]); + if (plan.last_seg[i]) + CHECK(sent_off[q] == sdu_len[q], "sdu %u: short %u != %u", q, + sent_off[q], sdu_len[q]); + + /* independent poll model (TS 38.322 5.3.3.2) */ + m_pwp += 1u; + m_bwp += plan.seg_len[i]; + uint32_t want_poll = 0; + if (poll_pdu && m_pwp >= poll_pdu) want_poll = 1; + else if (poll_byte && m_bwp >= poll_byte) want_poll = 1; + if (want_poll) { m_pwp = 0; m_bwp = 0; } + /* the buffer-empty poll is applied by the planner to the final PDU */ + const int drained_here = + in.queue_drained && !out.partial && (i == n - 1u); + if (drained_here && !want_poll) { + want_poll = 1; + m_pwp = 0; + m_bwp = 0; + } + CHECK(plan.poll[i] == want_poll, "pdu %u: poll=%u want %u", i, + plan.poll[i], want_poll); + + off += plan.hdr_len[i] + plan.seg_len[i]; + pdus++; + } + CHECK(plan.tb_used == off, "tb_used=%u want %u", plan.tb_used, off); + CHECK(out.pdu_without_poll == m_pwp, "pwp=%u want %u", + out.pdu_without_poll, m_pwp); + CHECK(out.byte_without_poll == m_bwp, "bwp=%u want %u", + out.byte_without_poll, m_bwp); + + /* advance the queue exactly as the kernel will */ + head += n - out.partial; + so_first = out.so_next; + CHECK(out.partial == 0 || so_first == sent_off[head], + "cursor %u != sent_off %u", so_first, sent_off[head]); + sn_base = out.sn_next; + pwp = out.pdu_without_poll; + bwp = out.byte_without_poll; + } + + for (uint32_t i = 0; i < n_sdus; i++) + CHECK(sent_off[i] == sdu_len[i], "sdu %u not fully sent: %u/%u", i, + sent_off[i], sdu_len[i]); + + printf(" %-28s %6u SDUs %6u grants %7u PDUs\n", name, n_sdus, grants, pdus); +} + +int main(void) { + printf("RLC AM plan reference tests\n"); + + /* TC1-like: 1350 B SDUs, generous grants -> mostly unsegmented */ + run_stream("tc1-large-grant", 2000, 1350, 1350, 20000, 40000, 32, 25000); + /* TC2-like: 800 B SDUs */ + run_stream("tc2-800B", 2000, 800, 800, 8000, 16000, 32, 25000); + /* grants near the PDU size -> segmentation on almost every grant */ + run_stream("heavy-segmentation", 1500, 1350, 1350, 200, 900, 32, 25000); + /* pathological: grants barely above the header */ + run_stream("tiny-grants", 300, 100, 400, 4, 12, 8, 64); + /* variable SDU sizes */ + run_stream("mixed-sizes", 2000, 1, 2000, 100, 5000, 16, 4000); + /* poll disabled */ + run_stream("no-poll", 1000, 800, 800, 4000, 9000, 0, 0); + /* poll on every PDU */ + run_stream("poll-every-pdu", 800, 500, 500, 3000, 6000, 1, 0); + /* byte-threshold poll only */ + run_stream("poll-bytes-only", 1200, 700, 700, 5000, 12000, 0, 3000); + /* SN wraparound */ + rng_state = 999u; + run_stream("sn-wrap", 3000, 900, 900, 2000, 4000, 32, 25000); + + printf("\n%ld checks, %d failures -> %s\n", checks, failures, + failures ? "FAIL" : "PASS"); + return failures ? 1 : 0; +} diff --git a/software/tests/multi_producer_single_consumer_double_linked_list/test/test_rlc_ul.c b/software/tests/multi_producer_single_consumer_double_linked_list/test/test_rlc_ul.c new file mode 100644 index 0000000..1b372ae --- /dev/null +++ b/software/tests/multi_producer_single_consumer_double_linked_list/test/test_rlc_ul.c @@ -0,0 +1,204 @@ +// Copyright 2025 ETH Zurich and University of Bologna. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// Author: Zexin Fu + +/* Host-side unit test for the RLC AM uplink. + + Builds transport blocks the way a conforming transmitter would -- SDUs + segmented across grants, headers serialised with the real rlc_pdu.h writer + -- then drives scan / reassemble / deliver and checks that every SDU comes + out exactly once, in order, at its original length. + + The part worth having: each TB is reassembled TWICE, once as a single range + and once split into N disjoint slices the way N cores would. Both must + produce identical entity state. That is the claim rlc_ul_reassemble_range() + makes about being safe to parallelise, tested rather than asserted. + + Build and run: + gcc -O2 -I../kernel test_rlc_ul.c -o /tmp/t && /tmp/t +*/ + +#include +#include + +#include "../kernel/rlc_ul.c" + +#define MAX_SDUS 2048 +#define TB_CAP 8192 + +static uint32_t rng_state = 2024u; +static uint32_t rnd(uint32_t lo, uint32_t hi) { + rng_state = rng_state * 1103515245u + 12345u; + return lo + (rng_state >> 9) % (hi - lo + 1u); +} + +static int failures = 0; +static long checks = 0; +#define CHECK(cond, fmt, ...) \ + do { \ + checks++; \ + if (!(cond)) { \ + failures++; \ + if (failures <= 20) \ + printf(" FAIL %s:%d: " fmt "\n", __func__, __LINE__, ##__VA_ARGS__); \ + } \ + } while (0) + +/* --- transmitter: segment SDUs into transport blocks ------------------- */ + +typedef struct { + uint8_t tb[TB_CAP]; + uint32_t len; + uint32_t npdu; +} tb_t; + +/* Emit one PDU into the TB: MAC length + RLC header + payload. */ +static int tb_put(tb_t *t, uint32_t sn, uint32_t si, uint32_t poll, uint32_t so, + const uint8_t *payload, uint32_t seg_len) { + const uint32_t hdr = rlc_amd_hdr_len(si); + const uint32_t need = RLC_UL_MAC_HDR + hdr + seg_len; + if (t->len + need > TB_CAP) return 0; + uint8_t *p = t->tb + t->len; + p[0] = (uint8_t)(((hdr + seg_len) >> 8) & 0xFF); + p[1] = (uint8_t)((hdr + seg_len) & 0xFF); + rlc_amd_hdr_write(p + RLC_UL_MAC_HDR, sn, si, poll, so); + memcpy(p + RLC_UL_MAC_HDR + hdr, payload, seg_len); + t->len += need; + t->npdu++; + return 1; +} + +/* --- one stream ------------------------------------------------------- */ + +static void run_stream(const char *name, uint32_t n_sdus, uint32_t lo, + uint32_t hi, uint32_t tb_budget, uint32_t poll_every, + uint32_t slices) { + static uint8_t sdu[MAX_SDUS][2048]; + static uint32_t sdu_len[MAX_SDUS]; + static rlc_ul_scan_t scan; + static rlc_ul_entity_t ent, ent_ref; + + for (uint32_t i = 0; i < n_sdus; i++) { + sdu_len[i] = rnd(lo, hi); + for (uint32_t b = 0; b < sdu_len[i]; b++) sdu[i][b] = (uint8_t)(i * 7u + b); + } + + rlc_ul_entity_init(&ent); + uint32_t sn = 0, cur = 0, so = 0, tbs = 0, total_pdus = 0; + uint32_t delivered_total = 0; + + while (cur < n_sdus) { + tb_t t; + t.len = 0; t.npdu = 0; + + /* Fill one TB, segmenting the SDU that does not fit whole. */ + while (cur < n_sdus) { + const uint32_t remaining = sdu_len[cur] - so; + const uint32_t si_full = (so == 0) ? RLC_SI_FULL : RLC_SI_LAST; + const uint32_t hdr = rlc_amd_hdr_len(si_full); + if (t.len + RLC_UL_MAC_HDR + hdr + 1u > tb_budget) break; + const uint32_t room = tb_budget - t.len - RLC_UL_MAC_HDR - hdr; + const uint32_t poll = (poll_every && ((sn + 1u) % poll_every == 0)) ? 1u : 0u; + + if (remaining <= room) { + if (!tb_put(&t, sn, si_full, poll, so, sdu[cur] + so, remaining)) break; + sn = (sn + 1u) & RLC_SN_MASK; cur++; so = 0; + } else { + const uint32_t si = (so == 0) ? RLC_SI_FIRST : RLC_SI_MIDDLE; + if (!tb_put(&t, sn, si, poll, so, sdu[cur] + so, room)) break; + /* SN is per SDU: a segment does NOT consume one. The next segment of + this same SDU reuses it, and SO tells the receiver where it goes. */ + so += room; + break; /* TB is full by construction */ + } + } + if (t.npdu == 0) break; + tbs++; + + /* --- scan --- */ + const uint32_t n = rlc_ul_scan(&scan, t.tb, t.len); + CHECK(n == t.npdu, "TB %u: scanned %u PDUs, emitted %u", tbs, n, t.npdu); + CHECK(scan.truncated == 0, "TB %u: reported truncated", tbs); + CHECK(scan.overflow == 0, "TB %u: reported overflow", tbs); + total_pdus += n; + + for (uint32_t i = 0; i < n; i++) { + CHECK(scan.pdu[i].hdr_len == rlc_amd_hdr_len(scan.pdu[i].si), + "pdu %u: hdr_len %u vs si %u", i, scan.pdu[i].hdr_len, + scan.pdu[i].si); + CHECK(scan.pdu[i].seg_len >= 1u, "pdu %u: empty payload", i); + } + + /* --- reassemble twice: one range, then sliced like N cores --- */ + memcpy(&ent_ref, &ent, sizeof(ent)); + rlc_ul_reassemble_range(&ent_ref, &scan, 0, n); + + const uint32_t step = (n + slices - 1u) / (slices ? slices : 1u); + for (uint32_t s = 0; s < n; s += (step ? step : 1u)) + rlc_ul_reassemble_range(&ent, &scan, s, s + (step ? step : 1u)); + + CHECK(memcmp(&ent, &ent_ref, sizeof(ent)) == 0, + "TB %u: %u-way sliced reassembly differs from single-range", tbs, + slices); + + /* --- deliver --- */ + delivered_total += rlc_ul_deliver(&ent); + } + + CHECK(delivered_total == n_sdus, "delivered %u of %u SDUs", delivered_total, + n_sdus); + CHECK(ent.delivered == n_sdus, "entity counter %u vs %u", ent.delivered, + n_sdus); + CHECK(ent.out_of_window == 0, "%u segments fell outside the window", + ent.out_of_window); + + uint32_t want_bytes = 0; + for (uint32_t i = 0; i < n_sdus; i++) want_bytes += sdu_len[i]; + CHECK(ent.delivered_bytes == want_bytes, "delivered %u bytes, want %u", + ent.delivered_bytes, want_bytes); + + /* STATUS must acknowledge exactly what was delivered in order. */ + uint8_t st[8]; + const uint32_t stl = rlc_ul_build_status(&ent, st); + uint32_t ack = 0, e1 = 0; + rlc_status_hdr_read(st, &ack, &e1); + CHECK(stl == RLC_STATUS_HDR_LEN, "status len %u", stl); + CHECK(ack == ent.rx_next, "STATUS ACK_SN %u != rx_next %u", ack, ent.rx_next); + CHECK(e1 == 0, "E1 set with no NACKs"); + + printf(" %-26s %5u SDUs %5u TBs %6u PDUs %u-way slices\n", name, n_sdus, + tbs, total_pdus, slices); +} + +int main(void) { + printf("RLC AM uplink tests\n"); + + run_stream("tc1-1350B-large-tb", 500, 1350, 1350, 8192, 32, 1); + run_stream("tc1-sliced-4way", 500, 1350, 1350, 8192, 32, 4); + run_stream("tc2-800B", 500, 800, 800, 8192, 32, 4); + run_stream("heavy-segmentation", 400, 1350, 1350, 1024, 32, 4); + run_stream("tiny-tb-every-sdu-cut",200, 600, 900, 300, 16, 4); + run_stream("mixed-sizes", 600, 1, 2000, 4096, 16, 8); + run_stream("poll-every-pdu", 200, 500, 500, 4096, 1, 4); + run_stream("no-poll", 200, 500, 500, 4096, 0, 4); + rng_state = 77u; + run_stream("sliced-16way", 400, 900, 900, 8192, 32, 16); + + printf("\n%ld checks, %d failures -> %s\n", checks, failures, + failures ? "FAIL" : "PASS"); + return failures ? 1 : 0; +} From f6e10d0e5d285f97b97d7480d963daae8fe48ea2 Mon Sep 17 00:00:00 2001 From: Zexin Fu Date: Tue, 8 Sep 2026 03:51:43 +0200 Subject: [PATCH 07/48] rlc: fence the UL phase barriers; align uplink to the documented 160 B profile The armed flag was a plain static: core 0's store and the consumers' load both execute and still disagreed. A hardware barrier synchronises execution, not memory. Now atomic + fenced, and the phase barriers fence on both sides so the scan buffer is published before it is read. Uplink SDUs are 160 B per the DP doc (1/8/4 Gbps, 1600 slots/s), not the 1360 B downlink dataset. At 1360 B an 8192 B block held exactly six whole SDUs, so nothing ever segmented. --- .../kernel/rlc_ul_drv.c | 58 +++++++++++++++++-- 1 file changed, 52 insertions(+), 6 deletions(-) diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_ul_drv.c b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_ul_drv.c index 8cb3f71..b41bd94 100644 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_ul_drv.c +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_ul_drv.c @@ -58,9 +58,46 @@ #define RLC_UL_TB_BYTES 8192u #endif -/* How many uplink SDUs the harness feeds in, per entity. */ +/* Uplink SDU size. + + The DP Introduction doc specifies the uplink as **160 B** PDUs at 1 / 8 / 4 + Gbps for TC1 / TC2 / TC3 (see doc/KERNEL_REVIEW_NOTES.md "Huawei test + cases"). The first version of this harness reused the 1360 B downlink + dataset, which is not the documented uplink workload and happens to be a + pathological choice: 1360 B SDUs in an 8192 B block pack as exactly six + whole SDUs with two bytes spare, so nothing ever segmented and the serial + header walk was measured on traffic containing none of what makes it + serial. At 160 B a block carries ~49 PDUs and the boundary segments. */ +#ifndef RLC_UL_SDU_BYTES +#define RLC_UL_SDU_BYTES 160u +#endif + +/* Documented UL rate per test case, bits/s (doc: TC1 1 Gbps, TC2 8 Gbps, + TC3 4 Gbps -- all at 160 B). RLC_UL_TC selects one. */ +#ifndef RLC_UL_TC +#define RLC_UL_TC 1 +#endif +#if RLC_UL_TC == 1 +#define RLC_UL_RATE_BPS 1000000000ull +#elif RLC_UL_TC == 2 +#define RLC_UL_RATE_BPS 8000000000ull +#elif RLC_UL_TC == 3 +#define RLC_UL_RATE_BPS 4000000000ull +#else +#error "RLC_UL_TC must be 1, 2 or 3" +#endif + +/* Slot cadence, from the doc's "pkts/slot (1600 slots/s)" row. One UL slot's + aggregate byte budget is rate/8/1600; at 160 B that is the SDU count a + conforming receiver must absorb per slot. */ +#define RLC_UL_SLOTS_PER_SEC 1600u +#define RLC_UL_SLOT_BYTES ((uint32_t)(RLC_UL_RATE_BPS / 8ull / RLC_UL_SLOTS_PER_SEC)) +#define RLC_UL_SLOT_SDUS (RLC_UL_SLOT_BYTES / RLC_UL_SDU_BYTES) + +/* How many uplink SDUs the harness feeds in, per entity. Defaults to one + slot's worth at the selected test case, so a run models a slot's arrival. */ #ifndef RLC_UL_SDUS -#define RLC_UL_SDUS 64u +#define RLC_UL_SDUS RLC_UL_SLOT_SDUS #endif static rlc_ul_entity_t rlc_ul_ent[NUM_USERS] @@ -170,9 +207,15 @@ void rlc_ul_init(void) { static uint32_t rlc_ul_build_tb(uint8_t *tb, uint32_t cap) { uint32_t len = 0u; while (rlc_ul_cur_sdu < RLC_UL_SDUS) { - const uint32_t sdu_len = PDU_SIZE; - const uint8_t *src = (const uint8_t *)(uintptr_t)pdcp_pkgs[rlc_ul_cur_sdu % - NUM_PKGS].src_addr; + const uint32_t sdu_len = RLC_UL_SDU_BYTES; + /* Payload comes from the PDCP source region so the harness needs no + dataset of its own; UL SDUs are smaller than a DL packet, so take + successive slices and wrap within the packet. */ + const uint32_t per_pkt = (uint32_t)PDU_SIZE / RLC_UL_SDU_BYTES; + const uint8_t *base = (const uint8_t *)(uintptr_t) + pdcp_pkgs[(rlc_ul_cur_sdu / (per_pkt ? per_pkt : 1u)) % NUM_PKGS].src_addr; + const uint8_t *src = + base + (per_pkt ? (rlc_ul_cur_sdu % per_pkt) : 0u) * RLC_UL_SDU_BYTES; const uint32_t remaining = sdu_len - rlc_ul_cur_so; const uint32_t si_full = (rlc_ul_cur_so == 0u) ? RLC_SI_FULL : RLC_SI_LAST; const uint32_t hdr = rlc_amd_hdr_len(si_full); @@ -269,7 +312,7 @@ static void rlc_ul_slot(uint32_t me, uint32_t bar_mask) { static void rlc_ul_report(void) { const rlc_ul_entity_t *e = &rlc_ul_ent[0]; - const uint32_t want = RLC_UL_SDUS * (uint32_t)PDU_SIZE; + const uint32_t want = (uint32_t)RLC_UL_SDUS * RLC_UL_SDU_BYTES; printf_lock_acquire(&printf_lock); printf("[UL] barrier tile_mask=0x%x local_mask=0x%x armed=%u\n", (uint32_t)atomic_load_explicit(&rlc_ul_tile_mask, memory_order_relaxed), @@ -280,6 +323,9 @@ static void rlc_ul_report(void) { printf("[UL] slots=%u tb_bytes=%u segments=%u polls_ack=%u exec=%s\n", rlc_ul_slots, rlc_ul_tb_bytes, e->reassembled, rlc_ul_status_pdus, (RLC_UL_EXEC == RLC_UL_EXEC_COPY) ? "copy" : "count"); + printf("[UL] tc=%u sdu=%uB slot_bytes=%u slot_sdus=%u\n", (unsigned)RLC_UL_TC, + (unsigned)RLC_UL_SDU_BYTES, (unsigned)RLC_UL_SLOT_BYTES, + (unsigned)RLC_UL_SLOT_SDUS); printf("[UL] delivered=%u/%u bytes=%u/%u rx_next=%u dup=%u oow=%u\n", e->delivered, (unsigned)RLC_UL_SDUS, e->delivered_bytes, want, e->rx_next, e->dup, e->out_of_window); From 998edd9db5e69825a0742496e7a0232a2847ce49 Mon Sep 17 00:00:00 2001 From: Zexin Fu Date: Tue, 8 Sep 2026 04:09:27 +0200 Subject: [PATCH 08/48] rlc: fence the TTI phase barriers snrt_cluster_partial_barrier is one plain store to the barrier register: it synchronises execution, not memory. Every phase boundary hands shared memory from one core to the others -- the owner writes a 7 KB plan and every helper reads it to copy payload -- so without a fence a helper can copy using stale lengths and offsets, silently. The uplink proved this mechanism on hardware today: a store and a load with a barrier between them disagreed, both provably executed. Legacy image bit-exact; UL images bit-identical, so the shared-barrier refactor changed no code. --- .../kernel/rlc_am.c | 9 +-- .../kernel/rlc_sync.h | 62 +++++++++++++++++++ .../kernel/rlc_ul_drv.c | 20 ++---- 3 files changed, 71 insertions(+), 20 deletions(-) create mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_sync.h diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.c b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.c index 492f9b5..9e62655 100644 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.c +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.c @@ -146,6 +146,7 @@ static void rlc_am_verify_grant(uint32_t u); /* rlc_memcpy8() lives in rlc_copy.h: the uplink harness needs the same copy, and neither direction owns it. */ #include "rlc_copy.h" +#include "rlc_sync.h" /* ------------------------------------------------------------------------ */ @@ -520,13 +521,13 @@ void rlc_am_consumer_tti(uint32_t core_id) { const uint32_t tti_start = benchmark_get_cycle(); #endif rlc_am_plan_phase(me); - snrt_cluster_partial_barrier(mask); /* helpers BLOCK here, not polling */ + rlc_phase_barrier(mask); /* helpers BLOCK here; fenced -- see rlc_sync.h */ rlc_am_execute_phase(); - snrt_cluster_partial_barrier(mask); + rlc_phase_barrier(mask); rlc_am_commit_phase(me); - snrt_cluster_partial_barrier(mask); + rlc_phase_barrier(mask); if (me == 0u) { rlc_am_ttis++; @@ -535,7 +536,7 @@ void rlc_am_consumer_tti(uint32_t core_id) { PRODUCER_CORE_NUM && rlc_am_idle()) ? 1u : 0u, memory_order_release); } - snrt_cluster_partial_barrier(mask); + rlc_phase_barrier(mask); if (atomic_load_explicit(&rlc_am_stop, memory_order_acquire)) break; #if RLC_TTI_CYCLES diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_sync.h b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_sync.h new file mode 100644 index 0000000..2afe9db --- /dev/null +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_sync.h @@ -0,0 +1,62 @@ +// Copyright 2025 ETH Zurich and University of Bologna. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// Author: Zexin Fu + +/* Phase barrier for the RLC TTI loops, downlink and uplink. + + **snrt_cluster_partial_barrier() synchronises execution, not memory.** Its + whole implementation is one plain store to the barrier register: + + void snrt_cluster_partial_barrier(uint32_t local_mask) { + *(volatile uint32_t *)_snrt_barrier_reg_ptr() = local_mask; + } + + It makes the participating cores wait for one another, and that is all. It + issues no fence, so a write made before it is not guaranteed visible to + another core after it. The name invites exactly the wrong assumption, and + the uplink proved the consequence on real hardware: a value one core stored + and another core loaded, with a barrier in between, disagreed -- both the + store and the load provably executed. + + Every RLC phase boundary is a producer/consumer handoff of shared memory: + + DL plan -> execute : the owner writes ~7 KB of plan (header lengths, + segment lengths, source pointers, n_avail, + tb_used) and every helper then reads it to copy + payload. Stale lengths or offsets here corrupt + the transport block silently. + DL execute -> commit: helpers write payload, the owner then accounts it. + UL scan -> reassemble: consumer 0 writes the scan buffer, the others + read it. + + So fence on both sides: release what this phase wrote, then acquire what + the others wrote. Cost is two fences per boundary against a whole phase of + work -- irrelevant next to a silently wrong transport block. */ + +#ifndef RLC_SYNC_H +#define RLC_SYNC_H + +#include +#include + +static inline void rlc_phase_barrier(uint32_t local_mask) { + asm volatile("fence" ::: "memory"); /* publish this phase's writes */ + snrt_cluster_partial_barrier(local_mask); + asm volatile("fence" ::: "memory"); /* observe the other cores' writes */ +} + +#endif /* RLC_SYNC_H */ diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_ul_drv.c b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_ul_drv.c index b41bd94..b4f0f2d 100644 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_ul_drv.c +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_ul_drv.c @@ -43,6 +43,7 @@ #define RLC_UL_DRV_C #include "rlc_copy.h" +#include "rlc_sync.h" #include "rlc_ul.h" #include "rlc_ul_drv.h" #include "rlc_ul.c" @@ -120,19 +121,6 @@ static uint32_t rlc_ul_status_pdus; static _Atomic uint32_t rlc_ul_stop __attribute__((aligned(CACHE_LINE_SIZE))) __attribute__((section(".data"))); -/* Phase barrier. - - snrt_cluster_partial_barrier() is documented as "a plain volatile store": it - is a synchronisation event, not a memory fence. Consumer 0 writes the scan - buffer in phase 1 and the other consumers read it in phase 2, so without an - explicit fence on both sides the readers may see a partially published - buffer even though the barrier did exactly what it promised. Fence before, - to publish this phase's writes; fence after, to see everyone else's. */ -static inline void rlc_ul_barrier(uint32_t mask) { - asm volatile("fence" ::: "memory"); - snrt_cluster_partial_barrier(mask); - asm volatile("fence" ::: "memory"); -} /* Per-phase cycle accounting. build/scan/deliver run on consumer 0 only; reassemble is per-core, because the point of the measurement is how the @@ -275,7 +263,7 @@ static void rlc_ul_slot(uint32_t me, uint32_t bar_mask) { rlc_ul_cyc_scan += t2 - t1; rlc_ul_slots++; } - rlc_ul_barrier(bar_mask); + rlc_phase_barrier(bar_mask); /* --- phase 2: reassemble (parallel, disjoint slices) --- */ { @@ -291,7 +279,7 @@ static void rlc_ul_slot(uint32_t me, uint32_t bar_mask) { } rlc_ul_cyc_reasm[me].cyc += benchmark_get_cycle() - t0; } - rlc_ul_barrier(bar_mask); + rlc_phase_barrier(bar_mask); /* --- phase 3: deliver in order + STATUS (serial by definition) --- */ if (me == 0u) { @@ -307,7 +295,7 @@ static void rlc_ul_slot(uint32_t me, uint32_t bar_mask) { if (rlc_ul_done() && rlc_ul_scan_buf.n == 0u) atomic_store_explicit(&rlc_ul_stop, 1u, memory_order_relaxed); } - rlc_ul_barrier(bar_mask); + rlc_phase_barrier(bar_mask); } static void rlc_ul_report(void) { From 7d3703d78a36d8f921ad32ac711f2d2f0122956d Mon Sep 17 00:00:00 2001 From: Zexin Fu Date: Tue, 8 Sep 2026 04:34:47 +0200 Subject: [PATCH 09/48] notes: synchronisation is not visibility -- four instances of one defect Both runtime barriers are a single memory-mapped access and emit no fence. Snitch and Spatz have separate LSUs. volatile constrains the compiler and nothing else. cache-test-scalar fails on the model and passes on RTL from the same binary, so passing on hardware is not evidence the class is absent. --- .../SYNCHRONISATION_IS_NOT_VISIBILITY.md | 83 +++++++++++++++++++ 1 file changed, 83 insertions(+) create mode 100644 reports/design_notes/SYNCHRONISATION_IS_NOT_VISIBILITY.md diff --git a/reports/design_notes/SYNCHRONISATION_IS_NOT_VISIBILITY.md b/reports/design_notes/SYNCHRONISATION_IS_NOT_VISIBILITY.md new file mode 100644 index 0000000..7f95f00 --- /dev/null +++ b/reports/design_notes/SYNCHRONISATION_IS_NOT_VISIBILITY.md @@ -0,0 +1,83 @@ +# Synchronisation is not visibility + +**2026-09-08.** Four instances of one defect in a single day, across the RLC +kernel and the cache test suite, on two engines. The instances are cheap to fix +individually; the pattern is the thing worth keeping. + +## The rule + +**Both of this runtime's barriers are a single memory-mapped access. Neither +emits a fence. They make cores wait for one another and nothing more.** + +```asm +_snrt_cluster_barrier: ; snRuntime/src/platforms/shared/start_snitch.S:35 + call _snrt_barrier_reg_ptr + lw a0, 0(a0) ; the entire barrier + ret +``` + +```c +void snrt_cluster_partial_barrier(uint32_t local_mask) { /* snRuntime/src/barrier.c */ + *(volatile uint32_t *)_snrt_barrier_reg_ptr() = local_mask; +} +``` + +So a store made before a barrier is **not** guaranteed visible to another core +after it. The names promise otherwise, which is the whole problem: "barrier" is +read as a memory barrier, and it is not one. + +A second, independent case of the same confusion: **Snitch and Spatz have +separate load/store units.** A vector store and a scalar load of the same +address are unordered with respect to each other without an explicit `fence`. + +And in both cases `volatile` does not help. It constrains the *compiler*. It +says nothing about a write buffer, an async cache, or a second LSU. An inline +asm `"memory"` clobber is likewise compiler-only. + +## The instances + +| # | Site | Handoff | Symptom | +|---|---|---|---| +| 1 | `rlc_ul_drv.c` armed flag | core 0 store โ†’ consumers load, across `snrt_cluster_hw_barrier()` | Flag read as 0 on every consumer. **Store and load both provably executed** (disassembly) and disagreed. | +| 2 | `rlc_am.c` / `rlc_ul_drv.c` TTI phase barriers | owner writes ~7 KB plan โ†’ helpers read it to copy payload | Suspected silent transport-block corruption; open. | +| 3 | `cache-mix-smoke/main.c` | Spatz `vse32.v` โ†’ Snitch scalar load, same address | **125 mismatches on RTL.** `fences: 0` in the file. | +| 4 | `cache-test-scalar/main.c` | core 0 writes 256 lines โ†’ all cores read, 14 bare barriers | Fails on GVSoC at 48-84 % density; `cache-basic` sub-test **passes on RTL**. | + +## What #4 shows that the others don't + +Instance 4 fails on the model and passes on hardware for the *same binary*. +That is not a model defect and not a hardware defect โ€” it is a **latent +software defect whose exposure depends on how wide the store-visibility window +is**. The model's async cache has a wider window than the RTL's, so the model +exposes it and the hardware hides it. + +The practical consequence: **passing on RTL is not evidence that this class of +bug is absent.** A test can rely on a guarantee it never had, and hardware +timing can conceal that indefinitely. + +## What to do + +1. Fence both sides of every phase boundary that hands memory between cores. + `rlc_sync.h`'s `rlc_phase_barrier()` is the pattern: fence, barrier, fence. +2. Fence after a vector store before any scalar access to the same address. + `rlc_copy.h`'s `rlc_memcpy8()` already does this. +3. For a flag one core publishes for others, use `_Atomic` with release/acquire + **and** a fence โ€” the atomic alone orders the compiler and the single core's + accesses, not the fabric. +4. Do not read `volatile` as a synchronisation primitive anywhere. + +## Cost + +Two `fence` instructions per boundary. Against a phase of work this is +irrelevant, and it is unconditionally cheaper than a silently wrong transport +block or a test that passes for the wrong reason. + +## Open + +- Whether #2 explains the RLC multi-entity wedge (M16/24/48). Fixed because it + is a defect regardless; **not** asserted as the wedge's cause. +- Whether fencing #4 collapses the GVSoC mismatch density. Experiment pending. +- #3 needs a pristine-RTL arm to separate "test was always racy" from "recent + cache rewrites perturbed the race" โ€” both hypotheses predict that adding a + fence fixes it, so the fence experiment alone cannot separate them. + (Correction owed to the L1-timing session, who caught that.) From 6407f9c91e1e97971052f84aa7f12845c50d882a Mon Sep 17 00:00:00 2001 From: Zexin Fu Date: Tue, 8 Sep 2026 04:37:53 +0200 Subject: [PATCH 10/48] notes: read the generated artefact, not the config Bender.lock pins insitu-cache to a Git rev and wins over Bender.local's path override until bender update regenerates it -- so the override did not apply, independently of compile.vsim.tcl being stale. Either alone defeats it. --- .../PROVENANCE_THE_TOOL_NOT_THE_CONFIG.md | 78 +++++++++++++++++++ 1 file changed, 78 insertions(+) create mode 100644 reports/design_notes/PROVENANCE_THE_TOOL_NOT_THE_CONFIG.md diff --git a/reports/design_notes/PROVENANCE_THE_TOOL_NOT_THE_CONFIG.md b/reports/design_notes/PROVENANCE_THE_TOOL_NOT_THE_CONFIG.md new file mode 100644 index 0000000..d970167 --- /dev/null +++ b/reports/design_notes/PROVENANCE_THE_TOOL_NOT_THE_CONFIG.md @@ -0,0 +1,78 @@ +# Ask the tool what it did, not the config what it should have done + +**2026-09-08.** Two provenance failures in one night, on two sides of the same +comparison, both of which would have produced a clean-looking wrong answer. + +## The rule + +**A configuration file states an intention. Only the generated artefact records +what actually happened.** Read the artefact. + +## Case 1 โ€” `Bender.local` overrides do not apply until the lock is regenerated + +`Bender.local` says: + +```yaml +overrides: + insitu-cache: { path: "working_dir/insitu-cache" } +``` + +`Bender.lock` says: + +```yaml +insitu-cache: + revision: f1cbe54dca0989f025b0450e85c42faf2bf5cbf1 + source: + Git: https://github.com/pulp-platform/Insitu-Cache.git +``` + +**The lock wins.** It resolves to a Git checkout under `hardware/deps/`, not to +the overridden path, until `bender update` regenerates it. So reading +`Bender.local` and concluding "we are compiling `working_dir`" is wrong twice +over: + +1. the lock still resolves to `hardware/deps`, and +2. `sim/work/compile.vsim.tcl` is a make target whose prerequisites are + `rtl_lib.cc`, `common_lib.cc`, `bootdata.cc`, `bootrom.bin` โ€” **RTL sources + are not among them**, so `make vsim` does not re-run bender at all and a + months-old script stays authoritative. + +Either alone is enough to defeat the override. A peer independently hit the +same thing from the other direction: repointed `Bender.local` at a private +copy, launched a run, and the tool analysed the original tree anyway. + +**Do:** `grep` the resolved path out of the generated `compile.vsim.tcl`. +**Don't:** infer it from `Bender.local`, `Bender.yml`, or a `bender` command +you ran earlier. + +## Case 2 โ€” a rebuild silently changes what a peer's comparison arm reads + +Two sessions compared RTL arms using ELFs from a shared `software/build/`. +One session was about to rebuild one of those ELFs (adding a fence to a test) +while the other planned to run it. The arms would then have differed in two +variables โ€” cache RTL *and* test binary โ€” and nothing in either log would have +shown it. + +**Do:** freeze the exact binaries a measurement used, `chmod a-w`, with a +manifest, *before* touching the build directory. Point collaborators at the +frozen copy, not at `software/build/`. + +## What made both catchable + +Not reasoning โ€” checking: + +| check | caught | +|---|---| +| `grep` the resolved path from the generated script | the `Bender.local` inference | +| hash the compile script + **all 30** sources it names | a mid-batch tree switch (tripwire) | +| verify a frozen ELF still matches the live one | that the freeze predated the rebuild | +| `pgrep -a vsim` before any process action | 19 unrelated simulations, none this repo | + +Each is seconds of work and each caught something the reasoning missed. Write +the comparability conditions down **before** running, while there is no result +yet to be tempted by. + +## Related + +See `SYNCHRONISATION_IS_NOT_VISIBILITY.md` for the other pattern from the same +night: a primitive whose name promises more than it delivers. From 0a542bef3a1e496d9a1fc0973e75de3a5fdbd31d Mon Sep 17 00:00:00 2001 From: Zexin Fu Date: Tue, 8 Sep 2026 04:39:43 +0200 Subject: [PATCH 11/48] notes: dependency tree is tool-owned; a marker inside it can outlive a revert --- .../PROVENANCE_THE_TOOL_NOT_THE_CONFIG.md | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/reports/design_notes/PROVENANCE_THE_TOOL_NOT_THE_CONFIG.md b/reports/design_notes/PROVENANCE_THE_TOOL_NOT_THE_CONFIG.md index d970167..a709bd1 100644 --- a/reports/design_notes/PROVENANCE_THE_TOOL_NOT_THE_CONFIG.md +++ b/reports/design_notes/PROVENANCE_THE_TOOL_NOT_THE_CONFIG.md @@ -45,6 +45,42 @@ copy, launched a run, and the tool analysed the original tree anyway. **Don't:** infer it from `Bender.local`, `Bender.yml`, or a `bender` command you ran earlier. +## Case 1b โ€” the dependency tree is tool-owned, so its contents are not stable + +Worse than the resolution problem: `hardware/deps/insitu-cache` is a +**bender-managed git checkout**, not a plain directory. + +``` +$ cd hardware/deps/insitu-cache && git status -sb +## HEAD (no branch) <- detached, as bender leaves it + M src/insitu_cache/insitu_cache_core.sv + M src/insitu_cache/insitu_cache_encoder.sv + M src/insitu_cache/insitu_cache_tcdm_wrapper.sv + M src/utilities/sram_forwarding_buffer.sv +?? DIRTY_zexin_timing_f1cbe54 +``` + +HEAD is `f1cbe54` and `Bender.lock` says `f1cbe54`, so **bender considers this +directory already correct.** Modified RTL exists only as uncommitted +working-tree changes on top. Any `bender checkout` / `bender update`, or a make +target depending on them, is entitled to restore the tree โ€” and it looks like +housekeeping, not a DUT change, precisely because HEAD already matches. + +**The failure mode is silent and inverts the result.** A mid-run revert means +the remaining tests measure *pristine* RTL, and they pass โ€” which is exactly +what a correct set of rewrites would also produce. Nothing looks wrong. + +**And the obvious mitigation is the one that fails here.** A marker file placed +in that directory (`DIRTY_zexin_timing_f1cbe54` above) is *untracked*, so a +`git checkout` reverts the `.sv` files and **leaves the marker standing**. The +marker then asserts "dirty" over pristine sources: worse than no marker. + +**Do:** keep the provenance record *outside* the tool-owned tree (here, +`reports/rtl_reference_2026-09-08/dut_tripwire.sha256`), and sample it +*during* a long run, not only at the end โ€” detection after the fact costs a +rerun. `dut_watch.sh` samples every 45 s and timestamps any change, so results +can be attributed to the DUT state that produced them. + ## Case 2 โ€” a rebuild silently changes what a peer's comparison arm reads Two sessions compared RTL arms using ELFs from a shared `software/build/`. @@ -67,11 +103,19 @@ Not reasoning โ€” checking: | hash the compile script + **all 30** sources it names | a mid-batch tree switch (tripwire) | | verify a frozen ELF still matches the live one | that the freeze predated the rebuild | | `pgrep -a vsim` before any process action | 19 unrelated simulations, none this repo | +| `git status -sb` inside a dependency directory | that it is a tool-owned detached checkout, revertible without warning | Each is seconds of work and each caught something the reasoning missed. Write the comparability conditions down **before** running, while there is no result yet to be tempted by. +**A freeze is a claim about a moment; it becomes evidence only when something +independently ties it to that moment.** For the ELFs that was a peer verifying +the frozen copy still matched the live one โ€” proving the freeze predated the +rebuild. For the RTL it was two sessions hashing the same four files from +opposite directions and agreeing. Neither artefact is self-validating, and a +manifest written after the fact looks identical to one written before. + ## Related See `SYNCHRONISATION_IS_NOT_VISIBILITY.md` for the other pattern from the same From d87e9cdc9277f424ae5f696022a5de83ac7ad834 Mon Sep 17 00:00:00 2001 From: Zexin Fu Date: Tue, 8 Sep 2026 04:41:03 +0200 Subject: [PATCH 12/48] notes: an assertion that can outlive its condition must carry its own falsifier --- reports/design_notes/PROVENANCE_THE_TOOL_NOT_THE_CONFIG.md | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/reports/design_notes/PROVENANCE_THE_TOOL_NOT_THE_CONFIG.md b/reports/design_notes/PROVENANCE_THE_TOOL_NOT_THE_CONFIG.md index a709bd1..978fc09 100644 --- a/reports/design_notes/PROVENANCE_THE_TOOL_NOT_THE_CONFIG.md +++ b/reports/design_notes/PROVENANCE_THE_TOOL_NOT_THE_CONFIG.md @@ -75,6 +75,13 @@ in that directory (`DIRTY_zexin_timing_f1cbe54` above) is *untracked*, so a `git checkout` reverts the `.sv` files and **leaves the marker standing**. The marker then asserts "dirty" over pristine sources: worse than no marker. +**The general rule:** *an assertion that can outlive the condition it asserts +must carry the means to falsify itself.* A marker file cannot detect a revert, +but it can refuse to be believed without a check that would โ€” so it should open +by telling the reader not to trust it, name the check, and point at an +authoritative copy outside the tree. That is weaker than a tripwire, and it is +what is available inside a directory another tool owns. + **Do:** keep the provenance record *outside* the tool-owned tree (here, `reports/rtl_reference_2026-09-08/dut_tripwire.sha256`), and sample it *during* a long run, not only at the end โ€” detection after the fact costs a From f95e47deede331f7d27e576c8321cac3525189cd Mon Sep 17 00:00:00 2001 From: Zexin Fu Date: Tue, 8 Sep 2026 05:40:44 +0200 Subject: [PATCH 13/48] rlc: read the participation-mask register back instead of echoing what we wrote The guard printed a software copy of the intended mask, so it reported a healthy line on a run whose mask write landed on an address the platform decodes as something else. A check that cannot fail is worth nothing. Now reads the register and prints wrote/readback plus MASK-OK or a mismatch pointing at the peripheral map. --- .../kernel/rlc_ul_drv.c | 36 +++++++++++++++---- 1 file changed, 30 insertions(+), 6 deletions(-) diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_ul_drv.c b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_ul_drv.c index b4f0f2d..f226952 100644 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_ul_drv.c +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_ul_drv.c @@ -152,6 +152,8 @@ static uint32_t rlc_ul_cyc_build, rlc_ul_cyc_scan, rlc_ul_cyc_deliver; static _Atomic uint32_t rlc_ul_barrier_armed __attribute__((aligned(CACHE_LINE_SIZE))) __attribute__((section(".data"))); static _Atomic uint32_t rlc_ul_tile_mask __attribute__((section(".data"))); +/* What the participation-mask register reads back as, after we wrote it. */ +static _Atomic uint32_t rlc_ul_mask_readback __attribute__((section(".data"))); void rlc_ul_init(void) { /* Step 1 of the partial-barrier API: programme which tiles take part. Must @@ -168,6 +170,18 @@ void rlc_ul_init(void) { if (t < 32u) tm_lo |= 1u << t; else tm_hi |= 1u << (t - 32u); } snrt_barrier_set_tile_mask(tm_lo, tm_hi); + /* Read the register back and keep what it actually holds, not what we + meant to write. An earlier version printed the software copy, which made + the guard unable to fail: a run whose mask write landed on an address + the platform decodes as something else still reported a healthy mask. + A check that cannot fail is worth nothing -- this one now catches a + wrong peripheral offset, which is exactly how it was first fooled. */ + { + volatile uint32_t *reg = (volatile uint32_t *) + _snrt_barrier_participation_mask_reg_ptr(); + asm volatile("fence" ::: "memory"); + atomic_store_explicit(&rlc_ul_mask_readback, reg[0], memory_order_relaxed); + } atomic_store_explicit(&rlc_ul_tile_mask, tm_lo, memory_order_relaxed); /* Release, then fence: the consumers read this without holding any lock, and main.c's snrt_cluster_hw_barrier() right after rlc_init() does not @@ -302,12 +316,22 @@ static void rlc_ul_report(void) { const rlc_ul_entity_t *e = &rlc_ul_ent[0]; const uint32_t want = (uint32_t)RLC_UL_SDUS * RLC_UL_SDU_BYTES; printf_lock_acquire(&printf_lock); - printf("[UL] barrier tile_mask=0x%x local_mask=0x%x armed=%u\n", - (uint32_t)atomic_load_explicit(&rlc_ul_tile_mask, memory_order_relaxed), - snrt_cluster_partial_barrier_mask(consumer_core_ids, - RLC_ACTUAL_CONSUMERS), - (uint32_t)atomic_load_explicit(&rlc_ul_barrier_armed, - memory_order_relaxed)); + { + const uint32_t wrote = + (uint32_t)atomic_load_explicit(&rlc_ul_tile_mask, memory_order_relaxed); + const uint32_t got = + (uint32_t)atomic_load_explicit(&rlc_ul_mask_readback, memory_order_relaxed); + printf("[UL] barrier tile_mask wrote=0x%x readback=0x%x local_mask=0x%x " + "armed=%u %s\n", + wrote, got, + snrt_cluster_partial_barrier_mask(consumer_core_ids, + RLC_ACTUAL_CONSUMERS), + (uint32_t)atomic_load_explicit(&rlc_ul_barrier_armed, + memory_order_relaxed), + (wrote == got) ? "MASK-OK" : "*** MASK MISMATCH: the participation " + "register is not where we wrote it -- " + "check the peripheral map ***"); + } printf("[UL] slots=%u tb_bytes=%u segments=%u polls_ack=%u exec=%s\n", rlc_ul_slots, rlc_ul_tb_bytes, e->reassembled, rlc_ul_status_pdus, (RLC_UL_EXEC == RLC_UL_EXEC_COPY) ? "copy" : "count"); From 4c3d799d0faab036867ed59b8131915b7ea0da2a Mon Sep 17 00:00:00 2001 From: Zexin Fu Date: Tue, 8 Sep 2026 05:53:15 +0200 Subject: [PATCH 14/48] notes: RLC partial-barrier design is wrong at more than one tile Two defects. The cluster mask is persistent and gates every barrier including full ones, and is never restored. And the tile barrier lets whichever request arrives first define the round, so non-participants parked at the full barrier in the same tile corrupt the participants' rounds. Neither has run on correct barrier hardware. --- .../design_notes/PARTIAL_BARRIER_MISUSE.md | 97 +++++++++++++++++++ 1 file changed, 97 insertions(+) create mode 100644 reports/design_notes/PARTIAL_BARRIER_MISUSE.md diff --git a/reports/design_notes/PARTIAL_BARRIER_MISUSE.md b/reports/design_notes/PARTIAL_BARRIER_MISUSE.md new file mode 100644 index 0000000..81e9cd4 --- /dev/null +++ b/reports/design_notes/PARTIAL_BARRIER_MISUSE.md @@ -0,0 +1,97 @@ +# The RLC partial-barrier design is wrong at more than one tile + +**2026-09-08.** Found by the GVSoC session after they implemented real +participation-mask semantics. Two independent defects, both mine, both +invisible in every configuration I have tested. + +## Defect 1 โ€” the cluster mask is programmed and never restored + +`cachepool_cluster_barrier.sv`: + +```systemverilog +Idle: if (|(tile_barrier_i & barrier_mask_i)) begin + mask_d = barrier_mask_i; // re-read from the REGISTER every round +assign all_arrived = (tile_barrier_i & mask_q) == mask_q; +``` + +**There is no full-versus-partial distinction at the cluster level.** The +read/write distinction exists only in the *tile* barrier, for the per-core +mask. The cluster mask is persistent and gates every round. + +`rlc_ul_init()` and `rlc_am_init()` set it to "tile 0 only" from `rlc_init()` +and never restore it. From that point **every `snrt_cluster_hw_barrier()` in +the program waits only for tile 0** โ€” including `main.c`'s startup resync and +the final barrier before the report. At 64 cores the other 60 sail through +unsynchronised. + +## Defect 2 โ€” participants and non-participants share a tile + +`cachepool_tile_barrier.sv`: + +```systemverilog +req_mask[i] = in_req_i[i].q.write ? in_req_i[i].q.data[NrPorts-1:0] + : {NrPorts{1'b1}}; // a READ means "all" +MaskIdle: if (|barrier_hit) begin + core_mask_d = req_mask[first_hit_idx]; // FIRST arrival owns the round +``` + +**Whichever request arrives first defines the round's participant set.** In +`cluster_entry()` the non-participating cores โ€” idle ones, and producers once +they finish โ€” go to `snrt_cluster_hw_barrier()`, a *read*, meaning "all cores +in this tile". Consumers in the same tile are meanwhile issuing partial-barrier +*writes*. + +So a consumer's partial barrier can be absorbed into an all-cores round (and +then blocks until every core in the tile arrives), or an idle core's full +barrier can be absorbed into a consumers-only round (and released early). +**Mixing the two inside one tile is unsafe by construction.** + +This one is not even multi-tile-specific: at 4 cores with P1/C1, cores 2 and 3 +are idle and parked at the full barrier while core 1 runs partial barriers. + +## Why nothing caught either + +- **Defect 1 is a no-op at one tile.** Every RLC run puts producers and + consumers in tile 0, where the mask is `0x1` โ€” the only tile. +- **Defect 2 has never run on correct barrier hardware.** GVSoC's barrier was + a global counter to `nb_cores` until today โ€” no masks at all โ€” so the model + could not expose it, and the partial-barrier TTI path has not been run on + RTL. + +The pattern from the other notes repeats: **a test passing is not evidence the +mechanism works, when the platform never implemented the mechanism.** + +## The API contradiction underneath + +`snrt.h` says to program the mask and then "use `snrt_cluster_hw_barrier()` as +a resync point before relying on it". But the narrowing is already in force by +then, so that resync barrier is itself masked and does not wait for everyone. +**The documented usage cannot work at more than one tile.** A fix has to +restructure the arm/resync sequence, not just add a restore. + +## Proposed fix (not yet implemented) + +1. **Do not program the mask in `rlc_init()`** โ€” that precedes `main.c`'s + startup full barrier, which the narrowing would break. +2. **Arm inside the consumer entry**: consumer 0 programs the mask; the other + consumers wait on an `_Atomic` release/acquire flag plus a fence, *not* on a + barrier โ€” they cannot use the barrier they are about to narrow. +3. **Keep non-participants out of the barrier entirely** while partial barriers + are in use: idle cores and finished producers spin on a "consumers done" + flag instead of entering `snrt_cluster_hw_barrier()`. +4. **Restore the mask to all-ones** (its `RESVAL`) after the TTI loop, before + setting that flag, so the final full barrier is a real full barrier. + +Costs one flag and one spin per non-participant, and removes the mixed-mode +round entirely. + +## Verification plan + +GVSoC can run a candidate at 4 and 16 tiles in minutes โ€” that is where the +difference appears, and their model now reproduces the contradiction faithfully +rather than hiding it. Cheaper than RTL for the first pass; RTL confirms after. + +## Related + +`SYNCHRONISATION_IS_NOT_VISIBILITY.md` โ€” the barriers do not fence. +`PROVENANCE_THE_TOOL_NOT_THE_CONFIG.md` โ€” measure the artefact, not the config. From ec993e99e56cd499d37015b823d1bee1179d4e3b Mon Sep 17 00:00:00 2001 From: Zexin Fu Date: Tue, 8 Sep 2026 05:56:56 +0200 Subject: [PATCH 15/48] notes: barrier done is broadcast cluster-wide, so the mask gates arrival not release Any partial-barrier completion releases every core waiting at a barrier anywhere in the cluster. That rules out moving non-participants to another tile, and makes the software spin forced rather than chosen. --- .../design_notes/PARTIAL_BARRIER_MISUSE.md | 34 ++++++++++++++++++- 1 file changed, 33 insertions(+), 1 deletion(-) diff --git a/reports/design_notes/PARTIAL_BARRIER_MISUSE.md b/reports/design_notes/PARTIAL_BARRIER_MISUSE.md index 81e9cd4..ecf353d 100644 --- a/reports/design_notes/PARTIAL_BARRIER_MISUSE.md +++ b/reports/design_notes/PARTIAL_BARRIER_MISUSE.md @@ -61,6 +61,32 @@ are idle and parked at the full barrier while core 1 runs partial barriers. The pattern from the other notes repeats: **a test passing is not evidence the mechanism works, when the platform never implemented the mechanism.** +## Defect 3 โ€” the mask restricts who must ARRIVE, not who gets RELEASED + +`cachepool_cluster_barrier.sv` has a single `barrier_done_o`, and every tile's +cores release on it unconditionally: + +```systemverilog +// cachepool_tile_barrier.sv +Global: if (barrier_done_i) state_d[i] = Take; // no mask check +``` + +**So any partial-barrier round's completion releases every core waiting at a +barrier anywhere in the cluster.** `barrier_mask_i` gates the *arrival* +condition (`all_arrived = (tile_barrier_i & mask_q) == mask_q`) and nothing +gates the broadcast. + +The consequence is stronger than defects 1 and 2, and it constrains any fix: + +> **A partial barrier is only safe when no core outside the participating set +> is waiting at a barrier at the same time โ€” anywhere in the cluster, not just +> in the same tile.** + +This kills the obvious workaround for defect 2 (move non-participants to other +tiles): they would be released by the participants' first partial barrier +round. It means the software spin in step 3 below is not a design preference, +it is the only option the hardware leaves. + ## The API contradiction underneath `snrt.h` says to program the mask and then "use `snrt_cluster_hw_barrier()` as @@ -78,7 +104,13 @@ restructure the arm/resync sequence, not just add a restore. barrier โ€” they cannot use the barrier they are about to narrow. 3. **Keep non-participants out of the barrier entirely** while partial barriers are in use: idle cores and finished producers spin on a "consumers done" - flag instead of entering `snrt_cluster_hw_barrier()`. + flag instead of entering `snrt_cluster_hw_barrier()`. **Forced by defect 3**, + not chosen โ€” moving them to another tile does not help, because the done + signal is broadcast cluster-wide. The flag needs `_Atomic` release/acquire + plus a fence (same treatment as `rlc_ul_barrier_armed`), and a back-off + between polls so it does not reintroduce the traffic the TTI loop exists to + remove. Note the *participants* still block on a real barrier โ€” only cores + with no work spin, and they had nothing else to do. 4. **Restore the mask to all-ones** (its `RESVAL`) after the TTI loop, before setting that flag, so the final full barrier is a real full barrier. From 604c7cfa75d742a881f639a89fa147909b5ff175 Mon Sep 17 00:00:00 2001 From: Zexin Fu Date: Tue, 8 Sep 2026 06:01:30 +0200 Subject: [PATCH 16/48] notes: record the refuted workaround for defect 2 explicitly --- .../design_notes/PARTIAL_BARRIER_MISUSE.md | 21 +++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/reports/design_notes/PARTIAL_BARRIER_MISUSE.md b/reports/design_notes/PARTIAL_BARRIER_MISUSE.md index ecf353d..e0e1a4e 100644 --- a/reports/design_notes/PARTIAL_BARRIER_MISUSE.md +++ b/reports/design_notes/PARTIAL_BARRIER_MISUSE.md @@ -82,10 +82,23 @@ The consequence is stronger than defects 1 and 2, and it constrains any fix: > is waiting at a barrier at the same time โ€” anywhere in the cluster, not just > in the same tile.** -This kills the obvious workaround for defect 2 (move non-participants to other -tiles): they would be released by the participants' first partial barrier -round. It means the software spin in step 3 below is not a design preference, -it is the only option the hardware leaves. +### Refuted: "move the non-participants to another tile" + +This is the obvious fix for defect 2 and it does not work. Recorded here so the +next person does not spend the same hour on it. + +The idea: if only consumers occupy the consumer tile, no read-barrier and +write-barrier ever share a tile, so defect 2 disappears โ€” and non-participants +in other tiles are outside the cluster mask, so they cannot satisfy the arrival +condition either. + +Why it fails: **they do not need to satisfy the arrival condition to be +released.** `barrier_done_o` is broadcast, and a core in `Global` takes it +whatever tile it is in. So the participants' first partial-barrier round frees +every non-participant that has reached its own tile barrier, cluster-wide. + +It means the software spin in step 3 below is not a design preference, it is +the only construct the hardware leaves. ## The API contradiction underneath From 86904f75ff66f41921455fd10dcb44aab249d249 Mon Sep 17 00:00:00 2001 From: Zexin Fu Date: Tue, 8 Sep 2026 06:04:42 +0200 Subject: [PATCH 17/48] notes: the mechanism was checking claims against artefacts, not descriptions --- .../PROVENANCE_THE_TOOL_NOT_THE_CONFIG.md | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/reports/design_notes/PROVENANCE_THE_TOOL_NOT_THE_CONFIG.md b/reports/design_notes/PROVENANCE_THE_TOOL_NOT_THE_CONFIG.md index 978fc09..26184f6 100644 --- a/reports/design_notes/PROVENANCE_THE_TOOL_NOT_THE_CONFIG.md +++ b/reports/design_notes/PROVENANCE_THE_TOOL_NOT_THE_CONFIG.md @@ -127,3 +127,27 @@ manifest written after the fact looks identical to one written before. See `SYNCHRONISATION_IS_NOT_VISIBILITY.md` for the other pattern from the same night: a primitive whose name promises more than it delivers. + +## The mechanism, stated plainly + +Across a night of two sessions checking each other, every real finding came from +one move and every failure from its opposite: + +| finding | what settled it | +|---|---| +| the tile mask is never programmed in UL builds | disassembly, not the source | +| "3 call sites" for `snrt_barrier_set_tile_mask` | they were source comments; resolved `auipc`+`jalr` targets settled it | +| which RTL tree the batch compiled | the generated `compile.vsim.tcl`, not `Bender.local` | +| which peripheral map an ELF uses | `set_eoc`'s immediate, not the header | +| whether a run succeeded | the `[EOC]` line, not plausible output | +| whether a register is the mask | its `RESVAL` signature, not that the address accepts a write | +| whether a peer's map claim held | the model's decode path, not its variables | + +**The useful mechanism was not either party being right. It was each checking +the other's claim against an artefact rather than against a description.** Both +sides' errors came from the reverse: reading intent out of a name, a header, a +config file, or a partial output. + +Corollary worth keeping: a check that cannot fail is not a check. A guard that +echoed the value it had just written reported healthy on a run where the write +went to the wrong address entirely. From 753b9ec614ab0399447f083ba1720a16ad248f20 Mon Sep 17 00:00:00 2001 From: Zexin Fu Date: Tue, 8 Sep 2026 06:17:04 +0200 Subject: [PATCH 18/48] reports: RTL reference batch 2026-09-08 -- cycle-identity established on two kernels --- reports/rtl_reference_2026-09-08/RESULTS.md | 94 +++++++++++++ reports/rtl_reference_2026-09-08/RTL_STATE.md | 53 +++++++ .../rtl_reference_2026-09-08/build_report.sh | 41 ++++++ .../dut_tripwire.sha256 | 31 ++++ .../rtl_reference_2026-09-08/dut_watch.log | 132 ++++++++++++++++++ .../elf_under_test/MANIFEST.md5 | 5 + reports/rtl_reference_2026-09-08/summary.tsv | 6 + .../rtl_reference_2026-09-08/verify_dut.sh | 14 ++ 8 files changed, 376 insertions(+) create mode 100644 reports/rtl_reference_2026-09-08/RESULTS.md create mode 100644 reports/rtl_reference_2026-09-08/RTL_STATE.md create mode 100755 reports/rtl_reference_2026-09-08/build_report.sh create mode 100644 reports/rtl_reference_2026-09-08/dut_tripwire.sha256 create mode 100644 reports/rtl_reference_2026-09-08/dut_watch.log create mode 100644 reports/rtl_reference_2026-09-08/elf_under_test/MANIFEST.md5 create mode 100644 reports/rtl_reference_2026-09-08/summary.tsv create mode 100755 reports/rtl_reference_2026-09-08/verify_dut.sh diff --git a/reports/rtl_reference_2026-09-08/RESULTS.md b/reports/rtl_reference_2026-09-08/RESULTS.md new file mode 100644 index 0000000..9e073e2 --- /dev/null +++ b/reports/rtl_reference_2026-09-08/RESULTS.md @@ -0,0 +1,94 @@ +# RTL reference batch โ€” 2026-09-08 + +Config `cachepool_fpu_4g` (4 groups x 4 tiles x 4 cores = 64), QuestaSim. +Requested by the L1-timing session to check whether 15 cache rewrites are +cycle-identical. Run on their working tree; provenance pinned (see below). + +| kernel | status | EOC (cyc) | kernel cyc | 08-25 pristine | verdict | +|---|---|---|---|---|---| +| `bandwidth` | **PASS** | 33,876 | 2,058 (32/load) | 33,876 / 2,058 / 32 | **exact match** | +| `byte-enable` | **PASS** | 303,288 | n/a | 303,288 | **exact match** | +| `cache-mix-smoke` | **FAIL** | 69,378 | 125 mismatches | no baseline | test bug, not RTL | +| `cache-test-scalar` | `timeout_cap` | โ€” | `cache-basic` **PASS** | no baseline | partial | +| `cache-test-vector` | `timeout_cap` | โ€” | `vcache-basic` **PASS** | no baseline | partial | + +128 scoreboards PASS / 0 FAIL on all three that reached EOC. Zero illegal +instructions anywhere โ€” so no scalar-FP traps in this set. + +## Cycle-identity: established + +`bandwidth` and `byte-enable` both reproduce the 2026-08-25 pristine reference +**bit-identically**, against references taken two weeks before the rewrites +landed. Per-channel AR/R also match (CH0 159/182, CH1 8/9, CH2 4/4, CH3 164/227), +so refill traffic is identical in count *and* distribution. + +**EOC is the stronger figure than kernel cycles** (the peer's point): kernel +cycles cover the hot loop, EOC covers boot, snRuntime init, barriers, teardown +and all 64 cores. Nothing anywhere in either run shifted by a cycle. + +**Consequence:** if the RLC multi-entity wedge depends on write-visibility +*timing*, the L1D rewrites are excluded as a confound โ€” the cache presents +writes on identical cycles before and after. + +## `cache-mix-smoke` โ€” a test bug, attributable without a pristine arm + +```c +vec_store_u32(base + part_ofst); // vse32.v -> Spatz's LSU +for (j...) if (*(volatile uint32_t*)(base + part_ofst + j*4) != vec_vals[j]) errs++; + // scalar load -> Snitch's LSU +``` + +Independent LSUs, no `fence` between them; `fences: 0` in that file. `volatile` +constrains the compiler and says nothing about two hardware load/store units. +Predates the rewrites and is independent of the cache datapath. + +**Caveat recorded at the peer's insistence:** adding a fence would fix this +whether or not the rewrites perturbed the timing that exposes it, so the fence +experiment alone cannot separate "always racy" from "rewrites changed the +exposure". Their pristine arm settles it; this row is not evidence about their +RTL either way. + +## The two capped tests, and the part that is still informative + +Both hit the 1 h per-test cap during their `*-stress` phase. Both had already +**passed their `*-basic` phase**, which is the interesting half: + +> `cache-basic` and `vcache-basic` are unfenced cross-core write / barrier / +> read tests โ€” `fences: 0, volatile: 0, atomics: 0, 14 bare hw barriers` โ€” and +> **they pass on RTL**, while the same source fails on GVSoC at 48-84 % density. + +Same binary, passes on hardware, fails on the model. The hazard is real and in +the source; hardware's store-visibility window is narrow enough to hide it. +**Passing on RTL is not evidence this class of bug is absent.** + +Caveat added after the fact: the GVSoC arm ran under a global counting barrier +that has since been replaced, so that comparison needs re-measuring before it +is leaned on. Flagged by the GVSoC session, accepted here. + +## Provenance + +- DUT is `hardware/deps/insitu-cache` โ€” **grepped from the generated + `compile.vsim.tcl`**, not inferred from `Bender.local`, whose override never + applied (see `design_notes/PROVENANCE_THE_TOOL_NOT_THE_CONFIG.md`). +- `dut_tripwire.sha256` pins the compile script + all 30 insitu sources. + `dut_watch.sh` sampled it every 45 s: **130 samples, 0 changes.** +- `elf_under_test/` holds the exact test binaries used, frozen `chmod a-w` with + a manifest, verified by the peer against live `software/build` *before* any + rebuild โ€” which is what makes the freeze evidence rather than a claim. +- The four modified cache sources under test: + `b23ed202 / 2bf77815 / 5307c217 / f0629785`, independently confirmed by the + peer from a marker written before this batch was pinned. + +## Wallclock + +| kernel | wall | +|---|---| +| `bandwidth` | 598 s | +| `byte-enable` | 889 s | +| `cache-mix-smoke` | 236 s | +| `cache-test-scalar` | capped at 3600 s | +| `cache-test-vector` | capped at 3600 s | + +I predicted `byte-enable` would cap by extrapolating linearly from +`bandwidth`'s cycles-per-second. It took 15 minutes, not 90. **Wall time is not +linear in EOC cycles across kernels** โ€” different core counts and DRAM traffic. diff --git a/reports/rtl_reference_2026-09-08/RTL_STATE.md b/reports/rtl_reference_2026-09-08/RTL_STATE.md new file mode 100644 index 0000000..797f573 --- /dev/null +++ b/reports/rtl_reference_2026-09-08/RTL_STATE.md @@ -0,0 +1,53 @@ +# RTL state under test โ€” batch 2026-09-08 + +**RESOLVED PATH, grepped from the compile script โ€” not inferred from Bender.local.** + +`Bender.local` does override insitu-cache to `working_dir/insitu-cache`, and I +originally wrote that the batch therefore compiles that working copy. **That was +wrong.** `sim/work/compile.vsim.tcl` (mtime 2026-08-24 23:18, NOT regenerated) +resolves to `hardware/deps/insitu-cache`, and that is what vlog reads: + +``` +"$ROOT/./hardware/deps/insitu-cache/src/insitu_cache/insitu_cache_core.sv" +``` + +`compile.vsim.tcl` is a make target whose prerequisites are rtl_lib.cc, +common_lib.cc, bootdata.cc and bootrom.bin โ€” **RTL sources are not among them**, +so `make vsim` does not re-run bender and the Aug-24 script stands. + +The results are still valid, verified rather than assumed: the two trees are +byte-identical (`cmp` on all four modified files) and produce the same +diff-vs-HEAD hash `f6657ec2ac4eda12`. Only the path was wrong, not the DUT. + +**Hazard for future readers:** if anything touches a prerequisite of +compile.vsim.tcl mid-batch, make re-runs bender, the override takes effect, and +the source path switches trees silently โ€” a no-op only while the trees match. +`dut_tripwire.sha256` pins the compile script and every insitu source it names; +`verify_dut.sh` re-checks it after the batch. + +## IP git state +``` +f1cbe54 [Verif] Waive check for store requsets since Spatz do not need order in this case + +M src/insitu_cache/insitu_cache_core.sv +M src/insitu_cache/insitu_cache_encoder.sv +M src/insitu_cache/insitu_cache_tcdm_wrapper.sv +M src/utilities/sram_forwarding_buffer.sv + +diff vs HEAD: 1275 lines, sha256 f6657ec2ac4eda12 +``` + +## Modified file mtimes (all predate the vsim compile at ~03:44) +``` +2026-09-07 23:25 src/insitu_cache/insitu_cache_encoder.sv +2026-09-08 00:24 src/insitu_cache/insitu_cache_core.sv +2026-09-08 01:56 src/insitu_cache/insitu_cache_tcdm_wrapper.sv +2026-09-08 02:04 src/utilities/sram_forwarding_buffer.sv +``` + +## Attribution +- HEAD `f1cbe54` is the pristine baseline; the 4 modified files are the timing rewrites. +- `bandwidth` has a known-good pristine reference from 2026-08-25 (2,058 kernel cyc / 32 cyc-per-load), + so a deviation there is attributable to these rewrites. +- `cache-test-scalar` / `cache-test-vector` have NO pristine arm in this batch and may trap for an + unrelated reason (scalar-FP offload defect). Single-arm results there are UNATTRIBUTABLE โ€” informational only. diff --git a/reports/rtl_reference_2026-09-08/build_report.sh b/reports/rtl_reference_2026-09-08/build_report.sh new file mode 100755 index 0000000..7ec7c5d --- /dev/null +++ b/reports/rtl_reference_2026-09-08/build_report.sh @@ -0,0 +1,41 @@ +#!/bin/bash +# Rebuild summary.tsv from the logs. The batch script's inline grep looked for +# "Simulation ended at N" but the actual print is "[EOC] Simulation ended at +# N (retval = 0)" in picoseconds -- so it recorded n/a for a run that +# had the number. Parse the logs instead of trusting that grep. +cd /usr/scratch/fenga1/zexifu/manyRVData/ManyRVData_rebase +OUT=reports/rtl_reference_2026-09-08 +printf "kernel\tstatus\teoc_cyc\tretval\tkernel_cyc\tper_load\tsb_pass\tsb_fail\tillegal\n" > $OUT/summary.tsv +for t in bandwidth byte-enable cache-mix-smoke cache-test-scalar cache-test-vector; do + L=$OUT/logs/$t.log + [ -f "$L" ] || { printf "%s\tnot_run\t-\t-\t-\t-\t-\t-\t-\n" "$t" >> $OUT/summary.tsv; continue; } + eocps=$(grep -oE "Simulation ended at +[0-9]+" "$L" | grep -oE "[0-9]+$" | tail -1) + eoc=$([ -n "$eocps" ] && echo $((eocps/1000)) || echo "-") + ret=$(grep -oE "retval = [0-9-]+" "$L" | grep -oE "[0-9-]+$" | tail -1) + kc=$(grep -oE "Total cycles: [0-9]+" "$L" | grep -oE "[0-9]+$" | tail -1) + pl=$(grep -oE "avg per load: [0-9]+" "$L" | grep -oE "[0-9]+$" | tail -1) + sp=$(grep -c "STATUS: PASS" "$L"); sf=$(grep -c "STATUS: FAIL" "$L") + ill=$(grep -ciE "illegal instruction" "$L") + if [ -n "$eocps" ] && [ "$ret" = "0" ] && [ "$sf" = "0" ]; then st=PASS + elif [ -n "$eocps" ] && [ "$sf" != "0" ]; then st=sb_violation + elif [ -n "$eocps" ]; then st=eoc_nonzero_retval + elif [ "$ill" != "0" ]; then st=TRAP + else + # No EOC yet. Three different things, and calling them all timeout_cap is + # the kind of misleading row this script exists to avoid: + # running -- vsim alive and this is the newest log + # crash -- stopped early with an error + # timeout_cap -- neither; it was killed by the wallclock cap + newest=$(ls -t $OUT/logs/*.log 2>/dev/null | head -1) + if pgrep -f "vsimk.*ManyRVData_rebase" >/dev/null 2>&1 && [ "$newest" = "$L" ]; then + st=running + elif grep -qiE "fatal|error:|\\*\\* Error" "$L"; then st=crash + else st=timeout_cap; fi + fi + # Keep the last kernel-printed line: a capped run still carries real results + # (sub-tests that completed), and losing them to a bare timeout_cap row throws + # away the informative half of the run. + lu=$(grep "\[UART\]" "$L" | tail -1 | sed 's/.*\[UART\] *//' | cut -c1-46) + printf "%s\t%s\t%s\t%s\t%s\t%s\t%s\t%s\t%s\t%s\n" "$t" "$st" "$eoc" "${ret:--}" "${kc:--}" "${pl:--}" "$sp" "$sf" "$ill" "${lu:--}" >> $OUT/summary.tsv +done +column -t -s$'\t' $OUT/summary.tsv diff --git a/reports/rtl_reference_2026-09-08/dut_tripwire.sha256 b/reports/rtl_reference_2026-09-08/dut_tripwire.sha256 new file mode 100644 index 0000000..fe8b4e3 --- /dev/null +++ b/reports/rtl_reference_2026-09-08/dut_tripwire.sha256 @@ -0,0 +1,31 @@ +1203a1440956ab6fcf8c3f8976e89edd649428416ac448d82b8c13437875ceea sim/work/compile.vsim.tcl +d4cf9be82f9770ec17e56bbbf8a82e2cecfbd5b04f02bbb495e561ac837faa2a hardware/deps/insitu-cache/src/cachepool/cachepool_cache_ctrl.sv +cbf220f4643f89dfd484db6e2ee6da772ec8d6581d2a6df5a2a69ba2730b251d hardware/deps/insitu-cache/src/coalesce_unit/par_coalescer/non_coalescer.sv +2b19d084db209bc077c16d3fb5463f1f0041625f833dbd7512a15b06ef579158 hardware/deps/insitu-cache/src/coalesce_unit/par_coalescer/par_coalescer_equal_window.sv +24209b3aeb73769efe59ba5527afd9db2abb024573a66d7eb0c34fc703ab19cd hardware/deps/insitu-cache/src/coalesce_unit/par_coalescer/par_coalescer_extend_window.sv +ba81e0acf3ad966d72024709e02253642c76bb0dfaad99b114f4d1985432bc7b hardware/deps/insitu-cache/src/coalesce_unit/par_coalescer/par_coalescer_top.sv +0b316eeba6ca5dec17f9f5fe9fec15e235fde0794911de7c67a3e62125ca303b hardware/deps/insitu-cache/src/coalesce_unit/par_coalescer/req_coalescer_v2.sv +52905bb68feaee386b1abd2e6efcd08a83a567054df8a95dd957b7884ea7f150 hardware/deps/insitu-cache/src/coalesce_unit/par_coalescer/rsp_spliter_v2.sv +25f6b9e67a54f6bcd0af21bcafdac77f077cfebc419bfcb581ed6a9228f91214 hardware/deps/insitu-cache/src/coalesce_unit/seq_coalescer/seq_coalescer_multi_req_merger.sv +c207ed7ac50d2af303ff7e955fe522ee080183e41e3ec6f8d55a2006cc00c6dc hardware/deps/insitu-cache/src/coalesce_unit/seq_coalescer/seq_coalescer_req_merger.sv +e0df79c260f134531b11c8b6a8d47390283b89dd83cb97fd8355fc8a5ef86f03 hardware/deps/insitu-cache/src/coalesce_unit/seq_coalescer/seq_coalescer_top.sv +4e301e4cf36faf5b5c45364a9d1a19a277ab77ece85b044155dd9f2f47a2c52d hardware/deps/insitu-cache/src/coalesce_unit/wirte_merger/write_through_merger.sv +17bdf4e7d28110ddf6e3d2847001aa63b2ef24be634b481c4492bbd56ecf3ecb hardware/deps/insitu-cache/src/flamingo/flamingo_spatz_cache_ctrl.sv +b23ed2027fa1dc75c6e5dfaf8c745af35e38d74270220930ff03d4a87e454431 hardware/deps/insitu-cache/src/insitu_cache/insitu_cache_core.sv +61f7202ccf3cefbfaf439af682530f397b83db7e88d30ee8bc1d3f0f34ecaefe hardware/deps/insitu-cache/src/insitu_cache/insitu_cache_decoder.sv +2bf77815139b3838a4ed8ec7fee1c1796cfe64ee7a0201c89f7ad8deaa730bce hardware/deps/insitu-cache/src/insitu_cache/insitu_cache_encoder.sv +92b4b3840476d2bf4b0fe7bda1b8043fb0ce50a0461597fc8f1b8c20fd1330ca hardware/deps/insitu-cache/src/insitu_cache/insitu_cache_pkg.sv +c1b3b6a1d11e33bfad18cbf4cf85adf8183f90a9f45ff0c0c3c1eafb0b682488 hardware/deps/insitu-cache/src/insitu_cache/insitu_cache_tcdm_wrapper_partitionable_flushable.sv +5307c2177b04cfa3adce2b81146d8bcee4e53abd89d0555a613c0cec776a4ede hardware/deps/insitu-cache/src/insitu_cache/insitu_cache_tcdm_wrapper.sv +87101497eb0373f51cea90bb7e75832697c815b84d25932cb08170ff23460332 hardware/deps/insitu-cache/src/insitu_cache/insitu_cache_top.sv +eade4dd67b94611c3bfc3a992a7cb344204f6a09776e666d6bb8715a753c5bd4 hardware/deps/insitu-cache/src/utilities/cache_to_axi.sv +044c99c7088ab422b04865417abc3404d335f2cf151d502fe76dc98e11e9cd46 hardware/deps/insitu-cache/src/utilities/decouple_channels_adapter.sv +38439025cf5ccbb4a22b6601abe5db1c20b2bbf2c69b238fe554dc1710d8b8c5 hardware/deps/insitu-cache/src/utilities/decouple_queue_sync.sv +014f5da3cf6eeb3ac0a29e695bf2da655fdb4a11a503d4b86e99cdaf50d05638 hardware/deps/insitu-cache/src/utilities/folded_data_bank.sv +8f3d6864a6c2bee129fa743d1d1e9c7e0fbf1e856021be898ba2b8fb3c45361c hardware/deps/insitu-cache/src/utilities/id_buffer.sv +9eca29b1797d0aa5d8e78a1e8d84fb1efe762d0a46309576a8280910f2218b74 hardware/deps/insitu-cache/src/utilities/pseudo_dual_port_bank.sv +d6c46cd92c945c8525d95c40ebe06507a0fe0d84915db95721e625993387884d hardware/deps/insitu-cache/src/utilities/pseudo_dual_port_fifo.sv +6cda5a806f5948c233dd9ad5311808d8a92fb401b525f1a0899c5238c705ca13 hardware/deps/insitu-cache/src/utilities/pseudo_dual_port_way.sv +a0a2e42cba0e78deafa37c61bfa973e7401b22970e8a279ef4c2813e289e921e hardware/deps/insitu-cache/src/utilities/sram_forwarding_buffer_multi.sv +f06297858718811bc70455c43c0f0495c34226d45d2ea18fa93db2bec58eccbf hardware/deps/insitu-cache/src/utilities/sram_forwarding_buffer.sv +9107a7d66628fdaaf529d3860a28db91756793e8515cd80e7d8ecda7124cc75e hardware/deps/insitu-cache/src/verif/insitu_cache_scoreboard.sv diff --git a/reports/rtl_reference_2026-09-08/dut_watch.log b/reports/rtl_reference_2026-09-08/dut_watch.log new file mode 100644 index 0000000..8d58304 --- /dev/null +++ b/reports/rtl_reference_2026-09-08/dut_watch.log @@ -0,0 +1,132 @@ +04:39:19 watch start +04:39:19 OK 4 logs +04:40:04 OK 4 logs +04:40:50 OK 4 logs +04:41:35 OK 4 logs +04:42:20 OK 4 logs +04:43:05 OK 4 logs +04:43:50 OK 4 logs +04:44:35 OK 4 logs +04:45:20 OK 4 logs +04:46:05 OK 4 logs +04:46:50 OK 4 logs +04:47:35 OK 4 logs +04:48:20 OK 4 logs +04:49:05 OK 4 logs +04:49:50 OK 4 logs +04:50:36 OK 4 logs +04:51:21 OK 4 logs +04:52:06 OK 4 logs +04:52:51 OK 4 logs +04:53:36 OK 4 logs +04:54:21 OK 4 logs +04:55:06 OK 4 logs +04:55:51 OK 4 logs +04:56:36 OK 4 logs +04:57:21 OK 4 logs +04:58:06 OK 4 logs +04:58:51 OK 4 logs +04:59:36 OK 4 logs +05:00:22 OK 4 logs +05:01:07 OK 4 logs +05:01:52 OK 4 logs +05:02:37 OK 4 logs +05:03:22 OK 4 logs +05:04:07 OK 4 logs +05:04:52 OK 4 logs +05:05:37 OK 4 logs +05:06:22 OK 4 logs +05:07:07 OK 4 logs +05:07:52 OK 4 logs +05:08:37 OK 4 logs +05:09:22 OK 4 logs +05:10:08 OK 4 logs +05:10:53 OK 4 logs +05:11:38 OK 4 logs +05:12:23 OK 4 logs +05:13:08 OK 4 logs +05:13:53 OK 4 logs +05:14:38 OK 4 logs +05:15:23 OK 4 logs +05:16:08 OK 4 logs +05:16:53 OK 5 logs +05:17:38 OK 5 logs +05:18:23 OK 5 logs +05:19:08 OK 5 logs +05:19:53 OK 5 logs +05:20:39 OK 5 logs +05:21:24 OK 5 logs +05:22:09 OK 5 logs +05:22:54 OK 5 logs +05:23:39 OK 5 logs +05:24:24 OK 5 logs +05:25:09 OK 5 logs +05:25:54 OK 5 logs +05:26:39 OK 5 logs +05:27:24 OK 5 logs +05:28:09 OK 5 logs +05:28:54 OK 5 logs +05:29:39 OK 5 logs +05:30:25 OK 5 logs +05:31:10 OK 5 logs +05:31:55 OK 5 logs +05:32:40 OK 5 logs +05:33:25 OK 5 logs +05:34:10 OK 5 logs +05:34:55 OK 5 logs +05:35:40 OK 5 logs +05:36:25 OK 5 logs +05:37:10 OK 5 logs +05:37:55 OK 5 logs +05:38:40 OK 5 logs +05:39:25 OK 5 logs +05:40:10 OK 5 logs +05:40:56 OK 5 logs +05:41:41 OK 5 logs +05:42:26 OK 5 logs +05:43:11 OK 5 logs +05:43:56 OK 5 logs +05:44:41 OK 5 logs +05:45:26 OK 5 logs +05:46:11 OK 5 logs +05:46:56 OK 5 logs +05:47:41 OK 5 logs +05:48:26 OK 5 logs +05:49:11 OK 5 logs +05:49:56 OK 5 logs +05:50:42 OK 5 logs +05:51:27 OK 5 logs +05:52:12 OK 5 logs +05:52:57 OK 5 logs +05:53:42 OK 5 logs +05:54:27 OK 5 logs +05:55:12 OK 5 logs +05:55:57 OK 5 logs +05:56:42 OK 5 logs +05:57:27 OK 5 logs +05:58:12 OK 5 logs +05:58:57 OK 5 logs +05:59:42 OK 5 logs +06:00:28 OK 5 logs +06:01:13 OK 5 logs +06:01:58 OK 5 logs +06:02:43 OK 5 logs +06:03:28 OK 5 logs +06:04:13 OK 5 logs +06:04:58 OK 5 logs +06:05:43 OK 5 logs +06:06:28 OK 5 logs +06:07:13 OK 5 logs +06:07:58 OK 5 logs +06:08:43 OK 5 logs +06:09:28 OK 5 logs +06:10:14 OK 5 logs +06:10:59 OK 5 logs +06:11:44 OK 5 logs +06:12:29 OK 5 logs +06:13:14 OK 5 logs +06:13:59 OK 5 logs +06:14:44 OK 5 logs +06:15:29 OK 5 logs +06:16:14 OK 5 logs +06:16:59 watch end (no vsim) diff --git a/reports/rtl_reference_2026-09-08/elf_under_test/MANIFEST.md5 b/reports/rtl_reference_2026-09-08/elf_under_test/MANIFEST.md5 new file mode 100644 index 0000000..ae2a5f0 --- /dev/null +++ b/reports/rtl_reference_2026-09-08/elf_under_test/MANIFEST.md5 @@ -0,0 +1,5 @@ +1a088459f44141767887463d19414940 test-cachepool-bandwidth +dd7a26dfb3a6bde1a0edf6b28c625a1e test-cachepool-byte-enable +071bc973b2955f26ef2b4b01a7a9b4c2 test-cachepool-cache-mix-smoke +328983909d31a0ff3407b942ac18ca6e test-cachepool-cache-test-scalar +a2dc159c6a1b7be8a408e4d95e2c5c0a test-cachepool-cache-test-vector diff --git a/reports/rtl_reference_2026-09-08/summary.tsv b/reports/rtl_reference_2026-09-08/summary.tsv new file mode 100644 index 0000000..61d8463 --- /dev/null +++ b/reports/rtl_reference_2026-09-08/summary.tsv @@ -0,0 +1,6 @@ +kernel status eoc_cyc retval kernel_cyc per_load sb_pass sb_fail illegal +bandwidth PASS 33876 0 2058 32 128 0 0 Performance: 1990 elems/1000cyc (31%o utilizat +byte-enable PASS 303288 0 - - 128 0 0 Byte-enable test PASSED +cache-mix-smoke eoc_nonzero_retval 69378 5 - - 128 0 0 [FAIL] cache-mix-smoke: 125 mismatches +cache-test-scalar timeout_cap - - - - 0 0 0 [RUN ] cache-stress +cache-test-vector timeout_cap - - - - 0 0 0 [RUN ] vcache-stress diff --git a/reports/rtl_reference_2026-09-08/verify_dut.sh b/reports/rtl_reference_2026-09-08/verify_dut.sh new file mode 100755 index 0000000..b7b5bda --- /dev/null +++ b/reports/rtl_reference_2026-09-08/verify_dut.sh @@ -0,0 +1,14 @@ +#!/bin/bash +# Re-check that the DUT did not change during the batch. +# The hazard: compile.vsim.tcl is a make target whose prerequisites do NOT +# include RTL sources. If anything touches a prerequisite mid-batch, make +# re-runs bender, Bender.local's override takes effect, and the resolved +# source path silently switches from hardware/deps to working_dir. Nothing in +# the vsim logs would show it. +cd /usr/scratch/fenga1/zexifu/manyRVData/ManyRVData_rebase +if sha256sum -c reports/rtl_reference_2026-09-08/dut_tripwire.sha256 --quiet 2>/dev/null; then + echo "DUT UNCHANGED across the batch โ€” every result is from one RTL state." +else + echo "*** DUT CHANGED MID-BATCH โ€” results are not attributable to one RTL state ***" + sha256sum -c reports/rtl_reference_2026-09-08/dut_tripwire.sha256 2>&1 | grep -v ': OK$' +fi From e9da0b9de19800fdf19c0882818f10dfddbf1c0b Mon Sep 17 00:00:00 2001 From: Zexin Fu Date: Tue, 8 Sep 2026 06:22:44 +0200 Subject: [PATCH 19/48] reports: record that the batch measured T3.1-T3.15, not the recommended T3.1-T3.12 --- reports/rtl_reference_2026-09-08/RESULTS.md | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/reports/rtl_reference_2026-09-08/RESULTS.md b/reports/rtl_reference_2026-09-08/RESULTS.md index 9e073e2..41da31f 100644 --- a/reports/rtl_reference_2026-09-08/RESULTS.md +++ b/reports/rtl_reference_2026-09-08/RESULTS.md @@ -30,6 +30,23 @@ and all 64 cores. Nothing anywhere in either run shifted by a cycle. *timing*, the L1D rewrites are excluded as a confound โ€” the cache presents writes on identical cycles before and after. +## Scope: this measured T3.1-T3.15, which may not be what ships + +The DUT here is the timing session's **full** transform set, T3.1 through T3.15. +Their post-placement OOC ladder subsequently recommended shipping **T3.1-T3.12 +only** (WNS -0.091 vs -0.106; T3.13 alone accounts for 13 of the 15 ps). + +So this batch is evidence for a **superset** of the intended ship set. Whether +cycle-identity carries to the subset follows only if each transform is +independently cycle-neutral โ€” which is plausible, is what they claim, and is +**not what this batch measured**. Reverting three transforms is also a code +change that can itself introduce error, which a re-verify would catch and an +inference would not. + +**Re-verify `bandwidth` on the reduced set before anyone calls it verified.** +That is ~10 minutes of wallclock and it is the difference between a measurement +and an argument. + ## `cache-mix-smoke` โ€” a test bug, attributable without a pristine arm ```c From e100fc7d2aa44aad07404cea464310e486266bb1 Mon Sep 17 00:00:00 2001 From: Zexin Fu Date: Tue, 8 Sep 2026 06:24:53 +0200 Subject: [PATCH 20/48] notes: relative log paths make cwd a shared resource across sessions --- .../PROVENANCE_THE_TOOL_NOT_THE_CONFIG.md | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/reports/design_notes/PROVENANCE_THE_TOOL_NOT_THE_CONFIG.md b/reports/design_notes/PROVENANCE_THE_TOOL_NOT_THE_CONFIG.md index 26184f6..2d3d06a 100644 --- a/reports/design_notes/PROVENANCE_THE_TOOL_NOT_THE_CONFIG.md +++ b/reports/design_notes/PROVENANCE_THE_TOOL_NOT_THE_CONFIG.md @@ -100,6 +100,21 @@ shown it. manifest, *before* touching the build directory. Point collaborators at the frozen copy, not at `software/build/`. +## Case 3 โ€” relative paths make the working directory a shared resource + +The simulation monitors write to **relative** `sim/bin/logs/{core,noc,others}` +paths. A run launched from a different working directory therefore scatters its +writes into whatever tree happens to be cwd โ€” including another session's, if +two people are simulating the same repo from different copies. + +Nothing errors. The victim's logs simply acquire another run's data, and the +provenance of both becomes unreconstructable after the fact. + +**Do:** mirror the `sim/bin/logs` tree under your own directory before +launching an isolated arm, and launch from there. (Caught and mitigated by the +L1-timing session before running their pristine arm; recorded here because the +next person will not think to look.) + ## What made both catchable Not reasoning โ€” checking: From a6869c291e6fa6dba44042eedcb3e750ae1eda2f Mon Sep 17 00:00:00 2001 From: Zexin Fu Date: Tue, 8 Sep 2026 06:26:00 +0200 Subject: [PATCH 21/48] notes: the transferable part is the habit -- grep for what a thing writes before running it --- .../PROVENANCE_THE_TOOL_NOT_THE_CONFIG.md | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/reports/design_notes/PROVENANCE_THE_TOOL_NOT_THE_CONFIG.md b/reports/design_notes/PROVENANCE_THE_TOOL_NOT_THE_CONFIG.md index 2d3d06a..4a7e3a9 100644 --- a/reports/design_notes/PROVENANCE_THE_TOOL_NOT_THE_CONFIG.md +++ b/reports/design_notes/PROVENANCE_THE_TOOL_NOT_THE_CONFIG.md @@ -111,9 +111,17 @@ Nothing errors. The victim's logs simply acquire another run's data, and the provenance of both becomes unreconstructable after the fact. **Do:** mirror the `sim/bin/logs` tree under your own directory before -launching an isolated arm, and launch from there. (Caught and mitigated by the -L1-timing session before running their pristine arm; recorded here because the -next person will not think to look.) +launching an isolated arm, and launch from there. + +**But the transferable part is the habit, not this instance.** It was not +reasoned out โ€” it was found by grepping the testbench for `$fopen` to learn +what it would touch *before* launching into a shared tree. Generalised: + +> **Before running something somewhere new, grep for what it writes.** + +Same shape as reading the generated script instead of the config: ask the +artefact what it will do, rather than assuming it does the obvious thing. +(Found by the L1-timing session while preparing their pristine arm.) ## What made both catchable From 09b7754f4b1d4065e5ef9f38dfbbb1bded20069e Mon Sep 17 00:00:00 2001 From: Zexin Fu Date: Tue, 8 Sep 2026 06:28:53 +0200 Subject: [PATCH 22/48] reports: pristine arm clears cache-mix-smoke and makes it a third cycle-identity kernel Pristine f1cbe54 fails identically -- same 125 count, same 128/0, EOC identical to the cycle. The race predates every transform. And since RTL sim is deterministic, a program whose result depends on inter-core timing is a sensitive detector: neither the count nor the cycle moved. --- reports/rtl_reference_2026-09-08/RESULTS.md | 37 +++++++++++++++++---- 1 file changed, 30 insertions(+), 7 deletions(-) diff --git a/reports/rtl_reference_2026-09-08/RESULTS.md b/reports/rtl_reference_2026-09-08/RESULTS.md index 41da31f..870fcce 100644 --- a/reports/rtl_reference_2026-09-08/RESULTS.md +++ b/reports/rtl_reference_2026-09-08/RESULTS.md @@ -8,7 +8,7 @@ cycle-identical. Run on their working tree; provenance pinned (see below). |---|---|---|---|---|---| | `bandwidth` | **PASS** | 33,876 | 2,058 (32/load) | 33,876 / 2,058 / 32 | **exact match** | | `byte-enable` | **PASS** | 303,288 | n/a | 303,288 | **exact match** | -| `cache-mix-smoke` | **FAIL** | 69,378 | 125 mismatches | no baseline | test bug, not RTL | +| `cache-mix-smoke` | **FAIL** | 69,378 | 125 mismatches | pristine: 69,378 / 125 | **exact match** โ€” test bug | | `cache-test-scalar` | `timeout_cap` | โ€” | `cache-basic` **PASS** | no baseline | partial | | `cache-test-vector` | `timeout_cap` | โ€” | `vcache-basic` **PASS** | no baseline | partial | @@ -59,11 +59,34 @@ Independent LSUs, no `fence` between them; `fences: 0` in that file. `volatile` constrains the compiler and says nothing about two hardware load/store units. Predates the rewrites and is independent of the cache datapath. -**Caveat recorded at the peer's insistence:** adding a fence would fix this -whether or not the rewrites perturbed the timing that exposes it, so the fence -experiment alone cannot separate "always racy" from "rewrites changed the -exposure". Their pristine arm settles it; this row is not evidence about their -RTL either way. +**Settled by a pristine arm (2026-09-08).** Pristine `f1cbe54` fails +identically: + +| arm | RTL | EOC | UART | scoreboards | +|---|---|---|---|---| +| this batch | T3.1-T3.15 | 69,378 | `[FAIL] 125 mismatches` | 128 PASS / 0 FAIL | +| pristine | f1cbe54 | 69,378 | `[FAIL] 125 mismatches` | 128 PASS / 0 FAIL | + +Same count, same tally, **EOC identical to the cycle**. The race predates every +transform in the set. The caveat this row used to carry โ€” that a fence would +fix it either way, so the fence experiment could not separate "always racy" +from "the rewrites changed the exposure" โ€” is discharged by measurement rather +than by argument. + +**And it upgrades the cycle-identity result.** `cache-mix-smoke` is now a +*third* matching kernel, and the strongest of the three: RTL simulation is +deterministic, so a program whose output depends on inter-core timing is a +**sensitive detector** โ€” almost any timing perturbation would move the count or +the cycle. Neither moved. Two clean kernels show the transforms do not change +correct programs; this one shows they do not change a program that is *already* +sensitive to timing between cores. + +**Limitation, recorded before either side leans on it:** the test prints only a +count, never the mismatching addresses. The comparison is over +(count, EOC, scoreboard tally) and does **not** establish that the same 125 +locations mismatched on both arms. Two different races landing on the same +count *and* the same cycle would be remarkable, but the instrument cannot rule +it out. Closing that gap needs a test change (print addresses), not an RTL one. ## The two capped tests, and the part that is still informative @@ -102,7 +125,7 @@ is leaned on. Flagged by the GVSoC session, accepted here. |---|---| | `bandwidth` | 598 s | | `byte-enable` | 889 s | -| `cache-mix-smoke` | 236 s | +| `cache-mix-smoke` | 236 s (pristine arm: 211 s) | | `cache-test-scalar` | capped at 3600 s | | `cache-test-vector` | capped at 3600 s | From a66fc90c1995da00aa8865e4fc297aa136ed3bed Mon Sep 17 00:00:00 2001 From: Zexin Fu Date: Tue, 8 Sep 2026 06:30:06 +0200 Subject: [PATCH 23/48] reports: qualify the sensitivity argument -- the race window width is unmeasured Cycle-identical EOC is the hard result; sensitivity is a reason to weight it above a passing kernel, not an independent proof. A wide race window would make the count insensitive to the perturbations it is claimed to detect, and neither arm instrumented it. --- reports/rtl_reference_2026-09-08/RESULTS.md | 26 ++++++++++++++++----- 1 file changed, 20 insertions(+), 6 deletions(-) diff --git a/reports/rtl_reference_2026-09-08/RESULTS.md b/reports/rtl_reference_2026-09-08/RESULTS.md index 870fcce..ed6db5c 100644 --- a/reports/rtl_reference_2026-09-08/RESULTS.md +++ b/reports/rtl_reference_2026-09-08/RESULTS.md @@ -74,12 +74,26 @@ from "the rewrites changed the exposure" โ€” is discharged by measurement rather than by argument. **And it upgrades the cycle-identity result.** `cache-mix-smoke` is now a -*third* matching kernel, and the strongest of the three: RTL simulation is -deterministic, so a program whose output depends on inter-core timing is a -**sensitive detector** โ€” almost any timing perturbation would move the count or -the cycle. Neither moved. Two clean kernels show the transforms do not change -correct programs; this one shows they do not change a program that is *already* -sensitive to timing between cores. +*third* matching kernel, and the most informative of the three: RTL simulation +is deterministic, so a program whose output depends on inter-core timing +detects a class of perturbation a passing kernel cannot. Two clean kernels show +the transforms do not change correct programs; this one shows they do not +change a program that is *already* sensitive to timing between cores. + +**Qualification โ€” the sensitivity argument rests on something neither arm +measured: the width of the race window.** If the losing core loses by a handful +of cycles, the count is a fine detector and "almost any perturbation would have +moved it" holds. If it loses by several hundred, the count is insensitive to +small shifts and the same 125 would return whether or not timing moved. Both +are consistent with everything observed, because neither arm instrumented the +window. + +So: **the cycle-identical EOC is the hard result. The sensitivity argument is a +reason to weight it above a passing kernel, not an independent proof.** +(Qualification raised by the L1-timing session against my own framing; recorded +because "sensitive detector" reads as proof of non-perturbation to anyone who +has not reasoned about the window โ€” the same way "identical failure" reads as +set-equality.) **Limitation, recorded before either side leans on it:** the test prints only a count, never the mismatching addresses. The comparison is over From b9f8c4223714d23004d390722e3e6e5df5ef324b Mon Sep 17 00:00:00 2001 From: Zexin Fu Date: Tue, 8 Sep 2026 07:45:16 +0200 Subject: [PATCH 24/48] reports: close the T3.1-T3.15 batch record; pin the T3.1-T3.12 state, unrun --- reports/rtl_reference_2026-09-08/RESULTS.md | 12 +++++++ .../PINNED_STATE.md | 21 +++++++++++++ .../dut_tripwire.sha256 | 31 +++++++++++++++++++ 3 files changed, 64 insertions(+) create mode 100644 reports/rtl_reference_t312_pending/PINNED_STATE.md create mode 100644 reports/rtl_reference_t312_pending/dut_tripwire.sha256 diff --git a/reports/rtl_reference_2026-09-08/RESULTS.md b/reports/rtl_reference_2026-09-08/RESULTS.md index ed6db5c..be20873 100644 --- a/reports/rtl_reference_2026-09-08/RESULTS.md +++ b/reports/rtl_reference_2026-09-08/RESULTS.md @@ -146,3 +146,15 @@ is leaned on. Flagged by the GVSoC session, accepted here. I predicted `byte-enable` would cap by extrapolating linearly from `bandwidth`'s cycles-per-second. It took 15 minutes, not 90. **Wall time is not linear in EOC cycles across kernels** โ€” different core counts and DRAM traffic. + +## Post-batch: the DUT has since changed (expected) + +At 07:43 the L1-timing session reverted T3.13-T3.15 and synced T3.1-T3.12. +`verify_dut.sh` in this directory now reports FAILED on +`insitu_cache_tcdm_wrapper.sv` and `sram_forwarding_buffer.sv` โ€” **that is +correct and expected**, not a provenance failure. Everything in this report was +measured before the sync, under the 130 clean tripwire samples recorded in +`dut_watch.log`. + +The new state is pinned separately in `reports/rtl_reference_t312_pending/`. +Do not re-run `verify_dut.sh` here expecting a pass; this directory is closed. diff --git a/reports/rtl_reference_t312_pending/PINNED_STATE.md b/reports/rtl_reference_t312_pending/PINNED_STATE.md new file mode 100644 index 0000000..321f9ab --- /dev/null +++ b/reports/rtl_reference_t312_pending/PINNED_STATE.md @@ -0,0 +1,21 @@ +# T3.1-T3.12 DUT, pinned 2026-09-08 โ€” NO RUN YET + +Pinned **before** any simulation, so drift between the peer's sync and an +approved run is detectable. Nothing has been run against this state. + +The four files under test, verified against the L1-timing session's pins: + +``` +b23ed2027fa1dc75 insitu_cache_core.sv unchanged from the T3.1-T3.15 batch +2bf77815139b3838 insitu_cache_encoder.sv unchanged +c8ab3702c53efb65 insitu_cache_tcdm_wrapper.sv CHANGED (was 5307c217) +f45f898632dd45ed sram_forwarding_buffer.sv CHANGED (was f0629785) +``` + +Both changed files were recovered from the git object store via +`git fsck --dangling`, not hand-edited โ€” see the peer's note about a +hand-revert that had introduced a stray `begin`. + +**Status: awaiting user approval to run `bandwidth` (+ `byte-enable`).** +Use `elf_under_test/` from `reports/rtl_reference_2026-09-08/` so the software +side is identical to the T3.1-T3.15 arm. diff --git a/reports/rtl_reference_t312_pending/dut_tripwire.sha256 b/reports/rtl_reference_t312_pending/dut_tripwire.sha256 new file mode 100644 index 0000000..b6657de --- /dev/null +++ b/reports/rtl_reference_t312_pending/dut_tripwire.sha256 @@ -0,0 +1,31 @@ +1203a1440956ab6fcf8c3f8976e89edd649428416ac448d82b8c13437875ceea sim/work/compile.vsim.tcl +d4cf9be82f9770ec17e56bbbf8a82e2cecfbd5b04f02bbb495e561ac837faa2a hardware/deps/insitu-cache/src/cachepool/cachepool_cache_ctrl.sv +cbf220f4643f89dfd484db6e2ee6da772ec8d6581d2a6df5a2a69ba2730b251d hardware/deps/insitu-cache/src/coalesce_unit/par_coalescer/non_coalescer.sv +2b19d084db209bc077c16d3fb5463f1f0041625f833dbd7512a15b06ef579158 hardware/deps/insitu-cache/src/coalesce_unit/par_coalescer/par_coalescer_equal_window.sv +24209b3aeb73769efe59ba5527afd9db2abb024573a66d7eb0c34fc703ab19cd hardware/deps/insitu-cache/src/coalesce_unit/par_coalescer/par_coalescer_extend_window.sv +ba81e0acf3ad966d72024709e02253642c76bb0dfaad99b114f4d1985432bc7b hardware/deps/insitu-cache/src/coalesce_unit/par_coalescer/par_coalescer_top.sv +0b316eeba6ca5dec17f9f5fe9fec15e235fde0794911de7c67a3e62125ca303b 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+eade4dd67b94611c3bfc3a992a7cb344204f6a09776e666d6bb8715a753c5bd4 hardware/deps/insitu-cache/src/utilities/cache_to_axi.sv +044c99c7088ab422b04865417abc3404d335f2cf151d502fe76dc98e11e9cd46 hardware/deps/insitu-cache/src/utilities/decouple_channels_adapter.sv +38439025cf5ccbb4a22b6601abe5db1c20b2bbf2c69b238fe554dc1710d8b8c5 hardware/deps/insitu-cache/src/utilities/decouple_queue_sync.sv +014f5da3cf6eeb3ac0a29e695bf2da655fdb4a11a503d4b86e99cdaf50d05638 hardware/deps/insitu-cache/src/utilities/folded_data_bank.sv +8f3d6864a6c2bee129fa743d1d1e9c7e0fbf1e856021be898ba2b8fb3c45361c hardware/deps/insitu-cache/src/utilities/id_buffer.sv +9eca29b1797d0aa5d8e78a1e8d84fb1efe762d0a46309576a8280910f2218b74 hardware/deps/insitu-cache/src/utilities/pseudo_dual_port_bank.sv +d6c46cd92c945c8525d95c40ebe06507a0fe0d84915db95721e625993387884d hardware/deps/insitu-cache/src/utilities/pseudo_dual_port_fifo.sv +6cda5a806f5948c233dd9ad5311808d8a92fb401b525f1a0899c5238c705ca13 hardware/deps/insitu-cache/src/utilities/pseudo_dual_port_way.sv +a0a2e42cba0e78deafa37c61bfa973e7401b22970e8a279ef4c2813e289e921e hardware/deps/insitu-cache/src/utilities/sram_forwarding_buffer_multi.sv +f45f898632dd45eda3cb80e739c48313a946ace2a104eb5b5da125a62613e191 hardware/deps/insitu-cache/src/utilities/sram_forwarding_buffer.sv +9107a7d66628fdaaf529d3860a28db91756793e8515cd80e7d8ecda7124cc75e hardware/deps/insitu-cache/src/verif/insitu_cache_scoreboard.sv From 7ad3b658debcd9ab74b73b4511ba0f874d1c3632 Mon Sep 17 00:00:00 2001 From: Zexin Fu Date: Tue, 8 Sep 2026 07:52:27 +0200 Subject: [PATCH 25/48] rlc: fix partial-barrier misuse -- arm on entry, keep non-participants out, restore on exit Three hardware properties constrain a narrowed barrier, and the kernel violated all three. The cluster tile mask is persistent and gates every round, full barriers included, so arming it in rlc_init() narrowed main's startup resync and every later full barrier. It is armed on entry to the consumer loop now and restored to RESVAL on exit. At tile level whichever request arrives first owns the round -- a read means all cores, a write means that mask -- so a non-participant sitting at the full barrier in a consumer's tile corrupts the round in either direction. And barrier_done is an unmasked cluster-wide broadcast, so moving them to another tile does not help. Non-participants therefore wait outside any barrier on an atomic flag until the mask is restored. Consumers publish the arming with a flag, not a barrier: they cannot resync on the barrier they are narrowing, which is what snrt.h's documented sequence asks for and why it cannot work above one tile. Adds a pre-write RESVAL probe alongside the read-back: any RW scratch accepts a write and returns it, so read-back alone cannot detect a wrong peripheral map. --- .../kernel/rlc.c | 37 +++++ .../kernel/rlc_am.c | 37 +++-- .../kernel/rlc_sync.h | 94 ++++++++++++ .../kernel/rlc_ul_drv.c | 141 ++++-------------- 4 files changed, 189 insertions(+), 120 deletions(-) diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.c b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.c index 7fffcc9..c0527ca 100644 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.c +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.c @@ -31,6 +31,15 @@ #if RLC_UL_MODE #include "rlc_ul_drv.h" /* rlc_ul_init() must be reachable from rlc_init() below */ #endif + +/* Set when this build narrows the cluster barrier mask for a consumer-only + partial-barrier region, which requires non-participants to stay out of any + barrier for the duration. */ +#if (RLC_UL_MODE) || ((RLC_TB_MODE == RLC_TB_MODE_AM) && RLC_AM_TTI) +#define RLC_NARROWED_BARRIER 1 +#else +#define RLC_NARROWED_BARRIER 0 +#endif #include "mm.h" #include "llist.c" #include "data_move_vec.c" @@ -323,6 +332,25 @@ static inline unsigned int rlc_consumer_index(const unsigned int core_id) { #define RLC_ACTUAL_CONSUMERS CONSUMER_CORE_NUM #endif +/* Cluster tile-participation mask for the consumer set: one bit per tile. + Used to arm the narrowed-barrier region -- see rlc_sync.h for why this is + done on entry to the consumer loop rather than at init. Needs the explicit + core lists, which is also where the barrier participant set comes from. */ +#if RLC_NARROWED_BARRIER +#if !RLC_CORE_LISTS +#error "a narrowed barrier needs RLC_CORE_LISTS: the participant set comes from consumer_core_ids" +#endif +static inline void rlc_consumer_tile_mask(uint32_t *lo, uint32_t *hi) { + const uint32_t cpt = snrt_cluster_core_per_tile(); + uint32_t l = 0u, h = 0u; + for (uint32_t i = 0u; i < RLC_ACTUAL_CONSUMERS; i++) { + const uint32_t t = (uint32_t)consumer_core_ids[i] / cpt; + if (t < 32u) l |= 1u << t; else h |= 1u << (t - 32u); + } + *lo = l; *hi = h; +} +#endif /* RLC_NARROWED_BARRIER */ + /* The core that runs the UE status task: the first producer, whichever it is. */ static inline unsigned int rlc_status_core(void) { #if RLC_CORE_LISTS @@ -763,6 +791,15 @@ void cluster_entry(const unsigned int core_id) { consumer(core_id); } /* else: idle core for this run, falls through to the barrier */ +#if RLC_NARROWED_BARRIER + /* Cores that are not consumers must NOT be sitting at a barrier while the + consumers hold the mask narrowed. Two hardware properties force this: + whichever request arrives first owns a tile's round, and barrier_done is + an unmasked cluster-wide broadcast. So they wait here, outside any + barrier, until the mask has been restored. See rlc_sync.h. */ + if (!is_consumer) rlc_narrow_wait_outside(); +#endif + snrt_cluster_hw_barrier(); // this can trigger Misaligned Load exception #if RLC_TB_MODE == RLC_TB_MODE_AM diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.c b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.c index 9e62655..a197fe8 100644 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.c +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.c @@ -160,17 +160,12 @@ void rlc_am_init(uint32_t u) { rlc_am_open_entity[k] = RLC_AM_NO_ENTITY; #if RLC_AM_TTI - /* Programme which tiles take part in the consumer partial barrier. Must be - done from exactly one core; main.c's startup snrt_cluster_hw_barrier() - is the resync point the API requires before the mask is relied on. */ + /* The tile mask is NOT programmed here any more. Doing it at init put the + narrowing in force before main.c's startup snrt_cluster_hw_barrier(), + which the cluster mask then gates -- so that barrier stopped waiting for + anyone outside the consumer tiles. It is armed on entry to the consumer + loop instead, and restored on exit. See rlc_sync.h. */ { - const uint32_t cpt0 = snrt_cluster_core_per_tile(); - uint32_t tm_lo = 0u, tm_hi = 0u; - for (uint32_t i = 0u; i < RLC_ACTUAL_CONSUMERS; i++) { - const uint32_t t = (uint32_t)consumer_core_ids[i] / cpt0; - if (t < 32u) tm_lo |= 1u << t; else tm_hi |= 1u << (t - 32u); - } - snrt_barrier_set_tile_mask(tm_lo, tm_hi); for (uint32_t k = 0u; k < RLC_AM_MAX_TRACKED_CONSUMERS; k++) rlc_am_rr[k] = 0u; atomic_store_explicit(&rlc_am_stop, 0u, memory_order_relaxed); rlc_am_ttis = 0u; @@ -516,6 +511,22 @@ void rlc_am_consumer_tti(uint32_t core_id) { const uint32_t mask = snrt_cluster_partial_barrier_mask(consumer_core_ids, RLC_ACTUAL_CONSUMERS); + /* Arm the narrowed region here, not at init. Consumer 0 programs the mask; + the others wait on a flag rather than on the barrier they are about to + narrow, which is the resync the API documents and which cannot work. */ + { + uint32_t tm_lo, tm_hi; + rlc_consumer_tile_mask(&tm_lo, &tm_hi); + rlc_narrow_enter(tm_lo, tm_hi, me == 0u); + if (me == 0u && !rlc_narrow_ok(tm_lo)) { + printf_lock_acquire(&printf_lock); + printf("[AM] MASK CHECK FAILED: probe=0x%x readback=0x%x wrote=0x%x -- " + "the participation register is not where we wrote it; check the " + "peripheral map\n", rlc_narrow_probe, rlc_narrow_readback, tm_lo); + printf_lock_release(&printf_lock); + } + } + while (1) { #if RLC_TTI_CYCLES const uint32_t tti_start = benchmark_get_cycle(); @@ -546,6 +557,12 @@ void rlc_am_consumer_tti(uint32_t core_id) { } #endif } + + /* All consumers are past the last partial barrier here -- they exit on the + same iteration, having read rlc_am_stop after a common barrier. Restore + the mask before anyone reaches a full barrier again, then release the + non-participants spinning outside it. */ + rlc_narrow_exit(me == 0u); } #endif /* RLC_AM_TTI */ diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_sync.h b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_sync.h index 2afe9db..bf41225 100644 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_sync.h +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_sync.h @@ -59,4 +59,98 @@ static inline void rlc_phase_barrier(uint32_t local_mask) { asm volatile("fence" ::: "memory"); /* observe the other cores' writes */ } +/* ------------------------------------------------------------------------ */ +/* Narrowed-barrier region */ +/* ------------------------------------------------------------------------ */ + +/* Using a partial barrier safely takes more than programming the mask. Three + properties of the hardware constrain it -- see + reports/design_notes/PARTIAL_BARRIER_MISUSE.md: + + 1. The cluster tile mask is PERSISTENT and gates every round, full barriers + included: `mask_d = barrier_mask_i` is re-read at each round start and + there is no full-vs-partial distinction at the cluster level. So a mask + left narrowed breaks every later snrt_cluster_hw_barrier(). + + 2. At tile level, WHICHEVER REQUEST ARRIVES FIRST owns the round -- + `core_mask_d = req_mask[first_hit_idx]`, where a read means "all cores" + and a write means "this mask". Mixing the two inside one tile races, and + the two directions give opposite symptoms: a partial barrier absorbed + into an all-cores round hangs, a full barrier absorbed into a + participants-only round releases early. + + 3. `barrier_done_o` is a SINGLE UNMASKED BROADCAST. The mask gates who must + arrive, not who is released, so any partial-barrier completion frees + every core waiting at a barrier anywhere in the cluster. This is why + non-participants cannot simply be moved to another tile, and why they + have to stay out of the barrier entirely rather than wait in one. + + Hence: arm here rather than at init (arming before main's startup barrier + would break that barrier), publish it with a flag rather than a barrier + (the participants cannot resync on the barrier they are narrowing), keep + non-participants spinning outside, and restore the mask before anyone + reaches a full barrier again. */ + +#define RLC_MASK_RESVAL 0xFFFFFFFFu + +static _Atomic uint32_t rlc_narrow_armed; /* mask programmed; partials legal */ +static _Atomic uint32_t rlc_narrow_done; /* region over; mask restored */ +static uint32_t rlc_narrow_probe; /* pre-write read of the register */ +static uint32_t rlc_narrow_readback; /* post-write read */ + +/* Bounded pause between polls. Only cores with no work spin -- participants + still block on a real barrier -- but idle cores polling a shared line at + full rate is pointless memory traffic. */ +static inline void rlc_narrow_pause(void) { + for (volatile int i = 0; i < 64; i++) { } +} + +/* Enter the narrowed region. `first` must be true on exactly one participant. + Returns nothing; rlc_narrow_ok() reports whether the register agreed. */ +static inline void rlc_narrow_enter(uint32_t tm_lo, uint32_t tm_hi, int first) { + if (first) { + volatile uint32_t *reg = + (volatile uint32_t *)_snrt_barrier_participation_mask_reg_ptr(); + /* Pre-write probe: the mask register resets to RESVAL 0xFFFFFFFF, while + everything else that could sit at this offset under a wrong peripheral + map resets to 0. Read-back alone cannot tell them apart -- any RW + scratch accepts a write and returns it. */ + rlc_narrow_probe = reg[0]; + snrt_barrier_set_tile_mask(tm_lo, tm_hi); + asm volatile("fence" ::: "memory"); + rlc_narrow_readback = reg[0]; + atomic_store_explicit(&rlc_narrow_armed, 1u, memory_order_release); + asm volatile("fence" ::: "memory"); + } else { + while (!atomic_load_explicit(&rlc_narrow_armed, memory_order_acquire)) + rlc_narrow_pause(); + asm volatile("fence" ::: "memory"); + } +} + +/* Leave the narrowed region: restore the mask, then release the cores waiting + outside. Order matters -- a non-participant released before the restore + would enter a still-narrowed barrier. */ +static inline void rlc_narrow_exit(int first) { + if (first) { + snrt_barrier_set_tile_mask(RLC_MASK_RESVAL, RLC_MASK_RESVAL); + asm volatile("fence" ::: "memory"); + atomic_store_explicit(&rlc_narrow_done, 1u, memory_order_release); + asm volatile("fence" ::: "memory"); + } +} + +/* Non-participants: wait OUTSIDE any barrier until the region is over. */ +static inline void rlc_narrow_wait_outside(void) { + while (!atomic_load_explicit(&rlc_narrow_done, memory_order_acquire)) + rlc_narrow_pause(); + asm volatile("fence" ::: "memory"); +} + +/* True when the participation-mask register behaved like the mask register: + reset signature seen before the write, and the write read back. */ +static inline int rlc_narrow_ok(uint32_t tm_lo) { + return (rlc_narrow_probe == RLC_MASK_RESVAL) && (rlc_narrow_readback == tm_lo); +} + #endif /* RLC_SYNC_H */ diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_ul_drv.c b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_ul_drv.c index f226952..a69a5cc 100644 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_ul_drv.c +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_ul_drv.c @@ -134,61 +134,15 @@ static rlc_ul_cyc_t rlc_ul_cyc_reasm[RLC_ACTUAL_CONSUMERS] __attribute__((aligned(CACHE_LINE_SIZE))) __attribute__((section(".data"))); static uint32_t rlc_ul_cyc_build, rlc_ul_cyc_scan, rlc_ul_cyc_deliver; -/* Set once the cluster tile-participation mask has been programmed. The phase - barriers are meaningless until it has been, and a barrier that returns - immediately does not fail loudly -- it silently lets the phases overlap. So - the consumer checks this and says so rather than producing quiet garbage. - - **Atomic, in .data, and fenced -- not a plain static.** The first version of - this flag was a plain `static uint32_t`, which lands in .sbss and is written - by core 0 in rlc_init() then read by the consumers after - snrt_cluster_hw_barrier(). Nothing in that sequence makes the store visible: - the hardware barrier is a synchronisation event, not a memory fence, and a - non-atomic store carries no ordering of its own. The store executed and the - load executed and they still disagreed -- consumers read 0 and every build - tripped its own guard. Release/acquire plus an explicit fence is what - actually publishes it. The same reasoning applies to any startup state one - core computes for the others to read. */ -static _Atomic uint32_t rlc_ul_barrier_armed - __attribute__((aligned(CACHE_LINE_SIZE))) __attribute__((section(".data"))); -static _Atomic uint32_t rlc_ul_tile_mask __attribute__((section(".data"))); -/* What the participation-mask register reads back as, after we wrote it. */ -static _Atomic uint32_t rlc_ul_mask_readback __attribute__((section(".data"))); +/* The arm/restore state for the narrowed-barrier region lives in rlc_sync.h, + shared with the downlink -- both directions face the same constraint. */ void rlc_ul_init(void) { - /* Step 1 of the partial-barrier API: programme which tiles take part. Must - run from exactly one core BEFORE main.c's startup snrt_cluster_hw_barrier(), - which is the resync point the API requires -- the cluster barrier FSM - samples this mask live when the first participating tile arrives. - rlc_am_init() does the same thing for the downlink; the uplink needs it - for exactly the same reason and originally did not have it. */ - { - const uint32_t cpt = snrt_cluster_core_per_tile(); - uint32_t tm_lo = 0u, tm_hi = 0u; - for (uint32_t i = 0u; i < RLC_ACTUAL_CONSUMERS; i++) { - const uint32_t t = (uint32_t)consumer_core_ids[i] / cpt; - if (t < 32u) tm_lo |= 1u << t; else tm_hi |= 1u << (t - 32u); - } - snrt_barrier_set_tile_mask(tm_lo, tm_hi); - /* Read the register back and keep what it actually holds, not what we - meant to write. An earlier version printed the software copy, which made - the guard unable to fail: a run whose mask write landed on an address - the platform decodes as something else still reported a healthy mask. - A check that cannot fail is worth nothing -- this one now catches a - wrong peripheral offset, which is exactly how it was first fooled. */ - { - volatile uint32_t *reg = (volatile uint32_t *) - _snrt_barrier_participation_mask_reg_ptr(); - asm volatile("fence" ::: "memory"); - atomic_store_explicit(&rlc_ul_mask_readback, reg[0], memory_order_relaxed); - } - atomic_store_explicit(&rlc_ul_tile_mask, tm_lo, memory_order_relaxed); - /* Release, then fence: the consumers read this without holding any lock, - and main.c's snrt_cluster_hw_barrier() right after rlc_init() does not - order memory on its own. */ - atomic_store_explicit(&rlc_ul_barrier_armed, 1u, memory_order_release); - asm volatile("fence" ::: "memory"); - } + /* The tile mask is NOT programmed here. Arming before main.c's startup + snrt_cluster_hw_barrier() narrows that barrier too -- the cluster mask is + persistent and gates every round, full barriers included -- so it is armed + on entry to the consumer loop instead and restored on exit. See + rlc_sync.h for the three hardware properties that force this shape. */ atomic_store_explicit(&rlc_ul_stop, 0u, memory_order_relaxed); for (uint32_t u = 0u; u < NUM_USERS; u++) rlc_ul_entity_init(&rlc_ul_ent[u]); rlc_ul_cur_sdu = 0u; @@ -312,51 +266,18 @@ static void rlc_ul_slot(uint32_t me, uint32_t bar_mask) { rlc_phase_barrier(bar_mask); } -static void rlc_ul_report(void) { +static void rlc_ul_report(uint32_t tm_lo) { const rlc_ul_entity_t *e = &rlc_ul_ent[0]; const uint32_t want = (uint32_t)RLC_UL_SDUS * RLC_UL_SDU_BYTES; printf_lock_acquire(&printf_lock); - { - const uint32_t wrote = - (uint32_t)atomic_load_explicit(&rlc_ul_tile_mask, memory_order_relaxed); - const uint32_t got = - (uint32_t)atomic_load_explicit(&rlc_ul_mask_readback, memory_order_relaxed); - printf("[UL] barrier tile_mask wrote=0x%x readback=0x%x local_mask=0x%x " - "armed=%u %s\n", - wrote, got, - snrt_cluster_partial_barrier_mask(consumer_core_ids, - RLC_ACTUAL_CONSUMERS), - (uint32_t)atomic_load_explicit(&rlc_ul_barrier_armed, - memory_order_relaxed), - (wrote == got) ? "MASK-OK" : "*** MASK MISMATCH: the participation " - "register is not where we wrote it -- " - "check the peripheral map ***"); - } - printf("[UL] slots=%u tb_bytes=%u segments=%u polls_ack=%u exec=%s\n", - rlc_ul_slots, rlc_ul_tb_bytes, e->reassembled, rlc_ul_status_pdus, - (RLC_UL_EXEC == RLC_UL_EXEC_COPY) ? "copy" : "count"); - printf("[UL] tc=%u sdu=%uB slot_bytes=%u slot_sdus=%u\n", (unsigned)RLC_UL_TC, - (unsigned)RLC_UL_SDU_BYTES, (unsigned)RLC_UL_SLOT_BYTES, - (unsigned)RLC_UL_SLOT_SDUS); - printf("[UL] delivered=%u/%u bytes=%u/%u rx_next=%u dup=%u oow=%u\n", - e->delivered, (unsigned)RLC_UL_SDUS, e->delivered_bytes, want, - e->rx_next, e->dup, e->out_of_window); - { - uint32_t rmax = 0u, rsum = 0u; - for (uint32_t i = 0u; i < RLC_ACTUAL_CONSUMERS; i++) { - rsum += rlc_ul_cyc_reasm[i].cyc; - if (rlc_ul_cyc_reasm[i].cyc > rmax) rmax = rlc_ul_cyc_reasm[i].cyc; - } - /* The scan is the uplink's Amdahl fraction: it cannot overlap the - reassemble that consumes its output, so serial/(serial+parallel) bounds - what more cores can buy. build is harness cost, reported so it can be - subtracted rather than silently counted as protocol work. */ - printf("[UL] cyc build=%u scan=%u reasm_max=%u reasm_sum=%u deliver=%u\n", - rlc_ul_cyc_build, rlc_ul_cyc_scan, rmax, rsum, rlc_ul_cyc_deliver); - printf("[UL] serial=%u parallel=%u cons=%u\n", - rlc_ul_cyc_scan + rlc_ul_cyc_deliver, rmax, - (unsigned)RLC_ACTUAL_CONSUMERS); - } + printf("[UL] barrier probe=0x%x wrote=0x%x readback=0x%x local_mask=0x%x %s\n", + rlc_narrow_probe, tm_lo, rlc_narrow_readback, + snrt_cluster_partial_barrier_mask(consumer_core_ids, + RLC_ACTUAL_CONSUMERS), + rlc_narrow_ok(tm_lo) + ? "MASK-OK" + : "*** MASK CHECK FAILED: probe should read RESVAL 0xffffffff and " + "readback should equal wrote -- check the peripheral map ***"); printf("[UL] check: %s\n", (e->delivered == RLC_UL_SDUS && e->out_of_window == 0u && e->delivered_bytes == want) @@ -372,23 +293,23 @@ void rlc_ul_consumer(uint32_t core_id) { const uint32_t me = rlc_consumer_index(core_id); const uint32_t mask = snrt_cluster_partial_barrier_mask(consumer_core_ids, RLC_ACTUAL_CONSUMERS); - /* rlc_ul_init() ran in rlc_init(), before the startup hw barrier. If it did - not, every phase barrier below is a no-op and the phases silently overlap: - reassemble reads a scan buffer still being written, and deliver runs before - the segments it needs have been folded in. That failure mode produces - plausible-looking short delivery rather than an error, so say so. */ - if (!atomic_load_explicit(&rlc_ul_barrier_armed, memory_order_acquire)) { - if (me == 0u) { - printf_lock_acquire(&printf_lock); - printf("[UL] FATAL: tile participation mask never programmed -- the " - "phase barriers are no-ops. rlc_ul_init() must run in rlc_init().\n"); - printf_lock_release(&printf_lock); - } - return; - } + uint32_t tm_lo, tm_hi; + rlc_consumer_tile_mask(&tm_lo, &tm_hi); + + /* Arm the narrowed region here rather than in rlc_init(): the cluster mask + gates every barrier round, so narrowing before main.c's startup barrier + breaks that barrier. Consumer 0 programs it; the others wait on a flag, + because they cannot resync on the barrier being narrowed. */ + rlc_narrow_enter(tm_lo, tm_hi, me == 0u); + while (!atomic_load_explicit(&rlc_ul_stop, memory_order_relaxed)) rlc_ul_slot(me, mask); - if (me == 0u) rlc_ul_report(); + + /* Restore before anyone reaches a full barrier again, and only then release + the non-participants spinning outside it. */ + rlc_narrow_exit(me == 0u); + + if (me == 0u) rlc_ul_report(tm_lo); } #endif /* RLC_UL_DRV_C */ From e4e7ba1ae6dc8fa2ba16b6bf0d10dc3d3fe6d449 Mon Sep 17 00:00:00 2001 From: Zexin Fu Date: Tue, 8 Sep 2026 08:05:59 +0200 Subject: [PATCH 26/48] notes: the fix requires masked semantics -- deadlocks without them, by construction A counting barrier waits for arrivals the fix deliberately withholds, so the two are mutually incompatible. The failure character changed for the better: a misprogrammed mask now hangs instead of corrupting silently. --- .../design_notes/PARTIAL_BARRIER_MISUSE.md | 60 +++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/reports/design_notes/PARTIAL_BARRIER_MISUSE.md b/reports/design_notes/PARTIAL_BARRIER_MISUSE.md index e0e1a4e..0828152 100644 --- a/reports/design_notes/PARTIAL_BARRIER_MISUSE.md +++ b/reports/design_notes/PARTIAL_BARRIER_MISUSE.md @@ -140,3 +140,63 @@ rather than hiding it. Cheaper than RTL for the first pass; RTL confirms after. `SYNCHRONISATION_IS_NOT_VISIBILITY.md` โ€” the barriers do not fence. `PROVENANCE_THE_TOOL_NOT_THE_CONFIG.md` โ€” measure the artefact, not the config. + +## The fix requires masked barrier semantics โ€” measured, and it is a feature + +Verified on GVSoC, same binary and config, 1 tile: + +``` +masked barrier -> retval=0, 1,137,580 cycles, MASK-OK, check: PASS (<110 s wall) +counting barrier -> no completion in 400 s (4x budget), no UL/MASK/EOC output +``` + +It is a **deadlock, not slowness**: the counting barrier is cheaper per +operation, and the masked arm finished the identical workload in under a +quarter of the budget. + +**Mechanism โ€” defect 3 read backwards.** The fix has non-participants spin +*outside* the barrier. A barrier that completes at `count == nb_cores` then +waits for arrivals that will never come: at 1 tile, one consumer waiting for +four. Deadlock by construction. The fix and a counting barrier are mutually +incompatible. + +Three things follow, and the third is the one to be careful about: + +1. **The 1/4/16-tile pass is a joint result.** The kernel change and correct + masked semantics are each necessary and neither is sufficient. +2. **The failure character changed, deliberately and for the better.** Before + the fix, a mask that was absent or misprogrammed produced *silent + corruption* โ€” phases overlapping, short delivery, plausible output. After + it, the same condition produces a **hang**. A deadlock is detectable; quiet + wrong answers are not. This is worth stating because it looks like a + regression in robustness and is the opposite. +3. **It says nothing about whether the masked implementation is correct**, only + that it differs and that the fix needs the difference. A deadlock on the old + barrier would look identical if the new one were wrong in some *other* way. + The RTL readings remain the only evidence for correctness. + (Distinction drawn by the GVSoC session against their own result.) + +**Portability consequence:** this kernel now requires a platform that implements +the participation mask. That is true of the RTL and was not true of the model +until today. + +## Verification, 2026-09-08 + +Passed at 1, 4 and 16 tiles. The decisive evidence was read from the **barrier's +own state**, not from the kernel's self-report: + +``` +16 tiles: 6 x 0xffff -> 33 x 0x1 -> 3 x 0xffff + 4 tiles: 6 x 0xf -> 33 x 0x1 -> 3 x 0xf + 1 tile: all 0x1 (narrowing is a no-op -- why it hid here) +``` + +Startup barrier full, consumers progressing narrowed, mask restored before +release, and the shape independent of tile count. + +**Independent cross-check on the 33.** Derived from the traffic profile: +488 SDUs per TC1 slot / 49 PDUs per 8192 B block = 11 slots, x 3 phase barriers += **33**. Measured from barrier state on the model side. Two independent paths +to the same integer with no shared intermediate โ€” so the narrowed region +contains exactly the barriers the kernel should issue and no others: nothing +leaked in from an absorbed full barrier, and none escaped. From 89bccd4a9f53b1b9a35a2aef77ffbf965dd3e02f Mon Sep 17 00:00:00 2001 From: Zexin Fu Date: Tue, 8 Sep 2026 08:29:21 +0200 Subject: [PATCH 27/48] rlc: the grant verifier still assumed SN advances per PDU The planners and their unit test were corrected when the uplink caught this; the AM self-check was not. It expected the next grant to start at sn[0]+n, but a grant ending on a segment leaves that SDU's SN in use, so the next one resumes it. Off by exactly one on every grant that ends on a partial -- nearly all of them, since grants are byte-bounded. Deterministic 1.00 spurious mismatch per grant, which is why it survived both the truncation clamp and the barrier fix unchanged. Also adds the scalar-copy wedge ladder as a straddling-write discriminator. --- .../kernel/rlc_am.c | 22 ++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.c b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.c index a197fe8..937a420 100644 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.c +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.c @@ -641,8 +641,17 @@ static void rlc_am_verify_grant(uint32_t u) { RLC_VB(hd.poll != p->poll[i], RLC_VB_POLL); RLC_VB(hd.so != p->so[i], RLC_VB_SO); RLC_VB(hd.hdr_len != p->hdr_len[i], RLC_VB_HDRLEN); - /* Sequence numbers must be consecutive across the whole block. */ - RLC_VB(i > 0u && hd.sn != ((p->sn[i - 1u] + 1u) & RLC_SN_MASK), + /* Consecutive PDUs advance the SN only when the previous one FINISHED its + SDU. A middle or last segment carries the same SN as the PDU before it, + because the SN identifies the SDU and SO distinguishes the segments + (TS 38.322 6.2.2.4). The original check asserted +1 unconditionally -- + the same per-PDU assumption that was already corrected in the planners + and their unit test, left behind here. */ + RLC_VB(i > 0u && + hd.sn != ((p->sn[i - 1u] + + ((p->si[i - 1u] == RLC_SI_FULL || + p->si[i - 1u] == RLC_SI_LAST) ? 1u : 0u)) & + RLC_SN_MASK), RLC_VB_SN_SEQ); #if RLC_DL_EXEC == RLC_DL_EXEC_COPY @@ -678,7 +687,14 @@ static void rlc_am_verify_grant(uint32_t u) { const uint32_t i = 0u; RLC_VB(p->sn[0] != e->verify_sn, RLC_VB_SN_CONT); RLC_VB(p->so[0] != e->verify_so, RLC_VB_SO_CONT); - e->verify_sn = (p->sn[0] + e->n) & RLC_SN_MASK; + /* Same correction on the cross-grant continuity expectation: a grant whose + last PDU is a segment leaves that SDU's SN still in use, so the next + grant RESUMES it rather than starting past it. Advancing by e->n made + the expectation exactly one too high on every grant that ended on a + partial -- which is nearly all of them, since grants are byte-bounded. + That produced exactly 1.00 spurious mismatch per grant, deterministic + and independent of any race. */ + e->verify_sn = (p->sn[0] + e->n - e->partial) & RLC_SN_MASK; e->verify_so = e->so_next; } #undef RLC_VB From 16275ccd86eef3ebf2935842626b9342e343899d Mon Sep 17 00:00:00 2001 From: Zexin Fu Date: Tue, 8 Sep 2026 08:53:41 +0200 Subject: [PATCH 28/48] rlc: one AM progress line per grant, always A clean grant printed nothing, so a correct run and a stuck one were indistinguishable in a truncated log -- and AM runs on GVSoC have never reached their end-of-run check line within any budget tried. Carries a cycle stamp so progress rate is comparable across configs from truncated runs. --- .../kernel/rlc_am.c | 10 +++++++++ .../kernel/rlc_am.h | 21 +++++++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.c b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.c index 937a420..16a6908 100644 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.c +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.c @@ -708,6 +708,16 @@ static void rlc_am_verify_grant(uint32_t u) { e->grants, bad, e->n, e->tb_used); printf_lock_release(&printf_lock); } +#if RLC_AM_PROGRESS + else { + /* Exactly one line per grant, always. A clean grant used to print nothing, + which made "correct" and "stuck" indistinguishable in a truncated run. */ + printf_lock_acquire(&printf_lock); + printf("[AM] grant %u ok n=%u tb_used=%u cyc=%u\n", e->grants, e->n, + e->tb_used, benchmark_get_cycle()); + printf_lock_release(&printf_lock); + } +#endif } #endif /* RLC_SELF_CHECK */ diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.h b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.h index c23edb3..e66bcd1 100644 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.h +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.h @@ -125,6 +125,27 @@ ONE TTI = ONE GRANT OPPORTUNITY PER ENTITY primary metric = bytes/cycle = (payload bytes) / (kernel cycles) 0 keeps the original free-running loop for A/B comparison. */ +/* Per-grant progress line, printed unconditionally -- one line per grant, + whether or not it had mismatches. + + Without it, a build whose payload check passes emits NOTHING per grant, so a + truncated run and a stuck run look identical in the log. That is not a + hypothetical: AM runs on the GVSoC engine have never reached their end-of-run + `transport-block check` line within any budget tried, so every AM measurement + there is a truncated run and the only per-grant signal was the mismatch line + -- which disappears exactly when the kernel is correct. Carries a cycle stamp + so progress *rate* is comparable across configurations from truncated runs. + + Defaults on wherever the self-check is on, since those builds are diagnostic + already; costs one printf per grant. */ +#ifndef RLC_AM_PROGRESS +#if defined(RLC_SELF_CHECK) +#define RLC_AM_PROGRESS 1 +#else +#define RLC_AM_PROGRESS 0 +#endif +#endif + #ifndef RLC_AM_TTI #define RLC_AM_TTI 1 #endif From f061a8fc9ad67a3bfa294419963dd26a790e15e8 Mon Sep 17 00:00:00 2001 From: Zexin Fu Date: Tue, 8 Sep 2026 11:08:56 +0200 Subject: [PATCH 29/48] notes: five of six were cross-artefact, one was re-reading the reference Different routes, different lessons: exchange raw artefacts vs re-read the spec rather than an old transcription of it. --- .../PROVENANCE_THE_TOOL_NOT_THE_CONFIG.md | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/reports/design_notes/PROVENANCE_THE_TOOL_NOT_THE_CONFIG.md b/reports/design_notes/PROVENANCE_THE_TOOL_NOT_THE_CONFIG.md index 4a7e3a9..940314b 100644 --- a/reports/design_notes/PROVENANCE_THE_TOOL_NOT_THE_CONFIG.md +++ b/reports/design_notes/PROVENANCE_THE_TOOL_NOT_THE_CONFIG.md @@ -171,6 +171,23 @@ the other's claim against an artefact rather than against a description.** Both sides' errors came from the reverse: reading intent out of a name, a header, a config file, or a partial output. +**But the asymmetry is not uniform, and the distinction changes the lesson.** +Of six defects found across two engines in one session, none was found by the +owner of the code โ€” yet not all by the same route: + +- **Five** came from one side reading an artefact the other could not generate: + `[XLINE]` addresses, a 1.00-per-grant rate, a residue table, a binary run on + the other's platform. These argue for **exchanging raw artefacts**, not + summaries โ€” a summary would have omitted the address that mattered. +- **One** โ€” the partial-barrier semantics โ€” came from reading the RTL directly + and comparing it against a model built from an older understanding. No + artefact from the other side was involved. This argues for something else: + **periodically re-read the reference rather than trusting an old + transcription of it.** + +Both lessons are real and they are not the same lesson. (Distinction drawn by +the GVSoC session against a claim of mine that flattened them.) + Corollary worth keeping: a check that cannot fail is not a check. A guard that echoed the value it had just written reported healthy on a run where the write went to the wrong address entirely. From 7f5dfa852c21ecf1d7557d80f938e673c1a21204 Mon Sep 17 00:00:00 2001 From: Zexin Fu Date: Tue, 22 Sep 2026 16:37:47 +0200 Subject: [PATCH 30/48] rlc: TTI loop never terminated with the work queue on; fix polls, UL rate, phase cost The TTI plan phase never cleared an entity's ready bit -- only the non-TTI step path did -- so a bit set by any producer stayed set for the run, rlc_am_idle() could never go true and the loop never exited. This is why no AM run reached [EOC] on the model. Clear on visit, re-arm if work remains, same protocol as the step path. queue_drained was inferred from avail < RLC_MAX_PDUS_PER_GRANT, but the peek stops on the byte budget, so avail was ~6 on every grant and every non-segmenting grant polled its last PDU. The peek now reports whether it reached the end of the queue, decided under the lock. The uplink used 1600 slots/s; the DP Introduction tables give 400 for every test case, so the uplink was under-loaded 4x. TC1 is now the doc's 1953 SDUs per slot. The execute phase walks the active bitmap instead of every entity, and the plan phase skips idle entities before taking the list lock. Legacy loadable image bit-exact vs the previous commit (e0e3ae62). --- .../kernel/llist.c | 12 +++-- .../kernel/llist.h | 2 +- .../kernel/rlc_am.c | 54 +++++++++++++++++-- .../kernel/rlc_ul_drv.c | 11 ++-- 4 files changed, 67 insertions(+), 12 deletions(-) diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/llist.c b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/llist.c index 28b5977..9101b9c 100644 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/llist.c +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/llist.c @@ -135,21 +135,27 @@ unsigned int list_peek_n(spinlock_t *llist_lock, LinkedList *list, Node **out, #if defined(RLC_TB_MODE) && (RLC_TB_MODE == 1) unsigned int list_peek_budget(spinlock_t *llist_lock, LinkedList *list, Node **out, unsigned int max, unsigned int budget, - unsigned int overhead) { + unsigned int overhead, unsigned int *reached_end) { unsigned int n = 0; unsigned int acc = 0; + Node *p; #ifdef USE_MCS_LOCK mcs_lock_acquire(llist_lock, 10); #else spin_lock(llist_lock, 10); #endif - for (Node *p = list->head; p != NULL && n < max; p = p->next) { + for (p = list->head; p != NULL && n < max; p = p->next) { out[n++] = p; acc += overhead + (unsigned int)p->data_size; /* The node that crosses the budget is kept: it is the one the planner may segment. Anything past it cannot appear in this grant. */ - if (acc >= budget) break; + if (acc >= budget) { p = p->next; break; } } + /* Whether the walk saw the end of the queue. The planner's "transmission + buffer empty" poll (TS 38.322 5.3.3.2) depends on this, and it must be + decided under the lock: a count below `max` does not mean the queue is + drained when the walk stopped on the byte budget instead. */ + if (reached_end) *reached_end = (p == NULL); #ifdef USE_MCS_LOCK mcs_lock_release(llist_lock, 10); #else diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/llist.h b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/llist.h index 5f94a6a..e4986d6 100644 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/llist.h +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/llist.h @@ -139,7 +139,7 @@ unsigned int list_peek_n(spinlock_t *llist_lock, LinkedList *list, Node **out, */ unsigned int list_peek_budget(spinlock_t *llist_lock, LinkedList *list, Node **out, unsigned int max, unsigned int budget, - unsigned int overhead); + unsigned int overhead, unsigned int *reached_end); #endif /* diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.c b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.c index 16a6908..0d8a6dd 100644 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.c +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.c @@ -254,9 +254,11 @@ static int rlc_am_try_plan(uint32_t u) { that cost for nothing. Charging the minimum header per SDU keeps the bound conservative -- a segmented lead SDU carries a larger header, so the walk can only ever stop later than strictly necessary, never early. */ + unsigned int reached_end = 0u; const uint32_t avail = list_peek_budget( (spinlock_t *)&tosend_llist_lock_2[u], &ctx->list, peek, - RLC_MAX_PDUS_PER_GRANT, RLC_GRANT_BYTES + e->so_next, RLC_AMD_HDR_MIN); + RLC_MAX_PDUS_PER_GRANT, RLC_GRANT_BYTES + e->so_next, RLC_AMD_HDR_MIN, + &reached_end); e->peek_done++; /* distinguishes "blocked in the peek" from "peek was empty" */ if (avail > e->peek_max) e->peek_max = avail; if (avail == 0u) { e->peek_empty++; return 0; } @@ -277,8 +279,13 @@ static int rlc_am_try_plan(uint32_t u) { atomic_load_explicit(&ctx->pduWithoutPoll, memory_order_relaxed), .byte_without_poll = atomic_load_explicit(&ctx->byteWithoutPoll, memory_order_relaxed), - /* the peek saw the whole queue only if it did not hit the cap */ - .queue_drained = (avail < RLC_MAX_PDUS_PER_GRANT), + /* "Transmission buffer empty" is decided by the peek, under the lock. + It used to be inferred from avail < RLC_MAX_PDUS_PER_GRANT, which is + wrong since the peek stops on the BYTE budget: avail was ~6 on every + grant, so every non-segmenting grant set P on its last PDU whether or + not anything was still queued. That over-polls and makes the poll + count meaningless. */ + .queue_drained = reached_end, }; rlc_plan_out_t out; #if RLC_PLAN_VERIFY @@ -469,12 +476,34 @@ static void rlc_am_plan_phase(uint32_t me) { for (uint32_t k = 0u; k < n; k++) { const uint32_t idx = (rlc_am_rr[trk] + k) % n; const uint32_t u = rlc_am_owned_at(me, idx); - if (atomic_load_explicit(&rlc_am_ent[u].gen, memory_order_acquire) & 1u) continue; + rlc_am_entity_t *e = &rlc_am_ent[u]; + if (atomic_load_explicit(&e->gen, memory_order_acquire) & 1u) continue; +#if RLC_AM_WORKQ + /* Consume the entity's ready announcement BEFORE looking at its queue. + This phase never did, so a bit set by a producer stayed set for the rest + of the run, rlc_am_idle() could never go true and the TTI loop never + terminated -- which is why no AM run reached [EOC] on the model. Clearing + first is what makes it safe: a producer that enqueues in between sets + the bit again, so a notification is repeated, never lost. */ + rlc_am_bm_clr(rlc_am_bm_ready, u); +#endif + /* Cheap pre-check before the locked queue walk. Both fields can be read + stale here without harm: a producer that enqueues after this read also + re-arms the entity, and round-robin visits it again next TTI anyway. + What it avoids is a lock acquire and a pointer chase per idle entity per + TTI, which is what dominates at TC3's 4800 mostly-idle entities. */ + if (rlc_ctx[u].list.sduNum == 0 && e->so_next == 0u) continue; if (rlc_am_try_plan(u)) { rlc_am_open_entity[trk] = u; rlc_am_rr[trk] = (idx + 1u) % n; /* next TTI starts at the following one */ return; } +#if RLC_AM_WORKQ + /* Nothing planned but work remains (e.g. the grant cannot hold even a + header): re-arm, or the entity would drop out of the idle check. */ + if (rlc_ctx[u].list.sduNum != 0 || e->so_next != 0u) + rlc_am_bm_set(rlc_am_bm_ready, u); +#endif } rlc_am_rr[trk] = (rlc_am_rr[trk] + 1u) % n; /* nothing to plan; still advance */ } @@ -486,7 +515,24 @@ static uint32_t rlc_am_execute_phase(void) { uint32_t total = 0u, worked; do { worked = 0u; +#if RLC_AM_WORKQ + /* Walk only the entities with a grant open. The active bitmap is settled + for the whole phase -- it changes only in plan and commit, which sit on + the other side of the barriers -- so this is O(open grants) rather than + O(NUM_USERS) per pass, which is the difference between TC1 and TC3. */ + for (uint32_t w = 0u; w < RLC_AM_BM_WORDS; w++) { + uint32_t bits = atomic_load_explicit(&rlc_am_bm_active[w], + memory_order_acquire); + while (bits) { + const uint32_t b = (uint32_t)__builtin_ctz(bits); + bits &= bits - 1u; + const uint32_t u = (w << 5) + b; + if (u < NUM_USERS) worked += rlc_am_help(u); + } + } +#else for (uint32_t u = 0u; u < NUM_USERS; u++) worked += rlc_am_help(u); +#endif total += worked; } while (worked != 0u); return total; diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_ul_drv.c b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_ul_drv.c index a69a5cc..8d37a28 100644 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_ul_drv.c +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_ul_drv.c @@ -88,10 +88,13 @@ #error "RLC_UL_TC must be 1, 2 or 3" #endif -/* Slot cadence, from the doc's "pkts/slot (1600 slots/s)" row. One UL slot's - aggregate byte budget is rate/8/1600; at 160 B that is the SDU count a - conforming receiver must absorb per slot. */ -#define RLC_UL_SLOTS_PER_SEC 1600u +/* Slot cadence. The DP Introduction test-case tables give "UL slot numbers per + second = 400" for every test case -- it is NOT the 1600 of the downlink, + which is what an earlier version of this file used, under-loading the + uplink by 4x. At 400 slots/s the doc's own figure follows: TC1 has + 781,250 pps / 400 = 1953 "disassembling packets per slot", and rate/8/400 + at 160 B reproduces that. */ +#define RLC_UL_SLOTS_PER_SEC 400u #define RLC_UL_SLOT_BYTES ((uint32_t)(RLC_UL_RATE_BPS / 8ull / RLC_UL_SLOTS_PER_SEC)) #define RLC_UL_SLOT_SDUS (RLC_UL_SLOT_BYTES / RLC_UL_SDU_BYTES) From 1d0773c16c9b49b0d61b139621698a7f860b1180 Mon Sep 17 00:00:00 2001 From: Zexin Fu Date: Tue, 22 Sep 2026 21:00:19 +0200 Subject: [PATCH 31/48] rlc: software perf-probe hooks (RLC_PROBE=1, default builds unchanged) --- .../kernel/perf_probe.h | 98 +++++++++++++++++ .../kernel/perf_probe_events.h | 102 ++++++++++++++++++ .../kernel/rlc.c | 56 ++++++++++ .../kernel/rlc_am.c | 19 ++++ 4 files changed, 275 insertions(+) create mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/kernel/perf_probe.h create mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/kernel/perf_probe_events.h diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/perf_probe.h b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/perf_probe.h new file mode 100644 index 0000000..ff5026c --- /dev/null +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/perf_probe.h @@ -0,0 +1,98 @@ +/* + * Copyright (C) 2026 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * Kernel-side software performance probes. Copy this file (and perf_probe_events.h) into the + * kernel tree, or add core/models/probe to the include path. + * + * One posted 32-bit store per event, to an address that encodes the hart and the event id + * (perf_probe_events.h). The GVSoC collector decodes it; an RTL testbench snoops the same window, + * so the instrumentation in the kernel is identical for both engines. + * + * EVERYTHING COMPILES AWAY unless the build defines RLC_PROBE=1, so the default binaries stay + * byte-identical. Enable with -DRLC_PROBE=1. + * + * Usage: + * + * #include "perf_probe.h" + * perf_probe_init(); // once per core, before any other probe + * perf_probe_role(PERF_PROBE_ROLE_CONSUMER); + * perf_probe_entity(PROBE_EVT_SDU_RX, uid, node->data_size); + * perf_probe(PROBE_EVT_TTI_BEGIN, tti_index); + * + * The cost is one posted store plus the address arithmetic. In GVSoC the core's LSU hands the + * store straight to the collector (no interconnect traffic, no wait for a response), matching a + * posted store in hardware. Still: put probes at task boundaries (a packet, a PDU, a grant, a + * phase), never inside an inner loop. + */ + +#ifndef PERF_PROBE_H +#define PERF_PROBE_H + +#include +#include "perf_probe_events.h" + +#ifndef RLC_PROBE +#define RLC_PROBE 0 +#endif + +#if RLC_PROBE + +#include + +/* Per-core probe pointer, set ONCE by perf_probe_init() at kernel entry and kept in thread-local + storage (the runtime keeps its own per-core pointers the same way). + + Not recomputed per event on purpose: reading mhartid is a csrr, which Snitch treats as + non-sequenceable -- it waits for the offload sequencer to drain. Issued after a vector copy it + stalls the core until the copy completes, destroying exactly the overlap the kernel relies on + (measured: +8.7% kernel cycles on RLC TC1 with a csrr per event). The hart field is mhartid, the + same id the GVSoC core probes and the hardware barrier use. */ +static __thread volatile uint32_t *perf_probe_ptr; + +static inline void perf_probe_init(void) +{ + perf_probe_ptr = (volatile uint32_t *)(PERF_PROBE_BASE + + (snrt_hartid() << PERF_PROBE_HART_SHIFT)); +} + +/* One event with a plain 32-bit value. A no-op before perf_probe_init() on this core. */ +static inline void perf_probe(uint32_t evt, uint32_t val) +{ + volatile uint32_t *p = perf_probe_ptr; + if (p) p[evt] = val; +} + +/* One event carrying an RLC entity id: value = (entity << 16) | (v & 0xffff). */ +static inline void perf_probe_entity(uint32_t evt, uint32_t entity, uint32_t v) +{ + perf_probe(evt, (entity << PERF_PROBE_ENTITY_SHIFT) | (v & PERF_PROBE_VALUE_MASK)); +} + +static inline void perf_probe_role(uint32_t role) { perf_probe(PROBE_EVT_ROLE, role); } +static inline void perf_probe_phase(uint32_t ph) { perf_probe(PROBE_EVT_PHASE, ph); } + +#else /* !RLC_PROBE โ€” every probe vanishes */ + +#define perf_probe_init() ((void)0) +#define perf_probe(evt, val) ((void)0) +#define perf_probe_entity(evt, entity, v) ((void)0) +#define perf_probe_role(role) ((void)0) +#define perf_probe_phase(ph) ((void)0) + +#endif /* RLC_PROBE */ + +#endif /* PERF_PROBE_H */ diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/perf_probe_events.h b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/perf_probe_events.h new file mode 100644 index 0000000..ecf9ba0 --- /dev/null +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/perf_probe_events.h @@ -0,0 +1,102 @@ +/* + * Copyright (C) 2026 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * Software performance-probe port: the contract between the kernel, the GVSoC collector and + * (later) the RTL testbench. Plain C so the same file compiles into the RISC-V kernel. + * + * address = PERF_PROBE_BASE + (hart << PERF_PROBE_HART_SHIFT) + (event << 2) + * data = 32-bit value; for per-entity events value = (entity << 16) | v16 + * + * A store is self-describing (hart and event come from the address), so it needs no hart-id + * sideband and the layout survives into hardware unchanged. The window sits after the UART in the + * SoC peripheral space: peripheral 0xC000_0000, UART 0xC001_0000, probes 0xC002_0000..0xC005_FFFF. + * + * Keep this file identical in core/models/probe/ and in the kernel tree + * (software/tests/multi_producer_single_consumer_double_linked_list/kernel/). + */ + +#ifndef PERF_PROBE_EVENTS_H +#define PERF_PROBE_EVENTS_H + +#define PERF_PROBE_BASE 0xC0020000u +#define PERF_PROBE_WINDOW_SIZE 0x40000u /* 1024 harts x 64 events x 4 B */ +#define PERF_PROBE_HART_SHIFT 8 +#define PERF_PROBE_NB_EVENTS 64 +#define PERF_PROBE_ENTITY_SHIFT 16 +#define PERF_PROBE_VALUE_MASK 0xFFFFu + +enum perf_probe_evt { + PROBE_EVT_KERNEL_START = 0, /* -- core 0, kernel work phase begins */ + PROBE_EVT_KERNEL_END = 1, /* -- core 0, kernel work phase ends */ + PROBE_EVT_ROLE = 2, /* gauge: 0 idle 1 producer 2 consumer 3 status 4 helper */ + PROBE_EVT_SDU_RX = 3, /* entity | bytes producer enqueued one SDU */ + PROBE_EVT_PDU_TX = 4, /* entity | bytes one PDU assembled / sent */ + PROBE_EVT_GRANT = 5, /* entity | n_pdus AM: one grant committed */ + PROBE_EVT_SEGMENT = 6, /* entity | 1 AM: a PDU carried an SDU segment */ + PROBE_EVT_POLL = 7, /* entity | 1 P bit set on a PDU */ + PROBE_EVT_STATUS_ACK = 8, /* entity | sdus_released STATUS PDU processed */ + PROBE_EVT_QDEPTH = 9, /* gauge: entity | sduNum to-send list depth */ + PROBE_EVT_ACKDEPTH = 10, /* gauge: entity | sduNum wait-ack list depth */ + PROBE_EVT_TTI_BEGIN = 11, /* tti index consumer 0 */ + PROBE_EVT_TTI_END = 12, /* tti index consumer 0 */ + PROBE_EVT_PHASE = 13, /* gauge: 0 plan 1 execute 2 commit 3 barrier 4 idle */ + PROBE_EVT_LOCK_SPIN = 14, /* cycles spent spinning on a list lock */ + PROBE_EVT_MM_LIVE = 15, /* gauge: live nodes after mm_alloc / mm_free */ + PROBE_EVT_UL_TB = 16, /* entity | pdus UL: one transport block scanned */ + PROBE_EVT_UL_DELIVER = 17, /* entity | sdus UL: SDUs delivered in order */ + PROBE_EVT_UL_STATUS = 18, /* entity | bytes UL: STATUS PDU built */ + PROBE_EVT_MARK = 19, /* free-form */ + PROBE_EVT_PKT_IN = 20, /* tag (e.g. node address) SDU entered the entity; opens latency */ + PROBE_EVT_PKT_OUT = 21, /* same tag SDU fully sent; closes latency */ + PROBE_EVT_NB_DEFINED = 22, +}; + +/* Events whose value packs an entity id in the upper 16 bits. */ +#define PERF_PROBE_ENTITY_EVENTS \ + ((1u << PROBE_EVT_SDU_RX) | (1u << PROBE_EVT_PDU_TX) | (1u << PROBE_EVT_GRANT) | \ + (1u << PROBE_EVT_SEGMENT) | (1u << PROBE_EVT_POLL) | (1u << PROBE_EVT_STATUS_ACK) | \ + (1u << PROBE_EVT_QDEPTH) | (1u << PROBE_EVT_ACKDEPTH) | (1u << PROBE_EVT_UL_TB) | \ + (1u << PROBE_EVT_UL_DELIVER) | (1u << PROBE_EVT_UL_STATUS)) + +/* Events that are levels (the last value in a slice is the state), not increments. */ +#define PERF_PROBE_GAUGE_EVENTS \ + ((1u << PROBE_EVT_ROLE) | (1u << PROBE_EVT_QDEPTH) | (1u << PROBE_EVT_ACKDEPTH) | \ + (1u << PROBE_EVT_PHASE) | (1u << PROBE_EVT_MM_LIVE)) + +#define PERF_PROBE_EVENT_NAMES { \ + "kernel_start", "kernel_end", "role", "sdu_rx", "pdu_tx", "grant", "segment", "poll", \ + "status_ack", "qdepth", "ackdepth", "tti_begin", "tti_end", "phase", "lock_spin", "mm_live", \ + "ul_tb", "ul_deliver", "ul_status", "mark", "pkt_in", "pkt_out" } + +#define PERF_PROBE_ROLE_IDLE 0 +#define PERF_PROBE_ROLE_PRODUCER 1 +#define PERF_PROBE_ROLE_CONSUMER 2 +#define PERF_PROBE_ROLE_STATUS 3 +#define PERF_PROBE_ROLE_HELPER 4 + +/* PHASE values. The collector integrates time spent in each (sw_state.csv), so a hart's phase is + a state: emit on transitions only, never once per loop iteration. */ +#define PERF_PROBE_PHASE_PLAN 0 /* AM: grant planning */ +#define PERF_PROBE_PHASE_EXECUTE 1 /* assembling / copying a PDU */ +#define PERF_PROBE_PHASE_COMMIT 2 /* AM: grant commit */ +#define PERF_PROBE_PHASE_BARRIER 3 /* waiting at a (partial) barrier */ +#define PERF_PROBE_PHASE_IDLE 4 /* polling, nothing to do */ +#define PERF_PROBE_PHASE_RECEIVE 5 /* producer: taking a PDCP packet, enqueueing an SDU */ +#define PERF_PROBE_PHASE_STATUS 6 /* STATUS PDU processing (ACK release) */ +#define PERF_PROBE_PHASE_DONE 7 /* role finished, waiting for the others */ + +#endif /* PERF_PROBE_EVENTS_H */ diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.c b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.c index c0527ca..9ff8b71 100644 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.c +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.c @@ -61,6 +61,18 @@ #include #include "benchmark.h" +/* Software performance probes (gvsoc prompt/perf_probe_design.md). Every call below compiles to + nothing unless the build defines RLC_PROBE=1, so default ELFs are unchanged. */ +#include "perf_probe.h" +#if RLC_PROBE +/* PHASE is a state: store only on transitions, never once per loop iteration. */ +static inline void rlc_probe_phase_to(uint32_t *cur, uint32_t ph) { + if (*cur != ph) { *cur = ph; perf_probe_phase(ph); } +} +#define RLC_PROBE_PHASE_TO(cur, ph) rlc_probe_phase_to(&(cur), (ph)) +#else +#define RLC_PROBE_PHASE_TO(cur, ph) ((void)0) +#endif // volatile: these structs model memory traffic (status indications/reports); // their loaded values are intentionally unused, so without volatile the @@ -433,6 +445,7 @@ void ue_status_rpt(const unsigned int core_id) ctx->nackcount = 0; ctx->parseindex++; atomic_store_explicit(&ctx->vtNextAck, ACK_SN, memory_order_relaxed); // Update the next ACK sequence number + perf_probe_entity(PROBE_EVT_STATUS_ACK, u, 2u); for (uint32_t i = 0; i < 16; i++) { ctx->dlDelayInfo[i] = 300; } @@ -450,6 +463,10 @@ static int rlc_send_pkt(const unsigned int core_id, rlc_context_t *ctx, TestData if (node == 0) { return 0; } + /* No queue-depth gauges here: reading list.sduNum means a load on the line every core + contends for, and it measurably slowed the kernel it was measuring. Depth is rebuilt from + the SDU_RX / PDU_TX / STATUS_ACK counts instead. */ + perf_probe_phase(PERF_PROBE_PHASE_EXECUTE); #ifdef RLC_NODE_GUARD if (((uintptr_t)node->data & 0xFF000000) != 0xA0000000 || ((uintptr_t)node->tgt & 0xFF000000) != 0xB0000000 || @@ -520,6 +537,8 @@ static int rlc_send_pkt(const unsigned int core_id, rlc_context_t *ctx, TestData // (node->data_size * 1000 / (timer_mv_1 - timer_mv_0))); // DEBUG_PRINTF_LOCK_RELEASE(&printf_lock); + perf_probe_entity(PROBE_EVT_PDU_TX, u, (uint32_t)node->data_size); + perf_probe(PROBE_EVT_PKT_OUT, (uint32_t)(uintptr_t)node); // Add the node to the sent list list_push_back((spinlock_t *)&sent_llist_lock_2[u], &ctx->sent_list, node); return 1; @@ -577,6 +596,9 @@ static void consumer(const unsigned int core_id) { const unsigned int first = c % stride; /* first owned user */ unsigned int cursor = first; uint32_t total_cycle = RLC_TOTAL_CYCLE(CONSUMER_CORE_NUM, OUTPUT_DATARATE); +#if RLC_PROBE + uint32_t probe_ph = 0xffffffffu; +#endif while (1) { uint32_t start_timecycle = benchmark_get_cycle(); TestDataStru dfx = {0}; @@ -589,6 +611,10 @@ static void consumer(const unsigned int core_id) { if (!sent) { u += stride; if (u >= NUM_USERS) u = first; } } while (!sent && u != cursor); if (sent) { u += stride; if (u >= NUM_USERS) u = first; cursor = u; } +#if RLC_PROBE + if (sent) probe_ph = PERF_PROBE_PHASE_EXECUTE; /* rlc_send_pkt stored it */ + else RLC_PROBE_PHASE_TO(probe_ph, PERF_PROBE_PHASE_IDLE); +#endif uint32_t end_timecycle = benchmark_get_cycle(); /* calculate delay interval */ uint32_t interval = end_timecycle - start_timecycle; @@ -707,6 +733,10 @@ static int producer(const unsigned int core_id) { // /* Zero-initialize the payload using our custom mm_memset */ // mm_memset(node->data, 0, PACKET_SIZE); /* Append the node to the owning entity's to-send list */ +#if RLC_TB_MODE != RLC_TB_MODE_AM + perf_probe(PROBE_EVT_PKT_IN, (uint32_t)(uintptr_t)node); +#endif + perf_probe_entity(PROBE_EVT_SDU_RX, uid, (uint32_t)node->data_size); list_push_back((spinlock_t *)&tosend_llist_lock_2[uid], &ctx->list, node); #if (RLC_TB_MODE == RLC_TB_MODE_AM) && RLC_AM_WORKQ /* Announce the entity so an owner picks it up without scanning. */ @@ -739,8 +769,14 @@ static void pkt_production_and_recycle(const unsigned int core_id) { uint32_t total_cycle = RLC_TOTAL_CYCLE(PRODUCER_CORE_NUM, INPUT_DATARATE); int this_core_done = 0; +#if RLC_PROBE + uint32_t probe_ph = 0xffffffffu; +#endif while (1) { uint32_t start_timecycle = benchmark_get_cycle(); +#if RLC_PROBE + RLC_PROBE_PHASE_TO(probe_ph, this_core_done ? PERF_PROBE_PHASE_DONE : PERF_PROBE_PHASE_RECEIVE); +#endif if (!this_core_done) { if (producer(core_id) < 0) { this_core_done = 1; @@ -751,8 +787,14 @@ static void pkt_production_and_recycle(const unsigned int core_id) the list, not core 0: with explicit core lists core 0 need not be a producer at all, and gating on it would drop the ACK task entirely. */ if (core_id == rlc_status_core()) { +#if RLC_PROBE + if (!this_core_done) RLC_PROBE_PHASE_TO(probe_ph, PERF_PROBE_PHASE_STATUS); +#endif ue_status_rpt(core_id); } +#if RLC_PROBE + RLC_PROBE_PHASE_TO(probe_ph, this_core_done ? PERF_PROBE_PHASE_DONE : PERF_PROBE_PHASE_IDLE); +#endif uint32_t end_timecycle = benchmark_get_cycle(); /* calculate delay interval */ uint32_t interval = end_timecycle - start_timecycle; @@ -776,14 +818,21 @@ static void pkt_production_and_recycle(const unsigned int core_id) the shared barrier below. */ void cluster_entry(const unsigned int core_id) { uint32_t timer_0, timer_1; + perf_probe_init(); timer_0 = benchmark_get_cycle(); if(core_id == 0) { start_kernel(); + perf_probe(PROBE_EVT_KERNEL_START, 0u); } const int is_consumer = rlc_is_consumer(core_id); const int is_producer = rlc_is_producer(core_id); +#if RLC_PROBE + perf_probe_role(is_producer ? PERF_PROBE_ROLE_PRODUCER : + is_consumer ? PERF_PROBE_ROLE_CONSUMER : PERF_PROBE_ROLE_IDLE); + if (!is_producer && !is_consumer) perf_probe_phase(PERF_PROBE_PHASE_BARRIER); +#endif if (is_producer) { pkt_production_and_recycle(core_id); @@ -797,9 +846,15 @@ void cluster_entry(const unsigned int core_id) { whichever request arrives first owns a tile's round, and barrier_done is an unmasked cluster-wide broadcast. So they wait here, outside any barrier, until the mask has been restored. See rlc_sync.h. */ +#if RLC_PROBE + if (!is_consumer) perf_probe_phase(PERF_PROBE_PHASE_DONE); +#endif if (!is_consumer) rlc_narrow_wait_outside(); #endif +#if RLC_PROBE + if (is_producer || is_consumer) perf_probe_phase(PERF_PROBE_PHASE_BARRIER); +#endif snrt_cluster_hw_barrier(); // this can trigger Misaligned Load exception #if RLC_TB_MODE == RLC_TB_MODE_AM @@ -817,6 +872,7 @@ void cluster_entry(const unsigned int core_id) { #endif if(core_id == 0) { + perf_probe(PROBE_EVT_KERNEL_END, 0u); stop_kernel(); } diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.c b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.c index 0d8a6dd..5a89651 100644 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.c +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.c @@ -419,6 +419,14 @@ static void rlc_am_commit(uint32_t u) { e->pdus += n; e->polls += polls; e->segments += segs; + /* One grant: n PDUs carrying `bytes` of payload. In AM, PDU_TX is one event per grant whose + value is the grant's payload bytes; the PDU count comes from GRANT. */ +#if RLC_PROBE + perf_probe_entity(PROBE_EVT_GRANT, u, n); + perf_probe_entity(PROBE_EVT_PDU_TX, u, (uint32_t)bytes); + if (segs) perf_probe_entity(PROBE_EVT_SEGMENT, u, segs); + if (polls) perf_probe_entity(PROBE_EVT_POLL, u, polls); +#endif #ifdef RLC_SELF_CHECK rlc_am_verify_grant(u); @@ -577,16 +585,24 @@ void rlc_am_consumer_tti(uint32_t core_id) { #if RLC_TTI_CYCLES const uint32_t tti_start = benchmark_get_cycle(); #endif + if (me == 0u) perf_probe(PROBE_EVT_TTI_BEGIN, rlc_am_ttis); + perf_probe_phase(PERF_PROBE_PHASE_PLAN); rlc_am_plan_phase(me); + perf_probe_phase(PERF_PROBE_PHASE_BARRIER); rlc_phase_barrier(mask); /* helpers BLOCK here; fenced -- see rlc_sync.h */ + perf_probe_phase(PERF_PROBE_PHASE_EXECUTE); rlc_am_execute_phase(); + perf_probe_phase(PERF_PROBE_PHASE_BARRIER); rlc_phase_barrier(mask); + perf_probe_phase(PERF_PROBE_PHASE_COMMIT); rlc_am_commit_phase(me); + perf_probe_phase(PERF_PROBE_PHASE_BARRIER); rlc_phase_barrier(mask); if (me == 0u) { + perf_probe(PROBE_EVT_TTI_END, rlc_am_ttis); rlc_am_ttis++; atomic_store_explicit(&rlc_am_stop, (atomic_load_explicit(&producer_done, memory_order_relaxed) >= @@ -829,6 +845,9 @@ void rlc_am_status(void) { ctx->acksn = got_ack_sn; ctx->nackcount = 0u; if (freed) ctx->parseindex++; +#if RLC_PROBE + if (freed) perf_probe_entity(PROBE_EVT_STATUS_ACK, u, freed); +#endif } } From a1d54b1369390949b58cedb24209660b945ea66c Mon Sep 17 00:00:00 2001 From: Zexin Fu Date: Tue, 22 Sep 2026 21:00:19 +0200 Subject: [PATCH 32/48] rlc: full-cluster DP test cases (TC1/TC2/TC3, 64 producers + 192 consumers), probe targets --- .../data/.gitignore | 2 + .../script/pdcp_pkg_1_1350_1157_p64_c192.json | 270 ++++++++++++++++++ .../pdcp_pkg_4800_800_1963_p64_c192.json | 270 ++++++++++++++++++ .../script/pdcp_pkg_48_800_4882_p64_c192.json | 270 ++++++++++++++++++ 4 files changed, 812 insertions(+) create mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/data/.gitignore create mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_1_1350_1157_p64_c192.json create mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_4800_800_1963_p64_c192.json create mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_48_800_4882_p64_c192.json diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/data/.gitignore b/software/rlc/multi_producer_single_consumer_double_linked_list/data/.gitignore new file mode 100644 index 0000000..ea577c8 --- /dev/null +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/data/.gitignore @@ -0,0 +1,2 @@ +# Generated at build time from ../script/pdcp_pkg_*_p

_c.json (see software/tests/CMakeLists.txt) +data_*_p*_c*.h diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_1_1350_1157_p64_c192.json b/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_1_1350_1157_p64_c192.json new file mode 100644 index 0000000..f132fc9 --- /dev/null +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_1_1350_1157_p64_c192.json @@ -0,0 +1,270 @@ +{ + "active_user_number": 1, + "pkg_length": 1350, + "pdcp_header_length": 10, + "src_addr": "0xA0000000", + "src_length": 16777216, + "tgt_addr": "0xB0000000", + "tgt_length": 16777216, + "total_pkg_number": 1157, + "producer_cores": [ + 0, + 4, + 8, + 12, + 16, + 20, + 24, + 28, + 32, + 36, + 40, + 44, + 48, + 52, + 56, + 60, + 64, + 68, + 72, + 76, + 80, + 84, + 88, + 92, + 96, + 100, + 104, + 108, + 112, + 116, + 120, + 124, + 128, + 132, + 136, + 140, + 144, + 148, + 152, + 156, + 160, + 164, + 168, + 172, + 176, + 180, + 184, + 188, + 192, + 196, + 200, + 204, + 208, + 212, + 216, + 220, + 224, + 228, + 232, + 236, + 240, + 244, + 248, + 252 + ], + "consumer_cores": [ + 1, + 2, + 3, + 5, + 6, + 7, + 9, + 10, + 11, + 13, + 14, + 15, + 17, + 18, + 19, + 21, + 22, + 23, + 25, + 26, + 27, + 29, + 30, + 31, + 33, + 34, + 35, + 37, + 38, + 39, + 41, + 42, + 43, + 45, + 46, + 47, + 49, + 50, + 51, + 53, + 54, + 55, + 57, + 58, + 59, + 61, + 62, + 63, + 65, + 66, + 67, + 69, + 70, + 71, + 73, + 74, + 75, + 77, + 78, + 79, + 81, + 82, + 83, + 85, + 86, + 87, + 89, + 90, + 91, + 93, + 94, + 95, + 97, + 98, + 99, + 101, + 102, + 103, + 105, + 106, + 107, + 109, + 110, + 111, + 113, + 114, + 115, + 117, + 118, + 119, + 121, + 122, + 123, + 125, + 126, + 127, + 129, + 130, + 131, + 133, + 134, + 135, + 137, + 138, + 139, + 141, + 142, + 143, + 145, + 146, + 147, + 149, + 150, + 151, + 153, + 154, + 155, + 157, + 158, + 159, + 161, + 162, + 163, + 165, + 166, + 167, + 169, + 170, + 171, + 173, + 174, + 175, + 177, + 178, + 179, + 181, + 182, + 183, + 185, + 186, + 187, + 189, + 190, + 191, + 193, + 194, + 195, + 197, + 198, + 199, + 201, + 202, + 203, + 205, + 206, + 207, + 209, + 210, + 211, + 213, + 214, + 215, + 217, + 218, + 219, + 221, + 222, + 223, + 225, + 226, + 227, + 229, + 230, + 231, + 233, + 234, + 235, + 237, + 238, + 239, + 241, + 242, + 243, + 245, + 246, + 247, + 249, + 250, + 251, + 253, + 254, + 255 + ] +} diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_4800_800_1963_p64_c192.json b/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_4800_800_1963_p64_c192.json new file mode 100644 index 0000000..cc894b5 --- /dev/null +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_4800_800_1963_p64_c192.json @@ -0,0 +1,270 @@ +{ + "active_user_number": 4800, + "pkg_length": 800, + "pdcp_header_length": 10, + "src_addr": "0xA0000000", + "src_length": 16777216, + "tgt_addr": "0xB0000000", + "tgt_length": 16777216, + "total_pkg_number": 1963, + "producer_cores": [ + 0, + 4, + 8, + 12, + 16, + 20, + 24, + 28, + 32, + 36, + 40, + 44, + 48, + 52, + 56, + 60, + 64, + 68, + 72, + 76, + 80, + 84, + 88, + 92, + 96, + 100, + 104, + 108, + 112, + 116, + 120, + 124, + 128, + 132, + 136, + 140, + 144, + 148, + 152, + 156, + 160, + 164, + 168, + 172, + 176, + 180, + 184, + 188, + 192, + 196, + 200, + 204, + 208, + 212, + 216, + 220, + 224, + 228, + 232, + 236, + 240, + 244, + 248, + 252 + ], + "consumer_cores": [ + 1, + 2, + 3, + 5, + 6, + 7, + 9, + 10, + 11, + 13, + 14, + 15, + 17, + 18, + 19, + 21, + 22, + 23, + 25, + 26, + 27, + 29, + 30, + 31, + 33, + 34, + 35, + 37, + 38, + 39, + 41, + 42, + 43, + 45, + 46, + 47, + 49, + 50, + 51, + 53, + 54, + 55, + 57, + 58, + 59, + 61, + 62, + 63, + 65, + 66, + 67, + 69, + 70, + 71, + 73, + 74, + 75, + 77, + 78, + 79, + 81, + 82, + 83, + 85, + 86, + 87, + 89, + 90, + 91, + 93, + 94, + 95, + 97, + 98, + 99, + 101, + 102, + 103, + 105, + 106, + 107, + 109, + 110, + 111, + 113, + 114, + 115, + 117, + 118, + 119, + 121, + 122, + 123, + 125, + 126, + 127, + 129, + 130, + 131, + 133, + 134, + 135, + 137, + 138, + 139, + 141, + 142, + 143, + 145, + 146, + 147, + 149, + 150, + 151, + 153, + 154, + 155, + 157, + 158, + 159, + 161, + 162, + 163, + 165, + 166, + 167, + 169, + 170, + 171, + 173, + 174, + 175, + 177, + 178, + 179, + 181, + 182, + 183, + 185, + 186, + 187, + 189, + 190, + 191, + 193, + 194, + 195, + 197, + 198, + 199, + 201, + 202, + 203, + 205, + 206, + 207, + 209, + 210, + 211, + 213, + 214, + 215, + 217, + 218, + 219, + 221, + 222, + 223, + 225, + 226, + 227, + 229, + 230, + 231, + 233, + 234, + 235, + 237, + 238, + 239, + 241, + 242, + 243, + 245, + 246, + 247, + 249, + 250, + 251, + 253, + 254, + 255 + ] +} diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_48_800_4882_p64_c192.json b/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_48_800_4882_p64_c192.json new file mode 100644 index 0000000..d913536 --- /dev/null +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_48_800_4882_p64_c192.json @@ -0,0 +1,270 @@ +{ + "active_user_number": 48, + "pkg_length": 800, + "pdcp_header_length": 10, + "src_addr": "0xA0000000", + "src_length": 16777216, + "tgt_addr": "0xB0000000", + "tgt_length": 16777216, + "total_pkg_number": 4882, + "producer_cores": [ + 0, + 4, + 8, + 12, + 16, + 20, + 24, + 28, + 32, + 36, + 40, + 44, + 48, + 52, + 56, + 60, + 64, + 68, + 72, + 76, + 80, + 84, + 88, + 92, + 96, + 100, + 104, + 108, + 112, + 116, + 120, + 124, + 128, + 132, + 136, + 140, + 144, + 148, + 152, + 156, + 160, + 164, + 168, + 172, + 176, + 180, + 184, + 188, + 192, + 196, + 200, + 204, + 208, + 212, + 216, + 220, + 224, + 228, + 232, + 236, + 240, + 244, + 248, + 252 + ], + "consumer_cores": [ + 1, + 2, + 3, + 5, + 6, + 7, + 9, + 10, + 11, + 13, + 14, + 15, + 17, + 18, + 19, + 21, + 22, + 23, + 25, + 26, + 27, + 29, + 30, + 31, + 33, + 34, + 35, + 37, + 38, + 39, + 41, + 42, + 43, + 45, + 46, + 47, + 49, + 50, + 51, + 53, + 54, + 55, + 57, + 58, + 59, + 61, + 62, + 63, + 65, + 66, + 67, + 69, + 70, + 71, + 73, + 74, + 75, + 77, + 78, + 79, + 81, + 82, + 83, + 85, + 86, + 87, + 89, + 90, + 91, + 93, + 94, + 95, + 97, + 98, + 99, + 101, + 102, + 103, + 105, + 106, + 107, + 109, + 110, + 111, + 113, + 114, + 115, + 117, + 118, + 119, + 121, + 122, + 123, + 125, + 126, + 127, + 129, + 130, + 131, + 133, + 134, + 135, + 137, + 138, + 139, + 141, + 142, + 143, + 145, + 146, + 147, + 149, + 150, + 151, + 153, + 154, + 155, + 157, + 158, + 159, + 161, + 162, + 163, + 165, + 166, + 167, + 169, + 170, + 171, + 173, + 174, + 175, + 177, + 178, + 179, + 181, + 182, + 183, + 185, + 186, + 187, + 189, + 190, + 191, + 193, + 194, + 195, + 197, + 198, + 199, + 201, + 202, + 203, + 205, + 206, + 207, + 209, + 210, + 211, + 213, + 214, + 215, + 217, + 218, + 219, + 221, + 222, + 223, + 225, + 226, + 227, + 229, + 230, + 231, + 233, + 234, + 235, + 237, + 238, + 239, + 241, + 242, + 243, + 245, + 246, + 247, + 249, + 250, + 251, + 253, + 254, + 255 + ] +} From 63f43590757134ac109b5645121e1e517a4b0bde Mon Sep 17 00:00:00 2001 From: Zexin Fu Date: Tue, 22 Sep 2026 21:13:59 +0200 Subject: [PATCH 33/48] rlc: lock/flag cache-line padding (RLC_PAD_SYNC), paced arrival (RLC_ARRIVAL_PPS), multi-slot sweep targets --- .../kernel/llist.h | 21 ++ .../kernel/mm.h | 7 +- .../kernel/perf_probe_events.h | 6 +- .../kernel/rlc.c | 30 +- .../kernel/rlc.h | 41 ++- .../kernel/rlc_am.c | 10 +- .../main.c | 4 +- .../script/generate_pdcp_pkg.py | 11 +- .../script/pdcp_pkg_1_1350_9256_p16_c48.json | 79 +++++ .../script/pdcp_pkg_1_1350_9256_p2_c2.json | 19 ++ .../script/pdcp_pkg_1_1350_9256_p64_c192.json | 271 ++++++++++++++++++ .../pdcp_pkg_4800_800_15704_p16_c48.json | 79 +++++ .../script/pdcp_pkg_4800_800_15704_p2_c2.json | 19 ++ .../pdcp_pkg_4800_800_15704_p64_c192.json | 271 ++++++++++++++++++ .../script/pdcp_pkg_48_800_19528_p16_c48.json | 79 +++++ .../script/pdcp_pkg_48_800_19528_p2_c2.json | 19 ++ .../pdcp_pkg_48_800_19528_p64_c192.json | 271 ++++++++++++++++++ 17 files changed, 1217 insertions(+), 20 deletions(-) create mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_1_1350_9256_p16_c48.json create mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_1_1350_9256_p2_c2.json create mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_1_1350_9256_p64_c192.json create mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_4800_800_15704_p16_c48.json create mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_4800_800_15704_p2_c2.json create mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_4800_800_15704_p64_c192.json create mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_48_800_19528_p16_c48.json create mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_48_800_19528_p2_c2.json create mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_48_800_19528_p64_c192.json diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/llist.h b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/llist.h index e4986d6..e425183 100644 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/llist.h +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/llist.h @@ -29,6 +29,27 @@ /* We use a volatile int as a spinlock. Zero means unlocked. */ typedef volatile int spinlock_t __attribute__((aligned(4))); +/* RLC_PAD_SYNC=1 gives every lock and every cross-core flag a cache line of its own, and lets an + idle consumer look at a queue before locking it. Default 0 keeps the historical layout. + + Why it matters: in the default layout one 64 B line holds the descriptor lock every producer + takes per packet, `producer_done` which every core polls every iteration, and the per-user list + locks, all 48 of TC2's in about three lines. At 256 cores every lock operation and every poll + hits the same few lines; measured on GVSoC 4x4, TC1 ran 9x slower on 256 cores than on 4. */ +#ifndef RLC_PAD_SYNC +#define RLC_PAD_SYNC 0 +#endif +#define RLC_SYNC_LINE_BYTES 64 +/* Declares `name` in .data; with RLC_PAD_SYNC it is the only thing on its cache line (the name + then refers to `name##_line.v` through a #define placed next to the declaration). */ +#if RLC_PAD_SYNC +#define RLC_LINE_VAR(type, name) \ + struct { type v; char pad[RLC_SYNC_LINE_BYTES - sizeof(type)]; } name##_line \ + __attribute__((aligned(RLC_SYNC_LINE_BYTES))) __attribute__((section(".data"))) +#else +#define RLC_LINE_VAR(type, name) type name __attribute__((section(".data"))) +#endif + spinlock_t tosend_llist_lock __attribute__((section(".data"))); spinlock_t sent_llist_lock __attribute__((section(".data"))); /* Per-user mcs locks (tosend_llist_lock_2[NUM_USERS] / sent_llist_lock_2[NUM_USERS]) diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/mm.h b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/mm.h index d01ebd2..f037afa 100644 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/mm.h +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/mm.h @@ -34,7 +34,10 @@ static uint32_t bulk_buffer[BUFFER_SIZE / sizeof(uint32_t)] __attribute__((section(".dram"))) __attribute__((aligned(32))); -spinlock_t mm_lock __attribute__((section(".data"))); +RLC_LINE_VAR(spinlock_t, mm_lock); +#if RLC_PAD_SYNC +#define mm_lock (mm_lock_line.v) +#endif /* Type for free list entries */ typedef struct MM_FreePage { @@ -49,6 +52,8 @@ typedef struct { spinlock_t lock; /* Spinlock for mutual exclusion */ } mm_context_t __attribute__((aligned(8))); +/* Not given its own line: the name is also a parameter and a struct field, and every hot + neighbour it could share a line with already has one of its own under RLC_PAD_SYNC. */ mm_context_t mm_ctx __attribute__((section(".data"))); /* diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/perf_probe_events.h b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/perf_probe_events.h index ecf9ba0..cae687b 100644 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/perf_probe_events.h +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/perf_probe_events.h @@ -62,7 +62,9 @@ enum perf_probe_evt { PROBE_EVT_MARK = 19, /* free-form */ PROBE_EVT_PKT_IN = 20, /* tag (e.g. node address) SDU entered the entity; opens latency */ PROBE_EVT_PKT_OUT = 21, /* same tag SDU fully sent; closes latency */ - PROBE_EVT_NB_DEFINED = 22, + PROBE_EVT_PKT_LATE = 22, /* cycles since this hart's next packet arrived (paced */ + /* arrival); the collector back-dates the next PKT_IN to it */ + PROBE_EVT_NB_DEFINED = 23, }; /* Events whose value packs an entity id in the upper 16 bits. */ @@ -80,7 +82,7 @@ enum perf_probe_evt { #define PERF_PROBE_EVENT_NAMES { \ "kernel_start", "kernel_end", "role", "sdu_rx", "pdu_tx", "grant", "segment", "poll", \ "status_ack", "qdepth", "ackdepth", "tti_begin", "tti_end", "phase", "lock_spin", "mm_live", \ - "ul_tb", "ul_deliver", "ul_status", "mark", "pkt_in", "pkt_out" } + "ul_tb", "ul_deliver", "ul_status", "mark", "pkt_in", "pkt_out", "pkt_late" } #define PERF_PROBE_ROLE_IDLE 0 #define PERF_PROBE_ROLE_PRODUCER 1 diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.c b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.c index 9ff8b71..b0a9612 100644 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.c +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.c @@ -224,6 +224,11 @@ int __attribute__((noinline)) pdcp_receive_pkg(const unsigned int core_id, volat // If the pointer is within bounds, return the package pointer pkg_ptr = pdcp_pkd_ptr; pdcp_pkd_ptr++; // Increment the pointer for the next package +#if RLC_ARRIVAL_PPS + /* The arrival clock starts with the first descriptor. Set under the lock, so every later + taker (who acquires the lock after this release) sees it. */ + if (pkg_ptr == 0) rlc_arrival_t0 = benchmark_get_cycle(); +#endif } else { DEBUG_PRINTF_LOCK_ACQUIRE(&printf_lock); DEBUG_PRINTF("Producer (core %u): out of PDCP pkg, pdcp_pkd_ptr = %d\n", core_id, pdcp_pkd_ptr); @@ -427,7 +432,7 @@ void ue_status_rpt(const unsigned int core_id) for (int i = vtNextAck; i < ACK_SN; i++) { char ack = ue_status_rpt_content.stateRpt[16 + ACK_SN - i]; - Node *sent_node = list_pop_front((spinlock_t *)&sent_llist_lock_2[u], &ctx->sent_list); + Node *sent_node = list_pop_front((spinlock_t *)RLC_SENT_LOCK(u), &ctx->sent_list); if (sent_node != NULL) { // DEBUG_PRINTF_LOCK_ACQUIRE(&printf_lock); // DEBUG_PRINTF("[core %u][consumer] pop sent_list, ACK_SN=%d, SN=%d, sent node %p, data_size=%zu\n", @@ -459,7 +464,12 @@ void ue_status_rpt(const unsigned int core_id) static int rlc_send_pkt(const unsigned int core_id, rlc_context_t *ctx, TestDataStru *testData) { const unsigned int u = (unsigned int)(ctx - rlc_ctx); // lock-free user index - Node *node = list_pop_front((spinlock_t *)&tosend_llist_lock_2[u], &ctx->list); +#if RLC_PAD_SYNC + /* Look before locking: an idle consumer otherwise takes the lock (an atomic swap) on every + poll of an empty queue. A plain load; a push that lands just after is seen next pass. */ + if (ctx->list.sduNum == 0) return 0; +#endif + Node *node = list_pop_front((spinlock_t *)RLC_TOSEND_LOCK(u), &ctx->list); if (node == 0) { return 0; } @@ -540,7 +550,7 @@ static int rlc_send_pkt(const unsigned int core_id, rlc_context_t *ctx, TestData perf_probe_entity(PROBE_EVT_PDU_TX, u, (uint32_t)node->data_size); perf_probe(PROBE_EVT_PKT_OUT, (uint32_t)(uintptr_t)node); // Add the node to the sent list - list_push_back((spinlock_t *)&sent_llist_lock_2[u], &ctx->sent_list, node); + list_push_back((spinlock_t *)RLC_SENT_LOCK(u), &ctx->sent_list, node); return 1; } @@ -651,6 +661,18 @@ static int producer(const unsigned int core_id) { if (new_pdcp_pkg_ptr < 0) { return -1; // No more packages } +#if RLC_ARRIVAL_PPS + /* Wait for this packet's arrival time. Q8 fixed-point period keeps the math in 64-bit + multiplies (no 64-bit divide on rv32). */ + const uint64_t rlc_period_q8 = ((uint64_t)CPU_FREQENCY << 8) / RLC_ARRIVAL_PPS; + const uint32_t due = rlc_arrival_t0 + (uint32_t)(((uint64_t)new_pdcp_pkg_ptr * rlc_period_q8) >> 8); + uint32_t now_cyc; + while ((int32_t)((now_cyc = benchmark_get_cycle()) - due) < 0) { } + /* How long ago it arrived; the collector back-dates this packet's PKT_IN by it. Sent here, + from the cycle already read, not later: a csrr after the vector header copy would wait for + the vector unit to drain. */ + perf_probe(PROBE_EVT_PKT_LATE, now_cyc - due); +#endif /* Route the package to its owning RLC entity (one per UE). */ const unsigned int uid = (unsigned int)pdcp_pkgs[new_pdcp_pkg_ptr].user_id; @@ -737,7 +759,7 @@ static int producer(const unsigned int core_id) { perf_probe(PROBE_EVT_PKT_IN, (uint32_t)(uintptr_t)node); #endif perf_probe_entity(PROBE_EVT_SDU_RX, uid, (uint32_t)node->data_size); - list_push_back((spinlock_t *)&tosend_llist_lock_2[uid], &ctx->list, node); + list_push_back((spinlock_t *)RLC_TOSEND_LOCK(uid), &ctx->list, node); #if (RLC_TB_MODE == RLC_TB_MODE_AM) && RLC_AM_WORKQ /* Announce the entity so an owner picks it up without scanning. */ rlc_am_mark_ready(uid); diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.h b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.h index dc74187..3cfce7b 100644 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.h +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.h @@ -46,9 +46,31 @@ #define RLC_ENABLE_PACING 0 #endif +/* Paced arrival. 0 (default): every descriptor is available at t=0 (a burst). N: descriptor i + arrives at t0 + i * CPU_FREQ / N cycles, t0 = when the first descriptor is taken, so the + offered load is N packets/s -- the DP test case's rate. A producer holding a descriptor that + has not arrived yet waits for it. Latency is then measured from the arrival time, so a + producer that falls behind shows up as latency, not as a lower offered rate. */ +#ifndef RLC_ARRIVAL_PPS +#define RLC_ARRIVAL_PPS 0 +#endif + /* Per-user list locks (indexed by RLC entity / user id). */ +#if RLC_PAD_SYNC +typedef struct { + _Atomic mcs_lock_t l; + char pad[RLC_SYNC_LINE_BYTES - sizeof(mcs_lock_t)]; +} rlc_lock_line_t; +static rlc_lock_line_t tosend_llist_lock_2_line[NUM_USERS] __attribute__((aligned(RLC_SYNC_LINE_BYTES))) __attribute__((section(".data"))); +static rlc_lock_line_t sent_llist_lock_2_line[NUM_USERS] __attribute__((aligned(RLC_SYNC_LINE_BYTES))) __attribute__((section(".data"))); +#define RLC_TOSEND_LOCK(u) (&tosend_llist_lock_2_line[u].l) +#define RLC_SENT_LOCK(u) (&sent_llist_lock_2_line[u].l) +#else static _Atomic mcs_lock_t tosend_llist_lock_2[NUM_USERS] __attribute__((aligned(4))) __attribute__((section(".data"))); static _Atomic mcs_lock_t sent_llist_lock_2[NUM_USERS] __attribute__((aligned(4))) __attribute__((section(".data"))); +#define RLC_TOSEND_LOCK(u) (&tosend_llist_lock_2[u]) +#define RLC_SENT_LOCK(u) (&sent_llist_lock_2[u]) +#endif typedef struct { @@ -185,10 +207,21 @@ void cluster_entry(const unsigned int core_id); /* pdcp_pkd_ptr is a pointer to the new PDCP packet data structure. */ -spinlock_t pdcp_pkd_ptr __attribute__((section(".data"))); -mcs_lock_t pdcp_pkd_ptr_lock __attribute__((section(".data"))); - -_Atomic(uint32_t) producer_done __attribute__((section(".data"))); +RLC_LINE_VAR(spinlock_t, pdcp_pkd_ptr); +RLC_LINE_VAR(mcs_lock_t, pdcp_pkd_ptr_lock); + +RLC_LINE_VAR(_Atomic(uint32_t), producer_done); +#if RLC_ARRIVAL_PPS +RLC_LINE_VAR(uint32_t, rlc_arrival_t0); +#if RLC_PAD_SYNC +#define rlc_arrival_t0 (rlc_arrival_t0_line.v) +#endif +#endif +#if RLC_PAD_SYNC +#define pdcp_pkd_ptr (pdcp_pkd_ptr_line.v) +#define pdcp_pkd_ptr_lock (pdcp_pkd_ptr_lock_line.v) +#define producer_done (producer_done_line.v) +#endif /* Number of producer cores that have finished; producer_done is only set once this reaches NUM_PRODUCER_CORES, so multiple producers don't cause the consumer(s) to exit early when just the first one finishes. */ diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.c b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.c index 5a89651..bb3d8ff 100644 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.c +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.c @@ -256,7 +256,7 @@ static int rlc_am_try_plan(uint32_t u) { the walk can only ever stop later than strictly necessary, never early. */ unsigned int reached_end = 0u; const uint32_t avail = list_peek_budget( - (spinlock_t *)&tosend_llist_lock_2[u], &ctx->list, peek, + (spinlock_t *)RLC_TOSEND_LOCK(u), &ctx->list, peek, RLC_MAX_PDUS_PER_GRANT, RLC_GRANT_BYTES + e->so_next, RLC_AMD_HDR_MIN, &reached_end); e->peek_done++; /* distinguishes "blocked in the peek" from "peek was empty" */ @@ -389,7 +389,7 @@ static void rlc_am_commit(uint32_t u) { uint32_t retire = 0u; for (uint32_t i = 0u; i < n; i++) { if (!p->last_seg[i]) continue; - Node *node = list_pop_front((spinlock_t *)&tosend_llist_lock_2[u], + Node *node = list_pop_front((spinlock_t *)RLC_TOSEND_LOCK(u), &ctx->list); if (node == NULL) { DEBUG_PRINTF_LOCK_ACQUIRE(&printf_lock); @@ -398,7 +398,7 @@ static void rlc_am_commit(uint32_t u) { break; } node->last_sn = p->sn[i]; - list_push_back((spinlock_t *)&sent_llist_lock_2[u], &ctx->sent_list, node); + list_push_back((spinlock_t *)RLC_SENT_LOCK(u), &ctx->sent_list, node); retire++; } @@ -829,12 +829,12 @@ void rlc_am_status(void) { uint32_t freed = 0u; while (1) { Node *head = NULL; - if (list_peek_n((spinlock_t *)&sent_llist_lock_2[u], &ctx->sent_list, + if (list_peek_n((spinlock_t *)RLC_SENT_LOCK(u), &ctx->sent_list, &head, 1u) == 0u) { break; } if (!rlc_sn_lt(head->last_sn, got_ack_sn)) break; - Node *node = list_pop_front((spinlock_t *)&sent_llist_lock_2[u], + Node *node = list_pop_front((spinlock_t *)RLC_SENT_LOCK(u), &ctx->sent_list); if (node == NULL) break; mm_free(node); diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/main.c b/software/rlc/multi_producer_single_consumer_double_linked_list/main.c index 773238c..ae9377d 100644 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/main.c +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/main.c @@ -73,8 +73,8 @@ int main(void) { tosend_llist_lock = 0; sent_llist_lock = 0; for (unsigned int u = 0; u < NUM_USERS; u++) { - mcs_lock_init(&tosend_llist_lock_2[u]); - mcs_lock_init(&sent_llist_lock_2[u]); + mcs_lock_init(RLC_TOSEND_LOCK(u)); + mcs_lock_init(RLC_SENT_LOCK(u)); } } diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/script/generate_pdcp_pkg.py b/software/rlc/multi_producer_single_consumer_double_linked_list/script/generate_pdcp_pkg.py index f6695a7..38b2db9 100755 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/script/generate_pdcp_pkg.py +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/script/generate_pdcp_pkg.py @@ -34,6 +34,9 @@ tgt_addr (hex or int base address) tgt_length (int bytes) total_pkg_number (optional int): explicit number of PDCP packages to generate + payload (optional bool, default true): false leaves the source slots zero. Nothing + in the kernel's timing depends on the byte values, only RLC_SELF_CHECK does, + and it keeps multi-slot headers small (tens of KB instead of ~100 MB). If `total_pkg_number` is absent, it's derived as `src_length // (pdcp_header_length + pkg_length)`. """ @@ -134,16 +137,20 @@ def main(): filename = f"data_{active_users}_{pkg_len}_{num_pkgs}.h" out_path = os.path.join(data_dir, filename) + payload = bool(cfg.get('payload', True)) + # select unique slots slots = random.sample(range(num_src_slots), k=num_pkgs) # assemble metadata and data buffer entries = [] - pdu_buf = [[0] * pdu_stride for _ in range(num_src_slots)] + pdu_buf = [[0] * pdu_stride for _ in range(num_src_slots)] if payload else None for uid, slot in zip((random.randrange(active_users) for _ in range(num_pkgs)), slots): src_addr = src_base + slot * pdu_stride tgt_addr = tgt_base + slot * pdu_stride entries.append((uid, src_addr, tgt_addr, pdu_size)) + if not payload: + continue data = slot for i in range(hdr_len, pdu_size): pdu_buf[slot][i] = data & 0xFF @@ -195,7 +202,7 @@ def main(): # src data in its own section so .pdcp_src can be located at src_base h.write('static const uint8_t __attribute__((section(".pdcp_src"), used)) ' 'pdcp_src_data[NUM_SRC_SLOTS][PDU_STRIDE] = {\n') - for slot in range(num_src_slots): + for slot in (range(num_src_slots) if payload else ()): if args.fill_zero: row = ', '.join(f'0x{b:02X}' for b in pdu_buf[slot]) if any(pdu_buf[slot]): diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_1_1350_9256_p16_c48.json b/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_1_1350_9256_p16_c48.json new file mode 100644 index 0000000..75e9339 --- /dev/null +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_1_1350_9256_p16_c48.json @@ -0,0 +1,79 @@ +{ + "active_user_number": 1, + "pkg_length": 1350, + "pdcp_header_length": 10, + "src_addr": "0xA0000000", + "src_length": 16777216, + "tgt_addr": "0xB0000000", + "tgt_length": 16777216, + "total_pkg_number": 9256, + "payload": false, + "producer_cores": [ + 0, + 16, + 32, + 48, + 64, + 80, + 96, + 112, + 128, + 144, + 160, + 176, + 192, + 208, + 224, + 240 + ], + "consumer_cores": [ + 1, + 2, + 3, + 17, + 18, + 19, + 33, + 34, + 35, + 49, + 50, + 51, + 65, + 66, + 67, + 81, + 82, + 83, + 97, + 98, + 99, + 113, + 114, + 115, + 129, + 130, + 131, + 145, + 146, + 147, + 161, + 162, + 163, + 177, + 178, + 179, + 193, + 194, + 195, + 209, + 210, + 211, + 225, + 226, + 227, + 241, + 242, + 243 + ] +} diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_1_1350_9256_p2_c2.json b/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_1_1350_9256_p2_c2.json new file mode 100644 index 0000000..4f48e48 --- /dev/null +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_1_1350_9256_p2_c2.json @@ -0,0 +1,19 @@ +{ + "active_user_number": 1, + "pkg_length": 1350, + "pdcp_header_length": 10, + "src_addr": "0xA0000000", + "src_length": 16777216, + "tgt_addr": "0xB0000000", + "tgt_length": 16777216, + "total_pkg_number": 9256, + "payload": false, + "producer_cores": [ + 0, + 1 + ], + "consumer_cores": [ + 2, + 3 + ] +} diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_1_1350_9256_p64_c192.json b/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_1_1350_9256_p64_c192.json new file mode 100644 index 0000000..610a90d --- /dev/null +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_1_1350_9256_p64_c192.json @@ -0,0 +1,271 @@ +{ + "active_user_number": 1, + "pkg_length": 1350, + "pdcp_header_length": 10, + "src_addr": "0xA0000000", + "src_length": 16777216, + "tgt_addr": "0xB0000000", + "tgt_length": 16777216, + "total_pkg_number": 9256, + "payload": false, + "producer_cores": [ + 0, + 4, + 8, + 12, + 16, + 20, + 24, + 28, + 32, + 36, + 40, + 44, + 48, + 52, + 56, + 60, + 64, + 68, + 72, + 76, + 80, + 84, + 88, + 92, + 96, + 100, + 104, + 108, + 112, + 116, + 120, + 124, + 128, + 132, + 136, + 140, + 144, + 148, + 152, + 156, + 160, + 164, + 168, + 172, + 176, + 180, + 184, + 188, + 192, + 196, + 200, + 204, + 208, + 212, + 216, + 220, + 224, + 228, + 232, + 236, + 240, + 244, + 248, + 252 + ], + "consumer_cores": [ + 1, + 2, + 3, + 5, + 6, + 7, + 9, + 10, + 11, + 13, + 14, + 15, + 17, + 18, + 19, + 21, + 22, + 23, + 25, + 26, + 27, + 29, + 30, + 31, + 33, + 34, + 35, + 37, + 38, + 39, + 41, + 42, + 43, + 45, + 46, + 47, + 49, + 50, + 51, + 53, + 54, + 55, + 57, + 58, + 59, + 61, + 62, + 63, + 65, + 66, + 67, + 69, + 70, + 71, + 73, + 74, + 75, + 77, + 78, + 79, + 81, + 82, + 83, + 85, + 86, + 87, + 89, + 90, + 91, + 93, + 94, + 95, + 97, + 98, + 99, + 101, + 102, + 103, + 105, + 106, + 107, + 109, + 110, + 111, + 113, + 114, + 115, + 117, + 118, + 119, + 121, + 122, + 123, + 125, + 126, + 127, + 129, + 130, + 131, + 133, + 134, + 135, + 137, + 138, + 139, + 141, + 142, + 143, + 145, + 146, + 147, + 149, + 150, + 151, + 153, + 154, + 155, + 157, + 158, + 159, + 161, + 162, + 163, + 165, + 166, + 167, + 169, + 170, + 171, + 173, + 174, + 175, + 177, + 178, + 179, + 181, + 182, + 183, + 185, + 186, + 187, + 189, + 190, + 191, + 193, + 194, + 195, + 197, + 198, + 199, + 201, + 202, + 203, + 205, + 206, + 207, + 209, + 210, + 211, + 213, + 214, + 215, + 217, + 218, + 219, + 221, + 222, + 223, + 225, + 226, + 227, + 229, + 230, + 231, + 233, + 234, + 235, + 237, + 238, + 239, + 241, + 242, + 243, + 245, + 246, + 247, + 249, + 250, + 251, + 253, + 254, + 255 + ] +} diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_4800_800_15704_p16_c48.json b/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_4800_800_15704_p16_c48.json new file mode 100644 index 0000000..38dec64 --- /dev/null +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_4800_800_15704_p16_c48.json @@ -0,0 +1,79 @@ +{ + "active_user_number": 4800, + "pkg_length": 800, + "pdcp_header_length": 10, + "src_addr": "0xA0000000", + "src_length": 16777216, + "tgt_addr": "0xB0000000", + "tgt_length": 16777216, + "total_pkg_number": 15704, + "payload": false, + "producer_cores": [ + 0, + 16, + 32, + 48, + 64, + 80, + 96, + 112, + 128, + 144, + 160, + 176, + 192, + 208, + 224, + 240 + ], + "consumer_cores": [ + 1, + 2, + 3, + 17, + 18, + 19, + 33, + 34, + 35, + 49, + 50, + 51, + 65, + 66, + 67, + 81, + 82, + 83, + 97, + 98, + 99, + 113, + 114, + 115, + 129, + 130, + 131, + 145, + 146, + 147, + 161, + 162, + 163, + 177, + 178, + 179, + 193, + 194, + 195, + 209, + 210, + 211, + 225, + 226, + 227, + 241, + 242, + 243 + ] +} diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_4800_800_15704_p2_c2.json b/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_4800_800_15704_p2_c2.json new file mode 100644 index 0000000..82e76fc --- /dev/null +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_4800_800_15704_p2_c2.json @@ -0,0 +1,19 @@ +{ + "active_user_number": 4800, + "pkg_length": 800, + "pdcp_header_length": 10, + "src_addr": "0xA0000000", + "src_length": 16777216, + "tgt_addr": "0xB0000000", + "tgt_length": 16777216, + "total_pkg_number": 15704, + "payload": false, + "producer_cores": [ + 0, + 1 + ], + "consumer_cores": [ + 2, + 3 + ] +} diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_4800_800_15704_p64_c192.json b/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_4800_800_15704_p64_c192.json new file mode 100644 index 0000000..9d7a622 --- /dev/null +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_4800_800_15704_p64_c192.json @@ -0,0 +1,271 @@ +{ + "active_user_number": 4800, + "pkg_length": 800, + "pdcp_header_length": 10, + "src_addr": "0xA0000000", + "src_length": 16777216, + "tgt_addr": "0xB0000000", + "tgt_length": 16777216, + "total_pkg_number": 15704, + "payload": false, + "producer_cores": [ + 0, + 4, + 8, + 12, + 16, + 20, + 24, + 28, + 32, + 36, + 40, + 44, + 48, + 52, + 56, + 60, + 64, + 68, + 72, + 76, + 80, + 84, + 88, + 92, + 96, + 100, + 104, + 108, + 112, + 116, + 120, + 124, + 128, + 132, + 136, + 140, + 144, + 148, + 152, + 156, + 160, + 164, + 168, + 172, + 176, + 180, + 184, + 188, + 192, + 196, + 200, + 204, + 208, + 212, + 216, + 220, + 224, + 228, + 232, + 236, + 240, + 244, + 248, + 252 + ], + "consumer_cores": [ + 1, + 2, + 3, + 5, + 6, + 7, + 9, + 10, + 11, + 13, + 14, + 15, + 17, + 18, + 19, + 21, + 22, + 23, + 25, + 26, + 27, + 29, + 30, + 31, + 33, + 34, + 35, + 37, + 38, + 39, + 41, + 42, + 43, + 45, + 46, + 47, + 49, + 50, + 51, + 53, + 54, + 55, + 57, + 58, + 59, + 61, + 62, + 63, + 65, + 66, + 67, + 69, + 70, + 71, + 73, + 74, + 75, + 77, + 78, + 79, + 81, + 82, + 83, + 85, + 86, + 87, + 89, + 90, + 91, + 93, + 94, + 95, + 97, + 98, + 99, + 101, + 102, + 103, + 105, + 106, + 107, + 109, + 110, + 111, + 113, + 114, + 115, + 117, + 118, + 119, + 121, + 122, + 123, + 125, + 126, + 127, + 129, + 130, + 131, + 133, + 134, + 135, + 137, + 138, + 139, + 141, + 142, + 143, + 145, + 146, + 147, + 149, + 150, + 151, + 153, + 154, + 155, + 157, + 158, + 159, + 161, + 162, + 163, + 165, + 166, + 167, + 169, + 170, + 171, + 173, + 174, + 175, + 177, + 178, + 179, + 181, + 182, + 183, + 185, + 186, + 187, + 189, + 190, + 191, + 193, + 194, + 195, + 197, + 198, + 199, + 201, + 202, + 203, + 205, + 206, + 207, + 209, + 210, + 211, + 213, + 214, + 215, + 217, + 218, + 219, + 221, + 222, + 223, + 225, + 226, + 227, + 229, + 230, + 231, + 233, + 234, + 235, + 237, + 238, + 239, + 241, + 242, + 243, + 245, + 246, + 247, + 249, + 250, + 251, + 253, + 254, + 255 + ] +} diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_48_800_19528_p16_c48.json b/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_48_800_19528_p16_c48.json new file mode 100644 index 0000000..98c13dd --- /dev/null +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_48_800_19528_p16_c48.json @@ -0,0 +1,79 @@ +{ + "active_user_number": 48, + "pkg_length": 800, + "pdcp_header_length": 10, + "src_addr": "0xA0000000", + "src_length": 16777216, + "tgt_addr": "0xB0000000", + "tgt_length": 16777216, + "total_pkg_number": 19528, + "payload": false, + "producer_cores": [ + 0, + 16, + 32, + 48, + 64, + 80, + 96, + 112, + 128, + 144, + 160, + 176, + 192, + 208, + 224, + 240 + ], + "consumer_cores": [ + 1, + 2, + 3, + 17, + 18, + 19, + 33, + 34, + 35, + 49, + 50, + 51, + 65, + 66, + 67, + 81, + 82, + 83, + 97, + 98, + 99, + 113, + 114, + 115, + 129, + 130, + 131, + 145, + 146, + 147, + 161, + 162, + 163, + 177, + 178, + 179, + 193, + 194, + 195, + 209, + 210, + 211, + 225, + 226, + 227, + 241, + 242, + 243 + ] +} diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_48_800_19528_p2_c2.json b/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_48_800_19528_p2_c2.json new file mode 100644 index 0000000..a5d2e7b --- /dev/null +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_48_800_19528_p2_c2.json @@ -0,0 +1,19 @@ +{ + "active_user_number": 48, + "pkg_length": 800, + "pdcp_header_length": 10, + "src_addr": "0xA0000000", + "src_length": 16777216, + "tgt_addr": "0xB0000000", + "tgt_length": 16777216, + "total_pkg_number": 19528, + "payload": false, + "producer_cores": [ + 0, + 1 + ], + "consumer_cores": [ + 2, + 3 + ] +} diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_48_800_19528_p64_c192.json b/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_48_800_19528_p64_c192.json new file mode 100644 index 0000000..71eeab6 --- /dev/null +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_48_800_19528_p64_c192.json @@ -0,0 +1,271 @@ +{ + "active_user_number": 48, + "pkg_length": 800, + "pdcp_header_length": 10, + "src_addr": "0xA0000000", + "src_length": 16777216, + "tgt_addr": "0xB0000000", + "tgt_length": 16777216, + "total_pkg_number": 19528, + "payload": false, + "producer_cores": [ + 0, + 4, + 8, + 12, + 16, + 20, + 24, + 28, + 32, + 36, + 40, + 44, + 48, + 52, + 56, + 60, + 64, + 68, + 72, + 76, + 80, + 84, + 88, + 92, + 96, + 100, + 104, + 108, + 112, + 116, + 120, + 124, + 128, + 132, + 136, + 140, + 144, + 148, + 152, + 156, + 160, + 164, + 168, + 172, + 176, + 180, + 184, + 188, + 192, + 196, + 200, + 204, + 208, + 212, + 216, + 220, + 224, + 228, + 232, + 236, + 240, + 244, + 248, + 252 + ], + "consumer_cores": [ + 1, + 2, + 3, + 5, + 6, + 7, + 9, + 10, + 11, + 13, + 14, + 15, + 17, + 18, + 19, + 21, + 22, + 23, + 25, + 26, + 27, + 29, + 30, + 31, + 33, + 34, + 35, + 37, + 38, + 39, + 41, + 42, + 43, + 45, + 46, + 47, + 49, + 50, + 51, + 53, + 54, + 55, + 57, + 58, + 59, + 61, + 62, + 63, + 65, + 66, + 67, + 69, + 70, + 71, + 73, + 74, + 75, + 77, + 78, + 79, + 81, + 82, + 83, + 85, + 86, + 87, + 89, + 90, + 91, + 93, + 94, + 95, + 97, + 98, + 99, + 101, + 102, + 103, + 105, + 106, + 107, + 109, + 110, + 111, + 113, + 114, + 115, + 117, + 118, + 119, + 121, + 122, + 123, + 125, + 126, + 127, + 129, + 130, + 131, + 133, + 134, + 135, + 137, + 138, + 139, + 141, + 142, + 143, + 145, + 146, + 147, + 149, + 150, + 151, + 153, + 154, + 155, + 157, + 158, + 159, + 161, + 162, + 163, + 165, + 166, + 167, + 169, + 170, + 171, + 173, + 174, + 175, + 177, + 178, + 179, + 181, + 182, + 183, + 185, + 186, + 187, + 189, + 190, + 191, + 193, + 194, + 195, + 197, + 198, + 199, + 201, + 202, + 203, + 205, + 206, + 207, + 209, + 210, + 211, + 213, + 214, + 215, + 217, + 218, + 219, + 221, + 222, + 223, + 225, + 226, + 227, + 229, + 230, + 231, + 233, + 234, + 235, + 237, + 238, + 239, + 241, + 242, + 243, + 245, + 246, + 247, + 249, + 250, + 251, + 253, + 254, + 255 + ] +} From 644b64905b62137f21aeddfd612b1414693a4ff1 Mon Sep 17 00:00:00 2001 From: Zexin Fu Date: Tue, 22 Sep 2026 22:10:22 +0200 Subject: [PATCH 34/48] rlc: per-group packet streams and node pools (RLC_GROUP_STREAMS) with work stealing --- .../kernel/llist.h | 7 + .../kernel/mm.h | 5 + .../kernel/rlc.c | 159 +++++++++++++++++- .../kernel/rlc.h | 31 ++++ .../kernel/rlc_am.c | 2 +- .../main.c | 5 + 6 files changed, 206 insertions(+), 3 deletions(-) diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/llist.h b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/llist.h index e425183..064bfb0 100644 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/llist.h +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/llist.h @@ -40,6 +40,13 @@ typedef volatile int spinlock_t __attribute__((aligned(4))); #define RLC_PAD_SYNC 0 #endif #define RLC_SYNC_LINE_BYTES 64 + +/* RLC_GROUP_STREAMS=1: per-group packet streams and node pools instead of one descriptor lock and + one pool lock for the whole cluster (see rlc.h). Default 0. */ +#ifndef RLC_GROUP_STREAMS +#define RLC_GROUP_STREAMS 0 +#endif +#define RLC_MAX_STREAMS 64 /* Declares `name` in .data; with RLC_PAD_SYNC it is the only thing on its cache line (the name then refers to `name##_line.v` through a #define placed next to the declaration). */ #if RLC_PAD_SYNC diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/mm.h b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/mm.h index f037afa..149b4dc 100644 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/mm.h +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/mm.h @@ -28,7 +28,12 @@ #ifndef MM_POOL_PAGES #define MM_POOL_PAGES 1024 /* live nodes are bounded by min(NUM_PKGS, MM_POOL_PAGES) */ #endif +#if RLC_GROUP_STREAMS +/* One partition per stream, each rounded up to a whole page count. */ +#define BUFFER_SIZE (PAGE_SIZE * (MM_POOL_PAGES + RLC_MAX_STREAMS)) +#else #define BUFFER_SIZE (PAGE_SIZE * MM_POOL_PAGES) /* memory pool size in byte */ +#endif static uint32_t bulk_buffer[BUFFER_SIZE / sizeof(uint32_t)] __attribute__((section(".dram"))) diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.c b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.c index b0a9612..2300ac8 100644 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.c +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.c @@ -377,6 +377,146 @@ static inline unsigned int rlc_status_core(void) { #endif } +#if RLC_GROUP_STREAMS +#if !RLC_CORE_LISTS +#error "RLC_GROUP_STREAMS needs the data header's producer_core_ids" +#endif +/* Lead between stream setup and the first paced arrival: covers the start barrier and dispatch. */ +#define RLC_ARRIVAL_LEAD 5000u + +static inline uint32_t rlc_group_of(uint32_t core) { + return core / (snrt_cluster_core_per_tile() * RLC_TILES_PER_GROUP); +} + +/* The STATUS core (first producer) takes no packets in stream mode when there are other producers: + it sweeps every entity between two packets, so a stream it owned would lag the others by that + much, and with paced arrival nobody steals from a stream that is late but not empty (TC3 16P: + 1/16 of the packets up to 5 ms late). */ +#define RLC_STATUS_PRODUCES (NUM_PRODUCER_CORES == 1) + +/* Stream of a core = position of its group among the distinct groups of the packet-taking + producers, in list order. Also returns the number of streams. */ +static uint32_t rlc_stream_index(uint32_t core, uint32_t *nstreams) { + uint32_t groups[RLC_MAX_STREAMS]; + uint32_t n = 0u, mine = 0u; + const uint32_t g_me = rlc_group_of(core); + for (uint32_t i = RLC_STATUS_PRODUCES ? 0u : 1u; i < NUM_PRODUCER_CORES; i++) { + const uint32_t g = rlc_group_of(producer_core_ids[i]); + uint32_t j = 0u; + while (j < n && groups[j] != g) j++; + if (j == n && n < RLC_MAX_STREAMS) groups[n++] = g; + if (g == g_me) mine = j; + } + *nstreams = n; + return mine; +} + +void rlc_streams_init(void) { + uint32_t n; + (void)rlc_stream_index(producer_core_ids[NUM_PRODUCER_CORES - 1], &n); + rlc_nstreams = n; + rlc_stream_pages = (MM_POOL_PAGES + n - 1u) / n; + for (uint32_t s = 0u; s < RLC_MAX_STREAMS; s++) { + rlc_stream[s].next = 0u; + rlc_stream[s].pool_lock = 0; + rlc_stream[s].pool_used = 0u; + rlc_stream[s].free_list = NULL; + } +#if RLC_ARRIVAL_PPS + rlc_arrival_t0 = benchmark_get_cycle() + RLC_ARRIVAL_LEAD; +#endif +} + +/* This core's stream, set once on entry to the producer loop, and the stream it currently takes + from (its own until that runs dry, then the others in turn). */ +static __thread uint32_t rlc_my_stream; +static __thread uint32_t rlc_take_stream; + +/* Next descriptor, or -1 when every stream is exhausted. + + A producer drains its own stream first and then steals from the others. Without stealing a + stream is only as fast as its own producers: the STATUS core is also a producer and sweeps + every entity between two packets, so on TC3 (4800 entities) its stream trickled out for + ~170 ms after all the others were done. */ +#if RLC_ARRIVAL_PPS +#define CPU_FREQENCY 1000000000 /* same definition as below, needed earlier here */ +#define RLC_PERIOD_Q8 (((uint64_t)CPU_FREQENCY << 8) / RLC_ARRIVAL_PPS) +static inline uint32_t rlc_due(uint32_t idx) { + return rlc_arrival_t0 + (uint32_t)(((uint64_t)idx * RLC_PERIOD_Q8) >> 8); +} +/* Streams are fed by different numbers of producers (the STATUS core's group has one fewer), so + under paced arrival one stream can fall behind while the others are merely early -- and + stealing on exhaustion never triggers. A producer whose own next packet has not arrived yet + serves the first stream that is more than RLC_STEAL_SLACK cycles behind instead of waiting. */ +#define RLC_STEAL_SLACK 2000u +static int rlc_stream_take_late(void) { + const uint32_t now = benchmark_get_cycle(); + const uint32_t own = rlc_take_stream; + const uint32_t k_own = atomic_load_explicit(&rlc_stream[own].next, memory_order_relaxed); + const uint32_t i_own = k_own * rlc_nstreams + own; + if (i_own >= NUM_PKGS || (int32_t)(rlc_due(i_own) - now) <= 0) return -1; + for (uint32_t d = 1u; d < rlc_nstreams; d++) { + const uint32_t s = (own + d) % rlc_nstreams; + const uint32_t k = atomic_load_explicit(&rlc_stream[s].next, memory_order_relaxed); + const uint32_t i = k * rlc_nstreams + s; + if (i < NUM_PKGS && (int32_t)(now - rlc_due(i)) > (int32_t)RLC_STEAL_SLACK) { + const uint32_t k2 = atomic_fetch_add_explicit(&rlc_stream[s].next, 1u, memory_order_relaxed); + const uint32_t i2 = k2 * rlc_nstreams + s; + if (i2 < NUM_PKGS) return (int)i2; + } + } + return -1; +} +#endif + +static int rlc_stream_take(void) { +#if RLC_ARRIVAL_PPS + const int late = rlc_stream_take_late(); + if (late >= 0) return late; +#endif + for (uint32_t tries = 0u; tries < rlc_nstreams; tries++) { + const uint32_t s = rlc_take_stream; + const uint32_t k = atomic_fetch_add_explicit(&rlc_stream[s].next, 1u, memory_order_relaxed); + const uint32_t idx = k * rlc_nstreams + s; + if (idx < NUM_PKGS) return (int)idx; + rlc_take_stream = (s + 1u == rlc_nstreams) ? 0u : s + 1u; + } + return -1; +} + +/* Nodes come from the slice of the stream the packet belongs to, not the producer's: a stealing + producer would otherwise run its own slice dry, and an allocation failure drops the packet. */ +static void *rlc_node_alloc(uint32_t s) { + rlc_stream_t *st = &rlc_stream[s]; + void *page = NULL; + mm_lock_acquire(&st->pool_lock); + if (st->pool_used < rlc_stream_pages) { + page = (uint8_t *)bulk_buffer + (s * rlc_stream_pages + st->pool_used) * PAGE_SIZE; + st->pool_used++; + } else if (st->free_list != NULL) { + page = (void *)st->free_list; + st->free_list = st->free_list->next; + } + mm_lock_release(&st->pool_lock); + return page; +} + +static void rlc_node_free(void *p) { + if (!p) return; + const uint32_t s = (uint32_t)(((uint8_t *)p - (uint8_t *)bulk_buffer) / PAGE_SIZE) / rlc_stream_pages; + rlc_stream_t *st = &rlc_stream[s]; + mm_lock_acquire(&st->pool_lock); + ((MM_FreePage *)p)->next = st->free_list; + st->free_list = (MM_FreePage *)p; + mm_lock_release(&st->pool_lock); +} +#define RLC_NODE_ALLOC(idx) rlc_node_alloc((uint32_t)(idx) % rlc_nstreams) +#define RLC_NODE_FREE(p) rlc_node_free(p) +#else +#define RLC_NODE_ALLOC(idx) mm_alloc() +#define RLC_NODE_FREE(p) mm_free(p) +#endif + /* AM transport-block assembly. Included here, after the core-role helpers, so rlc_ctx[], the per-user list locks and rlc_consumer_index() are in scope. */ #if RLC_TB_MODE == RLC_TB_MODE_AM @@ -444,7 +584,7 @@ void ue_status_rpt(const unsigned int core_id) core_id, ACK_SN, i); DEBUG_PRINTF_LOCK_RELEASE(&printf_lock); } - mm_free(sent_node); // Free the sent node memory + RLC_NODE_FREE(sent_node); // Free the sent node memory } ctx->acksn = ACK_SN; ctx->nackcount = 0; @@ -657,7 +797,11 @@ static int producer(const unsigned int core_id) { // pdcp_src_data[NUM_SRC_SLOTS-1][PDU_SIZE-1], // benchmark_get_cycle()); // DEBUG_PRINTF_LOCK_RELEASE(&printf_lock); +#if RLC_GROUP_STREAMS + int new_pdcp_pkg_ptr = rlc_stream_take(); +#else int new_pdcp_pkg_ptr = pdcp_receive_pkg(core_id, &pdcp_pkd_ptr_lock); +#endif if (new_pdcp_pkg_ptr < 0) { return -1; // No more packages } @@ -702,7 +846,7 @@ static int producer(const unsigned int core_id) { // DEBUG_PRINTF_LOCK_RELEASE(&printf_lock); - Node *node = (Node *)mm_alloc(); + Node *node = (Node *)RLC_NODE_ALLOC(new_pdcp_pkg_ptr); if (!node) { DEBUG_PRINTF_LOCK_ACQUIRE(&printf_lock); @@ -791,6 +935,17 @@ static void pkt_production_and_recycle(const unsigned int core_id) { uint32_t total_cycle = RLC_TOTAL_CYCLE(PRODUCER_CORE_NUM, INPUT_DATARATE); int this_core_done = 0; +#if RLC_GROUP_STREAMS + uint32_t nstreams_unused; + rlc_my_stream = rlc_stream_index(core_id, &nstreams_unused); + rlc_take_stream = rlc_my_stream; + (void)nstreams_unused; + if (!RLC_STATUS_PRODUCES && core_id == rlc_status_core()) { + /* STATUS only: counts as a finished producer from the start. */ + this_core_done = 1; + atomic_fetch_add_explicit(&producer_done, 1, memory_order_relaxed); + } +#endif #if RLC_PROBE uint32_t probe_ph = 0xffffffffu; #endif diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.h b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.h index 3cfce7b..0b9634c 100644 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.h +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.h @@ -211,6 +211,37 @@ RLC_LINE_VAR(spinlock_t, pdcp_pkd_ptr); RLC_LINE_VAR(mcs_lock_t, pdcp_pkd_ptr_lock); RLC_LINE_VAR(_Atomic(uint32_t), producer_done); +/* Per-group packet streams (RLC_GROUP_STREAMS=1). + + The default producer path takes one global descriptor lock and one global node-pool lock per + packet. On the 4x4 mesh that caps the whole cluster at ~4 M pkt/s with 16 producers and ~0.9 M + with 64 (the handoff crosses the mesh), whatever the entity count. + + With streams, every group that hosts producers owns one stream: stream s takes descriptors + s, s+n, s+2n, ... (n = number of streams) with a single atomic fetch-add -- no lock -- and + allocates nodes from its own slice of the pool under its own lock. A node goes back to the slice + it came from (found from its address), so the STATUS core can free any node. Every stream sits + on its own cache line. Needs the data header's producer list. */ +#if RLC_GROUP_STREAMS +#ifndef RLC_TILES_PER_GROUP +#define RLC_TILES_PER_GROUP 4 +#endif +typedef struct { + _Atomic uint32_t next; /* descriptors taken from this stream so far */ + spinlock_t pool_lock; + uint32_t pool_used; /* pages handed out from this stream's slice */ + MM_FreePage *free_list; +} __attribute__((aligned(RLC_SYNC_LINE_BYTES))) rlc_stream_t; +static rlc_stream_t rlc_stream[RLC_MAX_STREAMS] __attribute__((section(".data"))); +RLC_LINE_VAR(uint32_t, rlc_nstreams); /* set once by core 0 before the start barrier */ +RLC_LINE_VAR(uint32_t, rlc_stream_pages); /* pool pages per stream */ +#if RLC_PAD_SYNC +#define rlc_nstreams (rlc_nstreams_line.v) +#define rlc_stream_pages (rlc_stream_pages_line.v) +#endif +void rlc_streams_init(void); +#endif + #if RLC_ARRIVAL_PPS RLC_LINE_VAR(uint32_t, rlc_arrival_t0); #if RLC_PAD_SYNC diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.c b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.c index bb3d8ff..b6f8f41 100644 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.c +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.c @@ -837,7 +837,7 @@ void rlc_am_status(void) { Node *node = list_pop_front((spinlock_t *)RLC_SENT_LOCK(u), &ctx->sent_list); if (node == NULL) break; - mm_free(node); + RLC_NODE_FREE(node); freed++; } diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/main.c b/software/rlc/multi_producer_single_consumer_double_linked_list/main.c index ae9377d..4e4bd04 100644 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/main.c +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/main.c @@ -76,6 +76,11 @@ int main(void) { mcs_lock_init(RLC_TOSEND_LOCK(u)); mcs_lock_init(RLC_SENT_LOCK(u)); } + +#if RLC_GROUP_STREAMS + /* Last, right before the start barrier: it also starts the paced-arrival clock. */ + rlc_streams_init(); +#endif } // debug_printf_locked("[core %u] pre snrt_cluster_hw_barrier()\n", core_id); From aaabad855278d76a76c277f64a498905b20c928e Mon Sep 17 00:00:00 2001 From: Zexin Fu Date: Wed, 23 Sep 2026 00:27:08 +0200 Subject: [PATCH 35/48] rlc: tile affinity on a half-private L1, AM in-tile and cross-tile, batched AM commit --- .../kernel/llist.c | 48 ++++ .../kernel/llist.h | 32 +++ .../kernel/rlc.c | 206 ++++++++++++- .../kernel/rlc.h | 90 +++++- .../kernel/rlc_am.c | 180 +++++++++++- .../kernel/rlc_am.h | 6 + .../main.c | 25 +- .../script/generate_pdcp_pkg.py | 6 +- .../pdcp_pkg_1_1350_9256_p16_c48_l64.json | 80 ++++++ .../pdcp_pkg_1_1350_9256_p64_c192_l64.json | 272 ++++++++++++++++++ .../pdcp_pkg_4800_800_15704_p48_c144_l64.json | 208 ++++++++++++++ .../pdcp_pkg_4800_800_15704_p64_c192_l64.json | 272 ++++++++++++++++++ .../pdcp_pkg_48_800_19528_p48_c144_l64.json | 208 ++++++++++++++ 13 files changed, 1608 insertions(+), 25 deletions(-) create mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_1_1350_9256_p16_c48_l64.json create mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_1_1350_9256_p64_c192_l64.json create mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_4800_800_15704_p48_c144_l64.json create mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_4800_800_15704_p64_c192_l64.json create mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_48_800_19528_p48_c144_l64.json diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/llist.c b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/llist.c index 9101b9c..fb734f9 100644 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/llist.c +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/llist.c @@ -272,4 +272,52 @@ void list_remove(spinlock_t *llist_lock, LinkedList *list, Node *node) { } + +#if defined(RLC_TB_MODE) && (RLC_TB_MODE == 1) && RLC_AM_BATCH +unsigned int list_peek_budget_nolock(spinlock_t *llist_lock, LinkedList *list, Node **out, + unsigned int max, unsigned int budget, unsigned int overhead, + unsigned int *reached_end) { + spin_lock(llist_lock, 10); + Node *p = list->head; + unsigned int avail = (unsigned int)list->sduNum; + spin_unlock(llist_lock, 10); + unsigned int n = 0, acc = 0, stopped_on_budget = 0; + for (unsigned int k = 0; k < avail && n < max; k++) { + out[n++] = p; + acc += overhead + (unsigned int)p->data_size; + if (acc >= budget) { stopped_on_budget = 1; break; } + if (k + 1 < avail) p = p->next; /* never past the snapshot: tail->next may be moving */ + } + /* "Transmission buffer empty" as of the snapshot: the walk took the last queued SDU (the + locked version's p == NULL). A node appended after the snapshot is seen next grant. */ + (void)stopped_on_budget; + if (reached_end) *reached_end = (n == avail) ? 1u : 0u; + return n; +} + +void list_detach_front_upto(spinlock_t *llist_lock, LinkedList *list, Node *last, + unsigned int n, unsigned int bytes) { + spin_lock(llist_lock, 10); + Node *rest = last->next; + list->head = rest; + if (rest != NULL) rest->prev = NULL; else list->tail = NULL; + last->next = NULL; + list->sduNum -= (int)n; + list->sduBytes -= (int)bytes; + spin_unlock(llist_lock, 10); +} + +void list_append_chain(spinlock_t *llist_lock, LinkedList *list, Node *first, Node *last, + unsigned int n, unsigned int bytes) { + spin_lock(llist_lock, 10); + first->prev = list->tail; + if (list->tail != NULL) list->tail->next = first; else list->head = first; + list->tail = last; + last->next = NULL; + list->sduNum += (int)n; + list->sduBytes += (int)bytes; + spin_unlock(llist_lock, 10); +} +#endif + #endif diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/llist.h b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/llist.h index 064bfb0..3d67d36 100644 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/llist.h +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/llist.h @@ -47,6 +47,14 @@ typedef volatile int spinlock_t __attribute__((aligned(4))); #define RLC_GROUP_STREAMS 0 #endif #define RLC_MAX_STREAMS 64 + +/* RLC_TILE_AFFINITY=1: every UE is owned by one tile and handled entirely inside it, with its + state in that tile's PRIVATE L1 partition (see rlc.h). RLC_PRIVATE_BANKS: L1 banks per tile + given to the private partition (0 / 1 / N/2 / N-1 / N of N; the RTL's tcdm_cache_interco). + Default 0 / the historical all-private setting. */ +#ifndef RLC_TILE_AFFINITY +#define RLC_TILE_AFFINITY 0 +#endif /* Declares `name` in .data; with RLC_PAD_SYNC it is the only thing on its cache line (the name then refers to `name##_line.v` through a #define placed next to the declaration). */ #if RLC_PAD_SYNC @@ -168,6 +176,30 @@ unsigned int list_peek_n(spinlock_t *llist_lock, LinkedList *list, Node **out, unsigned int list_peek_budget(spinlock_t *llist_lock, LinkedList *list, Node **out, unsigned int max, unsigned int budget, unsigned int overhead, unsigned int *reached_end); + +#ifndef RLC_AM_BATCH +#define RLC_AM_BATCH 0 +#endif +#if RLC_AM_BATCH +/* Batched queue operations for an AM owner (RLC_AM_BATCH=1). Only the owner removes nodes from + its to-send queue; producers only append at the tail. That makes two things safe: + + list_peek_budget_nolock(): read head and length under the lock, then walk the nodes WITHOUT it. + Every node in front of the snapshot length is fixed (nobody but the caller removes), and the + walk never reads past that count, so it never races the producer writing tail->next. The + locked walk held the lock for the whole pointer chase and stalled every producer behind it. + + list_detach_front_upto(): detach the chain head..last (the caller knows `last` and the chain's + length and bytes, from its plan) in one O(1) locked step, instead of one lock per node. + list_append_chain(): append a detached chain in one O(1) locked step. */ +unsigned int list_peek_budget_nolock(spinlock_t *llist_lock, LinkedList *list, Node **out, + unsigned int max, unsigned int budget, unsigned int overhead, + unsigned int *reached_end); +void list_detach_front_upto(spinlock_t *llist_lock, LinkedList *list, Node *last, + unsigned int n, unsigned int bytes); +void list_append_chain(spinlock_t *llist_lock, LinkedList *list, Node *first, Node *last, + unsigned int n, unsigned int bytes); +#endif #endif /* diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.c b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.c index 2300ac8..edda7ef 100644 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.c +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.c @@ -35,7 +35,7 @@ /* Set when this build narrows the cluster barrier mask for a consumer-only partial-barrier region, which requires non-participants to stay out of any barrier for the duration. */ -#if (RLC_UL_MODE) || ((RLC_TB_MODE == RLC_TB_MODE_AM) && RLC_AM_TTI) +#if (RLC_UL_MODE) || ((RLC_TB_MODE == RLC_TB_MODE_AM) && RLC_AM_TTI && !RLC_TILE_AFFINITY) #define RLC_NARROWED_BARRIER 1 #else #define RLC_NARROWED_BARRIER 0 @@ -512,6 +512,128 @@ static void rlc_node_free(void *p) { } #define RLC_NODE_ALLOC(idx) rlc_node_alloc((uint32_t)(idx) % rlc_nstreams) #define RLC_NODE_FREE(p) rlc_node_free(p) +#elif RLC_TILE_AFFINITY +#if !RLC_CORE_LISTS +#error "RLC_TILE_AFFINITY needs the data header's producer/consumer lists" +#endif +#define RLC_ARRIVAL_LEAD 5000u + +/* Per core, set once by rlc_tile_setup(): this core's tile arena (NULL if its tile owns no UEs), + and its rank among the consumers of its tile. */ +static __thread rlc_tile_hdr_t *rlc_my_arena; +static __thread uint32_t rlc_my_crank, rlc_my_ncons; +static uint32_t rlc_n_workers_cached; /* per-core copy, written only by rlc_tile_setup() */ + +static inline uint32_t rlc_tile_of(uint32_t core) { return core / snrt_cluster_core_per_tile(); } + +/* Worker tiles = distinct tiles of producer_core_ids, in list order; exactly one producer each. */ +static uint32_t rlc_worker_of_tile(uint32_t tile, uint32_t *n_workers) { + uint32_t n = 0u, mine = 0xffffffffu; + for (uint32_t i = 0u; i < NUM_PRODUCER_CORES; i++) { + const uint32_t t = rlc_tile_of(producer_core_ids[i]); + uint32_t j = 0u; + while (j < i && rlc_tile_of(producer_core_ids[j]) != t) j++; + if (j < i) continue; /* tile already counted */ + if (t == tile) mine = n; + n++; + } + *n_workers = n; + return mine; +} + +static inline void rlc_zero_lines(void *p, uint32_t bytes) { + volatile uint32_t *w = (volatile uint32_t *)p; + for (uint32_t i = 0u; i < bytes / 4u; i++) w[i] = 0u; +} + +/* Every core, after the partition is set and before the start barrier. The tile's producer also + builds the tile: its UEs (cleared and initialised here, by the owner, so no other tile ever + holds a copy of their lines), their locks, the tile's descriptors and its node pool. */ +void rlc_tile_setup(const unsigned int core_id) { + const uint32_t tile = rlc_tile_of(core_id); + uint32_t nw; + const uint32_t w = rlc_worker_of_tile(tile, &nw); + rlc_n_workers_cached = nw; + rlc_my_arena = (w == 0xffffffffu) ? NULL : RLC_TILE_ARENA(w); + rlc_my_crank = 0u; rlc_my_ncons = 0u; + for (uint32_t i = 0u; i < NUM_CONSUMER_CORES; i++) { + if (rlc_tile_of(consumer_core_ids[i]) != tile) continue; + if (consumer_core_ids[i] == core_id) rlc_my_crank = rlc_my_ncons; + rlc_my_ncons++; + } + if (rlc_my_arena == NULL || !rlc_is_producer(core_id)) return; + + rlc_tile_hdr_t *th = rlc_my_arena; + rlc_zero_lines(th, sizeof(*th)); + uint32_t *ues = RLC_TILE_UES(th); + uint32_t n_ues = 0u; + for (uint32_t u = w; u < NUM_USERS; u += nw) { + if (n_ues == RLC_TILE_MAX_UES) { + printf("[TILE][FATAL] tile %u owns more than %u UEs\n", tile, (unsigned)RLC_TILE_MAX_UES); + break; + } + ues[n_ues++] = u; + rlc_zero_lines(&rlc_ctx[u], sizeof(rlc_context_t)); + rlc_init(u, 0, &mm_ctx); + mcs_lock_init(RLC_TOSEND_LOCK(u)); + mcs_lock_init(RLC_SENT_LOCK(u)); + } + th->n_ues = n_ues; +#if RLC_TB_MODE == RLC_TB_MODE_AM + /* Owner of the tile's k-th UE = tile consumer k % stride (the global rule, applied inside the + tile); each owner has one plan buffer and one transport block in the arena. */ + { + const uint32_t stride = (rlc_my_ncons < n_ues) ? rlc_my_ncons : n_ues; + for (uint32_t k = 0u; k < n_ues && stride; k++) { + const uint32_t r = k % stride; + rlc_am_ent[ues[k]].plan = (rlc_plan_t *)((uint8_t *)th + RLC_TILE_PLAN_OFF + r * sizeof(rlc_plan_t)); + rlc_am_ent[ues[k]].tb = (uint8_t *)th + RLC_TILE_TB_OFF + r * RLC_TILE_TB_BYTES; + } + rlc_tile_bar_t *bar = RLC_TILE_BAR(th); + rlc_zero_lines(bar, sizeof(*bar)); + if (rlc_my_ncons > RLC_TILE_MAX_CONS || RLC_TILE_PLAN_OFF + RLC_TILE_MAX_CONS * sizeof(rlc_plan_t) > RLC_TILE_TB_OFF || + RLC_TILE_TB_OFF + RLC_TILE_MAX_CONS * RLC_TILE_TB_BYTES > RLC_TILE_ARENA_BYTES) + printf("[TILE][FATAL] AM arena layout does not fit (grant %u B)\n", (unsigned)RLC_GRANT_BYTES); + } +#endif + /* A private copy of the scheduling indication every consumer reads per iteration, so idle + polling never leaves the tile. */ + for (uint32_t i = 0u; i < sizeof(DlschInd); i++) + RLC_TILE_DLSCH(th)->content[i] = dlsch_ind.content[i]; + rlc_tile_pkt_t *pk = RLC_TILE_PKTS(th); + uint32_t n = 0u; + for (uint32_t i = 0u; i < NUM_PKGS; i++) { + if ((uint32_t)pdcp_pkgs[i].user_id % nw != w) continue; + pk[n].gidx = i; + pk[n].pkg = pdcp_pkgs[i]; + n++; + } + th->n_pkts = n; + th->pool_off = (RLC_TILE_PKTS_OFF + n * (uint32_t)sizeof(rlc_tile_pkt_t) + 63u) & ~63u; + th->pool_pages = n; /* one node per packet: never runs dry */ + if (th->pool_off + n * PAGE_SIZE > RLC_TILE_POOL_END) + printf("[TILE][FATAL] tile %u: %u packets overflow its %u-byte arena\n", + tile, n, (unsigned)RLC_TILE_ARENA_BYTES); +} + +/* The tile's node pool. Allocation (producer) and release (STATUS) both run on the tile's + producer core, so no lock. */ +static void *rlc_tile_node_alloc(void) { + rlc_tile_hdr_t *th = rlc_my_arena; + if (th->pool_used < th->pool_pages) + return (uint8_t *)th + th->pool_off + (th->pool_used++) * PAGE_SIZE; + MM_FreePage *p = th->free_list; + if (p != NULL) th->free_list = p->next; + return p; +} +static void rlc_tile_node_free(void *p) { + if (!p) return; + rlc_tile_hdr_t *th = rlc_my_arena; + ((MM_FreePage *)p)->next = th->free_list; + th->free_list = (MM_FreePage *)p; +} +#define RLC_NODE_ALLOC(idx) rlc_tile_node_alloc() +#define RLC_NODE_FREE(p) rlc_tile_node_free(p) #else #define RLC_NODE_ALLOC(idx) mm_alloc() #define RLC_NODE_FREE(p) mm_free(p) @@ -561,7 +683,14 @@ void ue_status_rpt(const unsigned int core_id) // Simulate receiving ACK from UE after certain sent pkgs, per RLC entity. // ACK_SN is ctx->vtNextAck+2. Core 0 scans all users each call (single // writer per entity; striping across producer cores is a future option). +#if RLC_TILE_AFFINITY + /* Only this tile's UEs: STATUS runs on every worker tile's producer. */ + const rlc_tile_hdr_t *th_st = rlc_my_arena; + for (unsigned int k = 0; k < th_st->n_ues; k++) { + const unsigned int u = RLC_TILE_UES(th_st)[k]; +#else for (unsigned int u = 0; u < NUM_USERS; u++) { +#endif rlc_context_t *ctx = &rlc_ctx[u]; if (ctx->sent_list.sduNum >= 2) { char head = ue_status_rpt_content.stateRpt[0]; @@ -710,6 +839,10 @@ static void consumer(const unsigned int core_id) { rlc_ul_consumer(core_id); } #elif RLC_TB_MODE == RLC_TB_MODE_AM static void consumer(const unsigned int core_id) { /* Grant-based assembly: plan (owner) + execute (all cores) + commit. */ +#if RLC_TILE_AFFINITY + rlc_am_consumer_tile(core_id); /* the whole TTI loop runs inside the tile */ + return; +#endif #if RLC_AM_TTI && RLC_CORE_LISTS /* TTI-structured: the three phases are separated by a partial barrier over the consumer set, so a helper with nothing to do blocks rather than @@ -739,6 +872,44 @@ static void consumer(const unsigned int core_id) { } } } +#elif RLC_TILE_AFFINITY +/* Tile mode: a consumer serves only its tile's UEs (split over the tile's consumers the same way + the global version splits all UEs over all consumers) and watches only its tile's producer. */ +static void consumer(const unsigned int core_id) { + rlc_tile_hdr_t *th = rlc_my_arena; + if (th == NULL || rlc_my_ncons == 0u) return; + const uint32_t *ues = RLC_TILE_UES(th); + const unsigned int n = th->n_ues; + if (n == 0u) { while (!th->tile_done) { } return; } + const unsigned int stride = (rlc_my_ncons < n) ? rlc_my_ncons : n; + const unsigned int first = rlc_my_crank % stride; + unsigned int cursor = first; +#if RLC_PROBE + uint32_t probe_ph = 0xffffffffu; +#endif + while (1) { + TestDataStru dfx = {0}; + dfx.dlschInd = *RLC_TILE_DLSCH(th); + unsigned int k = cursor; + int sent = 0; + do { + sent = rlc_send_pkt(core_id, &rlc_ctx[ues[k]], &dfx); + if (!sent) { k += stride; if (k >= n) k = first; } + } while (!sent && k != cursor); + if (sent) { k += stride; if (k >= n) k = first; cursor = k; } +#if RLC_PROBE + if (sent) probe_ph = PERF_PROBE_PHASE_EXECUTE; + else RLC_PROBE_PHASE_TO(probe_ph, PERF_PROBE_PHASE_IDLE); +#endif + if (th->tile_done) { + int drained = 1; + for (unsigned int j = first; j < n; j += stride) { + if (rlc_ctx[ues[j]].list.sduNum != 0) { drained = 0; break; } + } + if (drained) break; + } + } +} #else static void consumer(const unsigned int core_id) { const unsigned int c = rlc_consumer_index(core_id); @@ -786,6 +957,12 @@ static void consumer(const unsigned int core_id) { /* Producer behavior (runs on cores other than 0) */ /* Returns 0 on success, -1 when no more packages available. */ +/* The descriptor of the packet being produced: the tile's local copy in tile mode. */ +#if RLC_TILE_AFFINITY +#define RLC_PKG(i) (rlc_cur->pkg) +#else +#define RLC_PKG(i) pdcp_pkgs[i] +#endif static int producer(const unsigned int core_id) { // DEBUG_PRINTF_LOCK_ACQUIRE(&printf_lock); // DEBUG_PRINTF("Producer (core %u): pdcp_src_data[0][0] = %d, pdcp_src_data[3657][500] = %d, pdcp_src_data[%d-1][%d-1] = %d, @mcycle = %d\n", @@ -799,6 +976,12 @@ static int producer(const unsigned int core_id) { // DEBUG_PRINTF_LOCK_RELEASE(&printf_lock); #if RLC_GROUP_STREAMS int new_pdcp_pkg_ptr = rlc_stream_take(); +#elif RLC_TILE_AFFINITY + /* The tile's own packets, in arrival order; this core is the tile's only producer. */ + rlc_tile_hdr_t *th_p = rlc_my_arena; + if (th_p->next >= th_p->n_pkts) return -1; + const rlc_tile_pkt_t *rlc_cur = &RLC_TILE_PKTS(th_p)[th_p->next++]; + int new_pdcp_pkg_ptr = (int)rlc_cur->gidx; #else int new_pdcp_pkg_ptr = pdcp_receive_pkg(core_id, &pdcp_pkd_ptr_lock); #endif @@ -819,17 +1002,17 @@ static int producer(const unsigned int core_id) { #endif /* Route the package to its owning RLC entity (one per UE). */ - const unsigned int uid = (unsigned int)pdcp_pkgs[new_pdcp_pkg_ptr].user_id; + const unsigned int uid = (unsigned int)RLC_PKG(new_pdcp_pkg_ptr).user_id; rlc_context_t *ctx = &rlc_ctx[uid]; ctx->latestSduPktRxCycle = benchmark_get_cycle(); #ifdef RLC_NODE_GUARD if (uid >= NUM_USERS || - (pdcp_pkgs[new_pdcp_pkg_ptr].src_addr & 0xFF000000) != 0xA0000000 || - (pdcp_pkgs[new_pdcp_pkg_ptr].tgt_addr & 0xFF000000) != 0xB0000000) { + (RLC_PKG(new_pdcp_pkg_ptr).src_addr & 0xFF000000) != 0xA0000000 || + (RLC_PKG(new_pdcp_pkg_ptr).tgt_addr & 0xFF000000) != 0xB0000000) { printf_lock_acquire(&printf_lock); printf("[GUARD][core %u] BAD DESCRIPTOR idx=%d uid=%u src=0x%x tgt=0x%x cyc=%d\n", core_id, new_pdcp_pkg_ptr, uid, - pdcp_pkgs[new_pdcp_pkg_ptr].src_addr, pdcp_pkgs[new_pdcp_pkg_ptr].tgt_addr, + RLC_PKG(new_pdcp_pkg_ptr).src_addr, RLC_PKG(new_pdcp_pkg_ptr).tgt_addr, benchmark_get_cycle()); printf_lock_release(&printf_lock); } @@ -867,9 +1050,9 @@ static int producer(const unsigned int core_id) { node->user_id = uid; /* Set the payload pointer immediately after the Node structure */ if (new_pdcp_pkg_ptr >= 0) { - node->data = (void *)((uint8_t *)(pdcp_pkgs[new_pdcp_pkg_ptr].src_addr)); - node->tgt = (void *)((uint8_t *)(pdcp_pkgs[new_pdcp_pkg_ptr].tgt_addr)); - node->data_size = pdcp_pkgs[new_pdcp_pkg_ptr].pkg_length; + node->data = (void *)((uint8_t *)(RLC_PKG(new_pdcp_pkg_ptr).src_addr)); + node->tgt = (void *)((uint8_t *)(RLC_PKG(new_pdcp_pkg_ptr).tgt_addr)); + node->data_size = RLC_PKG(new_pdcp_pkg_ptr).pkg_length; /* read one cacheline from node mem */ RcvPktHeader tmp = *(RcvPktHeader *)node->data; unsigned int pingflag = ctx->pingFlag; @@ -899,9 +1082,7 @@ static int producer(const unsigned int core_id) { // /* Zero-initialize the payload using our custom mm_memset */ // mm_memset(node->data, 0, PACKET_SIZE); /* Append the node to the owning entity's to-send list */ -#if RLC_TB_MODE != RLC_TB_MODE_AM perf_probe(PROBE_EVT_PKT_IN, (uint32_t)(uintptr_t)node); -#endif perf_probe_entity(PROBE_EVT_SDU_RX, uid, (uint32_t)node->data_size); list_push_back((spinlock_t *)RLC_TOSEND_LOCK(uid), &ctx->list, node); #if (RLC_TB_MODE == RLC_TB_MODE_AM) && RLC_AM_WORKQ @@ -957,13 +1138,16 @@ static void pkt_production_and_recycle(const unsigned int core_id) if (!this_core_done) { if (producer(core_id) < 0) { this_core_done = 1; +#if RLC_TILE_AFFINITY + rlc_my_arena->tile_done = 1u; /* the tile's consumers watch this, locally */ +#endif atomic_fetch_add_explicit(&producer_done, 1, memory_order_relaxed); } } /* UE status report runs on exactly one core -- the first producer in the list, not core 0: with explicit core lists core 0 need not be a producer at all, and gating on it would drop the ACK task entirely. */ - if (core_id == rlc_status_core()) { + if (RLC_TILE_AFFINITY || core_id == rlc_status_core()) { /* tile mode: each tile acks its own UEs */ #if RLC_PROBE if (!this_core_done) RLC_PROBE_PHASE_TO(probe_ph, PERF_PROBE_PHASE_STATUS); #endif diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.h b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.h index 0b9634c..01e740a 100644 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.h +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.h @@ -56,7 +56,85 @@ #endif /* Per-user list locks (indexed by RLC entity / user id). */ -#if RLC_PAD_SYNC +#if RLC_TILE_AFFINITY +/* Tile affinity (RLC_TILE_AFFINITY=1). + + The L1 runs half private / half shared (RLC_PRIVATE_BANKS of each tile's banks private). + Addresses at or above the partition boundary (0xA000_0000, the reset value) are cached in the + requesting tile's private banks -- always local, never on the mesh, but EACH TILE HAS ITS OWN + COPY and nothing keeps copies in step. Below the boundary there is one copy per line, at its + home tile. + + Every UE is owned by one worker tile (u % n_workers); its packets are produced, assembled and + acknowledged there, by that tile's cores only. So everything that belongs to a UE lives in the + private region, and the only rule is: no cache line is ever touched by two tiles. + - rlc_ctx[u] 0xB100_0000 + u * sizeof(rlc_context_t) (a whole number of lines) + - its two list locks 0xB300_0000 + u * 128 (one line each) + - per worker tile 0xB400_0000 + w * 1 MiB: header, owned-UE list, the tile's packet + descriptors (copied at init, read-only after), node pool + Cross-tile state -- the finish counter, the paced-arrival clock -- stays below the boundary. */ +#if RLC_GROUP_STREAMS +#error "RLC_TILE_AFFINITY and RLC_GROUP_STREAMS are alternative producer designs" +#endif +#if !RLC_PAD_SYNC +#error "RLC_TILE_AFFINITY needs RLC_PAD_SYNC" +#endif +#ifndef RLC_PRIVATE_BANKS +#define RLC_PRIVATE_BANKS 2 +#endif +#define RLC_PRIV_UE_BASE 0xB1000000u +#define RLC_PRIV_LOCK_BASE 0xB3000000u +#define RLC_PRIV_TILE_BASE 0xB4000000u +#define RLC_PRIV_AM_BASE 0xB3200000u /* rlc_am_ent[NUM_USERS] (AM builds), whole lines each */ +#define rlc_am_ent ((rlc_am_entity_t *)(uintptr_t)RLC_PRIV_AM_BASE) +#define RLC_TILE_ARENA_BYTES 0x00100000u +#define RLC_TILE_DLSCH_OFF 64u /* the tile's copy of the DL scheduling indication */ +#define RLC_TILE_UES_OFF 128u /* owned-UE ids, u32 each, up to RLC_TILE_PKTS_OFF */ +#define RLC_TILE_PKTS_OFF 0x2000u /* rlc_tile_pkt_t each */ +#define RLC_TILE_BAR_OFF (RLC_TILE_PKTS_OFF - 64u) /* tile barrier + AM grant table line */ +#define RLC_TILE_MAX_UES ((RLC_TILE_BAR_OFF - RLC_TILE_UES_OFF) / 4u) +#define RLC_TILE_PLAN_OFF 0xC0000u /* AM: one plan buffer per tile consumer (owner) */ +#define RLC_TILE_TB_OFF 0xD0000u /* AM: one transport block per tile consumer */ +#define RLC_TILE_MAX_CONS 4u +#define RLC_TILE_POOL_END RLC_TILE_PLAN_OFF +#define RLC_TILE_TB_BYTES ((((uint32_t)RLC_GRANT_BYTES) + 63u) & ~63u) +#define RLC_TOSEND_LOCK(u) ((_Atomic mcs_lock_t *)(uintptr_t)(RLC_PRIV_LOCK_BASE + (uint32_t)(u) * 128u)) +#define RLC_SENT_LOCK(u) ((_Atomic mcs_lock_t *)(uintptr_t)(RLC_PRIV_LOCK_BASE + (uint32_t)(u) * 128u + 64u)) + +typedef struct { + uint32_t gidx; /* global packet index = its arrival slot under pacing */ + pdcp_pkg_t pkg; /* the descriptor, copied into the tile at init */ + uint32_t pad[3]; +} rlc_tile_pkt_t; /* 32 B, two per line: both belong to the same tile */ + +typedef struct { + uint32_t next; /* next of this tile's packets; only the tile's producer takes */ + uint32_t n_pkts; + uint32_t n_ues; + volatile uint32_t tile_done; /* set by the tile's producer, read by its consumers */ + uint32_t pool_off; /* byte offset of the node pool in the arena */ + uint32_t pool_pages; + uint32_t pool_used; + MM_FreePage *free_list; /* alloc and free both run on the tile's producer core */ + uint32_t pad[8]; +} rlc_tile_hdr_t; /* one line */ + +#define RLC_TILE_ARENA(w) ((rlc_tile_hdr_t *)(uintptr_t)(RLC_PRIV_TILE_BASE + (uint32_t)(w) * RLC_TILE_ARENA_BYTES)) +#define RLC_TILE_UES(th) ((uint32_t *)((uint8_t *)(th) + RLC_TILE_UES_OFF)) +#define RLC_TILE_DLSCH(th) ((volatile DlschInd *)((uint8_t *)(th) + RLC_TILE_DLSCH_OFF)) + +/* Tile-local software barrier and AM grant table: the tile's consumers only, in the tile's + private banks. The hardware barrier is cluster-wide, so a per-tile TTI loop cannot use it. */ +typedef struct { + _Atomic uint32_t count; + _Atomic uint32_t sense; + volatile uint32_t stop; + volatile uint32_t open[RLC_TILE_MAX_CONS]; /* AM: entity with rank r's open grant */ + uint32_t pad[16 - 3 - RLC_TILE_MAX_CONS]; +} rlc_tile_bar_t; +#define RLC_TILE_BAR(th) ((rlc_tile_bar_t *)((uint8_t *)(th) + RLC_TILE_BAR_OFF)) +#define RLC_TILE_PKTS(th) ((rlc_tile_pkt_t *)((uint8_t *)(th) + RLC_TILE_PKTS_OFF)) +#elif RLC_PAD_SYNC typedef struct { _Atomic mcs_lock_t l; char pad[RLC_SYNC_LINE_BYTES - sizeof(mcs_lock_t)]; @@ -182,7 +260,14 @@ typedef struct { /* One RLC entity per UE. 64-byte alignment gives every entity its own cache lines (no inter-entity false sharing); at NUM_USERS == 1 the layout is identical to the single-entity kernel. */ +#if RLC_TILE_AFFINITY +/* In the private region, owner tile only (see above). */ +#define rlc_ctx ((rlc_context_t *)(uintptr_t)RLC_PRIV_UE_BASE) +_Static_assert(sizeof(rlc_context_t) % CACHE_LINE_SIZE == 0, + "rlc_context_t must be whole lines: two UEs of different tiles may not share one"); +#else rlc_context_t rlc_ctx[NUM_USERS] __attribute__((aligned(CACHE_LINE_SIZE))) __attribute__((section(".data"))); +#endif /* rlc_init() initializes the RLC context for the given RLC ID and cell ID. It sets the initial values for pollPdu, pollByte, pduWithoutPoll, byteWithoutPoll, @@ -241,6 +326,9 @@ RLC_LINE_VAR(uint32_t, rlc_stream_pages); /* pool pages per stream */ #endif void rlc_streams_init(void); #endif +#if RLC_TILE_AFFINITY +void rlc_tile_setup(const unsigned int core_id); +#endif #if RLC_ARRIVAL_PPS RLC_LINE_VAR(uint32_t, rlc_arrival_t0); diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.c b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.c index b6f8f41..b9c0f1a 100644 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.c +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.c @@ -32,8 +32,12 @@ indexing by the owner's consumer index needs no allocator. (~5.6 KiB each at RLC_MAX_PDUS_PER_GRANT = 128.) */ #ifndef RLC_AM_MAX_CONSUMERS +#if RLC_TILE_AFFINITY +#define RLC_AM_MAX_CONSUMERS 1 /* plans live in the tile arenas */ +#else #define RLC_AM_MAX_CONSUMERS RLC_ACTUAL_CONSUMERS #endif +#endif static rlc_plan_t rlc_am_plan_pool[RLC_AM_MAX_CONSUMERS] __attribute__((aligned(CACHE_LINE_SIZE))) __attribute__((section(".data"))); @@ -74,7 +78,11 @@ static uint32_t rlc_am_sweeps[RLC_AM_MAX_TRACKED_CONSUMERS] does not work: the linker is free to place it after rlc_am_ent (it did), so the addresses would not move at all. Enclosing both in one struct makes the offset a language guarantee rather than a linker accident. */ -#if RLC_LAYOUT_PAD +#if RLC_TILE_AFFINITY +/* Per-UE AM state in the owner tile's private partition: rlc_am_ent is defined in rlc.h. */ +_Static_assert(sizeof(rlc_am_entity_t) % CACHE_LINE_SIZE == 0, + "rlc_am_entity_t must be whole lines (RLC_AM_ENT_PADDED)"); +#elif RLC_LAYOUT_PAD static struct { volatile char pad[RLC_LAYOUT_PAD]; rlc_am_entity_t ent[NUM_USERS]; @@ -176,7 +184,7 @@ void rlc_am_init(uint32_t u) { that arena is private. Checked once, loudly: getting this wrong loses payload writes with no other symptom. */ rlc_am_cross_tile_unsafe = 0u; -#if !RLC_AM_ALLOW_CROSS_TILE_TB +#if !RLC_AM_ALLOW_CROSS_TILE_TB && !RLC_TILE_AFFINITY /* tile mode: executors never leave the tile */ { const uint32_t cpt = snrt_cluster_core_per_tile(); uint32_t tile0 = 0u, spans = 0u; @@ -255,7 +263,11 @@ static int rlc_am_try_plan(uint32_t u) { bound conservative -- a segmented lead SDU carries a larger header, so the walk can only ever stop later than strictly necessary, never early. */ unsigned int reached_end = 0u; +#if RLC_AM_BATCH + const uint32_t avail = list_peek_budget_nolock( +#else const uint32_t avail = list_peek_budget( +#endif (spinlock_t *)RLC_TOSEND_LOCK(u), &ctx->list, peek, RLC_MAX_PDUS_PER_GRANT, RLC_GRANT_BYTES + e->so_next, RLC_AMD_HDR_MIN, &reached_end); @@ -387,6 +399,27 @@ static void rlc_am_commit(uint32_t u) { SDU is fully acknowledged. The trailing segment's SDU stays at the head with e->so_next recording how much of it has gone out. */ uint32_t retire = 0u; +#if RLC_AM_BATCH + /* PDU i carries SDU i (plan order = queue order), and only the grant's last PDU can leave its + SDU unfinished. So the retired SDUs are exactly the first `retire` queued nodes, which the + plan already holds: stamp them, then move the whole chain in two O(1) locked steps. */ + { + uint32_t rbytes = 0u; + while (retire < n && p->last_seg[retire]) { + Node *node = (Node *)p->sdu_node[retire]; + node->last_sn = p->sn[retire]; + rbytes += (uint32_t)node->data_size; + perf_probe(PROBE_EVT_PKT_OUT, (uint32_t)(uintptr_t)node); /* SDU fully sent */ + retire++; + } + if (retire) { + Node *first = (Node *)p->sdu_node[0]; + Node *last = (Node *)p->sdu_node[retire - 1u]; + list_detach_front_upto((spinlock_t *)RLC_TOSEND_LOCK(u), &ctx->list, last, retire, rbytes); + list_append_chain((spinlock_t *)RLC_SENT_LOCK(u), &ctx->sent_list, first, last, retire, rbytes); + } + } +#else for (uint32_t i = 0u; i < n; i++) { if (!p->last_seg[i]) continue; Node *node = list_pop_front((spinlock_t *)RLC_TOSEND_LOCK(u), @@ -398,9 +431,11 @@ static void rlc_am_commit(uint32_t u) { break; } node->last_sn = p->sn[i]; + perf_probe(PROBE_EVT_PKT_OUT, (uint32_t)(uintptr_t)node); /* SDU fully sent */ list_push_back((spinlock_t *)RLC_SENT_LOCK(u), &ctx->sent_list, node); retire++; } +#endif uint32_t bytes = 0u, polls = 0u, segs = 0u; for (uint32_t i = 0u; i < n; i++) { @@ -448,6 +483,97 @@ static void rlc_am_commit(uint32_t u) { } +#if RLC_TILE_AFFINITY +/* ------------------------------------------------------------------------ */ +/* Tile-local TTI loop (RLC_TILE_AFFINITY) */ +/* ------------------------------------------------------------------------ */ +/* Same three phases as rlc_am_consumer_tti() -- owners plan, everyone executes, owners commit -- + but among the tile's own consumers, over the tile's own UEs, separated by a software barrier + on a private line. Nothing in the loop leaves the tile. */ + +/* Run totals, added once per owner at exit (grants, pdus, segments, polls, payload bytes). */ +static _Atomic uint32_t rlc_am_tot[5] __attribute__((section(".data"))); + +static __thread uint32_t rlc_am_t_sense; + +static void rlc_tile_barrier(rlc_tile_bar_t *b, uint32_t n) { + asm volatile("fence" ::: "memory"); + const uint32_t s = rlc_am_t_sense ^ 1u; + rlc_am_t_sense = s; + if (atomic_fetch_add_explicit(&b->count, 1u, memory_order_acq_rel) == n - 1u) { + atomic_store_explicit(&b->count, 0u, memory_order_relaxed); + atomic_store_explicit(&b->sense, s, memory_order_release); + } else { + while (atomic_load_explicit(&b->sense, memory_order_acquire) != s) { } + } + asm volatile("fence" ::: "memory"); +} + +void rlc_am_consumer_tile(uint32_t core_id) { + (void)core_id; + rlc_tile_hdr_t *th = rlc_my_arena; + if (th == NULL || rlc_my_ncons == 0u) return; + rlc_tile_bar_t *bar = RLC_TILE_BAR(th); + const uint32_t *ues = RLC_TILE_UES(th); + const uint32_t n = th->n_ues, nc = rlc_my_ncons, rank = rlc_my_crank; + const uint32_t stride = (nc < n) ? nc : n; + const uint32_t owned = (stride && rank < stride) ? (n - rank + stride - 1u) / stride : 0u; + uint32_t open = RLC_AM_NO_ENTITY, rr = 0u; + rlc_am_t_sense = 0u; + + while (1) { + /* plan: at most one open grant per owner */ + perf_probe_phase(PERF_PROBE_PHASE_PLAN); + for (uint32_t k = 0u; k < owned && open == RLC_AM_NO_ENTITY; k++) { + const uint32_t idx = (rr + k) % owned; + const uint32_t u = ues[rank + idx * stride]; + if (rlc_ctx[u].list.sduNum == 0 && rlc_am_ent[u].so_next == 0u) continue; + if (rlc_am_try_plan(u)) { open = u; rr = (idx + 1u) % owned; } + } + bar->open[rank] = open; + perf_probe_phase(PERF_PROBE_PHASE_BARRIER); + rlc_tile_barrier(bar, nc); + + /* execute: every consumer helps every open grant of the tile */ + perf_probe_phase(PERF_PROBE_PHASE_EXECUTE); + uint32_t worked; + do { + worked = 0u; + for (uint32_t r = 0u; r < nc; r++) { + const uint32_t u = bar->open[r]; + if (u != RLC_AM_NO_ENTITY) worked += rlc_am_help(u); + } + } while (worked); + perf_probe_phase(PERF_PROBE_PHASE_BARRIER); + rlc_tile_barrier(bar, nc); + + /* commit */ + perf_probe_phase(PERF_PROBE_PHASE_COMMIT); + if (open != RLC_AM_NO_ENTITY) { rlc_am_commit(open); open = RLC_AM_NO_ENTITY; } + perf_probe_phase(PERF_PROBE_PHASE_BARRIER); + rlc_tile_barrier(bar, nc); + + if (rank == 0u) { + uint32_t idle = th->tile_done; + for (uint32_t k = 0u; k < n && idle; k++) + if (rlc_ctx[ues[k]].list.sduNum != 0 || rlc_am_ent[ues[k]].so_next != 0u) idle = 0u; + bar->stop = idle; + } + rlc_tile_barrier(bar, nc); + if (bar->stop) break; + } + + for (uint32_t k = 0u; k < owned; k++) { + const uint32_t u = ues[rank + k * stride]; + atomic_fetch_add_explicit(&rlc_am_tot[0], rlc_am_ent[u].grants, memory_order_relaxed); + atomic_fetch_add_explicit(&rlc_am_tot[1], rlc_am_ent[u].pdus, memory_order_relaxed); + atomic_fetch_add_explicit(&rlc_am_tot[2], rlc_am_ent[u].segments, memory_order_relaxed); + atomic_fetch_add_explicit(&rlc_am_tot[3], rlc_am_ent[u].polls, memory_order_relaxed); + atomic_fetch_add_explicit(&rlc_am_tot[4], rlc_ctx[u].rlcthrp, memory_order_relaxed); + } +} +#endif /* RLC_TILE_AFFINITY */ + /* ------------------------------------------------------------------------ */ /* TTI-structured consumer loop */ /* ------------------------------------------------------------------------ */ @@ -475,14 +601,20 @@ static inline uint32_t rlc_am_owned_at(uint32_t me, uint32_t k) { so each gets a turn every ceil(owned/1) TTIs. The agreed cross-engine metric is bytes/cycle and does not depend on how a TTI is defined, so this changes the reporting granularity only. */ +/* This core's open grant and round-robin cursor. Per core (thread-local), not a table indexed by + consumer: the table had RLC_AM_MAX_TRACKED_CONSUMERS (16) slots and every consumer above that + fell back to slot 0 -- the owner's -- so with more than 16 consumers the helpers would each + commit the owner's grant in the commit phase. */ +static __thread uint32_t rlc_am_my_open; +static __thread uint32_t rlc_am_my_rr; + static void rlc_am_plan_phase(uint32_t me) { - const uint32_t trk = (me < RLC_AM_MAX_TRACKED_CONSUMERS) ? me : 0u; const uint32_t n = rlc_am_owned_count(me); if (n == 0u) return; - if (rlc_am_open_entity[trk] != RLC_AM_NO_ENTITY) return; + if (rlc_am_my_open != RLC_AM_NO_ENTITY) return; for (uint32_t k = 0u; k < n; k++) { - const uint32_t idx = (rlc_am_rr[trk] + k) % n; + const uint32_t idx = (rlc_am_my_rr + k) % n; const uint32_t u = rlc_am_owned_at(me, idx); rlc_am_entity_t *e = &rlc_am_ent[u]; if (atomic_load_explicit(&e->gen, memory_order_acquire) & 1u) continue; @@ -502,8 +634,8 @@ static void rlc_am_plan_phase(uint32_t me) { TTI, which is what dominates at TC3's 4800 mostly-idle entities. */ if (rlc_ctx[u].list.sduNum == 0 && e->so_next == 0u) continue; if (rlc_am_try_plan(u)) { - rlc_am_open_entity[trk] = u; - rlc_am_rr[trk] = (idx + 1u) % n; /* next TTI starts at the following one */ + rlc_am_my_open = u; + rlc_am_my_rr = (idx + 1u) % n; /* next TTI starts at the following one */ return; } #if RLC_AM_WORKQ @@ -513,7 +645,7 @@ static void rlc_am_plan_phase(uint32_t me) { rlc_am_bm_set(rlc_am_bm_ready, u); #endif } - rlc_am_rr[trk] = (rlc_am_rr[trk] + 1u) % n; /* nothing to plan; still advance */ + rlc_am_my_rr = (rlc_am_my_rr + 1u) % n; /* nothing to plan; still advance */ } /* Phase 2: everyone drains every open grant. Terminates when no chunk is left @@ -550,16 +682,18 @@ static uint32_t rlc_am_execute_phase(void) { between execute and commit already guarantees every chunk has completed -- the counter is kept as a cross-check rather than as the synchronisation. */ static void rlc_am_commit_phase(uint32_t me) { - const uint32_t trk = (me < RLC_AM_MAX_TRACKED_CONSUMERS) ? me : 0u; - const uint32_t u = rlc_am_open_entity[trk]; + (void)me; + const uint32_t u = rlc_am_my_open; if (u == RLC_AM_NO_ENTITY) return; if ((atomic_load_explicit(&rlc_am_ent[u].gen, memory_order_acquire) & 1u) == 0u) return; rlc_am_commit(u); - rlc_am_open_entity[trk] = RLC_AM_NO_ENTITY; + rlc_am_my_open = RLC_AM_NO_ENTITY; } void rlc_am_consumer_tti(uint32_t core_id) { const uint32_t me = rlc_consumer_index(core_id); + rlc_am_my_open = RLC_AM_NO_ENTITY; + rlc_am_my_rr = 0u; /* Tile-local participant mask. O(n), computed once on entry, never in the loop. Every consumer in a tile derives the same value independently. */ const uint32_t mask = @@ -793,7 +927,16 @@ static uint8_t rlc_am_status_buf[NUM_USERS][RLC_STATUS_HDR_LEN + 4u] __attribute__((aligned(4))) __attribute__((section(".data"))); void rlc_am_status(void) { +#if RLC_TILE_AFFINITY + /* This tile's UEs only; the STATUS PDU is built in a stack buffer (private) rather than the + shared per-entity array. */ + const rlc_tile_hdr_t *th_st = rlc_my_arena; + uint8_t st_buf[RLC_STATUS_HDR_LEN + 4u] __attribute__((aligned(4))); + for (uint32_t k = 0u; k < th_st->n_ues; k++) { + const uint32_t u = RLC_TILE_UES(th_st)[k]; +#else for (uint32_t u = 0u; u < NUM_USERS; u++) { +#endif rlc_context_t *ctx = &rlc_ctx[u]; /* The modelled UE acknowledges everything up to RLC_AM_ACK_LAG PDUs @@ -809,7 +952,11 @@ void rlc_am_status(void) { /* Build it, then decode it -- the parse is the part a receiver pays for, and it is what the legacy model skipped entirely. */ +#if RLC_TILE_AFFINITY + uint8_t *buf = st_buf; +#else uint8_t *buf = rlc_am_status_buf[u]; +#endif rlc_status_hdr_write(buf, ack_sn, /*e1=*/0u); uint32_t got_ack_sn, got_e1; rlc_status_hdr_read(buf, &got_ack_sn, &got_e1); @@ -853,12 +1000,17 @@ void rlc_am_status(void) { void rlc_am_report(void) { uint32_t grants = 0u, pdus = 0u, segs = 0u, polls = 0u; +#if RLC_TILE_AFFINITY + /* The entities live in other tiles' private partitions; each owner added its totals on exit. */ + grants = rlc_am_tot[0]; pdus = rlc_am_tot[1]; segs = rlc_am_tot[2]; polls = rlc_am_tot[3]; +#else for (uint32_t u = 0u; u < NUM_USERS; u++) { grants += rlc_am_ent[u].grants; pdus += rlc_am_ent[u].pdus; segs += rlc_am_ent[u].segments; polls += rlc_am_ent[u].polls; } +#endif printf_lock_acquire(&printf_lock); printf("[AM] entities=%u grants=%u pdus=%u segments=%u polls=%u grant_bytes=%u\n", (unsigned)NUM_USERS, grants, pdus, segs, polls, @@ -876,16 +1028,22 @@ void rlc_am_report(void) { printf("[AM] cross-tile transport block: UNSAFE -> results are not " "trustworthy\n"); } +#if !RLC_TILE_AFFINITY printf("[AM] layout: sizeof(entity)=%u pad=%u ent@%p ctx@%p\n", (unsigned)sizeof(rlc_am_entity_t), (unsigned)RLC_LAYOUT_PAD, (void *)&rlc_am_ent[0], (void *)&rlc_ctx[0]); +#endif printf("[AM] zero-vl vsetvli events: %u\n", (unsigned)atomic_load_explicit(&rlc_vec_zero_vl, memory_order_relaxed)); #if RLC_AM_TTI { uint32_t bytes = 0u; +#if RLC_TILE_AFFINITY + bytes = rlc_am_tot[4]; +#else for (uint32_t u = 0u; u < NUM_USERS; u++) bytes += atomic_load_explicit(&rlc_ctx[u].rlcthrp, memory_order_relaxed); +#endif printf("[AM] ttis=%u payload_bytes=%u tti_cycles=%u (one TTI = one grant " "opportunity per OWNER; bytes/cycle = payload_bytes / kernel_cycles)\n", rlc_am_ttis, bytes, (unsigned)RLC_TTI_CYCLES); diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.h b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.h index e66bcd1..9818b2d 100644 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.h +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.h @@ -196,6 +196,9 @@ to be untenable: 8 entities x 8 packets could not finish an hour of RTL even with this enabled, because helpers poll. Without it, cost scales with the entity count on every step. */ +#if RLC_TILE_AFFINITY && !defined(RLC_AM_WORKQ) +#define RLC_AM_WORKQ 0 /* tile mode scans its own few UEs; no cluster-wide bitmaps */ +#endif #ifndef RLC_AM_WORKQ #define RLC_AM_WORKQ 1 #endif @@ -320,6 +323,9 @@ void rlc_am_status(void); finished and every entity is drained. */ void rlc_am_consumer_tti(uint32_t core_id); +/* Tile-affinity variant: the TTI loop among one tile's consumers, over its UEs. */ +void rlc_am_consumer_tile(uint32_t core_id); + /* Print the AM summary (grants, PDUs, segments, polls) and, when the checks are compiled in, the verdict. Call on one core after the final barrier. */ void rlc_am_report(void); diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/main.c b/software/rlc/multi_producer_single_consumer_double_linked_list/main.c index 4e4bd04..0ca0f19 100644 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/main.c +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/main.c @@ -48,7 +48,15 @@ int main(void) { // path. Safe for this kernel's cross-core linked-list handoff since // private partitioning is tile-scoped, not per-core -- see l1cache.c. const unsigned int num_cores_per_tile = snrt_cluster_core_per_tile(); +#if defined(RLC_PRIVATE_BANKS) + /* Partial partition (RLC_PRIVATE_BANKS of the tile's banks private, the rest shared); the + boundary stays at its reset value 0xA000_0000: data above it is tile-private (tile mode puts + the UE state there), everything in .data/.dram below it has one copy cluster-wide. */ + (void)num_cores_per_tile; + l1d_part(RLC_PRIVATE_BANKS); +#else l1d_part(num_cores_per_tile); +#endif if (core_id == 0) { // Initalize the thread saft printf @@ -57,10 +65,14 @@ int main(void) { // Initialize memory management context mm_init(); - // Initialize all RLC entities (one per UE) + // Initialize all RLC entities (one per UE). Tile mode: each owner tile does its own + // in rlc_tile_setup() -- core 0 writing them here would leave copies of other tiles' + // private lines in tile 0. +#if !RLC_TILE_AFFINITY for (unsigned int u = 0; u < NUM_USERS; u++) { rlc_init(u, 0, &mm_ctx); } +#endif // Initialize shared/global resources (single producer-descriptor stream) pdcp_pkd_ptr = 0; @@ -72,10 +84,12 @@ int main(void) { mm_lock = 0; tosend_llist_lock = 0; sent_llist_lock = 0; +#if !RLC_TILE_AFFINITY for (unsigned int u = 0; u < NUM_USERS; u++) { mcs_lock_init(RLC_TOSEND_LOCK(u)); mcs_lock_init(RLC_SENT_LOCK(u)); } +#endif #if RLC_GROUP_STREAMS /* Last, right before the start barrier: it also starts the paced-arrival clock. */ @@ -85,6 +99,15 @@ int main(void) { // debug_printf_locked("[core %u] pre snrt_cluster_hw_barrier()\n", core_id); +#if RLC_TILE_AFFINITY + snrt_cluster_hw_barrier(); + rlc_tile_setup(core_id); // every core; each worker tile's producer builds its tile + snrt_cluster_hw_barrier(); +#if RLC_ARRIVAL_PPS + if (core_id == 0) rlc_arrival_t0 = benchmark_get_cycle() + RLC_ARRIVAL_LEAD; +#endif +#endif + // Wait for all cores to finish snrt_cluster_hw_barrier(); diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/script/generate_pdcp_pkg.py b/software/rlc/multi_producer_single_consumer_double_linked_list/script/generate_pdcp_pkg.py index 38b2db9..61093ec 100755 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/script/generate_pdcp_pkg.py +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/script/generate_pdcp_pkg.py @@ -34,6 +34,9 @@ tgt_addr (hex or int base address) tgt_length (int bytes) total_pkg_number (optional int): explicit number of PDCP packages to generate + slot_align (optional int, default 4): slot stride alignment in bytes. 64 puts every + packet on its own cache lines, which tile-private L1 partitions need: + two tiles writing different packets must never share a line. payload (optional bool, default true): false leaves the source slots zero. Nothing in the kernel's timing depends on the byte values, only RLC_SELF_CHECK does, and it keeps multi-slot headers small (tens of KB instead of ~100 MB). @@ -115,7 +118,8 @@ def main(): # Slot stride: slots must stay 4-byte aligned or the word/vector payload # copies in the kernel trap on misaligned bases (e.g. 810-byte PDUs). # The copy length stays pdu_size; padding [pdu_size, pdu_stride) is zero. - pdu_stride = (pdu_size + 3) & ~3 + align = int(cfg.get('slot_align', 4)) + pdu_stride = (pdu_size + align - 1) // align * align num_src_slots = src_len // pdu_stride num_pkgs = min(int(cfg.get('total_pkg_number', num_src_slots)), num_src_slots) diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_1_1350_9256_p16_c48_l64.json b/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_1_1350_9256_p16_c48_l64.json new file mode 100644 index 0000000..22b6282 --- /dev/null +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_1_1350_9256_p16_c48_l64.json @@ -0,0 +1,80 @@ +{ + "active_user_number": 1, + "pkg_length": 1350, + "pdcp_header_length": 10, + "src_addr": "0xA0000000", + "src_length": 16777216, + "tgt_addr": "0xB0000000", + "tgt_length": 16777216, + "total_pkg_number": 9256, + "payload": false, + "slot_align": 64, + "producer_cores": [ + 0, + 16, + 32, + 48, + 64, + 80, + 96, + 112, + 128, + 144, + 160, + 176, + 192, + 208, + 224, + 240 + ], + "consumer_cores": [ + 1, + 2, + 3, + 17, + 18, + 19, + 33, + 34, + 35, + 49, + 50, + 51, + 65, + 66, + 67, + 81, + 82, + 83, + 97, + 98, + 99, + 113, + 114, + 115, + 129, + 130, + 131, + 145, + 146, + 147, + 161, + 162, + 163, + 177, + 178, + 179, + 193, + 194, + 195, + 209, + 210, + 211, + 225, + 226, + 227, + 241, + 242, + 243 + ] +} diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_1_1350_9256_p64_c192_l64.json b/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_1_1350_9256_p64_c192_l64.json new file mode 100644 index 0000000..a59e3c0 --- /dev/null +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_1_1350_9256_p64_c192_l64.json @@ -0,0 +1,272 @@ +{ + "active_user_number": 1, + "pkg_length": 1350, + "pdcp_header_length": 10, + "src_addr": "0xA0000000", + "src_length": 16777216, + "tgt_addr": "0xB0000000", + "tgt_length": 16777216, + "total_pkg_number": 9256, + "payload": false, + "slot_align": 64, + "producer_cores": [ + 0, + 4, + 8, + 12, + 16, + 20, + 24, + 28, + 32, + 36, + 40, + 44, + 48, + 52, + 56, + 60, + 64, + 68, + 72, + 76, + 80, + 84, + 88, + 92, + 96, + 100, + 104, + 108, + 112, + 116, + 120, + 124, + 128, + 132, + 136, + 140, + 144, + 148, + 152, + 156, + 160, + 164, + 168, + 172, + 176, + 180, + 184, + 188, + 192, + 196, + 200, + 204, + 208, + 212, + 216, + 220, + 224, + 228, + 232, + 236, + 240, + 244, + 248, + 252 + ], + "consumer_cores": [ + 1, + 2, + 3, + 5, + 6, + 7, + 9, + 10, + 11, + 13, + 14, + 15, + 17, + 18, + 19, + 21, + 22, + 23, + 25, + 26, + 27, + 29, + 30, + 31, + 33, + 34, + 35, + 37, + 38, + 39, + 41, + 42, + 43, + 45, + 46, + 47, + 49, + 50, + 51, + 53, + 54, + 55, + 57, + 58, + 59, + 61, + 62, + 63, + 65, + 66, + 67, + 69, + 70, + 71, + 73, + 74, + 75, + 77, + 78, + 79, + 81, + 82, + 83, + 85, + 86, + 87, + 89, + 90, + 91, + 93, + 94, + 95, + 97, + 98, + 99, + 101, + 102, + 103, + 105, + 106, + 107, + 109, + 110, + 111, + 113, + 114, + 115, + 117, + 118, + 119, + 121, + 122, + 123, + 125, + 126, + 127, + 129, + 130, + 131, + 133, + 134, + 135, + 137, + 138, + 139, + 141, + 142, + 143, + 145, + 146, + 147, + 149, + 150, + 151, + 153, + 154, + 155, + 157, + 158, + 159, + 161, + 162, + 163, + 165, + 166, + 167, + 169, + 170, + 171, + 173, + 174, + 175, + 177, + 178, + 179, + 181, + 182, + 183, + 185, + 186, + 187, + 189, + 190, + 191, + 193, + 194, + 195, + 197, + 198, + 199, + 201, + 202, + 203, + 205, + 206, + 207, + 209, + 210, + 211, + 213, + 214, + 215, + 217, + 218, + 219, + 221, + 222, + 223, + 225, + 226, + 227, + 229, + 230, + 231, + 233, + 234, + 235, + 237, + 238, + 239, + 241, + 242, + 243, + 245, + 246, + 247, + 249, + 250, + 251, + 253, + 254, + 255 + ] +} diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_4800_800_15704_p48_c144_l64.json b/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_4800_800_15704_p48_c144_l64.json new file mode 100644 index 0000000..17bdc24 --- /dev/null +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_4800_800_15704_p48_c144_l64.json @@ -0,0 +1,208 @@ +{ + "active_user_number": 4800, + "pkg_length": 800, + "pdcp_header_length": 10, + "src_addr": "0xA0000000", + "src_length": 16777216, + "tgt_addr": "0xB0000000", + "tgt_length": 16777216, + "total_pkg_number": 15704, + "payload": false, + "slot_align": 64, + "producer_cores": [ + 0, + 4, + 8, + 16, + 20, + 24, + 32, + 36, + 40, + 48, + 52, + 56, + 64, + 68, + 72, + 80, + 84, + 88, + 96, + 100, + 104, + 112, + 116, + 120, + 128, + 132, + 136, + 144, + 148, + 152, + 160, + 164, + 168, + 176, + 180, + 184, + 192, + 196, + 200, + 208, + 212, + 216, + 224, + 228, + 232, + 240, + 244, + 248 + ], + "consumer_cores": [ + 1, + 2, + 3, + 5, + 6, + 7, + 9, + 10, + 11, + 17, + 18, + 19, + 21, + 22, + 23, + 25, + 26, + 27, + 33, + 34, + 35, + 37, + 38, + 39, + 41, + 42, + 43, + 49, + 50, + 51, + 53, + 54, + 55, + 57, + 58, + 59, + 65, + 66, + 67, + 69, + 70, + 71, + 73, + 74, + 75, + 81, + 82, + 83, + 85, + 86, + 87, + 89, + 90, + 91, + 97, + 98, + 99, + 101, + 102, + 103, + 105, + 106, + 107, + 113, + 114, + 115, + 117, + 118, + 119, + 121, + 122, + 123, + 129, + 130, + 131, + 133, + 134, + 135, + 137, + 138, + 139, + 145, + 146, + 147, + 149, + 150, + 151, + 153, + 154, + 155, + 161, + 162, + 163, + 165, + 166, + 167, + 169, + 170, + 171, + 177, + 178, + 179, + 181, + 182, + 183, + 185, + 186, + 187, + 193, + 194, + 195, + 197, + 198, + 199, + 201, + 202, + 203, + 209, + 210, + 211, + 213, + 214, + 215, + 217, + 218, + 219, + 225, + 226, + 227, + 229, + 230, + 231, + 233, + 234, + 235, + 241, + 242, + 243, + 245, + 246, + 247, + 249, + 250, + 251 + ] +} diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_4800_800_15704_p64_c192_l64.json b/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_4800_800_15704_p64_c192_l64.json new file mode 100644 index 0000000..5cc59cd --- /dev/null +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_4800_800_15704_p64_c192_l64.json @@ -0,0 +1,272 @@ +{ + "active_user_number": 4800, + "pkg_length": 800, + "pdcp_header_length": 10, + "src_addr": "0xA0000000", + "src_length": 16777216, + "tgt_addr": "0xB0000000", + "tgt_length": 16777216, + "total_pkg_number": 15704, + "payload": false, + "slot_align": 64, + "producer_cores": [ + 0, + 4, + 8, + 12, + 16, + 20, + 24, + 28, + 32, + 36, + 40, + 44, + 48, + 52, + 56, + 60, + 64, + 68, + 72, + 76, + 80, + 84, + 88, + 92, + 96, + 100, + 104, + 108, + 112, + 116, + 120, + 124, + 128, + 132, + 136, + 140, + 144, + 148, + 152, + 156, + 160, + 164, + 168, + 172, + 176, + 180, + 184, + 188, + 192, + 196, + 200, + 204, + 208, + 212, + 216, + 220, + 224, + 228, + 232, + 236, + 240, + 244, + 248, + 252 + ], + "consumer_cores": [ + 1, + 2, + 3, + 5, + 6, + 7, + 9, + 10, + 11, + 13, + 14, + 15, + 17, + 18, + 19, + 21, + 22, + 23, + 25, + 26, + 27, + 29, + 30, + 31, + 33, + 34, + 35, + 37, + 38, + 39, + 41, + 42, + 43, + 45, + 46, + 47, + 49, + 50, + 51, + 53, + 54, + 55, + 57, + 58, + 59, + 61, + 62, + 63, + 65, + 66, + 67, + 69, + 70, + 71, + 73, + 74, + 75, + 77, + 78, + 79, + 81, + 82, + 83, + 85, + 86, + 87, + 89, + 90, + 91, + 93, + 94, + 95, + 97, + 98, + 99, + 101, + 102, + 103, + 105, + 106, + 107, + 109, + 110, + 111, + 113, + 114, + 115, + 117, + 118, + 119, + 121, + 122, + 123, + 125, + 126, + 127, + 129, + 130, + 131, + 133, + 134, + 135, + 137, + 138, + 139, + 141, + 142, + 143, + 145, + 146, + 147, + 149, + 150, + 151, + 153, + 154, + 155, + 157, + 158, + 159, + 161, + 162, + 163, + 165, + 166, + 167, + 169, + 170, + 171, + 173, + 174, + 175, + 177, + 178, + 179, + 181, + 182, + 183, + 185, + 186, + 187, + 189, + 190, + 191, + 193, + 194, + 195, + 197, + 198, + 199, + 201, + 202, + 203, + 205, + 206, + 207, + 209, + 210, + 211, + 213, + 214, + 215, + 217, + 218, + 219, + 221, + 222, + 223, + 225, + 226, + 227, + 229, + 230, + 231, + 233, + 234, + 235, + 237, + 238, + 239, + 241, + 242, + 243, + 245, + 246, + 247, + 249, + 250, + 251, + 253, + 254, + 255 + ] +} diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_48_800_19528_p48_c144_l64.json b/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_48_800_19528_p48_c144_l64.json new file mode 100644 index 0000000..a3c292e --- /dev/null +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_48_800_19528_p48_c144_l64.json @@ -0,0 +1,208 @@ +{ + "active_user_number": 48, + "pkg_length": 800, + "pdcp_header_length": 10, + "src_addr": "0xA0000000", + "src_length": 16777216, + "tgt_addr": "0xB0000000", + "tgt_length": 16777216, + "total_pkg_number": 19528, + "payload": false, + "slot_align": 64, + "producer_cores": [ + 0, + 4, + 8, + 16, + 20, + 24, + 32, + 36, + 40, + 48, + 52, + 56, + 64, + 68, + 72, + 80, + 84, + 88, + 96, + 100, + 104, + 112, + 116, + 120, + 128, + 132, + 136, + 144, + 148, + 152, + 160, + 164, + 168, + 176, + 180, + 184, + 192, + 196, + 200, + 208, + 212, + 216, + 224, + 228, + 232, + 240, + 244, + 248 + ], + "consumer_cores": [ + 1, + 2, + 3, + 5, + 6, + 7, + 9, + 10, + 11, + 17, + 18, + 19, + 21, + 22, + 23, + 25, + 26, + 27, + 33, + 34, + 35, + 37, + 38, + 39, + 41, + 42, + 43, + 49, + 50, + 51, + 53, + 54, + 55, + 57, + 58, + 59, + 65, + 66, + 67, + 69, + 70, + 71, + 73, + 74, + 75, + 81, + 82, + 83, + 85, + 86, + 87, + 89, + 90, + 91, + 97, + 98, + 99, + 101, + 102, + 103, + 105, + 106, + 107, + 113, + 114, + 115, + 117, + 118, + 119, + 121, + 122, + 123, + 129, + 130, + 131, + 133, + 134, + 135, + 137, + 138, + 139, + 145, + 146, + 147, + 149, + 150, + 151, + 153, + 154, + 155, + 161, + 162, + 163, + 165, + 166, + 167, + 169, + 170, + 171, + 177, + 178, + 179, + 181, + 182, + 183, + 185, + 186, + 187, + 193, + 194, + 195, + 197, + 198, + 199, + 201, + 202, + 203, + 209, + 210, + 211, + 213, + 214, + 215, + 217, + 218, + 219, + 225, + 226, + 227, + 229, + 230, + 231, + 233, + 234, + 235, + 241, + 242, + 243, + 245, + 246, + 247, + 249, + 250, + 251 + ] +} From d5c639ac80dc7965067537103da1bfc10a3a23ce Mon Sep 17 00:00:00 2001 From: Zexin Fu Date: Wed, 23 Sep 2026 00:45:19 +0200 Subject: [PATCH 36/48] rlc: AM tile STATUS on a dirty bitmap, multiple grants per owner per TTI --- .../kernel/rlc.c | 14 ++--- .../kernel/rlc.h | 19 +++++-- .../kernel/rlc_am.c | 57 ++++++++++++++----- 3 files changed, 63 insertions(+), 27 deletions(-) diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.c b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.c index edda7ef..ba354dc 100644 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.c +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.c @@ -583,16 +583,14 @@ void rlc_tile_setup(const unsigned int core_id) { /* Owner of the tile's k-th UE = tile consumer k % stride (the global rule, applied inside the tile); each owner has one plan buffer and one transport block in the arena. */ { - const uint32_t stride = (rlc_my_ncons < n_ues) ? rlc_my_ncons : n_ues; - for (uint32_t k = 0u; k < n_ues && stride; k++) { - const uint32_t r = k % stride; - rlc_am_ent[ues[k]].plan = (rlc_plan_t *)((uint8_t *)th + RLC_TILE_PLAN_OFF + r * sizeof(rlc_plan_t)); - rlc_am_ent[ues[k]].tb = (uint8_t *)th + RLC_TILE_TB_OFF + r * RLC_TILE_TB_BYTES; - } + /* Plan buffers and transport blocks are per (owner rank, grant slot) and are bound to an + entity when its grant is opened (rlc_am_consumer_tile). */ rlc_tile_bar_t *bar = RLC_TILE_BAR(th); rlc_zero_lines(bar, sizeof(*bar)); - if (rlc_my_ncons > RLC_TILE_MAX_CONS || RLC_TILE_PLAN_OFF + RLC_TILE_MAX_CONS * sizeof(rlc_plan_t) > RLC_TILE_TB_OFF || - RLC_TILE_TB_OFF + RLC_TILE_MAX_CONS * RLC_TILE_TB_BYTES > RLC_TILE_ARENA_BYTES) + rlc_zero_lines(RLC_TILE_DIRTY(th), (RLC_TILE_MAX_UES + 31u) / 32u * 4u); + const uint32_t nslots = RLC_TILE_MAX_CONS * RLC_AM_TILE_GRANTS; + if (rlc_my_ncons > RLC_TILE_MAX_CONS || RLC_TILE_PLAN_OFF + nslots * sizeof(rlc_plan_t) > RLC_TILE_TB_OFF || + RLC_TILE_TB_OFF + nslots * RLC_TILE_TB_BYTES > RLC_TILE_ARENA_BYTES) printf("[TILE][FATAL] AM arena layout does not fit (grant %u B)\n", (unsigned)RLC_GRANT_BYTES); } #endif diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.h b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.h index 01e740a..2b5601c 100644 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.h +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.h @@ -91,8 +91,12 @@ #define RLC_TILE_DLSCH_OFF 64u /* the tile's copy of the DL scheduling indication */ #define RLC_TILE_UES_OFF 128u /* owned-UE ids, u32 each, up to RLC_TILE_PKTS_OFF */ #define RLC_TILE_PKTS_OFF 0x2000u /* rlc_tile_pkt_t each */ -#define RLC_TILE_BAR_OFF (RLC_TILE_PKTS_OFF - 64u) /* tile barrier + AM grant table line */ -#define RLC_TILE_MAX_UES ((RLC_TILE_BAR_OFF - RLC_TILE_UES_OFF) / 4u) +#ifndef RLC_AM_TILE_GRANTS +#define RLC_AM_TILE_GRANTS 1u /* AM: grants an owner may open per TTI (plan slots) */ +#endif +#define RLC_TILE_BAR_OFF 0x1E00u /* tile barrier + AM grant table (up to 512 B) */ +#define RLC_TILE_DIRTY_OFF 0x1C00u /* AM: bit per local UE with unacknowledged PDUs */ +#define RLC_TILE_MAX_UES ((RLC_TILE_DIRTY_OFF - RLC_TILE_UES_OFF) / 4u) #define RLC_TILE_PLAN_OFF 0xC0000u /* AM: one plan buffer per tile consumer (owner) */ #define RLC_TILE_TB_OFF 0xD0000u /* AM: one transport block per tile consumer */ #define RLC_TILE_MAX_CONS 4u @@ -129,10 +133,17 @@ typedef struct { _Atomic uint32_t count; _Atomic uint32_t sense; volatile uint32_t stop; - volatile uint32_t open[RLC_TILE_MAX_CONS]; /* AM: entity with rank r's open grant */ - uint32_t pad[16 - 3 - RLC_TILE_MAX_CONS]; + uint32_t pad[13]; + /* AM: entity of owner rank r's j-th open grant at [r * RLC_AM_TILE_GRANTS + j] */ + volatile uint32_t open[RLC_TILE_MAX_CONS * RLC_AM_TILE_GRANTS]; } rlc_tile_bar_t; +_Static_assert(sizeof(rlc_tile_bar_t) <= RLC_TILE_PKTS_OFF - RLC_TILE_BAR_OFF, "tile barrier area"); #define RLC_TILE_BAR(th) ((rlc_tile_bar_t *)((uint8_t *)(th) + RLC_TILE_BAR_OFF)) +#define RLC_TILE_DIRTY(th) ((_Atomic uint32_t *)((uint8_t *)(th) + RLC_TILE_DIRTY_OFF)) +/* Owner rank r's grant slot j: plan buffer and transport block. */ +#define RLC_TILE_SLOT(r, j) ((r) * RLC_AM_TILE_GRANTS + (j)) +#define RLC_TILE_SLOT_PLAN(th, s) ((rlc_plan_t *)((uint8_t *)(th) + RLC_TILE_PLAN_OFF + (s) * sizeof(rlc_plan_t))) +#define RLC_TILE_SLOT_TB(th, s) ((uint8_t *)(th) + RLC_TILE_TB_OFF + (s) * RLC_TILE_TB_BYTES) #define RLC_TILE_PKTS(th) ((rlc_tile_pkt_t *)((uint8_t *)(th) + RLC_TILE_PKTS_OFF)) #elif RLC_PAD_SYNC typedef struct { diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.c b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.c index b9c0f1a..51313a2 100644 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.c +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.c @@ -518,19 +518,26 @@ void rlc_am_consumer_tile(uint32_t core_id) { const uint32_t n = th->n_ues, nc = rlc_my_ncons, rank = rlc_my_crank; const uint32_t stride = (nc < n) ? nc : n; const uint32_t owned = (stride && rank < stride) ? (n - rank + stride - 1u) / stride : 0u; - uint32_t open = RLC_AM_NO_ENTITY, rr = 0u; + const uint32_t G = RLC_AM_TILE_GRANTS; + uint32_t open[RLC_AM_TILE_GRANTS]; + uint32_t rr = 0u; rlc_am_t_sense = 0u; while (1) { - /* plan: at most one open grant per owner */ + /* plan: up to G grants per owner, each for a different entity, each in its own plan slot */ perf_probe_phase(PERF_PROBE_PHASE_PLAN); - for (uint32_t k = 0u; k < owned && open == RLC_AM_NO_ENTITY; k++) { + uint32_t g = 0u, k = 0u; + for (; k < owned && g < G; k++) { const uint32_t idx = (rr + k) % owned; const uint32_t u = ues[rank + idx * stride]; if (rlc_ctx[u].list.sduNum == 0 && rlc_am_ent[u].so_next == 0u) continue; - if (rlc_am_try_plan(u)) { open = u; rr = (idx + 1u) % owned; } + const uint32_t slot = RLC_TILE_SLOT(rank, g); + rlc_am_ent[u].plan = RLC_TILE_SLOT_PLAN(th, slot); + rlc_am_ent[u].tb = RLC_TILE_SLOT_TB(th, slot); + if (rlc_am_try_plan(u)) open[g++] = u; } - bar->open[rank] = open; + if (owned) rr = (rr + k) % owned; /* next TTI continues after the last entity looked at */ + for (uint32_t j = 0u; j < G; j++) bar->open[RLC_TILE_SLOT(rank, j)] = (j < g) ? open[j] : RLC_AM_NO_ENTITY; perf_probe_phase(PERF_PROBE_PHASE_BARRIER); rlc_tile_barrier(bar, nc); @@ -539,32 +546,36 @@ void rlc_am_consumer_tile(uint32_t core_id) { uint32_t worked; do { worked = 0u; - for (uint32_t r = 0u; r < nc; r++) { - const uint32_t u = bar->open[r]; + for (uint32_t s = 0u; s < nc * G; s++) { + const uint32_t u = bar->open[s]; if (u != RLC_AM_NO_ENTITY) worked += rlc_am_help(u); } } while (worked); perf_probe_phase(PERF_PROBE_PHASE_BARRIER); rlc_tile_barrier(bar, nc); - /* commit */ + /* commit, and mark the entities STATUS has to look at */ perf_probe_phase(PERF_PROBE_PHASE_COMMIT); - if (open != RLC_AM_NO_ENTITY) { rlc_am_commit(open); open = RLC_AM_NO_ENTITY; } + for (uint32_t j = 0u; j < g; j++) { + rlc_am_commit(open[j]); + const uint32_t li = open[j] / rlc_n_workers_cached; /* local index of the entity */ + atomic_fetch_or_explicit(&RLC_TILE_DIRTY(th)[li >> 5], 1u << (li & 31u), memory_order_relaxed); + } perf_probe_phase(PERF_PROBE_PHASE_BARRIER); rlc_tile_barrier(bar, nc); if (rank == 0u) { uint32_t idle = th->tile_done; - for (uint32_t k = 0u; k < n && idle; k++) - if (rlc_ctx[ues[k]].list.sduNum != 0 || rlc_am_ent[ues[k]].so_next != 0u) idle = 0u; + for (uint32_t q = 0u; q < n && idle; q++) + if (rlc_ctx[ues[q]].list.sduNum != 0 || rlc_am_ent[ues[q]].so_next != 0u) idle = 0u; bar->stop = idle; } rlc_tile_barrier(bar, nc); if (bar->stop) break; } - for (uint32_t k = 0u; k < owned; k++) { - const uint32_t u = ues[rank + k * stride]; + for (uint32_t q = 0u; q < owned; q++) { + const uint32_t u = ues[rank + q * stride]; atomic_fetch_add_explicit(&rlc_am_tot[0], rlc_am_ent[u].grants, memory_order_relaxed); atomic_fetch_add_explicit(&rlc_am_tot[1], rlc_am_ent[u].pdus, memory_order_relaxed); atomic_fetch_add_explicit(&rlc_am_tot[2], rlc_am_ent[u].segments, memory_order_relaxed); @@ -930,9 +941,20 @@ void rlc_am_status(void) { #if RLC_TILE_AFFINITY /* This tile's UEs only; the STATUS PDU is built in a stack buffer (private) rather than the shared per-entity array. */ + /* Only entities that transmitted since the last pass (commit sets their bit): a full sweep of + the tile's ~100 TC3 entities after every packet was 67% of the producer's time. An entity + still waiting for acknowledgements is re-marked below. */ const rlc_tile_hdr_t *th_st = rlc_my_arena; uint8_t st_buf[RLC_STATUS_HDR_LEN + 4u] __attribute__((aligned(4))); - for (uint32_t k = 0u; k < th_st->n_ues; k++) { + _Atomic uint32_t *dirty = RLC_TILE_DIRTY(th_st); + const uint32_t nwords = (th_st->n_ues + 31u) / 32u; + for (uint32_t wd = 0u; wd < nwords; wd++) { + uint32_t bits = atomic_load_explicit(&dirty[wd], memory_order_relaxed); + if (bits == 0u) continue; + bits = atomic_exchange_explicit(&dirty[wd], 0u, memory_order_relaxed); + while (bits) { + const uint32_t k = (wd << 5) + (uint32_t)__builtin_ctz(bits); + bits &= bits - 1u; const uint32_t u = RLC_TILE_UES(th_st)[k]; #else for (uint32_t u = 0u; u < NUM_USERS; u++) { @@ -996,6 +1018,9 @@ void rlc_am_status(void) { if (freed) perf_probe_entity(PROBE_EVT_STATUS_ACK, u, freed); #endif } +#if RLC_TILE_AFFINITY + } /* while (bits) and for (wd): see the tile-mode loop head */ +#endif } void rlc_am_report(void) { @@ -1053,7 +1078,9 @@ void rlc_am_report(void) { (unsigned)PRODUCER_CORE_NUM, (unsigned)NUM_PRODUCER_CORES, (unsigned)CONSUMER_CORE_NUM, (unsigned)NUM_CONSUMER_CORES, (unsigned)RLC_AM_WORKQ); - for (uint32_t u = 0u; u < NUM_USERS; u++) { + /* Per-entity dump: not in tile mode, where the entities sit in other tiles' private partitions + (and 4800 of them took ~90 M cycles of printf after the kernel). */ + for (uint32_t u = 0u; u < (RLC_TILE_AFFINITY ? 0u : NUM_USERS); u++) { const rlc_am_entity_t *e = &rlc_am_ent[u]; printf("[AM] u%u: plan_calls=%u peek_empty=%u peek_max=%u plan_zero=%u " "peek_done=%u plan_ok=%u poison=%u published=%u grants=%u | tosend=%d sent=%d " From 142358ef6ed39799c396ac8fd169111de0aee81d Mon Sep 17 00:00:00 2001 From: Zexin Fu Date: Wed, 23 Sep 2026 01:09:43 +0200 Subject: [PATCH 37/48] rlc: TC1 at target -- descriptor-ring to-send queue, owner plans in its private partition --- .../kernel/rlc.c | 31 +++++ .../kernel/rlc_am.c | 111 +++++++++++++++++- .../kernel/rlc_am.h | 45 +++++++ 3 files changed, 182 insertions(+), 5 deletions(-) diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.c b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.c index ba354dc..0ad1526 100644 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.c +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.c @@ -955,6 +955,11 @@ static void consumer(const unsigned int core_id) { /* Producer behavior (runs on cores other than 0) */ /* Returns 0 on success, -1 when no more packages available. */ +#if RLC_AM_RING +/* Per-core shard of the entity receive statistics (ring mode). */ +static __thread uint32_t rlc_rx_shard_pkts, rlc_rx_shard_bytes; +#endif + /* The descriptor of the packet being produced: the tile's local copy in tile mode. */ #if RLC_TILE_AFFINITY #define RLC_PKG(i) (rlc_cur->pkg) @@ -1001,6 +1006,32 @@ static int producer(const unsigned int core_id) { /* Route the package to its owning RLC entity (one per UE). */ const unsigned int uid = (unsigned int)RLC_PKG(new_pdcp_pkg_ptr).user_id; +#if RLC_AM_RING + { + /* Ring mode: claim a slot with one atomic add, fill it, publish it. No node, no pool, no + list lock. The per-packet entity statistics go to a per-core shard instead of ~10 + atomics on the entity's lines that every producer contends for. */ + rlc_ring_t *rg = &rlc_ring[uid]; + const uint32_t idx = atomic_fetch_add_explicit(&rg->tail, 1u, memory_order_relaxed); + while ((uint32_t)(idx - atomic_load_explicit(&rg->ack, memory_order_acquire)) >= RLC_AM_RING_SIZE) { } + rlc_ring_slot_t *sl = &rg->slot[idx & RLC_RING_MASK]; + const uint32_t src = RLC_PKG(new_pdcp_pkg_ptr).src_addr; + const uint32_t len = RLC_PKG(new_pdcp_pkg_ptr).pkg_length; + sl->data = src; + sl->len = len; + /* The PDCP header work every producer does: read the header line, write 64 B back. */ + RcvPktHeader tmp = *(RcvPktHeader *)(uintptr_t)src; + RcvPktHeader *pt = (RcvPktHeader *)((char *)(uintptr_t)src + sizeof(RcvPktHeader)); + vector_memcpy32_m4_opt((pt + 1), &tmp, sizeof(RcvPktHeader)); + rlc_rx_shard_pkts++; + rlc_rx_shard_bytes += len; + perf_probe_entity(PROBE_EVT_SDU_RX, uid, len); + perf_probe(PROBE_EVT_PKT_IN, RLC_RING_TAG(uid, idx)); + asm volatile("fence w, w" ::: "memory"); /* slot contents before seq */ + sl->seq = idx + 1u; + return 0; + } +#endif rlc_context_t *ctx = &rlc_ctx[uid]; ctx->latestSduPktRxCycle = benchmark_get_cycle(); #ifdef RLC_NODE_GUARD diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.c b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.c index 51313a2..c4488ee 100644 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.c +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.c @@ -78,6 +78,23 @@ static uint32_t rlc_am_sweeps[RLC_AM_MAX_TRACKED_CONSUMERS] does not work: the linker is free to place it after rlc_am_ent (it did), so the addresses would not move at all. Enclosing both in one struct makes the offset a language guarantee rather than a linker accident. */ +#if RLC_AM_RING +#if RLC_TILE_AFFINITY || RLC_AM_WORKQ +#error "RLC_AM_RING: cross-tile AM without the work-queue bitmaps (RLC_AM_WORKQ=0), not tile mode" +#endif +/* Below the partition boundary (.dram): producers and owner are on different tiles. */ +static rlc_ring_t rlc_ring[NUM_USERS] __attribute__((section(".dram"))) __attribute__((aligned(64))); +#define RLC_RING_MASK (RLC_AM_RING_SIZE - 1u) +#define RLC_RING_TAG(u, i) (((uint32_t)(u) << 24) | ((uint32_t)(i) & 0xffffffu)) +static inline int rlc_ring_queued(uint32_t u) { + const uint32_t h = atomic_load_explicit(&rlc_ring[u].head, memory_order_relaxed); + return rlc_ring[u].slot[h & RLC_RING_MASK].seq == h + 1u; +} +#define RLC_AM_QUEUED(u) rlc_ring_queued(u) +#else +#define RLC_AM_QUEUED(u) (rlc_ctx[u].list.sduNum != 0) +#endif + #if RLC_TILE_AFFINITY /* Per-UE AM state in the owner tile's private partition: rlc_am_ent is defined in rlc.h. */ _Static_assert(sizeof(rlc_am_entity_t) % CACHE_LINE_SIZE == 0, @@ -210,6 +227,14 @@ void rlc_am_init(uint32_t u) { rlc_am_entity_t *e = &rlc_am_ent[u]; e->so_next = 0u; e->plan = &rlc_am_plan_pool[rlc_am_owner_idx(u)]; +#if RLC_AM_PRIV_PLAN +#if RLC_TILE_AFFINITY +#error "RLC_AM_PRIV_PLAN is for cross-tile AM; tile mode already keeps plans private" +#endif + /* One private buffer per owner, at distinct addresses (no line shared between owners). */ + e->plan_priv = (rlc_plan_t *)(uintptr_t)(RLC_AM_PRIV_PLAN_BASE + + rlc_am_owner_idx(u) * (uint32_t)sizeof(rlc_plan_t)); +#endif e->tb = (uint8_t *)(uintptr_t)(RLC_TB_BASE + u * RLC_TB_STRIDE); e->n = 0u; e->tb_used = 0u; @@ -247,11 +272,41 @@ void rlc_am_init(uint32_t u) { static int rlc_am_try_plan(uint32_t u) { rlc_am_entity_t *e = &rlc_am_ent[u]; rlc_context_t *ctx = &rlc_ctx[u]; +#if RLC_AM_PRIV_PLAN + rlc_plan_t *plan = e->plan_priv; +#else rlc_plan_t *plan = e->plan; +#endif /* Look ahead over the queue without detaching anything: a partially sent SDU must stay at the head until its final segment goes out. */ e->plan_calls++; +#if RLC_AM_RING + /* Gather published slots from head: independent loads, no lock, no pointer chase. */ + unsigned int reached_end = 0u; + uint32_t avail = 0u, acc = 0u; + { + rlc_ring_t *rg = &rlc_ring[u]; + const uint32_t h = atomic_load_explicit(&rg->head, memory_order_relaxed); + const uint32_t budget = RLC_GRANT_BYTES + e->so_next; + while (avail < RLC_MAX_PDUS_PER_GRANT) { + const rlc_ring_slot_t *sl = &rg->slot[(h + avail) & RLC_RING_MASK]; + if (sl->seq != h + avail + 1u) { reached_end = 1u; break; } + plan->sdu_data[avail] = (void *)(uintptr_t)sl->data; + plan->sdu_len[avail] = sl->len; + avail++; + acc += RLC_AMD_HDR_MIN + sl->len; + if (acc >= budget) { + reached_end = (rg->slot[(h + avail) & RLC_RING_MASK].seq != h + avail + 1u); + break; + } + } + asm volatile("fence r, rw" ::: "memory"); /* slot contents after their seq */ + } + e->peek_done++; + if (avail > e->peek_max) e->peek_max = avail; + if (avail == 0u) { e->peek_empty++; return 0; } +#else /* Peek straight into the plan's own node array. A local Node*[128] would put 512 B on the stack, and Snitch stacks are small -- this keeps the frame flat and saves a copy. */ @@ -279,6 +334,7 @@ static int rlc_am_try_plan(uint32_t u) { plan->sdu_data[i] = peek[i]->data; plan->sdu_len[i] = (uint32_t)peek[i]->data_size; } +#endif plan->n_avail = avail; const rlc_plan_in_t in = { @@ -310,6 +366,25 @@ static int rlc_am_try_plan(uint32_t u) { #endif if (n == 0u) { e->plan_zero++; return 0; } e->plan_ok++; +#if RLC_AM_PRIV_PLAN + /* Publish what the executors read (rlc_am_execute_range) to the shared plan: streaming stores, + no reads of remote lines. */ + { + /* Vector copies: a scalar store to a remote line waits for its response, so 8 x n scalar + stores cost more than the private planning saved; the vector unit streams them. */ + rlc_plan_t *sp = e->plan; + const size_t nb = (size_t)n * 4u; + vector_memcpy32_m8_m4_general_opt(sp->sdu_data, plan->sdu_data, nb); + vector_memcpy32_m8_m4_general_opt(sp->sn, plan->sn, nb); + vector_memcpy32_m8_m4_general_opt(sp->tb_off, plan->tb_off, nb); + vector_memcpy32_m8_m4_general_opt(sp->seg_len, plan->seg_len, nb); + vector_memcpy32_m8_m4_general_opt(sp->so, plan->so, nb); + vector_memcpy32_m8_m4_general_opt(sp->si, plan->si, nb); + vector_memcpy32_m8_m4_general_opt(sp->poll, plan->poll, nb); + vector_memcpy32_m8_m4_general_opt(sp->hdr_len, plan->hdr_len, nb); + asm volatile("fence" ::: "memory"); /* published (vector stores drained) before the generation bump */ + } +#endif /* Stash what commit needs; it must not re-run the planner. */ e->n = n; @@ -390,7 +465,11 @@ static uint32_t rlc_am_help(uint32_t u) { static void rlc_am_commit(uint32_t u) { rlc_am_entity_t *e = &rlc_am_ent[u]; rlc_context_t *ctx = &rlc_ctx[u]; +#if RLC_AM_PRIV_PLAN + const rlc_plan_t *p = e->plan_priv; /* the owner's local copy */ +#else const rlc_plan_t *p = e->plan; +#endif const uint32_t n = e->n; const uint32_t partial = e->partial; @@ -399,7 +478,19 @@ static void rlc_am_commit(uint32_t u) { SDU is fully acknowledged. The trailing segment's SDU stays at the head with e->so_next recording how much of it has gone out. */ uint32_t retire = 0u; -#if RLC_AM_BATCH +#if RLC_AM_RING + { + rlc_ring_t *rg = &rlc_ring[u]; + const uint32_t h = atomic_load_explicit(&rg->head, memory_order_relaxed); + while (retire < n && p->last_seg[retire]) { + rg->slot[(h + retire) & RLC_RING_MASK].last_sn = p->sn[retire]; + perf_probe(PROBE_EVT_PKT_OUT, RLC_RING_TAG(u, h + retire)); /* SDU fully sent */ + retire++; + } + asm volatile("fence w, w" ::: "memory"); /* last_sn before STATUS can see the new head */ + atomic_store_explicit(&rg->head, h + retire, memory_order_release); + } +#elif RLC_AM_BATCH /* PDU i carries SDU i (plan order = queue order), and only the grant's last PDU can leave its SDU unfinished. So the retired SDUs are exactly the first `retire` queued nodes, which the plan already holds: stamp them, then move the whole chain in two O(1) locked steps. */ @@ -476,7 +567,7 @@ static void rlc_am_commit(uint32_t u) { rlc_am_bm_clr(rlc_am_bm_active, u); /* Anything left -- queued SDUs, or a segment mid-flight -- re-arms the entity so it is picked up again without a scan. */ - if (ctx->list.sduNum != 0 || e->so_next != 0u) { + if (RLC_AM_QUEUED(u) || e->so_next != 0u) { rlc_am_bm_set(rlc_am_bm_ready, u); } #endif @@ -643,7 +734,7 @@ static void rlc_am_plan_phase(uint32_t me) { re-arms the entity, and round-robin visits it again next TTI anyway. What it avoids is a lock acquire and a pointer chase per idle entity per TTI, which is what dominates at TC3's 4800 mostly-idle entities. */ - if (rlc_ctx[u].list.sduNum == 0 && e->so_next == 0u) continue; + if (!RLC_AM_QUEUED(u) && e->so_next == 0u) continue; if (rlc_am_try_plan(u)) { rlc_am_my_open = u; rlc_am_my_rr = (idx + 1u) % n; /* next TTI starts at the following one */ @@ -652,7 +743,7 @@ static void rlc_am_plan_phase(uint32_t me) { #if RLC_AM_WORKQ /* Nothing planned but work remains (e.g. the grant cannot hold even a header): re-arm, or the entity would drop out of the idle check. */ - if (rlc_ctx[u].list.sduNum != 0 || e->so_next != 0u) + if (RLC_AM_QUEUED(u) || e->so_next != 0u) rlc_am_bm_set(rlc_am_bm_ready, u); #endif } @@ -996,6 +1087,15 @@ void rlc_am_status(void) { retired in order, their last_sn values are monotonic, so the first node that is not acknowledged ends the scan. */ uint32_t freed = 0u; +#if RLC_AM_RING + { + rlc_ring_t *rg = &rlc_ring[u]; + uint32_t a = atomic_load_explicit(&rg->ack, memory_order_relaxed); + const uint32_t hd = atomic_load_explicit(&rg->head, memory_order_acquire); + while (a != hd && rlc_sn_lt(rg->slot[a & RLC_RING_MASK].last_sn, got_ack_sn)) { a++; freed++; } + atomic_store_explicit(&rg->ack, a, memory_order_release); + } +#else while (1) { Node *head = NULL; if (list_peek_n((spinlock_t *)RLC_SENT_LOCK(u), &ctx->sent_list, @@ -1009,6 +1109,7 @@ void rlc_am_status(void) { RLC_NODE_FREE(node); freed++; } +#endif atomic_store_explicit(&ctx->vtNextAck, got_ack_sn, memory_order_relaxed); ctx->acksn = got_ack_sn; @@ -1231,7 +1332,7 @@ int rlc_am_idle(void) { for (uint32_t u = 0u; u < NUM_USERS; u++) { if (atomic_load_explicit(&rlc_am_ent[u].gen, memory_order_acquire) & 1u) return 0; - if (rlc_ctx[u].list.sduNum != 0) return 0; + if (RLC_AM_QUEUED(u)) return 0; if (rlc_am_ent[u].so_next != 0u) return 0; } return 1; diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.h b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.h index 9818b2d..907f5d8 100644 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.h +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.h @@ -209,6 +209,46 @@ #define RLC_AM_CLAIM_CHUNK 4u #endif +/* --- descriptor ring to-send queue (RLC_AM_RING) --------------------------- */ + +/* RLC_AM_RING=1 replaces an entity's linked to-send / sent lists with one array ring of SDU + descriptors. Built for TC1 (one entity served by many cores), where the owner core walking a + linked list across the mesh -- a dependent remote load per node -- and 15 producers contending + for its lock made the owner the serial bottleneck (plan 53% + commit 31% of its time). + + tail producers claim slot `tail++` (one atomic add), fill it, then publish seq = idx + 1 + head the owner: first SDU not fully sent. Plan reads a batch of published slots with + independent loads; commit stamps last_sn and advances head -- no lock, no node + ack the STATUS core: first SDU not acknowledged. STATUS advances it; nothing to free + + Slots between ack and head are the "sent, awaiting ACK" SDUs, [head, tail) the to-send queue. + A producer waits if the ring is full (tail - ack == size). */ +#ifndef RLC_AM_RING +#define RLC_AM_RING 0 +#endif +/* RLC_AM_PRIV_PLAN=1 (cross-tile AM): plan in the owner tile's private partition, publish the + executor fields to the shared plan. The shared plan is ~7 KB spread over ~28 home tiles; the + vector planner reading and writing it across the mesh was most of the owner's time. */ +#ifndef RLC_AM_PRIV_PLAN +#define RLC_AM_PRIV_PLAN 0 +#endif +#define RLC_AM_PRIV_PLAN_BASE 0xB8000000u /* above the partition boundary: tile-private */ +#ifndef RLC_AM_RING_SIZE +#define RLC_AM_RING_SIZE 16384u /* power of two */ +#endif +typedef struct { + volatile uint32_t seq; /* idx + 1 once published */ + uint32_t data; /* payload source */ + uint32_t len; + uint32_t last_sn; /* SN of the SDU's final segment, set at commit */ +} rlc_ring_slot_t; +typedef struct { + _Atomic uint32_t tail __attribute__((aligned(64))); + _Atomic uint32_t head __attribute__((aligned(64))); + _Atomic uint32_t ack __attribute__((aligned(64))); + rlc_ring_slot_t slot[RLC_AM_RING_SIZE] __attribute__((aligned(64))); +} rlc_ring_t; + /* --- scatter-gather output (RLC_DL_EXEC_SGL) ----------------------------- */ typedef struct { @@ -229,6 +269,11 @@ typedef struct { /* Published grant. `gen` is odd while a grant is open; plan/tb/n are written before it is bumped and stay stable until the grant closes. */ rlc_plan_t *plan; +#if RLC_AM_PRIV_PLAN + /* The owner's working copy, in its tile's private partition: the planner and commit run on it + locally; only the fields the executors read are published to `plan` (shared). */ + rlc_plan_t *plan_priv; +#endif uint8_t *tb; uint32_t n; uint32_t tb_used; From 40c4b72db9788d9d77d7f4682995330f7d2cd74c Mon Sep 17 00:00:00 2001 From: Zexin Fu Date: Wed, 30 Sep 2026 08:22:05 +0200 Subject: [PATCH 38/48] worklog: remap hashes after rewording 2094188 --- reports/history_rewrite_2026-09-30.map | 39 ++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) create mode 100644 reports/history_rewrite_2026-09-30.map diff --git a/reports/history_rewrite_2026-09-30.map b/reports/history_rewrite_2026-09-30.map new file mode 100644 index 0000000..f9c206d --- /dev/null +++ b/reports/history_rewrite_2026-09-30.map @@ -0,0 +1,39 @@ +# old new subject +2094188 c7ddb5d [RTL] add insitu_cache_ooc_wrapper: OOC timing harness for one L1 cache ctrl +7325757 7cbc7a2 rlc: AM transport-block assembly (DL) and reassembly (UL) +db94852 ec7a2ff rlc: fence the UL phase barriers; align uplink to the documented 160 B profile +de08892 eea647a worklog: RTL reference batch, bandwidth reproduces pristine exactly +0346ebf 4239973 rlc: fence the TTI phase barriers +aa7ad50 d11b98c notes: synchronisation is not visibility -- four instances of one defect +691d316 22ad3e4 notes: read the generated artefact, not the config +c47d883 909b88d notes: dependency tree is tool-owned; a marker inside it can outlive a revert +e7ad2d4 ccd5077 notes: an assertion that can outlive its condition must carry its own falsifier +136fe71 18ae20d rlc: read the participation-mask register back instead of echoing what we wrote +577ba57 523b8e2 notes: RLC partial-barrier design is wrong at more than one tile +171c79d dab460d notes: barrier done is broadcast cluster-wide, so the mask gates arrival not release +0143e71 aaec01a notes: record the refuted workaround for defect 2 explicitly +d6d7439 c08c1fc notes: the mechanism was checking claims against artefacts, not descriptions +f3269de 3b4b1a0 reports: RTL reference batch 2026-09-08 -- cycle-identity established on two kernels +681813e 20cb24a worklog: batch complete; partial-barrier design broken at three levels +01d17a5 317b85c reports: record that the batch measured T3.1-T3.15, not the recommended T3.1-T3.12 +a05aeea 3a584af notes: relative log paths make cwd a shared resource across sessions +a750067 3488749 notes: the transferable part is the habit -- grep for what a thing writes before running it +246b430 9cd4457 reports: pristine arm clears cache-mix-smoke and makes it a third cycle-identity kernel +a9c647f 4a9995a reports: qualify the sensitivity argument -- the race window width is unmeasured +dedde97 cbc45bf reports: close the T3.1-T3.15 batch record; pin the T3.1-T3.12 state, unrun +6df0e68 dd5531e rlc: fix partial-barrier misuse -- arm on entry, keep non-participants out, restore on exit +a79e83b 671462c notes: the fix requires masked semantics -- deadlocks without them, by construction +145d66a 46e1a33 rlc: the grant verifier still assumed SN advances per PDU +e0f505c 3da7786 rlc: one AM progress line per grant, always +843032d 4a5b0de worklog: partial-barrier fix validated; AM mismatch column resolved as three bugs +b6eb72f 4245048 worklog: wedge signature absent at 64 cores/M48; original observation retracted as confounded +32b5198 a0e5d3d notes: five of six were cross-artefact, one was re-reading the reference +00ab4ef da9f0b6 rlc: TTI loop never terminated with the work queue on; fix polls, UL rate, phase cost +a3ced2b 9ac50f9 worklog: kernel review and four fixes +2cc5b8a 78a00b0 rlc: software perf-probe hooks (RLC_PROBE=1, default builds unchanged) +09fba4d e16dd15 rlc: full-cluster DP test cases (TC1/TC2/TC3, 64 producers + 192 consumers), probe targets +eb9259e 3ba3e5d rlc: lock/flag cache-line padding (RLC_PAD_SYNC), paced arrival (RLC_ARRIVAL_PPS), multi-slot sweep targets +4942fc4 2cf725c rlc: per-group packet streams and node pools (RLC_GROUP_STREAMS) with work stealing +33fb09d 1bfe7b2 rlc: tile affinity on a half-private L1, AM in-tile and cross-tile, batched AM commit +b997edd 2e03e38 rlc: AM tile STATUS on a dirty bitmap, multiple grants per owner per TTI +0b40899 82613d3 rlc: TC1 at target -- descriptor-ring to-send queue, owner plans in its private partition From 2db3274cdd32f6396268ff72326b8e603e612cf5 Mon Sep 17 00:00:00 2001 From: Zexin Fu Date: Wed, 30 Sep 2026 08:33:47 +0200 Subject: [PATCH 39/48] bump insitu cache dep --- Bender.lock | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Bender.lock b/Bender.lock index aa9373c..7fe072c 100644 --- a/Bender.lock +++ b/Bender.lock @@ -109,7 +109,7 @@ packages: - obi - register_interface insitu-cache: - revision: 189bf8cd5b7a49cde3b6aa5b75590ee15521eaf9 + revision: 654e1760a944d539e27661701343b0e22a17e468 version: null source: Git: https://github.com/pulp-platform/Insitu-Cache.git From f07a94be60a17b50288e794ee5d433eef4ad5313 Mon Sep 17 00:00:00 2001 From: Zexin Fu Date: Wed, 14 Oct 2026 23:11:38 +0200 Subject: [PATCH 40/48] bump insitu cache dep --- Bender.lock | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Bender.lock b/Bender.lock index 7fe072c..30a569c 100644 --- a/Bender.lock +++ b/Bender.lock @@ -109,7 +109,7 @@ packages: - obi - register_interface insitu-cache: - revision: 654e1760a944d539e27661701343b0e22a17e468 + revision: d7a526ebc965c3c9808f348b377d06f4479cc4ab version: null source: Git: https://github.com/pulp-platform/Insitu-Cache.git From 497a60dfc654bef6dc78f81b545c3481cbf73d0c Mon Sep 17 00:00:00 2001 From: Zexin Fu Date: Wed, 14 Oct 2026 23:19:54 +0200 Subject: [PATCH 41/48] rlc: port the RLC test targets to software/rlc after the main rebase main moved the RLC test to software/rlc with its own CMakeLists and moved the shared test macros to software/cmake/CachePoolTests.cmake. The RLC targets and macros that lived in software/tests/CMakeLists.txt move here. The per-kernel add_library() lines are dropped: rlc.c needs a per-variant DATAHEADER that a library target cannot get, and nothing linked them. The host unit tests move with the kernel. --- software/rlc/CMakeLists.txt | 549 +++++++++++++++++- .../test/test_rlc_plan.c | 0 .../test/test_rlc_ul.c | 0 3 files changed, 544 insertions(+), 5 deletions(-) rename software/{tests => rlc}/multi_producer_single_consumer_double_linked_list/test/test_rlc_plan.c (100%) rename software/{tests => rlc}/multi_producer_single_consumer_double_linked_list/test/test_rlc_ul.c (100%) diff --git a/software/rlc/CMakeLists.txt b/software/rlc/CMakeLists.txt index a9495e0..cad7d82 100644 --- a/software/rlc/CMakeLists.txt +++ b/software/rlc/CMakeLists.txt @@ -2,11 +2,13 @@ # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -add_library(printf_lock multi_producer_single_consumer_double_linked_list/kernel/printf_lock.c) -add_library(llist multi_producer_single_consumer_double_linked_list/kernel/llist.c) -add_library(mm multi_producer_single_consumer_double_linked_list/kernel/mm.c) -add_library(rlc multi_producer_single_consumer_double_linked_list/kernel/rlc.c) -add_library(data_move_vec multi_producer_single_consumer_double_linked_list/kernel/data_move_vec.c) +# RLC data-plane kernel. +# +# The kernel sources are compiled into each test executable through main.c's +# textual #include, so no per-kernel libraries are built here: rlc.c needs the +# per-variant DATAHEADER define, which a shared library target cannot get. +# The shared test macros and the benchmark/spin_lock/mcs_lock libraries come +# from software/cmake/CachePoolTests.cmake. # add_snitch_test(multi_producer_single_consumer_double_linked_list multi_producer_single_consumer_double_linked_list/main.c) # add_spatz_test_threeParam(multi_producer_single_consumer_double_linked_list multi_producer_single_consumer_double_linked_list/main.c 1 1350 1000) @@ -14,3 +16,540 @@ add_library(data_move_vec multi_producer_single_consumer_double_linked_list/kern add_spatz_test_threeParam(multi_producer_single_consumer_double_linked_list multi_producer_single_consumer_double_linked_list/main.c 1 1350 300) add_spatz_test_threeParam(multi_producer_single_consumer_double_linked_list multi_producer_single_consumer_double_linked_list/main.c 1 1350 100) add_spatz_test_threeParam(multi_producer_single_consumer_double_linked_list multi_producer_single_consumer_double_linked_list/main.c 1 1350 10) +# TC2 multi-user peak rate: 48 UEs, 800 B packets (data_48_800_*.h) +add_spatz_test_threeParam(multi_producer_single_consumer_double_linked_list multi_producer_single_consumer_double_linked_list/main.c 48 800 300) +add_spatz_test_threeParam(multi_producer_single_consumer_double_linked_list multi_producer_single_consumer_double_linked_list/main.c 48 800 1000) + +# RLC variant with explicit producer/consumer core counts (thread-scaling runs). +# RLC AM mode: grant-based transport-block assembly (RLC_TB_MODE=1) instead of +# the legacy copy-to-fixed-destination path. `verify` builds with the planner +# self-check, which runs the scalar reference alongside the vectorised planner +# and counts divergences. +macro(add_spatz_test_rlc_am_wq name file param1 param2 param3 pcore ccore grant verify) + set(target_name ${name}_M${param1}_N${param2}_K${param3}_P${pcore}_C${ccore}_am_G${grant}_wq) + add_snitch_test(${target_name} ${file}) + target_link_libraries(test-${SNITCH_TEST_PREFIX}${target_name} benchmark spin_lock mcs_lock ${SNITCH_RUNTIME}) + target_compile_definitions(test-${SNITCH_TEST_PREFIX}${target_name} PUBLIC + DATAHEADER="data/data_${param1}_${param2}_${param3}.h" + PRODUCER_CORE_NUM=${pcore} CONSUMER_CORE_NUM=${ccore} + RLC_TB_MODE=1 RLC_GRANT_BYTES=${grant} RLC_AM_WORKQ=1) + if(${verify}) + target_compile_definitions(test-${SNITCH_TEST_PREFIX}${target_name} PUBLIC + RLC_PLAN_VERIFY=1 RLC_SELF_CHECK=1) + endif() +endmacro() + +macro(add_spatz_test_rlc_am name file param1 param2 param3 pcore ccore grant verify) + set(target_name ${name}_M${param1}_N${param2}_K${param3}_P${pcore}_C${ccore}_am_G${grant}) + add_snitch_test(${target_name} ${file}) + target_link_libraries(test-${SNITCH_TEST_PREFIX}${target_name} benchmark spin_lock mcs_lock ${SNITCH_RUNTIME}) + target_compile_definitions(test-${SNITCH_TEST_PREFIX}${target_name} PUBLIC + DATAHEADER="data/data_${param1}_${param2}_${param3}.h" + PRODUCER_CORE_NUM=${pcore} CONSUMER_CORE_NUM=${ccore} + RLC_TB_MODE=1 RLC_GRANT_BYTES=${grant}) + if(${verify}) + # Diff the vectorised planner against the scalar reference, and decode + # every assembled transport block back to check the execute stage. + target_compile_definitions(test-${SNITCH_TEST_PREFIX}${target_name} PUBLIC + RLC_PLAN_VERIFY=1 RLC_SELF_CHECK=1) + endif() +endmacro() + +macro(add_spatz_test_rlc name file param1 param2 param3 pcore ccore) + set(target_name ${name}_M${param1}_N${param2}_K${param3}_P${pcore}_C${ccore}) + add_snitch_test(${target_name} ${file}) + target_link_libraries(test-${SNITCH_TEST_PREFIX}${target_name} benchmark spin_lock mcs_lock ${SNITCH_RUNTIME}) + target_compile_definitions(test-${SNITCH_TEST_PREFIX}${target_name} PUBLIC + DATAHEADER="data/data_${param1}_${param2}_${param3}.h" + PRODUCER_CORE_NUM=${pcore} CONSUMER_CORE_NUM=${ccore}) +endmacro() +add_spatz_test_rlc(multi_producer_single_consumer_double_linked_list multi_producer_single_consumer_double_linked_list/main.c 48 800 300 2 2) +add_spatz_test_rlc(multi_producer_single_consumer_double_linked_list multi_producer_single_consumer_double_linked_list/main.c 48 800 300 2 4) +add_spatz_test_rlc(multi_producer_single_consumer_double_linked_list multi_producer_single_consumer_double_linked_list/main.c 48 800 300 4 4) +add_spatz_test_rlc(multi_producer_single_consumer_double_linked_list multi_producer_single_consumer_double_linked_list/main.c 48 800 300 2 8) +add_spatz_test_rlc(multi_producer_single_consumer_double_linked_list multi_producer_single_consumer_double_linked_list/main.c 48 800 300 4 8) + +# --- AM transport-block assembly ------------------------------------------- +# TC1 single entity: one owner plans, the other consumers help execute the +# same transport block -- the case that needs intra-entity parallelism. +add_spatz_test_rlc_am(multi_producer_single_consumer_double_linked_list multi_producer_single_consumer_double_linked_list/main.c 1 1350 100 2 2 8192 1) +add_spatz_test_rlc_am(multi_producer_single_consumer_double_linked_list multi_producer_single_consumer_double_linked_list/main.c 1 1350 100 2 4 8192 0) +# TC2 multi entity. +add_spatz_test_rlc_am(multi_producer_single_consumer_double_linked_list multi_producer_single_consumer_double_linked_list/main.c 48 800 300 2 2 8192 1) +add_spatz_test_rlc_am(multi_producer_single_consumer_double_linked_list multi_producer_single_consumer_double_linked_list/main.c 48 800 300 4 8 8192 0) +# Small grant -> segmentation on nearly every grant. +add_spatz_test_rlc_am(multi_producer_single_consumer_double_linked_list multi_producer_single_consumer_double_linked_list/main.c 1 1350 100 2 4 1024 1) + +# --- Performance-probe variants --------------------------------------------- +# Same kernels with RLC_PROBE=1: they also emit software probe events (role, phase, SDU/PDU, +# queue depth, per-packet latency, TTI) for the GVSoC perf-probe collector. Targets get a +# `_probe` suffix; the default targets above are untouched and stay byte-identical. +macro(add_spatz_test_rlc_probe suffix name file param1 param2 param3) + set(target_name ${name}_M${param1}_N${param2}_K${param3}${suffix}_probe) + add_snitch_test(${target_name} ${file}) + target_link_libraries(test-${SNITCH_TEST_PREFIX}${target_name} benchmark spin_lock mcs_lock ${SNITCH_RUNTIME}) + target_compile_definitions(test-${SNITCH_TEST_PREFIX}${target_name} PUBLIC + DATAHEADER="data/data_${param1}_${param2}_${param3}.h" RLC_PROBE=1 ${ARGN}) +endmacro() +add_spatz_test_rlc_probe("" multi_producer_single_consumer_double_linked_list multi_producer_single_consumer_double_linked_list/main.c 1 1350 100) +add_spatz_test_rlc_probe("" multi_producer_single_consumer_double_linked_list multi_producer_single_consumer_double_linked_list/main.c 48 800 300) +add_spatz_test_rlc_probe("_P2_C2_am_G8192" multi_producer_single_consumer_double_linked_list multi_producer_single_consumer_double_linked_list/main.c 1 1350 10 + PRODUCER_CORE_NUM=2 CONSUMER_CORE_NUM=2 RLC_TB_MODE=1 RLC_GRANT_BYTES=8192) + +# --- Full-cluster DP test cases (16 groups / 64 tiles / 256 cores) ------------ +# One DL slot of packets per test case (DP Introduction: TC1 1157, TC2 4882, TC3 1963 per slot). +# Core layout from the data header: per tile, core 0 produces and cores 1-3 consume, so every +# core of the cluster works (64 producers, 192 consumers). `layout` is both the header suffix and +# the target suffix. The node pool is sized to the packet count: nodes are only freed by ACKs, +# which come two per entity, so with many entities most nodes stay live to the end, and an +# exhausted pool drops the packet whose descriptor the producer already took. +# The data header is generated from script/pdcp_pkg____.json at build time (it is +# 10-200 MB, too large to keep in git). +set(RLC_DIR ${CMAKE_CURRENT_SOURCE_DIR}/multi_producer_single_consumer_double_linked_list) +# `variant` is appended to the target name and says which extra defines (ARGN) it carries. +macro(add_spatz_test_rlc_full layout variant name file param1 param2 param3) + string(TOLOWER ${layout} layout_lc) + set(rlc_cfg ${param1}_${param2}_${param3}_${layout_lc}) + if(NOT TARGET rlc_data_${rlc_cfg}) + add_custom_command( + OUTPUT ${RLC_DIR}/data/data_${rlc_cfg}.h + COMMAND python3 ${RLC_DIR}/script/generate_pdcp_pkg.py ${RLC_DIR}/script/pdcp_pkg_${rlc_cfg}.json + -o ${RLC_DIR}/data/data_${rlc_cfg}.h + DEPENDS ${RLC_DIR}/script/pdcp_pkg_${rlc_cfg}.json ${RLC_DIR}/script/generate_pdcp_pkg.py + COMMENT "Generating RLC data header data_${rlc_cfg}.h") + add_custom_target(rlc_data_${rlc_cfg} DEPENDS ${RLC_DIR}/data/data_${rlc_cfg}.h) + endif() + foreach(probe 0 1) + if(${probe}) + set(target_name ${name}_M${param1}_N${param2}_K${param3}_${layout}${variant}_probe) + else() + set(target_name ${name}_M${param1}_N${param2}_K${param3}_${layout}${variant}) + endif() + add_snitch_test(${target_name} ${file}) + target_link_libraries(test-${SNITCH_TEST_PREFIX}${target_name} benchmark spin_lock mcs_lock ${SNITCH_RUNTIME}) + target_compile_definitions(test-${SNITCH_TEST_PREFIX}${target_name} PUBLIC + DATAHEADER="data/data_${param1}_${param2}_${param3}_${layout_lc}.h" + MM_POOL_PAGES=${param3} RLC_PROBE=${probe} ${ARGN}) + add_dependencies(test-${SNITCH_TEST_PREFIX}${target_name} rlc_data_${rlc_cfg}) + endforeach() +endmacro() +add_spatz_test_rlc_full(P64_C192 "" multi_producer_single_consumer_double_linked_list multi_producer_single_consumer_double_linked_list/main.c 1 1350 1157) +add_spatz_test_rlc_full(P64_C192 "" multi_producer_single_consumer_double_linked_list multi_producer_single_consumer_double_linked_list/main.c 48 800 4882) +add_spatz_test_rlc_full(P64_C192 "" multi_producer_single_consumer_double_linked_list multi_producer_single_consumer_double_linked_list/main.c 4800 800 1963) + +# Sustained-load sweep: 8 DL slots (TC1, TC3) or 4 (TC2, the 16 MiB source window holds 4.2), on +# 4, 64 and 256 cores. `_pad` = RLC_PAD_SYNC (one cache line per lock/flag, look before locking); +# `_paced` adds RLC_ARRIVAL_PPS = the test case's packet rate, so the offered load is the target +# and latency is measured from each packet's arrival. +set(RLC_T multi_producer_single_consumer_double_linked_list) +foreach(rlc_layout P2_C2 P16_C48 P64_C192) + add_spatz_test_rlc_full(${rlc_layout} "_pad" ${RLC_T} ${RLC_T}/main.c 1 1350 9256 RLC_PAD_SYNC=1) + add_spatz_test_rlc_full(${rlc_layout} "_pad_paced" ${RLC_T} ${RLC_T}/main.c 1 1350 9256 RLC_PAD_SYNC=1 RLC_ARRIVAL_PPS=1851851) + add_spatz_test_rlc_full(${rlc_layout} "_pad" ${RLC_T} ${RLC_T}/main.c 48 800 19528 RLC_PAD_SYNC=1) + add_spatz_test_rlc_full(${rlc_layout} "_pad_paced" ${RLC_T} ${RLC_T}/main.c 48 800 19528 RLC_PAD_SYNC=1 RLC_ARRIVAL_PPS=7812500) + add_spatz_test_rlc_full(${rlc_layout} "_pad" ${RLC_T} ${RLC_T}/main.c 4800 800 15704 RLC_PAD_SYNC=1) + add_spatz_test_rlc_full(${rlc_layout} "_pad_paced" ${RLC_T} ${RLC_T}/main.c 4800 800 15704 RLC_PAD_SYNC=1 RLC_ARRIVAL_PPS=3125000) +endforeach() + +# `_grp`: RLC_GROUP_STREAMS -- per-group descriptor streams and node pools (no cluster-wide lock +# on the producer path). +foreach(rlc_layout P16_C48 P64_C192) + add_spatz_test_rlc_full(${rlc_layout} "_pad_grp" ${RLC_T} ${RLC_T}/main.c 1 1350 9256 RLC_PAD_SYNC=1 RLC_GROUP_STREAMS=1) + add_spatz_test_rlc_full(${rlc_layout} "_pad_grp_paced" ${RLC_T} ${RLC_T}/main.c 1 1350 9256 RLC_PAD_SYNC=1 RLC_GROUP_STREAMS=1 RLC_ARRIVAL_PPS=1851851) + add_spatz_test_rlc_full(${rlc_layout} "_pad_grp" ${RLC_T} ${RLC_T}/main.c 48 800 19528 RLC_PAD_SYNC=1 RLC_GROUP_STREAMS=1) + add_spatz_test_rlc_full(${rlc_layout} "_pad_grp_paced" ${RLC_T} ${RLC_T}/main.c 48 800 19528 RLC_PAD_SYNC=1 RLC_GROUP_STREAMS=1 RLC_ARRIVAL_PPS=7812500) + add_spatz_test_rlc_full(${rlc_layout} "_pad_grp" ${RLC_T} ${RLC_T}/main.c 4800 800 15704 RLC_PAD_SYNC=1 RLC_GROUP_STREAMS=1) + add_spatz_test_rlc_full(${rlc_layout} "_pad_grp_paced" ${RLC_T} ${RLC_T}/main.c 4800 800 15704 RLC_PAD_SYNC=1 RLC_GROUP_STREAMS=1 RLC_ARRIVAL_PPS=3125000) +endforeach() + +# `_tile`: RLC_TILE_AFFINITY -- every UE owned by one tile, its state in that tile's private L1 +# partition (2 of 4 banks private, 2 shared); `_L64` datasets put every packet on its own lines. +add_spatz_test_rlc_full(P48_C144_L64 "_tile" ${RLC_T} ${RLC_T}/main.c 48 800 19528 RLC_PAD_SYNC=1 RLC_TILE_AFFINITY=1) +add_spatz_test_rlc_full(P48_C144_L64 "_tile_paced" ${RLC_T} ${RLC_T}/main.c 48 800 19528 RLC_PAD_SYNC=1 RLC_TILE_AFFINITY=1 RLC_ARRIVAL_PPS=7812500) +foreach(rlc_layout P64_C192_L64 P48_C144_L64) + add_spatz_test_rlc_full(${rlc_layout} "_tile" ${RLC_T} ${RLC_T}/main.c 4800 800 15704 RLC_PAD_SYNC=1 RLC_TILE_AFFINITY=1) + add_spatz_test_rlc_full(${rlc_layout} "_tile_paced" ${RLC_T} ${RLC_T}/main.c 4800 800 15704 RLC_PAD_SYNC=1 RLC_TILE_AFFINITY=1 RLC_ARRIVAL_PPS=3125000) +endforeach() + +# `_am_tile`: RLC AM (grant-based transport blocks) on the tile-affinity layout; the TTI loop runs +# inside each worker tile. +add_spatz_test_rlc_full(P48_C144_L64 "_am_tile" ${RLC_T} ${RLC_T}/main.c 48 800 19528 RLC_TB_MODE=1 RLC_GRANT_BYTES=8192 RLC_PAD_SYNC=1 RLC_TILE_AFFINITY=1) +add_spatz_test_rlc_full(P48_C144_L64 "_am_tile_paced" ${RLC_T} ${RLC_T}/main.c 48 800 19528 RLC_TB_MODE=1 RLC_GRANT_BYTES=8192 RLC_PAD_SYNC=1 RLC_TILE_AFFINITY=1 RLC_ARRIVAL_PPS=7812500) +foreach(rlc_layout P64_C192_L64 P48_C144_L64) + add_spatz_test_rlc_full(${rlc_layout} "_am_tile" ${RLC_T} ${RLC_T}/main.c 4800 800 15704 RLC_TB_MODE=1 RLC_GRANT_BYTES=8192 RLC_PAD_SYNC=1 RLC_TILE_AFFINITY=1) + add_spatz_test_rlc_full(${rlc_layout} "_am_tile_paced" ${RLC_T} ${RLC_T}/main.c 4800 800 15704 RLC_TB_MODE=1 RLC_GRANT_BYTES=8192 RLC_PAD_SYNC=1 RLC_TILE_AFFINITY=1 RLC_ARRIVAL_PPS=3125000) +endforeach() + +# `_am_x`: TC1 -- one UE served across tiles. The owner plans, helpers on other tiles copy. What +# crosses tiles (entity, plan, transport block, queue) is below the partition boundary (shared); +# payload sources stay private. 2 of 4 banks private; producers on per-group streams. +set(RLC_AMX RLC_TB_MODE=1 RLC_MAX_PDUS_PER_GRANT=128 RLC_AM_CLAIM_CHUNK=2 RLC_TB_BASE=0x9A000000u + RLC_AM_ALLOW_CROSS_TILE_TB=1 RLC_PAD_SYNC=1 RLC_GROUP_STREAMS=1 RLC_PRIVATE_BANKS=2) +foreach(rlc_layout P16_C48_L64 P64_C192_L64) + # `_am_xb`: + RLC_AM_BATCH -- the owner's commit moves the finished chain in two O(1) locked + # steps and plans from a lock-free walk (it was 80% of the owner's time, per-node locking). + add_spatz_test_rlc_full(${rlc_layout} "_am_xb" ${RLC_T} ${RLC_T}/main.c 1 1350 9256 ${RLC_AMX} RLC_GRANT_BYTES=131072 RLC_AM_BATCH=1) + add_spatz_test_rlc_full(${rlc_layout} "_am_xb_paced" ${RLC_T} ${RLC_T}/main.c 1 1350 9256 ${RLC_AMX} RLC_GRANT_BYTES=131072 RLC_AM_BATCH=1 RLC_ARRIVAL_PPS=1851851) + # `_am_xr`: + RLC_AM_RING -- descriptor-ring to-send queue (no list, no node pool, no queue lock). + add_spatz_test_rlc_full(${rlc_layout} "_am_xr" ${RLC_T} ${RLC_T}/main.c 1 1350 9256 ${RLC_AMX} RLC_GRANT_BYTES=131072 RLC_AM_RING=1 RLC_AM_WORKQ=0) + add_spatz_test_rlc_full(${rlc_layout} "_am_xr_paced" ${RLC_T} ${RLC_T}/main.c 1 1350 9256 ${RLC_AMX} RLC_GRANT_BYTES=131072 RLC_AM_RING=1 RLC_AM_WORKQ=0 RLC_ARRIVAL_PPS=1851851) + # `_am_xrp`: + RLC_AM_PRIV_PLAN -- the owner plans in its tile's private partition. + add_spatz_test_rlc_full(${rlc_layout} "_am_xrp" ${RLC_T} ${RLC_T}/main.c 1 1350 9256 ${RLC_AMX} RLC_GRANT_BYTES=131072 RLC_AM_RING=1 RLC_AM_WORKQ=0 RLC_AM_PRIV_PLAN=1) + add_spatz_test_rlc_full(${rlc_layout} "_am_xrp_paced" ${RLC_T} ${RLC_T}/main.c 1 1350 9256 ${RLC_AMX} RLC_GRANT_BYTES=131072 RLC_AM_RING=1 RLC_AM_WORKQ=0 RLC_AM_PRIV_PLAN=1 RLC_ARRIVAL_PPS=1851851) + add_spatz_test_rlc_full(${rlc_layout} "_am_x" ${RLC_T} ${RLC_T}/main.c 1 1350 9256 ${RLC_AMX} RLC_GRANT_BYTES=131072) + add_spatz_test_rlc_full(${rlc_layout} "_am_x_paced" ${RLC_T} ${RLC_T}/main.c 1 1350 9256 ${RLC_AMX} RLC_GRANT_BYTES=131072 RLC_ARRIVAL_PPS=1851851) +endforeach() + +# `_am_tile_g8`: TC3 with up to 8 grants per owner per TTI (a TC3 UE holds 1-3 SDUs, so one grant +# per owner per TTI moved a handful of packets per 4 barriers); 4 KB grants, 16 PDUs max. +foreach(rlc_layout P64_C192_L64 P48_C144_L64) + add_spatz_test_rlc_full(${rlc_layout} "_am_tile_g8" ${RLC_T} ${RLC_T}/main.c 4800 800 15704 RLC_TB_MODE=1 RLC_GRANT_BYTES=4096 RLC_MAX_PDUS_PER_GRANT=16 RLC_AM_TILE_GRANTS=8 RLC_PAD_SYNC=1 RLC_TILE_AFFINITY=1) + add_spatz_test_rlc_full(${rlc_layout} "_am_tile_g8_paced" ${RLC_T} ${RLC_T}/main.c 4800 800 15704 RLC_TB_MODE=1 RLC_GRANT_BYTES=4096 RLC_MAX_PDUS_PER_GRANT=16 RLC_AM_TILE_GRANTS=8 RLC_PAD_SYNC=1 RLC_TILE_AFFINITY=1 RLC_ARRIVAL_PPS=3125000) +endforeach() + +# Scalar-planner control: same scan algorithm, RVV primitives swapped for their +# plain-C twins (RLC_PLAN_VECTOR=0). Executes no vector instruction in the +# planner at all, so it separates "my algorithm is wrong" from "my RVV is wrong" +# in one run. +add_snitch_test(multi_producer_single_consumer_double_linked_list_M1_N1350_K100_P2_C2_am_G8192_novec + multi_producer_single_consumer_double_linked_list/main.c) +target_link_libraries(test-${SNITCH_TEST_PREFIX}multi_producer_single_consumer_double_linked_list_M1_N1350_K100_P2_C2_am_G8192_novec + benchmark spin_lock mcs_lock ${SNITCH_RUNTIME}) +target_compile_definitions(test-${SNITCH_TEST_PREFIX}multi_producer_single_consumer_double_linked_list_M1_N1350_K100_P2_C2_am_G8192_novec PUBLIC + DATAHEADER="data/data_1_1350_100.h" + PRODUCER_CORE_NUM=2 CONSUMER_CORE_NUM=2 + RLC_TB_MODE=1 RLC_GRANT_BYTES=8192 RLC_PLAN_IMPL=0 RLC_SELF_CHECK=1) + +# Bisect ladder for the scan planner. RLC_PLAN_VECTOR is a bitmask over the +# planner's primitives (1 maps, 2 prefix-sum, 4 first-crossing); each has an +# RVV form and a plain-C twin with identical semantics. Running these isolates +# a vector-execution failure to one primitive without needing a PC trace. +macro(add_rlc_am_bisect suffix vecmask) + set(tn multi_producer_single_consumer_double_linked_list_M1_N1350_K100_P2_C2_am_G8192_${suffix}) + add_snitch_test(${tn} multi_producer_single_consumer_double_linked_list/main.c) + target_link_libraries(test-${SNITCH_TEST_PREFIX}${tn} benchmark spin_lock mcs_lock ${SNITCH_RUNTIME}) + target_compile_definitions(test-${SNITCH_TEST_PREFIX}${tn} PUBLIC + DATAHEADER="data/data_1_1350_100.h" + PRODUCER_CORE_NUM=2 CONSUMER_CORE_NUM=2 + RLC_TB_MODE=1 RLC_GRANT_BYTES=8192 RLC_SELF_CHECK=1 + RLC_PLAN_IMPL=1 RLC_PLAN_VECTOR=${vecmask}) +endmacro() +add_rlc_am_bisect(scanC 0) # scan planner, every primitive in plain C +add_rlc_am_bisect(v1 1) # + maps only +add_rlc_am_bisect(v2 2) # + prefix-sum only +# WARNING: v4 emits vmsgtu.vx and vmerge.vvm. Spatz's RTL decodes both and +# implements neither, so a pass here on any simulator that models them says +# nothing about hardware -- on Spatz they would corrupt silently. +add_rlc_am_bisect(v4 4) # + first-crossing only + +# Payload-verification target sized to FINISH on RTL. RTL runs the AM path at +# ~52 cycles/s, so the K100 checked build cannot reach EOC inside an hour. This +# uses the 10-packet header and drops RLC_PLAN_VERIFY (the planner is already +# cleared by the host test and by GVSoC's vector-vs-reference pass), keeping +# only RLC_SELF_CHECK -- the transport-block decode. That is the one question +# GVSoC can no longer answer, since its cross-core shared-data path is unsound. +add_snitch_test(multi_producer_single_consumer_double_linked_list_M1_N1350_K10_P2_C2_am_G8192_tbchk + multi_producer_single_consumer_double_linked_list/main.c) +target_link_libraries(test-${SNITCH_TEST_PREFIX}multi_producer_single_consumer_double_linked_list_M1_N1350_K10_P2_C2_am_G8192_tbchk + benchmark spin_lock mcs_lock ${SNITCH_RUNTIME}) +target_compile_definitions(test-${SNITCH_TEST_PREFIX}multi_producer_single_consumer_double_linked_list_M1_N1350_K10_P2_C2_am_G8192_tbchk PUBLIC + DATAHEADER="data/data_1_1350_10.h" + PRODUCER_CORE_NUM=2 CONSUMER_CORE_NUM=2 + RLC_TB_MODE=1 RLC_GRANT_BYTES=8192 RLC_SELF_CHECK=1) + +# Multi-entity AM, sized to complete on RTL. Eight entities over 24 packets +# exercises what TC2 does and TC1 cannot -- several entities per owner, the +# one-open-grant-per-owner rule, and the ownership partition -- at a twentieth +# of TC2's work. RLC_SELF_CHECK only, for the same reason as the tbchk target. +add_snitch_test(multi_producer_single_consumer_double_linked_list_M8_N1350_K24_P2_C2_am_G8192_tbchk + multi_producer_single_consumer_double_linked_list/main.c) +target_link_libraries(test-${SNITCH_TEST_PREFIX}multi_producer_single_consumer_double_linked_list_M8_N1350_K24_P2_C2_am_G8192_tbchk + benchmark spin_lock mcs_lock ${SNITCH_RUNTIME}) +target_compile_definitions(test-${SNITCH_TEST_PREFIX}multi_producer_single_consumer_double_linked_list_M8_N1350_K24_P2_C2_am_G8192_tbchk PUBLIC + DATAHEADER="data/data_8_1350_24.h" + PRODUCER_CORE_NUM=2 CONSUMER_CORE_NUM=2 + RLC_TB_MODE=1 RLC_GRANT_BYTES=8192 RLC_SELF_CHECK=1) + +# Entity-count control: 48 entities at M8's 24-packet workload. Separates +# "many entities" from "deep queues". If this passes while TC2 (48 entities, +# 300 packets) does not, the cost is queue depth -- i.e. the gather -- not the +# entity count; if it also wedges, entity count is implicated on its own. +add_snitch_test(multi_producer_single_consumer_double_linked_list_M48_N1350_K24_P2_C2_am_G8192_tbchk + multi_producer_single_consumer_double_linked_list/main.c) +target_link_libraries(test-${SNITCH_TEST_PREFIX}multi_producer_single_consumer_double_linked_list_M48_N1350_K24_P2_C2_am_G8192_tbchk + benchmark spin_lock mcs_lock ${SNITCH_RUNTIME}) +target_compile_definitions(test-${SNITCH_TEST_PREFIX}multi_producer_single_consumer_double_linked_list_M48_N1350_K24_P2_C2_am_G8192_tbchk PUBLIC + DATAHEADER="data/data_48_1350_24.h" + PRODUCER_CORE_NUM=2 CONSUMER_CORE_NUM=2 + RLC_TB_MODE=1 RLC_GRANT_BYTES=8192 RLC_SELF_CHECK=1) + +# Smallest payload check that can finish on RTL. The AM path simulates at +# ~39 cycles/s measured, so even K10 does not reach EOC in an hour. Four +# packets fit one grant (4 x 1363 = 5452 < 8192), giving 4 PDUs and ~5.4 k +# byte-compares in the verifier -- minutes, not hours. +add_snitch_test(multi_producer_single_consumer_double_linked_list_M1_N1350_K4_P2_C2_am_G8192_tbchk + multi_producer_single_consumer_double_linked_list/main.c) +target_link_libraries(test-${SNITCH_TEST_PREFIX}multi_producer_single_consumer_double_linked_list_M1_N1350_K4_P2_C2_am_G8192_tbchk + benchmark spin_lock mcs_lock ${SNITCH_RUNTIME}) +target_compile_definitions(test-${SNITCH_TEST_PREFIX}multi_producer_single_consumer_double_linked_list_M1_N1350_K4_P2_C2_am_G8192_tbchk PUBLIC + DATAHEADER="data/data_1_1350_4.h" + PRODUCER_CORE_NUM=2 CONSUMER_CORE_NUM=2 + RLC_TB_MODE=1 RLC_GRANT_BYTES=8192 RLC_SELF_CHECK=1) + +# Same multi-entity pair with the bitmap work queue (RLC_AM_WORKQ=1). The +# non-wq sweep visits EVERY entity per step and helpers spin, so cost scales +# as packets x entities: K4/M1 took 10 min, K8/M8 exceeded 60. That makes +# multi-entity RTL infeasible without the queue, which skips idle entities +# entirely -- so F5 is the enabler here, not an optimisation. +add_snitch_test(multi_producer_single_consumer_double_linked_list_M8_N1350_K8_P2_C2_am_G8192_wqchk + multi_producer_single_consumer_double_linked_list/main.c) +target_link_libraries(test-${SNITCH_TEST_PREFIX}multi_producer_single_consumer_double_linked_list_M8_N1350_K8_P2_C2_am_G8192_wqchk + benchmark spin_lock mcs_lock ${SNITCH_RUNTIME}) +target_compile_definitions(test-${SNITCH_TEST_PREFIX}multi_producer_single_consumer_double_linked_list_M8_N1350_K8_P2_C2_am_G8192_wqchk PUBLIC + DATAHEADER="data/data_8_1350_8.h" + PRODUCER_CORE_NUM=2 CONSUMER_CORE_NUM=2 + RLC_TB_MODE=1 RLC_GRANT_BYTES=8192 RLC_SELF_CHECK=1 RLC_AM_WORKQ=1) + +add_snitch_test(multi_producer_single_consumer_double_linked_list_M48_N1350_K8_P2_C2_am_G8192_wqchk + multi_producer_single_consumer_double_linked_list/main.c) +target_link_libraries(test-${SNITCH_TEST_PREFIX}multi_producer_single_consumer_double_linked_list_M48_N1350_K8_P2_C2_am_G8192_wqchk + benchmark spin_lock mcs_lock ${SNITCH_RUNTIME}) +target_compile_definitions(test-${SNITCH_TEST_PREFIX}multi_producer_single_consumer_double_linked_list_M48_N1350_K8_P2_C2_am_G8192_wqchk PUBLIC + DATAHEADER="data/data_48_1350_8.h" + PRODUCER_CORE_NUM=2 CONSUMER_CORE_NUM=2 + RLC_TB_MODE=1 RLC_GRANT_BYTES=8192 RLC_SELF_CHECK=1 RLC_AM_WORKQ=1) + +# Multi-entity pair sized for RTL. The K24 rungs extrapolate to ~62 min against +# a 60 min cap (K4 took 10 min for 4 packets), so they cannot answer anything. +# 8 packets is ~21 min. Entity count is held as the variable, matching the +# GVSoC ladder's axis, at a workload RTL can actually finish. +add_snitch_test(multi_producer_single_consumer_double_linked_list_M8_N1350_K8_P2_C2_am_G8192_tbchk + multi_producer_single_consumer_double_linked_list/main.c) +target_link_libraries(test-${SNITCH_TEST_PREFIX}multi_producer_single_consumer_double_linked_list_M8_N1350_K8_P2_C2_am_G8192_tbchk + benchmark spin_lock mcs_lock ${SNITCH_RUNTIME}) +target_compile_definitions(test-${SNITCH_TEST_PREFIX}multi_producer_single_consumer_double_linked_list_M8_N1350_K8_P2_C2_am_G8192_tbchk PUBLIC + DATAHEADER="data/data_8_1350_8.h" + PRODUCER_CORE_NUM=2 CONSUMER_CORE_NUM=2 + RLC_TB_MODE=1 RLC_GRANT_BYTES=8192 RLC_SELF_CHECK=1) + +add_snitch_test(multi_producer_single_consumer_double_linked_list_M48_N1350_K8_P2_C2_am_G8192_tbchk + multi_producer_single_consumer_double_linked_list/main.c) +target_link_libraries(test-${SNITCH_TEST_PREFIX}multi_producer_single_consumer_double_linked_list_M48_N1350_K8_P2_C2_am_G8192_tbchk + benchmark spin_lock mcs_lock ${SNITCH_RUNTIME}) +target_compile_definitions(test-${SNITCH_TEST_PREFIX}multi_producer_single_consumer_double_linked_list_M48_N1350_K8_P2_C2_am_G8192_tbchk PUBLIC + DATAHEADER="data/data_48_1350_8.h" + PRODUCER_CORE_NUM=2 CONSUMER_CORE_NUM=2 + RLC_TB_MODE=1 RLC_GRANT_BYTES=8192 RLC_SELF_CHECK=1) + +# Segmentation under test. The K4/G8192 payload check passed on RTL but +# reported segments=0: four 1360 B SDUs fit inside one 8192 B grant, so the +# whole SI / SO / partial-cursor / cross-grant-so_next path never ran. At +# G1024 a 1360 B SDU cannot fit any grant whole, so every SDU must split and +# so_next chaining becomes the thing under test. +add_snitch_test(multi_producer_single_consumer_double_linked_list_M1_N1350_K4_P2_C2_am_G1024_tbchk + multi_producer_single_consumer_double_linked_list/main.c) +target_link_libraries(test-${SNITCH_TEST_PREFIX}multi_producer_single_consumer_double_linked_list_M1_N1350_K4_P2_C2_am_G1024_tbchk + benchmark spin_lock mcs_lock ${SNITCH_RUNTIME}) +target_compile_definitions(test-${SNITCH_TEST_PREFIX}multi_producer_single_consumer_double_linked_list_M1_N1350_K4_P2_C2_am_G1024_tbchk PUBLIC + DATAHEADER="data/data_1_1350_4.h" + PRODUCER_CORE_NUM=2 CONSUMER_CORE_NUM=2 + RLC_TB_MODE=1 RLC_GRANT_BYTES=1024 RLC_SELF_CHECK=1) + +# Mirror arm: can a PASSING rung be BROKEN by layout? The M16 arm tested only +# whether a failure can be rescued. For an address-dependent corruption those +# are different questions, and only this one probes whether M32's success is a +# lucky layout rather than a property of 32 entities. +# M32 keeps passing under both -> layout inert, entity count is real +# M32 fails under either -> success is layout-contingent +add_snitch_test(multi_producer_single_consumer_double_linked_list_M32_N1350_K24_P2_C2_am_G8192_padshift + multi_producer_single_consumer_double_linked_list/main.c) +target_link_libraries(test-${SNITCH_TEST_PREFIX}multi_producer_single_consumer_double_linked_list_M32_N1350_K24_P2_C2_am_G8192_padshift + benchmark spin_lock mcs_lock ${SNITCH_RUNTIME}) +target_compile_definitions(test-${SNITCH_TEST_PREFIX}multi_producer_single_consumer_double_linked_list_M32_N1350_K24_P2_C2_am_G8192_padshift PUBLIC + DATAHEADER="data/data_32_1350_24.h" + PRODUCER_CORE_NUM=2 CONSUMER_CORE_NUM=2 + RLC_TB_MODE=1 RLC_GRANT_BYTES=8192 RLC_SELF_CHECK=1 RLC_LAYOUT_PAD=320) + +add_snitch_test(multi_producer_single_consumer_double_linked_list_M32_N1350_K24_P2_C2_am_G8192_entpad + multi_producer_single_consumer_double_linked_list/main.c) +target_link_libraries(test-${SNITCH_TEST_PREFIX}multi_producer_single_consumer_double_linked_list_M32_N1350_K24_P2_C2_am_G8192_entpad + benchmark spin_lock mcs_lock ${SNITCH_RUNTIME}) +target_compile_definitions(test-${SNITCH_TEST_PREFIX}multi_producer_single_consumer_double_linked_list_M32_N1350_K24_P2_C2_am_G8192_entpad PUBLIC + DATAHEADER="data/data_32_1350_24.h" + PRODUCER_CORE_NUM=2 CONSUMER_CORE_NUM=2 + RLC_TB_MODE=1 RLC_GRANT_BYTES=8192 RLC_SELF_CHECK=1 RLC_AM_ENT_PADDED=1) + +# Three-way layout discriminator at a FIXED entity count (16, which fails). +# padshift passes, entpad fails -> pure layout sensitivity (not the kernel) +# padshift fails, entpad passes -> false sharing on rlc_am_ent (kernel bug) +# both fail -> neither; look elsewhere +add_snitch_test(multi_producer_single_consumer_double_linked_list_M16_N1350_K24_P2_C2_am_G8192_pad0 + multi_producer_single_consumer_double_linked_list/main.c) +target_link_libraries(test-${SNITCH_TEST_PREFIX}multi_producer_single_consumer_double_linked_list_M16_N1350_K24_P2_C2_am_G8192_pad0 + benchmark spin_lock mcs_lock ${SNITCH_RUNTIME}) +target_compile_definitions(test-${SNITCH_TEST_PREFIX}multi_producer_single_consumer_double_linked_list_M16_N1350_K24_P2_C2_am_G8192_pad0 PUBLIC + DATAHEADER="data/data_16_1350_24.h" + PRODUCER_CORE_NUM=2 CONSUMER_CORE_NUM=2 + RLC_TB_MODE=1 RLC_GRANT_BYTES=8192 RLC_SELF_CHECK=1) + +add_snitch_test(multi_producer_single_consumer_double_linked_list_M16_N1350_K24_P2_C2_am_G8192_padshift + multi_producer_single_consumer_double_linked_list/main.c) +target_link_libraries(test-${SNITCH_TEST_PREFIX}multi_producer_single_consumer_double_linked_list_M16_N1350_K24_P2_C2_am_G8192_padshift + benchmark spin_lock mcs_lock ${SNITCH_RUNTIME}) +target_compile_definitions(test-${SNITCH_TEST_PREFIX}multi_producer_single_consumer_double_linked_list_M16_N1350_K24_P2_C2_am_G8192_padshift PUBLIC + DATAHEADER="data/data_16_1350_24.h" + PRODUCER_CORE_NUM=2 CONSUMER_CORE_NUM=2 + RLC_TB_MODE=1 RLC_GRANT_BYTES=8192 RLC_SELF_CHECK=1 RLC_LAYOUT_PAD=320) + +add_snitch_test(multi_producer_single_consumer_double_linked_list_M16_N1350_K24_P2_C2_am_G8192_entpad + multi_producer_single_consumer_double_linked_list/main.c) +target_link_libraries(test-${SNITCH_TEST_PREFIX}multi_producer_single_consumer_double_linked_list_M16_N1350_K24_P2_C2_am_G8192_entpad + benchmark spin_lock mcs_lock ${SNITCH_RUNTIME}) +target_compile_definitions(test-${SNITCH_TEST_PREFIX}multi_producer_single_consumer_double_linked_list_M16_N1350_K24_P2_C2_am_G8192_entpad PUBLIC + DATAHEADER="data/data_16_1350_24.h" + PRODUCER_CORE_NUM=2 CONSUMER_CORE_NUM=2 + RLC_TB_MODE=1 RLC_GRANT_BYTES=8192 RLC_SELF_CHECK=1 RLC_AM_ENT_PADDED=1) + +# Entity-count bracket: 8 / 12 / 16 / 24 / 32 / 48 entities, all at 24 packets +# and 4 cores. A sharp flip implies a structure crossing a size boundary; a +# gradual one implies accumulation. Those are different bugs. +add_snitch_test(multi_producer_single_consumer_double_linked_list_M12_N1350_K24_P2_C2_am_G8192_tbchk + multi_producer_single_consumer_double_linked_list/main.c) +target_link_libraries(test-${SNITCH_TEST_PREFIX}multi_producer_single_consumer_double_linked_list_M12_N1350_K24_P2_C2_am_G8192_tbchk + benchmark spin_lock mcs_lock ${SNITCH_RUNTIME}) +target_compile_definitions(test-${SNITCH_TEST_PREFIX}multi_producer_single_consumer_double_linked_list_M12_N1350_K24_P2_C2_am_G8192_tbchk PUBLIC + DATAHEADER="data/data_12_1350_24.h" + PRODUCER_CORE_NUM=2 CONSUMER_CORE_NUM=2 + RLC_TB_MODE=1 RLC_GRANT_BYTES=8192 RLC_SELF_CHECK=1) + +add_snitch_test(multi_producer_single_consumer_double_linked_list_M16_N1350_K24_P2_C2_am_G8192_tbchk + multi_producer_single_consumer_double_linked_list/main.c) +target_link_libraries(test-${SNITCH_TEST_PREFIX}multi_producer_single_consumer_double_linked_list_M16_N1350_K24_P2_C2_am_G8192_tbchk + benchmark spin_lock mcs_lock ${SNITCH_RUNTIME}) +target_compile_definitions(test-${SNITCH_TEST_PREFIX}multi_producer_single_consumer_double_linked_list_M16_N1350_K24_P2_C2_am_G8192_tbchk PUBLIC + DATAHEADER="data/data_16_1350_24.h" + PRODUCER_CORE_NUM=2 CONSUMER_CORE_NUM=2 + RLC_TB_MODE=1 RLC_GRANT_BYTES=8192 RLC_SELF_CHECK=1) + +add_snitch_test(multi_producer_single_consumer_double_linked_list_M24_N1350_K24_P2_C2_am_G8192_tbchk + multi_producer_single_consumer_double_linked_list/main.c) +target_link_libraries(test-${SNITCH_TEST_PREFIX}multi_producer_single_consumer_double_linked_list_M24_N1350_K24_P2_C2_am_G8192_tbchk + benchmark spin_lock mcs_lock ${SNITCH_RUNTIME}) +target_compile_definitions(test-${SNITCH_TEST_PREFIX}multi_producer_single_consumer_double_linked_list_M24_N1350_K24_P2_C2_am_G8192_tbchk PUBLIC + DATAHEADER="data/data_24_1350_24.h" + PRODUCER_CORE_NUM=2 CONSUMER_CORE_NUM=2 + RLC_TB_MODE=1 RLC_GRANT_BYTES=8192 RLC_SELF_CHECK=1) + +add_snitch_test(multi_producer_single_consumer_double_linked_list_M32_N1350_K24_P2_C2_am_G8192_tbchk + multi_producer_single_consumer_double_linked_list/main.c) +target_link_libraries(test-${SNITCH_TEST_PREFIX}multi_producer_single_consumer_double_linked_list_M32_N1350_K24_P2_C2_am_G8192_tbchk + benchmark spin_lock mcs_lock ${SNITCH_RUNTIME}) +target_compile_definitions(test-${SNITCH_TEST_PREFIX}multi_producer_single_consumer_double_linked_list_M32_N1350_K24_P2_C2_am_G8192_tbchk PUBLIC + DATAHEADER="data/data_32_1350_24.h" + PRODUCER_CORE_NUM=2 CONSUMER_CORE_NUM=2 + RLC_TB_MODE=1 RLC_GRANT_BYTES=8192 RLC_SELF_CHECK=1) + +# Scalar-copy control: identical in every respect except that the payload is +# moved with scalar byte stores instead of the e8/m8 vector copy. Isolates an +# alignment-sensitive vector copy from wrong offset arithmetic. +add_snitch_test(multi_producer_single_consumer_double_linked_list_M1_N1350_K100_P2_C2_am_G8192_scpy + multi_producer_single_consumer_double_linked_list/main.c) +target_link_libraries(test-${SNITCH_TEST_PREFIX}multi_producer_single_consumer_double_linked_list_M1_N1350_K100_P2_C2_am_G8192_scpy + benchmark spin_lock mcs_lock ${SNITCH_RUNTIME}) +target_compile_definitions(test-${SNITCH_TEST_PREFIX}multi_producer_single_consumer_double_linked_list_M1_N1350_K100_P2_C2_am_G8192_scpy PUBLIC + DATAHEADER="data/data_1_1350_100.h" + PRODUCER_CORE_NUM=2 CONSUMER_CORE_NUM=2 + RLC_TB_MODE=1 RLC_GRANT_BYTES=8192 RLC_SELF_CHECK=1 RLC_DL_COPY_SCALAR=1) + +# C=1 control. Dispatch follows the data header's core lists, so a genuine +# single-consumer run needs its own header (the *_CORE_NUM defines cannot +# shrink the list). Anything that reproduces here is not a concurrency bug. +add_snitch_test(multi_producer_single_consumer_double_linked_list_M1_N1350_K100_P1_C1_am_G8192 + multi_producer_single_consumer_double_linked_list/main.c) +target_link_libraries(test-${SNITCH_TEST_PREFIX}multi_producer_single_consumer_double_linked_list_M1_N1350_K100_P1_C1_am_G8192 + benchmark spin_lock mcs_lock ${SNITCH_RUNTIME}) +target_compile_definitions(test-${SNITCH_TEST_PREFIX}multi_producer_single_consumer_double_linked_list_M1_N1350_K100_P1_C1_am_G8192 PUBLIC + DATAHEADER="data/data_1_1350_100_p1c1.h" + PRODUCER_CORE_NUM=1 CONSUMER_CORE_NUM=1 + RLC_TB_MODE=1 RLC_GRANT_BYTES=8192 RLC_PLAN_VERIFY=1 RLC_SELF_CHECK=1) + +# Scalar-copy wedge ladder. RLC_DL_COPY_SCALAR=1 moves payload with 1-byte +# scalar stores instead of the e8/m8 vector copy. A 1-byte store cannot straddle +# a 64-byte cache line, so this build generates NO straddling payload writes -- +# which makes it a decisive discriminator against a platform that truncates +# straddling accesses rather than splitting them. If payload mismatches vanish +# here and persist in the vector build, the mismatches are the platform's, not +# the kernel's. +foreach(M 8 16 24 32) + add_snitch_test(multi_producer_single_consumer_double_linked_list_M${M}_N1350_K24_P2_C2_am_G8192_scpy + multi_producer_single_consumer_double_linked_list/main.c) + target_link_libraries(test-${SNITCH_TEST_PREFIX}multi_producer_single_consumer_double_linked_list_M${M}_N1350_K24_P2_C2_am_G8192_scpy + benchmark spin_lock mcs_lock ${SNITCH_RUNTIME}) + target_compile_definitions(test-${SNITCH_TEST_PREFIX}multi_producer_single_consumer_double_linked_list_M${M}_N1350_K24_P2_C2_am_G8192_scpy PUBLIC + DATAHEADER="data/data_${M}_1350_24.h" + PRODUCER_CORE_NUM=2 CONSUMER_CORE_NUM=2 + RLC_TB_MODE=1 RLC_GRANT_BYTES=8192 RLC_SELF_CHECK=1 RLC_DL_COPY_SCALAR=1) +endforeach() + +# --------------------------------------------------------------------------- +# Uplink (RLC_UL_MODE=1): receive -> scan -> reassemble -> deliver. +# +# The consumer set runs uplink slots instead of downlink assembly, so these are +# a separate ELF rather than a flag on the DL tests. The C1/C2/C3 ladder is the +# measurement that matters: the scan is serial by construction (an AMD header +# is 3 or 5 bytes depending on SI, so PDU i+1's offset needs PDU i parsed), +# reassembly is not, and the ratio bounds what more cores can buy. Consumers +# stay inside one tile because the TB arena is above the l1d_addr boundary and +# therefore tile-private. +# --------------------------------------------------------------------------- +macro(add_rlc_ul name source dataheader prod cons exec tc tb suffix) + add_snitch_test(${name}_P${prod}_C${cons}_ul_${suffix} ${source}) + target_link_libraries(test-${SNITCH_TEST_PREFIX}${name}_P${prod}_C${cons}_ul_${suffix} + benchmark spin_lock mcs_lock ${SNITCH_RUNTIME}) + target_compile_definitions(test-${SNITCH_TEST_PREFIX}${name}_P${prod}_C${cons}_ul_${suffix} PUBLIC + DATAHEADER="${dataheader}" + PRODUCER_CORE_NUM=${prod} CONSUMER_CORE_NUM=${cons} + RLC_UL_MODE=1 RLC_UL_EXEC=${exec} RLC_UL_TC=${tc} RLC_UL_TB_BYTES=${tb} + RLC_SELF_CHECK=1) +endmacro() + +# TC1 consumer ladder at the DOCUMENTED uplink profile: 160 B PDUs, 1 Gbps, +# 1600 slots/s -> 78,125 B and 488 SDUs per slot. Each 8 KB block carries ~49 +# PDUs and segments at the boundary, so the serial header walk is measured on +# traffic that actually contains 5-byte SO headers. +add_rlc_ul(multi_producer_single_consumer_double_linked_list + multi_producer_single_consumer_double_linked_list/main.c + "data/data_1_1350_100_p1c1.h" 1 1 0 1 8192 tc1_copy) +add_rlc_ul(multi_producer_single_consumer_double_linked_list + multi_producer_single_consumer_double_linked_list/main.c + "data/data_1_1350_100.h" 2 2 0 1 8192 tc1_copy) +add_rlc_ul(multi_producer_single_consumer_double_linked_list + multi_producer_single_consumer_double_linked_list/main.c + "data/data_1_1350_100_p1c3.h" 1 3 0 1 8192 tc1_copy) + +# Header-only control: payload accounted for but never read, which is what a +# receiver handing payload to a DMA does. Isolates header-walk cost. +add_rlc_ul(multi_producer_single_consumer_double_linked_list + multi_producer_single_consumer_double_linked_list/main.c + "data/data_1_1350_100_p1c3.h" 1 3 1 1 8192 tc1_count) + +# Smaller block: more block boundaries per byte, so proportionally more +# segmentation. Separates per-block cost from per-PDU cost. +add_rlc_ul(multi_producer_single_consumer_double_linked_list + multi_producer_single_consumer_double_linked_list/main.c + "data/data_1_1350_100_p1c3.h" 1 3 0 1 2048 tc1_smallblk) + +# Same cases with the bitmap work queue (RLC_AM_WORKQ=1), so the scan-free path +# can be diffed against the plain one rather than replacing it. +add_spatz_test_rlc_am_wq(multi_producer_single_consumer_double_linked_list multi_producer_single_consumer_double_linked_list/main.c 1 1350 100 2 4 8192 1) +add_spatz_test_rlc_am_wq(multi_producer_single_consumer_double_linked_list multi_producer_single_consumer_double_linked_list/main.c 48 800 300 2 2 8192 1) +add_spatz_test_rlc_am_wq(multi_producer_single_consumer_double_linked_list multi_producer_single_consumer_double_linked_list/main.c 48 800 300 4 8 8192 0) +# Large-config thread-scaling (GVSoC 64/256-core sweeps): all-cores-work variants. +# P16/C48 = 64 active (16x4); P48/C48 = 96 active (M48 ceiling); M256 P128/C128 = 256 active (64x4). +add_spatz_test_rlc(multi_producer_single_consumer_double_linked_list multi_producer_single_consumer_double_linked_list/main.c 48 800 300 16 48) +add_spatz_test_rlc(multi_producer_single_consumer_double_linked_list multi_producer_single_consumer_double_linked_list/main.c 48 800 300 48 48) +add_spatz_test_rlc(multi_producer_single_consumer_double_linked_list multi_producer_single_consumer_double_linked_list/main.c 256 800 300 128 128) +# TC2 with the payload self-check enabled (src vs tgt compare after the barrier) +add_snitch_test(multi_producer_single_consumer_double_linked_list_M48_N800_K300_sc multi_producer_single_consumer_double_linked_list/main.c) +target_link_libraries(test-${SNITCH_TEST_PREFIX}multi_producer_single_consumer_double_linked_list_M48_N800_K300_sc benchmark spin_lock mcs_lock ${SNITCH_RUNTIME}) +target_compile_definitions(test-${SNITCH_TEST_PREFIX}multi_producer_single_consumer_double_linked_list_M48_N800_K300_sc PUBLIC DATAHEADER="data/data_48_800_300.h" RLC_SELF_CHECK=1) diff --git a/software/tests/multi_producer_single_consumer_double_linked_list/test/test_rlc_plan.c b/software/rlc/multi_producer_single_consumer_double_linked_list/test/test_rlc_plan.c similarity index 100% rename from software/tests/multi_producer_single_consumer_double_linked_list/test/test_rlc_plan.c rename to software/rlc/multi_producer_single_consumer_double_linked_list/test/test_rlc_plan.c diff --git a/software/tests/multi_producer_single_consumer_double_linked_list/test/test_rlc_ul.c b/software/rlc/multi_producer_single_consumer_double_linked_list/test/test_rlc_ul.c similarity index 100% rename from software/tests/multi_producer_single_consumer_double_linked_list/test/test_rlc_ul.c rename to software/rlc/multi_producer_single_consumer_double_linked_list/test/test_rlc_ul.c From 4fa0e64de08f81a8589b98155d43924895cca9fc Mon Sep 17 00:00:00 2001 From: Zexin Fu Date: Wed, 14 Oct 2026 23:33:07 +0200 Subject: [PATCH 42/48] rlc: run the consumer phase barrier on its own barrier slot Main replaced the tile participation mask with per-slot barriers, so snrt_barrier_set_tile_mask is gone. Use snrt_cluster_group_barrier on a dedicated slot and drop the narrow/restore region and the non-participant spin it needed. --- software/rlc/CMakeLists.txt | 2 +- .../kernel/rlc.c | 52 ++---- .../kernel/rlc_am.c | 42 +---- .../kernel/rlc_sync.h | 154 +++++++----------- .../kernel/rlc_ul_drv.c | 48 ++---- .../kernel/rlc_ul_drv.h | 5 +- .../main.c | 2 + 7 files changed, 101 insertions(+), 204 deletions(-) diff --git a/software/rlc/CMakeLists.txt b/software/rlc/CMakeLists.txt index cad7d82..b3ba532 100644 --- a/software/rlc/CMakeLists.txt +++ b/software/rlc/CMakeLists.txt @@ -514,7 +514,7 @@ macro(add_rlc_ul name source dataheader prod cons exec tc tb suffix) endmacro() # TC1 consumer ladder at the DOCUMENTED uplink profile: 160 B PDUs, 1 Gbps, -# 1600 slots/s -> 78,125 B and 488 SDUs per slot. Each 8 KB block carries ~49 +# 400 slots/s -> 312,500 B and 1953 SDUs per slot. Each 8 KB block carries ~49 # PDUs and segments at the boundary, so the serial header walk is measured on # traffic that actually contains 5-byte SO headers. add_rlc_ul(multi_producer_single_consumer_double_linked_list diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.c b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.c index 0ad1526..b31c665 100644 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.c +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.c @@ -32,13 +32,12 @@ #include "rlc_ul_drv.h" /* rlc_ul_init() must be reachable from rlc_init() below */ #endif -/* Set when this build narrows the cluster barrier mask for a consumer-only - partial-barrier region, which requires non-participants to stay out of any - barrier for the duration. */ +/* Set when the consumers synchronise their TTI phases with a consumer-only + hardware barrier (see rlc_sync.h). */ #if (RLC_UL_MODE) || ((RLC_TB_MODE == RLC_TB_MODE_AM) && RLC_AM_TTI && !RLC_TILE_AFFINITY) -#define RLC_NARROWED_BARRIER 1 +#define RLC_CONSUMER_BARRIER 1 #else -#define RLC_NARROWED_BARRIER 0 +#define RLC_CONSUMER_BARRIER 0 #endif #include "mm.h" #include "llist.c" @@ -197,10 +196,8 @@ void rlc_init(const unsigned int rlcId, const unsigned int cellId, mm_context_t rlc_am_init(rlcId); #endif #if RLC_UL_MODE - /* Uplink init must happen HERE, not lazily on entry to the consumer: it - programmes the cluster tile participation mask, and main.c's startup - snrt_cluster_hw_barrier() right after this is the resync point the - partial-barrier API requires before that mask can be relied on. */ + /* Uplink state is set up here, by core 0 before main.c's startup + barrier, so no consumer can enter a slot before it exists. */ if (rlcId == 0u) rlc_ul_init(); #endif } @@ -349,24 +346,19 @@ static inline unsigned int rlc_consumer_index(const unsigned int core_id) { #define RLC_ACTUAL_CONSUMERS CONSUMER_CORE_NUM #endif -/* Cluster tile-participation mask for the consumer set: one bit per tile. - Used to arm the narrowed-barrier region -- see rlc_sync.h for why this is - done on entry to the consumer loop rather than at init. Needs the explicit - core lists, which is also where the barrier participant set comes from. */ -#if RLC_NARROWED_BARRIER +/* The consumer barrier's participant set comes from consumer_core_ids. Core 0 + calls rlc_barrier_init() before the startup barrier; see rlc_sync.h. */ +#if RLC_CONSUMER_BARRIER #if !RLC_CORE_LISTS -#error "a narrowed barrier needs RLC_CORE_LISTS: the participant set comes from consumer_core_ids" +#error "the consumer barrier needs RLC_CORE_LISTS: the participant set comes from consumer_core_ids" #endif -static inline void rlc_consumer_tile_mask(uint32_t *lo, uint32_t *hi) { - const uint32_t cpt = snrt_cluster_core_per_tile(); - uint32_t l = 0u, h = 0u; - for (uint32_t i = 0u; i < RLC_ACTUAL_CONSUMERS; i++) { - const uint32_t t = (uint32_t)consumer_core_ids[i] / cpt; - if (t < 32u) l |= 1u << t; else h |= 1u << (t - 32u); - } - *lo = l; *hi = h; +#include "rlc_sync.h" +static inline void rlc_barrier_init(void) { + rlc_bar_init(consumer_core_ids, RLC_ACTUAL_CONSUMERS); } -#endif /* RLC_NARROWED_BARRIER */ +#else +static inline void rlc_barrier_init(void) { } +#endif /* RLC_CONSUMER_BARRIER */ /* The core that runs the UE status task: the first producer, whichever it is. */ static inline unsigned int rlc_status_core(void) { @@ -1230,18 +1222,6 @@ void cluster_entry(const unsigned int core_id) { consumer(core_id); } /* else: idle core for this run, falls through to the barrier */ -#if RLC_NARROWED_BARRIER - /* Cores that are not consumers must NOT be sitting at a barrier while the - consumers hold the mask narrowed. Two hardware properties force this: - whichever request arrives first owns a tile's round, and barrier_done is - an unmasked cluster-wide broadcast. So they wait here, outside any - barrier, until the mask has been restored. See rlc_sync.h. */ -#if RLC_PROBE - if (!is_consumer) perf_probe_phase(PERF_PROBE_PHASE_DONE); -#endif - if (!is_consumer) rlc_narrow_wait_outside(); -#endif - #if RLC_PROBE if (is_producer || is_consumer) perf_probe_phase(PERF_PROBE_PHASE_BARRIER); #endif diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.c b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.c index c4488ee..5ffa652 100644 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.c +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.c @@ -185,11 +185,6 @@ void rlc_am_init(uint32_t u) { rlc_am_open_entity[k] = RLC_AM_NO_ENTITY; #if RLC_AM_TTI - /* The tile mask is NOT programmed here any more. Doing it at init put the - narrowing in force before main.c's startup snrt_cluster_hw_barrier(), - which the cluster mask then gates -- so that barrier stopped waiting for - anyone outside the consumer tiles. It is armed on entry to the consumer - loop instead, and restored on exit. See rlc_sync.h. */ { for (uint32_t k = 0u; k < RLC_AM_MAX_TRACKED_CONSUMERS; k++) rlc_am_rr[k] = 0u; atomic_store_explicit(&rlc_am_stop, 0u, memory_order_relaxed); @@ -796,26 +791,9 @@ void rlc_am_consumer_tti(uint32_t core_id) { const uint32_t me = rlc_consumer_index(core_id); rlc_am_my_open = RLC_AM_NO_ENTITY; rlc_am_my_rr = 0u; - /* Tile-local participant mask. O(n), computed once on entry, never in the - loop. Every consumer in a tile derives the same value independently. */ - const uint32_t mask = - snrt_cluster_partial_barrier_mask(consumer_core_ids, RLC_ACTUAL_CONSUMERS); - - /* Arm the narrowed region here, not at init. Consumer 0 programs the mask; - the others wait on a flag rather than on the barrier they are about to - narrow, which is the resync the API documents and which cannot work. */ - { - uint32_t tm_lo, tm_hi; - rlc_consumer_tile_mask(&tm_lo, &tm_hi); - rlc_narrow_enter(tm_lo, tm_hi, me == 0u); - if (me == 0u && !rlc_narrow_ok(tm_lo)) { - printf_lock_acquire(&printf_lock); - printf("[AM] MASK CHECK FAILED: probe=0x%x readback=0x%x wrote=0x%x -- " - "the participation register is not where we wrote it; check the " - "peripheral map\n", rlc_narrow_probe, rlc_narrow_readback, tm_lo); - printf_lock_release(&printf_lock); - } - } + /* Barrier descriptor. O(n), computed once on entry, never in the loop. + Every consumer derives its own tile's value independently. */ + const rlc_bar_t bar = rlc_bar_describe(consumer_core_ids, RLC_ACTUAL_CONSUMERS); while (1) { #if RLC_TTI_CYCLES @@ -825,17 +803,17 @@ void rlc_am_consumer_tti(uint32_t core_id) { perf_probe_phase(PERF_PROBE_PHASE_PLAN); rlc_am_plan_phase(me); perf_probe_phase(PERF_PROBE_PHASE_BARRIER); - rlc_phase_barrier(mask); /* helpers BLOCK here; fenced -- see rlc_sync.h */ + rlc_phase_barrier(&bar); /* helpers BLOCK here; fenced -- see rlc_sync.h */ perf_probe_phase(PERF_PROBE_PHASE_EXECUTE); rlc_am_execute_phase(); perf_probe_phase(PERF_PROBE_PHASE_BARRIER); - rlc_phase_barrier(mask); + rlc_phase_barrier(&bar); perf_probe_phase(PERF_PROBE_PHASE_COMMIT); rlc_am_commit_phase(me); perf_probe_phase(PERF_PROBE_PHASE_BARRIER); - rlc_phase_barrier(mask); + rlc_phase_barrier(&bar); if (me == 0u) { perf_probe(PROBE_EVT_TTI_END, rlc_am_ttis); @@ -845,7 +823,7 @@ void rlc_am_consumer_tti(uint32_t core_id) { PRODUCER_CORE_NUM && rlc_am_idle()) ? 1u : 0u, memory_order_release); } - rlc_phase_barrier(mask); + rlc_phase_barrier(&bar); if (atomic_load_explicit(&rlc_am_stop, memory_order_acquire)) break; #if RLC_TTI_CYCLES @@ -855,12 +833,6 @@ void rlc_am_consumer_tti(uint32_t core_id) { } #endif } - - /* All consumers are past the last partial barrier here -- they exit on the - same iteration, having read rlc_am_stop after a common barrier. Restore - the mask before anyone reaches a full barrier again, then release the - non-participants spinning outside it. */ - rlc_narrow_exit(me == 0u); } #endif /* RLC_AM_TTI */ diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_sync.h b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_sync.h index bf41225..eede067 100644 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_sync.h +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_sync.h @@ -18,12 +18,10 @@ /* Phase barrier for the RLC TTI loops, downlink and uplink. - **snrt_cluster_partial_barrier() synchronises execution, not memory.** Its - whole implementation is one plain store to the barrier register: + **A hardware barrier synchronises execution, not memory.** A partial + barrier is one plain store to the barrier register: - void snrt_cluster_partial_barrier(uint32_t local_mask) { - *(volatile uint32_t *)_snrt_barrier_reg_ptr() = local_mask; - } + *(volatile uint32_t *)_snrt_barrier_reg_ptr() = payload; It makes the participating cores wait for one another, and that is all. It issues no fence, so a write made before it is not guaranteed visible to @@ -52,105 +50,79 @@ #include #include - -static inline void rlc_phase_barrier(uint32_t local_mask) { - asm volatile("fence" ::: "memory"); /* publish this phase's writes */ - snrt_cluster_partial_barrier(local_mask); - asm volatile("fence" ::: "memory"); /* observe the other cores' writes */ -} +#include "cachepool_peripheral.h" /* ------------------------------------------------------------------------ */ -/* Narrowed-barrier region */ +/* Consumer-only barrier on its own hardware slot */ /* ------------------------------------------------------------------------ */ -/* Using a partial barrier safely takes more than programming the mask. Three - properties of the hardware constrain it -- see - reports/design_notes/PARTIAL_BARRIER_MISUSE.md: - - 1. The cluster tile mask is PERSISTENT and gates every round, full barriers - included: `mask_d = barrier_mask_i` is re-read at each round start and - there is no full-vs-partial distinction at the cluster level. So a mask - left narrowed breaks every later snrt_cluster_hw_barrier(). - - 2. At tile level, WHICHEVER REQUEST ARRIVES FIRST owns the round -- - `core_mask_d = req_mask[first_hit_idx]`, where a read means "all cores" - and a write means "this mask". Mixing the two inside one tile races, and - the two directions give opposite symptoms: a partial barrier absorbed - into an all-cores round hangs, a full barrier absorbed into a - participants-only round releases early. - - 3. `barrier_done_o` is a SINGLE UNMASKED BROADCAST. The mask gates who must - arrive, not who is released, so any partial-barrier completion frees - every core waiting at a barrier anywhere in the cluster. This is why - non-participants cannot simply be moved to another tile, and why they - have to stay out of the barrier entirely rather than wait in one. - - Hence: arm here rather than at init (arming before main's startup barrier - would break that barrier), publish it with a flag rather than a barrier - (the participants cannot resync on the barrier they are narrowing), keep - non-participants spinning outside, and restore the mask before anyone - reaches a full barrier again. */ - -#define RLC_MASK_RESVAL 0xFFFFFFFFu +/* The phase barrier runs on a dedicated barrier slot. Slot 0 belongs to the + full-cluster barrier (snrt_cluster_hw_barrier) and, on dual-scalar builds, + slot 1 to the host barriers; every slot has its own tile/group/cluster + round tracker and its own release, so the consumers' rounds never mix with + the full barrier the other cores are waiting in. Non-participants therefore + simply proceed to snrt_cluster_hw_barrier(). */ +#if SNRT_HOST_BARRIER_SLOT == 1 +#define RLC_BARRIER_SLOT 2u +#else +#define RLC_BARRIER_SLOT 1u +#endif -static _Atomic uint32_t rlc_narrow_armed; /* mask programmed; partials legal */ -static _Atomic uint32_t rlc_narrow_done; /* region over; mask restored */ -static uint32_t rlc_narrow_probe; /* pre-write read of the register */ -static uint32_t rlc_narrow_readback; /* post-write read */ +#if RLC_BARRIER_SLOT >= CACHEPOOL_PERIPHERAL_PARAM_NUM_BARRIER_SLOTS +#error "RLC phase barrier needs a free barrier slot: raise NumBarrierSlots" +#endif -/* Bounded pause between polls. Only cores with no work spin -- participants - still block on a real barrier -- but idle cores polling a shared line at - full rate is pointless memory traffic. */ -static inline void rlc_narrow_pause(void) { - for (volatile int i = 0; i < 64; i++) { } -} +/* Everything one barrier round needs; identical on every core of a tile, and + the tile mask identical on every tile of a group, which is what the + tile/group trackers latch and compare. */ +typedef struct { + uint32_t core_mask; /* participants in my tile */ + uint32_t tile_mask; /* participating tiles of my group (group-relative) */ + uint32_t local_only; /* 1: the round resolves without the cluster level */ + uint32_t group_mask; /* participating groups (cluster-level, per slot) */ +} rlc_bar_t; -/* Enter the narrowed region. `first` must be true on exactly one participant. - Returns nothing; rlc_narrow_ok() reports whether the register agreed. */ -static inline void rlc_narrow_enter(uint32_t tm_lo, uint32_t tm_hi, int first) { - if (first) { - volatile uint32_t *reg = - (volatile uint32_t *)_snrt_barrier_participation_mask_reg_ptr(); - /* Pre-write probe: the mask register resets to RESVAL 0xFFFFFFFF, while - everything else that could sit at this offset under a wrong peripheral - map resets to 0. Read-back alone cannot tell them apart -- any RW - scratch accepts a write and returns it. */ - rlc_narrow_probe = reg[0]; - snrt_barrier_set_tile_mask(tm_lo, tm_hi); - asm volatile("fence" ::: "memory"); - rlc_narrow_readback = reg[0]; - atomic_store_explicit(&rlc_narrow_armed, 1u, memory_order_release); - asm volatile("fence" ::: "memory"); - } else { - while (!atomic_load_explicit(&rlc_narrow_armed, memory_order_acquire)) - rlc_narrow_pause(); - asm volatile("fence" ::: "memory"); +/* Derive the descriptor for the calling core from the participant list. */ +static inline rlc_bar_t rlc_bar_describe(const unsigned int *cids, uint32_t n) { + const uint32_t cpt = snrt_cluster_core_per_tile(); + const uint32_t ngrp = snrt_cluster_group_num(); + const uint32_t tpg = snrt_cluster_tile_num() / ngrp; + const uint32_t my_tile = snrt_cluster_tile_idx(); + const uint32_t my_grp = my_tile / tpg; + rlc_bar_t b = {0u, 0u, 1u, 0u}; + for (uint32_t i = 0u; i < n; i++) { + const uint32_t t = cids[i] / cpt; + const uint32_t g = t / tpg; + b.group_mask |= 1u << g; + if (g == my_grp) b.tile_mask |= 1u << (t % tpg); + if (t == my_tile) b.core_mask |= 1u << (cids[i] % cpt); } -} - -/* Leave the narrowed region: restore the mask, then release the cores waiting - outside. Order matters -- a non-participant released before the restore - would enter a still-narrowed barrier. */ -static inline void rlc_narrow_exit(int first) { - if (first) { - snrt_barrier_set_tile_mask(RLC_MASK_RESVAL, RLC_MASK_RESVAL); - asm volatile("fence" ::: "memory"); - atomic_store_explicit(&rlc_narrow_done, 1u, memory_order_release); - asm volatile("fence" ::: "memory"); + if (b.group_mask & (b.group_mask - 1u)) { + b.local_only = 0u; /* several groups: via the cluster */ + } else if (b.tile_mask == (1u << (my_tile % tpg))) { + b.tile_mask = SNRT_BARRIER_TILE_MASK_SELF; /* one tile: never leaves it */ } + return b; } -/* Non-participants: wait OUTSIDE any barrier until the region is over. */ -static inline void rlc_narrow_wait_outside(void) { - while (!atomic_load_explicit(&rlc_narrow_done, memory_order_acquire)) - rlc_narrow_pause(); - asm volatile("fence" ::: "memory"); +/* Called once, by one core, before the startup snrt_cluster_hw_barrier(), + which is the resync point the API asks for. Programming slot RLC_BARRIER_SLOT + cannot disturb that barrier: it runs on slot 0. Only needed when the round + crosses groups and not every group takes part (the register resets to all + groups). */ +static inline void rlc_bar_init(const unsigned int *cids, uint32_t n) { + const rlc_bar_t b = rlc_bar_describe(cids, n); + const uint32_t ngrp = snrt_cluster_group_num(); + const uint32_t all = (ngrp >= 32u) ? 0xffffffffu : ((1u << ngrp) - 1u); + if (!b.local_only && b.group_mask != all) + snrt_barrier_set_group_mask(RLC_BARRIER_SLOT, b.group_mask); } -/* True when the participation-mask register behaved like the mask register: - reset signature seen before the write, and the write read back. */ -static inline int rlc_narrow_ok(uint32_t tm_lo) { - return (rlc_narrow_probe == RLC_MASK_RESVAL) && (rlc_narrow_readback == tm_lo); +static inline void rlc_phase_barrier(const rlc_bar_t *b) { + asm volatile("fence" ::: "memory"); /* publish this phase's writes */ + snrt_cluster_group_barrier(b->core_mask, b->tile_mask, (int)b->local_only, + RLC_BARRIER_SLOT); + asm volatile("fence" ::: "memory"); /* observe the other cores' writes */ } #endif /* RLC_SYNC_H */ diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_ul_drv.c b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_ul_drv.c index 8d37a28..020c985 100644 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_ul_drv.c +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_ul_drv.c @@ -137,15 +137,7 @@ static rlc_ul_cyc_t rlc_ul_cyc_reasm[RLC_ACTUAL_CONSUMERS] __attribute__((aligned(CACHE_LINE_SIZE))) __attribute__((section(".data"))); static uint32_t rlc_ul_cyc_build, rlc_ul_cyc_scan, rlc_ul_cyc_deliver; -/* The arm/restore state for the narrowed-barrier region lives in rlc_sync.h, - shared with the downlink -- both directions face the same constraint. */ - void rlc_ul_init(void) { - /* The tile mask is NOT programmed here. Arming before main.c's startup - snrt_cluster_hw_barrier() narrows that barrier too -- the cluster mask is - persistent and gates every round, full barriers included -- so it is armed - on entry to the consumer loop instead and restored on exit. See - rlc_sync.h for the three hardware properties that force this shape. */ atomic_store_explicit(&rlc_ul_stop, 0u, memory_order_relaxed); for (uint32_t u = 0u; u < NUM_USERS; u++) rlc_ul_entity_init(&rlc_ul_ent[u]); rlc_ul_cur_sdu = 0u; @@ -218,7 +210,7 @@ static int rlc_ul_done(void) { return rlc_ul_cur_sdu >= RLC_UL_SDUS; } single stream, which is what the scan-versus-reassemble split is measured on. Multi-entity uplink reuses these phases under the ownership map the downlink already has. */ -static void rlc_ul_slot(uint32_t me, uint32_t bar_mask) { +static void rlc_ul_slot(uint32_t me, const rlc_bar_t *bar) { uint8_t *tb = (uint8_t *)(uintptr_t)RLC_UL_TB_BASE; /* --- phase 1: build + scan (serial by construction) --- */ @@ -234,7 +226,7 @@ static void rlc_ul_slot(uint32_t me, uint32_t bar_mask) { rlc_ul_cyc_scan += t2 - t1; rlc_ul_slots++; } - rlc_phase_barrier(bar_mask); + rlc_phase_barrier(bar); /* --- phase 2: reassemble (parallel, disjoint slices) --- */ { @@ -250,7 +242,7 @@ static void rlc_ul_slot(uint32_t me, uint32_t bar_mask) { } rlc_ul_cyc_reasm[me].cyc += benchmark_get_cycle() - t0; } - rlc_phase_barrier(bar_mask); + rlc_phase_barrier(bar); /* --- phase 3: deliver in order + STATUS (serial by definition) --- */ if (me == 0u) { @@ -266,21 +258,16 @@ static void rlc_ul_slot(uint32_t me, uint32_t bar_mask) { if (rlc_ul_done() && rlc_ul_scan_buf.n == 0u) atomic_store_explicit(&rlc_ul_stop, 1u, memory_order_relaxed); } - rlc_phase_barrier(bar_mask); + rlc_phase_barrier(bar); } -static void rlc_ul_report(uint32_t tm_lo) { +static void rlc_ul_report(const rlc_bar_t *bar) { const rlc_ul_entity_t *e = &rlc_ul_ent[0]; const uint32_t want = (uint32_t)RLC_UL_SDUS * RLC_UL_SDU_BYTES; printf_lock_acquire(&printf_lock); - printf("[UL] barrier probe=0x%x wrote=0x%x readback=0x%x local_mask=0x%x %s\n", - rlc_narrow_probe, tm_lo, rlc_narrow_readback, - snrt_cluster_partial_barrier_mask(consumer_core_ids, - RLC_ACTUAL_CONSUMERS), - rlc_narrow_ok(tm_lo) - ? "MASK-OK" - : "*** MASK CHECK FAILED: probe should read RESVAL 0xffffffff and " - "readback should equal wrote -- check the peripheral map ***"); + printf("[UL] barrier slot=%u core_mask=0x%x tile_mask=0x%x local_only=%u " + "group_mask=0x%x\n", RLC_BARRIER_SLOT, bar->core_mask, bar->tile_mask, + bar->local_only, bar->group_mask); printf("[UL] check: %s\n", (e->delivered == RLC_UL_SDUS && e->out_of_window == 0u && e->delivered_bytes == want) @@ -294,25 +281,12 @@ static void rlc_ul_report(uint32_t tm_lo) { barrier, so rlc_init() needs no uplink hook. */ void rlc_ul_consumer(uint32_t core_id) { const uint32_t me = rlc_consumer_index(core_id); - const uint32_t mask = - snrt_cluster_partial_barrier_mask(consumer_core_ids, RLC_ACTUAL_CONSUMERS); - uint32_t tm_lo, tm_hi; - rlc_consumer_tile_mask(&tm_lo, &tm_hi); - - /* Arm the narrowed region here rather than in rlc_init(): the cluster mask - gates every barrier round, so narrowing before main.c's startup barrier - breaks that barrier. Consumer 0 programs it; the others wait on a flag, - because they cannot resync on the barrier being narrowed. */ - rlc_narrow_enter(tm_lo, tm_hi, me == 0u); + const rlc_bar_t bar = rlc_bar_describe(consumer_core_ids, RLC_ACTUAL_CONSUMERS); while (!atomic_load_explicit(&rlc_ul_stop, memory_order_relaxed)) - rlc_ul_slot(me, mask); - - /* Restore before anyone reaches a full barrier again, and only then release - the non-participants spinning outside it. */ - rlc_narrow_exit(me == 0u); + rlc_ul_slot(me, &bar); - if (me == 0u) rlc_ul_report(tm_lo); + if (me == 0u) rlc_ul_report(&bar); } #endif /* RLC_UL_DRV_C */ diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_ul_drv.h b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_ul_drv.h index ceade3e..07de7d5 100644 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_ul_drv.h +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_ul_drv.h @@ -26,10 +26,7 @@ #include /* MUST be called from exactly one core, from rlc_init(), i.e. BEFORE main.c's - startup snrt_cluster_hw_barrier(). It programs the cluster tile - participation mask, and that barrier is the resync point the partial-barrier - API requires before the mask can be relied on. Doing it later -- lazily on - entry to rlc_ul_consumer() -- leaves the phase barriers unprogrammed. */ + startup snrt_cluster_hw_barrier(), which publishes the state it sets up. */ void rlc_ul_init(void); /* Uplink consumer entry point: receive/reassemble/deliver slots. */ diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/main.c b/software/rlc/multi_producer_single_consumer_double_linked_list/main.c index 0ca0f19..5cfbe3b 100644 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/main.c +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/main.c @@ -91,6 +91,8 @@ int main(void) { } #endif + rlc_barrier_init(); + #if RLC_GROUP_STREAMS /* Last, right before the start barrier: it also starts the paced-arrival clock. */ rlc_streams_init(); From bd534ef4511086cfd1ef40f9297dafa582030ad7 Mon Sep 17 00:00:00 2001 From: Zexin Fu Date: Thu, 15 Oct 2026 21:47:13 +0200 Subject: [PATCH 43/48] bootrom: use the IIS GCC 9.5.0 wrapper when available Fall back to the repo toolchain otherwise; override with BOOTROM_GCC_PREFIX. --- Makefile | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/Makefile b/Makefile index 2f588f7..def098f 100644 --- a/Makefile +++ b/Makefile @@ -160,9 +160,18 @@ SNRT_BOOTINFO_H := $(SOFTWARE_DIR)/snRuntime/include/snrt_bootinfo.h $(SNRT_BOOTINFO_H): $(SCRIPTS_DIR)/generate_bootdata.py $(HJSON_OUT) $(BOOTROM_DIR)/snrt_bootinfo.h.tpl ${PYTHON} $< -c $(HJSON_OUT) -d $(BOOTROM_DIR) -t snrt_bootinfo.h.tpl -o $@ +# BootROM compiler: the IIS GCC 9.5.0 wrapper when available, otherwise the repo toolchain. +# Override with BOOTROM_GCC_PREFIX=/riscv32-unknown-elf- +BOOTROM_GCC_9_5 := riscv -riscv64-gcc-9.5.0 riscv64-unknown-elf- +ifeq ($(shell $(BOOTROM_GCC_9_5)gcc --version >/dev/null 2>&1 && echo ok),ok) + BOOTROM_GCC_PREFIX ?= $(BOOTROM_GCC_9_5) +else + BOOTROM_GCC_PREFIX ?= $(GCC_INSTALL_DIR)/bin/riscv32-unknown-elf- +endif + $(BOOTROM_DIR)/bootrom.elf $(BOOTROM_DIR)/bootrom.dump $(BOOTROM_DIR)/bootrom.bin: \ $(BOOTROM_DIR)/bootrom.S $(BOOTROM_DIR)/bootdata_bootrom.cc $(BOOTROM_DIR)/bootrom.ld $(SNRT_BOOTINFO_H) - $(GCC_INSTALL_DIR)/bin/riscv32-unknown-elf-gcc \ + $(BOOTROM_GCC_PREFIX)gcc \ -mabi=ilp32 -march=rv32imaf -static -nostartfiles \ -T$(BOOTROM_DIR)/bootrom.ld \ $(BOOTROM_DIR)/bootrom.S \ @@ -170,8 +179,8 @@ $(BOOTROM_DIR)/bootrom.elf $(BOOTROM_DIR)/bootrom.dump $(BOOTROM_DIR)/bootrom.bi -I$(SPATZ_DIR)/hw/ip/snitch_test/src \ -I$(SOFTWARE_DIR)/snRuntime/include \ -o $(BOOTROM_DIR)/bootrom.elf - $(GCC_INSTALL_DIR)/bin/riscv32-unknown-elf-objdump -D $(BOOTROM_DIR)/bootrom.elf > $(BOOTROM_DIR)/bootrom.dump - $(GCC_INSTALL_DIR)/bin/riscv32-unknown-elf-objcopy -O binary $(BOOTROM_DIR)/bootrom.elf $(BOOTROM_DIR)/bootrom.bin + $(BOOTROM_GCC_PREFIX)objdump -D $(BOOTROM_DIR)/bootrom.elf > $(BOOTROM_DIR)/bootrom.dump + $(BOOTROM_GCC_PREFIX)objcopy -O binary $(BOOTROM_DIR)/bootrom.elf $(BOOTROM_DIR)/bootrom.bin $(BOOTROM_DIR)/bootrom.sv: $(BOOTROM_DIR)/bootrom.bin $(BOOTROM_DIR)/bootdata.cc ${PYTHON} $(SCRIPTS_DIR)/generate_bootrom.py \ From 58b053e17962fc3734b0b68e78fad7175b832fe4 Mon Sep 17 00:00:00 2001 From: Zexin Fu Date: Thu, 15 Oct 2026 23:10:34 +0200 Subject: [PATCH 44/48] Drop local report files from the repo and condense a tile comment Fixes the lint-license, rtl-style and repo-files checks. --- hardware/src/cachepool_tile.sv | 9 +- .../design_notes/PARTIAL_BARRIER_MISUSE.md | 202 ------------------ .../PROVENANCE_THE_TOOL_NOT_THE_CONFIG.md | 193 ----------------- .../SYNCHRONISATION_IS_NOT_VISIBILITY.md | 83 ------- reports/history_rewrite_2026-09-30.map | 39 ---- reports/rtl_reference_2026-09-08/RESULTS.md | 160 -------------- reports/rtl_reference_2026-09-08/RTL_STATE.md | 53 ----- .../rtl_reference_2026-09-08/build_report.sh | 41 ---- .../dut_tripwire.sha256 | 31 --- .../rtl_reference_2026-09-08/dut_watch.log | 132 ------------ .../elf_under_test/MANIFEST.md5 | 5 - reports/rtl_reference_2026-09-08/summary.tsv | 6 - .../rtl_reference_2026-09-08/verify_dut.sh | 14 -- .../PINNED_STATE.md | 21 -- .../dut_tripwire.sha256 | 31 --- 15 files changed, 3 insertions(+), 1017 deletions(-) delete mode 100644 reports/design_notes/PARTIAL_BARRIER_MISUSE.md delete mode 100644 reports/design_notes/PROVENANCE_THE_TOOL_NOT_THE_CONFIG.md delete mode 100644 reports/design_notes/SYNCHRONISATION_IS_NOT_VISIBILITY.md delete mode 100644 reports/history_rewrite_2026-09-30.map delete mode 100644 reports/rtl_reference_2026-09-08/RESULTS.md delete mode 100644 reports/rtl_reference_2026-09-08/RTL_STATE.md delete mode 100755 reports/rtl_reference_2026-09-08/build_report.sh delete mode 100644 reports/rtl_reference_2026-09-08/dut_tripwire.sha256 delete mode 100644 reports/rtl_reference_2026-09-08/dut_watch.log delete mode 100644 reports/rtl_reference_2026-09-08/elf_under_test/MANIFEST.md5 delete mode 100644 reports/rtl_reference_2026-09-08/summary.tsv delete mode 100755 reports/rtl_reference_2026-09-08/verify_dut.sh delete mode 100644 reports/rtl_reference_t312_pending/PINNED_STATE.md delete mode 100644 reports/rtl_reference_t312_pending/dut_tripwire.sha256 diff --git a/hardware/src/cachepool_tile.sv b/hardware/src/cachepool_tile.sv index 8658ffa..e8ee825 100644 --- a/hardware/src/cachepool_tile.sv +++ b/hardware/src/cachepool_tile.sv @@ -1299,12 +1299,9 @@ module cachepool_tile automatic logic sel_found; automatic int unsigned sel_part_idx; - // Timing (T1.1): bank_we/bank_req are value-identical to direct OR-reduces - // of the part bits (the arbiter always selects a write-part when any - // write exists, else a read-part), so compute them directly off the - // critical path tail (data-bank we -> meta-write clock-gate) instead - // of riding the priority cascade + 4:1 sel_part_idx mux. addr/wdata/ - // be still use the mux. Matches gen_unfolded_data_banks (1303-1304). + // Timing: we/req equal the OR of the part bits (the cascade prefers a write part), + // so take them directly instead of through the sel_part_idx mux, off the critical + // path tail. addr/wdata/be still use the mux. bank_we[col][bank_sel] = |part_we[col][bank_sel]; bank_req[col][bank_sel] = (|part_we[col][bank_sel]) | (|part_req[col][bank_sel]); bank_addr[col][bank_sel] = '0; diff --git a/reports/design_notes/PARTIAL_BARRIER_MISUSE.md b/reports/design_notes/PARTIAL_BARRIER_MISUSE.md deleted file mode 100644 index 0828152..0000000 --- a/reports/design_notes/PARTIAL_BARRIER_MISUSE.md +++ /dev/null @@ -1,202 +0,0 @@ -# The RLC partial-barrier design is wrong at more than one tile - -**2026-09-08.** Found by the GVSoC session after they implemented real -participation-mask semantics. Two independent defects, both mine, both -invisible in every configuration I have tested. - -## Defect 1 โ€” the cluster mask is programmed and never restored - -`cachepool_cluster_barrier.sv`: - -```systemverilog -Idle: if (|(tile_barrier_i & barrier_mask_i)) begin - mask_d = barrier_mask_i; // re-read from the REGISTER every round -assign all_arrived = (tile_barrier_i & mask_q) == mask_q; -``` - -**There is no full-versus-partial distinction at the cluster level.** The -read/write distinction exists only in the *tile* barrier, for the per-core -mask. The cluster mask is persistent and gates every round. - -`rlc_ul_init()` and `rlc_am_init()` set it to "tile 0 only" from `rlc_init()` -and never restore it. From that point **every `snrt_cluster_hw_barrier()` in -the program waits only for tile 0** โ€” including `main.c`'s startup resync and -the final barrier before the report. At 64 cores the other 60 sail through -unsynchronised. - -## Defect 2 โ€” participants and non-participants share a tile - -`cachepool_tile_barrier.sv`: - -```systemverilog -req_mask[i] = in_req_i[i].q.write ? in_req_i[i].q.data[NrPorts-1:0] - : {NrPorts{1'b1}}; // a READ means "all" -MaskIdle: if (|barrier_hit) begin - core_mask_d = req_mask[first_hit_idx]; // FIRST arrival owns the round -``` - -**Whichever request arrives first defines the round's participant set.** In -`cluster_entry()` the non-participating cores โ€” idle ones, and producers once -they finish โ€” go to `snrt_cluster_hw_barrier()`, a *read*, meaning "all cores -in this tile". Consumers in the same tile are meanwhile issuing partial-barrier -*writes*. - -So a consumer's partial barrier can be absorbed into an all-cores round (and -then blocks until every core in the tile arrives), or an idle core's full -barrier can be absorbed into a consumers-only round (and released early). -**Mixing the two inside one tile is unsafe by construction.** - -This one is not even multi-tile-specific: at 4 cores with P1/C1, cores 2 and 3 -are idle and parked at the full barrier while core 1 runs partial barriers. - -## Why nothing caught either - -- **Defect 1 is a no-op at one tile.** Every RLC run puts producers and - consumers in tile 0, where the mask is `0x1` โ€” the only tile. -- **Defect 2 has never run on correct barrier hardware.** GVSoC's barrier was - a global counter to `nb_cores` until today โ€” no masks at all โ€” so the model - could not expose it, and the partial-barrier TTI path has not been run on - RTL. - -The pattern from the other notes repeats: **a test passing is not evidence the -mechanism works, when the platform never implemented the mechanism.** - -## Defect 3 โ€” the mask restricts who must ARRIVE, not who gets RELEASED - -`cachepool_cluster_barrier.sv` has a single `barrier_done_o`, and every tile's -cores release on it unconditionally: - -```systemverilog -// cachepool_tile_barrier.sv -Global: if (barrier_done_i) state_d[i] = Take; // no mask check -``` - -**So any partial-barrier round's completion releases every core waiting at a -barrier anywhere in the cluster.** `barrier_mask_i` gates the *arrival* -condition (`all_arrived = (tile_barrier_i & mask_q) == mask_q`) and nothing -gates the broadcast. - -The consequence is stronger than defects 1 and 2, and it constrains any fix: - -> **A partial barrier is only safe when no core outside the participating set -> is waiting at a barrier at the same time โ€” anywhere in the cluster, not just -> in the same tile.** - -### Refuted: "move the non-participants to another tile" - -This is the obvious fix for defect 2 and it does not work. Recorded here so the -next person does not spend the same hour on it. - -The idea: if only consumers occupy the consumer tile, no read-barrier and -write-barrier ever share a tile, so defect 2 disappears โ€” and non-participants -in other tiles are outside the cluster mask, so they cannot satisfy the arrival -condition either. - -Why it fails: **they do not need to satisfy the arrival condition to be -released.** `barrier_done_o` is broadcast, and a core in `Global` takes it -whatever tile it is in. So the participants' first partial-barrier round frees -every non-participant that has reached its own tile barrier, cluster-wide. - -It means the software spin in step 3 below is not a design preference, it is -the only construct the hardware leaves. - -## The API contradiction underneath - -`snrt.h` says to program the mask and then "use `snrt_cluster_hw_barrier()` as -a resync point before relying on it". But the narrowing is already in force by -then, so that resync barrier is itself masked and does not wait for everyone. -**The documented usage cannot work at more than one tile.** A fix has to -restructure the arm/resync sequence, not just add a restore. - -## Proposed fix (not yet implemented) - -1. **Do not program the mask in `rlc_init()`** โ€” that precedes `main.c`'s - startup full barrier, which the narrowing would break. -2. **Arm inside the consumer entry**: consumer 0 programs the mask; the other - consumers wait on an `_Atomic` release/acquire flag plus a fence, *not* on a - barrier โ€” they cannot use the barrier they are about to narrow. -3. **Keep non-participants out of the barrier entirely** while partial barriers - are in use: idle cores and finished producers spin on a "consumers done" - flag instead of entering `snrt_cluster_hw_barrier()`. **Forced by defect 3**, - not chosen โ€” moving them to another tile does not help, because the done - signal is broadcast cluster-wide. The flag needs `_Atomic` release/acquire - plus a fence (same treatment as `rlc_ul_barrier_armed`), and a back-off - between polls so it does not reintroduce the traffic the TTI loop exists to - remove. Note the *participants* still block on a real barrier โ€” only cores - with no work spin, and they had nothing else to do. -4. **Restore the mask to all-ones** (its `RESVAL`) after the TTI loop, before - setting that flag, so the final full barrier is a real full barrier. - -Costs one flag and one spin per non-participant, and removes the mixed-mode -round entirely. - -## Verification plan - -GVSoC can run a candidate at 4 and 16 tiles in minutes โ€” that is where the -difference appears, and their model now reproduces the contradiction faithfully -rather than hiding it. Cheaper than RTL for the first pass; RTL confirms after. - -## Related - -`SYNCHRONISATION_IS_NOT_VISIBILITY.md` โ€” the barriers do not fence. -`PROVENANCE_THE_TOOL_NOT_THE_CONFIG.md` โ€” measure the artefact, not the config. - -## The fix requires masked barrier semantics โ€” measured, and it is a feature - -Verified on GVSoC, same binary and config, 1 tile: - -``` -masked barrier -> retval=0, 1,137,580 cycles, MASK-OK, check: PASS (<110 s wall) -counting barrier -> no completion in 400 s (4x budget), no UL/MASK/EOC output -``` - -It is a **deadlock, not slowness**: the counting barrier is cheaper per -operation, and the masked arm finished the identical workload in under a -quarter of the budget. - -**Mechanism โ€” defect 3 read backwards.** The fix has non-participants spin -*outside* the barrier. A barrier that completes at `count == nb_cores` then -waits for arrivals that will never come: at 1 tile, one consumer waiting for -four. Deadlock by construction. The fix and a counting barrier are mutually -incompatible. - -Three things follow, and the third is the one to be careful about: - -1. **The 1/4/16-tile pass is a joint result.** The kernel change and correct - masked semantics are each necessary and neither is sufficient. -2. **The failure character changed, deliberately and for the better.** Before - the fix, a mask that was absent or misprogrammed produced *silent - corruption* โ€” phases overlapping, short delivery, plausible output. After - it, the same condition produces a **hang**. A deadlock is detectable; quiet - wrong answers are not. This is worth stating because it looks like a - regression in robustness and is the opposite. -3. **It says nothing about whether the masked implementation is correct**, only - that it differs and that the fix needs the difference. A deadlock on the old - barrier would look identical if the new one were wrong in some *other* way. - The RTL readings remain the only evidence for correctness. - (Distinction drawn by the GVSoC session against their own result.) - -**Portability consequence:** this kernel now requires a platform that implements -the participation mask. That is true of the RTL and was not true of the model -until today. - -## Verification, 2026-09-08 - -Passed at 1, 4 and 16 tiles. The decisive evidence was read from the **barrier's -own state**, not from the kernel's self-report: - -``` -16 tiles: 6 x 0xffff -> 33 x 0x1 -> 3 x 0xffff - 4 tiles: 6 x 0xf -> 33 x 0x1 -> 3 x 0xf - 1 tile: all 0x1 (narrowing is a no-op -- why it hid here) -``` - -Startup barrier full, consumers progressing narrowed, mask restored before -release, and the shape independent of tile count. - -**Independent cross-check on the 33.** Derived from the traffic profile: -488 SDUs per TC1 slot / 49 PDUs per 8192 B block = 11 slots, x 3 phase barriers -= **33**. Measured from barrier state on the model side. Two independent paths -to the same integer with no shared intermediate โ€” so the narrowed region -contains exactly the barriers the kernel should issue and no others: nothing -leaked in from an absorbed full barrier, and none escaped. diff --git a/reports/design_notes/PROVENANCE_THE_TOOL_NOT_THE_CONFIG.md b/reports/design_notes/PROVENANCE_THE_TOOL_NOT_THE_CONFIG.md deleted file mode 100644 index 940314b..0000000 --- a/reports/design_notes/PROVENANCE_THE_TOOL_NOT_THE_CONFIG.md +++ /dev/null @@ -1,193 +0,0 @@ -# Ask the tool what it did, not the config what it should have done - -**2026-09-08.** Two provenance failures in one night, on two sides of the same -comparison, both of which would have produced a clean-looking wrong answer. - -## The rule - -**A configuration file states an intention. Only the generated artefact records -what actually happened.** Read the artefact. - -## Case 1 โ€” `Bender.local` overrides do not apply until the lock is regenerated - -`Bender.local` says: - -```yaml -overrides: - insitu-cache: { path: "working_dir/insitu-cache" } -``` - -`Bender.lock` says: - -```yaml -insitu-cache: - revision: f1cbe54dca0989f025b0450e85c42faf2bf5cbf1 - source: - Git: https://github.com/pulp-platform/Insitu-Cache.git -``` - -**The lock wins.** It resolves to a Git checkout under `hardware/deps/`, not to -the overridden path, until `bender update` regenerates it. So reading -`Bender.local` and concluding "we are compiling `working_dir`" is wrong twice -over: - -1. the lock still resolves to `hardware/deps`, and -2. `sim/work/compile.vsim.tcl` is a make target whose prerequisites are - `rtl_lib.cc`, `common_lib.cc`, `bootdata.cc`, `bootrom.bin` โ€” **RTL sources - are not among them**, so `make vsim` does not re-run bender at all and a - months-old script stays authoritative. - -Either alone is enough to defeat the override. A peer independently hit the -same thing from the other direction: repointed `Bender.local` at a private -copy, launched a run, and the tool analysed the original tree anyway. - -**Do:** `grep` the resolved path out of the generated `compile.vsim.tcl`. -**Don't:** infer it from `Bender.local`, `Bender.yml`, or a `bender` command -you ran earlier. - -## Case 1b โ€” the dependency tree is tool-owned, so its contents are not stable - -Worse than the resolution problem: `hardware/deps/insitu-cache` is a -**bender-managed git checkout**, not a plain directory. - -``` -$ cd hardware/deps/insitu-cache && git status -sb -## HEAD (no branch) <- detached, as bender leaves it - M src/insitu_cache/insitu_cache_core.sv - M src/insitu_cache/insitu_cache_encoder.sv - M src/insitu_cache/insitu_cache_tcdm_wrapper.sv - M src/utilities/sram_forwarding_buffer.sv -?? DIRTY_zexin_timing_f1cbe54 -``` - -HEAD is `f1cbe54` and `Bender.lock` says `f1cbe54`, so **bender considers this -directory already correct.** Modified RTL exists only as uncommitted -working-tree changes on top. Any `bender checkout` / `bender update`, or a make -target depending on them, is entitled to restore the tree โ€” and it looks like -housekeeping, not a DUT change, precisely because HEAD already matches. - -**The failure mode is silent and inverts the result.** A mid-run revert means -the remaining tests measure *pristine* RTL, and they pass โ€” which is exactly -what a correct set of rewrites would also produce. Nothing looks wrong. - -**And the obvious mitigation is the one that fails here.** A marker file placed -in that directory (`DIRTY_zexin_timing_f1cbe54` above) is *untracked*, so a -`git checkout` reverts the `.sv` files and **leaves the marker standing**. The -marker then asserts "dirty" over pristine sources: worse than no marker. - -**The general rule:** *an assertion that can outlive the condition it asserts -must carry the means to falsify itself.* A marker file cannot detect a revert, -but it can refuse to be believed without a check that would โ€” so it should open -by telling the reader not to trust it, name the check, and point at an -authoritative copy outside the tree. That is weaker than a tripwire, and it is -what is available inside a directory another tool owns. - -**Do:** keep the provenance record *outside* the tool-owned tree (here, -`reports/rtl_reference_2026-09-08/dut_tripwire.sha256`), and sample it -*during* a long run, not only at the end โ€” detection after the fact costs a -rerun. `dut_watch.sh` samples every 45 s and timestamps any change, so results -can be attributed to the DUT state that produced them. - -## Case 2 โ€” a rebuild silently changes what a peer's comparison arm reads - -Two sessions compared RTL arms using ELFs from a shared `software/build/`. -One session was about to rebuild one of those ELFs (adding a fence to a test) -while the other planned to run it. The arms would then have differed in two -variables โ€” cache RTL *and* test binary โ€” and nothing in either log would have -shown it. - -**Do:** freeze the exact binaries a measurement used, `chmod a-w`, with a -manifest, *before* touching the build directory. Point collaborators at the -frozen copy, not at `software/build/`. - -## Case 3 โ€” relative paths make the working directory a shared resource - -The simulation monitors write to **relative** `sim/bin/logs/{core,noc,others}` -paths. A run launched from a different working directory therefore scatters its -writes into whatever tree happens to be cwd โ€” including another session's, if -two people are simulating the same repo from different copies. - -Nothing errors. The victim's logs simply acquire another run's data, and the -provenance of both becomes unreconstructable after the fact. - -**Do:** mirror the `sim/bin/logs` tree under your own directory before -launching an isolated arm, and launch from there. - -**But the transferable part is the habit, not this instance.** It was not -reasoned out โ€” it was found by grepping the testbench for `$fopen` to learn -what it would touch *before* launching into a shared tree. Generalised: - -> **Before running something somewhere new, grep for what it writes.** - -Same shape as reading the generated script instead of the config: ask the -artefact what it will do, rather than assuming it does the obvious thing. -(Found by the L1-timing session while preparing their pristine arm.) - -## What made both catchable - -Not reasoning โ€” checking: - -| check | caught | -|---|---| -| `grep` the resolved path from the generated script | the `Bender.local` inference | -| hash the compile script + **all 30** sources it names | a mid-batch tree switch (tripwire) | -| verify a frozen ELF still matches the live one | that the freeze predated the rebuild | -| `pgrep -a vsim` before any process action | 19 unrelated simulations, none this repo | -| `git status -sb` inside a dependency directory | that it is a tool-owned detached checkout, revertible without warning | - -Each is seconds of work and each caught something the reasoning missed. Write -the comparability conditions down **before** running, while there is no result -yet to be tempted by. - -**A freeze is a claim about a moment; it becomes evidence only when something -independently ties it to that moment.** For the ELFs that was a peer verifying -the frozen copy still matched the live one โ€” proving the freeze predated the -rebuild. For the RTL it was two sessions hashing the same four files from -opposite directions and agreeing. Neither artefact is self-validating, and a -manifest written after the fact looks identical to one written before. - -## Related - -See `SYNCHRONISATION_IS_NOT_VISIBILITY.md` for the other pattern from the same -night: a primitive whose name promises more than it delivers. - -## The mechanism, stated plainly - -Across a night of two sessions checking each other, every real finding came from -one move and every failure from its opposite: - -| finding | what settled it | -|---|---| -| the tile mask is never programmed in UL builds | disassembly, not the source | -| "3 call sites" for `snrt_barrier_set_tile_mask` | they were source comments; resolved `auipc`+`jalr` targets settled it | -| which RTL tree the batch compiled | the generated `compile.vsim.tcl`, not `Bender.local` | -| which peripheral map an ELF uses | `set_eoc`'s immediate, not the header | -| whether a run succeeded | the `[EOC]` line, not plausible output | -| whether a register is the mask | its `RESVAL` signature, not that the address accepts a write | -| whether a peer's map claim held | the model's decode path, not its variables | - -**The useful mechanism was not either party being right. It was each checking -the other's claim against an artefact rather than against a description.** Both -sides' errors came from the reverse: reading intent out of a name, a header, a -config file, or a partial output. - -**But the asymmetry is not uniform, and the distinction changes the lesson.** -Of six defects found across two engines in one session, none was found by the -owner of the code โ€” yet not all by the same route: - -- **Five** came from one side reading an artefact the other could not generate: - `[XLINE]` addresses, a 1.00-per-grant rate, a residue table, a binary run on - the other's platform. These argue for **exchanging raw artefacts**, not - summaries โ€” a summary would have omitted the address that mattered. -- **One** โ€” the partial-barrier semantics โ€” came from reading the RTL directly - and comparing it against a model built from an older understanding. No - artefact from the other side was involved. This argues for something else: - **periodically re-read the reference rather than trusting an old - transcription of it.** - -Both lessons are real and they are not the same lesson. (Distinction drawn by -the GVSoC session against a claim of mine that flattened them.) - -Corollary worth keeping: a check that cannot fail is not a check. A guard that -echoed the value it had just written reported healthy on a run where the write -went to the wrong address entirely. diff --git a/reports/design_notes/SYNCHRONISATION_IS_NOT_VISIBILITY.md b/reports/design_notes/SYNCHRONISATION_IS_NOT_VISIBILITY.md deleted file mode 100644 index 7f95f00..0000000 --- a/reports/design_notes/SYNCHRONISATION_IS_NOT_VISIBILITY.md +++ /dev/null @@ -1,83 +0,0 @@ -# Synchronisation is not visibility - -**2026-09-08.** Four instances of one defect in a single day, across the RLC -kernel and the cache test suite, on two engines. The instances are cheap to fix -individually; the pattern is the thing worth keeping. - -## The rule - -**Both of this runtime's barriers are a single memory-mapped access. Neither -emits a fence. They make cores wait for one another and nothing more.** - -```asm -_snrt_cluster_barrier: ; snRuntime/src/platforms/shared/start_snitch.S:35 - call _snrt_barrier_reg_ptr - lw a0, 0(a0) ; the entire barrier - ret -``` - -```c -void snrt_cluster_partial_barrier(uint32_t local_mask) { /* snRuntime/src/barrier.c */ - *(volatile uint32_t *)_snrt_barrier_reg_ptr() = local_mask; -} -``` - -So a store made before a barrier is **not** guaranteed visible to another core -after it. The names promise otherwise, which is the whole problem: "barrier" is -read as a memory barrier, and it is not one. - -A second, independent case of the same confusion: **Snitch and Spatz have -separate load/store units.** A vector store and a scalar load of the same -address are unordered with respect to each other without an explicit `fence`. - -And in both cases `volatile` does not help. It constrains the *compiler*. It -says nothing about a write buffer, an async cache, or a second LSU. An inline -asm `"memory"` clobber is likewise compiler-only. - -## The instances - -| # | Site | Handoff | Symptom | -|---|---|---|---| -| 1 | `rlc_ul_drv.c` armed flag | core 0 store โ†’ consumers load, across `snrt_cluster_hw_barrier()` | Flag read as 0 on every consumer. **Store and load both provably executed** (disassembly) and disagreed. | -| 2 | `rlc_am.c` / `rlc_ul_drv.c` TTI phase barriers | owner writes ~7 KB plan โ†’ helpers read it to copy payload | Suspected silent transport-block corruption; open. | -| 3 | `cache-mix-smoke/main.c` | Spatz `vse32.v` โ†’ Snitch scalar load, same address | **125 mismatches on RTL.** `fences: 0` in the file. | -| 4 | `cache-test-scalar/main.c` | core 0 writes 256 lines โ†’ all cores read, 14 bare barriers | Fails on GVSoC at 48-84 % density; `cache-basic` sub-test **passes on RTL**. | - -## What #4 shows that the others don't - -Instance 4 fails on the model and passes on hardware for the *same binary*. -That is not a model defect and not a hardware defect โ€” it is a **latent -software defect whose exposure depends on how wide the store-visibility window -is**. The model's async cache has a wider window than the RTL's, so the model -exposes it and the hardware hides it. - -The practical consequence: **passing on RTL is not evidence that this class of -bug is absent.** A test can rely on a guarantee it never had, and hardware -timing can conceal that indefinitely. - -## What to do - -1. Fence both sides of every phase boundary that hands memory between cores. - `rlc_sync.h`'s `rlc_phase_barrier()` is the pattern: fence, barrier, fence. -2. Fence after a vector store before any scalar access to the same address. - `rlc_copy.h`'s `rlc_memcpy8()` already does this. -3. For a flag one core publishes for others, use `_Atomic` with release/acquire - **and** a fence โ€” the atomic alone orders the compiler and the single core's - accesses, not the fabric. -4. Do not read `volatile` as a synchronisation primitive anywhere. - -## Cost - -Two `fence` instructions per boundary. Against a phase of work this is -irrelevant, and it is unconditionally cheaper than a silently wrong transport -block or a test that passes for the wrong reason. - -## Open - -- Whether #2 explains the RLC multi-entity wedge (M16/24/48). Fixed because it - is a defect regardless; **not** asserted as the wedge's cause. -- Whether fencing #4 collapses the GVSoC mismatch density. Experiment pending. -- #3 needs a pristine-RTL arm to separate "test was always racy" from "recent - cache rewrites perturbed the race" โ€” both hypotheses predict that adding a - fence fixes it, so the fence experiment alone cannot separate them. - (Correction owed to the L1-timing session, who caught that.) diff --git a/reports/history_rewrite_2026-09-30.map b/reports/history_rewrite_2026-09-30.map deleted file mode 100644 index f9c206d..0000000 --- a/reports/history_rewrite_2026-09-30.map +++ /dev/null @@ -1,39 +0,0 @@ -# old new subject -2094188 c7ddb5d [RTL] add insitu_cache_ooc_wrapper: OOC timing harness for one L1 cache ctrl -7325757 7cbc7a2 rlc: AM transport-block assembly (DL) and reassembly (UL) -db94852 ec7a2ff rlc: fence the UL phase barriers; align uplink to the documented 160 B profile -de08892 eea647a worklog: RTL reference batch, bandwidth reproduces pristine exactly -0346ebf 4239973 rlc: fence the TTI phase barriers -aa7ad50 d11b98c notes: synchronisation is not visibility -- four instances of one defect -691d316 22ad3e4 notes: read the generated artefact, not the config -c47d883 909b88d notes: dependency tree is tool-owned; a marker inside it can outlive a revert -e7ad2d4 ccd5077 notes: an assertion that can outlive its condition must carry its own falsifier -136fe71 18ae20d rlc: read the participation-mask register back instead of echoing what we wrote -577ba57 523b8e2 notes: RLC partial-barrier design is wrong at more than one tile -171c79d dab460d notes: barrier done is broadcast cluster-wide, so the mask gates arrival not release -0143e71 aaec01a notes: record the refuted workaround for defect 2 explicitly -d6d7439 c08c1fc notes: the mechanism was checking claims against artefacts, not descriptions -f3269de 3b4b1a0 reports: RTL reference batch 2026-09-08 -- cycle-identity established on two kernels -681813e 20cb24a worklog: batch complete; partial-barrier design broken at three levels -01d17a5 317b85c reports: record that the batch measured T3.1-T3.15, not the recommended T3.1-T3.12 -a05aeea 3a584af notes: relative log paths make cwd a shared resource across sessions -a750067 3488749 notes: the transferable part is the habit -- grep for what a thing writes before running it -246b430 9cd4457 reports: pristine arm clears cache-mix-smoke and makes it a third cycle-identity kernel -a9c647f 4a9995a reports: qualify the sensitivity argument -- the race window width is unmeasured -dedde97 cbc45bf reports: close the T3.1-T3.15 batch record; pin the T3.1-T3.12 state, unrun -6df0e68 dd5531e rlc: fix partial-barrier misuse -- arm on entry, keep non-participants out, restore on exit -a79e83b 671462c notes: the fix requires masked semantics -- deadlocks without them, by construction -145d66a 46e1a33 rlc: the grant verifier still assumed SN advances per PDU -e0f505c 3da7786 rlc: one AM progress line per grant, always -843032d 4a5b0de worklog: partial-barrier fix validated; AM mismatch column resolved as three bugs -b6eb72f 4245048 worklog: wedge signature absent at 64 cores/M48; original observation retracted as confounded -32b5198 a0e5d3d notes: five of six were cross-artefact, one was re-reading the reference -00ab4ef da9f0b6 rlc: TTI loop never terminated with the work queue on; fix polls, UL rate, phase cost -a3ced2b 9ac50f9 worklog: kernel review and four fixes -2cc5b8a 78a00b0 rlc: software perf-probe hooks (RLC_PROBE=1, default builds unchanged) -09fba4d e16dd15 rlc: full-cluster DP test cases (TC1/TC2/TC3, 64 producers + 192 consumers), probe targets -eb9259e 3ba3e5d rlc: lock/flag cache-line padding (RLC_PAD_SYNC), paced arrival (RLC_ARRIVAL_PPS), multi-slot sweep targets -4942fc4 2cf725c rlc: per-group packet streams and node pools (RLC_GROUP_STREAMS) with work stealing -33fb09d 1bfe7b2 rlc: tile affinity on a half-private L1, AM in-tile and cross-tile, batched AM commit -b997edd 2e03e38 rlc: AM tile STATUS on a dirty bitmap, multiple grants per owner per TTI -0b40899 82613d3 rlc: TC1 at target -- descriptor-ring to-send queue, owner plans in its private partition diff --git a/reports/rtl_reference_2026-09-08/RESULTS.md b/reports/rtl_reference_2026-09-08/RESULTS.md deleted file mode 100644 index be20873..0000000 --- a/reports/rtl_reference_2026-09-08/RESULTS.md +++ /dev/null @@ -1,160 +0,0 @@ -# RTL reference batch โ€” 2026-09-08 - -Config `cachepool_fpu_4g` (4 groups x 4 tiles x 4 cores = 64), QuestaSim. -Requested by the L1-timing session to check whether 15 cache rewrites are -cycle-identical. Run on their working tree; provenance pinned (see below). - -| kernel | status | EOC (cyc) | kernel cyc | 08-25 pristine | verdict | -|---|---|---|---|---|---| -| `bandwidth` | **PASS** | 33,876 | 2,058 (32/load) | 33,876 / 2,058 / 32 | **exact match** | -| `byte-enable` | **PASS** | 303,288 | n/a | 303,288 | **exact match** | -| `cache-mix-smoke` | **FAIL** | 69,378 | 125 mismatches | pristine: 69,378 / 125 | **exact match** โ€” test bug | -| `cache-test-scalar` | `timeout_cap` | โ€” | `cache-basic` **PASS** | no baseline | partial | -| `cache-test-vector` | `timeout_cap` | โ€” | `vcache-basic` **PASS** | no baseline | partial | - -128 scoreboards PASS / 0 FAIL on all three that reached EOC. Zero illegal -instructions anywhere โ€” so no scalar-FP traps in this set. - -## Cycle-identity: established - -`bandwidth` and `byte-enable` both reproduce the 2026-08-25 pristine reference -**bit-identically**, against references taken two weeks before the rewrites -landed. Per-channel AR/R also match (CH0 159/182, CH1 8/9, CH2 4/4, CH3 164/227), -so refill traffic is identical in count *and* distribution. - -**EOC is the stronger figure than kernel cycles** (the peer's point): kernel -cycles cover the hot loop, EOC covers boot, snRuntime init, barriers, teardown -and all 64 cores. Nothing anywhere in either run shifted by a cycle. - -**Consequence:** if the RLC multi-entity wedge depends on write-visibility -*timing*, the L1D rewrites are excluded as a confound โ€” the cache presents -writes on identical cycles before and after. - -## Scope: this measured T3.1-T3.15, which may not be what ships - -The DUT here is the timing session's **full** transform set, T3.1 through T3.15. -Their post-placement OOC ladder subsequently recommended shipping **T3.1-T3.12 -only** (WNS -0.091 vs -0.106; T3.13 alone accounts for 13 of the 15 ps). - -So this batch is evidence for a **superset** of the intended ship set. Whether -cycle-identity carries to the subset follows only if each transform is -independently cycle-neutral โ€” which is plausible, is what they claim, and is -**not what this batch measured**. Reverting three transforms is also a code -change that can itself introduce error, which a re-verify would catch and an -inference would not. - -**Re-verify `bandwidth` on the reduced set before anyone calls it verified.** -That is ~10 minutes of wallclock and it is the difference between a measurement -and an argument. - -## `cache-mix-smoke` โ€” a test bug, attributable without a pristine arm - -```c -vec_store_u32(base + part_ofst); // vse32.v -> Spatz's LSU -for (j...) if (*(volatile uint32_t*)(base + part_ofst + j*4) != vec_vals[j]) errs++; - // scalar load -> Snitch's LSU -``` - -Independent LSUs, no `fence` between them; `fences: 0` in that file. `volatile` -constrains the compiler and says nothing about two hardware load/store units. -Predates the rewrites and is independent of the cache datapath. - -**Settled by a pristine arm (2026-09-08).** Pristine `f1cbe54` fails -identically: - -| arm | RTL | EOC | UART | scoreboards | -|---|---|---|---|---| -| this batch | T3.1-T3.15 | 69,378 | `[FAIL] 125 mismatches` | 128 PASS / 0 FAIL | -| pristine | f1cbe54 | 69,378 | `[FAIL] 125 mismatches` | 128 PASS / 0 FAIL | - -Same count, same tally, **EOC identical to the cycle**. The race predates every -transform in the set. The caveat this row used to carry โ€” that a fence would -fix it either way, so the fence experiment could not separate "always racy" -from "the rewrites changed the exposure" โ€” is discharged by measurement rather -than by argument. - -**And it upgrades the cycle-identity result.** `cache-mix-smoke` is now a -*third* matching kernel, and the most informative of the three: RTL simulation -is deterministic, so a program whose output depends on inter-core timing -detects a class of perturbation a passing kernel cannot. Two clean kernels show -the transforms do not change correct programs; this one shows they do not -change a program that is *already* sensitive to timing between cores. - -**Qualification โ€” the sensitivity argument rests on something neither arm -measured: the width of the race window.** If the losing core loses by a handful -of cycles, the count is a fine detector and "almost any perturbation would have -moved it" holds. If it loses by several hundred, the count is insensitive to -small shifts and the same 125 would return whether or not timing moved. Both -are consistent with everything observed, because neither arm instrumented the -window. - -So: **the cycle-identical EOC is the hard result. The sensitivity argument is a -reason to weight it above a passing kernel, not an independent proof.** -(Qualification raised by the L1-timing session against my own framing; recorded -because "sensitive detector" reads as proof of non-perturbation to anyone who -has not reasoned about the window โ€” the same way "identical failure" reads as -set-equality.) - -**Limitation, recorded before either side leans on it:** the test prints only a -count, never the mismatching addresses. The comparison is over -(count, EOC, scoreboard tally) and does **not** establish that the same 125 -locations mismatched on both arms. Two different races landing on the same -count *and* the same cycle would be remarkable, but the instrument cannot rule -it out. Closing that gap needs a test change (print addresses), not an RTL one. - -## The two capped tests, and the part that is still informative - -Both hit the 1 h per-test cap during their `*-stress` phase. Both had already -**passed their `*-basic` phase**, which is the interesting half: - -> `cache-basic` and `vcache-basic` are unfenced cross-core write / barrier / -> read tests โ€” `fences: 0, volatile: 0, atomics: 0, 14 bare hw barriers` โ€” and -> **they pass on RTL**, while the same source fails on GVSoC at 48-84 % density. - -Same binary, passes on hardware, fails on the model. The hazard is real and in -the source; hardware's store-visibility window is narrow enough to hide it. -**Passing on RTL is not evidence this class of bug is absent.** - -Caveat added after the fact: the GVSoC arm ran under a global counting barrier -that has since been replaced, so that comparison needs re-measuring before it -is leaned on. Flagged by the GVSoC session, accepted here. - -## Provenance - -- DUT is `hardware/deps/insitu-cache` โ€” **grepped from the generated - `compile.vsim.tcl`**, not inferred from `Bender.local`, whose override never - applied (see `design_notes/PROVENANCE_THE_TOOL_NOT_THE_CONFIG.md`). -- `dut_tripwire.sha256` pins the compile script + all 30 insitu sources. - `dut_watch.sh` sampled it every 45 s: **130 samples, 0 changes.** -- `elf_under_test/` holds the exact test binaries used, frozen `chmod a-w` with - a manifest, verified by the peer against live `software/build` *before* any - rebuild โ€” which is what makes the freeze evidence rather than a claim. -- The four modified cache sources under test: - `b23ed202 / 2bf77815 / 5307c217 / f0629785`, independently confirmed by the - peer from a marker written before this batch was pinned. - -## Wallclock - -| kernel | wall | -|---|---| -| `bandwidth` | 598 s | -| `byte-enable` | 889 s | -| `cache-mix-smoke` | 236 s (pristine arm: 211 s) | -| `cache-test-scalar` | capped at 3600 s | -| `cache-test-vector` | capped at 3600 s | - -I predicted `byte-enable` would cap by extrapolating linearly from -`bandwidth`'s cycles-per-second. It took 15 minutes, not 90. **Wall time is not -linear in EOC cycles across kernels** โ€” different core counts and DRAM traffic. - -## Post-batch: the DUT has since changed (expected) - -At 07:43 the L1-timing session reverted T3.13-T3.15 and synced T3.1-T3.12. -`verify_dut.sh` in this directory now reports FAILED on -`insitu_cache_tcdm_wrapper.sv` and `sram_forwarding_buffer.sv` โ€” **that is -correct and expected**, not a provenance failure. Everything in this report was -measured before the sync, under the 130 clean tripwire samples recorded in -`dut_watch.log`. - -The new state is pinned separately in `reports/rtl_reference_t312_pending/`. -Do not re-run `verify_dut.sh` here expecting a pass; this directory is closed. diff --git a/reports/rtl_reference_2026-09-08/RTL_STATE.md b/reports/rtl_reference_2026-09-08/RTL_STATE.md deleted file mode 100644 index 797f573..0000000 --- a/reports/rtl_reference_2026-09-08/RTL_STATE.md +++ /dev/null @@ -1,53 +0,0 @@ -# RTL state under test โ€” batch 2026-09-08 - -**RESOLVED PATH, grepped from the compile script โ€” not inferred from Bender.local.** - -`Bender.local` does override insitu-cache to `working_dir/insitu-cache`, and I -originally wrote that the batch therefore compiles that working copy. **That was -wrong.** `sim/work/compile.vsim.tcl` (mtime 2026-08-24 23:18, NOT regenerated) -resolves to `hardware/deps/insitu-cache`, and that is what vlog reads: - -``` -"$ROOT/./hardware/deps/insitu-cache/src/insitu_cache/insitu_cache_core.sv" -``` - -`compile.vsim.tcl` is a make target whose prerequisites are rtl_lib.cc, -common_lib.cc, bootdata.cc and bootrom.bin โ€” **RTL sources are not among them**, -so `make vsim` does not re-run bender and the Aug-24 script stands. - -The results are still valid, verified rather than assumed: the two trees are -byte-identical (`cmp` on all four modified files) and produce the same -diff-vs-HEAD hash `f6657ec2ac4eda12`. Only the path was wrong, not the DUT. - -**Hazard for future readers:** if anything touches a prerequisite of -compile.vsim.tcl mid-batch, make re-runs bender, the override takes effect, and -the source path switches trees silently โ€” a no-op only while the trees match. -`dut_tripwire.sha256` pins the compile script and every insitu source it names; -`verify_dut.sh` re-checks it after the batch. - -## IP git state -``` -f1cbe54 [Verif] Waive check for store requsets since Spatz do not need order in this case - -M src/insitu_cache/insitu_cache_core.sv -M src/insitu_cache/insitu_cache_encoder.sv -M src/insitu_cache/insitu_cache_tcdm_wrapper.sv -M src/utilities/sram_forwarding_buffer.sv - -diff vs HEAD: 1275 lines, sha256 f6657ec2ac4eda12 -``` - -## Modified file mtimes (all predate the vsim compile at ~03:44) -``` -2026-09-07 23:25 src/insitu_cache/insitu_cache_encoder.sv -2026-09-08 00:24 src/insitu_cache/insitu_cache_core.sv -2026-09-08 01:56 src/insitu_cache/insitu_cache_tcdm_wrapper.sv -2026-09-08 02:04 src/utilities/sram_forwarding_buffer.sv -``` - -## Attribution -- HEAD `f1cbe54` is the pristine baseline; the 4 modified files are the timing rewrites. -- `bandwidth` has a known-good pristine reference from 2026-08-25 (2,058 kernel cyc / 32 cyc-per-load), - so a deviation there is attributable to these rewrites. -- `cache-test-scalar` / `cache-test-vector` have NO pristine arm in this batch and may trap for an - unrelated reason (scalar-FP offload defect). Single-arm results there are UNATTRIBUTABLE โ€” informational only. diff --git a/reports/rtl_reference_2026-09-08/build_report.sh b/reports/rtl_reference_2026-09-08/build_report.sh deleted file mode 100755 index 7ec7c5d..0000000 --- a/reports/rtl_reference_2026-09-08/build_report.sh +++ /dev/null @@ -1,41 +0,0 @@ -#!/bin/bash -# Rebuild summary.tsv from the logs. The batch script's inline grep looked for -# "Simulation ended at N" but the actual print is "[EOC] Simulation ended at -# N (retval = 0)" in picoseconds -- so it recorded n/a for a run that -# had the number. Parse the logs instead of trusting that grep. -cd /usr/scratch/fenga1/zexifu/manyRVData/ManyRVData_rebase -OUT=reports/rtl_reference_2026-09-08 -printf "kernel\tstatus\teoc_cyc\tretval\tkernel_cyc\tper_load\tsb_pass\tsb_fail\tillegal\n" > $OUT/summary.tsv -for t in bandwidth byte-enable cache-mix-smoke cache-test-scalar cache-test-vector; do - L=$OUT/logs/$t.log - [ -f "$L" ] || { printf "%s\tnot_run\t-\t-\t-\t-\t-\t-\t-\n" "$t" >> $OUT/summary.tsv; continue; } - eocps=$(grep -oE "Simulation ended at +[0-9]+" "$L" | grep -oE "[0-9]+$" | tail -1) - eoc=$([ -n "$eocps" ] && echo $((eocps/1000)) || echo "-") - ret=$(grep -oE "retval = [0-9-]+" "$L" | grep -oE "[0-9-]+$" | tail -1) - kc=$(grep -oE "Total cycles: [0-9]+" "$L" | grep -oE "[0-9]+$" | tail -1) - pl=$(grep -oE "avg per load: [0-9]+" "$L" | grep -oE "[0-9]+$" | tail -1) - sp=$(grep -c "STATUS: PASS" "$L"); sf=$(grep -c "STATUS: FAIL" "$L") - ill=$(grep -ciE "illegal instruction" "$L") - if [ -n "$eocps" ] && [ "$ret" = "0" ] && [ "$sf" = "0" ]; then st=PASS - elif [ -n "$eocps" ] && [ "$sf" != "0" ]; then st=sb_violation - elif [ -n "$eocps" ]; then st=eoc_nonzero_retval - elif [ "$ill" != "0" ]; then st=TRAP - else - # No EOC yet. Three different things, and calling them all timeout_cap is - # the kind of misleading row this script exists to avoid: - # running -- vsim alive and this is the newest log - # crash -- stopped early with an error - # timeout_cap -- neither; it was killed by the wallclock cap - newest=$(ls -t $OUT/logs/*.log 2>/dev/null | head -1) - if pgrep -f "vsimk.*ManyRVData_rebase" >/dev/null 2>&1 && [ "$newest" = "$L" ]; then - st=running - elif grep -qiE "fatal|error:|\\*\\* Error" "$L"; then st=crash - else st=timeout_cap; fi - fi - # Keep the last kernel-printed line: a capped run still carries real results - # (sub-tests that completed), and losing them to a bare timeout_cap row throws - # away the informative half of the run. - lu=$(grep "\[UART\]" "$L" | tail -1 | sed 's/.*\[UART\] *//' | cut -c1-46) - printf "%s\t%s\t%s\t%s\t%s\t%s\t%s\t%s\t%s\t%s\n" "$t" "$st" "$eoc" "${ret:--}" "${kc:--}" "${pl:--}" "$sp" "$sf" "$ill" "${lu:--}" >> $OUT/summary.tsv -done -column -t -s$'\t' $OUT/summary.tsv diff --git a/reports/rtl_reference_2026-09-08/dut_tripwire.sha256 b/reports/rtl_reference_2026-09-08/dut_tripwire.sha256 deleted file mode 100644 index fe8b4e3..0000000 --- a/reports/rtl_reference_2026-09-08/dut_tripwire.sha256 +++ /dev/null @@ -1,31 +0,0 @@ -1203a1440956ab6fcf8c3f8976e89edd649428416ac448d82b8c13437875ceea sim/work/compile.vsim.tcl -d4cf9be82f9770ec17e56bbbf8a82e2cecfbd5b04f02bbb495e561ac837faa2a hardware/deps/insitu-cache/src/cachepool/cachepool_cache_ctrl.sv -cbf220f4643f89dfd484db6e2ee6da772ec8d6581d2a6df5a2a69ba2730b251d hardware/deps/insitu-cache/src/coalesce_unit/par_coalescer/non_coalescer.sv -2b19d084db209bc077c16d3fb5463f1f0041625f833dbd7512a15b06ef579158 hardware/deps/insitu-cache/src/coalesce_unit/par_coalescer/par_coalescer_equal_window.sv -24209b3aeb73769efe59ba5527afd9db2abb024573a66d7eb0c34fc703ab19cd hardware/deps/insitu-cache/src/coalesce_unit/par_coalescer/par_coalescer_extend_window.sv -ba81e0acf3ad966d72024709e02253642c76bb0dfaad99b114f4d1985432bc7b hardware/deps/insitu-cache/src/coalesce_unit/par_coalescer/par_coalescer_top.sv -0b316eeba6ca5dec17f9f5fe9fec15e235fde0794911de7c67a3e62125ca303b hardware/deps/insitu-cache/src/coalesce_unit/par_coalescer/req_coalescer_v2.sv -52905bb68feaee386b1abd2e6efcd08a83a567054df8a95dd957b7884ea7f150 hardware/deps/insitu-cache/src/coalesce_unit/par_coalescer/rsp_spliter_v2.sv -25f6b9e67a54f6bcd0af21bcafdac77f077cfebc419bfcb581ed6a9228f91214 hardware/deps/insitu-cache/src/coalesce_unit/seq_coalescer/seq_coalescer_multi_req_merger.sv -c207ed7ac50d2af303ff7e955fe522ee080183e41e3ec6f8d55a2006cc00c6dc hardware/deps/insitu-cache/src/coalesce_unit/seq_coalescer/seq_coalescer_req_merger.sv -e0df79c260f134531b11c8b6a8d47390283b89dd83cb97fd8355fc8a5ef86f03 hardware/deps/insitu-cache/src/coalesce_unit/seq_coalescer/seq_coalescer_top.sv -4e301e4cf36faf5b5c45364a9d1a19a277ab77ece85b044155dd9f2f47a2c52d hardware/deps/insitu-cache/src/coalesce_unit/wirte_merger/write_through_merger.sv -17bdf4e7d28110ddf6e3d2847001aa63b2ef24be634b481c4492bbd56ecf3ecb hardware/deps/insitu-cache/src/flamingo/flamingo_spatz_cache_ctrl.sv -b23ed2027fa1dc75c6e5dfaf8c745af35e38d74270220930ff03d4a87e454431 hardware/deps/insitu-cache/src/insitu_cache/insitu_cache_core.sv -61f7202ccf3cefbfaf439af682530f397b83db7e88d30ee8bc1d3f0f34ecaefe hardware/deps/insitu-cache/src/insitu_cache/insitu_cache_decoder.sv -2bf77815139b3838a4ed8ec7fee1c1796cfe64ee7a0201c89f7ad8deaa730bce hardware/deps/insitu-cache/src/insitu_cache/insitu_cache_encoder.sv -92b4b3840476d2bf4b0fe7bda1b8043fb0ce50a0461597fc8f1b8c20fd1330ca hardware/deps/insitu-cache/src/insitu_cache/insitu_cache_pkg.sv -c1b3b6a1d11e33bfad18cbf4cf85adf8183f90a9f45ff0c0c3c1eafb0b682488 hardware/deps/insitu-cache/src/insitu_cache/insitu_cache_tcdm_wrapper_partitionable_flushable.sv -5307c2177b04cfa3adce2b81146d8bcee4e53abd89d0555a613c0cec776a4ede hardware/deps/insitu-cache/src/insitu_cache/insitu_cache_tcdm_wrapper.sv -87101497eb0373f51cea90bb7e75832697c815b84d25932cb08170ff23460332 hardware/deps/insitu-cache/src/insitu_cache/insitu_cache_top.sv -eade4dd67b94611c3bfc3a992a7cb344204f6a09776e666d6bb8715a753c5bd4 hardware/deps/insitu-cache/src/utilities/cache_to_axi.sv -044c99c7088ab422b04865417abc3404d335f2cf151d502fe76dc98e11e9cd46 hardware/deps/insitu-cache/src/utilities/decouple_channels_adapter.sv -38439025cf5ccbb4a22b6601abe5db1c20b2bbf2c69b238fe554dc1710d8b8c5 hardware/deps/insitu-cache/src/utilities/decouple_queue_sync.sv -014f5da3cf6eeb3ac0a29e695bf2da655fdb4a11a503d4b86e99cdaf50d05638 hardware/deps/insitu-cache/src/utilities/folded_data_bank.sv -8f3d6864a6c2bee129fa743d1d1e9c7e0fbf1e856021be898ba2b8fb3c45361c hardware/deps/insitu-cache/src/utilities/id_buffer.sv -9eca29b1797d0aa5d8e78a1e8d84fb1efe762d0a46309576a8280910f2218b74 hardware/deps/insitu-cache/src/utilities/pseudo_dual_port_bank.sv -d6c46cd92c945c8525d95c40ebe06507a0fe0d84915db95721e625993387884d hardware/deps/insitu-cache/src/utilities/pseudo_dual_port_fifo.sv -6cda5a806f5948c233dd9ad5311808d8a92fb401b525f1a0899c5238c705ca13 hardware/deps/insitu-cache/src/utilities/pseudo_dual_port_way.sv -a0a2e42cba0e78deafa37c61bfa973e7401b22970e8a279ef4c2813e289e921e hardware/deps/insitu-cache/src/utilities/sram_forwarding_buffer_multi.sv -f06297858718811bc70455c43c0f0495c34226d45d2ea18fa93db2bec58eccbf hardware/deps/insitu-cache/src/utilities/sram_forwarding_buffer.sv -9107a7d66628fdaaf529d3860a28db91756793e8515cd80e7d8ecda7124cc75e hardware/deps/insitu-cache/src/verif/insitu_cache_scoreboard.sv diff --git a/reports/rtl_reference_2026-09-08/dut_watch.log b/reports/rtl_reference_2026-09-08/dut_watch.log deleted file mode 100644 index 8d58304..0000000 --- a/reports/rtl_reference_2026-09-08/dut_watch.log +++ /dev/null @@ -1,132 +0,0 @@ -04:39:19 watch start -04:39:19 OK 4 logs -04:40:04 OK 4 logs -04:40:50 OK 4 logs -04:41:35 OK 4 logs -04:42:20 OK 4 logs -04:43:05 OK 4 logs -04:43:50 OK 4 logs -04:44:35 OK 4 logs -04:45:20 OK 4 logs -04:46:05 OK 4 logs -04:46:50 OK 4 logs -04:47:35 OK 4 logs -04:48:20 OK 4 logs -04:49:05 OK 4 logs -04:49:50 OK 4 logs -04:50:36 OK 4 logs -04:51:21 OK 4 logs -04:52:06 OK 4 logs -04:52:51 OK 4 logs -04:53:36 OK 4 logs -04:54:21 OK 4 logs -04:55:06 OK 4 logs -04:55:51 OK 4 logs -04:56:36 OK 4 logs -04:57:21 OK 4 logs -04:58:06 OK 4 logs -04:58:51 OK 4 logs -04:59:36 OK 4 logs -05:00:22 OK 4 logs -05:01:07 OK 4 logs -05:01:52 OK 4 logs -05:02:37 OK 4 logs -05:03:22 OK 4 logs -05:04:07 OK 4 logs -05:04:52 OK 4 logs -05:05:37 OK 4 logs -05:06:22 OK 4 logs -05:07:07 OK 4 logs -05:07:52 OK 4 logs -05:08:37 OK 4 logs -05:09:22 OK 4 logs -05:10:08 OK 4 logs -05:10:53 OK 4 logs -05:11:38 OK 4 logs -05:12:23 OK 4 logs -05:13:08 OK 4 logs -05:13:53 OK 4 logs -05:14:38 OK 4 logs -05:15:23 OK 4 logs -05:16:08 OK 4 logs -05:16:53 OK 5 logs -05:17:38 OK 5 logs -05:18:23 OK 5 logs -05:19:08 OK 5 logs -05:19:53 OK 5 logs -05:20:39 OK 5 logs -05:21:24 OK 5 logs -05:22:09 OK 5 logs -05:22:54 OK 5 logs -05:23:39 OK 5 logs -05:24:24 OK 5 logs -05:25:09 OK 5 logs -05:25:54 OK 5 logs -05:26:39 OK 5 logs -05:27:24 OK 5 logs -05:28:09 OK 5 logs -05:28:54 OK 5 logs -05:29:39 OK 5 logs -05:30:25 OK 5 logs -05:31:10 OK 5 logs -05:31:55 OK 5 logs -05:32:40 OK 5 logs -05:33:25 OK 5 logs -05:34:10 OK 5 logs -05:34:55 OK 5 logs -05:35:40 OK 5 logs -05:36:25 OK 5 logs -05:37:10 OK 5 logs -05:37:55 OK 5 logs -05:38:40 OK 5 logs -05:39:25 OK 5 logs -05:40:10 OK 5 logs -05:40:56 OK 5 logs -05:41:41 OK 5 logs -05:42:26 OK 5 logs -05:43:11 OK 5 logs -05:43:56 OK 5 logs -05:44:41 OK 5 logs -05:45:26 OK 5 logs -05:46:11 OK 5 logs -05:46:56 OK 5 logs -05:47:41 OK 5 logs -05:48:26 OK 5 logs -05:49:11 OK 5 logs -05:49:56 OK 5 logs -05:50:42 OK 5 logs -05:51:27 OK 5 logs -05:52:12 OK 5 logs -05:52:57 OK 5 logs -05:53:42 OK 5 logs -05:54:27 OK 5 logs -05:55:12 OK 5 logs -05:55:57 OK 5 logs -05:56:42 OK 5 logs -05:57:27 OK 5 logs -05:58:12 OK 5 logs -05:58:57 OK 5 logs -05:59:42 OK 5 logs -06:00:28 OK 5 logs -06:01:13 OK 5 logs -06:01:58 OK 5 logs -06:02:43 OK 5 logs -06:03:28 OK 5 logs -06:04:13 OK 5 logs -06:04:58 OK 5 logs -06:05:43 OK 5 logs -06:06:28 OK 5 logs -06:07:13 OK 5 logs -06:07:58 OK 5 logs -06:08:43 OK 5 logs -06:09:28 OK 5 logs -06:10:14 OK 5 logs -06:10:59 OK 5 logs -06:11:44 OK 5 logs -06:12:29 OK 5 logs -06:13:14 OK 5 logs -06:13:59 OK 5 logs -06:14:44 OK 5 logs -06:15:29 OK 5 logs -06:16:14 OK 5 logs -06:16:59 watch end (no vsim) diff --git a/reports/rtl_reference_2026-09-08/elf_under_test/MANIFEST.md5 b/reports/rtl_reference_2026-09-08/elf_under_test/MANIFEST.md5 deleted file mode 100644 index ae2a5f0..0000000 --- a/reports/rtl_reference_2026-09-08/elf_under_test/MANIFEST.md5 +++ /dev/null @@ -1,5 +0,0 @@ -1a088459f44141767887463d19414940 test-cachepool-bandwidth -dd7a26dfb3a6bde1a0edf6b28c625a1e test-cachepool-byte-enable -071bc973b2955f26ef2b4b01a7a9b4c2 test-cachepool-cache-mix-smoke -328983909d31a0ff3407b942ac18ca6e test-cachepool-cache-test-scalar -a2dc159c6a1b7be8a408e4d95e2c5c0a test-cachepool-cache-test-vector diff --git a/reports/rtl_reference_2026-09-08/summary.tsv b/reports/rtl_reference_2026-09-08/summary.tsv deleted file mode 100644 index 61d8463..0000000 --- a/reports/rtl_reference_2026-09-08/summary.tsv +++ /dev/null @@ -1,6 +0,0 @@ -kernel status eoc_cyc retval kernel_cyc per_load sb_pass sb_fail illegal -bandwidth PASS 33876 0 2058 32 128 0 0 Performance: 1990 elems/1000cyc (31%o utilizat -byte-enable PASS 303288 0 - - 128 0 0 Byte-enable test PASSED -cache-mix-smoke eoc_nonzero_retval 69378 5 - - 128 0 0 [FAIL] cache-mix-smoke: 125 mismatches -cache-test-scalar timeout_cap - - - - 0 0 0 [RUN ] cache-stress -cache-test-vector timeout_cap - - - - 0 0 0 [RUN ] vcache-stress diff --git a/reports/rtl_reference_2026-09-08/verify_dut.sh b/reports/rtl_reference_2026-09-08/verify_dut.sh deleted file mode 100755 index b7b5bda..0000000 --- a/reports/rtl_reference_2026-09-08/verify_dut.sh +++ /dev/null @@ -1,14 +0,0 @@ -#!/bin/bash -# Re-check that the DUT did not change during the batch. -# The hazard: compile.vsim.tcl is a make target whose prerequisites do NOT -# include RTL sources. If anything touches a prerequisite mid-batch, make -# re-runs bender, Bender.local's override takes effect, and the resolved -# source path silently switches from hardware/deps to working_dir. Nothing in -# the vsim logs would show it. -cd /usr/scratch/fenga1/zexifu/manyRVData/ManyRVData_rebase -if sha256sum -c reports/rtl_reference_2026-09-08/dut_tripwire.sha256 --quiet 2>/dev/null; then - echo "DUT UNCHANGED across the batch โ€” every result is from one RTL state." -else - echo "*** DUT CHANGED MID-BATCH โ€” results are not attributable to one RTL state ***" - sha256sum -c reports/rtl_reference_2026-09-08/dut_tripwire.sha256 2>&1 | grep -v ': OK$' -fi diff --git a/reports/rtl_reference_t312_pending/PINNED_STATE.md b/reports/rtl_reference_t312_pending/PINNED_STATE.md deleted file mode 100644 index 321f9ab..0000000 --- a/reports/rtl_reference_t312_pending/PINNED_STATE.md +++ /dev/null @@ -1,21 +0,0 @@ -# T3.1-T3.12 DUT, pinned 2026-09-08 โ€” NO RUN YET - -Pinned **before** any simulation, so drift between the peer's sync and an -approved run is detectable. Nothing has been run against this state. - -The four files under test, verified against the L1-timing session's pins: - -``` -b23ed2027fa1dc75 insitu_cache_core.sv unchanged from the T3.1-T3.15 batch -2bf77815139b3838 insitu_cache_encoder.sv unchanged -c8ab3702c53efb65 insitu_cache_tcdm_wrapper.sv CHANGED (was 5307c217) -f45f898632dd45ed sram_forwarding_buffer.sv CHANGED (was f0629785) -``` - -Both changed files were recovered from the git object store via -`git fsck --dangling`, not hand-edited โ€” see the peer's note about a -hand-revert that had introduced a stray `begin`. - -**Status: awaiting user approval to run `bandwidth` (+ `byte-enable`).** -Use `elf_under_test/` from `reports/rtl_reference_2026-09-08/` so the software -side is identical to the T3.1-T3.15 arm. diff --git a/reports/rtl_reference_t312_pending/dut_tripwire.sha256 b/reports/rtl_reference_t312_pending/dut_tripwire.sha256 deleted file mode 100644 index b6657de..0000000 --- a/reports/rtl_reference_t312_pending/dut_tripwire.sha256 +++ /dev/null @@ -1,31 +0,0 @@ -1203a1440956ab6fcf8c3f8976e89edd649428416ac448d82b8c13437875ceea sim/work/compile.vsim.tcl -d4cf9be82f9770ec17e56bbbf8a82e2cecfbd5b04f02bbb495e561ac837faa2a hardware/deps/insitu-cache/src/cachepool/cachepool_cache_ctrl.sv -cbf220f4643f89dfd484db6e2ee6da772ec8d6581d2a6df5a2a69ba2730b251d hardware/deps/insitu-cache/src/coalesce_unit/par_coalescer/non_coalescer.sv -2b19d084db209bc077c16d3fb5463f1f0041625f833dbd7512a15b06ef579158 hardware/deps/insitu-cache/src/coalesce_unit/par_coalescer/par_coalescer_equal_window.sv -24209b3aeb73769efe59ba5527afd9db2abb024573a66d7eb0c34fc703ab19cd hardware/deps/insitu-cache/src/coalesce_unit/par_coalescer/par_coalescer_extend_window.sv -ba81e0acf3ad966d72024709e02253642c76bb0dfaad99b114f4d1985432bc7b hardware/deps/insitu-cache/src/coalesce_unit/par_coalescer/par_coalescer_top.sv -0b316eeba6ca5dec17f9f5fe9fec15e235fde0794911de7c67a3e62125ca303b hardware/deps/insitu-cache/src/coalesce_unit/par_coalescer/req_coalescer_v2.sv -52905bb68feaee386b1abd2e6efcd08a83a567054df8a95dd957b7884ea7f150 hardware/deps/insitu-cache/src/coalesce_unit/par_coalescer/rsp_spliter_v2.sv -25f6b9e67a54f6bcd0af21bcafdac77f077cfebc419bfcb581ed6a9228f91214 hardware/deps/insitu-cache/src/coalesce_unit/seq_coalescer/seq_coalescer_multi_req_merger.sv -c207ed7ac50d2af303ff7e955fe522ee080183e41e3ec6f8d55a2006cc00c6dc hardware/deps/insitu-cache/src/coalesce_unit/seq_coalescer/seq_coalescer_req_merger.sv -e0df79c260f134531b11c8b6a8d47390283b89dd83cb97fd8355fc8a5ef86f03 hardware/deps/insitu-cache/src/coalesce_unit/seq_coalescer/seq_coalescer_top.sv -4e301e4cf36faf5b5c45364a9d1a19a277ab77ece85b044155dd9f2f47a2c52d hardware/deps/insitu-cache/src/coalesce_unit/wirte_merger/write_through_merger.sv -17bdf4e7d28110ddf6e3d2847001aa63b2ef24be634b481c4492bbd56ecf3ecb hardware/deps/insitu-cache/src/flamingo/flamingo_spatz_cache_ctrl.sv -b23ed2027fa1dc75c6e5dfaf8c745af35e38d74270220930ff03d4a87e454431 hardware/deps/insitu-cache/src/insitu_cache/insitu_cache_core.sv -61f7202ccf3cefbfaf439af682530f397b83db7e88d30ee8bc1d3f0f34ecaefe hardware/deps/insitu-cache/src/insitu_cache/insitu_cache_decoder.sv -2bf77815139b3838a4ed8ec7fee1c1796cfe64ee7a0201c89f7ad8deaa730bce hardware/deps/insitu-cache/src/insitu_cache/insitu_cache_encoder.sv -92b4b3840476d2bf4b0fe7bda1b8043fb0ce50a0461597fc8f1b8c20fd1330ca hardware/deps/insitu-cache/src/insitu_cache/insitu_cache_pkg.sv -c1b3b6a1d11e33bfad18cbf4cf85adf8183f90a9f45ff0c0c3c1eafb0b682488 hardware/deps/insitu-cache/src/insitu_cache/insitu_cache_tcdm_wrapper_partitionable_flushable.sv -c8ab3702c53efb654a18c309059f9e5807aed6f805b0d796040da55faec18c2f hardware/deps/insitu-cache/src/insitu_cache/insitu_cache_tcdm_wrapper.sv -87101497eb0373f51cea90bb7e75832697c815b84d25932cb08170ff23460332 hardware/deps/insitu-cache/src/insitu_cache/insitu_cache_top.sv -eade4dd67b94611c3bfc3a992a7cb344204f6a09776e666d6bb8715a753c5bd4 hardware/deps/insitu-cache/src/utilities/cache_to_axi.sv -044c99c7088ab422b04865417abc3404d335f2cf151d502fe76dc98e11e9cd46 hardware/deps/insitu-cache/src/utilities/decouple_channels_adapter.sv -38439025cf5ccbb4a22b6601abe5db1c20b2bbf2c69b238fe554dc1710d8b8c5 hardware/deps/insitu-cache/src/utilities/decouple_queue_sync.sv -014f5da3cf6eeb3ac0a29e695bf2da655fdb4a11a503d4b86e99cdaf50d05638 hardware/deps/insitu-cache/src/utilities/folded_data_bank.sv -8f3d6864a6c2bee129fa743d1d1e9c7e0fbf1e856021be898ba2b8fb3c45361c hardware/deps/insitu-cache/src/utilities/id_buffer.sv -9eca29b1797d0aa5d8e78a1e8d84fb1efe762d0a46309576a8280910f2218b74 hardware/deps/insitu-cache/src/utilities/pseudo_dual_port_bank.sv -d6c46cd92c945c8525d95c40ebe06507a0fe0d84915db95721e625993387884d hardware/deps/insitu-cache/src/utilities/pseudo_dual_port_fifo.sv -6cda5a806f5948c233dd9ad5311808d8a92fb401b525f1a0899c5238c705ca13 hardware/deps/insitu-cache/src/utilities/pseudo_dual_port_way.sv -a0a2e42cba0e78deafa37c61bfa973e7401b22970e8a279ef4c2813e289e921e hardware/deps/insitu-cache/src/utilities/sram_forwarding_buffer_multi.sv -f45f898632dd45eda3cb80e739c48313a946ace2a104eb5b5da125a62613e191 hardware/deps/insitu-cache/src/utilities/sram_forwarding_buffer.sv -9107a7d66628fdaaf529d3860a28db91756793e8515cd80e7d8ecda7124cc75e hardware/deps/insitu-cache/src/verif/insitu_cache_scoreboard.sv From d5cfab6a07bb38e69c657d99eca9b9ad17a62f45 Mon Sep 17 00:00:00 2001 From: Zexin Fu Date: Fri, 16 Oct 2026 10:29:59 +0200 Subject: [PATCH 45/48] rlc: generate the data headers with make gen-data instead of tracking them Rename the generator to script/gen_data.py and the configs to script/data_.json, so gen-data picks them up like the other kernels. Add configs for the headers that had none and drop the two unused legacy headers (1_1350_1000, 1_2044_100). --- software/rlc/CMakeLists.txt | 15 +- .../data/.gitignore | 4 +- .../data/data_12_1350_24.h | 99 - .../data/data_16_1350_24.h | 99 - .../data/data_1_1350_10.h | 71 - .../data/data_1_1350_100.h | 251 -- .../data/data_1_1350_1000.h | 2036 ---------------- .../data/data_1_1350_100_p1c1.h | 251 -- .../data/data_1_1350_100_p1c3.h | 251 -- .../data/data_1_1350_300.h | 651 ------ .../data/data_1_1350_4.h | 59 - .../data/data_1_2044_100.h | 240 -- .../data/data_24_1350_24.h | 99 - .../data/data_256_800_300.h | 644 ------ .../data/data_32_1350_24.h | 99 - .../data/data_48_1350_24.h | 99 - .../data/data_48_1350_8.h | 67 - .../data/data_48_800_1000.h | 2051 ----------------- .../data/data_48_800_300.h | 651 ------ .../data/data_8_1350_24.h | 99 - .../data/data_8_1350_8.h | 67 - ...g_12_1350_24.json => data_12_1350_24.json} | 0 ...g_16_1350_24.json => data_16_1350_24.json} | 0 .../script/data_1_1350_10.json | 32 + .../script/data_1_1350_100.json | 32 + ...00_p1c1.json => data_1_1350_100_p1c1.json} | 0 .../script/data_1_1350_100_p1c3.json | 32 + ...92.json => data_1_1350_1157_p64_c192.json} | 0 .../{pdcp_pkg.json => data_1_1350_300.json} | 11 - ...p_pkg_1_1350_4.json => data_1_1350_4.json} | 0 ...c48.json => data_1_1350_9256_p16_c48.json} | 0 ...json => data_1_1350_9256_p16_c48_l64.json} | 0 ...p2_c2.json => data_1_1350_9256_p2_c2.json} | 0 ...92.json => data_1_1350_9256_p64_c192.json} | 0 ...son => data_1_1350_9256_p64_c192_l64.json} | 0 ...g_24_1350_24.json => data_24_1350_24.json} | 0 .../script/data_256_800_300.json | 12 + ...g_32_1350_24.json => data_32_1350_24.json} | 0 ....json => data_4800_800_15704_p16_c48.json} | 0 ...c2.json => data_4800_800_15704_p2_c2.json} | 0 ... => data_4800_800_15704_p48_c144_l64.json} | 0 ...json => data_4800_800_15704_p64_c192.json} | 0 ... => data_4800_800_15704_p64_c192_l64.json} | 0 ....json => data_4800_800_1963_p64_c192.json} | 0 ...g_48_1350_24.json => data_48_1350_24.json} | 0 ...pkg_48_1350_8.json => data_48_1350_8.json} | 0 ...48_800_1000.json => data_48_800_1000.json} | 0 ...48.json => data_48_800_19528_p16_c48.json} | 0 ...2_c2.json => data_48_800_19528_p2_c2.json} | 0 ...on => data_48_800_19528_p48_c144_l64.json} | 0 ...2.json => data_48_800_19528_p64_c192.json} | 0 ...g_48_800_300.json => data_48_800_300.json} | 0 ...92.json => data_48_800_4882_p64_c192.json} | 0 ...pkg_8_1350_24.json => data_8_1350_24.json} | 0 ...p_pkg_8_1350_8.json => data_8_1350_8.json} | 0 .../{generate_pdcp_pkg.py => gen_data.py} | 14 +- .../script/pdcp_pkg_256_800_300.json | 10 - 57 files changed, 118 insertions(+), 7928 deletions(-) delete mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/data/data_12_1350_24.h delete mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/data/data_16_1350_24.h delete mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/data/data_1_1350_10.h delete mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/data/data_1_1350_100.h delete mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/data/data_1_1350_1000.h delete mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/data/data_1_1350_100_p1c1.h delete mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/data/data_1_1350_100_p1c3.h delete mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/data/data_1_1350_300.h delete mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/data/data_1_1350_4.h delete mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/data/data_1_2044_100.h delete mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/data/data_24_1350_24.h delete mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/data/data_256_800_300.h delete mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/data/data_32_1350_24.h delete mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/data/data_48_1350_24.h delete mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/data/data_48_1350_8.h delete mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/data/data_48_800_1000.h delete mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/data/data_48_800_300.h delete mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/data/data_8_1350_24.h delete mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/data/data_8_1350_8.h rename software/rlc/multi_producer_single_consumer_double_linked_list/script/{pdcp_pkg_12_1350_24.json => data_12_1350_24.json} (100%) rename software/rlc/multi_producer_single_consumer_double_linked_list/script/{pdcp_pkg_16_1350_24.json => data_16_1350_24.json} (100%) create mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/script/data_1_1350_10.json create mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/script/data_1_1350_100.json rename software/rlc/multi_producer_single_consumer_double_linked_list/script/{pdcp_pkg_1_1350_100_p1c1.json => data_1_1350_100_p1c1.json} (100%) create mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/script/data_1_1350_100_p1c3.json rename software/rlc/multi_producer_single_consumer_double_linked_list/script/{pdcp_pkg_1_1350_1157_p64_c192.json => data_1_1350_1157_p64_c192.json} (100%) rename software/rlc/multi_producer_single_consumer_double_linked_list/script/{pdcp_pkg.json => data_1_1350_300.json} (77%) rename software/rlc/multi_producer_single_consumer_double_linked_list/script/{pdcp_pkg_1_1350_4.json => data_1_1350_4.json} (100%) rename software/rlc/multi_producer_single_consumer_double_linked_list/script/{pdcp_pkg_1_1350_9256_p16_c48.json => data_1_1350_9256_p16_c48.json} (100%) rename software/rlc/multi_producer_single_consumer_double_linked_list/script/{pdcp_pkg_1_1350_9256_p16_c48_l64.json => data_1_1350_9256_p16_c48_l64.json} (100%) rename software/rlc/multi_producer_single_consumer_double_linked_list/script/{pdcp_pkg_1_1350_9256_p2_c2.json => data_1_1350_9256_p2_c2.json} (100%) rename software/rlc/multi_producer_single_consumer_double_linked_list/script/{pdcp_pkg_1_1350_9256_p64_c192.json => data_1_1350_9256_p64_c192.json} (100%) rename software/rlc/multi_producer_single_consumer_double_linked_list/script/{pdcp_pkg_1_1350_9256_p64_c192_l64.json => data_1_1350_9256_p64_c192_l64.json} (100%) rename software/rlc/multi_producer_single_consumer_double_linked_list/script/{pdcp_pkg_24_1350_24.json => data_24_1350_24.json} (100%) create mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/script/data_256_800_300.json rename software/rlc/multi_producer_single_consumer_double_linked_list/script/{pdcp_pkg_32_1350_24.json => data_32_1350_24.json} (100%) rename software/rlc/multi_producer_single_consumer_double_linked_list/script/{pdcp_pkg_4800_800_15704_p16_c48.json => data_4800_800_15704_p16_c48.json} (100%) rename software/rlc/multi_producer_single_consumer_double_linked_list/script/{pdcp_pkg_4800_800_15704_p2_c2.json => data_4800_800_15704_p2_c2.json} (100%) rename software/rlc/multi_producer_single_consumer_double_linked_list/script/{pdcp_pkg_4800_800_15704_p48_c144_l64.json => data_4800_800_15704_p48_c144_l64.json} (100%) rename software/rlc/multi_producer_single_consumer_double_linked_list/script/{pdcp_pkg_4800_800_15704_p64_c192.json => data_4800_800_15704_p64_c192.json} (100%) rename software/rlc/multi_producer_single_consumer_double_linked_list/script/{pdcp_pkg_4800_800_15704_p64_c192_l64.json => data_4800_800_15704_p64_c192_l64.json} (100%) rename software/rlc/multi_producer_single_consumer_double_linked_list/script/{pdcp_pkg_4800_800_1963_p64_c192.json => data_4800_800_1963_p64_c192.json} (100%) rename software/rlc/multi_producer_single_consumer_double_linked_list/script/{pdcp_pkg_48_1350_24.json => data_48_1350_24.json} (100%) rename software/rlc/multi_producer_single_consumer_double_linked_list/script/{pdcp_pkg_48_1350_8.json => data_48_1350_8.json} (100%) rename software/rlc/multi_producer_single_consumer_double_linked_list/script/{pdcp_pkg_48_800_1000.json => data_48_800_1000.json} (100%) rename software/rlc/multi_producer_single_consumer_double_linked_list/script/{pdcp_pkg_48_800_19528_p16_c48.json => data_48_800_19528_p16_c48.json} (100%) rename software/rlc/multi_producer_single_consumer_double_linked_list/script/{pdcp_pkg_48_800_19528_p2_c2.json => data_48_800_19528_p2_c2.json} (100%) rename software/rlc/multi_producer_single_consumer_double_linked_list/script/{pdcp_pkg_48_800_19528_p48_c144_l64.json => data_48_800_19528_p48_c144_l64.json} (100%) rename software/rlc/multi_producer_single_consumer_double_linked_list/script/{pdcp_pkg_48_800_19528_p64_c192.json => data_48_800_19528_p64_c192.json} (100%) rename software/rlc/multi_producer_single_consumer_double_linked_list/script/{pdcp_pkg_48_800_300.json => data_48_800_300.json} (100%) rename software/rlc/multi_producer_single_consumer_double_linked_list/script/{pdcp_pkg_48_800_4882_p64_c192.json => data_48_800_4882_p64_c192.json} (100%) rename software/rlc/multi_producer_single_consumer_double_linked_list/script/{pdcp_pkg_8_1350_24.json => data_8_1350_24.json} (100%) rename software/rlc/multi_producer_single_consumer_double_linked_list/script/{pdcp_pkg_8_1350_8.json => data_8_1350_8.json} (100%) rename software/rlc/multi_producer_single_consumer_double_linked_list/script/{generate_pdcp_pkg.py => gen_data.py} (95%) delete mode 100644 software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_256_800_300.json diff --git a/software/rlc/CMakeLists.txt b/software/rlc/CMakeLists.txt index b3ba532..cff7567 100644 --- a/software/rlc/CMakeLists.txt +++ b/software/rlc/CMakeLists.txt @@ -103,22 +103,10 @@ add_spatz_test_rlc_probe("_P2_C2_am_G8192" multi_producer_single_consumer_double # the target suffix. The node pool is sized to the packet count: nodes are only freed by ACKs, # which come two per entity, so with many entities most nodes stay live to the end, and an # exhausted pool drops the packet whose descriptor the producer already took. -# The data header is generated from script/pdcp_pkg____.json at build time (it is -# 10-200 MB, too large to keep in git). -set(RLC_DIR ${CMAKE_CURRENT_SOURCE_DIR}/multi_producer_single_consumer_double_linked_list) +# The data header comes from script/data____.json (`make gen-data`). # `variant` is appended to the target name and says which extra defines (ARGN) it carries. macro(add_spatz_test_rlc_full layout variant name file param1 param2 param3) string(TOLOWER ${layout} layout_lc) - set(rlc_cfg ${param1}_${param2}_${param3}_${layout_lc}) - if(NOT TARGET rlc_data_${rlc_cfg}) - add_custom_command( - OUTPUT ${RLC_DIR}/data/data_${rlc_cfg}.h - COMMAND python3 ${RLC_DIR}/script/generate_pdcp_pkg.py ${RLC_DIR}/script/pdcp_pkg_${rlc_cfg}.json - -o ${RLC_DIR}/data/data_${rlc_cfg}.h - DEPENDS ${RLC_DIR}/script/pdcp_pkg_${rlc_cfg}.json ${RLC_DIR}/script/generate_pdcp_pkg.py - COMMENT "Generating RLC data header data_${rlc_cfg}.h") - add_custom_target(rlc_data_${rlc_cfg} DEPENDS ${RLC_DIR}/data/data_${rlc_cfg}.h) - endif() foreach(probe 0 1) if(${probe}) set(target_name ${name}_M${param1}_N${param2}_K${param3}_${layout}${variant}_probe) @@ -130,7 +118,6 @@ macro(add_spatz_test_rlc_full layout variant name file param1 param2 param3) target_compile_definitions(test-${SNITCH_TEST_PREFIX}${target_name} PUBLIC DATAHEADER="data/data_${param1}_${param2}_${param3}_${layout_lc}.h" MM_POOL_PAGES=${param3} RLC_PROBE=${probe} ${ARGN}) - add_dependencies(test-${SNITCH_TEST_PREFIX}${target_name} rlc_data_${rlc_cfg}) endforeach() endmacro() add_spatz_test_rlc_full(P64_C192 "" multi_producer_single_consumer_double_linked_list multi_producer_single_consumer_double_linked_list/main.c 1 1350 1157) diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/data/.gitignore b/software/rlc/multi_producer_single_consumer_double_linked_list/data/.gitignore index ea577c8..b14ab3f 100644 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/data/.gitignore +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/data/.gitignore @@ -1,2 +1,2 @@ -# Generated at build time from ../script/pdcp_pkg_*_p

_c.json (see software/tests/CMakeLists.txt) -data_*_p*_c*.h +# Generated data headers, reproduced by `make gen-data` from ../script/data_.json +*.h diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/data/data_12_1350_24.h b/software/rlc/multi_producer_single_consumer_double_linked_list/data/data_12_1350_24.h deleted file mode 100644 index e852b77..0000000 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/data/data_12_1350_24.h +++ /dev/null @@ -1,99 +0,0 @@ - -// Copyright 2025 ETH Zurich and University of Bologna. -// -// SPDX-License-Identifier: Apache-2.0 -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -// Author: Zexin Fu - -#ifndef PDCP_PKG_H -#define PDCP_PKG_H - -#include - -typedef struct { - int user_id; - unsigned int src_addr; - unsigned int tgt_addr; - unsigned int pkg_length; -} pdcp_pkg_t; - -#define NUM_SRC_SLOTS 12336 -#define PDU_SIZE 1360 -#define PDU_STRIDE 1360 -#define NUM_PKGS 24 -#define ACTIVE_USER_NUMBER 12 - -#define NUM_PRODUCER_CORES 2 -static const unsigned int producer_core_ids[NUM_PRODUCER_CORES] = {0, 1}; -#define NUM_CONSUMER_CORES 2 -static const unsigned int consumer_core_ids[NUM_CONSUMER_CORES] = {2, 3}; -#define NUM_RLC_KERNEL_CORES (NUM_PRODUCER_CORES + NUM_CONSUMER_CORES) -static const unsigned int rlc_kernel_core_ids[NUM_RLC_KERNEL_CORES] = {0, 1, 2, 3}; - -static const pdcp_pkg_t __attribute__((section(".pdcp_info"), used)) pdcp_pkgs[NUM_PKGS] = { - { 8, 0xA0D965C0, 0xB0D965C0, 1360 }, - { 3, 0xA025DA00, 0xB025DA00, 1360 }, - { 11, 0xA0087CD0, 0xB0087CD0, 1360 }, - { 10, 0xA0FC1D90, 0xB0FC1D90, 1360 }, - { 11, 0xA05D8220, 0xB05D8220, 1360 }, - { 8, 0xA05341C0, 0xB05341C0, 1360 }, - { 6, 0xA04BE3D0, 0xB04BE3D0, 1360 }, - { 3, 0xA02F7060, 0xB02F7060, 1360 }, - { 7, 0xA0FA64A0, 0xB0FA64A0, 1360 }, - { 9, 0xA022D7B0, 0xB022D7B0, 1360 }, - { 4, 0xA0E613B0, 0xB0E613B0, 1360 }, - { 0, 0xA0FBD330, 0xB0FBD330, 1360 }, - { 2, 0xA0B96B30, 0xB0B96B30, 1360 }, - { 11, 0xA01D8D00, 0xB01D8D00, 1360 }, - { 6, 0xA0C8C120, 0xB0C8C120, 1360 }, - { 5, 0xA08F7000, 0xB08F7000, 1360 }, - { 4, 0xA00ACA80, 0xB00ACA80, 1360 }, - { 2, 0xA00A2080, 0xB00A2080, 1360 }, - { 3, 0xA01FDAB0, 0xB01FDAB0, 1360 }, - { 5, 0xA04A5560, 0xB04A5560, 1360 }, - { 1, 0xA04F15F0, 0xB04F15F0, 1360 }, - { 1, 0xA0ABCE30, 0xB0ABCE30, 1360 }, - { 6, 0xA0CCAD30, 0xB0CCAD30, 1360 }, - { 1, 0xA00901A0, 0xB00901A0, 1360 }, -}; - -static const uint8_t __attribute__((section(".pdcp_src"), used)) pdcp_src_data[NUM_SRC_SLOTS][PDU_STRIDE] = { - [409] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF, 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0xDF, 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 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a/software/rlc/multi_producer_single_consumer_double_linked_list/data/data_16_1350_24.h b/software/rlc/multi_producer_single_consumer_double_linked_list/data/data_16_1350_24.h deleted file mode 100644 index ee14424..0000000 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/data/data_16_1350_24.h +++ /dev/null @@ -1,99 +0,0 @@ - -// Copyright 2025 ETH Zurich and University of Bologna. -// -// SPDX-License-Identifier: Apache-2.0 -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -// Author: Zexin Fu - -#ifndef PDCP_PKG_H -#define PDCP_PKG_H - -#include - -typedef struct { - int user_id; - unsigned int src_addr; - unsigned int tgt_addr; - unsigned int pkg_length; -} pdcp_pkg_t; - -#define NUM_SRC_SLOTS 12336 -#define PDU_SIZE 1360 -#define PDU_STRIDE 1360 -#define NUM_PKGS 24 -#define ACTIVE_USER_NUMBER 16 - -#define NUM_PRODUCER_CORES 2 -static const unsigned int producer_core_ids[NUM_PRODUCER_CORES] = {0, 1}; -#define NUM_CONSUMER_CORES 2 -static const unsigned int consumer_core_ids[NUM_CONSUMER_CORES] = {2, 3}; -#define NUM_RLC_KERNEL_CORES (NUM_PRODUCER_CORES + NUM_CONSUMER_CORES) -static const unsigned int rlc_kernel_core_ids[NUM_RLC_KERNEL_CORES] = {0, 1, 2, 3}; - -static const pdcp_pkg_t __attribute__((section(".pdcp_info"), used)) pdcp_pkgs[NUM_PKGS] = { - { 6, 0xA0D965C0, 0xB0D965C0, 1360 }, - { 13, 0xA025DA00, 0xB025DA00, 1360 }, - { 7, 0xA0087CD0, 0xB0087CD0, 1360 }, - { 14, 0xA0FC1D90, 0xB0FC1D90, 1360 }, - { 8, 0xA05D8220, 0xB05D8220, 1360 }, - { 0, 0xA05341C0, 0xB05341C0, 1360 }, - { 5, 0xA04BE3D0, 0xB04BE3D0, 1360 }, - { 13, 0xA02F7060, 0xB02F7060, 1360 }, - { 10, 0xA0FA64A0, 0xB0FA64A0, 1360 }, - { 8, 0xA022D7B0, 0xB022D7B0, 1360 }, - { 4, 0xA0E613B0, 0xB0E613B0, 1360 }, - { 6, 0xA0FBD330, 0xB0FBD330, 1360 }, - { 10, 0xA0B96B30, 0xB0B96B30, 1360 }, - { 3, 0xA01D8D00, 0xB01D8D00, 1360 }, - { 2, 0xA0C8C120, 0xB0C8C120, 1360 }, - { 12, 0xA08F7000, 0xB08F7000, 1360 }, - { 3, 0xA00ACA80, 0xB00ACA80, 1360 }, - { 11, 0xA00A2080, 0xB00A2080, 1360 }, - { 11, 0xA01FDAB0, 0xB01FDAB0, 1360 }, - { 8, 0xA04A5560, 0xB04A5560, 1360 }, - { 1, 0xA04F15F0, 0xB04F15F0, 1360 }, - { 14, 0xA0ABCE30, 0xB0ABCE30, 1360 }, - { 3, 0xA0CCAD30, 0xB0CCAD30, 1360 }, - { 12, 0xA00901A0, 0xB00901A0, 1360 }, -}; - -static const uint8_t __attribute__((section(".pdcp_src"), used)) pdcp_src_data[NUM_SRC_SLOTS][PDU_STRIDE] = { - [409] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, 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b/software/rlc/multi_producer_single_consumer_double_linked_list/data/data_1_1350_10.h deleted file mode 100644 index 2c2de1f..0000000 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/data/data_1_1350_10.h +++ /dev/null @@ -1,71 +0,0 @@ - -// Copyright 2025 ETH Zurich and University of Bologna. -// -// SPDX-License-Identifier: Apache-2.0 -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -// Author: Zexin Fu - -#ifndef PDCP_PKG_H -#define PDCP_PKG_H - -#include - -typedef struct { - int user_id; - unsigned int src_addr; - unsigned int tgt_addr; - unsigned int pkg_length; -} pdcp_pkg_t; - -#define NUM_SRC_SLOTS 12336 -#define PDU_SIZE 1360 -#define PDU_STRIDE 1360 -#define NUM_PKGS 10 -#define ACTIVE_USER_NUMBER 1 - -#define NUM_PRODUCER_CORES 2 -static const unsigned int producer_core_ids[NUM_PRODUCER_CORES] = {0, 1}; -#define NUM_CONSUMER_CORES 2 -static const unsigned int consumer_core_ids[NUM_CONSUMER_CORES] = {2, 3}; -#define NUM_RLC_KERNEL_CORES (NUM_PRODUCER_CORES + NUM_CONSUMER_CORES) -static const unsigned int rlc_kernel_core_ids[NUM_RLC_KERNEL_CORES] = {0, 1, 2, 3}; - -static const pdcp_pkg_t __attribute__((section(".pdcp_info"), used)) pdcp_pkgs[NUM_PKGS] = { - { 0, 0xA0D965C0, 0xB0D965C0, 1360 }, - { 0, 0xA025DA00, 0xB025DA00, 1360 }, - { 0, 0xA0087CD0, 0xB0087CD0, 1360 }, - { 0, 0xA0FC1D90, 0xB0FC1D90, 1360 }, - { 0, 0xA05D8220, 0xB05D8220, 1360 }, - { 0, 0xA05341C0, 0xB05341C0, 1360 }, - { 0, 0xA04BE3D0, 0xB04BE3D0, 1360 }, - { 0, 0xA02F7060, 0xB02F7060, 1360 }, - { 0, 0xA0FA64A0, 0xB0FA64A0, 1360 }, - { 0, 0xA022D7B0, 0xB022D7B0, 1360 }, -}; - -static const uint8_t __attribute__((section(".pdcp_src"), used)) pdcp_src_data[NUM_SRC_SLOTS][PDU_STRIDE] = { - [409] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF, 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0xDF, 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 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0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF, 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0xDF, 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 0x5F, 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F, 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F, 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF, 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0xDF, 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 0x5F, 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F, 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F, 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF, 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0xDF, 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 0x5F, 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F, 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F, 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF, 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0xDF, 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 0x5F, 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F, 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F, 0x90, 0x91, 0x92, 0x93, 0x94, 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0x8B, 0x8C, 0x8D, 0x8E, 0x8F, 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA }, -}; - -#endif // PDCP_PKG_H diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/data/data_1_1350_100.h b/software/rlc/multi_producer_single_consumer_double_linked_list/data/data_1_1350_100.h deleted file mode 100644 index bf1a71a..0000000 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/data/data_1_1350_100.h +++ /dev/null @@ -1,251 +0,0 @@ - -// Copyright 2025 ETH Zurich and University of Bologna. -// -// SPDX-License-Identifier: Apache-2.0 -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -// Author: Zexin Fu - -#ifndef PDCP_PKG_H -#define PDCP_PKG_H - -#include - -typedef struct { - int user_id; - unsigned int src_addr; - unsigned int tgt_addr; - unsigned int pkg_length; -} pdcp_pkg_t; - -#define NUM_SRC_SLOTS 12336 -#define PDU_SIZE 1360 -#define PDU_STRIDE 1360 -#define NUM_PKGS 100 -#define ACTIVE_USER_NUMBER 1 - -#define NUM_PRODUCER_CORES 2 -static const unsigned int producer_core_ids[NUM_PRODUCER_CORES] = {0, 1}; -#define NUM_CONSUMER_CORES 2 -static const unsigned int consumer_core_ids[NUM_CONSUMER_CORES] = {2, 3}; -#define NUM_RLC_KERNEL_CORES (NUM_PRODUCER_CORES + NUM_CONSUMER_CORES) -static const unsigned int rlc_kernel_core_ids[NUM_RLC_KERNEL_CORES] = {0, 1, 2, 3}; - -static const pdcp_pkg_t __attribute__((section(".pdcp_info"), used)) pdcp_pkgs[NUM_PKGS] = { - { 0, 0xA0D965C0, 0xB0D965C0, 1360 }, - { 0, 0xA025DA00, 0xB025DA00, 1360 }, - { 0, 0xA0087CD0, 0xB0087CD0, 1360 }, - { 0, 0xA0FC1D90, 0xB0FC1D90, 1360 }, - { 0, 0xA05D8220, 0xB05D8220, 1360 }, - { 0, 0xA05341C0, 0xB05341C0, 1360 }, - { 0, 0xA04BE3D0, 0xB04BE3D0, 1360 }, - { 0, 0xA02F7060, 0xB02F7060, 1360 }, - { 0, 0xA0FA64A0, 0xB0FA64A0, 1360 }, - { 0, 0xA022D7B0, 0xB022D7B0, 1360 }, - { 0, 0xA0E613B0, 0xB0E613B0, 1360 }, - { 0, 0xA0FBD330, 0xB0FBD330, 1360 }, - { 0, 0xA0B96B30, 0xB0B96B30, 1360 }, - { 0, 0xA01D8D00, 0xB01D8D00, 1360 }, - { 0, 0xA0C8C120, 0xB0C8C120, 1360 }, - { 0, 0xA08F7000, 0xB08F7000, 1360 }, - { 0, 0xA00ACA80, 0xB00ACA80, 1360 }, - { 0, 0xA00A2080, 0xB00A2080, 1360 }, - { 0, 0xA01FDAB0, 0xB01FDAB0, 1360 }, - { 0, 0xA04A5560, 0xB04A5560, 1360 }, - { 0, 0xA04F15F0, 0xB04F15F0, 1360 }, - { 0, 0xA0ABCE30, 0xB0ABCE30, 1360 }, - { 0, 0xA0CCAD30, 0xB0CCAD30, 1360 }, - { 0, 0xA00901A0, 0xB00901A0, 1360 }, - { 0, 0xA0BED070, 0xB0BED070, 1360 }, - { 0, 0xA04396D0, 0xB04396D0, 1360 }, - { 0, 0xA0F370F0, 0xB0F370F0, 1360 }, - { 0, 0xA0DCF230, 0xB0DCF230, 1360 }, - { 0, 0xA0EE70A0, 0xB0EE70A0, 1360 }, - { 0, 0xA0B94600, 0xB0B94600, 1360 }, - { 0, 0xA08EA0D0, 0xB08EA0D0, 1360 }, - { 0, 0xA04AEF70, 0xB04AEF70, 1360 }, - { 0, 0xA098B6B0, 0xB098B6B0, 1360 }, - { 0, 0xA0C856E0, 0xB0C856E0, 1360 }, - { 0, 0xA05E9110, 0xB05E9110, 1360 }, - { 0, 0xA0023320, 0xB0023320, 1360 }, - { 0, 0xA0364430, 0xB0364430, 1360 }, - { 0, 0xA0ED5C60, 0xB0ED5C60, 1360 }, - { 0, 0xA08FAFC0, 0xB08FAFC0, 1360 }, - { 0, 0xA073ABE0, 0xB073ABE0, 1360 }, - { 0, 0xA05E7680, 0xB05E7680, 1360 }, - { 0, 0xA034DAF0, 0xB034DAF0, 1360 }, - { 0, 0xA0493130, 0xB0493130, 1360 }, - { 0, 0xA0726D20, 0xB0726D20, 1360 }, - { 0, 0xA022BD20, 0xB022BD20, 1360 }, - { 0, 0xA01F85B0, 0xB01F85B0, 1360 }, - { 0, 0xA0812900, 0xB0812900, 1360 }, - { 0, 0xA020DF00, 0xB020DF00, 1360 }, - { 0, 0xA07A0AD0, 0xB07A0AD0, 1360 }, - { 0, 0xA074EFF0, 0xB074EFF0, 1360 }, - { 0, 0xA0CD41F0, 0xB0CD41F0, 1360 }, - { 0, 0xA059EB10, 0xB059EB10, 1360 }, - { 0, 0xA00EC130, 0xB00EC130, 1360 }, - { 0, 0xA0F816F0, 0xB0F816F0, 1360 }, - { 0, 0xA09C3330, 0xB09C3330, 1360 }, - { 0, 0xA0B64E50, 0xB0B64E50, 1360 }, - { 0, 0xA02A7010, 0xB02A7010, 1360 }, - { 0, 0xA080AED0, 0xB080AED0, 1360 }, - { 0, 0xA01ACA70, 0xB01ACA70, 1360 }, - { 0, 0xA0BBAE40, 0xB0BBAE40, 1360 }, - { 0, 0xA063ABF0, 0xB063ABF0, 1360 }, - { 0, 0xA0D5B970, 0xB0D5B970, 1360 }, - { 0, 0xA0D24790, 0xB0D24790, 1360 }, - { 0, 0xA07AF490, 0xB07AF490, 1360 }, - { 0, 0xA0C44AF0, 0xB0C44AF0, 1360 }, - { 0, 0xA0415E60, 0xB0415E60, 1360 }, - { 0, 0xA0EF8A30, 0xB0EF8A30, 1360 }, - { 0, 0xA017A2F0, 0xB017A2F0, 1360 }, - { 0, 0xA00F9060, 0xB00F9060, 1360 }, - { 0, 0xA0E0D3A0, 0xB0E0D3A0, 1360 }, - { 0, 0xA04D7790, 0xB04D7790, 1360 }, - { 0, 0xA0626290, 0xB0626290, 1360 }, - { 0, 0xA01B1F70, 0xB01B1F70, 1360 }, - { 0, 0xA04F25E0, 0xB04F25E0, 1360 }, - { 0, 0xA02252E0, 0xB02252E0, 1360 }, - { 0, 0xA08138F0, 0xB08138F0, 1360 }, - { 0, 0xA05E8120, 0xB05E8120, 1360 }, - { 0, 0xA09A2540, 0xB09A2540, 1360 }, - { 0, 0xA0D821B0, 0xB0D821B0, 1360 }, - { 0, 0xA07C08D0, 0xB07C08D0, 1360 }, - { 0, 0xA0374880, 0xB0374880, 1360 }, - { 0, 0xA07DDC50, 0xB07DDC50, 1360 }, - { 0, 0xA078C6C0, 0xB078C6C0, 1360 }, - { 0, 0xA0473880, 0xB0473880, 1360 }, - { 0, 0xA0E3DB40, 0xB0E3DB40, 1360 }, - { 0, 0xA05AC4E0, 0xB05AC4E0, 1360 }, - { 0, 0xA0EE9B20, 0xB0EE9B20, 1360 }, - { 0, 0xA0E866B0, 0xB0E866B0, 1360 }, - { 0, 0xA0DC52D0, 0xB0DC52D0, 1360 }, - { 0, 0xA0184250, 0xB0184250, 1360 }, - { 0, 0xA0CF1AC0, 0xB0CF1AC0, 1360 }, - { 0, 0xA0D7E1F0, 0xB0D7E1F0, 1360 }, - { 0, 0xA03A2AF0, 0xB03A2AF0, 1360 }, - { 0, 0xA0B599B0, 0xB0B599B0, 1360 }, - { 0, 0xA0F7E720, 0xB0F7E720, 1360 }, - { 0, 0xA0533720, 0xB0533720, 1360 }, - { 0, 0xA0378D90, 0xB0378D90, 1360 }, - { 0, 0xA09D2790, 0xB09D2790, 1360 }, - { 0, 0xA080FE80, 0xB080FE80, 1360 }, - { 0, 0xA05BC3E0, 0xB05BC3E0, 1360 }, -}; - -static const uint8_t __attribute__((section(".pdcp_src"), used)) pdcp_src_data[NUM_SRC_SLOTS][PDU_STRIDE] = { - [106] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F, 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F, 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF, 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0xDF, 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 0x5F, 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F, 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 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0x2F, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 0x5F, 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F, 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F, 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF, 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 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a/software/rlc/multi_producer_single_consumer_double_linked_list/data/data_1_1350_1000.h +++ /dev/null @@ -1,2036 +0,0 @@ - -// Copyright 2025 ETH Zurich and University of Bologna. -// -// SPDX-License-Identifier: Apache-2.0 -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -// Author: Zexin Fu - -#ifndef PDCP_PKG_H -#define PDCP_PKG_H - -typedef struct { - int user_id; - unsigned int src_addr; - unsigned int tgt_addr; - unsigned int pkg_length; -} pdcp_pkg_t; - -#define NUM_SRC_SLOTS 197961 -#define PDU_SIZE 1356 -#define NUM_PKGS 1000 - -static const pdcp_pkg_t __attribute__((section(".pdcp_info"))) pdcp_pkgs[NUM_PKGS] = { - { 0, 0xA4492D64, 0xB4492D64, 1356 }, - { 0, 0xA6EC37F0, 0xB6EC37F0, 1356 }, - { 0, 0xAF59E35C, 0xBF59E35C, 1356 }, - { 0, 0xA0817BD8, 0xB0817BD8, 1356 }, - { 0, 0xAD29CE40, 0xBD29CE40, 1356 }, - { 0, 0xAC3E22D8, 0xBC3E22D8, 1356 }, - { 0, 0xAC7F0B24, 0xBC7F0B24, 1356 }, - { 0, 0xA2D86C7C, 0xB2D86C7C, 1356 }, - { 0, 0xA936A3F8, 0xB936A3F8, 1356 }, - { 0, 0xA0826A34, 0xB0826A34, 1356 }, - { 0, 0xA3322908, 0xB3322908, 1356 }, - { 0, 0xA668E4AC, 0xB668E4AC, 1356 }, - { 0, 0xA0C6EC28, 0xB0C6EC28, 1356 }, - { 0, 0xAE7ECAC0, 0xBE7ECAC0, 1356 }, - { 0, 0xAB0C97E4, 0xBB0C97E4, 1356 }, - { 0, 0xA59EC8CC, 0xB59EC8CC, 1356 }, - { 0, 0xA3D83F0C, 0xB3D83F0C, 1356 }, - { 0, 0xA8E090F8, 0xB8E090F8, 1356 }, - { 0, 0xAF7154B8, 0xBF7154B8, 1356 }, - { 0, 0xAADB4424, 0xBADB4424, 1356 }, - { 0, 0xA83E4EE0, 0xB83E4EE0, 1356 }, - { 0, 0xA3767B50, 0xB3767B50, 1356 }, - { 0, 0xAF65D8F4, 0xBF65D8F4, 1356 }, - { 0, 0xA6250C38, 0xB6250C38, 1356 }, - { 0, 0xA9D07F88, 0xB9D07F88, 1356 }, - { 0, 0xABA2850C, 0xBBA2850C, 1356 }, - { 0, 0xA16FC2A8, 0xB16FC2A8, 1356 }, - { 0, 0xA26BC14C, 0xB26BC14C, 1356 }, - { 0, 0xA5430528, 0xB5430528, 1356 }, - { 0, 0xA6BB48D4, 0xB6BB48D4, 1356 }, - { 0, 0xA50F061C, 0xB50F061C, 1356 }, - { 0, 0xAD86AAA0, 0xBD86AAA0, 1356 }, - { 0, 0xA4F72AD0, 0xB4F72AD0, 1356 }, - { 0, 0xA880D454, 0xB880D454, 1356 }, - { 0, 0xA0BC5974, 0xB0BC5974, 1356 }, - { 0, 0xAF60D1D0, 0xBF60D1D0, 1356 }, - { 0, 0xA4B03D20, 0xB4B03D20, 1356 }, - { 0, 0xA2779C68, 0xB2779C68, 1356 }, - { 0, 0xA0A8A6D4, 0xB0A8A6D4, 1356 }, - { 0, 0xAB7E9EF8, 0xBB7E9EF8, 1356 }, - { 0, 0xAD3C08CC, 0xBD3C08CC, 1356 }, - { 0, 0xAC749838, 0xBC749838, 1356 }, - { 0, 0xA1CCA9A0, 0xB1CCA9A0, 1356 }, - { 0, 0xADA6385C, 0xBDA6385C, 1356 }, - { 0, 0xA3A84398, 0xB3A84398, 1356 }, - { 0, 0xA02DA4E8, 0xB02DA4E8, 1356 }, - { 0, 0xA5CE353C, 0xB5CE353C, 1356 }, - { 0, 0xA29252AC, 0xB29252AC, 1356 }, - { 0, 0xA79F9BD8, 0xB79F9BD8, 1356 }, - { 0, 0xAF522654, 0xBF522654, 1356 }, - { 0, 0xA8E01C70, 0xB8E01C70, 1356 }, - { 0, 0xA8C2C578, 0xB8C2C578, 1356 }, - { 0, 0xA5A8C1E4, 0xB5A8C1E4, 1356 }, - { 0, 0xA46334DC, 0xB46334DC, 1356 }, - { 0, 0xABE5EE44, 0xBBE5EE44, 1356 }, - { 0, 0xA20A81FC, 0xB20A81FC, 1356 }, - { 0, 0xAD652064, 0xBD652064, 1356 }, - { 0, 0xA7030518, 0xB7030518, 1356 }, - { 0, 0xA5A99B10, 0xB5A99B10, 1356 }, - { 0, 0xAB82C7A4, 0xBB82C7A4, 1356 }, - { 0, 0xAB19A0EC, 0xBB19A0EC, 1356 }, - { 0, 0xACF4B12C, 0xBCF4B12C, 1356 }, - { 0, 0xA17F1258, 0xB17F1258, 1356 }, - { 0, 0xA6C37FB0, 0xB6C37FB0, 1356 }, - { 0, 0xA6A75158, 0xB6A75158, 1356 }, - { 0, 0xA0344E80, 0xB0344E80, 1356 }, - { 0, 0xAFA25904, 0xBFA25904, 1356 }, - { 0, 0xA6EB73F4, 0xB6EB73F4, 1356 }, - { 0, 0xAFBBA1CC, 0xBFBBA1CC, 1356 }, - { 0, 0xA2CA15C0, 0xB2CA15C0, 1356 }, - { 0, 0xA6834B7C, 0xB6834B7C, 1356 }, - { 0, 0xA86BE3E4, 0xB86BE3E4, 1356 }, - { 0, 0xAD8A8E70, 0xBD8A8E70, 1356 }, - { 0, 0xA23D08F4, 0xB23D08F4, 1356 }, - { 0, 0xAE5F91C4, 0xBE5F91C4, 1356 }, - { 0, 0xA1DA31C8, 0xB1DA31C8, 1356 }, - { 0, 0xAF0F0744, 0xBF0F0744, 1356 }, - { 0, 0xA94569F0, 0xB94569F0, 1356 }, - { 0, 0xA75381F0, 0xB75381F0, 1356 }, - { 0, 0xA5F16738, 0xB5F16738, 1356 }, - { 0, 0xAA21B5C4, 0xBA21B5C4, 1356 }, - { 0, 0xAEA23C4C, 0xBEA23C4C, 1356 }, - { 0, 0xA163FCBC, 0xB163FCBC, 1356 }, - { 0, 0xA763EFA8, 0xB763EFA8, 1356 }, - { 0, 0xA2BE2028, 0xB2BE2028, 1356 }, - { 0, 0xA275CF94, 0xB275CF94, 1356 }, - { 0, 0xA27FD890, 0xB27FD890, 1356 }, - { 0, 0xAAD5F824, 0xBAD5F824, 1356 }, - { 0, 0xA11C9538, 0xB11C9538, 1356 }, - { 0, 0xA4B39738, 0xB4B39738, 1356 }, - { 0, 0xAC5879C4, 0xBC5879C4, 1356 }, - { 0, 0xA7FAFAD8, 0xB7FAFAD8, 1356 }, - { 0, 0xAABC6A80, 0xBABC6A80, 1356 }, - { 0, 0xA7B55ADC, 0xB7B55ADC, 1356 }, - { 0, 0xAB503B60, 0xBB503B60, 1356 }, - { 0, 0xA9EBF47C, 0xB9EBF47C, 1356 }, - { 0, 0xA8796174, 0xB8796174, 1356 }, - { 0, 0xAE61048C, 0xBE61048C, 1356 }, - { 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0, 0xAF09A614, 0xBF09A614, 1356 }, - { 0, 0xAE742828, 0xBE742828, 1356 }, - { 0, 0xA7E7F704, 0xB7E7F704, 1356 }, - { 0, 0xADC541AC, 0xBDC541AC, 1356 }, - { 0, 0xA5143CEC, 0xB5143CEC, 1356 }, - { 0, 0xA9CD6500, 0xB9CD6500, 1356 }, - { 0, 0xABA8E47C, 0xBBA8E47C, 1356 }, - { 0, 0xAE5543EC, 0xBE5543EC, 1356 }, - { 0, 0xA1D83A94, 0xB1D83A94, 1356 }, - { 0, 0xA814A844, 0xB814A844, 1356 }, - { 0, 0xAC84E628, 0xBC84E628, 1356 }, - { 0, 0xA3412944, 0xB3412944, 1356 }, - { 0, 0xAF5D3828, 0xBF5D3828, 1356 }, - { 0, 0xADFF85AC, 0xBDFF85AC, 1356 }, - { 0, 0xA2682258, 0xB2682258, 1356 }, - { 0, 0xAECB78F8, 0xBECB78F8, 1356 }, - { 0, 0xA99A7964, 0xB99A7964, 1356 }, - { 0, 0xA85F053C, 0xB85F053C, 1356 }, - { 0, 0xA6462738, 0xB6462738, 1356 }, - { 0, 0xA20255B8, 0xB20255B8, 1356 }, - { 0, 0xAB1F2C7C, 0xBB1F2C7C, 1356 }, - { 0, 0xA2531220, 0xB2531220, 1356 }, - { 0, 0xAB57B38C, 0xBB57B38C, 1356 }, - { 0, 0xA83B8918, 0xB83B8918, 1356 }, - { 0, 0xAA1816B8, 0xBA1816B8, 1356 }, - { 0, 0xA86711B8, 0xB86711B8, 1356 }, - { 0, 0xA607C524, 0xB607C524, 1356 }, - { 0, 0xAD5531CC, 0xBD5531CC, 1356 }, - { 0, 0xAED857A0, 0xBED857A0, 1356 }, - { 0, 0xA2DB8704, 0xB2DB8704, 1356 }, - { 0, 0xA2A108C0, 0xB2A108C0, 1356 }, - { 0, 0xA5BE513C, 0xB5BE513C, 1356 }, - { 0, 0xAD1A5EC8, 0xBD1A5EC8, 1356 }, - { 0, 0xA19DD6CC, 0xB19DD6CC, 1356 }, - { 0, 0xAF86A9CC, 0xBF86A9CC, 1356 }, - { 0, 0xA68BA220, 0xB68BA220, 1356 }, - { 0, 0xA37FEFFC, 0xB37FEFFC, 1356 }, - { 0, 0xA3C4CBFC, 0xB3C4CBFC, 1356 }, - { 0, 0xA6D3D838, 0xB6D3D838, 1356 }, - { 0, 0xAB1CD5F0, 0xBB1CD5F0, 1356 }, - { 0, 0xAC438954, 0xBC438954, 1356 }, - { 0, 0xA132696C, 0xB132696C, 1356 }, - { 0, 0xAB5C3644, 0xBB5C3644, 1356 }, - { 0, 0xA35530A4, 0xB35530A4, 1356 }, - { 0, 0xAC79BF24, 0xBC79BF24, 1356 }, - { 0, 0xA99F75F0, 0xB99F75F0, 1356 }, - { 0, 0xA5184084, 0xB5184084, 1356 }, - { 0, 0xAC6956B8, 0xBC6956B8, 1356 }, - { 0, 0xAD5E8BFC, 0xBD5E8BFC, 1356 }, - { 0, 0xA7CD460C, 0xB7CD460C, 1356 }, - { 0, 0xA5C21544, 0xB5C21544, 1356 }, - { 0, 0xAC437970, 0xBC437970, 1356 }, - { 0, 0xA0AD19A8, 0xB0AD19A8, 1356 }, - { 0, 0xA3F7332C, 0xB3F7332C, 1356 }, - { 0, 0xA745BF84, 0xB745BF84, 1356 }, - { 0, 0xAEA55188, 0xBEA55188, 1356 }, - { 0, 0xAF669258, 0xBF669258, 1356 }, - { 0, 0xA1544868, 0xB1544868, 1356 }, - { 0, 0xAEC3C13C, 0xBEC3C13C, 1356 }, - { 0, 0xA94D56A4, 0xB94D56A4, 1356 }, - { 0, 0xA14C95F8, 0xB14C95F8, 1356 }, - { 0, 0xA12D8210, 0xB12D8210, 1356 }, - { 0, 0xAB1ED270, 0xBB1ED270, 1356 }, - { 0, 0xA6E2F83C, 0xB6E2F83C, 1356 }, - { 0, 0xAE18E8F0, 0xBE18E8F0, 1356 }, - { 0, 0xA696BE8C, 0xB696BE8C, 1356 }, - { 0, 0xA6DFA8BC, 0xB6DFA8BC, 1356 }, - { 0, 0xAB50D4FC, 0xBB50D4FC, 1356 }, - { 0, 0xA6AF7850, 0xB6AF7850, 1356 }, - { 0, 0xA778B06C, 0xB778B06C, 1356 }, - { 0, 0xADFAD348, 0xBDFAD348, 1356 }, - { 0, 0xA9BAEAE4, 0xB9BAEAE4, 1356 }, - { 0, 0xAB1E7864, 0xBB1E7864, 1356 }, - { 0, 0xA37B42E4, 0xB37B42E4, 1356 }, - { 0, 0xAB1D4FC4, 0xBB1D4FC4, 1356 }, - { 0, 0xAD5BEB48, 0xBD5BEB48, 1356 }, - { 0, 0xAC121B18, 0xBC121B18, 1356 }, - { 0, 0xA5CCF76C, 0xB5CCF76C, 1356 }, - { 0, 0xA1263EDC, 0xB1263EDC, 1356 }, - { 0, 0xABDEEAA0, 0xBBDEEAA0, 1356 }, - { 0, 0xA3CF73E0, 0xB3CF73E0, 1356 }, - { 0, 0xA3812334, 0xB3812334, 1356 }, - { 0, 0xA4FC3C8C, 0xB4FC3C8C, 1356 }, - { 0, 0xAC8CC844, 0xBC8CC844, 1356 }, - { 0, 0xA840DA64, 0xB840DA64, 1356 }, - { 0, 0xAF1A7870, 0xBF1A7870, 1356 }, - { 0, 0xA2485A58, 0xB2485A58, 1356 }, - { 0, 0xAD138584, 0xBD138584, 1356 }, - { 0, 0xA5C60E44, 0xB5C60E44, 1356 }, - { 0, 0xA468414C, 0xB468414C, 1356 }, - { 0, 0xAC25FD64, 0xBC25FD64, 1356 }, - { 0, 0xA8B3AAC0, 0xB8B3AAC0, 1356 }, - { 0, 0xA604F4C4, 0xB604F4C4, 1356 }, - { 0, 0xAF579768, 0xBF579768, 1356 }, - { 0, 0xA345D110, 0xB345D110, 1356 }, - { 0, 0xA7517AD8, 0xB7517AD8, 1356 }, - { 0, 0xADF1F838, 0xBDF1F838, 1356 }, - { 0, 0xAE13A23C, 0xBE13A23C, 1356 }, - { 0, 0xAA23927C, 0xBA23927C, 1356 }, - { 0, 0xA930BE5C, 0xB930BE5C, 1356 }, - { 0, 0xA4803C60, 0xB4803C60, 1356 }, - { 0, 0xA78A0734, 0xB78A0734, 1356 }, - { 0, 0xAEF032EC, 0xBEF032EC, 1356 }, - { 0, 0xA8A1BFA8, 0xB8A1BFA8, 1356 }, - { 0, 0xA0B6AE1C, 0xB0B6AE1C, 1356 }, - { 0, 0xA31C54D4, 0xB31C54D4, 1356 }, - { 0, 0xA7881FE4, 0xB7881FE4, 1356 }, - { 0, 0xA9FA9AAC, 0xB9FA9AAC, 1356 }, - { 0, 0xA0852FFC, 0xB0852FFC, 1356 }, - { 0, 0xAD155CF0, 0xBD155CF0, 1356 }, - { 0, 0xA8EA3A9C, 0xB8EA3A9C, 1356 }, - { 0, 0xAC5DA5FC, 0xBC5DA5FC, 1356 }, - { 0, 0xA0CC8250, 0xB0CC8250, 1356 }, - { 0, 0xA5EE81A8, 0xB5EE81A8, 1356 }, - { 0, 0xA05450C4, 0xB05450C4, 1356 }, - { 0, 0xA3FB6BBC, 0xB3FB6BBC, 1356 }, - { 0, 0xA0461F1C, 0xB0461F1C, 1356 }, - { 0, 0xA0D97B74, 0xB0D97B74, 1356 }, - { 0, 0xA86C586C, 0xB86C586C, 1356 }, - { 0, 0xA7DFB590, 0xB7DFB590, 1356 }, - { 0, 0xA6E2E858, 0xB6E2E858, 1356 }, - { 0, 0xA053C70C, 0xB053C70C, 1356 }, - { 0, 0xAC4A6D30, 0xBC4A6D30, 1356 }, - { 0, 0xAE553408, 0xBE553408, 1356 }, - { 0, 0xA03A63C8, 0xB03A63C8, 1356 }, - { 0, 0xA04A4D14, 0xB04A4D14, 1356 }, - { 0, 0xA7FDE068, 0xB7FDE068, 1356 }, - { 0, 0xA6233F64, 0xB6233F64, 1356 }, - { 0, 0xAC41AC9C, 0xBC41AC9C, 1356 }, - { 0, 0xA5EF7A9C, 0xB5EF7A9C, 1356 }, - { 0, 0xA0037494, 0xB0037494, 1356 }, - { 0, 0xA28F3D70, 0xB28F3D70, 1356 }, - { 0, 0xAB0377F8, 0xBB0377F8, 1356 }, - { 0, 0xA95464E0, 0xB95464E0, 1356 }, - { 0, 0xA3EDD3B0, 0xB3EDD3B0, 1356 }, - { 0, 0xA2B69818, 0xB2B69818, 1356 }, - { 0, 0xA0F4C608, 0xB0F4C608, 1356 }, - { 0, 0xACCAFAAC, 0xBCCAFAAC, 1356 }, - { 0, 0xAF9A51D4, 0xBF9A51D4, 1356 }, - { 0, 0xA2DCF480, 0xB2DCF480, 1356 }, - { 0, 0xA822D9EC, 0xB822D9EC, 1356 }, - { 0, 0xAB712168, 0xBB712168, 1356 }, - { 0, 0xA37A49F0, 0xB37A49F0, 1356 }, - { 0, 0xAC029670, 0xBC029670, 1356 }, - { 0, 0xA3D9B1D4, 0xB3D9B1D4, 1356 }, - { 0, 0xA1F7A888, 0xB1F7A888, 1356 }, - { 0, 0xA59B29D8, 0xB59B29D8, 1356 }, - { 0, 0xA21430EC, 0xB21430EC, 1356 }, - { 0, 0xA58FA37C, 0xB58FA37C, 1356 }, - { 0, 0xAEC1EF1C, 0xBEC1EF1C, 1356 }, - { 0, 0xAE3674E0, 0xBE3674E0, 1356 }, - { 0, 0xAF832AA0, 0xBF832AA0, 1356 }, - { 0, 0xA6EE7400, 0xB6EE7400, 1356 }, - { 0, 0xAAD35770, 0xBAD35770, 1356 }, - { 0, 0xAC6CD5E4, 0xBC6CD5E4, 1356 }, - { 0, 0xAF1EFB28, 0xBF1EFB28, 1356 }, - { 0, 0xA3F77808, 0xB3F77808, 1356 }, - { 0, 0xAE40F7B0, 0xBE40F7B0, 1356 }, - { 0, 0xAD82C6D0, 0xBD82C6D0, 1356 }, - { 0, 0xAFD3BCA8, 0xBFD3BCA8, 1356 }, - { 0, 0xA9C41AB4, 0xB9C41AB4, 1356 }, - { 0, 0xA5BD6D78, 0xB5BD6D78, 1356 }, - { 0, 0xA23C001C, 0xB23C001C, 1356 }, - { 0, 0xA1CFC428, 0xB1CFC428, 1356 }, - { 0, 0xA1CE7128, 0xB1CE7128, 1356 }, - { 0, 0xAACC88C4, 0xBACC88C4, 1356 }, - { 0, 0xA1377090, 0xB1377090, 1356 }, - { 0, 0xAB7EA990, 0xBB7EA990, 1356 }, - { 0, 0xAE506728, 0xBE506728, 1356 }, - { 0, 0xA6FC4B9C, 0xB6FC4B9C, 1356 }, - { 0, 0xAB34CBB8, 0xBB34CBB8, 1356 }, - { 0, 0xA3F53160, 0xB3F53160, 1356 }, - { 0, 0xA8B25274, 0xB8B25274, 1356 }, - { 0, 0xA3F70380, 0xB3F70380, 1356 }, - { 0, 0xA1C43334, 0xB1C43334, 1356 }, - { 0, 0xA4DFBEC0, 0xB4DFBEC0, 1356 }, - { 0, 0xA9E9F7FC, 0xB9E9F7FC, 1356 }, - { 0, 0xA3921FF0, 0xB3921FF0, 1356 }, - { 0, 0xAF5EA058, 0xBF5EA058, 1356 }, - { 0, 0xAE5ABF98, 0xBE5ABF98, 1356 }, - { 0, 0xA80D84D8, 0xB80D84D8, 1356 }, - { 0, 0xAC380D90, 0xBC380D90, 1356 }, - { 0, 0xA3014484, 0xB3014484, 1356 }, - { 0, 0xADC06F80, 0xBDC06F80, 1356 }, - { 0, 0xA5E65AB0, 0xB5E65AB0, 1356 }, - { 0, 0xA8B6CA94, 0xB8B6CA94, 1356 }, - { 0, 0xAE70CE10, 0xBE70CE10, 1356 }, - { 0, 0xAAE0A008, 0xBAE0A008, 1356 }, - { 0, 0xA4187340, 0xB4187340, 1356 }, - { 0, 0xA891D65C, 0xB891D65C, 1356 }, - { 0, 0xA4EDDB38, 0xB4EDDB38, 1356 }, - { 0, 0xA7E1629C, 0xB7E1629C, 1356 }, - { 0, 0xA07EF5A0, 0xB07EF5A0, 1356 }, - { 0, 0xAE2621A4, 0xBE2621A4, 1356 }, - { 0, 0xA9D433AC, 0xB9D433AC, 1356 }, - { 0, 0xA0FA7BF8, 0xB0FA7BF8, 1356 }, - { 0, 0xA0318E04, 0xB0318E04, 1356 }, - { 0, 0xAD3CA268, 0xBD3CA268, 1356 }, - { 0, 0xA086DD08, 0xB086DD08, 1356 }, - { 0, 0xA71A0C84, 0xB71A0C84, 1356 }, - { 0, 0xA2209B0C, 0xB2209B0C, 1356 }, - { 0, 0xAB1E6334, 0xBB1E6334, 1356 }, - { 0, 0xA9FF6CD8, 0xB9FF6CD8, 1356 }, - { 0, 0xA341BD94, 0xB341BD94, 1356 }, - { 0, 0xA0BE2648, 0xB0BE2648, 1356 }, - { 0, 0xA29ED748, 0xB29ED748, 1356 }, - { 0, 0xA935A5B8, 0xB935A5B8, 1356 }, - { 0, 0xA33B1948, 0xB33B1948, 1356 }, - { 0, 0xABC8D190, 0xBBC8D190, 1356 }, - { 0, 0xA6C9AA28, 0xB6C9AA28, 1356 }, - { 0, 0xABD4BC90, 0xBBD4BC90, 1356 }, - { 0, 0xA82DEBC0, 0xB82DEBC0, 1356 }, - { 0, 0xA6719010, 0xB6719010, 1356 }, - { 0, 0xA4CAEE18, 0xB4CAEE18, 1356 }, - { 0, 0xA6DA8C68, 0xB6DA8C68, 1356 }, - { 0, 0xADE32CF4, 0xBDE32CF4, 1356 }, - { 0, 0xA9C69BA0, 0xB9C69BA0, 1356 }, - { 0, 0xA6B21904, 0xB6B21904, 1356 }, - { 0, 0xAFAC91AC, 0xBFAC91AC, 1356 }, - { 0, 0xA1DF787C, 0xB1DF787C, 1356 }, - { 0, 0xA4B8B38C, 0xB4B8B38C, 1356 }, - { 0, 0xA00C54F0, 0xB00C54F0, 1356 }, - { 0, 0xA2577510, 0xB2577510, 1356 }, - { 0, 0xAEE54B78, 0xBEE54B78, 1356 }, - { 0, 0xA14A1FA4, 0xB14A1FA4, 1356 }, - { 0, 0xA18DDD9C, 0xB18DDD9C, 1356 }, - { 0, 0xAA3D8F5C, 0xBA3D8F5C, 1356 }, - { 0, 0xA1F8CBDC, 0xB1F8CBDC, 1356 }, - { 0, 0xA344CD84, 0xB344CD84, 1356 }, - { 0, 0xA5004024, 0xB5004024, 1356 }, - { 0, 0xA5F00EEC, 0xB5F00EEC, 1356 }, - { 0, 0xAACE20A0, 0xBACE20A0, 1356 }, - { 0, 0xA97058F4, 0xB97058F4, 1356 }, - { 0, 0xAF4AB374, 0xBF4AB374, 1356 }, - { 0, 0xA59893BC, 0xB59893BC, 1356 }, - { 0, 0xACD7D408, 0xBCD7D408, 1356 }, - { 0, 0xA195C504, 0xB195C504, 1356 }, - { 0, 0xA7211AC0, 0xB7211AC0, 1356 }, - { 0, 0xA21EA3D8, 0xB21EA3D8, 1356 }, -}; - -static const uint8_t __attribute__((section(".pdcp_src"))) pdcp_src_data[NUM_SRC_SLOTS][PDU_SIZE] = { - [167] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 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the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -// Author: Zexin Fu - -#ifndef PDCP_PKG_H -#define PDCP_PKG_H - -#include - -typedef struct { - int user_id; - unsigned int src_addr; - unsigned int tgt_addr; - unsigned int pkg_length; -} pdcp_pkg_t; - -#define NUM_SRC_SLOTS 12336 -#define PDU_SIZE 1360 -#define PDU_STRIDE 1360 -#define NUM_PKGS 100 -#define ACTIVE_USER_NUMBER 1 - -#define NUM_PRODUCER_CORES 1 -static const unsigned int producer_core_ids[NUM_PRODUCER_CORES] = {0}; -#define NUM_CONSUMER_CORES 1 -static const unsigned int consumer_core_ids[NUM_CONSUMER_CORES] = {1}; -#define NUM_RLC_KERNEL_CORES (NUM_PRODUCER_CORES + NUM_CONSUMER_CORES) -static const unsigned int rlc_kernel_core_ids[NUM_RLC_KERNEL_CORES] = {0, 1}; - -static const pdcp_pkg_t __attribute__((section(".pdcp_info"), used)) pdcp_pkgs[NUM_PKGS] = { - { 0, 0xA0D965C0, 0xB0D965C0, 1360 }, - { 0, 0xA025DA00, 0xB025DA00, 1360 }, - { 0, 0xA0087CD0, 0xB0087CD0, 1360 }, - { 0, 0xA0FC1D90, 0xB0FC1D90, 1360 }, - { 0, 0xA05D8220, 0xB05D8220, 1360 }, - { 0, 0xA05341C0, 0xB05341C0, 1360 }, - { 0, 0xA04BE3D0, 0xB04BE3D0, 1360 }, - { 0, 0xA02F7060, 0xB02F7060, 1360 }, - { 0, 0xA0FA64A0, 0xB0FA64A0, 1360 }, - { 0, 0xA022D7B0, 0xB022D7B0, 1360 }, - { 0, 0xA0E613B0, 0xB0E613B0, 1360 }, - { 0, 0xA0FBD330, 0xB0FBD330, 1360 }, - { 0, 0xA0B96B30, 0xB0B96B30, 1360 }, - { 0, 0xA01D8D00, 0xB01D8D00, 1360 }, - { 0, 0xA0C8C120, 0xB0C8C120, 1360 }, - { 0, 0xA08F7000, 0xB08F7000, 1360 }, - { 0, 0xA00ACA80, 0xB00ACA80, 1360 }, - { 0, 0xA00A2080, 0xB00A2080, 1360 }, - { 0, 0xA01FDAB0, 0xB01FDAB0, 1360 }, - { 0, 0xA04A5560, 0xB04A5560, 1360 }, - { 0, 0xA04F15F0, 0xB04F15F0, 1360 }, - { 0, 0xA0ABCE30, 0xB0ABCE30, 1360 }, - { 0, 0xA0CCAD30, 0xB0CCAD30, 1360 }, - { 0, 0xA00901A0, 0xB00901A0, 1360 }, - { 0, 0xA0BED070, 0xB0BED070, 1360 }, - { 0, 0xA04396D0, 0xB04396D0, 1360 }, - { 0, 0xA0F370F0, 0xB0F370F0, 1360 }, - { 0, 0xA0DCF230, 0xB0DCF230, 1360 }, - { 0, 0xA0EE70A0, 0xB0EE70A0, 1360 }, - { 0, 0xA0B94600, 0xB0B94600, 1360 }, - { 0, 0xA08EA0D0, 0xB08EA0D0, 1360 }, - { 0, 0xA04AEF70, 0xB04AEF70, 1360 }, - { 0, 0xA098B6B0, 0xB098B6B0, 1360 }, - { 0, 0xA0C856E0, 0xB0C856E0, 1360 }, - { 0, 0xA05E9110, 0xB05E9110, 1360 }, - { 0, 0xA0023320, 0xB0023320, 1360 }, - { 0, 0xA0364430, 0xB0364430, 1360 }, - { 0, 0xA0ED5C60, 0xB0ED5C60, 1360 }, - { 0, 0xA08FAFC0, 0xB08FAFC0, 1360 }, - { 0, 0xA073ABE0, 0xB073ABE0, 1360 }, - { 0, 0xA05E7680, 0xB05E7680, 1360 }, - { 0, 0xA034DAF0, 0xB034DAF0, 1360 }, - { 0, 0xA0493130, 0xB0493130, 1360 }, - { 0, 0xA0726D20, 0xB0726D20, 1360 }, - { 0, 0xA022BD20, 0xB022BD20, 1360 }, - { 0, 0xA01F85B0, 0xB01F85B0, 1360 }, - { 0, 0xA0812900, 0xB0812900, 1360 }, - { 0, 0xA020DF00, 0xB020DF00, 1360 }, - { 0, 0xA07A0AD0, 0xB07A0AD0, 1360 }, - { 0, 0xA074EFF0, 0xB074EFF0, 1360 }, - { 0, 0xA0CD41F0, 0xB0CD41F0, 1360 }, - { 0, 0xA059EB10, 0xB059EB10, 1360 }, - { 0, 0xA00EC130, 0xB00EC130, 1360 }, - { 0, 0xA0F816F0, 0xB0F816F0, 1360 }, - { 0, 0xA09C3330, 0xB09C3330, 1360 }, - { 0, 0xA0B64E50, 0xB0B64E50, 1360 }, - { 0, 0xA02A7010, 0xB02A7010, 1360 }, - { 0, 0xA080AED0, 0xB080AED0, 1360 }, - { 0, 0xA01ACA70, 0xB01ACA70, 1360 }, - { 0, 0xA0BBAE40, 0xB0BBAE40, 1360 }, - { 0, 0xA063ABF0, 0xB063ABF0, 1360 }, - { 0, 0xA0D5B970, 0xB0D5B970, 1360 }, - { 0, 0xA0D24790, 0xB0D24790, 1360 }, - { 0, 0xA07AF490, 0xB07AF490, 1360 }, - { 0, 0xA0C44AF0, 0xB0C44AF0, 1360 }, - { 0, 0xA0415E60, 0xB0415E60, 1360 }, - { 0, 0xA0EF8A30, 0xB0EF8A30, 1360 }, - { 0, 0xA017A2F0, 0xB017A2F0, 1360 }, - { 0, 0xA00F9060, 0xB00F9060, 1360 }, - { 0, 0xA0E0D3A0, 0xB0E0D3A0, 1360 }, - { 0, 0xA04D7790, 0xB04D7790, 1360 }, - { 0, 0xA0626290, 0xB0626290, 1360 }, - { 0, 0xA01B1F70, 0xB01B1F70, 1360 }, - { 0, 0xA04F25E0, 0xB04F25E0, 1360 }, - { 0, 0xA02252E0, 0xB02252E0, 1360 }, - { 0, 0xA08138F0, 0xB08138F0, 1360 }, - { 0, 0xA05E8120, 0xB05E8120, 1360 }, - { 0, 0xA09A2540, 0xB09A2540, 1360 }, - { 0, 0xA0D821B0, 0xB0D821B0, 1360 }, - { 0, 0xA07C08D0, 0xB07C08D0, 1360 }, - { 0, 0xA0374880, 0xB0374880, 1360 }, - { 0, 0xA07DDC50, 0xB07DDC50, 1360 }, - { 0, 0xA078C6C0, 0xB078C6C0, 1360 }, - { 0, 0xA0473880, 0xB0473880, 1360 }, - { 0, 0xA0E3DB40, 0xB0E3DB40, 1360 }, - { 0, 0xA05AC4E0, 0xB05AC4E0, 1360 }, - { 0, 0xA0EE9B20, 0xB0EE9B20, 1360 }, - { 0, 0xA0E866B0, 0xB0E866B0, 1360 }, - { 0, 0xA0DC52D0, 0xB0DC52D0, 1360 }, - { 0, 0xA0184250, 0xB0184250, 1360 }, - { 0, 0xA0CF1AC0, 0xB0CF1AC0, 1360 }, - { 0, 0xA0D7E1F0, 0xB0D7E1F0, 1360 }, - { 0, 0xA03A2AF0, 0xB03A2AF0, 1360 }, - { 0, 0xA0B599B0, 0xB0B599B0, 1360 }, - { 0, 0xA0F7E720, 0xB0F7E720, 1360 }, - { 0, 0xA0533720, 0xB0533720, 1360 }, - { 0, 0xA0378D90, 0xB0378D90, 1360 }, - { 0, 0xA09D2790, 0xB09D2790, 1360 }, - { 0, 0xA080FE80, 0xB080FE80, 1360 }, - { 0, 0xA05BC3E0, 0xB05BC3E0, 1360 }, -}; - -static const uint8_t __attribute__((section(".pdcp_src"), used)) pdcp_src_data[NUM_SRC_SLOTS][PDU_STRIDE] = { - [106] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F, 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F, 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF, 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0xDF, 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 0x5F, 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F, 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F, 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF, 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0xDF, 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 0x5F, 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F, 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F, 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF, 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0xDF, 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 0x5F, 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F, 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F, 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF, 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0xDF, 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 0x5F, 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F, 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F, 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF, 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0xDF, 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50, 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0x2F, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 0x5F, 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F, 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F, 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA }, -}; - -#endif // PDCP_PKG_H diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/data/data_1_1350_100_p1c3.h b/software/rlc/multi_producer_single_consumer_double_linked_list/data/data_1_1350_100_p1c3.h deleted file mode 100644 index 29b5c8c..0000000 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/data/data_1_1350_100_p1c3.h +++ /dev/null @@ -1,251 +0,0 @@ - -// Copyright 2025 ETH Zurich and University of Bologna. -// -// SPDX-License-Identifier: Apache-2.0 -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -// Author: Zexin Fu - -#ifndef PDCP_PKG_H -#define PDCP_PKG_H - -#include - -typedef struct { - int user_id; - unsigned int src_addr; - unsigned int tgt_addr; - unsigned int pkg_length; -} pdcp_pkg_t; - -#define NUM_SRC_SLOTS 12336 -#define PDU_SIZE 1360 -#define PDU_STRIDE 1360 -#define NUM_PKGS 100 -#define ACTIVE_USER_NUMBER 1 - -#define NUM_PRODUCER_CORES 1 -static const unsigned int producer_core_ids[NUM_PRODUCER_CORES] = {0}; -#define NUM_CONSUMER_CORES 3 -static const unsigned int consumer_core_ids[NUM_CONSUMER_CORES] = {1, 2, 3}; -#define NUM_RLC_KERNEL_CORES (NUM_PRODUCER_CORES + NUM_CONSUMER_CORES) -static const unsigned int rlc_kernel_core_ids[NUM_RLC_KERNEL_CORES] = {0, 1, 2, 3}; - -static const pdcp_pkg_t __attribute__((section(".pdcp_info"), used)) pdcp_pkgs[NUM_PKGS] = { - { 0, 0xA0D965C0, 0xB0D965C0, 1360 }, - { 0, 0xA025DA00, 0xB025DA00, 1360 }, - { 0, 0xA0087CD0, 0xB0087CD0, 1360 }, - { 0, 0xA0FC1D90, 0xB0FC1D90, 1360 }, - { 0, 0xA05D8220, 0xB05D8220, 1360 }, - { 0, 0xA05341C0, 0xB05341C0, 1360 }, - { 0, 0xA04BE3D0, 0xB04BE3D0, 1360 }, - { 0, 0xA02F7060, 0xB02F7060, 1360 }, - { 0, 0xA0FA64A0, 0xB0FA64A0, 1360 }, - { 0, 0xA022D7B0, 0xB022D7B0, 1360 }, - { 0, 0xA0E613B0, 0xB0E613B0, 1360 }, - { 0, 0xA0FBD330, 0xB0FBD330, 1360 }, - { 0, 0xA0B96B30, 0xB0B96B30, 1360 }, - { 0, 0xA01D8D00, 0xB01D8D00, 1360 }, - { 0, 0xA0C8C120, 0xB0C8C120, 1360 }, - { 0, 0xA08F7000, 0xB08F7000, 1360 }, - { 0, 0xA00ACA80, 0xB00ACA80, 1360 }, - { 0, 0xA00A2080, 0xB00A2080, 1360 }, - { 0, 0xA01FDAB0, 0xB01FDAB0, 1360 }, - { 0, 0xA04A5560, 0xB04A5560, 1360 }, - { 0, 0xA04F15F0, 0xB04F15F0, 1360 }, - { 0, 0xA0ABCE30, 0xB0ABCE30, 1360 }, - { 0, 0xA0CCAD30, 0xB0CCAD30, 1360 }, - { 0, 0xA00901A0, 0xB00901A0, 1360 }, - { 0, 0xA0BED070, 0xB0BED070, 1360 }, - { 0, 0xA04396D0, 0xB04396D0, 1360 }, - { 0, 0xA0F370F0, 0xB0F370F0, 1360 }, - { 0, 0xA0DCF230, 0xB0DCF230, 1360 }, - { 0, 0xA0EE70A0, 0xB0EE70A0, 1360 }, - { 0, 0xA0B94600, 0xB0B94600, 1360 }, - { 0, 0xA08EA0D0, 0xB08EA0D0, 1360 }, - { 0, 0xA04AEF70, 0xB04AEF70, 1360 }, - { 0, 0xA098B6B0, 0xB098B6B0, 1360 }, - { 0, 0xA0C856E0, 0xB0C856E0, 1360 }, - { 0, 0xA05E9110, 0xB05E9110, 1360 }, - { 0, 0xA0023320, 0xB0023320, 1360 }, - { 0, 0xA0364430, 0xB0364430, 1360 }, - { 0, 0xA0ED5C60, 0xB0ED5C60, 1360 }, - { 0, 0xA08FAFC0, 0xB08FAFC0, 1360 }, - { 0, 0xA073ABE0, 0xB073ABE0, 1360 }, - { 0, 0xA05E7680, 0xB05E7680, 1360 }, - { 0, 0xA034DAF0, 0xB034DAF0, 1360 }, - { 0, 0xA0493130, 0xB0493130, 1360 }, - { 0, 0xA0726D20, 0xB0726D20, 1360 }, - { 0, 0xA022BD20, 0xB022BD20, 1360 }, - { 0, 0xA01F85B0, 0xB01F85B0, 1360 }, - { 0, 0xA0812900, 0xB0812900, 1360 }, - { 0, 0xA020DF00, 0xB020DF00, 1360 }, - { 0, 0xA07A0AD0, 0xB07A0AD0, 1360 }, - { 0, 0xA074EFF0, 0xB074EFF0, 1360 }, - { 0, 0xA0CD41F0, 0xB0CD41F0, 1360 }, - { 0, 0xA059EB10, 0xB059EB10, 1360 }, - { 0, 0xA00EC130, 0xB00EC130, 1360 }, - { 0, 0xA0F816F0, 0xB0F816F0, 1360 }, - { 0, 0xA09C3330, 0xB09C3330, 1360 }, - { 0, 0xA0B64E50, 0xB0B64E50, 1360 }, - { 0, 0xA02A7010, 0xB02A7010, 1360 }, - { 0, 0xA080AED0, 0xB080AED0, 1360 }, - { 0, 0xA01ACA70, 0xB01ACA70, 1360 }, - { 0, 0xA0BBAE40, 0xB0BBAE40, 1360 }, - { 0, 0xA063ABF0, 0xB063ABF0, 1360 }, - { 0, 0xA0D5B970, 0xB0D5B970, 1360 }, - { 0, 0xA0D24790, 0xB0D24790, 1360 }, - { 0, 0xA07AF490, 0xB07AF490, 1360 }, - { 0, 0xA0C44AF0, 0xB0C44AF0, 1360 }, - { 0, 0xA0415E60, 0xB0415E60, 1360 }, - { 0, 0xA0EF8A30, 0xB0EF8A30, 1360 }, - { 0, 0xA017A2F0, 0xB017A2F0, 1360 }, - { 0, 0xA00F9060, 0xB00F9060, 1360 }, - { 0, 0xA0E0D3A0, 0xB0E0D3A0, 1360 }, - { 0, 0xA04D7790, 0xB04D7790, 1360 }, - { 0, 0xA0626290, 0xB0626290, 1360 }, - { 0, 0xA01B1F70, 0xB01B1F70, 1360 }, - { 0, 0xA04F25E0, 0xB04F25E0, 1360 }, - { 0, 0xA02252E0, 0xB02252E0, 1360 }, - { 0, 0xA08138F0, 0xB08138F0, 1360 }, - { 0, 0xA05E8120, 0xB05E8120, 1360 }, - { 0, 0xA09A2540, 0xB09A2540, 1360 }, - { 0, 0xA0D821B0, 0xB0D821B0, 1360 }, - { 0, 0xA07C08D0, 0xB07C08D0, 1360 }, - { 0, 0xA0374880, 0xB0374880, 1360 }, - { 0, 0xA07DDC50, 0xB07DDC50, 1360 }, - { 0, 0xA078C6C0, 0xB078C6C0, 1360 }, - { 0, 0xA0473880, 0xB0473880, 1360 }, - { 0, 0xA0E3DB40, 0xB0E3DB40, 1360 }, - { 0, 0xA05AC4E0, 0xB05AC4E0, 1360 }, - { 0, 0xA0EE9B20, 0xB0EE9B20, 1360 }, - { 0, 0xA0E866B0, 0xB0E866B0, 1360 }, - { 0, 0xA0DC52D0, 0xB0DC52D0, 1360 }, - { 0, 0xA0184250, 0xB0184250, 1360 }, - { 0, 0xA0CF1AC0, 0xB0CF1AC0, 1360 }, - { 0, 0xA0D7E1F0, 0xB0D7E1F0, 1360 }, - { 0, 0xA03A2AF0, 0xB03A2AF0, 1360 }, - { 0, 0xA0B599B0, 0xB0B599B0, 1360 }, - { 0, 0xA0F7E720, 0xB0F7E720, 1360 }, - { 0, 0xA0533720, 0xB0533720, 1360 }, - { 0, 0xA0378D90, 0xB0378D90, 1360 }, - { 0, 0xA09D2790, 0xB09D2790, 1360 }, - { 0, 0xA080FE80, 0xB080FE80, 1360 }, - { 0, 0xA05BC3E0, 0xB05BC3E0, 1360 }, -}; - -static const uint8_t __attribute__((section(".pdcp_src"), used)) pdcp_src_data[NUM_SRC_SLOTS][PDU_STRIDE] = { - [106] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F, 0x80, 0x81, 0x82, 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required by applicable law or agreed to in writing, software -// distributed under the License distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -// Author: Zexin Fu - -#ifndef PDCP_PKG_H -#define PDCP_PKG_H - -#include - -typedef struct { - int user_id; - unsigned int src_addr; - unsigned int tgt_addr; - unsigned int pkg_length; -} pdcp_pkg_t; - -#define NUM_SRC_SLOTS 12336 -#define PDU_SIZE 1360 -#define PDU_STRIDE 1360 -#define NUM_PKGS 300 -#define ACTIVE_USER_NUMBER 1 - -#define NUM_PRODUCER_CORES 2 -static const unsigned int producer_core_ids[NUM_PRODUCER_CORES] = {0, 1}; -#define NUM_CONSUMER_CORES 2 -static const unsigned int consumer_core_ids[NUM_CONSUMER_CORES] = {2, 3}; -#define NUM_RLC_KERNEL_CORES (NUM_PRODUCER_CORES + NUM_CONSUMER_CORES) -static const unsigned int rlc_kernel_core_ids[NUM_RLC_KERNEL_CORES] = {0, 1, 2, 3}; - -static const pdcp_pkg_t __attribute__((section(".pdcp_info"), used)) pdcp_pkgs[NUM_PKGS] = { - { 0, 0xA0D965C0, 0xB0D965C0, 1360 }, - { 0, 0xA025DA00, 0xB025DA00, 1360 }, - { 0, 0xA0087CD0, 0xB0087CD0, 1360 }, - { 0, 0xA0FC1D90, 0xB0FC1D90, 1360 }, - { 0, 0xA05D8220, 0xB05D8220, 1360 }, - { 0, 0xA05341C0, 0xB05341C0, 1360 }, - { 0, 0xA04BE3D0, 0xB04BE3D0, 1360 }, - { 0, 0xA02F7060, 0xB02F7060, 1360 }, - { 0, 0xA0FA64A0, 0xB0FA64A0, 1360 }, - { 0, 0xA022D7B0, 0xB022D7B0, 1360 }, - { 0, 0xA0E613B0, 0xB0E613B0, 1360 }, - { 0, 0xA0FBD330, 0xB0FBD330, 1360 }, - { 0, 0xA0B96B30, 0xB0B96B30, 1360 }, - { 0, 0xA01D8D00, 0xB01D8D00, 1360 }, - { 0, 0xA0C8C120, 0xB0C8C120, 1360 }, - { 0, 0xA08F7000, 0xB08F7000, 1360 }, - { 0, 0xA00ACA80, 0xB00ACA80, 1360 }, - { 0, 0xA00A2080, 0xB00A2080, 1360 }, - { 0, 0xA01FDAB0, 0xB01FDAB0, 1360 }, - { 0, 0xA04A5560, 0xB04A5560, 1360 }, - { 0, 0xA04F15F0, 0xB04F15F0, 1360 }, - { 0, 0xA0ABCE30, 0xB0ABCE30, 1360 }, - { 0, 0xA0CCAD30, 0xB0CCAD30, 1360 }, - { 0, 0xA00901A0, 0xB00901A0, 1360 }, - { 0, 0xA0BED070, 0xB0BED070, 1360 }, - { 0, 0xA04396D0, 0xB04396D0, 1360 }, - { 0, 0xA0F370F0, 0xB0F370F0, 1360 }, - { 0, 0xA0DCF230, 0xB0DCF230, 1360 }, - { 0, 0xA0EE70A0, 0xB0EE70A0, 1360 }, - { 0, 0xA0B94600, 0xB0B94600, 1360 }, - { 0, 0xA08EA0D0, 0xB08EA0D0, 1360 }, - { 0, 0xA04AEF70, 0xB04AEF70, 1360 }, - { 0, 0xA098B6B0, 0xB098B6B0, 1360 }, - { 0, 0xA0C856E0, 0xB0C856E0, 1360 }, - { 0, 0xA05E9110, 0xB05E9110, 1360 }, - { 0, 0xA0023320, 0xB0023320, 1360 }, - { 0, 0xA0364430, 0xB0364430, 1360 }, - { 0, 0xA0ED5C60, 0xB0ED5C60, 1360 }, - { 0, 0xA08FAFC0, 0xB08FAFC0, 1360 }, - { 0, 0xA073ABE0, 0xB073ABE0, 1360 }, - { 0, 0xA05E7680, 0xB05E7680, 1360 }, - { 0, 0xA034DAF0, 0xB034DAF0, 1360 }, - { 0, 0xA0493130, 0xB0493130, 1360 }, - { 0, 0xA0726D20, 0xB0726D20, 1360 }, - { 0, 0xA022BD20, 0xB022BD20, 1360 }, - { 0, 0xA01F85B0, 0xB01F85B0, 1360 }, - { 0, 0xA0812900, 0xB0812900, 1360 }, - { 0, 0xA020DF00, 0xB020DF00, 1360 }, - { 0, 0xA07A0AD0, 0xB07A0AD0, 1360 }, - { 0, 0xA074EFF0, 0xB074EFF0, 1360 }, - { 0, 0xA0CD41F0, 0xB0CD41F0, 1360 }, - { 0, 0xA059EB10, 0xB059EB10, 1360 }, - { 0, 0xA00EC130, 0xB00EC130, 1360 }, - { 0, 0xA0F816F0, 0xB0F816F0, 1360 }, - { 0, 0xA09C3330, 0xB09C3330, 1360 }, - { 0, 0xA0B64E50, 0xB0B64E50, 1360 }, - { 0, 0xA02A7010, 0xB02A7010, 1360 }, - { 0, 0xA080AED0, 0xB080AED0, 1360 }, - { 0, 0xA01ACA70, 0xB01ACA70, 1360 }, - { 0, 0xA0BBAE40, 0xB0BBAE40, 1360 }, - { 0, 0xA063ABF0, 0xB063ABF0, 1360 }, - { 0, 0xA0D5B970, 0xB0D5B970, 1360 }, - { 0, 0xA0D24790, 0xB0D24790, 1360 }, - { 0, 0xA07AF490, 0xB07AF490, 1360 }, - { 0, 0xA0C44AF0, 0xB0C44AF0, 1360 }, - { 0, 0xA0415E60, 0xB0415E60, 1360 }, - { 0, 0xA0EF8A30, 0xB0EF8A30, 1360 }, - { 0, 0xA017A2F0, 0xB017A2F0, 1360 }, - { 0, 0xA00F9060, 0xB00F9060, 1360 }, - { 0, 0xA0E0D3A0, 0xB0E0D3A0, 1360 }, - { 0, 0xA04D7790, 0xB04D7790, 1360 }, - { 0, 0xA0626290, 0xB0626290, 1360 }, - { 0, 0xA01B1F70, 0xB01B1F70, 1360 }, - { 0, 0xA04F25E0, 0xB04F25E0, 1360 }, - { 0, 0xA02252E0, 0xB02252E0, 1360 }, - { 0, 0xA08138F0, 0xB08138F0, 1360 }, - { 0, 0xA05E8120, 0xB05E8120, 1360 }, - { 0, 0xA09A2540, 0xB09A2540, 1360 }, - { 0, 0xA0D821B0, 0xB0D821B0, 1360 }, - { 0, 0xA07C08D0, 0xB07C08D0, 1360 }, - { 0, 0xA0374880, 0xB0374880, 1360 }, - { 0, 0xA07DDC50, 0xB07DDC50, 1360 }, - { 0, 0xA078C6C0, 0xB078C6C0, 1360 }, - { 0, 0xA0473880, 0xB0473880, 1360 }, - { 0, 0xA0E3DB40, 0xB0E3DB40, 1360 }, - { 0, 0xA05AC4E0, 0xB05AC4E0, 1360 }, - { 0, 0xA0EE9B20, 0xB0EE9B20, 1360 }, - { 0, 0xA0E866B0, 0xB0E866B0, 1360 }, - { 0, 0xA0DC52D0, 0xB0DC52D0, 1360 }, - { 0, 0xA0184250, 0xB0184250, 1360 }, - { 0, 0xA0CF1AC0, 0xB0CF1AC0, 1360 }, - { 0, 0xA0D7E1F0, 0xB0D7E1F0, 1360 }, - { 0, 0xA03A2AF0, 0xB03A2AF0, 1360 }, - { 0, 0xA0B599B0, 0xB0B599B0, 1360 }, - { 0, 0xA0F7E720, 0xB0F7E720, 1360 }, - { 0, 0xA0533720, 0xB0533720, 1360 }, - { 0, 0xA0378D90, 0xB0378D90, 1360 }, - { 0, 0xA09D2790, 0xB09D2790, 1360 }, - { 0, 0xA080FE80, 0xB080FE80, 1360 }, - { 0, 0xA05BC3E0, 0xB05BC3E0, 1360 }, - { 0, 0xA0D99590, 0xB0D99590, 1360 }, - { 0, 0xA0E9F520, 0xB0E9F520, 1360 }, - { 0, 0xA0BD5C90, 0xB0BD5C90, 1360 }, - { 0, 0xA04AAA60, 0xB04AAA60, 1360 }, - { 0, 0xA0E8C100, 0xB0E8C100, 1360 }, - { 0, 0xA06E4150, 0xB06E4150, 1360 }, - { 0, 0xA0130240, 0xB0130240, 1360 }, - { 0, 0xA04DDC80, 0xB04DDC80, 1360 }, - { 0, 0xA00AE510, 0xB00AE510, 1360 }, - { 0, 0xA06B3F00, 0xB06B3F00, 1360 }, - { 0, 0xA08861C0, 0xB08861C0, 1360 }, - { 0, 0xA05B04A0, 0xB05B04A0, 1360 }, - { 0, 0xA0167EC0, 0xB0167EC0, 1360 }, - { 0, 0xA047B800, 0xB047B800, 1360 }, - { 0, 0xA0C0D3C0, 0xB0C0D3C0, 1360 }, - { 0, 0xA0F415A0, 0xB0F415A0, 1360 }, - { 0, 0xA06AF9F0, 0xB06AF9F0, 1360 }, - { 0, 0xA0484770, 0xB0484770, 1360 }, - { 0, 0xA0DED5A0, 0xB0DED5A0, 1360 }, - { 0, 0xA0A9BAF0, 0xB0A9BAF0, 1360 }, - { 0, 0xA08683A0, 0xB08683A0, 1360 }, - { 0, 0xA0DA8F40, 0xB0DA8F40, 1360 }, - { 0, 0xA09BFE10, 0xB09BFE10, 1360 }, - { 0, 0xA0308F40, 0xB0308F40, 1360 }, - { 0, 0xA05A0AF0, 0xB05A0AF0, 1360 }, - { 0, 0xA02F75B0, 0xB02F75B0, 1360 }, - { 0, 0xA053D680, 0xB053D680, 1360 }, - { 0, 0xA0FD4710, 0xB0FD4710, 1360 }, - { 0, 0xA0BEDB10, 0xB0BEDB10, 1360 }, - { 0, 0xA0B73D60, 0xB0B73D60, 1360 }, - { 0, 0xA0595100, 0xB0595100, 1360 }, - { 0, 0xA0FDFBB0, 0xB0FDFBB0, 1360 }, - { 0, 0xA0C6BDD0, 0xB0C6BDD0, 1360 }, - { 0, 0xA091A870, 0xB091A870, 1360 }, - { 0, 0xA0C66380, 0xB0C66380, 1360 }, - { 0, 0xA087C7B0, 0xB087C7B0, 1360 }, - { 0, 0xA07B0F20, 0xB07B0F20, 1360 }, - { 0, 0xA04A8FD0, 0xB04A8FD0, 1360 }, - { 0, 0xA02F0620, 0xB02F0620, 1360 }, - { 0, 0xA0AD3CC0, 0xB0AD3CC0, 1360 }, - { 0, 0xA0A7C790, 0xB0A7C790, 1360 }, - { 0, 0xA01EE650, 0xB01EE650, 1360 }, - { 0, 0xA00FFFF0, 0xB00FFFF0, 1360 }, - { 0, 0xA0254540, 0xB0254540, 1360 }, - { 0, 0xA033F680, 0xB033F680, 1360 }, - { 0, 0xA0D55480, 0xB0D55480, 1360 }, - { 0, 0xA0366410, 0xB0366410, 1360 }, - { 0, 0xA0E75D10, 0xB0E75D10, 1360 }, - { 0, 0xA08F8540, 0xB08F8540, 1360 }, - { 0, 0xA0CAC470, 0xB0CAC470, 1360 }, - { 0, 0xA0159500, 0xB0159500, 1360 }, - { 0, 0xA082D200, 0xB082D200, 1360 }, - { 0, 0xA081BDC0, 0xB081BDC0, 1360 }, - { 0, 0xA0CA99F0, 0xB0CA99F0, 1360 }, - { 0, 0xA09F2040, 0xB09F2040, 1360 }, - { 0, 0xA0B3E610, 0xB0B3E610, 1360 }, - { 0, 0xA0557A30, 0xB0557A30, 1360 }, - { 0, 0xA0BC1880, 0xB0BC1880, 1360 }, - { 0, 0xA003E6C0, 0xB003E6C0, 1360 }, - { 0, 0xA0E747D0, 0xB0E747D0, 1360 }, - { 0, 0xA0F50A00, 0xB0F50A00, 1360 }, - { 0, 0xA026EE40, 0xB026EE40, 1360 }, - { 0, 0xA0E7C750, 0xB0E7C750, 1360 }, - { 0, 0xA0B68E10, 0xB0B68E10, 1360 }, - { 0, 0xA0FF4A60, 0xB0FF4A60, 1360 }, - { 0, 0xA05AB4F0, 0xB05AB4F0, 1360 }, - { 0, 0xA0D9EA90, 0xB0D9EA90, 1360 }, - { 0, 0xA073A690, 0xB073A690, 1360 }, - { 0, 0xA025E9F0, 0xB025E9F0, 1360 }, - { 0, 0xA063C680, 0xB063C680, 1360 }, - { 0, 0xA093D0F0, 0xB093D0F0, 1360 }, - { 0, 0xA035C4B0, 0xB035C4B0, 1360 }, - { 0, 0xA09A3FD0, 0xB09A3FD0, 1360 }, - { 0, 0xA0011990, 0xB0011990, 1360 }, - { 0, 0xA0F57EE0, 0xB0F57EE0, 1360 }, - { 0, 0xA0F4AFB0, 0xB0F4AFB0, 1360 }, - { 0, 0xA0598B70, 0xB0598B70, 1360 }, - { 0, 0xA0AA2FD0, 0xB0AA2FD0, 1360 }, - { 0, 0xA03CBDB0, 0xB03CBDB0, 1360 }, - { 0, 0xA0AC9810, 0xB0AC9810, 1360 }, - { 0, 0xA0242BB0, 0xB0242BB0, 1360 }, - { 0, 0xA0D49540, 0xB0D49540, 1360 }, - { 0, 0xA06574D0, 0xB06574D0, 1360 }, - { 0, 0xA0D93B40, 0xB0D93B40, 1360 }, - { 0, 0xA0CF0AD0, 0xB0CF0AD0, 1360 }, - { 0, 0xA0439C20, 0xB0439C20, 1360 }, - { 0, 0xA07F2060, 0xB07F2060, 1360 }, - { 0, 0xA036E8E0, 0xB036E8E0, 1360 }, - { 0, 0xA0B76290, 0xB0B76290, 1360 }, - { 0, 0xA0B45050, 0xB0B45050, 1360 }, - { 0, 0xA0002FD0, 0xB0002FD0, 1360 }, - { 0, 0xA0CBA390, 0xB0CBA390, 1360 }, - { 0, 0xA06E3160, 0xB06E3160, 1360 }, - { 0, 0xA0A61E90, 0xB0A61E90, 1360 }, - { 0, 0xA0069EB0, 0xB0069EB0, 1360 }, - { 0, 0xA0260480, 0xB0260480, 1360 }, - { 0, 0xA07B6970, 0xB07B6970, 1360 }, - { 0, 0xA0688C60, 0xB0688C60, 1360 }, - { 0, 0xA05168F0, 0xB05168F0, 1360 }, - { 0, 0xA013B190, 0xB013B190, 1360 }, - { 0, 0xA051E320, 0xB051E320, 1360 }, - { 0, 0xA0C0E3B0, 0xB0C0E3B0, 1360 }, - { 0, 0xA01AC520, 0xB01AC520, 1360 }, - { 0, 0xA01D1D70, 0xB01D1D70, 1360 }, - { 0, 0xA0F8D630, 0xB0F8D630, 1360 }, - { 0, 0xA0A53A20, 0xB0A53A20, 1360 }, - { 0, 0xA0178310, 0xB0178310, 1360 }, - { 0, 0xA0B51A30, 0xB0B51A30, 1360 }, - { 0, 0xA02ABFC0, 0xB02ABFC0, 1360 }, - { 0, 0xA02BA430, 0xB02BA430, 1360 }, - { 0, 0xA0E04ED0, 0xB0E04ED0, 1360 }, - { 0, 0xA0A19870, 0xB0A19870, 1360 }, - { 0, 0xA0BAE9B0, 0xB0BAE9B0, 1360 }, - { 0, 0xA0382250, 0xB0382250, 1360 }, - { 0, 0xA05A1AE0, 0xB05A1AE0, 1360 }, - { 0, 0xA0B36690, 0xB0B36690, 1360 }, - { 0, 0xA0CE3BA0, 0xB0CE3BA0, 1360 }, - { 0, 0xA08FDA40, 0xB08FDA40, 1360 }, - { 0, 0xA0480260, 0xB0480260, 1360 }, - { 0, 0xA0B757F0, 0xB0B757F0, 1360 }, - { 0, 0xA0F82C30, 0xB0F82C30, 1360 }, - { 0, 0xA0EA89E0, 0xB0EA89E0, 1360 }, - { 0, 0xA04460B0, 0xB04460B0, 1360 }, - { 0, 0xA0F26200, 0xB0F26200, 1360 }, - { 0, 0xA069FAF0, 0xB069FAF0, 1360 }, - { 0, 0xA087A7D0, 0xB087A7D0, 1360 }, - { 0, 0xA0E45AC0, 0xB0E45AC0, 1360 }, - { 0, 0xA07EF5E0, 0xB07EF5E0, 1360 }, - { 0, 0xA094EFD0, 0xB094EFD0, 1360 }, - { 0, 0xA0AFF4B0, 0xB0AFF4B0, 1360 }, - { 0, 0xA0998090, 0xB0998090, 1360 }, - { 0, 0xA0292160, 0xB0292160, 1360 }, - { 0, 0xA0544610, 0xB0544610, 1360 }, - { 0, 0xA04C6350, 0xB04C6350, 1360 }, - { 0, 0xA015C4D0, 0xB015C4D0, 1360 }, - { 0, 0xA072F1F0, 0xB072F1F0, 1360 }, - { 0, 0xA0072380, 0xB0072380, 1360 }, - { 0, 0xA0C801E0, 0xB0C801E0, 1360 }, - { 0, 0xA0BC52F0, 0xB0BC52F0, 1360 }, - { 0, 0xA04E3C20, 0xB04E3C20, 1360 }, - { 0, 0xA0C811D0, 0xB0C811D0, 1360 }, - { 0, 0xA04ADF80, 0xB04ADF80, 1360 }, - { 0, 0xA0026D90, 0xB0026D90, 1360 }, - { 0, 0xA0182270, 0xB0182270, 1360 }, - { 0, 0xA0F0A910, 0xB0F0A910, 1360 }, - { 0, 0xA0D68DF0, 0xB0D68DF0, 1360 }, - { 0, 0xA0140140, 0xB0140140, 1360 }, - { 0, 0xA04DD1E0, 0xB04DD1E0, 1360 }, - { 0, 0xA016E900, 0xB016E900, 1360 }, - { 0, 0xA00AAAA0, 0xB00AAAA0, 1360 }, - { 0, 0xA0705490, 0xB0705490, 1360 }, - { 0, 0xA0181280, 0xB0181280, 1360 }, - { 0, 0xA0AECB30, 0xB0AECB30, 1360 }, - { 0, 0xA050E970, 0xB050E970, 1360 }, - { 0, 0xA05EABA0, 0xB05EABA0, 1360 }, - { 0, 0xA0E37100, 0xB0E37100, 1360 }, - { 0, 0xA0A50A50, 0xB0A50A50, 1360 }, - { 0, 0xA048D6E0, 0xB048D6E0, 1360 }, - { 0, 0xA0B752A0, 0xB0B752A0, 1360 }, - { 0, 0xA02CF830, 0xB02CF830, 1360 }, - { 0, 0xA0F5EE70, 0xB0F5EE70, 1360 }, - { 0, 0xA0C22270, 0xB0C22270, 1360 }, - { 0, 0xA0C3E600, 0xB0C3E600, 1360 }, - { 0, 0xA0A0B400, 0xB0A0B400, 1360 }, - { 0, 0xA0529D10, 0xB0529D10, 1360 }, - { 0, 0xA0A0CE90, 0xB0A0CE90, 1360 }, - { 0, 0xA08A6510, 0xB08A6510, 1360 }, - { 0, 0xA040B9B0, 0xB040B9B0, 1360 }, - { 0, 0xA0200FD0, 0xB0200FD0, 1360 }, - { 0, 0xA020F440, 0xB020F440, 1360 }, - { 0, 0xA0E009C0, 0xB0E009C0, 1360 }, - { 0, 0xA0928CE0, 0xB0928CE0, 1360 }, - { 0, 0xA07871C0, 0xB07871C0, 1360 }, - { 0, 0xA08FFF70, 0xB08FFF70, 1360 }, - { 0, 0xA08BC3B0, 0xB08BC3B0, 1360 }, - { 0, 0xA09EC5F0, 0xB09EC5F0, 1360 }, - { 0, 0xA0F7E1D0, 0xB0F7E1D0, 1360 }, - { 0, 0xA0126830, 0xB0126830, 1360 }, - { 0, 0xA0E4EF80, 0xB0E4EF80, 1360 }, - { 0, 0xA0DE2BA0, 0xB0DE2BA0, 1360 }, - { 0, 0xA0DBB370, 0xB0DBB370, 1360 }, - { 0, 0xA02173C0, 0xB02173C0, 1360 }, - { 0, 0xA0149B50, 0xB0149B50, 1360 }, - { 0, 0xA088E140, 0xB088E140, 1360 }, - { 0, 0xA0F79770, 0xB0F79770, 1360 }, - { 0, 0xA0735C30, 0xB0735C30, 1360 }, - { 0, 0xA0252560, 0xB0252560, 1360 }, - { 0, 0xA05485D0, 0xB05485D0, 1360 }, - { 0, 0xA04123F0, 0xB04123F0, 1360 }, - { 0, 0xA040A9C0, 0xB040A9C0, 1360 }, - { 0, 0xA0B653A0, 0xB0B653A0, 1360 }, - { 0, 0xA09886E0, 0xB09886E0, 1360 }, - { 0, 0xA02FA580, 0xB02FA580, 1360 }, - { 0, 0xA03E6160, 0xB03E6160, 1360 }, - { 0, 0xA05EB0F0, 0xB05EB0F0, 1360 }, - { 0, 0xA09D4770, 0xB09D4770, 1360 }, - { 0, 0xA054EAC0, 0xB054EAC0, 1360 }, - { 0, 0xA019A0F0, 0xB019A0F0, 1360 }, - { 0, 0xA096A8C0, 0xB096A8C0, 1360 }, - { 0, 0xA0BB1980, 0xB0BB1980, 1360 }, -}; - -static const uint8_t __attribute__((section(".pdcp_src"), used)) pdcp_src_data[NUM_SRC_SLOTS][PDU_STRIDE] = { - [9] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 0x5F, 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F, 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F, 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0x9B, 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Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -// Author: Zexin Fu - -#ifndef PDCP_PKG_H -#define PDCP_PKG_H - -#include - -typedef struct { - int user_id; - unsigned int src_addr; - unsigned int tgt_addr; - unsigned int pkg_length; -} pdcp_pkg_t; - -#define NUM_SRC_SLOTS 12336 -#define PDU_SIZE 1360 -#define PDU_STRIDE 1360 -#define NUM_PKGS 4 -#define ACTIVE_USER_NUMBER 1 - -#define NUM_PRODUCER_CORES 2 -static const unsigned int producer_core_ids[NUM_PRODUCER_CORES] = {0, 1}; -#define NUM_CONSUMER_CORES 2 -static const unsigned int consumer_core_ids[NUM_CONSUMER_CORES] = {2, 3}; -#define NUM_RLC_KERNEL_CORES (NUM_PRODUCER_CORES + NUM_CONSUMER_CORES) -static const unsigned int rlc_kernel_core_ids[NUM_RLC_KERNEL_CORES] = {0, 1, 2, 3}; - -static const pdcp_pkg_t __attribute__((section(".pdcp_info"), used)) pdcp_pkgs[NUM_PKGS] = { - { 0, 0xA0D965C0, 0xB0D965C0, 1360 }, - { 0, 0xA025DA00, 0xB025DA00, 1360 }, - { 0, 0xA0087CD0, 0xB0087CD0, 1360 }, - { 0, 0xA0FC1D90, 0xB0FC1D90, 1360 }, -}; - -static const uint8_t __attribute__((section(".pdcp_src"), used)) pdcp_src_data[NUM_SRC_SLOTS][PDU_STRIDE] = { - [409] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF, 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 0xD0, 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file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -// Author: Zexin Fu - -#ifndef PDCP_PKG_H -#define PDCP_PKG_H - -typedef struct { - int user_id; - unsigned int src_addr; - unsigned int tgt_addr; - unsigned int pkg_length; -} pdcp_pkg_t; - -#define NUM_SRC_SLOTS 131072 -#define PDU_SIZE 2048 -#define NUM_PKGS 100 - -static const pdcp_pkg_t __attribute__((section(".pdcp_info"))) pdcp_pkgs[NUM_PKGS] = { - { 0, 0xA0CF5800, 0xB0CF5800, 2048 }, - { 0, 0xACB09800, 0xBCB09800, 2048 }, - { 0, 0xA957C800, 0xB957C800, 2048 }, - { 0, 0xA5BAC800, 0xB5BAC800, 2048 }, - { 0, 0xA021E000, 0xB021E000, 2048 }, - { 0, 0xAB569000, 0xBB569000, 2048 }, - { 0, 0xA6BA8800, 0xB6BA8800, 2048 }, - { 0, 0xAD84D800, 0xBD84D800, 2048 }, - { 0, 0xA6CF9800, 0xB6CF9800, 2048 }, - { 0, 0xAF428800, 0xBF428800, 2048 }, - { 0, 0xAAC95000, 0xBAC95000, 2048 }, - { 0, 0xA7549800, 0xB7549800, 2048 }, - { 0, 0xAAB68000, 0xBAB68000, 2048 }, - { 0, 0xA7F46800, 0xB7F46800, 2048 }, - { 0, 0xAFFD4000, 0xBFFD4000, 2048 }, - { 0, 0xA60E4800, 0xB60E4800, 2048 }, - { 0, 0xA1D88800, 0xB1D88800, 2048 }, - { 0, 0xAE016000, 0xBE016000, 2048 }, - { 0, 0xACD1C000, 0xBCD1C000, 2048 }, - { 0, 0xAE9E5800, 0xBE9E5800, 2048 }, - { 0, 0xA9C23000, 0xB9C23000, 2048 }, - { 0, 0xA8727000, 0xB8727000, 2048 }, - { 0, 0xACFC8800, 0xBCFC8800, 2048 }, - { 0, 0xAFDDA000, 0xBFDDA000, 2048 }, - { 0, 0xA67B6000, 0xB67B6000, 2048 }, - { 0, 0xAA584000, 0xBA584000, 2048 }, - { 0, 0xA66F0000, 0xB66F0000, 2048 }, - { 0, 0xACA1F800, 0xBCA1F800, 2048 }, - { 0, 0xA2436000, 0xB2436000, 2048 }, - { 0, 0xA5835800, 0xB5835800, 2048 }, - { 0, 0xAA2AE000, 0xBA2AE000, 2048 }, - { 0, 0xA29F4000, 0xB29F4000, 2048 }, - { 0, 0xA6040800, 0xB6040800, 2048 }, - { 0, 0xA508B000, 0xB508B000, 2048 }, - { 0, 0xA6658800, 0xB6658800, 2048 }, - { 0, 0xA563D000, 0xB563D000, 2048 }, - { 0, 0xADDEF000, 0xBDDEF000, 2048 }, - { 0, 0xAFBD5800, 0xBFBD5800, 2048 }, - { 0, 0xADDF9800, 0xBDDF9800, 2048 }, - { 0, 0xAFACF000, 0xBFACF000, 2048 }, - { 0, 0xA699B000, 0xB699B000, 2048 }, - { 0, 0xA9198800, 0xB9198800, 2048 }, - { 0, 0xA4FC3800, 0xB4FC3800, 2048 }, - { 0, 0xAEC1C000, 0xBEC1C000, 2048 }, - { 0, 0xA92E1800, 0xB92E1800, 2048 }, - { 0, 0xAC211000, 0xBC211000, 2048 }, - { 0, 0xA0AA9800, 0xB0AA9800, 2048 }, - { 0, 0xA1704000, 0xB1704000, 2048 }, - { 0, 0xA73E9000, 0xB73E9000, 2048 }, - { 0, 0xA2E06000, 0xB2E06000, 2048 }, - { 0, 0xA0677800, 0xB0677800, 2048 }, - { 0, 0xAF352800, 0xBF352800, 2048 }, - { 0, 0xA2F5F800, 0xB2F5F800, 2048 }, - { 0, 0xADCE1000, 0xBDCE1000, 2048 }, - { 0, 0xA0E7E800, 0xB0E7E800, 2048 }, - { 0, 0xA308D000, 0xB308D000, 2048 }, - { 0, 0xAC6F8000, 0xBC6F8000, 2048 }, - { 0, 0xACF3D800, 0xBCF3D800, 2048 }, - { 0, 0xA6F71800, 0xB6F71800, 2048 }, - { 0, 0xA5198800, 0xB5198800, 2048 }, - { 0, 0xA4C57000, 0xB4C57000, 2048 }, - { 0, 0xAE8FC800, 0xBE8FC800, 2048 }, - { 0, 0xAB4B1800, 0xBB4B1800, 2048 }, - { 0, 0xA83D2800, 0xB83D2800, 2048 }, - { 0, 0xADF6E000, 0xBDF6E000, 2048 }, - { 0, 0xA883C800, 0xB883C800, 2048 }, - { 0, 0xA3B7C800, 0xB3B7C800, 2048 }, - { 0, 0xA7B18800, 0xB7B18800, 2048 }, - { 0, 0xA2571800, 0xB2571800, 2048 }, - { 0, 0xA08A5000, 0xB08A5000, 2048 }, - { 0, 0xA4229000, 0xB4229000, 2048 }, - { 0, 0xAD7C3000, 0xBD7C3000, 2048 }, - { 0, 0xAF8DD000, 0xBF8DD000, 2048 }, - { 0, 0xA77AE000, 0xB77AE000, 2048 }, - { 0, 0xAD51E000, 0xBD51E000, 2048 }, - { 0, 0xA54DF000, 0xB54DF000, 2048 }, - { 0, 0xACDEA000, 0xBCDEA000, 2048 }, - { 0, 0xA026C800, 0xB026C800, 2048 }, - { 0, 0xA7FC7800, 0xB7FC7800, 2048 }, - { 0, 0xA8D3F800, 0xB8D3F800, 2048 }, - { 0, 0xAFBD9800, 0xBFBD9800, 2048 }, - { 0, 0xA770B000, 0xB770B000, 2048 }, - { 0, 0xA7D20800, 0xB7D20800, 2048 }, - { 0, 0xA5715800, 0xB5715800, 2048 }, - { 0, 0xAFD43000, 0xBFD43000, 2048 }, - { 0, 0xA6B24000, 0xB6B24000, 2048 }, - { 0, 0xAAF18800, 0xBAF18800, 2048 }, - { 0, 0xA0C36800, 0xB0C36800, 2048 }, - { 0, 0xA83D2000, 0xB83D2000, 2048 }, - { 0, 0xA815D800, 0xB815D800, 2048 }, - { 0, 0xA1CFB000, 0xB1CFB000, 2048 }, - { 0, 0xAA19C000, 0xBA19C000, 2048 }, - { 0, 0xAAEAD800, 0xBAEAD800, 2048 }, - { 0, 0xA9FA7800, 0xB9FA7800, 2048 }, - { 0, 0xAB4AF800, 0xBB4AF800, 2048 }, - { 0, 0xA3362000, 0xB3362000, 2048 }, - { 0, 0xAAFD8800, 0xBAFD8800, 2048 }, - { 0, 0xABBDF800, 0xBBBDF800, 2048 }, - { 0, 0xA3E8A000, 0xB3E8A000, 2048 }, - { 0, 0xA0C8B000, 0xB0C8B000, 2048 }, -}; - -static const uint8_t __attribute__((section(".pdcp_src"))) pdcp_src_data[NUM_SRC_SLOTS][PDU_SIZE] = { - [1084] = { 0x00, 0x00, 0x00, 0x00, 0x3C, 0x3C, 0x3C, 0x3C, 0x3C, 0x3C, 0x3C, 0x3C, 0x3C, 0x3C, 0x3C, 0x3C, 0x3C, 0x3C, 0x3C, 0x3C, 0x3C, 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b/software/rlc/multi_producer_single_consumer_double_linked_list/data/data_24_1350_24.h deleted file mode 100644 index a236581..0000000 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/data/data_24_1350_24.h +++ /dev/null @@ -1,99 +0,0 @@ - -// Copyright 2025 ETH Zurich and University of Bologna. -// -// SPDX-License-Identifier: Apache-2.0 -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -// Author: Zexin Fu - -#ifndef PDCP_PKG_H -#define PDCP_PKG_H - -#include - -typedef struct { - int user_id; - unsigned int src_addr; - unsigned int tgt_addr; - unsigned int pkg_length; -} pdcp_pkg_t; - -#define NUM_SRC_SLOTS 12336 -#define PDU_SIZE 1360 -#define PDU_STRIDE 1360 -#define NUM_PKGS 24 -#define ACTIVE_USER_NUMBER 24 - -#define NUM_PRODUCER_CORES 2 -static const unsigned int producer_core_ids[NUM_PRODUCER_CORES] = {0, 1}; -#define NUM_CONSUMER_CORES 2 -static const unsigned int consumer_core_ids[NUM_CONSUMER_CORES] = {2, 3}; -#define NUM_RLC_KERNEL_CORES (NUM_PRODUCER_CORES + NUM_CONSUMER_CORES) -static const unsigned int rlc_kernel_core_ids[NUM_RLC_KERNEL_CORES] = {0, 1, 2, 3}; - -static const pdcp_pkg_t __attribute__((section(".pdcp_info"), used)) pdcp_pkgs[NUM_PKGS] = { - { 17, 0xA0D965C0, 0xB0D965C0, 1360 }, - { 6, 0xA025DA00, 0xB025DA00, 1360 }, - { 22, 0xA0087CD0, 0xB0087CD0, 1360 }, - { 20, 0xA0FC1D90, 0xB0FC1D90, 1360 }, - { 22, 0xA05D8220, 0xB05D8220, 1360 }, - { 17, 0xA05341C0, 0xB05341C0, 1360 }, - { 13, 0xA04BE3D0, 0xB04BE3D0, 1360 }, - { 7, 0xA02F7060, 0xB02F7060, 1360 }, - { 14, 0xA0FA64A0, 0xB0FA64A0, 1360 }, - { 18, 0xA022D7B0, 0xB022D7B0, 1360 }, - { 8, 0xA0E613B0, 0xB0E613B0, 1360 }, - { 0, 0xA0FBD330, 0xB0FBD330, 1360 }, - { 5, 0xA0B96B30, 0xB0B96B30, 1360 }, - { 22, 0xA01D8D00, 0xB01D8D00, 1360 }, - { 13, 0xA0C8C120, 0xB0C8C120, 1360 }, - { 10, 0xA08F7000, 0xB08F7000, 1360 }, - { 8, 0xA00ACA80, 0xB00ACA80, 1360 }, - { 4, 0xA00A2080, 0xB00A2080, 1360 }, - { 6, 0xA01FDAB0, 0xB01FDAB0, 1360 }, - { 10, 0xA04A5560, 0xB04A5560, 1360 }, - { 3, 0xA04F15F0, 0xB04F15F0, 1360 }, - { 2, 0xA0ABCE30, 0xB0ABCE30, 1360 }, - { 12, 0xA0CCAD30, 0xB0CCAD30, 1360 }, - { 3, 0xA00901A0, 0xB00901A0, 1360 }, -}; - -static const uint8_t __attribute__((section(".pdcp_src"), used)) pdcp_src_data[NUM_SRC_SLOTS][PDU_STRIDE] = { - [409] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 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a/software/rlc/multi_producer_single_consumer_double_linked_list/data/data_256_800_300.h +++ /dev/null @@ -1,644 +0,0 @@ - -// Copyright 2025 ETH Zurich and University of Bologna. -// -// SPDX-License-Identifier: Apache-2.0 -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -// Author: Zexin Fu - -#ifndef PDCP_PKG_H -#define PDCP_PKG_H - -#include - -typedef struct { - int user_id; - unsigned int src_addr; - unsigned int tgt_addr; - unsigned int pkg_length; -} pdcp_pkg_t; - -#define NUM_SRC_SLOTS 20661 -#define PDU_SIZE 810 -#define PDU_STRIDE 812 -#define NUM_PKGS 300 -#define ACTIVE_USER_NUMBER 256 - -static const pdcp_pkg_t __attribute__((section(".pdcp_info"), used)) pdcp_pkgs[NUM_PKGS] = { - { 20, 0xA02D3300, 0xB02D3300, 810 }, - { 41, 0xA00A25C4, 0xB00A25C4, 810 }, - { 214, 0xA06FA8F0, 0xB06FA8F0, 810 }, - { 161, 0xA0636B20, 0xB0636B20, 810 }, - { 133, 0xA05A9F18, 0xB05A9F18, 810 }, - { 104, 0xA038A5D0, 0xB038A5D0, 810 }, - { 160, 0xA0299B28, 0xB0299B28, 810 }, - { 122, 0xA0DD6968, 0xB0DD6968, 810 }, - { 135, 0xA0234980, 0xB0234980, 810 }, - { 202, 0xA0EFBC9C, 0xB0EFBC9C, 810 }, - { 67, 0xA0AB4B2C, 0xB0AB4B2C, 810 }, - { 153, 0xA00CE5EC, 0xB00CE5EC, 810 }, - { 234, 0xA00C17C0, 0xB00C17C0, 810 }, - { 161, 0xA02609A8, 0xB02609A8, 810 }, - { 37, 0xA058C350, 0xB058C350, 810 }, - { 4, 0xA05E7334, 0xB05E7334, 810 }, - { 234, 0xA0CD2B14, 0xB0CD2B14, 810 }, - { 51, 0xA0F46868, 0xB0F46868, 810 }, - { 37, 0xA00AC45C, 0xB00AC45C, 810 }, - { 109, 0xA0E3DAC8, 0xB0E3DAC8, 810 }, - { 135, 0xA050B8C4, 0xB050B8C4, 810 }, - { 67, 0xA0DD3D00, 0xB0DD3D00, 810 }, - { 178, 0xA0AA5098, 0xB0AA5098, 810 }, - { 35, 0xA0597E74, 0xB0597E74, 810 }, - { 125, 0xA0B65ED4, 0xB0B65ED4, 810 }, - { 189, 0xA0EF3DBC, 0xB0EF3DBC, 810 }, - { 145, 0xA070EFA4, 0xB070EFA4, 810 }, - { 80, 0xA002A070, 0xB002A070, 810 }, - { 224, 0xA040D014, 0xB040D014, 810 }, - { 154, 0xA0AB9420, 0xB0AB9420, 810 }, - { 4, 0xA08A233C, 0xB08A233C, 810 }, - { 153, 0xA070CFEC, 0xB070CFEC, 810 }, - { 53, 0xA03F1D88, 0xB03F1D88, 810 }, - { 68, 0xA0576994, 0xB0576994, 810 }, - { 135, 0xA088A69C, 0xB088A69C, 810 }, - { 59, 0xA0297E9C, 0xB0297E9C, 810 }, - { 54, 0xA025A754, 0xB025A754, 810 }, - { 79, 0xA09A3EAC, 0xB09A3EAC, 810 }, - { 139, 0xA02743AC, 0xB02743AC, 810 }, - { 144, 0xA091BEC4, 0xB091BEC4, 810 }, - { 107, 0xA08BA308, 0xB08BA308, 810 }, - { 175, 0xA0F51A08, 0xB0F51A08, 810 }, - { 104, 0xA06B62A4, 0xB06B62A4, 810 }, - { 135, 0xA011A194, 0xB011A194, 810 }, - { 250, 0xA0BA8568, 0xB0BA8568, 810 }, - { 128, 0xA0D9B504, 0xB0D9B504, 810 }, - { 26, 0xA032ACF8, 0xB032ACF8, 810 }, - { 47, 0xA099ACC4, 0xB099ACC4, 810 }, - { 216, 0xA01FFDC8, 0xB01FFDC8, 810 }, - { 141, 0xA0E0200C, 0xB0E0200C, 810 }, - { 22, 0xA0770508, 0xB0770508, 810 }, - { 1, 0xA0FF3974, 0xB0FF3974, 810 }, - { 170, 0xA0FB1C64, 0xB0FB1C64, 810 }, - { 66, 0xA092D2B8, 0xB092D2B8, 810 }, - { 134, 0xA0EA6588, 0xB0EA6588, 810 }, - { 82, 0xA04E0ED0, 0xB04E0ED0, 810 }, - { 226, 0xA01C3CB4, 0xB01C3CB4, 810 }, - { 218, 0xA01298FC, 0xB01298FC, 810 }, - { 4, 0xA05C8464, 0xB05C8464, 810 }, - { 57, 0xA0757BB8, 0xB0757BB8, 810 }, - { 38, 0xA0206348, 0xB0206348, 810 }, - { 76, 0xA05E8310, 0xB05E8310, 810 }, - { 18, 0xA028FFBC, 0xB028FFBC, 810 }, - { 189, 0xA09A51B4, 0xB09A51B4, 810 }, - { 75, 0xA070D970, 0xB070D970, 810 }, - { 220, 0xA0B8148C, 0xB0B8148C, 810 }, - { 65, 0xA0941C98, 0xB0941C98, 810 }, - { 21, 0xA04206EC, 0xB04206EC, 810 }, - { 157, 0xA0964AD8, 0xB0964AD8, 810 }, - { 186, 0xA0903BCC, 0xB0903BCC, 810 }, - { 20, 0xA0550EEC, 0xB0550EEC, 810 }, - { 183, 0xA06C6390, 0xB06C6390, 810 }, - { 107, 0xA01CFB04, 0xB01CFB04, 810 }, - { 127, 0xA0F74EA0, 0xB0F74EA0, 810 }, - { 52, 0xA04578B4, 0xB04578B4, 810 }, - { 181, 0xA0D8DA28, 0xB0D8DA28, 810 }, - { 208, 0xA063619C, 0xB063619C, 810 }, - { 79, 0xA0425638, 0xB0425638, 810 }, - { 121, 0xA0BBAC64, 0xB0BBAC64, 810 }, - { 83, 0xA09A0BEC, 0xB09A0BEC, 810 }, - { 90, 0xA06D973C, 0xB06D973C, 810 }, - { 211, 0xA0E21EB8, 0xB0E21EB8, 810 }, - { 12, 0xA05928D0, 0xB05928D0, 810 }, - { 91, 0xA083A858, 0xB083A858, 810 }, - { 170, 0xA016B2E0, 0xB016B2E0, 810 }, - { 210, 0xA05CFCEC, 0xB05CFCEC, 810 }, - { 127, 0xA00D05A4, 0xB00D05A4, 810 }, - { 136, 0xA0801080, 0xB0801080, 810 }, - { 81, 0xA0A2DE4C, 0xB0A2DE4C, 810 }, - { 55, 0xA06CB2DC, 0xB06CB2DC, 810 }, - { 195, 0xA01ADCA0, 0xB01ADCA0, 810 }, - { 19, 0xA055A72C, 0xB055A72C, 810 }, - { 240, 0xA0E6454C, 0xB0E6454C, 810 }, - { 113, 0xA07FC134, 0xB07FC134, 810 }, - { 102, 0xA0565274, 0xB0565274, 810 }, - { 235, 0xA0CAAD88, 0xB0CAAD88, 810 }, - { 179, 0xA0A0A030, 0xB0A0A030, 810 }, - { 156, 0xA0BA4924, 0xB0BA4924, 810 }, - { 116, 0xA039FF8C, 0xB039FF8C, 810 }, - { 114, 0xA06B88B4, 0xB06B88B4, 810 }, - { 12, 0xA038AF54, 0xB038AF54, 810 }, - { 98, 0xA0641FEC, 0xB0641FEC, 810 }, - { 204, 0xA0E3E778, 0xB0E3E778, 810 }, - { 168, 0xA0DAD27C, 0xB0DAD27C, 810 }, - { 142, 0xA06AAAAC, 0xB06AAAAC, 810 }, - { 35, 0xA0ED5544, 0xB0ED5544, 810 }, - { 142, 0xA0ADEEC8, 0xB0ADEEC8, 810 }, - { 179, 0xA0ECE96C, 0xB0ECE96C, 810 }, - { 204, 0xA0A22654, 0xB0A22654, 810 }, - { 169, 0xA092F59C, 0xB092F59C, 810 }, - { 14, 0xA0590918, 0xB0590918, 810 }, - { 59, 0xA03826F0, 0xB03826F0, 810 }, - { 133, 0xA0CEDDA0, 0xB0CEDDA0, 810 }, - { 91, 0xA0C85C64, 0xB0C85C64, 810 }, - { 135, 0xA024E5D8, 0xB024E5D8, 810 }, - { 19, 0xA0131E34, 0xB0131E34, 810 }, - { 55, 0xA02C8160, 0xB02C8160, 810 }, - { 222, 0xA03E0CC0, 0xB03E0CC0, 810 }, - { 176, 0xA0FEBDC0, 0xB0FEBDC0, 810 }, - { 160, 0xA040F2F8, 0xB040F2F8, 810 }, - { 223, 0xA0AB648C, 0xB0AB648C, 810 }, - { 59, 0xA0F223F4, 0xB0F223F4, 810 }, - { 197, 0xA019C8AC, 0xB019C8AC, 810 }, - { 97, 0xA09C3700, 0xB09C3700, 810 }, - { 130, 0xA09AED20, 0xB09AED20, 810 }, - { 22, 0xA0F1EE08, 0xB0F1EE08, 810 }, - { 223, 0xA0BE070C, 0xB0BE070C, 810 }, - { 0, 0xA0D6D1F8, 0xB0D6D1F8, 810 }, - { 100, 0xA06611E8, 0xB06611E8, 810 }, - { 186, 0xA0E09BC0, 0xB0E09BC0, 810 }, - { 220, 0xA004A8A0, 0xB004A8A0, 810 }, - { 35, 0xA02E800C, 0xB02E800C, 810 }, - { 169, 0xA0DA0124, 0xB0DA0124, 810 }, - { 160, 0xA06C53B4, 0xB06C53B4, 810 }, - { 63, 0xA08A19B8, 0xB08A19B8, 810 }, - { 153, 0xA02D4934, 0xB02D4934, 810 }, - { 158, 0xA07727EC, 0xB07727EC, 810 }, - { 209, 0xA0B08288, 0xB0B08288, 810 }, - { 167, 0xA04034A8, 0xB04034A8, 810 }, - { 206, 0xA0B83444, 0xB0B83444, 810 }, - { 151, 0xA0015038, 0xB0015038, 810 }, - { 65, 0xA06AED48, 0xB06AED48, 810 }, - { 98, 0xA0CB3C44, 0xB0CB3C44, 810 }, - { 215, 0xA0488828, 0xB0488828, 810 }, - { 194, 0xA0CE1C24, 0xB0CE1C24, 810 }, - { 89, 0xA02B3128, 0xB02B3128, 810 }, - { 154, 0xA0FDDC8C, 0xB0FDDC8C, 810 }, - { 207, 0xA07929C4, 0xB07929C4, 810 }, - { 0, 0xA0F73B98, 0xB0F73B98, 810 }, - { 155, 0xA050BF1C, 0xB050BF1C, 810 }, - { 146, 0xA097CDD0, 0xB097CDD0, 810 }, - { 107, 0xA04194BC, 0xB04194BC, 810 }, - { 220, 0xA0DAFBB8, 0xB0DAFBB8, 810 }, - { 164, 0xA0D750D8, 0xB0D750D8, 810 }, - { 238, 0xA0003918, 0xB0003918, 810 }, - { 226, 0xA0F32B38, 0xB0F32B38, 810 }, - { 226, 0xA083987C, 0xB083987C, 810 }, - { 109, 0xA0C65DB8, 0xB0C65DB8, 810 }, - { 242, 0xA007E7A8, 0xB007E7A8, 810 }, - { 86, 0xA02D68EC, 0xB02D68EC, 810 }, - { 43, 0xA0935E48, 0xB0935E48, 810 }, - { 145, 0xA07CD7D0, 0xB07CD7D0, 810 }, - { 171, 0xA0613688, 0xB0613688, 810 }, - { 47, 0xA0178438, 0xB0178438, 810 }, - { 120, 0xA061C870, 0xB061C870, 810 }, - { 158, 0xA0E65854, 0xB0E65854, 810 }, - { 115, 0xA01FF770, 0xB01FF770, 810 }, - { 101, 0xA022C448, 0xB022C448, 810 }, - { 75, 0xA0C54CF0, 0xB0C54CF0, 810 }, - { 12, 0xA01C16A4, 0xB01C16A4, 810 }, - { 23, 0xA0D84514, 0xB0D84514, 810 }, - { 125, 0xA0330C20, 0xB0330C20, 810 }, - { 243, 0xA0342014, 0xB0342014, 810 }, - { 37, 0xA0C0F6C8, 0xB0C0F6C8, 810 }, - { 233, 0xA0DF3554, 0xB0DF3554, 810 }, - { 212, 0xA04307D8, 0xB04307D8, 810 }, - { 99, 0xA06B9BBC, 0xB06B9BBC, 810 }, - { 196, 0xA0D639B8, 0xB0D639B8, 810 }, - { 253, 0xA0F64430, 0xB0F64430, 810 }, - { 204, 0xA0ABCA0C, 0xB0ABCA0C, 810 }, - { 124, 0xA055FCD0, 0xB055FCD0, 810 }, - { 75, 0xA0DAF234, 0xB0DAF234, 810 }, - { 2, 0xA051A9D4, 0xB051A9D4, 810 }, - { 54, 0xA07E8D88, 0xB07E8D88, 810 }, - { 217, 0xA0A1FD18, 0xB0A1FD18, 810 }, - { 112, 0xA0979B10, 0xB0979B10, 810 }, - { 90, 0xA0B1DC44, 0xB0B1DC44, 810 }, - { 237, 0xA0D21FD4, 0xB0D21FD4, 810 }, - { 25, 0xA0B74CB8, 0xB0B74CB8, 810 }, - { 127, 0xA031207C, 0xB031207C, 810 }, - { 62, 0xA064A524, 0xB064A524, 810 }, - { 233, 0xA05B3758, 0xB05B3758, 810 }, - { 68, 0xA019FE98, 0xB019FE98, 810 }, - { 237, 0xA0894208, 0xB0894208, 810 }, - { 162, 0xA008896C, 0xB008896C, 810 }, - { 226, 0xA0EED83C, 0xB0EED83C, 810 }, - { 218, 0xA0E0E188, 0xB0E0E188, 810 }, - { 228, 0xA05D6BF0, 0xB05D6BF0, 810 }, - { 81, 0xA0EEE818, 0xB0EEE818, 810 }, - { 243, 0xA0596840, 0xB0596840, 810 }, - { 230, 0xA002E964, 0xB002E964, 810 }, - { 132, 0xA01CD1C8, 0xB01CD1C8, 810 }, - { 126, 0xA017E68C, 0xB017E68C, 810 }, - { 141, 0xA05CF03C, 0xB05CF03C, 810 }, - { 248, 0xA01B5B80, 0xB01B5B80, 810 }, - { 122, 0xA00CBFDC, 0xB00CBFDC, 810 }, - { 140, 0xA08625E4, 0xB08625E4, 810 }, - { 225, 0xA01CC1EC, 0xB01CC1EC, 810 }, - { 39, 0xA0D0BC94, 0xB0D0BC94, 810 }, - { 146, 0xA0609E48, 0xB0609E48, 810 }, - { 120, 0xA0710F5C, 0xB0710F5C, 810 }, - { 139, 0xA0C513D8, 0xB0C513D8, 810 }, - { 171, 0xA056FA90, 0xB056FA90, 810 }, - { 163, 0xA0DAEBDC, 0xB0DAEBDC, 810 }, - { 41, 0xA035B614, 0xB035B614, 810 }, - { 70, 0xA0E7D4F4, 0xB0E7D4F4, 810 }, - { 77, 0xA0E9F02C, 0xB0E9F02C, 810 }, - { 118, 0xA0BFE600, 0xB0BFE600, 810 }, - { 196, 0xA062A678, 0xB062A678, 810 }, - { 78, 0xA0C005B8, 0xB0C005B8, 810 }, - { 109, 0xA0A54278, 0xB0A54278, 810 }, - { 32, 0xA04D4D54, 0xB04D4D54, 810 }, - { 212, 0xA0264918, 0xB0264918, 810 }, - { 208, 0xA02759E0, 0xB02759E0, 810 }, - { 169, 0xA0AEFF90, 0xB0AEFF90, 810 }, - { 238, 0xA08FD64C, 0xB08FD64C, 810 }, - { 212, 0xA0ABF674, 0xB0ABF674, 810 }, - { 31, 0xA0A6E528, 0xB0A6E528, 810 }, - { 105, 0xA0BD9B34, 0xB0BD9B34, 810 }, - { 215, 0xA015FE14, 0xB015FE14, 810 }, - { 199, 0xA027F220, 0xB027F220, 810 }, - { 10, 0xA0189B58, 0xB0189B58, 810 }, - { 194, 0xA0A3768C, 0xB0A3768C, 810 }, - { 244, 0xA089C0E8, 0xB089C0E8, 810 }, - { 3, 0xA02C5B50, 0xB02C5B50, 810 }, - { 180, 0xA064F144, 0xB064F144, 810 }, - { 152, 0xA04DC908, 0xB04DC908, 810 }, - { 199, 0xA04D3720, 0xB04D3720, 810 }, - { 214, 0xA0D9BB5C, 0xB0D9BB5C, 810 }, - { 112, 0xA0B62290, 0xB0B62290, 810 }, - { 249, 0xA038E86C, 0xB038E86C, 810 }, - { 112, 0xA0AB4800, 0xB0AB4800, 810 }, - { 139, 0xA04A7D50, 0xB04A7D50, 810 }, - { 223, 0xA07115B4, 0xB07115B4, 810 }, - { 248, 0xA0BBD274, 0xB0BBD274, 810 }, - { 14, 0xA06569CC, 0xB06569CC, 810 }, - { 199, 0xA01E9A88, 0xB01E9A88, 810 }, - { 172, 0xA0B3E7A0, 0xB0B3E7A0, 810 }, - { 207, 0xA0DF6E6C, 0xB0DF6E6C, 810 }, - { 84, 0xA027BF60, 0xB027BF60, 810 }, - { 239, 0xA01487CC, 0xB01487CC, 810 }, - { 65, 0xA0DB776C, 0xB0DB776C, 810 }, - { 13, 0xA005FC04, 0xB005FC04, 810 }, - { 201, 0xA025DD40, 0xB025DD40, 810 }, - { 13, 0xA05FF62C, 0xB05FF62C, 810 }, - { 42, 0xA043838C, 0xB043838C, 810 }, - { 219, 0xA0A4FFDC, 0xB0A4FFDC, 810 }, - { 69, 0xA0C52A0C, 0xB0C52A0C, 810 }, - { 236, 0xA0C36DFC, 0xB0C36DFC, 810 }, - { 93, 0xA056C7D0, 0xB056C7D0, 810 }, - { 25, 0xA0A2D19C, 0xB0A2D19C, 810 }, - { 133, 0xA017CD2C, 0xB017CD2C, 810 }, - { 194, 0xA042D518, 0xB042D518, 810 }, - { 167, 0xA099DC58, 0xB099DC58, 810 }, - { 108, 0xA000DE08, 0xB000DE08, 810 }, - { 232, 0xA09E81CC, 0xB09E81CC, 810 }, - { 167, 0xA06BAB98, 0xB06BAB98, 810 }, - { 172, 0xA0B8B97C, 0xB0B8B97C, 810 }, - { 194, 0xA073CF84, 0xB073CF84, 810 }, - { 142, 0xA0ABBD5C, 0xB0ABBD5C, 810 }, - { 215, 0xA0E1A304, 0xB0E1A304, 810 }, - { 129, 0xA0C595E4, 0xB0C595E4, 810 }, - { 41, 0xA03ED7C0, 0xB03ED7C0, 810 }, - { 240, 0xA04D1768, 0xB04D1768, 810 }, - { 9, 0xA07874F8, 0xB07874F8, 810 }, - { 26, 0xA05860FC, 0xB05860FC, 810 }, - { 179, 0xA017BD50, 0xB017BD50, 810 }, - { 114, 0xA0EB23D8, 0xB0EB23D8, 810 }, - { 35, 0xA0DC1F88, 0xB0DC1F88, 810 }, - { 20, 0xA018BE3C, 0xB018BE3C, 810 }, - { 15, 0xA07F5230, 0xB07F5230, 810 }, - { 126, 0xA01734EC, 0xB01734EC, 810 }, - { 102, 0xA0145B64, 0xB0145B64, 810 }, - { 10, 0xA0ED2C08, 0xB0ED2C08, 810 }, - { 78, 0xA0C19234, 0xB0C19234, 810 }, - { 122, 0xA0CC26FC, 0xB0CC26FC, 810 }, - { 64, 0xA0D7A024, 0xB0D7A024, 810 }, - { 242, 0xA03FE888, 0xB03FE888, 810 }, - { 58, 0xA0171534, 0xB0171534, 810 }, - { 111, 0xA0CE2C00, 0xB0CE2C00, 810 }, - { 238, 0xA020862C, 0xB020862C, 810 }, - { 131, 0xA04B718C, 0xB04B718C, 810 }, - { 188, 0xA01BD0DC, 0xB01BD0DC, 810 }, - { 85, 0xA0F19538, 0xB0F19538, 810 }, - { 58, 0xA01B9498, 0xB01B9498, 810 }, - { 83, 0xA05F7DA4, 0xB05F7DA4, 810 }, - { 159, 0xA0A3EBE8, 0xB0A3EBE8, 810 }, - { 55, 0xA030AB20, 0xB030AB20, 810 }, - { 13, 0xA0E74964, 0xB0E74964, 810 }, - { 159, 0xA063F384, 0xB063F384, 810 }, -}; - -static const uint8_t __attribute__((section(".pdcp_src"), used)) pdcp_src_data[NUM_SRC_SLOTS][PDU_STRIDE] = { - [18] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 0x5F, 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F, 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F, 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF, 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0xDF, 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 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copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -// Author: Zexin Fu - -#ifndef PDCP_PKG_H -#define PDCP_PKG_H - -#include - -typedef struct { - int user_id; - unsigned int src_addr; - unsigned int tgt_addr; - unsigned int pkg_length; -} pdcp_pkg_t; - -#define NUM_SRC_SLOTS 12336 -#define PDU_SIZE 1360 -#define PDU_STRIDE 1360 -#define NUM_PKGS 24 -#define ACTIVE_USER_NUMBER 32 - -#define NUM_PRODUCER_CORES 2 -static const unsigned int producer_core_ids[NUM_PRODUCER_CORES] = {0, 1}; -#define NUM_CONSUMER_CORES 2 -static const unsigned int consumer_core_ids[NUM_CONSUMER_CORES] = {2, 3}; -#define NUM_RLC_KERNEL_CORES (NUM_PRODUCER_CORES + NUM_CONSUMER_CORES) -static const unsigned int rlc_kernel_core_ids[NUM_RLC_KERNEL_CORES] = {0, 1, 2, 3}; - -static const pdcp_pkg_t __attribute__((section(".pdcp_info"), used)) pdcp_pkgs[NUM_PKGS] = { - { 12, 0xA0D965C0, 0xB0D965C0, 1360 }, - { 26, 0xA025DA00, 0xB025DA00, 1360 }, - { 14, 0xA0087CD0, 0xB0087CD0, 1360 }, - { 28, 0xA0FC1D90, 0xB0FC1D90, 1360 }, - { 17, 0xA05D8220, 0xB05D8220, 1360 }, - { 0, 0xA05341C0, 0xB05341C0, 1360 }, - { 10, 0xA04BE3D0, 0xB04BE3D0, 1360 }, - { 27, 0xA02F7060, 0xB02F7060, 1360 }, - { 21, 0xA0FA64A0, 0xB0FA64A0, 1360 }, - { 17, 0xA022D7B0, 0xB022D7B0, 1360 }, - { 9, 0xA0E613B0, 0xB0E613B0, 1360 }, - { 13, 0xA0FBD330, 0xB0FBD330, 1360 }, - { 21, 0xA0B96B30, 0xB0B96B30, 1360 }, - { 6, 0xA01D8D00, 0xB01D8D00, 1360 }, - { 5, 0xA0C8C120, 0xB0C8C120, 1360 }, - { 24, 0xA08F7000, 0xB08F7000, 1360 }, - { 6, 0xA00ACA80, 0xB00ACA80, 1360 }, - { 22, 0xA00A2080, 0xB00A2080, 1360 }, - { 22, 0xA01FDAB0, 0xB01FDAB0, 1360 }, - { 16, 0xA04A5560, 0xB04A5560, 1360 }, - { 2, 0xA04F15F0, 0xB04F15F0, 1360 }, - { 29, 0xA0ABCE30, 0xB0ABCE30, 1360 }, - { 7, 0xA0CCAD30, 0xB0CCAD30, 1360 }, - { 24, 0xA00901A0, 0xB00901A0, 1360 }, -}; - -static const uint8_t __attribute__((section(".pdcp_src"), used)) pdcp_src_data[NUM_SRC_SLOTS][PDU_STRIDE] = { - [409] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF, 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0xDF, 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 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0x9C, 0x9D, 0x9E, 0x9F, 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA }, -}; - -#endif // PDCP_PKG_H diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/data/data_48_1350_24.h b/software/rlc/multi_producer_single_consumer_double_linked_list/data/data_48_1350_24.h deleted file mode 100644 index 4bdaf4f..0000000 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/data/data_48_1350_24.h +++ /dev/null @@ -1,99 +0,0 @@ - -// Copyright 2025 ETH Zurich and University of Bologna. -// -// SPDX-License-Identifier: Apache-2.0 -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -// Author: Zexin Fu - -#ifndef PDCP_PKG_H -#define PDCP_PKG_H - -#include - -typedef struct { - int user_id; - unsigned int src_addr; - unsigned int tgt_addr; - unsigned int pkg_length; -} pdcp_pkg_t; - -#define NUM_SRC_SLOTS 12336 -#define PDU_SIZE 1360 -#define PDU_STRIDE 1360 -#define NUM_PKGS 24 -#define ACTIVE_USER_NUMBER 48 - -#define NUM_PRODUCER_CORES 2 -static const unsigned int producer_core_ids[NUM_PRODUCER_CORES] = {0, 1}; -#define NUM_CONSUMER_CORES 2 -static const unsigned int consumer_core_ids[NUM_CONSUMER_CORES] = {2, 3}; -#define NUM_RLC_KERNEL_CORES (NUM_PRODUCER_CORES + NUM_CONSUMER_CORES) -static const unsigned int rlc_kernel_core_ids[NUM_RLC_KERNEL_CORES] = {0, 1, 2, 3}; - -static const pdcp_pkg_t __attribute__((section(".pdcp_info"), used)) pdcp_pkgs[NUM_PKGS] = { - { 35, 0xA0D965C0, 0xB0D965C0, 1360 }, - { 12, 0xA025DA00, 0xB025DA00, 1360 }, - { 45, 0xA0087CD0, 0xB0087CD0, 1360 }, - { 41, 0xA0FC1D90, 0xB0FC1D90, 1360 }, - { 44, 0xA05D8220, 0xB05D8220, 1360 }, - { 34, 0xA05341C0, 0xB05341C0, 1360 }, - { 26, 0xA04BE3D0, 0xB04BE3D0, 1360 }, - { 14, 0xA02F7060, 0xB02F7060, 1360 }, - { 28, 0xA0FA64A0, 0xB0FA64A0, 1360 }, - { 37, 0xA022D7B0, 0xB022D7B0, 1360 }, - { 17, 0xA0E613B0, 0xB0E613B0, 1360 }, - { 0, 0xA0FBD330, 0xB0FBD330, 1360 }, - { 10, 0xA0B96B30, 0xB0B96B30, 1360 }, - { 44, 0xA01D8D00, 0xB01D8D00, 1360 }, - { 27, 0xA0C8C120, 0xB0C8C120, 1360 }, - { 21, 0xA08F7000, 0xB08F7000, 1360 }, - { 17, 0xA00ACA80, 0xB00ACA80, 1360 }, - { 9, 0xA00A2080, 0xB00A2080, 1360 }, - { 13, 0xA01FDAB0, 0xB01FDAB0, 1360 }, - { 21, 0xA04A5560, 0xB04A5560, 1360 }, - { 6, 0xA04F15F0, 0xB04F15F0, 1360 }, - { 5, 0xA0ABCE30, 0xB0ABCE30, 1360 }, - { 24, 0xA0CCAD30, 0xB0CCAD30, 1360 }, - { 6, 0xA00901A0, 0xB00901A0, 1360 }, -}; - -static const uint8_t __attribute__((section(".pdcp_src"), used)) pdcp_src_data[NUM_SRC_SLOTS][PDU_STRIDE] = { - [409] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF, 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0xDF, 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 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0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA }, -}; - -#endif // PDCP_PKG_H diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/data/data_48_1350_8.h b/software/rlc/multi_producer_single_consumer_double_linked_list/data/data_48_1350_8.h deleted file mode 100644 index ad5e8a7..0000000 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/data/data_48_1350_8.h +++ /dev/null @@ -1,67 +0,0 @@ - -// Copyright 2025 ETH Zurich and University of Bologna. -// -// SPDX-License-Identifier: Apache-2.0 -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -// Author: Zexin Fu - -#ifndef PDCP_PKG_H -#define PDCP_PKG_H - -#include - -typedef struct { - int user_id; - unsigned int src_addr; - unsigned int tgt_addr; - unsigned int pkg_length; -} pdcp_pkg_t; - -#define NUM_SRC_SLOTS 12336 -#define PDU_SIZE 1360 -#define PDU_STRIDE 1360 -#define NUM_PKGS 8 -#define ACTIVE_USER_NUMBER 48 - -#define NUM_PRODUCER_CORES 2 -static const unsigned int producer_core_ids[NUM_PRODUCER_CORES] = {0, 1}; -#define NUM_CONSUMER_CORES 2 -static const unsigned int consumer_core_ids[NUM_CONSUMER_CORES] = {2, 3}; -#define NUM_RLC_KERNEL_CORES (NUM_PRODUCER_CORES + NUM_CONSUMER_CORES) -static const unsigned int rlc_kernel_core_ids[NUM_RLC_KERNEL_CORES] = {0, 1, 2, 3}; - -static const pdcp_pkg_t __attribute__((section(".pdcp_info"), used)) pdcp_pkgs[NUM_PKGS] = { - { 47, 0xA0D965C0, 0xB0D965C0, 1360 }, - { 6, 0xA025DA00, 0xB025DA00, 1360 }, - { 43, 0xA0087CD0, 0xB0087CD0, 1360 }, - { 47, 0xA0FC1D90, 0xB0FC1D90, 1360 }, - { 34, 0xA05D8220, 0xB05D8220, 1360 }, - { 5, 0xA05341C0, 0xB05341C0, 1360 }, - { 37, 0xA04BE3D0, 0xB04BE3D0, 1360 }, - { 27, 0xA02F7060, 0xB02F7060, 1360 }, -}; - -static const uint8_t __attribute__((section(".pdcp_src"), used)) pdcp_src_data[NUM_SRC_SLOTS][PDU_STRIDE] = { - [409] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF, 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0xDF, 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 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// PDCP_PKG_H diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/data/data_48_800_1000.h b/software/rlc/multi_producer_single_consumer_double_linked_list/data/data_48_800_1000.h deleted file mode 100644 index 63dec64..0000000 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/data/data_48_800_1000.h +++ /dev/null @@ -1,2051 +0,0 @@ - -// Copyright 2025 ETH Zurich and University of Bologna. -// -// SPDX-License-Identifier: Apache-2.0 -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -// Author: Zexin Fu - -#ifndef PDCP_PKG_H -#define PDCP_PKG_H - -#include - -typedef struct { - int user_id; - unsigned int src_addr; - unsigned int tgt_addr; - unsigned int pkg_length; -} pdcp_pkg_t; - -#define NUM_SRC_SLOTS 20661 -#define PDU_SIZE 810 -#define PDU_STRIDE 812 -#define NUM_PKGS 1000 -#define ACTIVE_USER_NUMBER 48 - -#define NUM_PRODUCER_CORES 2 -static const unsigned int producer_core_ids[NUM_PRODUCER_CORES] = {0, 1}; -#define NUM_CONSUMER_CORES 2 -static const unsigned int consumer_core_ids[NUM_CONSUMER_CORES] = {2, 3}; -#define NUM_RLC_KERNEL_CORES (NUM_PRODUCER_CORES + NUM_CONSUMER_CORES) -static const unsigned int rlc_kernel_core_ids[NUM_RLC_KERNEL_CORES] = {0, 1, 2, 3}; - -static const pdcp_pkg_t __attribute__((section(".pdcp_info"), used)) pdcp_pkgs[NUM_PKGS] = { - { 34, 0xA02D3300, 0xB02D3300, 810 }, - { 24, 0xA00A25C4, 0xB00A25C4, 810 }, - { 29, 0xA06FA8F0, 0xB06FA8F0, 810 }, - { 20, 0xA0636B20, 0xB0636B20, 810 }, - { 12, 0xA05A9F18, 0xB05A9F18, 810 }, - { 44, 0xA038A5D0, 0xB038A5D0, 810 }, - { 15, 0xA0299B28, 0xB0299B28, 810 }, - { 36, 0xA0DD6968, 0xB0DD6968, 810 }, - { 24, 0xA0234980, 0xB0234980, 810 }, - { 14, 0xA0EFBC9C, 0xB0EFBC9C, 810 }, - { 26, 0xA0AB4B2C, 0xB0AB4B2C, 810 }, - { 2, 0xA00CE5EC, 0xB00CE5EC, 810 }, - { 20, 0xA00C17C0, 0xB00C17C0, 810 }, - { 47, 0xA02609A8, 0xB02609A8, 810 }, - { 30, 0xA058C350, 0xB058C350, 810 }, - { 45, 0xA05E7334, 0xB05E7334, 810 }, - { 24, 0xA0CD2B14, 0xB0CD2B14, 810 }, - { 24, 0xA0F46868, 0xB0F46868, 810 }, - { 42, 0xA00AC45C, 0xB00AC45C, 810 }, - { 41, 0xA0E3DAC8, 0xB0E3DAC8, 810 }, - { 9, 0xA050B8C4, 0xB050B8C4, 810 }, - { 31, 0xA0DD3D00, 0xB0DD3D00, 810 }, - { 2, 0xA0AA5098, 0xB0AA5098, 810 }, - { 8, 0xA0597E74, 0xB0597E74, 810 }, - { 32, 0xA0B65ED4, 0xB0B65ED4, 810 }, - { 37, 0xA0EF3DBC, 0xB0EF3DBC, 810 }, - { 21, 0xA070EFA4, 0xB070EFA4, 810 }, - { 6, 0xA002A070, 0xB002A070, 810 }, - { 28, 0xA040D014, 0xB040D014, 810 }, - { 6, 0xA0AB9420, 0xB0AB9420, 810 }, - { 33, 0xA08A233C, 0xB08A233C, 810 }, - { 29, 0xA070CFEC, 0xB070CFEC, 810 }, - { 0, 0xA03F1D88, 0xB03F1D88, 810 }, - { 46, 0xA0576994, 0xB0576994, 810 }, - { 9, 0xA088A69C, 0xB088A69C, 810 }, - { 26, 0xA0297E9C, 0xB0297E9C, 810 }, - { 41, 0xA025A754, 0xB025A754, 810 }, - { 9, 0xA09A3EAC, 0xB09A3EAC, 810 }, - { 4, 0xA02743AC, 0xB02743AC, 810 }, - { 30, 0xA091BEC4, 0xB091BEC4, 810 }, - { 16, 0xA08BA308, 0xB08BA308, 810 }, - { 21, 0xA0F51A08, 0xB0F51A08, 810 }, - { 39, 0xA06B62A4, 0xB06B62A4, 810 }, - { 44, 0xA011A194, 0xB011A194, 810 }, - { 25, 0xA0BA8568, 0xB0BA8568, 810 }, - { 41, 0xA0D9B504, 0xB0D9B504, 810 }, - { 5, 0xA032ACF8, 0xB032ACF8, 810 }, - { 21, 0xA099ACC4, 0xB099ACC4, 810 }, - { 43, 0xA01FFDC8, 0xB01FFDC8, 810 }, - { 34, 0xA0E0200C, 0xB0E0200C, 810 }, - { 24, 0xA0770508, 0xB0770508, 810 }, - { 20, 0xA0FF3974, 0xB0FF3974, 810 }, - { 40, 0xA0FB1C64, 0xB0FB1C64, 810 }, - { 45, 0xA092D2B8, 0xB092D2B8, 810 }, - { 31, 0xA0EA6588, 0xB0EA6588, 810 }, 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0xA0D0EC28, 0xB0D0EC28, 810 }, - { 23, 0xA000755C, 0xB000755C, 810 }, - { 16, 0xA0DC48C4, 0xB0DC48C4, 810 }, - { 47, 0xA0BB8FD8, 0xB0BB8FD8, 810 }, - { 1, 0xA0A7C65C, 0xB0A7C65C, 810 }, - { 22, 0xA0160140, 0xB0160140, 810 }, - { 4, 0xA04C2658, 0xB04C2658, 810 }, - { 22, 0xA0D27BD0, 0xB0D27BD0, 810 }, - { 15, 0xA092DF68, 0xB092DF68, 810 }, - { 46, 0xA0FCC898, 0xB0FCC898, 810 }, - { 42, 0xA0CA6168, 0xB0CA6168, 810 }, - { 40, 0xA0FDE93C, 0xB0FDE93C, 810 }, - { 6, 0xA0B37570, 0xB0B37570, 810 }, - { 37, 0xA014F3A4, 0xB014F3A4, 810 }, - { 47, 0xA052A468, 0xB052A468, 810 }, - { 21, 0xA06C69E8, 0xB06C69E8, 810 }, - { 8, 0xA0DEF910, 0xB0DEF910, 810 }, - { 2, 0xA03530DC, 0xB03530DC, 810 }, - { 22, 0xA074F028, 0xB074F028, 810 }, - { 34, 0xA0B1DF70, 0xB0B1DF70, 810 }, - { 21, 0xA0C4CAE4, 0xB0C4CAE4, 810 }, - { 41, 0xA03149B8, 0xB03149B8, 810 }, - { 11, 0xA00BB56C, 0xB00BB56C, 810 }, - { 43, 0xA0FFC830, 0xB0FFC830, 810 }, - { 29, 0xA0F73214, 0xB0F73214, 810 }, - { 44, 0xA06126AC, 0xB06126AC, 810 }, - { 30, 0xA0404ADC, 0xB0404ADC, 810 }, - { 40, 0xA07E2808, 0xB07E2808, 810 }, - { 11, 0xA0DFA12C, 0xB0DFA12C, 810 }, - { 8, 0xA0058D00, 0xB0058D00, 810 }, - { 4, 0xA0E03640, 0xB0E03640, 810 }, - { 45, 0xA0A5A4CC, 0xB0A5A4CC, 810 }, - { 29, 0xA025D6E8, 0xB025D6E8, 810 }, - { 2, 0xA02E0DDC, 0xB02E0DDC, 810 }, - { 18, 0xA0BB56C0, 0xB0BB56C0, 810 }, - { 12, 0xA02FB08C, 0xB02FB08C, 810 }, - { 2, 0xA03E821C, 0xB03E821C, 810 }, - { 12, 0xA0CA54B8, 0xB0CA54B8, 810 }, - { 2, 0xA0767CA4, 0xB0767CA4, 810 }, - { 20, 0xA0CE97D8, 0xB0CE97D8, 810 }, - { 19, 0xA06F00D4, 0xB06F00D4, 810 }, - { 32, 0xA0A8ADE8, 0xB0A8ADE8, 810 }, - { 25, 0xA0C3E358, 0xB0C3E358, 810 }, - { 34, 0xA0BFB66C, 0xB0BFB66C, 810 }, - { 30, 0xA062F298, 0xB062F298, 810 }, - { 16, 0xA0B97174, 0xB0B97174, 810 }, - { 2, 0xA0DFCD94, 0xB0DFCD94, 810 }, - { 41, 0xA03AB784, 0xB03AB784, 810 }, - { 12, 0xA09BBB4C, 0xB09BBB4C, 810 }, - { 18, 0xA04D605C, 0xB04D605C, 810 }, - { 22, 0xA0F357A0, 0xB0F357A0, 810 }, - { 3, 0xA0CE5868, 0xB0CE5868, 810 }, - { 41, 0xA0376BCC, 0xB0376BCC, 810 }, - { 21, 0xA01C5614, 0xB01C5614, 810 }, - { 17, 0xA0A874D0, 0xB0A874D0, 810 }, - { 7, 0xA089FD2C, 0xB089FD2C, 810 }, - { 23, 0xA0CE227C, 0xB0CE227C, 810 }, - { 27, 0xA06C7698, 0xB06C7698, 810 }, - { 25, 0xA0010A70, 0xB0010A70, 810 }, - { 47, 0xA072D4F0, 0xB072D4F0, 810 }, - { 28, 0xA0793674, 0xB0793674, 810 }, - { 24, 0xA0EE4980, 0xB0EE4980, 810 }, - { 21, 0xA0EB6FF8, 0xB0EB6FF8, 810 }, - { 11, 0xA0C6C990, 0xB0C6C990, 810 }, - { 31, 0xA03C53DC, 0xB03C53DC, 810 }, - { 44, 0xA0B54AE0, 0xB0B54AE0, 810 }, - { 31, 0xA0DAA940, 0xB0DAA940, 810 }, - { 23, 0xA0C4A1A8, 0xB0C4A1A8, 810 }, - { 33, 0xA08C1EBC, 0xB08C1EBC, 810 }, - { 17, 0xA086F73C, 0xB086F73C, 810 }, - { 5, 0xA0E0135C, 0xB0E0135C, 810 }, -}; - -static const uint8_t __attribute__((section(".pdcp_src"), used)) pdcp_src_data[NUM_SRC_SLOTS][PDU_STRIDE] = { - [13] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 0x5F, 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F, 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F, 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF, 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0xDF, 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 0x5F, 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F, 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F, 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF, 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0xDF, 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 0x5F, 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F, 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F, 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF, 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0xDF, 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x00, 0x00 }, - [18] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 0x5F, 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F, 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F, 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF, 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0xDF, 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 0x5F, 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 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use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -// Author: Zexin Fu - -#ifndef PDCP_PKG_H -#define PDCP_PKG_H - -#include - -typedef struct { - int user_id; - unsigned int src_addr; - unsigned int tgt_addr; - unsigned int pkg_length; -} pdcp_pkg_t; - -#define NUM_SRC_SLOTS 20661 -#define PDU_SIZE 810 -#define PDU_STRIDE 812 -#define NUM_PKGS 300 -#define ACTIVE_USER_NUMBER 48 - -#define NUM_PRODUCER_CORES 2 -static const unsigned int producer_core_ids[NUM_PRODUCER_CORES] = {0, 1}; -#define NUM_CONSUMER_CORES 2 -static const unsigned int consumer_core_ids[NUM_CONSUMER_CORES] = {2, 3}; -#define NUM_RLC_KERNEL_CORES (NUM_PRODUCER_CORES + NUM_CONSUMER_CORES) -static const unsigned int rlc_kernel_core_ids[NUM_RLC_KERNEL_CORES] = {0, 1, 2, 3}; - -static const pdcp_pkg_t __attribute__((section(".pdcp_info"), used)) pdcp_pkgs[NUM_PKGS] = { - { 37, 0xA02D3300, 0xB02D3300, 810 }, - { 38, 0xA00A25C4, 0xB00A25C4, 810 }, - { 2, 0xA06FA8F0, 0xB06FA8F0, 810 }, - { 39, 0xA0636B20, 0xB0636B20, 810 }, - { 5, 0xA05A9F18, 0xB05A9F18, 810 }, - { 26, 0xA038A5D0, 0xB038A5D0, 810 }, - { 42, 0xA0299B28, 0xB0299B28, 810 }, - { 37, 0xA0DD6968, 0xB0DD6968, 810 }, - { 36, 0xA0234980, 0xB0234980, 810 }, - { 33, 0xA0EFBC9C, 0xB0EFBC9C, 810 }, - { 20, 0xA0AB4B2C, 0xB0AB4B2C, 810 }, - { 16, 0xA00CE5EC, 0xB00CE5EC, 810 }, - { 13, 0xA00C17C0, 0xB00C17C0, 810 }, - { 42, 0xA02609A8, 0xB02609A8, 810 }, - { 45, 0xA058C350, 0xB058C350, 810 }, - { 20, 0xA05E7334, 0xB05E7334, 810 }, - { 15, 0xA0CD2B14, 0xB0CD2B14, 810 }, - { 16, 0xA0F46868, 0xB0F46868, 810 }, - { 25, 0xA00AC45C, 0xB00AC45C, 810 }, - { 8, 0xA0E3DAC8, 0xB0E3DAC8, 810 }, - { 42, 0xA050B8C4, 0xB050B8C4, 810 }, - { 41, 0xA0DD3D00, 0xB0DD3D00, 810 }, - { 19, 0xA0AA5098, 0xB0AA5098, 810 }, - { 29, 0xA0597E74, 0xB0597E74, 810 }, - { 20, 0xA0B65ED4, 0xB0B65ED4, 810 }, - { 4, 0xA0EF3DBC, 0xB0EF3DBC, 810 }, - { 0, 0xA070EFA4, 0xB070EFA4, 810 }, - { 29, 0xA002A070, 0xB002A070, 810 }, - { 39, 0xA040D014, 0xB040D014, 810 }, - { 36, 0xA0AB9420, 0xB0AB9420, 810 }, - { 6, 0xA08A233C, 0xB08A233C, 810 }, - { 4, 0xA070CFEC, 0xB070CFEC, 810 }, - { 34, 0xA03F1D88, 0xB03F1D88, 810 }, - { 13, 0xA0576994, 0xB0576994, 810 }, - { 32, 0xA088A69C, 0xB088A69C, 810 }, - { 16, 0xA0297E9C, 0xB0297E9C, 810 }, - { 8, 0xA025A754, 0xB025A754, 810 }, - { 22, 0xA09A3EAC, 0xB09A3EAC, 810 }, - { 4, 0xA02743AC, 0xB02743AC, 810 }, - { 15, 0xA091BEC4, 0xB091BEC4, 810 }, - { 23, 0xA08BA308, 0xB08BA308, 810 }, - { 18, 0xA0F51A08, 0xB0F51A08, 810 }, - { 10, 0xA06B62A4, 0xB06B62A4, 810 }, - { 28, 0xA011A194, 0xB011A194, 810 }, - { 34, 0xA0BA8568, 0xB0BA8568, 810 }, - { 45, 0xA0D9B504, 0xB0D9B504, 810 }, - { 19, 0xA032ACF8, 0xB032ACF8, 810 }, - { 39, 0xA099ACC4, 0xB099ACC4, 810 }, - { 41, 0xA01FFDC8, 0xB01FFDC8, 810 }, - { 33, 0xA0E0200C, 0xB0E0200C, 810 }, - { 0, 0xA0770508, 0xB0770508, 810 }, - { 42, 0xA0FF3974, 0xB0FF3974, 810 }, - { 35, 0xA0FB1C64, 0xB0FB1C64, 810 }, - { 19, 0xA092D2B8, 0xB092D2B8, 810 }, - { 42, 0xA0EA6588, 0xB0EA6588, 810 }, - { 6, 0xA04E0ED0, 0xB04E0ED0, 810 }, - { 8, 0xA01C3CB4, 0xB01C3CB4, 810 }, - { 16, 0xA01298FC, 0xB01298FC, 810 }, - { 7, 0xA05C8464, 0xB05C8464, 810 }, - { 6, 0xA0757BB8, 0xB0757BB8, 810 }, - { 47, 0xA0206348, 0xB0206348, 810 }, - { 35, 0xA05E8310, 0xB05E8310, 810 }, - { 9, 0xA028FFBC, 0xB028FFBC, 810 }, - { 17, 0xA09A51B4, 0xB09A51B4, 810 }, - { 18, 0xA070D970, 0xB070D970, 810 }, - { 38, 0xA0B8148C, 0xB0B8148C, 810 }, - { 13, 0xA0941C98, 0xB0941C98, 810 }, - { 45, 0xA04206EC, 0xB04206EC, 810 }, - { 21, 0xA0964AD8, 0xB0964AD8, 810 }, - { 13, 0xA0903BCC, 0xB0903BCC, 810 }, - { 43, 0xA0550EEC, 0xB0550EEC, 810 }, - { 40, 0xA06C6390, 0xB06C6390, 810 }, - { 16, 0xA01CFB04, 0xB01CFB04, 810 }, - { 32, 0xA0F74EA0, 0xB0F74EA0, 810 }, - { 31, 0xA04578B4, 0xB04578B4, 810 }, - { 16, 0xA0D8DA28, 0xB0D8DA28, 810 }, - { 3, 0xA063619C, 0xB063619C, 810 }, - { 5, 0xA0425638, 0xB0425638, 810 }, - { 40, 0xA0BBAC64, 0xB0BBAC64, 810 }, - { 27, 0xA09A0BEC, 0xB09A0BEC, 810 }, - { 17, 0xA06D973C, 0xB06D973C, 810 }, - { 2, 0xA0E21EB8, 0xB0E21EB8, 810 }, - { 0, 0xA05928D0, 0xB05928D0, 810 }, - { 21, 0xA083A858, 0xB083A858, 810 }, - { 8, 0xA016B2E0, 0xB016B2E0, 810 }, - { 40, 0xA05CFCEC, 0xB05CFCEC, 810 }, - { 16, 0xA00D05A4, 0xB00D05A4, 810 }, - { 10, 0xA0801080, 0xB0801080, 810 }, - { 47, 0xA0A2DE4C, 0xB0A2DE4C, 810 }, - { 28, 0xA06CB2DC, 0xB06CB2DC, 810 }, - { 35, 0xA01ADCA0, 0xB01ADCA0, 810 }, - { 45, 0xA055A72C, 0xB055A72C, 810 }, - { 27, 0xA0E6454C, 0xB0E6454C, 810 }, - { 35, 0xA07FC134, 0xB07FC134, 810 }, - { 0, 0xA0565274, 0xB0565274, 810 }, - { 7, 0xA0CAAD88, 0xB0CAAD88, 810 }, - { 4, 0xA0A0A030, 0xB0A0A030, 810 }, - { 44, 0xA0BA4924, 0xB0BA4924, 810 }, - { 9, 0xA039FF8C, 0xB039FF8C, 810 }, - { 34, 0xA06B88B4, 0xB06B88B4, 810 }, - { 2, 0xA038AF54, 0xB038AF54, 810 }, - { 23, 0xA0641FEC, 0xB0641FEC, 810 }, - { 37, 0xA0E3E778, 0xB0E3E778, 810 }, - { 35, 0xA0DAD27C, 0xB0DAD27C, 810 }, - { 9, 0xA06AAAAC, 0xB06AAAAC, 810 }, - { 27, 0xA0ED5544, 0xB0ED5544, 810 }, - { 8, 0xA0ADEEC8, 0xB0ADEEC8, 810 }, - { 2, 0xA0ECE96C, 0xB0ECE96C, 810 }, - { 19, 0xA0A22654, 0xB0A22654, 810 }, - { 23, 0xA092F59C, 0xB092F59C, 810 }, - { 2, 0xA0590918, 0xB0590918, 810 }, - { 22, 0xA03826F0, 0xB03826F0, 810 }, - { 13, 0xA0CEDDA0, 0xB0CEDDA0, 810 }, - { 43, 0xA0C85C64, 0xB0C85C64, 810 }, - { 15, 0xA024E5D8, 0xB024E5D8, 810 }, - { 42, 0xA0131E34, 0xB0131E34, 810 }, - { 6, 0xA02C8160, 0xB02C8160, 810 }, - { 22, 0xA03E0CC0, 0xB03E0CC0, 810 }, - { 35, 0xA0FEBDC0, 0xB0FEBDC0, 810 }, - { 26, 0xA040F2F8, 0xB040F2F8, 810 }, - { 39, 0xA0AB648C, 0xB0AB648C, 810 }, - { 47, 0xA0F223F4, 0xB0F223F4, 810 }, - { 9, 0xA019C8AC, 0xB019C8AC, 810 }, - { 15, 0xA09C3700, 0xB09C3700, 810 }, - { 10, 0xA09AED20, 0xB09AED20, 810 }, - { 11, 0xA0F1EE08, 0xB0F1EE08, 810 }, - { 26, 0xA0BE070C, 0xB0BE070C, 810 }, - { 1, 0xA0D6D1F8, 0xB0D6D1F8, 810 }, - { 11, 0xA06611E8, 0xB06611E8, 810 }, - { 47, 0xA0E09BC0, 0xB0E09BC0, 810 }, - { 21, 0xA004A8A0, 0xB004A8A0, 810 }, - { 26, 0xA02E800C, 0xB02E800C, 810 }, - { 42, 0xA0DA0124, 0xB0DA0124, 810 }, - { 47, 0xA06C53B4, 0xB06C53B4, 810 }, - { 15, 0xA08A19B8, 0xB08A19B8, 810 }, - { 17, 0xA02D4934, 0xB02D4934, 810 }, - { 10, 0xA07727EC, 0xB07727EC, 810 }, - { 44, 0xA0B08288, 0xB0B08288, 810 }, - { 6, 0xA04034A8, 0xB04034A8, 810 }, - { 24, 0xA0B83444, 0xB0B83444, 810 }, - { 2, 0xA0015038, 0xB0015038, 810 }, - { 30, 0xA06AED48, 0xB06AED48, 810 }, - { 14, 0xA0CB3C44, 0xB0CB3C44, 810 }, - { 12, 0xA0488828, 0xB0488828, 810 }, - { 29, 0xA0CE1C24, 0xB0CE1C24, 810 }, - { 22, 0xA02B3128, 0xB02B3128, 810 }, - { 19, 0xA0FDDC8C, 0xB0FDDC8C, 810 }, - { 14, 0xA07929C4, 0xB07929C4, 810 }, - { 14, 0xA0F73B98, 0xB0F73B98, 810 }, - { 1, 0xA050BF1C, 0xB050BF1C, 810 }, - { 42, 0xA097CDD0, 0xB097CDD0, 810 }, - { 12, 0xA04194BC, 0xB04194BC, 810 }, - { 25, 0xA0DAFBB8, 0xB0DAFBB8, 810 }, - { 21, 0xA0D750D8, 0xB0D750D8, 810 }, - { 17, 0xA0003918, 0xB0003918, 810 }, - { 4, 0xA0F32B38, 0xB0F32B38, 810 }, - { 17, 0xA083987C, 0xB083987C, 810 }, - { 22, 0xA0C65DB8, 0xB0C65DB8, 810 }, - { 41, 0xA007E7A8, 0xB007E7A8, 810 }, - { 32, 0xA02D68EC, 0xB02D68EC, 810 }, - { 25, 0xA0935E48, 0xB0935E48, 810 }, - { 43, 0xA07CD7D0, 0xB07CD7D0, 810 }, - { 34, 0xA0613688, 0xB0613688, 810 }, - { 21, 0xA0178438, 0xB0178438, 810 }, - { 1, 0xA061C870, 0xB061C870, 810 }, - { 7, 0xA0E65854, 0xB0E65854, 810 }, - { 16, 0xA01FF770, 0xB01FF770, 810 }, - { 11, 0xA022C448, 0xB022C448, 810 }, - { 37, 0xA0C54CF0, 0xB0C54CF0, 810 }, - { 16, 0xA01C16A4, 0xB01C16A4, 810 }, - { 2, 0xA0D84514, 0xB0D84514, 810 }, - { 6, 0xA0330C20, 0xB0330C20, 810 }, - { 38, 0xA0342014, 0xB0342014, 810 }, - { 27, 0xA0C0F6C8, 0xB0C0F6C8, 810 }, - { 22, 0xA0DF3554, 0xB0DF3554, 810 }, - { 46, 0xA04307D8, 0xB04307D8, 810 }, - { 20, 0xA06B9BBC, 0xB06B9BBC, 810 }, - { 27, 0xA0D639B8, 0xB0D639B8, 810 }, - { 38, 0xA0F64430, 0xB0F64430, 810 }, - { 32, 0xA0ABCA0C, 0xB0ABCA0C, 810 }, - { 7, 0xA055FCD0, 0xB055FCD0, 810 }, - { 24, 0xA0DAF234, 0xB0DAF234, 810 }, - { 36, 0xA051A9D4, 0xB051A9D4, 810 }, - { 12, 0xA07E8D88, 0xB07E8D88, 810 }, - { 16, 0xA0A1FD18, 0xB0A1FD18, 810 }, - { 2, 0xA0979B10, 0xB0979B10, 810 }, - { 45, 0xA0B1DC44, 0xB0B1DC44, 810 }, - { 27, 0xA0D21FD4, 0xB0D21FD4, 810 }, - { 0, 0xA0B74CB8, 0xB0B74CB8, 810 }, - { 33, 0xA031207C, 0xB031207C, 810 }, - { 34, 0xA064A524, 0xB064A524, 810 }, - { 43, 0xA05B3758, 0xB05B3758, 810 }, - { 46, 0xA019FE98, 0xB019FE98, 810 }, - { 47, 0xA0894208, 0xB0894208, 810 }, - { 47, 0xA008896C, 0xB008896C, 810 }, - { 42, 0xA0EED83C, 0xB0EED83C, 810 }, - { 12, 0xA0E0E188, 0xB0E0E188, 810 }, - { 23, 0xA05D6BF0, 0xB05D6BF0, 810 }, - { 27, 0xA0EEE818, 0xB0EEE818, 810 }, - { 4, 0xA0596840, 0xB0596840, 810 }, - { 42, 0xA002E964, 0xB002E964, 810 }, - { 21, 0xA01CD1C8, 0xB01CD1C8, 810 }, - { 39, 0xA017E68C, 0xB017E68C, 810 }, - { 20, 0xA05CF03C, 0xB05CF03C, 810 }, - { 42, 0xA01B5B80, 0xB01B5B80, 810 }, - { 7, 0xA00CBFDC, 0xB00CBFDC, 810 }, - { 46, 0xA08625E4, 0xB08625E4, 810 }, - { 19, 0xA01CC1EC, 0xB01CC1EC, 810 }, - { 32, 0xA0D0BC94, 0xB0D0BC94, 810 }, - { 19, 0xA0609E48, 0xB0609E48, 810 }, - { 42, 0xA0710F5C, 0xB0710F5C, 810 }, - { 26, 0xA0C513D8, 0xB0C513D8, 810 }, - { 20, 0xA056FA90, 0xB056FA90, 810 }, - { 25, 0xA0DAEBDC, 0xB0DAEBDC, 810 }, - { 44, 0xA035B614, 0xB035B614, 810 }, - { 18, 0xA0E7D4F4, 0xB0E7D4F4, 810 }, - { 35, 0xA0E9F02C, 0xB0E9F02C, 810 }, - { 8, 0xA0BFE600, 0xB0BFE600, 810 }, - { 12, 0xA062A678, 0xB062A678, 810 }, - { 26, 0xA0C005B8, 0xB0C005B8, 810 }, - { 42, 0xA0A54278, 0xB0A54278, 810 }, - { 24, 0xA04D4D54, 0xB04D4D54, 810 }, - { 43, 0xA0264918, 0xB0264918, 810 }, - { 47, 0xA02759E0, 0xB02759E0, 810 }, - { 11, 0xA0AEFF90, 0xB0AEFF90, 810 }, - { 39, 0xA08FD64C, 0xB08FD64C, 810 }, - { 36, 0xA0ABF674, 0xB0ABF674, 810 }, - { 19, 0xA0A6E528, 0xB0A6E528, 810 }, - { 25, 0xA0BD9B34, 0xB0BD9B34, 810 }, - { 35, 0xA015FE14, 0xB015FE14, 810 }, - { 0, 0xA027F220, 0xB027F220, 810 }, - { 19, 0xA0189B58, 0xB0189B58, 810 }, - { 18, 0xA0A3768C, 0xB0A3768C, 810 }, - { 13, 0xA089C0E8, 0xB089C0E8, 810 }, - { 27, 0xA02C5B50, 0xB02C5B50, 810 }, - { 37, 0xA064F144, 0xB064F144, 810 }, - { 38, 0xA04DC908, 0xB04DC908, 810 }, - { 41, 0xA04D3720, 0xB04D3720, 810 }, - { 20, 0xA0D9BB5C, 0xB0D9BB5C, 810 }, - { 29, 0xA0B62290, 0xB0B62290, 810 }, - { 28, 0xA038E86C, 0xB038E86C, 810 }, - { 28, 0xA0AB4800, 0xB0AB4800, 810 }, - { 43, 0xA04A7D50, 0xB04A7D50, 810 }, - { 13, 0xA07115B4, 0xB07115B4, 810 }, - { 32, 0xA0BBD274, 0xB0BBD274, 810 }, - { 30, 0xA06569CC, 0xB06569CC, 810 }, - { 47, 0xA01E9A88, 0xB01E9A88, 810 }, - { 10, 0xA0B3E7A0, 0xB0B3E7A0, 810 }, - { 42, 0xA0DF6E6C, 0xB0DF6E6C, 810 }, - { 5, 0xA027BF60, 0xB027BF60, 810 }, - { 18, 0xA01487CC, 0xB01487CC, 810 }, - { 32, 0xA0DB776C, 0xB0DB776C, 810 }, - { 42, 0xA005FC04, 0xB005FC04, 810 }, - { 40, 0xA025DD40, 0xB025DD40, 810 }, - { 39, 0xA05FF62C, 0xB05FF62C, 810 }, - { 21, 0xA043838C, 0xB043838C, 810 }, - { 5, 0xA0A4FFDC, 0xB0A4FFDC, 810 }, - { 15, 0xA0C52A0C, 0xB0C52A0C, 810 }, - { 43, 0xA0C36DFC, 0xB0C36DFC, 810 }, - { 19, 0xA056C7D0, 0xB056C7D0, 810 }, - { 14, 0xA0A2D19C, 0xB0A2D19C, 810 }, - { 12, 0xA017CD2C, 0xB017CD2C, 810 }, - { 9, 0xA042D518, 0xB042D518, 810 }, - { 1, 0xA099DC58, 0xB099DC58, 810 }, - { 2, 0xA000DE08, 0xB000DE08, 810 }, - { 15, 0xA09E81CC, 0xB09E81CC, 810 }, - { 30, 0xA06BAB98, 0xB06BAB98, 810 }, - { 39, 0xA0B8B97C, 0xB0B8B97C, 810 }, - { 4, 0xA073CF84, 0xB073CF84, 810 }, - { 29, 0xA0ABBD5C, 0xB0ABBD5C, 810 }, - { 26, 0xA0E1A304, 0xB0E1A304, 810 }, - { 40, 0xA0C595E4, 0xB0C595E4, 810 }, - { 36, 0xA03ED7C0, 0xB03ED7C0, 810 }, - { 12, 0xA04D1768, 0xB04D1768, 810 }, - { 45, 0xA07874F8, 0xB07874F8, 810 }, - { 44, 0xA05860FC, 0xB05860FC, 810 }, - { 24, 0xA017BD50, 0xB017BD50, 810 }, - { 31, 0xA0EB23D8, 0xB0EB23D8, 810 }, - { 25, 0xA0DC1F88, 0xB0DC1F88, 810 }, - { 15, 0xA018BE3C, 0xB018BE3C, 810 }, - { 9, 0xA07F5230, 0xB07F5230, 810 }, - { 41, 0xA01734EC, 0xB01734EC, 810 }, - { 44, 0xA0145B64, 0xB0145B64, 810 }, - { 0, 0xA0ED2C08, 0xB0ED2C08, 810 }, - { 6, 0xA0C19234, 0xB0C19234, 810 }, - { 27, 0xA0CC26FC, 0xB0CC26FC, 810 }, - { 14, 0xA0D7A024, 0xB0D7A024, 810 }, - { 11, 0xA03FE888, 0xB03FE888, 810 }, - { 44, 0xA0171534, 0xB0171534, 810 }, - { 33, 0xA0CE2C00, 0xB0CE2C00, 810 }, - { 29, 0xA020862C, 0xB020862C, 810 }, - { 3, 0xA04B718C, 0xB04B718C, 810 }, - { 35, 0xA01BD0DC, 0xB01BD0DC, 810 }, - { 15, 0xA0F19538, 0xB0F19538, 810 }, - { 7, 0xA01B9498, 0xB01B9498, 810 }, - { 29, 0xA05F7DA4, 0xB05F7DA4, 810 }, - { 8, 0xA0A3EBE8, 0xB0A3EBE8, 810 }, - { 29, 0xA030AB20, 0xB030AB20, 810 }, - { 42, 0xA0E74964, 0xB0E74964, 810 }, - { 33, 0xA063F384, 0xB063F384, 810 }, -}; - -static const uint8_t __attribute__((section(".pdcp_src"), used)) pdcp_src_data[NUM_SRC_SLOTS][PDU_STRIDE] = { - [18] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 0x5F, 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F, 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F, 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF, 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0xDF, 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, 0x40, 0x41, 0x42, 0x43, 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IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -// Author: Zexin Fu - -#ifndef PDCP_PKG_H -#define PDCP_PKG_H - -#include - -typedef struct { - int user_id; - unsigned int src_addr; - unsigned int tgt_addr; - unsigned int pkg_length; -} pdcp_pkg_t; - -#define NUM_SRC_SLOTS 12336 -#define PDU_SIZE 1360 -#define PDU_STRIDE 1360 -#define NUM_PKGS 24 -#define ACTIVE_USER_NUMBER 8 - -#define NUM_PRODUCER_CORES 2 -static const unsigned int producer_core_ids[NUM_PRODUCER_CORES] = {0, 1}; -#define NUM_CONSUMER_CORES 2 -static const unsigned int consumer_core_ids[NUM_CONSUMER_CORES] = {2, 3}; -#define NUM_RLC_KERNEL_CORES (NUM_PRODUCER_CORES + NUM_CONSUMER_CORES) -static const unsigned int rlc_kernel_core_ids[NUM_RLC_KERNEL_CORES] = {0, 1, 2, 3}; - -static const pdcp_pkg_t __attribute__((section(".pdcp_info"), used)) pdcp_pkgs[NUM_PKGS] = { - { 3, 0xA0D965C0, 0xB0D965C0, 1360 }, - { 6, 0xA025DA00, 0xB025DA00, 1360 }, - { 3, 0xA0087CD0, 0xB0087CD0, 1360 }, - { 7, 0xA0FC1D90, 0xB0FC1D90, 1360 }, - { 4, 0xA05D8220, 0xB05D8220, 1360 }, - { 0, 0xA05341C0, 0xB05341C0, 1360 }, - { 2, 0xA04BE3D0, 0xB04BE3D0, 1360 }, - { 6, 0xA02F7060, 0xB02F7060, 1360 }, - { 5, 0xA0FA64A0, 0xB0FA64A0, 1360 }, - { 4, 0xA022D7B0, 0xB022D7B0, 1360 }, - { 2, 0xA0E613B0, 0xB0E613B0, 1360 }, - { 3, 0xA0FBD330, 0xB0FBD330, 1360 }, - { 5, 0xA0B96B30, 0xB0B96B30, 1360 }, - { 1, 0xA01D8D00, 0xB01D8D00, 1360 }, - { 1, 0xA0C8C120, 0xB0C8C120, 1360 }, - { 6, 0xA08F7000, 0xB08F7000, 1360 }, - { 1, 0xA00ACA80, 0xB00ACA80, 1360 }, - { 5, 0xA00A2080, 0xB00A2080, 1360 }, - { 5, 0xA01FDAB0, 0xB01FDAB0, 1360 }, - { 4, 0xA04A5560, 0xB04A5560, 1360 }, - { 0, 0xA04F15F0, 0xB04F15F0, 1360 }, - { 7, 0xA0ABCE30, 0xB0ABCE30, 1360 }, - { 1, 0xA0CCAD30, 0xB0CCAD30, 1360 }, - { 6, 0xA00901A0, 0xB00901A0, 1360 }, -}; - -static const uint8_t __attribute__((section(".pdcp_src"), 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a/software/rlc/multi_producer_single_consumer_double_linked_list/data/data_8_1350_8.h b/software/rlc/multi_producer_single_consumer_double_linked_list/data/data_8_1350_8.h deleted file mode 100644 index 0783b6d..0000000 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/data/data_8_1350_8.h +++ /dev/null @@ -1,67 +0,0 @@ - -// Copyright 2025 ETH Zurich and University of Bologna. -// -// SPDX-License-Identifier: Apache-2.0 -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -// Author: Zexin Fu - -#ifndef PDCP_PKG_H -#define PDCP_PKG_H - -#include - -typedef struct { - int user_id; - unsigned int src_addr; - unsigned int tgt_addr; - unsigned int pkg_length; -} pdcp_pkg_t; - -#define NUM_SRC_SLOTS 12336 -#define PDU_SIZE 1360 -#define PDU_STRIDE 1360 -#define NUM_PKGS 8 -#define ACTIVE_USER_NUMBER 8 - -#define NUM_PRODUCER_CORES 2 -static const unsigned int producer_core_ids[NUM_PRODUCER_CORES] = {0, 1}; -#define NUM_CONSUMER_CORES 2 -static const unsigned int consumer_core_ids[NUM_CONSUMER_CORES] = {2, 3}; -#define NUM_RLC_KERNEL_CORES (NUM_PRODUCER_CORES + NUM_CONSUMER_CORES) -static const unsigned int rlc_kernel_core_ids[NUM_RLC_KERNEL_CORES] = {0, 1, 2, 3}; - -static const pdcp_pkg_t __attribute__((section(".pdcp_info"), used)) pdcp_pkgs[NUM_PKGS] = { - { 1, 0xA0D965C0, 0xB0D965C0, 1360 }, - { 1, 0xA025DA00, 0xB025DA00, 1360 }, - { 6, 0xA0087CD0, 0xB0087CD0, 1360 }, - { 0, 0xA0FC1D90, 0xB0FC1D90, 1360 }, - { 0, 0xA05D8220, 0xB05D8220, 1360 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a/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_12_1350_24.json b/software/rlc/multi_producer_single_consumer_double_linked_list/script/data_12_1350_24.json similarity index 100% rename from software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_12_1350_24.json rename to software/rlc/multi_producer_single_consumer_double_linked_list/script/data_12_1350_24.json diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_16_1350_24.json b/software/rlc/multi_producer_single_consumer_double_linked_list/script/data_16_1350_24.json similarity index 100% rename from software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_16_1350_24.json rename to software/rlc/multi_producer_single_consumer_double_linked_list/script/data_16_1350_24.json diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/script/data_1_1350_10.json b/software/rlc/multi_producer_single_consumer_double_linked_list/script/data_1_1350_10.json new file mode 100644 index 0000000..d527a8e --- /dev/null +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/script/data_1_1350_10.json @@ -0,0 +1,32 @@ +// Copyright 2025 ETH Zurich and University of Bologna. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// Author: Zexin Fu +{ + "active_user_number": 1, + "pkg_length": 1350, + "pdcp_header_length": 10, + "src_addr": "0xA0000000", + "src_length": 16777216, // 16777216 bytes = 16 MiB + "tgt_addr": "0xB0000000", + "tgt_length": 16777216, // 16777216 bytes = 16 MiB + "total_pkg_number": 10, + // Cores that limit which cluster cores actually run the RLC kernel. + // Any core id not listed here stays idle and only touches the + // matching partial-barrier checkpoints (see snrt_cluster_partial_barrier). + "producer_cores": [0, 1], + "consumer_cores": [2, 3] +} diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/script/data_1_1350_100.json b/software/rlc/multi_producer_single_consumer_double_linked_list/script/data_1_1350_100.json new file mode 100644 index 0000000..2c13e82 --- /dev/null +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/script/data_1_1350_100.json @@ -0,0 +1,32 @@ +// Copyright 2025 ETH Zurich and University of Bologna. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// Author: Zexin Fu +{ + "active_user_number": 1, + "pkg_length": 1350, + "pdcp_header_length": 10, + "src_addr": "0xA0000000", + "src_length": 16777216, // 16777216 bytes = 16 MiB + "tgt_addr": "0xB0000000", + "tgt_length": 16777216, // 16777216 bytes = 16 MiB + "total_pkg_number": 100, + // Cores that limit which cluster cores actually run the RLC kernel. + // Any core id not listed here stays idle and only touches the + // matching partial-barrier checkpoints (see snrt_cluster_partial_barrier). + "producer_cores": [0, 1], + "consumer_cores": [2, 3] +} diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_1_1350_100_p1c1.json b/software/rlc/multi_producer_single_consumer_double_linked_list/script/data_1_1350_100_p1c1.json similarity index 100% rename from software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_1_1350_100_p1c1.json rename to software/rlc/multi_producer_single_consumer_double_linked_list/script/data_1_1350_100_p1c1.json diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/script/data_1_1350_100_p1c3.json b/software/rlc/multi_producer_single_consumer_double_linked_list/script/data_1_1350_100_p1c3.json new file mode 100644 index 0000000..3cf6881 --- /dev/null +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/script/data_1_1350_100_p1c3.json @@ -0,0 +1,32 @@ +// Copyright 2025 ETH Zurich and University of Bologna. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// Author: Zexin Fu +{ + "active_user_number": 1, + "pkg_length": 1350, + "pdcp_header_length": 10, + "src_addr": "0xA0000000", + "src_length": 16777216, // 16777216 bytes = 16 MiB + "tgt_addr": "0xB0000000", + "tgt_length": 16777216, // 16777216 bytes = 16 MiB + "total_pkg_number": 100, + // Cores that limit which cluster cores actually run the RLC kernel. + // Any core id not listed here stays idle and only touches the + // matching partial-barrier checkpoints (see snrt_cluster_partial_barrier). + "producer_cores": [0], + "consumer_cores": [1, 2, 3] +} diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_1_1350_1157_p64_c192.json b/software/rlc/multi_producer_single_consumer_double_linked_list/script/data_1_1350_1157_p64_c192.json similarity index 100% rename from software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_1_1350_1157_p64_c192.json rename to software/rlc/multi_producer_single_consumer_double_linked_list/script/data_1_1350_1157_p64_c192.json diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg.json b/software/rlc/multi_producer_single_consumer_double_linked_list/script/data_1_1350_300.json similarity index 77% rename from software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg.json rename to software/rlc/multi_producer_single_consumer_double_linked_list/script/data_1_1350_300.json index 96ac65d..b1ea66c 100644 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg.json +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/script/data_1_1350_300.json @@ -30,14 +30,3 @@ "producer_cores": [0, 1], "consumer_cores": [2, 3] } - -// { -// "active_user_number": 1, -// "pkg_length": 2044, -// "pdcp_header_length": 4, -// "src_addr": "0xA0000000", -// "src_length": 268435456, // 268435456 bytes = 256 MiB -// "tgt_addr": "0xB0000000", -// "tgt_length": 268435456, // 268435456 bytes = 256 MiB -// "total_pkg_number": 100 // max 198400 packages = 268435456 bytes / (1350 + 3) bytes per package -// } diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_1_1350_4.json b/software/rlc/multi_producer_single_consumer_double_linked_list/script/data_1_1350_4.json similarity index 100% rename from software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_1_1350_4.json rename to software/rlc/multi_producer_single_consumer_double_linked_list/script/data_1_1350_4.json diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_1_1350_9256_p16_c48.json b/software/rlc/multi_producer_single_consumer_double_linked_list/script/data_1_1350_9256_p16_c48.json similarity index 100% rename from software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_1_1350_9256_p16_c48.json rename to software/rlc/multi_producer_single_consumer_double_linked_list/script/data_1_1350_9256_p16_c48.json diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_1_1350_9256_p16_c48_l64.json b/software/rlc/multi_producer_single_consumer_double_linked_list/script/data_1_1350_9256_p16_c48_l64.json similarity index 100% rename from software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_1_1350_9256_p16_c48_l64.json rename to software/rlc/multi_producer_single_consumer_double_linked_list/script/data_1_1350_9256_p16_c48_l64.json diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_1_1350_9256_p2_c2.json b/software/rlc/multi_producer_single_consumer_double_linked_list/script/data_1_1350_9256_p2_c2.json similarity index 100% rename from software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_1_1350_9256_p2_c2.json rename to software/rlc/multi_producer_single_consumer_double_linked_list/script/data_1_1350_9256_p2_c2.json diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_1_1350_9256_p64_c192.json b/software/rlc/multi_producer_single_consumer_double_linked_list/script/data_1_1350_9256_p64_c192.json similarity index 100% rename from software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_1_1350_9256_p64_c192.json rename to software/rlc/multi_producer_single_consumer_double_linked_list/script/data_1_1350_9256_p64_c192.json diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_1_1350_9256_p64_c192_l64.json b/software/rlc/multi_producer_single_consumer_double_linked_list/script/data_1_1350_9256_p64_c192_l64.json similarity index 100% rename from software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_1_1350_9256_p64_c192_l64.json rename to software/rlc/multi_producer_single_consumer_double_linked_list/script/data_1_1350_9256_p64_c192_l64.json diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_24_1350_24.json b/software/rlc/multi_producer_single_consumer_double_linked_list/script/data_24_1350_24.json similarity index 100% rename from software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_24_1350_24.json rename to software/rlc/multi_producer_single_consumer_double_linked_list/script/data_24_1350_24.json diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/script/data_256_800_300.json b/software/rlc/multi_producer_single_consumer_double_linked_list/script/data_256_800_300.json new file mode 100644 index 0000000..0b6899f --- /dev/null +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/script/data_256_800_300.json @@ -0,0 +1,12 @@ +{ + "active_user_number": 256, + "pkg_length": 800, + "pdcp_header_length": 10, + "src_addr": "0xA0000000", + "src_length": 16777216, + "tgt_addr": "0xB0000000", + "tgt_length": 16777216, + "total_pkg_number": 300, + "producer_cores": [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127], + "consumer_cores": [128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212, 213, 214, 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228, 229, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, 241, 242, 243, 244, 245, 246, 247, 248, 249, 250, 251, 252, 253, 254, 255] +} diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_32_1350_24.json b/software/rlc/multi_producer_single_consumer_double_linked_list/script/data_32_1350_24.json similarity index 100% rename from software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_32_1350_24.json rename to software/rlc/multi_producer_single_consumer_double_linked_list/script/data_32_1350_24.json diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_4800_800_15704_p16_c48.json b/software/rlc/multi_producer_single_consumer_double_linked_list/script/data_4800_800_15704_p16_c48.json similarity index 100% rename from software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_4800_800_15704_p16_c48.json rename to software/rlc/multi_producer_single_consumer_double_linked_list/script/data_4800_800_15704_p16_c48.json diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_4800_800_15704_p2_c2.json b/software/rlc/multi_producer_single_consumer_double_linked_list/script/data_4800_800_15704_p2_c2.json similarity index 100% rename from software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_4800_800_15704_p2_c2.json rename to software/rlc/multi_producer_single_consumer_double_linked_list/script/data_4800_800_15704_p2_c2.json diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_4800_800_15704_p48_c144_l64.json b/software/rlc/multi_producer_single_consumer_double_linked_list/script/data_4800_800_15704_p48_c144_l64.json similarity index 100% rename from software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_4800_800_15704_p48_c144_l64.json rename to software/rlc/multi_producer_single_consumer_double_linked_list/script/data_4800_800_15704_p48_c144_l64.json diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_4800_800_15704_p64_c192.json b/software/rlc/multi_producer_single_consumer_double_linked_list/script/data_4800_800_15704_p64_c192.json similarity index 100% rename from software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_4800_800_15704_p64_c192.json rename to software/rlc/multi_producer_single_consumer_double_linked_list/script/data_4800_800_15704_p64_c192.json diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_4800_800_15704_p64_c192_l64.json b/software/rlc/multi_producer_single_consumer_double_linked_list/script/data_4800_800_15704_p64_c192_l64.json similarity index 100% rename from software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_4800_800_15704_p64_c192_l64.json rename to software/rlc/multi_producer_single_consumer_double_linked_list/script/data_4800_800_15704_p64_c192_l64.json diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_4800_800_1963_p64_c192.json b/software/rlc/multi_producer_single_consumer_double_linked_list/script/data_4800_800_1963_p64_c192.json similarity index 100% rename from software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_4800_800_1963_p64_c192.json rename to software/rlc/multi_producer_single_consumer_double_linked_list/script/data_4800_800_1963_p64_c192.json diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_48_1350_24.json b/software/rlc/multi_producer_single_consumer_double_linked_list/script/data_48_1350_24.json similarity index 100% rename from software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_48_1350_24.json rename to software/rlc/multi_producer_single_consumer_double_linked_list/script/data_48_1350_24.json diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_48_1350_8.json b/software/rlc/multi_producer_single_consumer_double_linked_list/script/data_48_1350_8.json similarity index 100% rename from software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_48_1350_8.json rename to software/rlc/multi_producer_single_consumer_double_linked_list/script/data_48_1350_8.json diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_48_800_1000.json b/software/rlc/multi_producer_single_consumer_double_linked_list/script/data_48_800_1000.json similarity index 100% rename from software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_48_800_1000.json rename to software/rlc/multi_producer_single_consumer_double_linked_list/script/data_48_800_1000.json diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_48_800_19528_p16_c48.json b/software/rlc/multi_producer_single_consumer_double_linked_list/script/data_48_800_19528_p16_c48.json similarity index 100% rename from software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_48_800_19528_p16_c48.json rename to software/rlc/multi_producer_single_consumer_double_linked_list/script/data_48_800_19528_p16_c48.json diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_48_800_19528_p2_c2.json b/software/rlc/multi_producer_single_consumer_double_linked_list/script/data_48_800_19528_p2_c2.json similarity index 100% rename from software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_48_800_19528_p2_c2.json rename to software/rlc/multi_producer_single_consumer_double_linked_list/script/data_48_800_19528_p2_c2.json diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_48_800_19528_p48_c144_l64.json b/software/rlc/multi_producer_single_consumer_double_linked_list/script/data_48_800_19528_p48_c144_l64.json similarity index 100% rename from software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_48_800_19528_p48_c144_l64.json rename to software/rlc/multi_producer_single_consumer_double_linked_list/script/data_48_800_19528_p48_c144_l64.json diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_48_800_19528_p64_c192.json b/software/rlc/multi_producer_single_consumer_double_linked_list/script/data_48_800_19528_p64_c192.json similarity index 100% rename from software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_48_800_19528_p64_c192.json rename to software/rlc/multi_producer_single_consumer_double_linked_list/script/data_48_800_19528_p64_c192.json diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_48_800_300.json b/software/rlc/multi_producer_single_consumer_double_linked_list/script/data_48_800_300.json similarity index 100% rename from software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_48_800_300.json rename to software/rlc/multi_producer_single_consumer_double_linked_list/script/data_48_800_300.json diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_48_800_4882_p64_c192.json b/software/rlc/multi_producer_single_consumer_double_linked_list/script/data_48_800_4882_p64_c192.json similarity index 100% rename from software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_48_800_4882_p64_c192.json rename to software/rlc/multi_producer_single_consumer_double_linked_list/script/data_48_800_4882_p64_c192.json diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_8_1350_24.json b/software/rlc/multi_producer_single_consumer_double_linked_list/script/data_8_1350_24.json similarity index 100% rename from software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_8_1350_24.json rename to software/rlc/multi_producer_single_consumer_double_linked_list/script/data_8_1350_24.json diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_8_1350_8.json b/software/rlc/multi_producer_single_consumer_double_linked_list/script/data_8_1350_8.json similarity index 100% rename from software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_8_1350_8.json rename to software/rlc/multi_producer_single_consumer_double_linked_list/script/data_8_1350_8.json diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/script/generate_pdcp_pkg.py b/software/rlc/multi_producer_single_consumer_double_linked_list/script/gen_data.py similarity index 95% rename from software/rlc/multi_producer_single_consumer_double_linked_list/script/generate_pdcp_pkg.py rename to software/rlc/multi_producer_single_consumer_double_linked_list/script/gen_data.py index 61093ec..8a00a72 100755 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/script/generate_pdcp_pkg.py +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/script/gen_data.py @@ -19,9 +19,9 @@ # Author: Zexin Fu """ -generate_pdcp_pkg_header.py +gen_data.py -Reads a JSON config (default: pdcp_pkg.json), strips C-style comments, and emits a C header defining: +Reads a JSON config (script/data_.json), strips C-style comments, and emits a C header defining: - `pdcp_pkg_t pdcp_pkgs[]` in the .dram section - A 2D array `pdcp_src_data[NUM_SRC_SLOTS][PDU_SIZE]` in its own .pdcp_src section (so its [0] element begins at src_addr) @@ -75,10 +75,10 @@ def parse_args(): parser = argparse.ArgumentParser( description='Generate a PDCP-package header from JSON config') - parser.add_argument('config', nargs='?', default='pdcp_pkg.json', - help='JSON config file (default: pdcp_pkg.json)') + parser.add_argument('-c', '--cfg', required=True, + help='JSON config file, script/data_.json') parser.add_argument('-o', '--output', - help='Output header file (default: ../data/data___.h)') + help='Output header file (default: ../data/data_.h)') parser.add_argument('-f', '--fill-zero', help='Fill unused slots with zeroes (default: False)', action='store_true', default=False) parser.add_argument('--seed', type=int, default=42, @@ -96,7 +96,7 @@ def main(): args = parse_args() # Load config try: - cfg = load_config(args.config) + cfg = load_config(args.cfg) except Exception as e: print(f"Error loading config: {e}", file=sys.stderr) sys.exit(1) @@ -138,7 +138,7 @@ def main(): else: data_dir = os.path.abspath(os.path.join(os.path.dirname(__file__), '..', 'data')) os.makedirs(data_dir, exist_ok=True) - filename = f"data_{active_users}_{pkg_len}_{num_pkgs}.h" + filename = os.path.splitext(os.path.basename(args.cfg))[0] + '.h' out_path = os.path.join(data_dir, filename) payload = bool(cfg.get('payload', True)) diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_256_800_300.json b/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_256_800_300.json deleted file mode 100644 index 59366fa..0000000 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/script/pdcp_pkg_256_800_300.json +++ /dev/null @@ -1,10 +0,0 @@ -{ - "active_user_number": 256, - "pkg_length": 800, - "pdcp_header_length": 10, - "src_addr": "0xA0000000", - "src_length": 16777216, - "tgt_addr": "0xB0000000", - "tgt_length": 16777216, - "total_pkg_number": 300 -} From af33f847547d710dc59b0911fd846c02fca7ed6e Mon Sep 17 00:00:00 2001 From: Zexin Fu Date: Fri, 16 Oct 2026 11:01:33 +0200 Subject: [PATCH 46/48] bump spatz dep (VLSU partial-port fix) --- Bender.lock | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Bender.lock b/Bender.lock index 30a569c..6147730 100644 --- a/Bender.lock +++ b/Bender.lock @@ -150,7 +150,7 @@ packages: dependencies: - tech_cells_generic spatz: - revision: f4741b0a5bcc49103bd8a3db8d51fdf76d240df7 + revision: 6acbd2e0cb9131f870209d03ffb85c46fbd2ea9c version: null source: Git: https://github.com/pulp-platform/spatz.git From cd844acc5b921f2d48e3ab1298203d645b73f9a4 Mon Sep 17 00:00:00 2001 From: Zexin Fu Date: Fri, 16 Oct 2026 21:08:56 +0200 Subject: [PATCH 47/48] rlc: return check failures as the exit code and add AM/UL tests to CI --- .gitlab-ci.yml | 2 ++ software/rlc/CMakeLists.txt | 8 ++++++++ .../kernel/rlc.c | 14 ++++++++++++-- .../kernel/rlc.h | 3 ++- .../kernel/rlc_am.c | 6 +++++- .../kernel/rlc_am.h | 5 +++-- .../kernel/rlc_ul_drv.c | 13 ++++++++----- .../main.c | 4 ++-- 8 files changed, 42 insertions(+), 13 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index a91a5e8..0c7e5d9 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -170,6 +170,8 @@ test: - fft-32b_M1024_N16 - byte-enable - multi_producer_single_consumer_double_linked_list_M1_N1350_K10 + - multi_producer_single_consumer_double_linked_list_M1_N1350_K4_P2_C2_am_G1024_tbchk + - multi_producer_single_consumer_double_linked_list_P1_C3_ul_ci script: # The vsim script writes a .rtlbinary marker here; monitor logs need the # core/noc/others subfolders. Build artifacts exclude sim/bin/logs/, so diff --git a/software/rlc/CMakeLists.txt b/software/rlc/CMakeLists.txt index cff7567..c273337 100644 --- a/software/rlc/CMakeLists.txt +++ b/software/rlc/CMakeLists.txt @@ -526,6 +526,14 @@ add_rlc_ul(multi_producer_single_consumer_double_linked_list multi_producer_single_consumer_double_linked_list/main.c "data/data_1_1350_100_p1c3.h" 1 3 0 1 2048 tc1_smallblk) +# CI regression size: tc1_smallblk cut to 256 SDUs (~20 blocks, still segmenting at every block +# boundary), so the uplink path and its end-of-run check run in a few minutes on RTL. +add_rlc_ul(multi_producer_single_consumer_double_linked_list + multi_producer_single_consumer_double_linked_list/main.c + "data/data_1_1350_100_p1c3.h" 1 3 0 1 2048 ci) +target_compile_definitions(test-${SNITCH_TEST_PREFIX}multi_producer_single_consumer_double_linked_list_P1_C3_ul_ci PUBLIC + RLC_UL_SDUS=256) + # Same cases with the bitmap work queue (RLC_AM_WORKQ=1), so the scan-free path # can be diffed against the plain one rather than replacing it. add_spatz_test_rlc_am_wq(multi_producer_single_consumer_double_linked_list multi_producer_single_consumer_double_linked_list/main.c 1 1350 100 2 4 8192 1) diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.c b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.c index b31c665..43767ac 100644 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.c +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.c @@ -1194,6 +1194,10 @@ static void pkt_production_and_recycle(const unsigned int core_id) } } +/* Non-zero once a compiled-in result check failed; written and read by core 0 only. + rlc_start() returns it so the failure reaches the EOC exit code. */ +static uint32_t rlc_check_failed; + /* cluster_entry() dispatches behavior based on core_id: cores listed in producer_core_ids/consumer_core_ids (see the generated data header) run the RLC kernel; any other core stays idle for this run and just reaches @@ -1232,7 +1236,7 @@ void cluster_entry(const unsigned int core_id) { the AM path never writes -- it assembles transport blocks instead, and those are checked at commit time by rlc_am_verify_grant(). */ if (core_id == 0) { - rlc_am_report(); + rlc_check_failed |= rlc_am_report(); } #elif defined(RLC_SELF_CHECK) /* All sends are complete and tgt buffers are stable here. */ @@ -1240,6 +1244,11 @@ void cluster_entry(const unsigned int core_id) { self_check(pdcp_pkgs, NUM_PKGS); } #endif +#if RLC_UL_MODE + if (core_id == 0) { + rlc_check_failed |= atomic_load_explicit(&rlc_ul_failed, memory_order_relaxed); + } +#endif if(core_id == 0) { perf_probe(PROBE_EVT_KERNEL_END, 0u); @@ -1271,9 +1280,10 @@ void cluster_entry(const unsigned int core_id) { } -void rlc_start(const unsigned int core_id) { +int rlc_start(const unsigned int core_id) { /* Enter per-core processing based on core_id */ cluster_entry(core_id); + return (core_id == 0) ? (int)rlc_check_failed : 0; } diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.h b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.h index 2b5601c..d62b174 100644 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.h +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.h @@ -290,8 +290,9 @@ void rlc_init(const unsigned int rlcId, const unsigned int cellId, mm_context_t /* rlc_start() initializes shared RLC resources and starts the RLC kernel for the current core. The core ID, obtained in main(), is passed here. + Returns non-zero on core 0 when a compiled-in result check failed. */ -void rlc_start(const unsigned int core_id); +int rlc_start(const unsigned int core_id); /* cluster_entry() is the per-core entry function for the RLC kernel. diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.c b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.c index 5ffa652..c4963e0 100644 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.c +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.c @@ -1096,8 +1096,9 @@ void rlc_am_status(void) { #endif } -void rlc_am_report(void) { +uint32_t rlc_am_report(void) { uint32_t grants = 0u, pdus = 0u, segs = 0u, polls = 0u; + uint32_t failed = 0u; #if RLC_TILE_AFFINITY /* The entities live in other tiles' private partitions; each owner added its totals on exit. */ grants = rlc_am_tot[0]; pdus = rlc_am_tot[1]; segs = rlc_am_tot[2]; polls = rlc_am_tot[3]; @@ -1177,6 +1178,7 @@ void rlc_am_report(void) { atomic_load_explicit(&rlc_am_plan_bad, memory_order_relaxed); printf("[AM] plan vector-vs-reference mismatches: %u -> %s\n", pb, pb ? "FAIL" : "PASS"); + failed |= (pb != 0u); } #endif #ifdef RLC_SELF_CHECK @@ -1187,6 +1189,7 @@ void rlc_am_report(void) { atomic_load_explicit(&rlc_am_verify_grants, memory_order_relaxed); printf("[AM] transport-block check: %u grants, %u mismatches -> %s\n", vg, ve, ve ? "FAIL" : "PASS"); + failed |= (ve != 0u); for (uint32_t u = 0u; u < NUM_USERS; u++) { const rlc_am_entity_t *e = &rlc_am_ent[u]; if (!e->verify_mask) continue; @@ -1205,6 +1208,7 @@ void rlc_am_report(void) { } #endif printf_lock_release(&printf_lock); + return failed; } /* ------------------------------------------------------------------------ */ diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.h b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.h index 907f5d8..39baf74 100644 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.h +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_am.h @@ -372,7 +372,8 @@ void rlc_am_consumer_tti(uint32_t core_id); void rlc_am_consumer_tile(uint32_t core_id); /* Print the AM summary (grants, PDUs, segments, polls) and, when the checks - are compiled in, the verdict. Call on one core after the final barrier. */ -void rlc_am_report(void); + are compiled in, the verdict. Call on one core after the final barrier. + Returns non-zero if a check failed. */ +uint32_t rlc_am_report(void); #endif /* RLC_AM_H */ diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_ul_drv.c b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_ul_drv.c index 020c985..618c36a 100644 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_ul_drv.c +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_ul_drv.c @@ -124,6 +124,10 @@ static uint32_t rlc_ul_status_pdus; static _Atomic uint32_t rlc_ul_stop __attribute__((aligned(CACHE_LINE_SIZE))) __attribute__((section(".data"))); +/* Set by consumer 0 when the end-of-run check fails; core 0 reads it after the final barrier. */ +static _Atomic uint32_t rlc_ul_failed __attribute__((aligned(CACHE_LINE_SIZE))) + __attribute__((section(".data"))); + /* Per-phase cycle accounting. build/scan/deliver run on consumer 0 only; reassemble is per-core, because the point of the measurement is how the @@ -264,15 +268,14 @@ static void rlc_ul_slot(uint32_t me, const rlc_bar_t *bar) { static void rlc_ul_report(const rlc_bar_t *bar) { const rlc_ul_entity_t *e = &rlc_ul_ent[0]; const uint32_t want = (uint32_t)RLC_UL_SDUS * RLC_UL_SDU_BYTES; + const uint32_t ok = e->delivered == RLC_UL_SDUS && e->out_of_window == 0u && + e->delivered_bytes == want; + atomic_store_explicit(&rlc_ul_failed, ok ? 0u : 1u, memory_order_relaxed); printf_lock_acquire(&printf_lock); printf("[UL] barrier slot=%u core_mask=0x%x tile_mask=0x%x local_only=%u " "group_mask=0x%x\n", RLC_BARRIER_SLOT, bar->core_mask, bar->tile_mask, bar->local_only, bar->group_mask); - printf("[UL] check: %s\n", - (e->delivered == RLC_UL_SDUS && e->out_of_window == 0u && - e->delivered_bytes == want) - ? "PASS" - : "FAIL"); + printf("[UL] check: %s\n", ok ? "PASS" : "FAIL"); printf_lock_release(&printf_lock); } diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/main.c b/software/rlc/multi_producer_single_consumer_double_linked_list/main.c index 5cfbe3b..b4808cb 100644 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/main.c +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/main.c @@ -121,10 +121,10 @@ int main(void) { // DEBUG_PRINTF("[core %u] post snrt_cluster_hw_barrier() done\n", core_id); // DEBUG_PRINTF_LOCK_RELEASE(&printf_lock); - rlc_start(core_id); + const int ret = rlc_start(core_id); // Wait for all cores to finish snrt_cluster_hw_barrier(); // this can trigger Misaligned Load exception - return 0; + return ret; } From e26b010f898456487d148d0261f3665653d48c59 Mon Sep 17 00:00:00 2001 From: Zexin Fu Date: Fri, 16 Oct 2026 21:27:33 +0200 Subject: [PATCH 48/48] rlc: fix review findings in the PDU, planner and uplink code Correct the 12-bit STATUS header length, set the buffer-empty poll only when the grant carries every gathered SDU, check the SI-dependent header length before parsing, let RX_Next_Highest advance by a full window, skip the downlink self-check in uplink builds, and mark the probe builds GVSoC-only. --- software/rlc/CMakeLists.txt | 2 ++ .../kernel/perf_probe.h | 8 ++++++-- .../kernel/rlc.c | 5 +++-- .../kernel/rlc_pdu.h | 2 +- .../kernel/rlc_plan.c | 5 +++-- .../kernel/rlc_ul.c | 5 +++-- .../test/test_rlc_plan.c | 2 +- 7 files changed, 19 insertions(+), 10 deletions(-) diff --git a/software/rlc/CMakeLists.txt b/software/rlc/CMakeLists.txt index c273337..798b8c3 100644 --- a/software/rlc/CMakeLists.txt +++ b/software/rlc/CMakeLists.txt @@ -84,6 +84,7 @@ add_spatz_test_rlc_am(multi_producer_single_consumer_double_linked_list multi_pr # Same kernels with RLC_PROBE=1: they also emit software probe events (role, phase, SDU/PDU, # queue depth, per-packet latency, TTI) for the GVSoC perf-probe collector. Targets get a # `_probe` suffix; the default targets above are untouched and stay byte-identical. +# GVSoC only: on RTL the probe stores land on cluster control registers (see perf_probe.h). macro(add_spatz_test_rlc_probe suffix name file param1 param2 param3) set(target_name ${name}_M${param1}_N${param2}_K${param3}${suffix}_probe) add_snitch_test(${target_name} ${file}) @@ -105,6 +106,7 @@ add_spatz_test_rlc_probe("_P2_C2_am_G8192" multi_producer_single_consumer_double # exhausted pool drops the packet whose descriptor the producer already took. # The data header comes from script/data____.json (`make gen-data`). # `variant` is appended to the target name and says which extra defines (ARGN) it carries. +# Each case also gets a GVSoC-only `_probe` twin (RLC_PROBE=1, see the probe variants above). macro(add_spatz_test_rlc_full layout variant name file param1 param2 param3) string(TOLOWER ${layout} layout_lc) foreach(probe 0 1) diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/perf_probe.h b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/perf_probe.h index ff5026c..f24756c 100644 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/perf_probe.h +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/perf_probe.h @@ -19,8 +19,12 @@ * kernel tree, or add core/models/probe to the include path. * * One posted 32-bit store per event, to an address that encodes the hart and the event id - * (perf_probe_events.h). The GVSoC collector decodes it; an RTL testbench snoops the same window, - * so the instrumentation in the kernel is identical for both engines. + * (perf_probe_events.h). The GVSoC collector decodes it. + * + * GVSoC ONLY: the RTL has no probe endpoint. Its peripheral decode sends the whole window to the + * cluster register block, which keeps only the low 7 address bits, so on RTL every probe store + * overwrites a control register (barrier, Spatz lock, EOC exit, ...). Never run an RLC_PROBE=1 + * binary on RTL. * * EVERYTHING COMPILES AWAY unless the build defines RLC_PROBE=1, so the default binaries stay * byte-identical. Enable with -DRLC_PROBE=1. diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.c b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.c index 43767ac..e911bca 100644 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.c +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc.c @@ -1238,8 +1238,9 @@ void cluster_entry(const unsigned int core_id) { if (core_id == 0) { rlc_check_failed |= rlc_am_report(); } -#elif defined(RLC_SELF_CHECK) - /* All sends are complete and tgt buffers are stable here. */ +#elif defined(RLC_SELF_CHECK) && !RLC_UL_MODE + /* All sends are complete and tgt buffers are stable here. The uplink never + writes the tgt buffers; it reports its own verdict below. */ if (core_id == 0) { self_check(pdcp_pkgs, NUM_PKGS); } diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_pdu.h b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_pdu.h index 42a7c86..5eedae1 100644 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_pdu.h +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_pdu.h @@ -145,7 +145,7 @@ static inline void rlc_amd_hdr_read(const uint8_t *p, rlc_amd_hdr_t *h) { #if RLC_SN_BITS == 18 #define RLC_STATUS_HDR_LEN 3u /* D/C|CPT(3)|ACK_SN[17:14] | [13:6] | [5:0]|E1|R */ #else -#define RLC_STATUS_HDR_LEN 2u /* D/C|CPT(3)|ACK_SN[11:8] | [7:0] ... + E1|R */ +#define RLC_STATUS_HDR_LEN 3u /* D/C|CPT(3)|ACK_SN[11:8] | [7:0] | E1|R(7) */ #endif /* Serialise a STATUS PDU header with the given ACK_SN. e1 = 1 when at least diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_plan.c b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_plan.c index c1158b2..39c4378 100644 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_plan.c +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_plan.c @@ -485,7 +485,8 @@ uint32_t rlc_plan_compute_scalar(rlc_plan_t *plan, const rlc_plan_in_t *in, } /* A poll is also triggered when the buffer runs empty (ยง5.3.3.2). */ - if (n > 0u && in->queue_drained && !partial && !plan->poll[n - 1u]) { + if (n > 0u && n == plan->n_avail && in->queue_drained && !partial && + !plan->poll[n - 1u]) { plan->poll[n - 1u] = 1u; pwp = 0u; bwp = 0u; @@ -607,7 +608,7 @@ uint32_t rlc_plan_compute_vector(rlc_plan_t *plan, const rlc_plan_in_t *in, uint32_t bwp = in->byte_without_poll; rlc_plan_polls_vector(plan, in, n, &pwp, &bwp); - if (in->queue_drained && !partial && !plan->poll[n - 1u]) { + if (n == n_avail && in->queue_drained && !partial && !plan->poll[n - 1u]) { plan->poll[n - 1u] = 1u; pwp = 0u; bwp = 0u; diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_ul.c b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_ul.c index c4071a1..0a3058e 100644 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_ul.c +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/kernel/rlc_ul.c @@ -79,9 +79,9 @@ uint32_t rlc_ul_scan(rlc_ul_scan_t *s, const uint8_t *tb, uint32_t tb_len) { /* The header must be parsed to know its own length: SO is present only for LAST/MIDDLE, and SI lives inside the first byte. This is what forces the walk to be sequential. */ + if (rlc_amd_hdr_len((tb[off] >> 4) & 3u) > plen) { s->truncated = 1u; break; } rlc_amd_hdr_t h; rlc_amd_hdr_read(tb + off, &h); - if (h.hdr_len > plen) { s->truncated = 1u; break; } if (s->n >= RLC_UL_MAX_PDUS) { s->overflow = 1u; break; } @@ -185,7 +185,8 @@ void rlc_ul_reassemble_range(rlc_ul_entity_t *e, const rlc_ul_scan_t *s, void rlc_ul_note_highest(rlc_ul_entity_t *e, const rlc_ul_scan_t *s) { if (!s->have_sn) return; const uint32_t nh = (s->max_sn + 1u) & RLC_SN_MASK; - if (((nh - e->rx_next_highest) & RLC_SN_MASK) < RLC_UL_WINDOW) + const uint32_t ahead = (nh - e->rx_next_highest) & RLC_SN_MASK; + if (ahead != 0u && ahead <= RLC_UL_WINDOW) e->rx_next_highest = nh; } diff --git a/software/rlc/multi_producer_single_consumer_double_linked_list/test/test_rlc_plan.c b/software/rlc/multi_producer_single_consumer_double_linked_list/test/test_rlc_plan.c index a772d50..b079af5 100644 --- a/software/rlc/multi_producer_single_consumer_double_linked_list/test/test_rlc_plan.c +++ b/software/rlc/multi_producer_single_consumer_double_linked_list/test/test_rlc_plan.c @@ -167,7 +167,7 @@ static void run_stream(const char *name, uint32_t n_sdus, uint32_t sdu_lo, if (want_poll) { m_pwp = 0; m_bwp = 0; } /* the buffer-empty poll is applied by the planner to the final PDU */ const int drained_here = - in.queue_drained && !out.partial && (i == n - 1u); + in.queue_drained && n == avail && !out.partial && (i == n - 1u); if (drained_here && !want_poll) { want_poll = 1; m_pwp = 0;