From 085f656c20bfa338796e6e1c4cb1144e2aa0711f Mon Sep 17 00:00:00 2001
From: Luca Toniolo <10792599+grandixximo@users.noreply.github.com>
Date: Mon, 28 Sep 2026 16:52:05 +1000
Subject: [PATCH] halmodule: fix inverted success check in port read() and
 peek()

hal_port_read() and hal_port_peek() return true when the bytes were copied. The check was inverted, so a successful read or peek returned False, and read() had already consumed the data. Add tests/halmodule/port covering write, peek, peek_commit and read.
---
 src/hal/halmodule.cc             |  2 +-
 tests/halmodule/port/expected    |  1 +
 tests/halmodule/port/porttest.py | 19 +++++++++++++++++++
 tests/halmodule/port/test.hal    |  1 +
 4 files changed, 22 insertions(+), 1 deletion(-)
 create mode 100644 tests/halmodule/port/expected
 create mode 100755 tests/halmodule/port/porttest.py
 create mode 100644 tests/halmodule/port/test.hal

diff --git a/src/hal/halmodule.cc b/src/hal/halmodule.cc
index 043581ca470..43735ccaf6b 100644
--- a/src/hal/halmodule.cc
+++ b/src/hal/halmodule.cc
@@ -970,7 +970,7 @@ static PyObject *pyhal_port_read_peek(pyhalitem *item, PyObject *o, bool isread)
         b = hal_port_read(item->pin.u->p, PyBytes_AsString(bts), (unsigned)l);
     else
         b = hal_port_peek(item->pin.u->p, PyBytes_AsString(bts), (unsigned)l);
-    if(b) {
+    if(!b) {
         Py_DECREF(bts);
         Py_INCREF(Py_False);
         return Py_False;
diff --git a/tests/halmodule/port/expected b/tests/halmodule/port/expected
new file mode 100644
index 00000000000..2ae28399f5f
--- /dev/null
+++ b/tests/halmodule/port/expected
@@ -0,0 +1 @@
+pass
diff --git a/tests/halmodule/port/porttest.py b/tests/halmodule/port/porttest.py
new file mode 100755
index 00000000000..3b94b56714b
--- /dev/null
+++ b/tests/halmodule/port/porttest.py
@@ -0,0 +1,19 @@
+#!/usr/bin/env python3
+# Port pins: write, then peek/peek_commit/read the same bytes back.
+import hal
+c = hal.component("porttest")
+wr = c.newpin("out", hal.Type.PORT, hal.Dir.OUT)
+rd = c.newpin("in", hal.Type.PORT, hal.Dir.IN)
+c.ready()
+hal.new_sig("portsig", hal.Type.PORT)
+hal.connect("porttest.out", "portsig")
+hal.connect("porttest.in", "portsig")
+hal.set_s("portsig", "16")
+
+assert wr.write(b"hello world")
+assert rd.peek(5) == b"hello"
+assert rd.peek_commit(6)
+assert rd.read(5) == b"world"
+assert rd.read(1) is False
+c.exit()
+print("pass")
diff --git a/tests/halmodule/port/test.hal b/tests/halmodule/port/test.hal
new file mode 100644
index 00000000000..bfaea531cdd
--- /dev/null
+++ b/tests/halmodule/port/test.hal
@@ -0,0 +1 @@
+loadusr -w ./porttest.py