diff --git a/.github/workflows/Test_Alif_E7.yml b/.github/workflows/Test_Alif_E7.yml index 30dc0e9..b006930 100644 --- a/.github/workflows/Test_Alif_E7.yml +++ b/.github/workflows/Test_Alif_E7.yml @@ -82,7 +82,7 @@ jobs: - name: Run on simulator working-directory: ${{env.DIR}} run: | - FVP_Corstone_SSE-300_Ethos-U55 -f ./Board/Corstone-300/fvp_config.txt -a ./out/AlgorithmTest/SSE-300-U55/Debug/AlgorithmTest.hex --simlimit 120 || true + FVP_Corstone_SSE-300_Ethos-U55 -f ./Board/Corstone-300/fvp_config_u55.txt -a ./out/AlgorithmTest/SSE-300-U55/Debug/AlgorithmTest.hex --simlimit 120 || true - name: Print sdsio.log file working-directory: ${{env.DIR}}/algorithm/SDS Recordings diff --git a/.github/workflows/Test_ST_KeywordSpotting.yml b/.github/workflows/Test_ST_KeywordSpotting.yml index aaff775..9d28541 100644 --- a/.github/workflows/Test_ST_KeywordSpotting.yml +++ b/.github/workflows/Test_ST_KeywordSpotting.yml @@ -82,7 +82,7 @@ jobs: - name: Run on simulator working-directory: ${{env.DIR}} run: | - FVP_Corstone_SSE-300_Ethos-U55 -f ./Board/Corstone-300/fvp_config.txt -a ./out/AlgorithmTest/SSE-300-U55/Debug/AlgorithmTest.hex --simlimit 120 || true + FVP_Corstone_SSE-300_Ethos-U55 -f ./Board/Corstone-300/fvp_config_u55.txt -a ./out/AlgorithmTest/SSE-300-U55/Debug/AlgorithmTest.hex --simlimit 120 || true - name: Print sdsio.log file working-directory: ${{env.DIR}}/algorithm/SDS Recordings diff --git a/.github/workflows/Test_ST_MotionRecognition.yml b/.github/workflows/Test_ST_MotionRecognition.yml index 94c75f7..ff6d3fe 100644 --- a/.github/workflows/Test_ST_MotionRecognition.yml +++ b/.github/workflows/Test_ST_MotionRecognition.yml @@ -82,7 +82,7 @@ jobs: - name: Run on simulator working-directory: ${{env.DIR}} run: | - FVP_Corstone_SSE-300_Ethos-U55 -f ./Board/Corstone-300/fvp_config.txt -a ./out/AlgorithmTest/SSE-300-U55/Debug/AlgorithmTest.hex --simlimit 120 || true + FVP_Corstone_SSE-300_Ethos-U55 -f ./Board/Corstone-300/fvp_config_u55.txt -a ./out/AlgorithmTest/SSE-300-U55/Debug/AlgorithmTest.hex --simlimit 120 || true - name: Print sdsio.log file working-directory: ${{env.DIR}}/algorithm/SDS Recordings diff --git a/Alif/AppKit-E7_USB/Board/Corstone-300/Board-U55.clayer.yml b/Alif/AppKit-E7_USB/Board/Corstone-300/Board-U55.clayer.yml index b033b5d..8d5541b 100644 --- a/Alif/AppKit-E7_USB/Board/Corstone-300/Board-U55.clayer.yml +++ b/Alif/AppKit-E7_USB/Board/Corstone-300/Board-U55.clayer.yml @@ -1,6 +1,6 @@ layer: type: Board - description: Board setup for AI/ML with Ethos U55 + description: Base configuration of SSE-300 FVP with Ethos U55 for-board: ARM::V2M-MPS3-SSE-300-FVP for-device: ARM::SSE-300-MPS3 @@ -12,18 +12,18 @@ layer: - STDIN - STDOUT - STDERR - - Heap: 786432 + - Heap: 98304 + consumes: + - CMSIS-RTOS2 define: - CMSIS_target_header: \"Corstone-300.h\" - - ETHOSU55 - CORSTONE300_FVP - - ARM_MODEL_USE_PMU_COUNTERS packs: - pack: ARM::CMSIS - - pack: ARM::CMSIS-Compiler@^2.1.0 - - pack: ARM::ethos-u-core-driver@^1.25.2 + - pack: ARM::CMSIS-Compiler@^2.3.0 + - pack: ARM::CMSIS-Ethos-U@^1.0.0 - pack: ARM::V2M_MPS3_SSE_300_BSP@1.5.0 components: @@ -33,9 +33,9 @@ layer: - component: CMSIS Driver:VIO - component: CMSIS-Compiler:CORE - - component: CMSIS-Compiler:STDERR:Custom - - component: CMSIS-Compiler:STDIN:Custom - - component: CMSIS-Compiler:STDOUT:Custom + - component: CMSIS-Compiler:STDERR:UART&CMSIS + - component: CMSIS-Compiler:STDIN:UART&CMSIS + - component: CMSIS-Compiler:STDOUT:UART&CMSIS - component: Device:Definition - component: Device:Startup&C Startup @@ -46,14 +46,17 @@ layer: - component: Device:Native Driver:UART - component: Machine Learning:NPU Support:Ethos-U Driver&Generic U55 + define: + - ETHOSU_MACS: 256 groups: - group: Board files: - - file: ./main.c - - file: ./main.h - - file: ./ethos_setup.c - - file: ./retarget_stdio.c + - file: main.c + - file: main.h + - file: ethos_setup.c + - file: ethosu_os_rtos2.c + - file: ethosu_dcache.c linker: - - regions: ./regions_SSE-300.h + - regions: RTE/Device/SSE-300-MPS3/regions_SSE-300.h diff --git a/Alif/AppKit-E7_USB/Board/Corstone-300/Board-U65.clayer.yml b/Alif/AppKit-E7_USB/Board/Corstone-300/Board-U65.clayer.yml index e0bed61..4cebf52 100644 --- a/Alif/AppKit-E7_USB/Board/Corstone-300/Board-U65.clayer.yml +++ b/Alif/AppKit-E7_USB/Board/Corstone-300/Board-U65.clayer.yml @@ -1,6 +1,6 @@ layer: type: Board - description: Board setup for AI/ML with Ethos U65 + description: Base configuration of SSE-300 FVP with Ethos U65 for-board: ARM::V2M-MPS3-SSE-300-FVP for-device: ARM::SSE-300-MPS3 @@ -12,18 +12,18 @@ layer: - STDIN - STDOUT - STDERR - - Heap: 786432 + - Heap: 98304 + consumes: + - CMSIS-RTOS2 define: - CMSIS_target_header: \"Corstone-300.h\" - - ETHOSU65 - CORSTONE300_FVP - - ARM_MODEL_USE_PMU_COUNTERS packs: - pack: ARM::CMSIS - - pack: ARM::CMSIS-Compiler@^2.1.0 - - pack: ARM::ethos-u-core-driver@^1.25.2 + - pack: ARM::CMSIS-Compiler@^2.3.0 + - pack: ARM::CMSIS-Ethos-U@^1.0.0 - pack: ARM::V2M_MPS3_SSE_300_BSP@1.5.0 components: @@ -33,9 +33,9 @@ layer: - component: CMSIS Driver:VIO - component: CMSIS-Compiler:CORE - - component: CMSIS-Compiler:STDERR:Custom - - component: CMSIS-Compiler:STDIN:Custom - - component: CMSIS-Compiler:STDOUT:Custom + - component: CMSIS-Compiler:STDERR:UART&CMSIS + - component: CMSIS-Compiler:STDIN:UART&CMSIS + - component: CMSIS-Compiler:STDOUT:UART&CMSIS - component: Device:Definition - component: Device:Startup&C Startup @@ -46,14 +46,17 @@ layer: - component: Device:Native Driver:UART - component: Machine Learning:NPU Support:Ethos-U Driver&Generic U65 + define: + - ETHOSU_MACS: 256 groups: - group: Board files: - - file: ./main.c - - file: ./main.h - - file: ./ethos_setup.c - - file: ./retarget_stdio.c + - file: main.c + - file: main.h + - file: ethos_setup.c + - file: ethosu_os_rtos2.c + - file: ethosu_dcache.c linker: - - regions: ./regions_SSE-300.h + - regions: RTE/Device/SSE-300-MPS3/regions_SSE-300.h diff --git a/Alif/AppKit-E7_USB/Board/Corstone-300/Board.clayer.yml b/Alif/AppKit-E7_USB/Board/Corstone-300/Board.clayer.yml index b7c2fe0..2fa6b04 100644 --- a/Alif/AppKit-E7_USB/Board/Corstone-300/Board.clayer.yml +++ b/Alif/AppKit-E7_USB/Board/Corstone-300/Board.clayer.yml @@ -1,6 +1,6 @@ layer: type: Board - description: Board setup for AI/ML + description: Base configuration of SSE-300 FVP for-board: ARM::V2M-MPS3-SSE-300-FVP for-device: ARM::SSE-300-MPS3 @@ -12,16 +12,15 @@ layer: - STDIN - STDOUT - STDERR - - Heap: 786432 + - Heap: 98304 define: - CMSIS_target_header: \"Corstone-300.h\" - CORSTONE300_FVP - - ARM_MODEL_USE_PMU_COUNTERS packs: - pack: ARM::CMSIS - - pack: ARM::CMSIS-Compiler@^2.1.0 + - pack: ARM::CMSIS-Compiler@^2.3.0 - pack: ARM::V2M_MPS3_SSE_300_BSP@1.5.0 components: @@ -31,9 +30,9 @@ layer: - component: CMSIS Driver:VIO - component: CMSIS-Compiler:CORE - - component: CMSIS-Compiler:STDERR:Custom - - component: CMSIS-Compiler:STDIN:Custom - - component: CMSIS-Compiler:STDOUT:Custom + - component: CMSIS-Compiler:STDERR:UART&CMSIS + - component: CMSIS-Compiler:STDIN:UART&CMSIS + - component: CMSIS-Compiler:STDOUT:UART&CMSIS - component: Device:Definition - component: Device:Startup&C Startup @@ -46,9 +45,8 @@ layer: groups: - group: Board files: - - file: ./main.c - - file: ./main.h - - file: ./retarget_stdio.c + - file: main.c + - file: main.h linker: - - regions: ./regions_SSE-300.h + - regions: RTE/Device/SSE-300-MPS3/regions_SSE-300.h diff --git a/Alif/AppKit-E7_USB/Board/Corstone-300/Corstone-300.h b/Alif/AppKit-E7_USB/Board/Corstone-300/Corstone-300.h index 8d1a416..4abb85d 100644 --- a/Alif/AppKit-E7_USB/Board/Corstone-300/Corstone-300.h +++ b/Alif/AppKit-E7_USB/Board/Corstone-300/Corstone-300.h @@ -1,6 +1,6 @@ -/*--------------------------------------------------------------------------- - * Copyright (c) 2025 Arm Limited (or its affiliates). - * All rights reserved. +/* + * Copyright 2025-2026 Arm Limited and/or its affiliates. + * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may @@ -14,7 +14,7 @@ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. - *---------------------------------------------------------------------------*/ + */ #ifndef CORSTONE_300_H_ #define CORSTONE_300_H_ diff --git a/Alif/AppKit-E7_USB/Board/Corstone-300/README.md b/Alif/AppKit-E7_USB/Board/Corstone-300/README.md index 97555a2..4b287fd 100644 --- a/Alif/AppKit-E7_USB/Board/Corstone-300/README.md +++ b/Alif/AppKit-E7_USB/Board/Corstone-300/README.md @@ -1,20 +1,30 @@ # Board: Arm V2M-MPS3-SSE-300-FVP -## Board Layer for Corstone-300 FVP +## Board Layers for Corstone-300 FVP -This layer works for: +These layers work for: ```yml board: ARM::V2M-MPS3-SSE-300-FVP device: ARM::SSE-300-MPS3 ``` +Select one layer matching the application's NPU requirements: + +| Layer file | Use in Application +|:---------------------|:------------------------ +| Board.clayer.yml | Without Ethos-U support +| Board-U55.clayer.yml | With Ethos-U55 support +| Board-U65.clayer.yml | With Ethos-U65 support + +Use the corresponding FVP configuration file listed below. + ### System Configuration | System Component | Setting |:------------------------|:---------------------------------- -| Heap | 768 kB (configured in linker file) -| Stack (MSP) | 32 kB (configured in linker file) +| Heap | 96 kB (configured in regions header) +| Stack (MSP) | 4 kB (configured in regions header) ### STDIO mapping @@ -41,4 +51,6 @@ interface for SDS data files using a [Virtual Streaming Interface](https://arm-s | File | Description |:-------------------|:------------- -| fvp_config.txt | Corstone-300 FVP without Ethos-U or with Ethos-U55/U65 +| fvp_config.txt | Corstone-300 FVP without Ethos-U +| fvp_config_u55.txt | Corstone-300 FVP with an Ethos-U55-256 +| fvp_config_u65.txt | Corstone-300 FVP with an Ethos-U65-256 diff --git a/Alif/AppKit-E7_USB/Board/Corstone-300/RTE/CMSIS-Compiler/stderr_cmsis_uart_config.h b/Alif/AppKit-E7_USB/Board/Corstone-300/RTE/CMSIS-Compiler/stderr_cmsis_uart_config.h new file mode 100644 index 0000000..d6a30a3 --- /dev/null +++ b/Alif/AppKit-E7_USB/Board/Corstone-300/RTE/CMSIS-Compiler/stderr_cmsis_uart_config.h @@ -0,0 +1,59 @@ +/*--------------------------------------------------------------------------- + * Copyright (c) 2026 Arm Limited (or its affiliates). + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * -------------------------------------------------------------------------- + * + * Purpose: Configure STDERR to CMSIS-Driver USART retarget implementation + * Revision: V1.0.0 + * + * --------------------------------------------------------------------------*/ + +#ifndef STDERR_CMSIS_UART_CONFIG_H_ +#define STDERR_CMSIS_UART_CONFIG_H_ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// UART STDERR Buffer Size +// UART STDERR buffer is used to store STDERR data before sending it via UART +// Default: 0 (unbuffered) +#ifndef STDERR_UART_BUFFER_SIZE +#define STDERR_UART_BUFFER_SIZE 0 +#endif + +// UART STDERR Buffer Section Name +// Specify the memory section name for UART STDERR buffer +// Default: .stderr_uart_buf +#ifndef STDERR_UART_BUFFER_SECTION +#define STDERR_UART_BUFFER_SECTION ".stderr_uart_buf" +#endif + +// UART STDERR Buffer Alignment +// Define the STDERR buffer alignment in bytes +// Default: 32 +#ifndef STDERR_UART_BUFFER_ALIGNMENT +#define STDERR_UART_BUFFER_ALIGNMENT 32 +#endif + +// Convert LF to CRLF +// If enabled, LF characters are preceded by CR characters on output +// Default: 0 +#ifndef STDERR_CR_LF +#define STDERR_CR_LF 1 +#endif + +#endif /* STDERR_CMSIS_UART_CONFIG_H_ */ diff --git a/Alif/AppKit-E7_USB/Board/Corstone-300/RTE/CMSIS-Compiler/stderr_cmsis_uart_config.h.base@1.0.0 b/Alif/AppKit-E7_USB/Board/Corstone-300/RTE/CMSIS-Compiler/stderr_cmsis_uart_config.h.base@1.0.0 new file mode 100644 index 0000000..192648e --- /dev/null +++ b/Alif/AppKit-E7_USB/Board/Corstone-300/RTE/CMSIS-Compiler/stderr_cmsis_uart_config.h.base@1.0.0 @@ -0,0 +1,59 @@ +/*--------------------------------------------------------------------------- + * Copyright (c) 2026 Arm Limited (or its affiliates). + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * -------------------------------------------------------------------------- + * + * Purpose: Configure STDERR to CMSIS-Driver USART retarget implementation + * Revision: V1.0.0 + * + * --------------------------------------------------------------------------*/ + +#ifndef STDERR_CMSIS_UART_CONFIG_H_ +#define STDERR_CMSIS_UART_CONFIG_H_ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// UART STDERR Buffer Size +// UART STDERR buffer is used to store STDERR data before sending it via UART +// Default: 0 (unbuffered) +#ifndef STDERR_UART_BUFFER_SIZE +#define STDERR_UART_BUFFER_SIZE 0 +#endif + +// UART STDERR Buffer Section Name +// Specify the memory section name for UART STDERR buffer +// Default: .stderr_uart_buf +#ifndef STDERR_UART_BUFFER_SECTION +#define STDERR_UART_BUFFER_SECTION ".stderr_uart_buf" +#endif + +// UART STDERR Buffer Alignment +// Define the STDERR buffer alignment in bytes +// Default: 32 +#ifndef STDERR_UART_BUFFER_ALIGNMENT +#define STDERR_UART_BUFFER_ALIGNMENT 32 +#endif + +// Convert LF to CRLF +// If enabled, LF characters are preceded by CR characters on output +// Default: 0 +#ifndef STDERR_CR_LF +#define STDERR_CR_LF 0 +#endif + +#endif /* STDERR_CMSIS_UART_CONFIG_H_ */ diff --git a/Alif/AppKit-E7_USB/Board/Corstone-300/RTE/CMSIS-Compiler/stdin_cmsis_uart_config.h b/Alif/AppKit-E7_USB/Board/Corstone-300/RTE/CMSIS-Compiler/stdin_cmsis_uart_config.h new file mode 100644 index 0000000..bce0ba2 --- /dev/null +++ b/Alif/AppKit-E7_USB/Board/Corstone-300/RTE/CMSIS-Compiler/stdin_cmsis_uart_config.h @@ -0,0 +1,59 @@ +/*--------------------------------------------------------------------------- + * Copyright (c) 2026 Arm Limited (or its affiliates). + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * -------------------------------------------------------------------------- + * + * Purpose: Configure STDIN to CMSIS-Driver USART retarget implementation + * Revision: V1.0.0 + * + * --------------------------------------------------------------------------*/ + +#ifndef STDIN_CMSIS_UART_CONFIG_H_ +#define STDIN_CMSIS_UART_CONFIG_H_ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// UART STDIN Buffer Size +// UART STDIN buffer is used to store STDIN data received via UART +// Default: 64 +#ifndef STDIN_UART_BUFFER_SIZE +#define STDIN_UART_BUFFER_SIZE 64 +#endif + +// UART STDIN Buffer Section Name +// Specify the memory section name for UART STDIN buffer +// Default: .stdin_uart_buf +#ifndef STDIN_UART_BUFFER_SECTION +#define STDIN_UART_BUFFER_SECTION ".stdin_uart_buf" +#endif + +// UART STDIN Buffer Alignment +// Define the STDIN buffer alignment in bytes +// Default: 32 +#ifndef STDIN_UART_BUFFER_ALIGNMENT +#define STDIN_UART_BUFFER_ALIGNMENT 32 +#endif + +// Echo Input Characters +// If enabled, received characters are echoed to STDOUT +// Default: 0 +#ifndef STDIN_ECHO +#define STDIN_ECHO 0 +#endif + +#endif /* STDIN_CMSIS_UART_CONFIG_H_ */ diff --git a/Alif/AppKit-E7_USB/Board/Corstone-300/RTE/CMSIS-Compiler/stdin_cmsis_uart_config.h.base@1.0.0 b/Alif/AppKit-E7_USB/Board/Corstone-300/RTE/CMSIS-Compiler/stdin_cmsis_uart_config.h.base@1.0.0 new file mode 100644 index 0000000..bce0ba2 --- /dev/null +++ b/Alif/AppKit-E7_USB/Board/Corstone-300/RTE/CMSIS-Compiler/stdin_cmsis_uart_config.h.base@1.0.0 @@ -0,0 +1,59 @@ +/*--------------------------------------------------------------------------- + * Copyright (c) 2026 Arm Limited (or its affiliates). + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * -------------------------------------------------------------------------- + * + * Purpose: Configure STDIN to CMSIS-Driver USART retarget implementation + * Revision: V1.0.0 + * + * --------------------------------------------------------------------------*/ + +#ifndef STDIN_CMSIS_UART_CONFIG_H_ +#define STDIN_CMSIS_UART_CONFIG_H_ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// UART STDIN Buffer Size +// UART STDIN buffer is used to store STDIN data received via UART +// Default: 64 +#ifndef STDIN_UART_BUFFER_SIZE +#define STDIN_UART_BUFFER_SIZE 64 +#endif + +// UART STDIN Buffer Section Name +// Specify the memory section name for UART STDIN buffer +// Default: .stdin_uart_buf +#ifndef STDIN_UART_BUFFER_SECTION +#define STDIN_UART_BUFFER_SECTION ".stdin_uart_buf" +#endif + +// UART STDIN Buffer Alignment +// Define the STDIN buffer alignment in bytes +// Default: 32 +#ifndef STDIN_UART_BUFFER_ALIGNMENT +#define STDIN_UART_BUFFER_ALIGNMENT 32 +#endif + +// Echo Input Characters +// If enabled, received characters are echoed to STDOUT +// Default: 0 +#ifndef STDIN_ECHO +#define STDIN_ECHO 0 +#endif + +#endif /* STDIN_CMSIS_UART_CONFIG_H_ */ diff --git a/Alif/AppKit-E7_USB/Board/Corstone-300/RTE/CMSIS-Compiler/stdio_cmsis_uart_config.h b/Alif/AppKit-E7_USB/Board/Corstone-300/RTE/CMSIS-Compiler/stdio_cmsis_uart_config.h new file mode 100644 index 0000000..aeeca61 --- /dev/null +++ b/Alif/AppKit-E7_USB/Board/Corstone-300/RTE/CMSIS-Compiler/stdio_cmsis_uart_config.h @@ -0,0 +1,52 @@ +/*--------------------------------------------------------------------------- + * Copyright (c) 2026 Arm Limited (or its affiliates). + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * -------------------------------------------------------------------------- + * + * Purpose: STDIO to CMSIS Driver USART Retarget Configuration + * Revision: V1.0.0 + * + * --------------------------------------------------------------------------*/ + +#ifndef STDIO_CMSIS_UART_CONFIG_H_ +#define STDIO_CMSIS_UART_CONFIG_H_ + +#ifdef CMSIS_target_header +#include CMSIS_target_header +#else +#define RETARGET_STDIO_UART 0 +#endif + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// Connect to hardware via Driver_USART# +// Select driver control block for hardware interface +// Default: 0 +#ifndef STDIO_UART_DRIVER +#define STDIO_UART_DRIVER RETARGET_STDIO_UART +#endif + +// UART baudrate +// Specifies the baudrate for UART communication +// Common values: 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 +// Default: 115200 +#ifndef STDIO_UART_BAUDRATE +#define STDIO_UART_BAUDRATE 115200 +#endif + +#endif /* STDIO_CMSIS_UART_CONFIG_H_ */ diff --git a/Alif/AppKit-E7_USB/Board/Corstone-300/RTE/CMSIS-Compiler/stdio_cmsis_uart_config.h.base@1.0.0 b/Alif/AppKit-E7_USB/Board/Corstone-300/RTE/CMSIS-Compiler/stdio_cmsis_uart_config.h.base@1.0.0 new file mode 100644 index 0000000..aeeca61 --- /dev/null +++ b/Alif/AppKit-E7_USB/Board/Corstone-300/RTE/CMSIS-Compiler/stdio_cmsis_uart_config.h.base@1.0.0 @@ -0,0 +1,52 @@ +/*--------------------------------------------------------------------------- + * Copyright (c) 2026 Arm Limited (or its affiliates). + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * -------------------------------------------------------------------------- + * + * Purpose: STDIO to CMSIS Driver USART Retarget Configuration + * Revision: V1.0.0 + * + * --------------------------------------------------------------------------*/ + +#ifndef STDIO_CMSIS_UART_CONFIG_H_ +#define STDIO_CMSIS_UART_CONFIG_H_ + +#ifdef CMSIS_target_header +#include CMSIS_target_header +#else +#define RETARGET_STDIO_UART 0 +#endif + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// Connect to hardware via Driver_USART# +// Select driver control block for hardware interface +// Default: 0 +#ifndef STDIO_UART_DRIVER +#define STDIO_UART_DRIVER RETARGET_STDIO_UART +#endif + +// UART baudrate +// Specifies the baudrate for UART communication +// Common values: 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 +// Default: 115200 +#ifndef STDIO_UART_BAUDRATE +#define STDIO_UART_BAUDRATE 115200 +#endif + +#endif /* STDIO_CMSIS_UART_CONFIG_H_ */ diff --git a/Alif/AppKit-E7_USB/Board/Corstone-300/RTE/CMSIS-Compiler/stdout_cmsis_uart_config.h b/Alif/AppKit-E7_USB/Board/Corstone-300/RTE/CMSIS-Compiler/stdout_cmsis_uart_config.h new file mode 100644 index 0000000..3cdc2ae --- /dev/null +++ b/Alif/AppKit-E7_USB/Board/Corstone-300/RTE/CMSIS-Compiler/stdout_cmsis_uart_config.h @@ -0,0 +1,59 @@ +/*--------------------------------------------------------------------------- + * Copyright (c) 2026 Arm Limited (or its affiliates). + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * -------------------------------------------------------------------------- + * + * Purpose: Configure STDOUT to CMSIS-Driver USART retarget implementation + * Revision: V1.0.0 + * + * --------------------------------------------------------------------------*/ + +#ifndef STDOUT_CMSIS_UART_CONFIG_H_ +#define STDOUT_CMSIS_UART_CONFIG_H_ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// UART STDOUT Buffer Size +// UART STDOUT buffer is used to store STDOUT data before sending it via UART +// Default: 0 (unbuffered) +#ifndef STDOUT_UART_BUFFER_SIZE +#define STDOUT_UART_BUFFER_SIZE 0 +#endif + +// UART STDOUT Buffer Section Name +// Specify the memory section name for UART STDOUT buffer +// Default: .stdout_uart_buf +#ifndef STDOUT_UART_BUFFER_SECTION +#define STDOUT_UART_BUFFER_SECTION ".stdout_uart_buf" +#endif + +// UART STDOUT Buffer Alignment +// Define the buffer alignment in bytes +// Default: 32 +#ifndef STDOUT_UART_BUFFER_ALIGNMENT +#define STDOUT_UART_BUFFER_ALIGNMENT 32 +#endif + +// Convert LF to CRLF +// If enabled, LF characters are preceded by CR characters on output +// Default: 0 +#ifndef STDOUT_CR_LF +#define STDOUT_CR_LF 1 +#endif + +#endif /* STDOUT_CMSIS_UART_CONFIG_H_ */ diff --git a/Alif/AppKit-E7_USB/Board/Corstone-300/RTE/CMSIS-Compiler/stdout_cmsis_uart_config.h.base@1.0.0 b/Alif/AppKit-E7_USB/Board/Corstone-300/RTE/CMSIS-Compiler/stdout_cmsis_uart_config.h.base@1.0.0 new file mode 100644 index 0000000..323d217 --- /dev/null +++ b/Alif/AppKit-E7_USB/Board/Corstone-300/RTE/CMSIS-Compiler/stdout_cmsis_uart_config.h.base@1.0.0 @@ -0,0 +1,59 @@ +/*--------------------------------------------------------------------------- + * Copyright (c) 2026 Arm Limited (or its affiliates). + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * -------------------------------------------------------------------------- + * + * Purpose: Configure STDOUT to CMSIS-Driver USART retarget implementation + * Revision: V1.0.0 + * + * --------------------------------------------------------------------------*/ + +#ifndef STDOUT_CMSIS_UART_CONFIG_H_ +#define STDOUT_CMSIS_UART_CONFIG_H_ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// UART STDOUT Buffer Size +// UART STDOUT buffer is used to store STDOUT data before sending it via UART +// Default: 0 (unbuffered) +#ifndef STDOUT_UART_BUFFER_SIZE +#define STDOUT_UART_BUFFER_SIZE 0 +#endif + +// UART STDOUT Buffer Section Name +// Specify the memory section name for UART STDOUT buffer +// Default: .stdout_uart_buf +#ifndef STDOUT_UART_BUFFER_SECTION +#define STDOUT_UART_BUFFER_SECTION ".stdout_uart_buf" +#endif + +// UART STDOUT Buffer Alignment +// Define the buffer alignment in bytes +// Default: 32 +#ifndef STDOUT_UART_BUFFER_ALIGNMENT +#define STDOUT_UART_BUFFER_ALIGNMENT 32 +#endif + +// Convert LF to CRLF +// If enabled, LF characters are preceded by CR characters on output +// Default: 0 +#ifndef STDOUT_CR_LF +#define STDOUT_CR_LF 0 +#endif + +#endif /* STDOUT_CMSIS_UART_CONFIG_H_ */ diff --git a/Alif/AppKit-E7_USB/Board/Corstone-300/RTE/Device/SSE-300-MPS3/ac6_linker_script.sct.src b/Alif/AppKit-E7_USB/Board/Corstone-300/RTE/Device/SSE-300-MPS3/ac6_linker_script.sct.src index 370d6b3..3576f33 100644 --- a/Alif/AppKit-E7_USB/Board/Corstone-300/RTE/Device/SSE-300-MPS3/ac6_linker_script.sct.src +++ b/Alif/AppKit-E7_USB/Board/Corstone-300/RTE/Device/SSE-300-MPS3/ac6_linker_script.sct.src @@ -34,7 +34,6 @@ LR_ROM0 __ROM0_BASE __ROM0_SIZE { ER_ROM0 __ROM0_BASE __ROM0_SIZE { *.o (RESET, +First) *(InRoot$$Sections) - *(+RO +XO) } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) @@ -42,6 +41,13 @@ LR_ROM0 __ROM0_BASE __ROM0_SIZE { *(Veneer$$CMSE) } #endif +} + +LR_ROM1 __ROM1_BASE __ROM1_SIZE { + + ER_ROM1 __ROM1_BASE __ROM1_SIZE { + *(+RO +XO) + } RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE) { *.o(.bss.noinit) @@ -67,11 +73,8 @@ LR_ROM0 __ROM0_BASE __ROM0_SIZE { #if __RAM1_SIZE > 0 RW_RAM1 __RAM1_BASE __RAM1_SIZE { - ; Ethos-U Cache Area - *.o (*ethos_cache_buf) - - ; NN Activation Tensor (activation buffer / tensor arena) - *.o (*activation_buf) + ; Ethos-U writable area + *.o (ethos_arena) .ANY (+RW +ZI) } @@ -90,19 +93,11 @@ LR_ROM0 __ROM0_BASE __ROM0_SIZE { #endif } -#if __ROM1_SIZE > 0 -LR_ROM1 __ROM1_BASE __ROM1_SIZE { - ER_ROM1 +0 __ROM1_SIZE { - .ANY (+RO +XO) - } -} -#endif - #if __ROM2_SIZE > 0 LR_ROM2 __ROM2_BASE __ROM2_SIZE { ER_ROM2 +0 __ROM2_SIZE { - ; NN Model Binary Representation - *.o (nn_model) + ; Ethos-U model, command stream and constants + *.o (ethos_model) .ANY (+RO +XO) } diff --git a/Alif/AppKit-E7_USB/Board/Corstone-300/RTE/Device/SSE-300-MPS3/clang_linker_script.ld.src b/Alif/AppKit-E7_USB/Board/Corstone-300/RTE/Device/SSE-300-MPS3/clang_linker_script.ld.src new file mode 100644 index 0000000..a64b505 --- /dev/null +++ b/Alif/AppKit-E7_USB/Board/Corstone-300/RTE/Device/SSE-300-MPS3/clang_linker_script.ld.src @@ -0,0 +1,406 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright © 2019 Keith Packard + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED + * OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* ---------------------------------------------------------------------------- + Stack seal size definition + *----------------------------------------------------------------------------*/ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define __STACKSEAL_SIZE ( 8 ) +#else +#define __STACKSEAL_SIZE ( 0 ) +#endif + +/* ---------------------------------------------------------------------------- + Memory definition + *----------------------------------------------------------------------------*/ +MEMORY +{ + ROM0 (rx!w) : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE +#if __ROM1_SIZE > 0 + ROM1 (rx!w) : ORIGIN = __ROM1_BASE, LENGTH = __ROM1_SIZE +#endif +#if __ROM2_SIZE > 0 + ROM2 (rx!w) : ORIGIN = __ROM2_BASE, LENGTH = __ROM2_SIZE +#endif +#if __ROM3_SIZE > 0 + ROM3 (rx!w) : ORIGIN = __ROM3_BASE, LENGTH = __ROM3_SIZE +#endif + + RAM0 (w!rx) : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE +#if __RAM1_SIZE > 0 + RAM1 (w!rx) : ORIGIN = __RAM1_BASE, LENGTH = __RAM1_SIZE +#endif +#if __RAM2_SIZE > 0 + RAM2 (w!rx) : ORIGIN = __RAM2_BASE, LENGTH = __RAM2_SIZE +#endif +#if __RAM3_SIZE > 0 + RAM3 (w!rx) : ORIGIN = __RAM3_BASE, LENGTH = __RAM3_SIZE +#endif +} + +ENTRY(Reset_Handler) + +PHDRS +{ + boot PT_LOAD; + text PT_LOAD; + ram PT_LOAD; + ram_init PT_LOAD; + tls PT_TLS; +#if __RAM1_SIZE > 0 + ethos_ram PT_LOAD; +#endif +#if __ROM2_SIZE > 0 + ethos_model PT_LOAD; +#endif +} + +SECTIONS +{ + .init : { + KEEP (*(.vectors)) + + /* Disable by default + * + * *.init.enter contains a vector table provided by picolibc, + * whereas CMSIS already provides a vector table via .vectors + */ + /* + KEEP (*(.text.init.enter)) + KEEP (*(.data.init.enter)) + */ + + KEEP (*(SORT_BY_NAME(.init) SORT_BY_NAME(.init.*))) + } >ROM0 AT>ROM0 :boot + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + .veneers : + { + . = ALIGN(32); + KEEP(*(.gnu.sgstubs)) + } > ROM0 AT>ROM0 :boot +#endif + + .text : { + + /* code */ + *(.text.unlikely .text.unlikely.*) + *(.text.startup .text.startup.*) + *(.text .text.* .opd .opd.*) + *(.gnu.linkonce.t.*) + KEEP (*(.fini .fini.*)) + __text_end = .; + + PROVIDE (__etext = __text_end); + PROVIDE (_etext = __text_end); + PROVIDE (etext = __text_end); + + /* read-only data */ + *(.rdata) + *(.rodata .rodata.*) + *(.gnu.linkonce.r.*) + + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + *(.data.rel.ro .data.rel.ro.*) + *(.got .got.*) + + /* Need to pre-align so that the symbols come after padding */ + . = ALIGN(8); + + /* lists of constructors and destructors */ + PROVIDE_HIDDEN ( __bothinit_array_start = . ); + PROVIDE_HIDDEN ( __preinit_array_start = . ); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN ( __preinit_array_end = . ); + + PROVIDE_HIDDEN ( __init_array_start = . ); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array .ctors)) + PROVIDE_HIDDEN ( __init_array_end = . ); + PROVIDE_HIDDEN ( __bothinit_array_end = . ); + + PROVIDE_HIDDEN ( __fini_array_start = . ); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array .dtors)) + PROVIDE_HIDDEN ( __fini_array_end = . ); + + } >ROM1 AT>ROM1 :text + + .toc : { + *(.toc .toc.*) + } >ROM1 AT>ROM1 :text + + /* additional sections when compiling with C++ exception support */ + + .except_ordered : { + *(.gcc_except_table *.gcc_except_table.*) + KEEP (*(.eh_frame .eh_frame.*)) + *(.ARM.extab* .gnu.linkonce.armextab.*) + } >ROM1 AT>ROM1 :text + + .except_unordered : { + . = ALIGN(8); + + PROVIDE(__exidx_start = .); + *(.ARM.exidx*) + PROVIDE(__exidx_end = .); + } >ROM1 AT>ROM1 :text + + + /* + * Data values which are preserved across reset + */ + .preserve (NOLOAD) : { + PROVIDE(__preserve_start__ = .); + KEEP(*(SORT_BY_NAME(.preserve.*))) + KEEP(*(.preserve)) + PROVIDE(__preserve_end__ = .); + } >RAM0 AT>RAM0 :ram + + .data : { + *(.data .data.*) + *(.gnu.linkonce.d.*) + + /* Need to pre-align so that the symbols come after padding */ + . = ALIGN(8); + + PROVIDE( __global_pointer$ = . + 0x800 ); + *(.sdata .sdata.* .sdata2.*) + *(.gnu.linkonce.s.*) + } >RAM0 AT>ROM1 :ram_init + PROVIDE(__data_start = ADDR(.data)); + PROVIDE(__data_source = LOADADDR(.data)); + + /* Thread local initialized data. This gets + * space allocated as it is expected to be placed + * in ram to be used as a template for TLS data blocks + * allocated at runtime. We're slightly abusing that + * by placing the data in flash where it will be copied + * into the allocate ram addresses by the existing + * data initialization code in crt0 + */ + .tdata : { + *(.tdata .tdata.* .gnu.linkonce.td.*) + PROVIDE(__data_end = .); + PROVIDE(__tdata_end = .); + } >RAM0 AT>ROM1 :tls :ram_init + PROVIDE( __tls_base = ADDR(.tdata)); + PROVIDE( __tdata_start = ADDR(.tdata)); + PROVIDE( __tdata_source = LOADADDR(.tdata) ); + PROVIDE( __tdata_source_end = LOADADDR(.tdata) + SIZEOF(.tdata) ); + PROVIDE( __data_source_end = __tdata_source_end ); + PROVIDE( __tdata_size = SIZEOF(.tdata) ); + PROVIDE( __tls_align = MAX(ALIGNOF(.tdata),ALIGNOF(.tbss)) ); + + PROVIDE( __edata = __data_end ); + PROVIDE( _edata = __data_end ); + PROVIDE( edata = __data_end ); + PROVIDE( __data_size = __data_end - __data_start ); + PROVIDE( __data_source_size = __data_source_end - __data_source ); + + .tbss (NOLOAD) : { + *(.tbss .tbss.* .gnu.linkonce.tb.*) + *(.tcommon) + PROVIDE( __tls_end = . ); + PROVIDE( __tbss_end = . ); + } >RAM0 AT>RAM0 :tls :ram + PROVIDE( __bss_start = ADDR(.tbss)); + PROVIDE( __tbss_start = ADDR(.tbss)); + PROVIDE( __tbss_offset = ADDR(.tbss) - ADDR(.tdata) ); + PROVIDE( __tbss_size = SIZEOF(.tbss) ); + PROVIDE( __tls_size = __tls_end - __tls_base ); + PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) ); + PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) ); + PROVIDE( __arm64_tls_tcb_offset = MAX(16, __tls_align) ); + + /* + * The linker special cases .tbss segments which are + * identified as segments which are not loaded and are + * thread_local. + * + * For these segments, the linker does not advance 'dot' + * across them. We actually need memory allocated for tbss, + * so we create a special segment here just to make room + */ + /* + .tbss_space (NOLOAD) : { + . = ADDR(.tbss); + . = . + SIZEOF(.tbss); + } >RAM0 AT>RAM0 :ram + */ + + .bss (NOLOAD) : { + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + + /* Align the end of this section, so next can start on aligned address */ + . = ALIGN(8); + __bss_end = .; + } >RAM0 AT>RAM0 :ram + PROVIDE( __non_tls_bss_start = ADDR(.bss) ); + PROVIDE( __bss_size = __bss_end - __bss_start ); + + /* This section contains data that is not initialized during load, + or during the application's initialization sequence. */ + .noinit (NOLOAD) : { + __noinit_start__ = .; + *(.noinit) + *(.noinit.*) + + /* Align the end of this section, so next (heap) can start on aligned address */ + . = ALIGN(8); + __noinit_end__ = .; + } >RAM0 AT>RAM0 :ram + + PROVIDE( __end = . ); + PROVIDE( _end = . ); + PROVIDE( end = . ); + + /* Make the rest of memory available for heap storage */ + PROVIDE (__heap_start = __end); +#ifdef __HEAP_SIZE + PROVIDE (__heap_end = __heap_start + __HEAP_SIZE); + PROVIDE (__heap_size = __HEAP_SIZE); +#else + PROVIDE (__heap_end = __stack - __STACK_SIZE); + PROVIDE (__heap_size = __heap_end - __heap_start); +#endif + .heap (NOLOAD) : { + . += __heap_size; + } >RAM0 :ram + + /* Define a stack region to make sure it fits in memory */ + PROVIDE(__stack = ORIGIN(RAM0) + LENGTH(RAM0) - __STACKSEAL_SIZE); + PROVIDE(__stack_limit = __stack - __STACK_SIZE); + .stack (__stack_limit) (NOLOAD) : { + . += __STACK_SIZE; + } >RAM0 :ram + +#if __STACKSEAL_SIZE > 0 + PROVIDE(__stack_seal = __stack); + .stackseal (__stack) (NOLOAD) : + { + . += __STACKSEAL_SIZE; + } >RAM0 :ram +#endif + + /* Ethos-U writable area */ +#if __RAM1_SIZE > 0 + .ethos_arena (NOLOAD) : ALIGN(32) { + *(ethos_arena) + } >RAM1 AT>RAM1 :ethos_ram +#endif + + /* Ethos-U model, command stream and constants */ +#if __ROM2_SIZE > 0 + .ethos_model : ALIGN(32) { + *(ethos_model) + } >ROM2 AT>ROM2 :ethos_model +#endif + + /* Throw away C++ exception handling information */ + + /* + + /DISCARD/ : { + *(.note .note.*) + *(.eh_frame .eh_frame.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + *(.ARM.exidx*) + } + + */ + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .gnu.build.attributes : { *(.gnu.build.attributes .gnu.build.attributes.*) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1. */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions. */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2. */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2. */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line .debug_line.* .debug_line_end) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions. */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + /* DWARF 3. */ + .debug_pubtypes 0 : { *(.debug_pubtypes) } + .debug_ranges 0 : { *(.debug_ranges) } + /* DWARF 5. */ + .debug_addr 0 : { *(.debug_addr) } + .debug_line_str 0 : { *(.debug_line_str) } + .debug_loclists 0 : { *(.debug_loclists) } + .debug_macro 0 : { *(.debug_macro) } + .debug_names 0 : { *(.debug_names) } + .debug_rnglists 0 : { *(.debug_rnglists) } + .debug_str_offsets 0 : { *(.debug_str_offsets) } + .debug_sup 0 : { *(.debug_sup) } + .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) } +} +/* + * Check that sections that are copied from flash to RAM have matching + * padding, so that a single memcpy() of __data_size copies the correct bytes. + */ +ASSERT( __data_size == __data_source_size, + "ERROR: .data/.tdata flash size does not match RAM size"); diff --git a/Alif/AppKit-E7_USB/Board/Corstone-300/RTE/Device/SSE-300-MPS3/gcc_linker_script.ld.src b/Alif/AppKit-E7_USB/Board/Corstone-300/RTE/Device/SSE-300-MPS3/gcc_linker_script.ld.src index 2e2ef6f..9f6f1a0 100644 --- a/Alif/AppKit-E7_USB/Board/Corstone-300/RTE/Device/SSE-300-MPS3/gcc_linker_script.ld.src +++ b/Alif/AppKit-E7_USB/Board/Corstone-300/RTE/Device/SSE-300-MPS3/gcc_linker_script.ld.src @@ -318,8 +318,7 @@ SECTIONS .cache (NOLOAD): { . = ALIGN(32); - *(*ethos_cache_buf) /* Ethos-U Cache Area */ - *(*activation_buf) /* NN Activation Tensor (activation buffer / tensor arena) */ + *(ethos_arena) /* Ethos-U writable area */ } > RAM1 /* Initialized buffers in fast access RAM */ @@ -331,7 +330,7 @@ SECTIONS .rom2 : { - *(*nn_model) /* NN Model Binary Representation */ + *(ethos_model) /* Ethos-U model, command stream and constants */ } > ROM2 .rom3 : diff --git a/Alif/AppKit-E7_USB/Board/Corstone-300/RTE/Device/SSE-300-MPS3/iar_linker_script.icf.src b/Alif/AppKit-E7_USB/Board/Corstone-300/RTE/Device/SSE-300-MPS3/iar_linker_script.icf.src index ea02d53..7d05a92 100644 --- a/Alif/AppKit-E7_USB/Board/Corstone-300/RTE/Device/SSE-300-MPS3/iar_linker_script.icf.src +++ b/Alif/AppKit-E7_USB/Board/Corstone-300/RTE/Device/SSE-300-MPS3/iar_linker_script.icf.src @@ -42,8 +42,6 @@ define memory mem with size = 4G; define region ROM3_region = []; #endif -define region ROM_region = ROM0_region | ROM1_region | ROM2_region | ROM3_region; - #if __RAM0_SIZE > 0 define region RAM0_region = mem:[from __RAM0_BASE to (__RAM0_BASE+__RAM0_SIZE-1)]; #else @@ -68,8 +66,6 @@ define region ROM_region = ROM0_region | ROM1_region | ROM2_region | ROM3_regio define region RAM3_region = []; #endif -define region RAM_region = RAM0_region | RAM1_region | RAM2_region | RAM3_region; - do not initialize { section .noinit }; initialize by copy { readwrite }; if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) @@ -80,15 +76,37 @@ if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) place at address mem:__ROM0_BASE { readonly section .intvec }; -if (!isempty(ROM_region)) +if (!isempty(ROM1_region)) { - place in ROM_region { readonly }; + place in ROM1_region { readonly }; } -if (!isempty(RAM_region)) +if (!isempty(RAM0_region)) { define block CSTACK with alignment = 8, size = __STACK_SIZE { }; define block PROC_STACK with alignment = 8, size = 0 { }; define block HEAP with alignment = 8, size = __HEAP_SIZE { }; - place in RAM_region { readwrite, block CSTACK, block PROC_STACK, block HEAP }; + place in RAM0_region { readwrite, block PROC_STACK, block HEAP }; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + /* Reserve the stack seal immediately above the stack. */ + define block STACKSEAL with alignment = 8, size = 8 { }; + define block CSTACK_WITH_SEAL with fixed order { block CSTACK, block STACKSEAL }; + place at end of RAM0_region { block CSTACK_WITH_SEAL }; +#else + place at end of RAM0_region { block CSTACK }; +#endif } + +/* Ethos-U writable area */ +#if __RAM1_SIZE > 0 + do not initialize { section ethos_arena }; + define block ETHOS_ARENA with alignment = 32 + { section ethos_arena }; + place in RAM1_region { block ETHOS_ARENA }; +#endif + +/* Ethos-U model, command stream and constants */ +#if __ROM2_SIZE > 0 + define block ETHOS_MODEL with alignment = 32 { readonly section ethos_model }; + place in ROM2_region { block ETHOS_MODEL }; +#endif diff --git a/Alif/AppKit-E7_USB/Board/Corstone-300/regions_SSE-300.h b/Alif/AppKit-E7_USB/Board/Corstone-300/RTE/Device/SSE-300-MPS3/regions_SSE-300.h similarity index 100% rename from Alif/AppKit-E7_USB/Board/Corstone-300/regions_SSE-300.h rename to Alif/AppKit-E7_USB/Board/Corstone-300/RTE/Device/SSE-300-MPS3/regions_SSE-300.h diff --git a/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/sse300_memmap_ns.h b/Alif/AppKit-E7_USB/Board/Corstone-300/RTE/Device/SSE-300-MPS3/sse300_memmap_ns.h similarity index 97% rename from ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/sse300_memmap_ns.h rename to Alif/AppKit-E7_USB/Board/Corstone-300/RTE/Device/SSE-300-MPS3/sse300_memmap_ns.h index d15a465..811a1c6 100644 --- a/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/sse300_memmap_ns.h +++ b/Alif/AppKit-E7_USB/Board/Corstone-300/RTE/Device/SSE-300-MPS3/sse300_memmap_ns.h @@ -57,10 +57,10 @@ #define SRAM_VM1_NS_LIMIT (SRAM_VM1_NS_BASE + SRAM_VM1_NS_SIZE - 1) /*---------------------------------------------------------------------------*/ -/* Secure QSPI Flash Regions */ +/* Non-Secure QSPI Flash Regions */ /*---------------------------------------------------------------------------*/ -/* QSPI Flash - Secure */ +/* QSPI Flash - Non-Secure */ #define QSPI_FLASH_NS_BASE 0x28000000 #define QSPI_FLASH_NS_SIZE 0x00800000 /* 8MB */ #define QSPI_FLASH_NS_LIMIT (QSPI_FLASH_NS_BASE + QSPI_FLASH_NS_SIZE - 1) diff --git a/Alif/AppKit-E7_USB/Board/Corstone-300/sse300_memmap_s.h b/Alif/AppKit-E7_USB/Board/Corstone-300/RTE/Device/SSE-300-MPS3/sse300_memmap_s.h similarity index 100% rename from Alif/AppKit-E7_USB/Board/Corstone-300/sse300_memmap_s.h rename to Alif/AppKit-E7_USB/Board/Corstone-300/RTE/Device/SSE-300-MPS3/sse300_memmap_s.h diff --git a/Alif/AppKit-E7_USB/Board/Corstone-300/ethos_setup.c b/Alif/AppKit-E7_USB/Board/Corstone-300/ethos_setup.c index f154c77..d4033b3 100644 --- a/Alif/AppKit-E7_USB/Board/Corstone-300/ethos_setup.c +++ b/Alif/AppKit-E7_USB/Board/Corstone-300/ethos_setup.c @@ -1,5 +1,5 @@ -/*--------------------------------------------------------------------------- - * Copyright (c) 2025 Arm Limited (or its affiliates). All rights reserved. +/* + * Copyright 2025-2026 Arm Limited and/or its affiliates. * * SPDX-License-Identifier: Apache-2.0 * @@ -14,7 +14,7 @@ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. - *---------------------------------------------------------------------------*/ + */ #include @@ -26,18 +26,18 @@ #if defined(ETHOSU65) || defined(ETHOSU85) /* Define Ethos-U NPU cache buffer size */ -#ifndef ETHOS_CACHE_BUF_SIZE -#define ETHOS_CACHE_BUF_SIZE 393216 +#ifndef ETHOS_CACHE_SIZE +#define ETHOS_CACHE_SIZE 0 #endif /* Define Ethos-U cache buffer alignment */ -#ifndef ETHOS_CACHE_BUF_ALIGNMENT -#define ETHOS_CACHE_BUF_ALIGNMENT 32 +#ifndef ETHOS_CACHE_ALIGNMENT +#define ETHOS_CACHE_ALIGNMENT 32 #endif /* Define Ethos-U NPU cache buffer attributes */ -#ifndef ETHOS_CACHE_BUF_ATTRIBUTES -#define ETHOS_CACHE_BUF_ATTRIBUTES __attribute__((section("ethos_cache_buf"), aligned(ETHOS_CACHE_BUF_ALIGNMENT))) +#ifndef ETHOS_CACHE_ATTRIBUTES +#define ETHOS_CACHE_ATTRIBUTES __attribute__((section("ethos_cache"), aligned(ETHOS_CACHE_ALIGNMENT))) #endif #endif @@ -54,8 +54,9 @@ /* Ethos NPU driver instance. */ static struct ethosu_driver EthosDriver; -#if defined(ETHOSU65) || defined(ETHOSU85) -static uint8_t ethos_cache[ETHOS_CACHE_BUF_SIZE] ETHOS_CACHE_BUF_ATTRIBUTES; +#if (defined(ETHOSU65) || defined(ETHOSU85)) && (ETHOS_CACHE_SIZE > 0) +/* Ethos-U NPU cache buffer */ +static uint8_t ethos_cache_buf[ETHOS_CACHE_SIZE] ETHOS_CACHE_ATTRIBUTES; #endif /* @@ -76,9 +77,9 @@ void ethos_setup (void) { /* Initialize Ethos-U NPU driver. */ rval = ethosu_init(&EthosDriver, /* Ethos-U device driver */ ethos_base_addr, /* Ethos-U base address */ - #if defined(ETHOSU65) || defined(ETHOSU85) - ethos_cache, /* Cache memory pointer */ - sizeof(ethos_cache), /* Cache memory size */ + #if (defined(ETHOSU65) || defined(ETHOSU85)) && (ETHOS_CACHE_SIZE > 0) + ethos_cache_buf, /* Cache memory pointer */ + sizeof(ethos_cache_buf), /* Cache memory size */ #else 0, /* Cache memory pointer */ 0, /* Cache memory size */ diff --git a/Alif/AppKit-E7_USB/Board/Corstone-300/ethosu_dcache.c b/Alif/AppKit-E7_USB/Board/Corstone-300/ethosu_dcache.c new file mode 100644 index 0000000..015a9d1 --- /dev/null +++ b/Alif/AppKit-E7_USB/Board/Corstone-300/ethosu_dcache.c @@ -0,0 +1,78 @@ +/* + * Copyright 2026 Arm Limited and/or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include + +#include "ethosu_driver.h" + +/** + \brief Cleans data-cache contents associated with buffers accessed by the NPU. + + Ensures that CPU writes to cacheable buffers are committed to memory before + the NPU starts accessing them. Non-cacheable buffers require no cache clean, + but the function ensures that all preceding memory accesses have completed + before it returns. + + \param[in] base_addr Array of buffer base addresses. + \param[in] base_addr_size Array containing the size, in bytes, of each buffer. + \param[in] num_base_addr Number of entries in the address and size arrays. +*/ +void ethosu_flush_dcache(const uint64_t *base_addr, const size_t *base_addr_size, int num_base_addr) { + + for (int i = 0; i < num_base_addr; i++) { + if ((base_addr[i] & 0x1F) != 0) { + /* Base address must be cache line aligned (32 bytes) */ + // ... + return; + } + + /* Flush data-cache for current buffer */ + // ... + // 32-bit system must cast base_addr to uint32_t* to avoid sign expansion + // CleanDCache((uint32_t *)(uint32_t)base_addr[i], base_addr_size[i]); + } +} + +/** + \brief Invalidates data-cache contents associated with buffers accessed by the NPU. + + Ensures that subsequent CPU reads observe data written by the NPU. Dirty + cache lines may be cleaned before invalidation to preserve pending CPU + writes. For non-cacheable buffers, no cache invalidation is required, + but the function ensures that all preceding memory accesses have completed + before it returns. + + \param[in] base_addr Array of buffer base addresses. + \param[in] base_addr_size Array containing the size, in bytes, of each buffer. + \param[in] num_base_addr Number of entries in the address and size arrays. +*/ +void ethosu_invalidate_dcache(const uint64_t *base_addr, const size_t *base_addr_size, int num_base_addr) { + + for (int i = 0; i < num_base_addr; i++) { + if ((base_addr[i] & 0x1F) != 0) { + /* Base address must be cache line aligned (32 bytes) */ + // ... + return; + } + + /* Invalidate data-cache for current buffer */ + // ... + // 32-bit system must cast base_addr to uint32_t* to avoid sign expansion + // InvalidateDCache((uint32_t *)(uint32_t)base_addr[i], base_addr_size[i]); + } +} diff --git a/Alif/AppKit-E7_USB/Board/Corstone-300/ethosu_os_rtos2.c b/Alif/AppKit-E7_USB/Board/Corstone-300/ethosu_os_rtos2.c new file mode 100644 index 0000000..fdab39b --- /dev/null +++ b/Alif/AppKit-E7_USB/Board/Corstone-300/ethosu_os_rtos2.c @@ -0,0 +1,141 @@ +/* + * Copyright 2026 Arm Limited and/or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ethosu_driver.h" +#include "cmsis_os2.h" + +/* Maximum number of Ethos-U instances. */ +/* Used as maximum semaphore count in ethosu_semaphore_create. */ +#ifndef ETHOSU_MAX_INSTANCES +#define ETHOSU_MAX_INSTANCES 2 +#endif + +/** + \brief Create a mutex object. + \return Pointer to a mutex object. +*/ +void *ethosu_mutex_create(void) { + osMutexId_t mutex_id = osMutexNew(NULL); + return (void *) mutex_id; +} + +/** + \brief Destroy a mutex object. + \param[in] mutex mutex object. +*/ +void ethosu_mutex_destroy(void *mutex) { + osMutexId_t mutex_id = (osMutexId_t) mutex; + osMutexDelete(mutex_id); +} + +/** + \brief Lock a mutex. + \param[in] mutex mutex object. + \return 0 on success, else negative error codes +*/ +int ethosu_mutex_lock(void *mutex) { + osMutexId_t mutex_id = (osMutexId_t) mutex; + osStatus_t status; + int rval; + + status = osMutexAcquire(mutex_id, osWaitForever); + if (status == osOK) { + rval = 0; + } else { + rval = -1; + } + return rval; +} + +/** + \brief Unlock a mutex. + \param[in] mutex mutex object. + \return 0 on success, else negative error codes +*/ +int ethosu_mutex_unlock(void *mutex) { + osMutexId_t mutex_id = (osMutexId_t) mutex; + osStatus_t status; + int rval; + + status = osMutexRelease(mutex_id); + if (status == osOK) { + rval = 0; + } else { + rval = -1; + } + return rval; +} + +/** + \brief Create a semaphore object. + \return Pointer to a semaphore object. +*/ +void *ethosu_semaphore_create(void) { + osSemaphoreId_t sem_id; + + sem_id = osSemaphoreNew(ETHOSU_MAX_INSTANCES, 0U, NULL); + return (void *) sem_id; +} + +/** + \brief Destroy a semaphore object. + \param[in] sem semaphore object. +*/ +void ethosu_semaphore_destroy(void *sem) { + osSemaphoreId_t sem_id = (osSemaphoreId_t) sem; + osSemaphoreDelete(sem_id); +} + +/** + \brief Take a semaphore object with timeout. + \param[in] sem semaphore object. + \param[in] timeout timeout value in ticks. + \return 0 on success, else negative error codes +*/ +int ethosu_semaphore_take(void *sem, uint64_t timeout) { + osSemaphoreId_t sem_id = (osSemaphoreId_t) sem; + osStatus_t status; + int rval; + + status = osSemaphoreAcquire(sem_id, timeout); + if (status == osOK) { + rval = 0; + } else { + rval = -1; + } + return rval; +} + +/** + \brief Give a semaphore object. + \param[in] sem semaphore object. + \return 0 on success, else negative error codes +*/ +int ethosu_semaphore_give(void *sem) { + osSemaphoreId_t sem_id = (osSemaphoreId_t) sem; + osStatus_t status; + int rval; + + status = osSemaphoreRelease(sem_id); + if (status == osOK) { + rval = 0; + } else { + rval = -1; + } + return rval; +} diff --git a/Alif/AppKit-E7_USB/Board/Corstone-300/fvp_config.txt b/Alif/AppKit-E7_USB/Board/Corstone-300/fvp_config.txt index e818f72..c21ae24 100644 --- a/Alif/AppKit-E7_USB/Board/Corstone-300/fvp_config.txt +++ b/Alif/AppKit-E7_USB/Board/Corstone-300/fvp_config.txt @@ -1,7 +1,6 @@ # Parameters: # instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] #------------------------------------------------------------------------------ -ethosu.num_macs=256 # (int , init-time) default = '0x100' : Number of 8x8 MACs performed per cycle (32, 64, 128, or 256). mps3_board.telnetterminal0.quiet=1 # (bool , init-time) default = '0' : Avoid output on stdout/stderr mps3_board.telnetterminal0.start_telnet=0 # (bool , init-time) default = '1' : Start telnet if nothing connected mps3_board.telnetterminal1.quiet=1 # (bool , init-time) default = '0' : Avoid output on stdout/stderr diff --git a/Alif/AppKit-E7_USB/Board/Corstone-300/fvp_config_u55.txt b/Alif/AppKit-E7_USB/Board/Corstone-300/fvp_config_u55.txt new file mode 100644 index 0000000..ab75990 --- /dev/null +++ b/Alif/AppKit-E7_USB/Board/Corstone-300/fvp_config_u55.txt @@ -0,0 +1,18 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +ethosu.num_macs=256 # (int , init-time) default = '0x100' : Number of 8x8 MACs performed per cycle (32, 64, 128, or 256). +mps3_board.telnetterminal0.quiet=1 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +mps3_board.telnetterminal0.start_telnet=0 # (bool , init-time) default = '1' : Start telnet if nothing connected +mps3_board.telnetterminal1.quiet=1 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +mps3_board.telnetterminal1.start_telnet=0 # (bool , init-time) default = '1' : Start telnet if nothing connected +mps3_board.telnetterminal2.quiet=1 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +mps3_board.telnetterminal2.start_telnet=0 # (bool , init-time) default = '1' : Start telnet if nothing connected +mps3_board.telnetterminal5.quiet=1 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +mps3_board.telnetterminal5.start_telnet=0 # (bool , init-time) default = '1' : Start telnet if nothing connected +mps3_board.uart0.out_file=- # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) +mps3_board.uart0.shutdown_on_eot=1 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) +mps3_board.visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation +#------------------------------------------------------------------------------ + +mps3_board.v_path=./Board/Corstone-300/vsi/python/ # Python VSI and VIO scripts diff --git a/Alif/AppKit-E7_USB/Board/Corstone-300/fvp_config_u65.txt b/Alif/AppKit-E7_USB/Board/Corstone-300/fvp_config_u65.txt new file mode 100644 index 0000000..ab75990 --- /dev/null +++ b/Alif/AppKit-E7_USB/Board/Corstone-300/fvp_config_u65.txt @@ -0,0 +1,18 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +ethosu.num_macs=256 # (int , init-time) default = '0x100' : Number of 8x8 MACs performed per cycle (32, 64, 128, or 256). +mps3_board.telnetterminal0.quiet=1 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +mps3_board.telnetterminal0.start_telnet=0 # (bool , init-time) default = '1' : Start telnet if nothing connected +mps3_board.telnetterminal1.quiet=1 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +mps3_board.telnetterminal1.start_telnet=0 # (bool , init-time) default = '1' : Start telnet if nothing connected +mps3_board.telnetterminal2.quiet=1 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +mps3_board.telnetterminal2.start_telnet=0 # (bool , init-time) default = '1' : Start telnet if nothing connected +mps3_board.telnetterminal5.quiet=1 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +mps3_board.telnetterminal5.start_telnet=0 # (bool , init-time) default = '1' : Start telnet if nothing connected +mps3_board.uart0.out_file=- # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) +mps3_board.uart0.shutdown_on_eot=1 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) +mps3_board.visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation +#------------------------------------------------------------------------------ + +mps3_board.v_path=./Board/Corstone-300/vsi/python/ # Python VSI and VIO scripts diff --git a/Alif/AppKit-E7_USB/Board/Corstone-300/main.c b/Alif/AppKit-E7_USB/Board/Corstone-300/main.c index 69b3485..009aec0 100644 --- a/Alif/AppKit-E7_USB/Board/Corstone-300/main.c +++ b/Alif/AppKit-E7_USB/Board/Corstone-300/main.c @@ -1,5 +1,5 @@ -/*--------------------------------------------------------------------------- - * Copyright (c) 2024 Arm Limited (or its affiliates). All rights reserved. +/* + * Copyright 2024-2026 Arm Limited and/or its affiliates. * * SPDX-License-Identifier: Apache-2.0 * @@ -14,7 +14,7 @@ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. - *---------------------------------------------------------------------------*/ + */ #include "RTE_Components.h" #include CMSIS_device_header diff --git a/Alif/AppKit-E7_USB/Board/Corstone-300/main.h b/Alif/AppKit-E7_USB/Board/Corstone-300/main.h index 6e2048e..2b576ad 100644 --- a/Alif/AppKit-E7_USB/Board/Corstone-300/main.h +++ b/Alif/AppKit-E7_USB/Board/Corstone-300/main.h @@ -1,6 +1,6 @@ -/*--------------------------------------------------------------------------- - * Copyright (c) 2020-2025 Arm Limited (or its affiliates). - * All rights reserved. +/* + * Copyright 2020-2026 Arm Limited and/or its affiliates. + * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may @@ -14,7 +14,7 @@ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. - *---------------------------------------------------------------------------*/ + */ #ifndef MAIN_H__ #define MAIN_H__ diff --git a/Alif/AppKit-E7_USB/Board/Corstone-300/retarget_stdio.c b/Alif/AppKit-E7_USB/Board/Corstone-300/retarget_stdio.c deleted file mode 100644 index f553eed..0000000 --- a/Alif/AppKit-E7_USB/Board/Corstone-300/retarget_stdio.c +++ /dev/null @@ -1,161 +0,0 @@ -/*--------------------------------------------------------------------------- - * Copyright (c) 2025 Arm Limited (or its affiliates). - * All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * Name: retarget_stdio.c - * Purpose: Retarget stdio to CMSIS UART - * - *---------------------------------------------------------------------------*/ - -#ifdef CMSIS_target_header -#include CMSIS_target_header -#else -#include "Driver_USART.h" -#endif - -#ifndef RETARGET_STDIO_UART -#error "RETARGET_STDIO_UART not defined!" -#endif - -/* Compile-time configuration */ -#ifndef UART_BAUDRATE -#define UART_BAUDRATE 115200 -#endif - -/* References to the external retarget functions */ -extern int stdio_init (void); -extern int stderr_putchar (int ch); -extern int stdout_putchar (int ch); -extern int stdin_getchar (void); - -/* Reference to the underlying USART driver */ -#ifndef CMSIS_target_header -extern ARM_DRIVER_USART ARM_Driver_USART_(RETARGET_STDIO_UART); -#endif -#define ptrUSART (&ARM_Driver_USART_(RETARGET_STDIO_UART)) - -/** - Initialize stdio - - \return 0 on success, or -1 on error. -*/ -int stdio_init (void) { - - if (ptrUSART->Initialize(NULL) != ARM_DRIVER_OK) { - return -1; - } - - if (ptrUSART->PowerControl(ARM_POWER_FULL) != ARM_DRIVER_OK) { - return -1; - } - - if (ptrUSART->Control(ARM_USART_MODE_ASYNCHRONOUS | - ARM_USART_DATA_BITS_8 | - ARM_USART_PARITY_NONE | - ARM_USART_STOP_BITS_1 | - ARM_USART_FLOW_CONTROL_NONE, - UART_BAUDRATE) != ARM_DRIVER_OK) { - return -1; - } - - if (ptrUSART->Control(ARM_USART_CONTROL_RX, 1U) != ARM_DRIVER_OK) { - return -1; - } - - if (ptrUSART->Control(ARM_USART_CONTROL_TX, 1U) != ARM_DRIVER_OK) { - return -1; - } - - return 0; -} - -/** - Put a character to the stderr - - \param[in] ch Character to output - \return The character written, or -1 on write error. -*/ -int stderr_putchar (int ch) { - uint8_t buf[1]; - - if (ch == '\n') { - buf[0] = (uint8_t)'\r'; - - if (ptrUSART->Send(buf, 1U) != ARM_DRIVER_OK) { - return -1; - } - - while (ptrUSART->GetStatus().tx_busy != 0U); - } - - buf[0] = (uint8_t)ch; - - if (ptrUSART->Send(buf, 1U) != ARM_DRIVER_OK) { - return -1; - } - - while (ptrUSART->GetStatus().tx_busy != 0U); - - return ch; -} - -/** - Put a character to the stdout - - \param[in] ch Character to output - \return The character written, or -1 on write error. -*/ -int stdout_putchar (int ch) { - uint8_t buf[1]; - - if (ch == '\n') { - buf[0] = (uint8_t)'\r'; - - if (ptrUSART->Send(buf, 1U) != ARM_DRIVER_OK) { - return -1; - } - - while (ptrUSART->GetStatus().tx_busy != 0U); - } - - buf[0] = (uint8_t)ch; - - if (ptrUSART->Send(buf, 1U) != ARM_DRIVER_OK) { - return -1; - } - - while (ptrUSART->GetStatus().tx_busy != 0U); - - return ch; -} - -/** - Get a character from the stdio - - \return The next character from the input, or -1 on read error. -*/ -int stdin_getchar (void) { - uint8_t buf[1]; - - if (ptrUSART->Receive(buf, 1U) != ARM_DRIVER_OK) { - return -1; - } - - while (ptrUSART->GetStatus().rx_busy != 0U); - - return (int)buf[0]; -} \ No newline at end of file diff --git a/Alif/AppKit-E7_USB/SDS.csolution.yml b/Alif/AppKit-E7_USB/SDS.csolution.yml index 7e40b1a..35a7891 100644 --- a/Alif/AppKit-E7_USB/SDS.csolution.yml +++ b/Alif/AppKit-E7_USB/SDS.csolution.yml @@ -52,7 +52,7 @@ solution: debugger: name: Arm-FVP model: FVP_Corstone_SSE-300_Ethos-U55 - config-file: Board/Corstone-300/fvp_config.txt + config-file: Board/Corstone-300/fvp_config_u55.txt # List of different build configurations. build-types: diff --git a/Alif/AppKit-E7_USB/algorithm/config_app.h b/Alif/AppKit-E7_USB/algorithm/config_app.h index 03f5f9f..b184603 100644 --- a/Alif/AppKit-E7_USB/algorithm/config_app.h +++ b/Alif/AppKit-E7_USB/algorithm/config_app.h @@ -33,9 +33,9 @@ // Activation Buffer Section Name // Define the name of the activation buffer section -// Default: ".bss.activation_buf" +// Default: "ethos_arena" #ifndef ACTIVATION_BUF_SECTION -#define ACTIVATION_BUF_SECTION ".bss.activation_buf" +#define ACTIVATION_BUF_SECTION "ethos_arena" #endif // Activation Buffer Alignment @@ -47,9 +47,9 @@ // NN Model Buffer Section Name // Define the name of the NN model buffer section -// Default: "nn_model" +// Default: "ethos_model" #ifndef NN_MODEL_BUF_SECTION -#define NN_MODEL_BUF_SECTION "nn_model" +#define NN_MODEL_BUF_SECTION "ethos_model" #endif // NN Model Buffer Alignment // Define the NN model buffer alignment in bytes diff --git a/Alif/DevKit-E8_ETH/Board/Corstone-320/Board-U85.clayer.yml b/Alif/DevKit-E8_ETH/Board/Corstone-320/Board-U85.clayer.yml index a90ba8e..9d76a09 100644 --- a/Alif/DevKit-E8_ETH/Board/Corstone-320/Board-U85.clayer.yml +++ b/Alif/DevKit-E8_ETH/Board/Corstone-320/Board-U85.clayer.yml @@ -1,6 +1,6 @@ layer: type: Board - description: Board setup for AI/ML with Ethos U85 + description: Base configuration of SSE-320 FVP with Ethos U85 for-board: ARM::SSE-320 for-device: ARM::SSE-320-FVP @@ -12,19 +12,19 @@ layer: - STDIN - STDOUT - STDERR - - Heap: 786432 + - Heap: 98304 + consumes: + - CMSIS-RTOS2 define: - CMSIS_target_header: \"Corstone-320.h\" - - ETHOSU85 - - ARM_MODEL_USE_PMU_COUNTERS - - UART0_BASE_S_TMP + - ETHOS_CACHE_SIZE: 393216 packs: - pack: ARM::CMSIS - - pack: ARM::CMSIS-Compiler@^2.1.0 - - pack: ARM::ethos-u-core-driver@^1.25.2 - - pack: ARM::SSE_320_BSP@1.1.0 + - pack: ARM::CMSIS-Compiler@^2.3.0 + - pack: ARM::CMSIS-Ethos-U@^1.0.0 + - pack: ARM::SSE_320_BSP@^2.0.0 components: - component: CMSIS:CORE @@ -33,9 +33,9 @@ layer: - component: CMSIS Driver:VIO - component: CMSIS-Compiler:CORE - - component: CMSIS-Compiler:STDERR:Custom - - component: CMSIS-Compiler:STDIN:Custom - - component: CMSIS-Compiler:STDOUT:Custom + - component: CMSIS-Compiler:STDERR:UART&CMSIS + - component: CMSIS-Compiler:STDIN:UART&CMSIS + - component: CMSIS-Compiler:STDOUT:UART&CMSIS - component: Device:Definition - component: Device:Startup&C Startup @@ -46,14 +46,19 @@ layer: - component: Device:Native Driver:UART - component: Machine Learning:NPU Support:Ethos-U Driver&Generic U85 + define: + - ETHOSU_MACS: 256 + # Dedicated SRAM: normal scratch uses AXI_EXT; fast scratch uses AXI_SRAM + - NPU_REGIONCFG_1: 3 groups: - group: Board files: - - file: ./main.c - - file: ./main.h - - file: ./ethos_setup.c - - file: ./retarget_stdio.c + - file: main.c + - file: main.h + - file: ethos_setup.c + - file: ethosu_os_rtos2.c + - file: ethosu_dcache.c linker: - - regions: ./regions_SSE-320.h + - regions: RTE/Device/SSE-320-FVP/regions_SSE-320.h diff --git a/Alif/DevKit-E8_ETH/Board/Corstone-320/Board.clayer.yml b/Alif/DevKit-E8_ETH/Board/Corstone-320/Board.clayer.yml index 64c1de5..1d5de57 100644 --- a/Alif/DevKit-E8_ETH/Board/Corstone-320/Board.clayer.yml +++ b/Alif/DevKit-E8_ETH/Board/Corstone-320/Board.clayer.yml @@ -1,6 +1,6 @@ layer: type: Board - description: Board setup for AI/ML + description: Base configuration of SSE-320 FVP for-board: ARM::SSE-320 for-device: ARM::SSE-320-FVP @@ -12,17 +12,15 @@ layer: - STDIN - STDOUT - STDERR - - Heap: 786432 + - Heap: 98304 define: - CMSIS_target_header: \"Corstone-320.h\" - - ARM_MODEL_USE_PMU_COUNTERS - - UART0_BASE_S_TMP packs: - pack: ARM::CMSIS - - pack: ARM::CMSIS-Compiler@^2.1.0 - - pack: ARM::SSE_320_BSP@1.1.0 + - pack: ARM::CMSIS-Compiler@^2.3.0 + - pack: ARM::SSE_320_BSP@^2.0.0 components: - component: CMSIS:CORE @@ -31,9 +29,9 @@ layer: - component: CMSIS Driver:VIO - component: CMSIS-Compiler:CORE - - component: CMSIS-Compiler:STDERR:Custom - - component: CMSIS-Compiler:STDIN:Custom - - component: CMSIS-Compiler:STDOUT:Custom + - component: CMSIS-Compiler:STDERR:UART&CMSIS + - component: CMSIS-Compiler:STDIN:UART&CMSIS + - component: CMSIS-Compiler:STDOUT:UART&CMSIS - component: Device:Definition - component: Device:Startup&C Startup @@ -46,9 +44,8 @@ layer: groups: - group: Board files: - - file: ./main.c - - file: ./main.h - - file: ./retarget_stdio.c + - file: main.c + - file: main.h linker: - - regions: ./regions_SSE-320.h + - regions: RTE/Device/SSE-320-FVP/regions_SSE-320.h diff --git a/Alif/DevKit-E8_ETH/Board/Corstone-320/Corstone-320.h b/Alif/DevKit-E8_ETH/Board/Corstone-320/Corstone-320.h index c066a58..62630a0 100644 --- a/Alif/DevKit-E8_ETH/Board/Corstone-320/Corstone-320.h +++ b/Alif/DevKit-E8_ETH/Board/Corstone-320/Corstone-320.h @@ -1,6 +1,6 @@ -/*--------------------------------------------------------------------------- - * Copyright (c) 2025 Arm Limited (or its affiliates). - * All rights reserved. +/* + * Copyright 2026 Arm Limited and/or its affiliates. + * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may @@ -14,7 +14,7 @@ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. - *---------------------------------------------------------------------------*/ + */ #ifndef CORSTONE_320_H_ #define CORSTONE_320_H_ diff --git a/Alif/DevKit-E8_ETH/Board/Corstone-320/README.md b/Alif/DevKit-E8_ETH/Board/Corstone-320/README.md index 86063f7..4882fdd 100644 --- a/Alif/DevKit-E8_ETH/Board/Corstone-320/README.md +++ b/Alif/DevKit-E8_ETH/Board/Corstone-320/README.md @@ -1,20 +1,29 @@ # Board: Arm SSE-320 -## Board Layer for Corstone-320 FVP +## Board Layers for Corstone-320 FVP -This layer works for: +These layers work for: ```yml board: ARM::SSE-320 device: ARM::SSE-320-FVP ``` +Select one layer matching the application's NPU requirements: + +| Layer file | Use in Application +|:---------------------|:------------------------ +| Board.clayer.yml | Without Ethos-U support +| Board-U85.clayer.yml | With Ethos-U85 support + +Use the corresponding FVP configuration file listed below. + ### System Configuration | System Component | Setting |:------------------------|:---------------------------------- -| Heap | 768 kB (configured in linker file) -| Stack (MSP) | 32 kB (configured in linker file) +| Heap | 96 kB (configured in regions header) +| Stack (MSP) | 4 kB (configured in regions header) ### STDIO mapping @@ -41,4 +50,4 @@ interface for SDS data files using a [Virtual Streaming Interface](https://arm-s | File | Description |:-------------------|:------------- -| fvp_config.txt | Corstone-320 FVP without Ethos-U or with Ethos-U85 +| fvp_config.txt | Corstone-320 FVP without or with an Ethos-U85-256 diff --git a/Alif/DevKit-E8_ETH/Board/Corstone-320/RTE/CMSIS-Compiler/stderr_cmsis_uart_config.h b/Alif/DevKit-E8_ETH/Board/Corstone-320/RTE/CMSIS-Compiler/stderr_cmsis_uart_config.h new file mode 100644 index 0000000..d6a30a3 --- /dev/null +++ b/Alif/DevKit-E8_ETH/Board/Corstone-320/RTE/CMSIS-Compiler/stderr_cmsis_uart_config.h @@ -0,0 +1,59 @@ +/*--------------------------------------------------------------------------- + * Copyright (c) 2026 Arm Limited (or its affiliates). + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * -------------------------------------------------------------------------- + * + * Purpose: Configure STDERR to CMSIS-Driver USART retarget implementation + * Revision: V1.0.0 + * + * --------------------------------------------------------------------------*/ + +#ifndef STDERR_CMSIS_UART_CONFIG_H_ +#define STDERR_CMSIS_UART_CONFIG_H_ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// UART STDERR Buffer Size +// UART STDERR buffer is used to store STDERR data before sending it via UART +// Default: 0 (unbuffered) +#ifndef STDERR_UART_BUFFER_SIZE +#define STDERR_UART_BUFFER_SIZE 0 +#endif + +// UART STDERR Buffer Section Name +// Specify the memory section name for UART STDERR buffer +// Default: .stderr_uart_buf +#ifndef STDERR_UART_BUFFER_SECTION +#define STDERR_UART_BUFFER_SECTION ".stderr_uart_buf" +#endif + +// UART STDERR Buffer Alignment +// Define the STDERR buffer alignment in bytes +// Default: 32 +#ifndef STDERR_UART_BUFFER_ALIGNMENT +#define STDERR_UART_BUFFER_ALIGNMENT 32 +#endif + +// Convert LF to CRLF +// If enabled, LF characters are preceded by CR characters on output +// Default: 0 +#ifndef STDERR_CR_LF +#define STDERR_CR_LF 1 +#endif + +#endif /* STDERR_CMSIS_UART_CONFIG_H_ */ diff --git a/Alif/DevKit-E8_ETH/Board/Corstone-320/RTE/CMSIS-Compiler/stderr_cmsis_uart_config.h.base@1.0.0 b/Alif/DevKit-E8_ETH/Board/Corstone-320/RTE/CMSIS-Compiler/stderr_cmsis_uart_config.h.base@1.0.0 new file mode 100644 index 0000000..192648e --- /dev/null +++ b/Alif/DevKit-E8_ETH/Board/Corstone-320/RTE/CMSIS-Compiler/stderr_cmsis_uart_config.h.base@1.0.0 @@ -0,0 +1,59 @@ +/*--------------------------------------------------------------------------- + * Copyright (c) 2026 Arm Limited (or its affiliates). + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * -------------------------------------------------------------------------- + * + * Purpose: Configure STDERR to CMSIS-Driver USART retarget implementation + * Revision: V1.0.0 + * + * --------------------------------------------------------------------------*/ + +#ifndef STDERR_CMSIS_UART_CONFIG_H_ +#define STDERR_CMSIS_UART_CONFIG_H_ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// UART STDERR Buffer Size +// UART STDERR buffer is used to store STDERR data before sending it via UART +// Default: 0 (unbuffered) +#ifndef STDERR_UART_BUFFER_SIZE +#define STDERR_UART_BUFFER_SIZE 0 +#endif + +// UART STDERR Buffer Section Name +// Specify the memory section name for UART STDERR buffer +// Default: .stderr_uart_buf +#ifndef STDERR_UART_BUFFER_SECTION +#define STDERR_UART_BUFFER_SECTION ".stderr_uart_buf" +#endif + +// UART STDERR Buffer Alignment +// Define the STDERR buffer alignment in bytes +// Default: 32 +#ifndef STDERR_UART_BUFFER_ALIGNMENT +#define STDERR_UART_BUFFER_ALIGNMENT 32 +#endif + +// Convert LF to CRLF +// If enabled, LF characters are preceded by CR characters on output +// Default: 0 +#ifndef STDERR_CR_LF +#define STDERR_CR_LF 0 +#endif + +#endif /* STDERR_CMSIS_UART_CONFIG_H_ */ diff --git a/Alif/DevKit-E8_ETH/Board/Corstone-320/RTE/CMSIS-Compiler/stdin_cmsis_uart_config.h b/Alif/DevKit-E8_ETH/Board/Corstone-320/RTE/CMSIS-Compiler/stdin_cmsis_uart_config.h new file mode 100644 index 0000000..bce0ba2 --- /dev/null +++ b/Alif/DevKit-E8_ETH/Board/Corstone-320/RTE/CMSIS-Compiler/stdin_cmsis_uart_config.h @@ -0,0 +1,59 @@ +/*--------------------------------------------------------------------------- + * Copyright (c) 2026 Arm Limited (or its affiliates). + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * -------------------------------------------------------------------------- + * + * Purpose: Configure STDIN to CMSIS-Driver USART retarget implementation + * Revision: V1.0.0 + * + * --------------------------------------------------------------------------*/ + +#ifndef STDIN_CMSIS_UART_CONFIG_H_ +#define STDIN_CMSIS_UART_CONFIG_H_ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// UART STDIN Buffer Size +// UART STDIN buffer is used to store STDIN data received via UART +// Default: 64 +#ifndef STDIN_UART_BUFFER_SIZE +#define STDIN_UART_BUFFER_SIZE 64 +#endif + +// UART STDIN Buffer Section Name +// Specify the memory section name for UART STDIN buffer +// Default: .stdin_uart_buf +#ifndef STDIN_UART_BUFFER_SECTION +#define STDIN_UART_BUFFER_SECTION ".stdin_uart_buf" +#endif + +// UART STDIN Buffer Alignment +// Define the STDIN buffer alignment in bytes +// Default: 32 +#ifndef STDIN_UART_BUFFER_ALIGNMENT +#define STDIN_UART_BUFFER_ALIGNMENT 32 +#endif + +// Echo Input Characters +// If enabled, received characters are echoed to STDOUT +// Default: 0 +#ifndef STDIN_ECHO +#define STDIN_ECHO 0 +#endif + +#endif /* STDIN_CMSIS_UART_CONFIG_H_ */ diff --git a/Alif/DevKit-E8_ETH/Board/Corstone-320/RTE/CMSIS-Compiler/stdin_cmsis_uart_config.h.base@1.0.0 b/Alif/DevKit-E8_ETH/Board/Corstone-320/RTE/CMSIS-Compiler/stdin_cmsis_uart_config.h.base@1.0.0 new file mode 100644 index 0000000..bce0ba2 --- /dev/null +++ b/Alif/DevKit-E8_ETH/Board/Corstone-320/RTE/CMSIS-Compiler/stdin_cmsis_uart_config.h.base@1.0.0 @@ -0,0 +1,59 @@ +/*--------------------------------------------------------------------------- + * Copyright (c) 2026 Arm Limited (or its affiliates). + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * -------------------------------------------------------------------------- + * + * Purpose: Configure STDIN to CMSIS-Driver USART retarget implementation + * Revision: V1.0.0 + * + * --------------------------------------------------------------------------*/ + +#ifndef STDIN_CMSIS_UART_CONFIG_H_ +#define STDIN_CMSIS_UART_CONFIG_H_ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// UART STDIN Buffer Size +// UART STDIN buffer is used to store STDIN data received via UART +// Default: 64 +#ifndef STDIN_UART_BUFFER_SIZE +#define STDIN_UART_BUFFER_SIZE 64 +#endif + +// UART STDIN Buffer Section Name +// Specify the memory section name for UART STDIN buffer +// Default: .stdin_uart_buf +#ifndef STDIN_UART_BUFFER_SECTION +#define STDIN_UART_BUFFER_SECTION ".stdin_uart_buf" +#endif + +// UART STDIN Buffer Alignment +// Define the STDIN buffer alignment in bytes +// Default: 32 +#ifndef STDIN_UART_BUFFER_ALIGNMENT +#define STDIN_UART_BUFFER_ALIGNMENT 32 +#endif + +// Echo Input Characters +// If enabled, received characters are echoed to STDOUT +// Default: 0 +#ifndef STDIN_ECHO +#define STDIN_ECHO 0 +#endif + +#endif /* STDIN_CMSIS_UART_CONFIG_H_ */ diff --git a/Alif/DevKit-E8_ETH/Board/Corstone-320/RTE/CMSIS-Compiler/stdio_cmsis_uart_config.h b/Alif/DevKit-E8_ETH/Board/Corstone-320/RTE/CMSIS-Compiler/stdio_cmsis_uart_config.h new file mode 100644 index 0000000..aeeca61 --- /dev/null +++ b/Alif/DevKit-E8_ETH/Board/Corstone-320/RTE/CMSIS-Compiler/stdio_cmsis_uart_config.h @@ -0,0 +1,52 @@ +/*--------------------------------------------------------------------------- + * Copyright (c) 2026 Arm Limited (or its affiliates). + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * -------------------------------------------------------------------------- + * + * Purpose: STDIO to CMSIS Driver USART Retarget Configuration + * Revision: V1.0.0 + * + * --------------------------------------------------------------------------*/ + +#ifndef STDIO_CMSIS_UART_CONFIG_H_ +#define STDIO_CMSIS_UART_CONFIG_H_ + +#ifdef CMSIS_target_header +#include CMSIS_target_header +#else +#define RETARGET_STDIO_UART 0 +#endif + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// Connect to hardware via Driver_USART# +// Select driver control block for hardware interface +// Default: 0 +#ifndef STDIO_UART_DRIVER +#define STDIO_UART_DRIVER RETARGET_STDIO_UART +#endif + +// UART baudrate +// Specifies the baudrate for UART communication +// Common values: 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 +// Default: 115200 +#ifndef STDIO_UART_BAUDRATE +#define STDIO_UART_BAUDRATE 115200 +#endif + +#endif /* STDIO_CMSIS_UART_CONFIG_H_ */ diff --git a/Alif/DevKit-E8_ETH/Board/Corstone-320/RTE/CMSIS-Compiler/stdio_cmsis_uart_config.h.base@1.0.0 b/Alif/DevKit-E8_ETH/Board/Corstone-320/RTE/CMSIS-Compiler/stdio_cmsis_uart_config.h.base@1.0.0 new file mode 100644 index 0000000..aeeca61 --- /dev/null +++ b/Alif/DevKit-E8_ETH/Board/Corstone-320/RTE/CMSIS-Compiler/stdio_cmsis_uart_config.h.base@1.0.0 @@ -0,0 +1,52 @@ +/*--------------------------------------------------------------------------- + * Copyright (c) 2026 Arm Limited (or its affiliates). + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * -------------------------------------------------------------------------- + * + * Purpose: STDIO to CMSIS Driver USART Retarget Configuration + * Revision: V1.0.0 + * + * --------------------------------------------------------------------------*/ + +#ifndef STDIO_CMSIS_UART_CONFIG_H_ +#define STDIO_CMSIS_UART_CONFIG_H_ + +#ifdef CMSIS_target_header +#include CMSIS_target_header +#else +#define RETARGET_STDIO_UART 0 +#endif + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// Connect to hardware via Driver_USART# +// Select driver control block for hardware interface +// Default: 0 +#ifndef STDIO_UART_DRIVER +#define STDIO_UART_DRIVER RETARGET_STDIO_UART +#endif + +// UART baudrate +// Specifies the baudrate for UART communication +// Common values: 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 +// Default: 115200 +#ifndef STDIO_UART_BAUDRATE +#define STDIO_UART_BAUDRATE 115200 +#endif + +#endif /* STDIO_CMSIS_UART_CONFIG_H_ */ diff --git a/Alif/DevKit-E8_ETH/Board/Corstone-320/RTE/CMSIS-Compiler/stdout_cmsis_uart_config.h b/Alif/DevKit-E8_ETH/Board/Corstone-320/RTE/CMSIS-Compiler/stdout_cmsis_uart_config.h new file mode 100644 index 0000000..3cdc2ae --- /dev/null +++ b/Alif/DevKit-E8_ETH/Board/Corstone-320/RTE/CMSIS-Compiler/stdout_cmsis_uart_config.h @@ -0,0 +1,59 @@ +/*--------------------------------------------------------------------------- + * Copyright (c) 2026 Arm Limited (or its affiliates). + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * -------------------------------------------------------------------------- + * + * Purpose: Configure STDOUT to CMSIS-Driver USART retarget implementation + * Revision: V1.0.0 + * + * --------------------------------------------------------------------------*/ + +#ifndef STDOUT_CMSIS_UART_CONFIG_H_ +#define STDOUT_CMSIS_UART_CONFIG_H_ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// UART STDOUT Buffer Size +// UART STDOUT buffer is used to store STDOUT data before sending it via UART +// Default: 0 (unbuffered) +#ifndef STDOUT_UART_BUFFER_SIZE +#define STDOUT_UART_BUFFER_SIZE 0 +#endif + +// UART STDOUT Buffer Section Name +// Specify the memory section name for UART STDOUT buffer +// Default: .stdout_uart_buf +#ifndef STDOUT_UART_BUFFER_SECTION +#define STDOUT_UART_BUFFER_SECTION ".stdout_uart_buf" +#endif + +// UART STDOUT Buffer Alignment +// Define the buffer alignment in bytes +// Default: 32 +#ifndef STDOUT_UART_BUFFER_ALIGNMENT +#define STDOUT_UART_BUFFER_ALIGNMENT 32 +#endif + +// Convert LF to CRLF +// If enabled, LF characters are preceded by CR characters on output +// Default: 0 +#ifndef STDOUT_CR_LF +#define STDOUT_CR_LF 1 +#endif + +#endif /* STDOUT_CMSIS_UART_CONFIG_H_ */ diff --git a/Alif/DevKit-E8_ETH/Board/Corstone-320/RTE/CMSIS-Compiler/stdout_cmsis_uart_config.h.base@1.0.0 b/Alif/DevKit-E8_ETH/Board/Corstone-320/RTE/CMSIS-Compiler/stdout_cmsis_uart_config.h.base@1.0.0 new file mode 100644 index 0000000..323d217 --- /dev/null +++ b/Alif/DevKit-E8_ETH/Board/Corstone-320/RTE/CMSIS-Compiler/stdout_cmsis_uart_config.h.base@1.0.0 @@ -0,0 +1,59 @@ +/*--------------------------------------------------------------------------- + * Copyright (c) 2026 Arm Limited (or its affiliates). + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * -------------------------------------------------------------------------- + * + * Purpose: Configure STDOUT to CMSIS-Driver USART retarget implementation + * Revision: V1.0.0 + * + * --------------------------------------------------------------------------*/ + +#ifndef STDOUT_CMSIS_UART_CONFIG_H_ +#define STDOUT_CMSIS_UART_CONFIG_H_ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// UART STDOUT Buffer Size +// UART STDOUT buffer is used to store STDOUT data before sending it via UART +// Default: 0 (unbuffered) +#ifndef STDOUT_UART_BUFFER_SIZE +#define STDOUT_UART_BUFFER_SIZE 0 +#endif + +// UART STDOUT Buffer Section Name +// Specify the memory section name for UART STDOUT buffer +// Default: .stdout_uart_buf +#ifndef STDOUT_UART_BUFFER_SECTION +#define STDOUT_UART_BUFFER_SECTION ".stdout_uart_buf" +#endif + +// UART STDOUT Buffer Alignment +// Define the buffer alignment in bytes +// Default: 32 +#ifndef STDOUT_UART_BUFFER_ALIGNMENT +#define STDOUT_UART_BUFFER_ALIGNMENT 32 +#endif + +// Convert LF to CRLF +// If enabled, LF characters are preceded by CR characters on output +// Default: 0 +#ifndef STDOUT_CR_LF +#define STDOUT_CR_LF 0 +#endif + +#endif /* STDOUT_CMSIS_UART_CONFIG_H_ */ diff --git a/Alif/DevKit-E8_ETH/Board/Corstone-320/RTE/Device/SSE-320-FVP/ac6_linker_script.sct.src b/Alif/DevKit-E8_ETH/Board/Corstone-320/RTE/Device/SSE-320-FVP/ac6_linker_script.sct.src index 220ca38..c8f36f6 100644 --- a/Alif/DevKit-E8_ETH/Board/Corstone-320/RTE/Device/SSE-320-FVP/ac6_linker_script.sct.src +++ b/Alif/DevKit-E8_ETH/Board/Corstone-320/RTE/Device/SSE-320-FVP/ac6_linker_script.sct.src @@ -48,9 +48,6 @@ LR_ROM1 __ROM1_BASE __ROM1_SIZE { ER_ROM1 __ROM1_BASE __ROM1_SIZE { *(+RO +XO) } -} - -LR_RAM0 __RAM0_BASE { RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE) { *.o(.bss.noinit) @@ -58,6 +55,9 @@ LR_RAM0 __RAM0_BASE { } RW_RAM0 AlignExpr(+0, 8) (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { + ; Ethos-U writable area + *.o (ethos_arena) + *(+RW +ZI) } @@ -76,11 +76,8 @@ LR_RAM0 __RAM0_BASE { #if __RAM1_SIZE > 0 RW_RAM1 __RAM1_BASE __RAM1_SIZE { - ; Ethos-U Cache Area - *.o (*ethos_cache_buf) - - ; NN Activation Tensor (activation buffer / tensor arena) - *.o (*activation_buf) + ; Ethos-U arena cache + *.o (ethos_cache) .ANY (+RW +ZI) } @@ -102,8 +99,8 @@ LR_RAM0 __RAM0_BASE { #if __ROM2_SIZE > 0 LR_ROM2 __ROM2_BASE __ROM2_SIZE { ER_ROM2 +0 __ROM2_SIZE { - ; NN Model Binary Representation - *.o (nn_model) + ; Ethos-U model, command stream and constants + *.o (ethos_model) .ANY (+RO +XO) } diff --git a/Alif/DevKit-E8_ETH/Board/Corstone-320/RTE/Device/SSE-320-FVP/clang_linker_script.ld.src b/Alif/DevKit-E8_ETH/Board/Corstone-320/RTE/Device/SSE-320-FVP/clang_linker_script.ld.src new file mode 100644 index 0000000..2ce72ee --- /dev/null +++ b/Alif/DevKit-E8_ETH/Board/Corstone-320/RTE/Device/SSE-320-FVP/clang_linker_script.ld.src @@ -0,0 +1,412 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright © 2019 Keith Packard + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED + * OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* ---------------------------------------------------------------------------- + Stack seal size definition + *----------------------------------------------------------------------------*/ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define __STACKSEAL_SIZE ( 8 ) +#else +#define __STACKSEAL_SIZE ( 0 ) +#endif + +/* ---------------------------------------------------------------------------- + Memory definition + *----------------------------------------------------------------------------*/ +MEMORY +{ + ROM0 (rx!w) : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE +#if __ROM1_SIZE > 0 + ROM1 (rx!w) : ORIGIN = __ROM1_BASE, LENGTH = __ROM1_SIZE +#endif +#if __ROM2_SIZE > 0 + ROM2 (rx!w) : ORIGIN = __ROM2_BASE, LENGTH = __ROM2_SIZE +#endif +#if __ROM3_SIZE > 0 + ROM3 (rx!w) : ORIGIN = __ROM3_BASE, LENGTH = __ROM3_SIZE +#endif + + RAM0 (w!rx) : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE +#if __RAM1_SIZE > 0 + RAM1 (w!rx) : ORIGIN = __RAM1_BASE, LENGTH = __RAM1_SIZE +#endif +#if __RAM2_SIZE > 0 + RAM2 (w!rx) : ORIGIN = __RAM2_BASE, LENGTH = __RAM2_SIZE +#endif +#if __RAM3_SIZE > 0 + RAM3 (w!rx) : ORIGIN = __RAM3_BASE, LENGTH = __RAM3_SIZE +#endif +} + +ENTRY(Reset_Handler) + +PHDRS +{ + boot PT_LOAD; + text PT_LOAD; + ram PT_LOAD; + ram_init PT_LOAD; + tls PT_TLS; +#if __RAM1_SIZE > 0 + ethos_ram PT_LOAD; +#endif +#if __ROM2_SIZE > 0 + ethos_model PT_LOAD; +#endif +} + +SECTIONS +{ + .init : { + KEEP (*(.vectors)) + + /* Disable by default + * + * *.init.enter contains a vector table provided by picolibc, + * whereas CMSIS already provides a vector table via .vectors + */ + /* + KEEP (*(.text.init.enter)) + KEEP (*(.data.init.enter)) + */ + + KEEP (*(SORT_BY_NAME(.init) SORT_BY_NAME(.init.*))) + } >ROM0 AT>ROM0 :boot + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + .veneers : + { + . = ALIGN(32); + KEEP(*(.gnu.sgstubs)) + } > ROM0 AT>ROM0 :boot +#endif + + .text : { + + /* code */ + *(.text.unlikely .text.unlikely.*) + *(.text.startup .text.startup.*) + *(.text .text.* .opd .opd.*) + *(.gnu.linkonce.t.*) + KEEP (*(.fini .fini.*)) + __text_end = .; + + PROVIDE (__etext = __text_end); + PROVIDE (_etext = __text_end); + PROVIDE (etext = __text_end); + + /* read-only data */ + *(.rdata) + *(.rodata .rodata.*) + *(.gnu.linkonce.r.*) + + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + *(.data.rel.ro .data.rel.ro.*) + *(.got .got.*) + + /* Need to pre-align so that the symbols come after padding */ + . = ALIGN(8); + + /* lists of constructors and destructors */ + PROVIDE_HIDDEN ( __bothinit_array_start = . ); + PROVIDE_HIDDEN ( __preinit_array_start = . ); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN ( __preinit_array_end = . ); + + PROVIDE_HIDDEN ( __init_array_start = . ); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array .ctors)) + PROVIDE_HIDDEN ( __init_array_end = . ); + PROVIDE_HIDDEN ( __bothinit_array_end = . ); + + PROVIDE_HIDDEN ( __fini_array_start = . ); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array .dtors)) + PROVIDE_HIDDEN ( __fini_array_end = . ); + + } >ROM1 AT>ROM1 :text + + .toc : { + *(.toc .toc.*) + } >ROM1 AT>ROM1 :text + + /* additional sections when compiling with C++ exception support */ + + .except_ordered : { + *(.gcc_except_table *.gcc_except_table.*) + KEEP (*(.eh_frame .eh_frame.*)) + *(.ARM.extab* .gnu.linkonce.armextab.*) + } >ROM1 AT>ROM1 :text + + .except_unordered : { + . = ALIGN(8); + + PROVIDE(__exidx_start = .); + *(.ARM.exidx*) + PROVIDE(__exidx_end = .); + } >ROM1 AT>ROM1 :text + + + /* + * Data values which are preserved across reset + */ + .preserve (NOLOAD) : { + PROVIDE(__preserve_start__ = .); + KEEP(*(SORT_BY_NAME(.preserve.*))) + KEEP(*(.preserve)) + PROVIDE(__preserve_end__ = .); + } >RAM0 AT>RAM0 :ram + + .data : { + *(.data .data.*) + *(.gnu.linkonce.d.*) + + /* Need to pre-align so that the symbols come after padding */ + . = ALIGN(8); + + PROVIDE( __global_pointer$ = . + 0x800 ); + *(.sdata .sdata.* .sdata2.*) + *(.gnu.linkonce.s.*) + } >RAM0 AT>ROM1 :ram_init + PROVIDE(__data_start = ADDR(.data)); + PROVIDE(__data_source = LOADADDR(.data)); + + /* Thread local initialized data. This gets + * space allocated as it is expected to be placed + * in ram to be used as a template for TLS data blocks + * allocated at runtime. We're slightly abusing that + * by placing the data in flash where it will be copied + * into the allocate ram addresses by the existing + * data initialization code in crt0 + */ + .tdata : { + *(.tdata .tdata.* .gnu.linkonce.td.*) + PROVIDE(__data_end = .); + PROVIDE(__tdata_end = .); + } >RAM0 AT>ROM1 :tls :ram_init + PROVIDE( __tls_base = ADDR(.tdata)); + PROVIDE( __tdata_start = ADDR(.tdata)); + PROVIDE( __tdata_source = LOADADDR(.tdata) ); + PROVIDE( __tdata_source_end = LOADADDR(.tdata) + SIZEOF(.tdata) ); + PROVIDE( __data_source_end = __tdata_source_end ); + PROVIDE( __tdata_size = SIZEOF(.tdata) ); + PROVIDE( __tls_align = MAX(ALIGNOF(.tdata),ALIGNOF(.tbss)) ); + + PROVIDE( __edata = __data_end ); + PROVIDE( _edata = __data_end ); + PROVIDE( edata = __data_end ); + PROVIDE( __data_size = __data_end - __data_start ); + PROVIDE( __data_source_size = __data_source_end - __data_source ); + + .tbss (NOLOAD) : { + *(.tbss .tbss.* .gnu.linkonce.tb.*) + *(.tcommon) + PROVIDE( __tls_end = . ); + PROVIDE( __tbss_end = . ); + } >RAM0 AT>RAM0 :tls :ram + PROVIDE( __bss_start = ADDR(.tbss)); + PROVIDE( __tbss_start = ADDR(.tbss)); + PROVIDE( __tbss_offset = ADDR(.tbss) - ADDR(.tdata) ); + PROVIDE( __tbss_size = SIZEOF(.tbss) ); + PROVIDE( __tls_size = __tls_end - __tls_base ); + PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) ); + PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) ); + PROVIDE( __arm64_tls_tcb_offset = MAX(16, __tls_align) ); + + /* + * The linker special cases .tbss segments which are + * identified as segments which are not loaded and are + * thread_local. + * + * For these segments, the linker does not advance 'dot' + * across them. We actually need memory allocated for tbss, + * so we create a special segment here just to make room + */ + /* + .tbss_space (NOLOAD) : { + . = ADDR(.tbss); + . = . + SIZEOF(.tbss); + } >RAM0 AT>RAM0 :ram + */ + + .bss (NOLOAD) : { + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + + /* Align the end of this section, so next can start on aligned address */ + . = ALIGN(8); + __bss_end = .; + } >RAM0 AT>RAM0 :ram + PROVIDE( __non_tls_bss_start = ADDR(.bss) ); + PROVIDE( __bss_size = __bss_end - __bss_start ); + + /* This section contains data that is not initialized during load, + or during the application's initialization sequence. */ + .noinit (NOLOAD) : { + __noinit_start__ = .; + *(.noinit) + *(.noinit.*) + + /* Align the end of this section, so next (heap) can start on aligned address */ + . = ALIGN(8); + __noinit_end__ = .; + } >RAM0 AT>RAM0 :ram + + /* Ethos-U writable area */ + .ethos_arena (NOLOAD) : ALIGN(32) { + *(ethos_arena) + } >RAM0 AT>RAM0 :ram + + PROVIDE( __end = . ); + PROVIDE( _end = . ); + PROVIDE( end = . ); + + /* Make the rest of memory available for heap storage */ + PROVIDE (__heap_start = __end); +#ifdef __HEAP_SIZE + PROVIDE (__heap_end = __heap_start + __HEAP_SIZE); + PROVIDE (__heap_size = __HEAP_SIZE); +#else + PROVIDE (__heap_end = __stack - __STACK_SIZE); + PROVIDE (__heap_size = __heap_end - __heap_start); +#endif + .heap (NOLOAD) : { + . += __heap_size; + } >RAM0 :ram + + /* Define a stack region to make sure it fits in memory */ + PROVIDE(__stack = ORIGIN(RAM0) + LENGTH(RAM0) - __STACKSEAL_SIZE); + PROVIDE(__stack_limit = __stack - __STACK_SIZE); + .stack (__stack_limit) (NOLOAD) : { + . += __STACK_SIZE; + } >RAM0 :ram + +#if __STACKSEAL_SIZE > 0 + PROVIDE(__stack_seal = __stack); + .stackseal (__stack) (NOLOAD) : + { + . += __STACKSEAL_SIZE; + } >RAM0 :ram +#endif + + /* Ethos-U arena cache */ +#if __RAM1_SIZE > 0 + .ethos_cache (NOLOAD) : ALIGN(32) { + *(ethos_cache) + } >RAM1 AT>RAM1 :ethos_ram +#endif + + /* Ethos-U model, command stream and constants */ +#if __ROM2_SIZE > 0 + .ethos_model : ALIGN(32) { + *(ethos_model) + } >ROM2 AT>ROM2 :ethos_model +#endif + + /* Throw away C++ exception handling information */ + + /* + + /DISCARD/ : { + *(.note .note.*) + *(.eh_frame .eh_frame.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + *(.ARM.exidx*) + } + + */ + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .gnu.build.attributes : { *(.gnu.build.attributes .gnu.build.attributes.*) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1. */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions. */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2. */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2. */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line .debug_line.* .debug_line_end) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions. */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + /* DWARF 3. */ + .debug_pubtypes 0 : { *(.debug_pubtypes) } + .debug_ranges 0 : { *(.debug_ranges) } + /* DWARF 5. */ + .debug_addr 0 : { *(.debug_addr) } + .debug_line_str 0 : { *(.debug_line_str) } + .debug_loclists 0 : { *(.debug_loclists) } + .debug_macro 0 : { *(.debug_macro) } + .debug_names 0 : { *(.debug_names) } + .debug_rnglists 0 : { *(.debug_rnglists) } + .debug_str_offsets 0 : { *(.debug_str_offsets) } + .debug_sup 0 : { *(.debug_sup) } + .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) } +} +/* + * Check that sections that are copied from flash to RAM have matching + * padding, so that a single memcpy() of __data_size copies the correct bytes. + */ +ASSERT( __data_size == __data_source_size, + "ERROR: .data/.tdata flash size does not match RAM size"); + diff --git a/Alif/DevKit-E8_ETH/Board/Corstone-320/RTE/Device/SSE-320-FVP/device_cfg.h b/Alif/DevKit-E8_ETH/Board/Corstone-320/RTE/Device/SSE-320-FVP/device_cfg.h index 3a68938..19e2c88 100644 --- a/Alif/DevKit-E8_ETH/Board/Corstone-320/RTE/Device/SSE-320-FVP/device_cfg.h +++ b/Alif/DevKit-E8_ETH/Board/Corstone-320/RTE/Device/SSE-320-FVP/device_cfg.h @@ -64,14 +64,8 @@ /* ARM UART Controller CMSDK */ #ifdef RTE_USART0 #define UART0_CMSDK_S -#ifdef UART0_BASE_S_TMP -/* Workaround for UART0 CMSDK base address mismatch */ -extern struct uart_cmsdk_dev_t UART0_CMSDK_DEV_S_TMP; -#define UART0_CMSDK_DEV UART0_CMSDK_DEV_S_TMP -#else #define UART0_CMSDK_DEV UART0_CMSDK_DEV_S #endif -#endif #ifdef RTE_USART1 #define UART1_CMSDK_S #define UART1_CMSDK_DEV UART1_CMSDK_DEV_S diff --git a/Alif/DevKit-E8_ETH/Board/Corstone-320/RTE/Device/SSE-320-FVP/gcc_linker_script.ld.src b/Alif/DevKit-E8_ETH/Board/Corstone-320/RTE/Device/SSE-320-FVP/gcc_linker_script.ld.src index 2e2ef6f..eb53773 100644 --- a/Alif/DevKit-E8_ETH/Board/Corstone-320/RTE/Device/SSE-320-FVP/gcc_linker_script.ld.src +++ b/Alif/DevKit-E8_ETH/Board/Corstone-320/RTE/Device/SSE-320-FVP/gcc_linker_script.ld.src @@ -281,6 +281,12 @@ SECTIONS __noinit_end = .; } > RAM0 + /* Ethos-U writable area */ + .ethos_arena (NOLOAD) : ALIGN(32) + { + *(ethos_arena) + } > RAM0 + .heap (NOLOAD) : { . = ALIGN(8); @@ -318,8 +324,7 @@ SECTIONS .cache (NOLOAD): { . = ALIGN(32); - *(*ethos_cache_buf) /* Ethos-U Cache Area */ - *(*activation_buf) /* NN Activation Tensor (activation buffer / tensor arena) */ + *(ethos_cache) /* Ethos-U arena cache */ } > RAM1 /* Initialized buffers in fast access RAM */ @@ -331,7 +336,7 @@ SECTIONS .rom2 : { - *(*nn_model) /* NN Model Binary Representation */ + *(ethos_model) /* Ethos-U model, command stream and constants */ } > ROM2 .rom3 : diff --git a/Alif/DevKit-E8_ETH/Board/Corstone-320/RTE/Device/SSE-320-FVP/iar_linker_script.icf.src b/Alif/DevKit-E8_ETH/Board/Corstone-320/RTE/Device/SSE-320-FVP/iar_linker_script.icf.src index ea02d53..9696ab1 100644 --- a/Alif/DevKit-E8_ETH/Board/Corstone-320/RTE/Device/SSE-320-FVP/iar_linker_script.icf.src +++ b/Alif/DevKit-E8_ETH/Board/Corstone-320/RTE/Device/SSE-320-FVP/iar_linker_script.icf.src @@ -42,8 +42,6 @@ define memory mem with size = 4G; define region ROM3_region = []; #endif -define region ROM_region = ROM0_region | ROM1_region | ROM2_region | ROM3_region; - #if __RAM0_SIZE > 0 define region RAM0_region = mem:[from __RAM0_BASE to (__RAM0_BASE+__RAM0_SIZE-1)]; #else @@ -68,8 +66,6 @@ define region ROM_region = ROM0_region | ROM1_region | ROM2_region | ROM3_regio define region RAM3_region = []; #endif -define region RAM_region = RAM0_region | RAM1_region | RAM2_region | RAM3_region; - do not initialize { section .noinit }; initialize by copy { readwrite }; if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) @@ -80,15 +76,42 @@ if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) place at address mem:__ROM0_BASE { readonly section .intvec }; -if (!isempty(ROM_region)) +if (!isempty(ROM1_region)) { - place in ROM_region { readonly }; + place in ROM1_region { readonly }; } -if (!isempty(RAM_region)) +if (!isempty(RAM0_region)) { define block CSTACK with alignment = 8, size = __STACK_SIZE { }; define block PROC_STACK with alignment = 8, size = 0 { }; define block HEAP with alignment = 8, size = __HEAP_SIZE { }; - place in RAM_region { readwrite, block CSTACK, block PROC_STACK, block HEAP }; + place in RAM0_region { readwrite, block PROC_STACK, block HEAP }; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + /* Reserve the stack seal immediately above the stack. */ + define block STACKSEAL with alignment = 8, size = 8 { }; + define block CSTACK_WITH_SEAL with fixed order { block CSTACK, block STACKSEAL }; + place at end of RAM0_region { block CSTACK_WITH_SEAL }; +#else + place at end of RAM0_region { block CSTACK }; +#endif } + +/* Ethos-U writable area */ + do not initialize { section ethos_arena }; + define block ETHOS_ARENA with alignment = 32 { section ethos_arena }; + place in RAM0_region { block ETHOS_ARENA }; + +/* Ethos-U arena cache */ +#if __RAM1_SIZE > 0 + do not initialize { section ethos_cache }; + define block ETHOS_CACHE with alignment = 32 + { section ethos_cache }; + place in RAM1_region { block ETHOS_CACHE }; +#endif + +/* Ethos-U model, command stream and constants */ +#if __ROM2_SIZE > 0 + define block ETHOS_MODEL with alignment = 32 { readonly section ethos_model }; + place in ROM2_region { block ETHOS_MODEL }; +#endif diff --git a/Alif/DevKit-E8_ETH/Board/Corstone-320/regions_SSE-320.h b/Alif/DevKit-E8_ETH/Board/Corstone-320/RTE/Device/SSE-320-FVP/regions_SSE-320.h similarity index 100% rename from Alif/DevKit-E8_ETH/Board/Corstone-320/regions_SSE-320.h rename to Alif/DevKit-E8_ETH/Board/Corstone-320/RTE/Device/SSE-320-FVP/regions_SSE-320.h diff --git a/Alif/DevKit-E8_ETH/Board/Corstone-320/sse320_memmap_ns.h b/Alif/DevKit-E8_ETH/Board/Corstone-320/RTE/Device/SSE-320-FVP/sse320_memmap_ns.h similarity index 100% rename from Alif/DevKit-E8_ETH/Board/Corstone-320/sse320_memmap_ns.h rename to Alif/DevKit-E8_ETH/Board/Corstone-320/RTE/Device/SSE-320-FVP/sse320_memmap_ns.h diff --git a/Alif/DevKit-E8_ETH/Board/Corstone-320/sse320_memmap_s.h b/Alif/DevKit-E8_ETH/Board/Corstone-320/RTE/Device/SSE-320-FVP/sse320_memmap_s.h similarity index 100% rename from Alif/DevKit-E8_ETH/Board/Corstone-320/sse320_memmap_s.h rename to Alif/DevKit-E8_ETH/Board/Corstone-320/RTE/Device/SSE-320-FVP/sse320_memmap_s.h diff --git a/Alif/DevKit-E8_ETH/Board/Corstone-320/ethos_setup.c b/Alif/DevKit-E8_ETH/Board/Corstone-320/ethos_setup.c index ca26dfa..4787ebb 100644 --- a/Alif/DevKit-E8_ETH/Board/Corstone-320/ethos_setup.c +++ b/Alif/DevKit-E8_ETH/Board/Corstone-320/ethos_setup.c @@ -1,5 +1,5 @@ -/*--------------------------------------------------------------------------- - * Copyright (c) 2025 Arm Limited (or its affiliates). All rights reserved. +/* + * Copyright 2025-2026 Arm Limited and/or its affiliates. * * SPDX-License-Identifier: Apache-2.0 * @@ -14,7 +14,7 @@ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. - *---------------------------------------------------------------------------*/ + */ #include @@ -26,18 +26,18 @@ #if defined(ETHOSU65) || defined(ETHOSU85) /* Define Ethos-U NPU cache buffer size */ -#ifndef ETHOS_CACHE_BUF_SIZE -#define ETHOS_CACHE_BUF_SIZE 393216 +#ifndef ETHOS_CACHE_SIZE +#define ETHOS_CACHE_SIZE 0 #endif /* Define Ethos-U cache buffer alignment */ -#ifndef ETHOS_CACHE_BUF_ALIGNMENT -#define ETHOS_CACHE_BUF_ALIGNMENT 32 +#ifndef ETHOS_CACHE_ALIGNMENT +#define ETHOS_CACHE_ALIGNMENT 32 #endif /* Define Ethos-U NPU cache buffer attributes */ -#ifndef ETHOS_CACHE_BUF_ATTRIBUTES -#define ETHOS_CACHE_BUF_ATTRIBUTES __attribute__((section("ethos_cache_buf"), aligned(ETHOS_CACHE_BUF_ALIGNMENT))) +#ifndef ETHOS_CACHE_ATTRIBUTES +#define ETHOS_CACHE_ATTRIBUTES __attribute__((section("ethos_cache"), aligned(ETHOS_CACHE_ALIGNMENT))) #endif #endif @@ -54,14 +54,15 @@ /* Ethos NPU driver instance. */ static struct ethosu_driver EthosDriver; -#if defined(ETHOSU65) || defined(ETHOSU85) -static uint8_t ethos_cache[ETHOS_CACHE_BUF_SIZE] ETHOS_CACHE_BUF_ATTRIBUTES; +#if (defined(ETHOSU65) || defined(ETHOSU85)) && (ETHOS_CACHE_SIZE > 0) +/* Ethos-U NPU cache buffer */ +static uint8_t ethos_cache_buf[ETHOS_CACHE_SIZE] ETHOS_CACHE_ATTRIBUTES; #endif /* Ethos NPU interrupt handler. */ -void NPU0_Handler(void) { +void NPU0_Handler (void) { ethosu_irq_handler(&EthosDriver); } @@ -76,9 +77,9 @@ void ethos_setup (void) { /* Initialize Ethos-U NPU driver. */ rval = ethosu_init(&EthosDriver, /* Ethos-U device driver */ ethos_base_addr, /* Ethos-U base address */ - #if defined(ETHOSU65) || defined(ETHOSU85) - ethos_cache, /* Cache memory pointer */ - sizeof(ethos_cache), /* Cache memory size */ + #if (defined(ETHOSU65) || defined(ETHOSU85)) && (ETHOS_CACHE_SIZE > 0) + ethos_cache_buf, /* Cache memory pointer */ + sizeof(ethos_cache_buf), /* Cache memory size */ #else 0, /* Cache memory pointer */ 0, /* Cache memory size */ diff --git a/Alif/DevKit-E8_ETH/Board/Corstone-320/ethosu_dcache.c b/Alif/DevKit-E8_ETH/Board/Corstone-320/ethosu_dcache.c new file mode 100644 index 0000000..015a9d1 --- /dev/null +++ b/Alif/DevKit-E8_ETH/Board/Corstone-320/ethosu_dcache.c @@ -0,0 +1,78 @@ +/* + * Copyright 2026 Arm Limited and/or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include + +#include "ethosu_driver.h" + +/** + \brief Cleans data-cache contents associated with buffers accessed by the NPU. + + Ensures that CPU writes to cacheable buffers are committed to memory before + the NPU starts accessing them. Non-cacheable buffers require no cache clean, + but the function ensures that all preceding memory accesses have completed + before it returns. + + \param[in] base_addr Array of buffer base addresses. + \param[in] base_addr_size Array containing the size, in bytes, of each buffer. + \param[in] num_base_addr Number of entries in the address and size arrays. +*/ +void ethosu_flush_dcache(const uint64_t *base_addr, const size_t *base_addr_size, int num_base_addr) { + + for (int i = 0; i < num_base_addr; i++) { + if ((base_addr[i] & 0x1F) != 0) { + /* Base address must be cache line aligned (32 bytes) */ + // ... + return; + } + + /* Flush data-cache for current buffer */ + // ... + // 32-bit system must cast base_addr to uint32_t* to avoid sign expansion + // CleanDCache((uint32_t *)(uint32_t)base_addr[i], base_addr_size[i]); + } +} + +/** + \brief Invalidates data-cache contents associated with buffers accessed by the NPU. + + Ensures that subsequent CPU reads observe data written by the NPU. Dirty + cache lines may be cleaned before invalidation to preserve pending CPU + writes. For non-cacheable buffers, no cache invalidation is required, + but the function ensures that all preceding memory accesses have completed + before it returns. + + \param[in] base_addr Array of buffer base addresses. + \param[in] base_addr_size Array containing the size, in bytes, of each buffer. + \param[in] num_base_addr Number of entries in the address and size arrays. +*/ +void ethosu_invalidate_dcache(const uint64_t *base_addr, const size_t *base_addr_size, int num_base_addr) { + + for (int i = 0; i < num_base_addr; i++) { + if ((base_addr[i] & 0x1F) != 0) { + /* Base address must be cache line aligned (32 bytes) */ + // ... + return; + } + + /* Invalidate data-cache for current buffer */ + // ... + // 32-bit system must cast base_addr to uint32_t* to avoid sign expansion + // InvalidateDCache((uint32_t *)(uint32_t)base_addr[i], base_addr_size[i]); + } +} diff --git a/Alif/DevKit-E8_ETH/Board/Corstone-320/ethosu_os_rtos2.c b/Alif/DevKit-E8_ETH/Board/Corstone-320/ethosu_os_rtos2.c new file mode 100644 index 0000000..fdab39b --- /dev/null +++ b/Alif/DevKit-E8_ETH/Board/Corstone-320/ethosu_os_rtos2.c @@ -0,0 +1,141 @@ +/* + * Copyright 2026 Arm Limited and/or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ethosu_driver.h" +#include "cmsis_os2.h" + +/* Maximum number of Ethos-U instances. */ +/* Used as maximum semaphore count in ethosu_semaphore_create. */ +#ifndef ETHOSU_MAX_INSTANCES +#define ETHOSU_MAX_INSTANCES 2 +#endif + +/** + \brief Create a mutex object. + \return Pointer to a mutex object. +*/ +void *ethosu_mutex_create(void) { + osMutexId_t mutex_id = osMutexNew(NULL); + return (void *) mutex_id; +} + +/** + \brief Destroy a mutex object. + \param[in] mutex mutex object. +*/ +void ethosu_mutex_destroy(void *mutex) { + osMutexId_t mutex_id = (osMutexId_t) mutex; + osMutexDelete(mutex_id); +} + +/** + \brief Lock a mutex. + \param[in] mutex mutex object. + \return 0 on success, else negative error codes +*/ +int ethosu_mutex_lock(void *mutex) { + osMutexId_t mutex_id = (osMutexId_t) mutex; + osStatus_t status; + int rval; + + status = osMutexAcquire(mutex_id, osWaitForever); + if (status == osOK) { + rval = 0; + } else { + rval = -1; + } + return rval; +} + +/** + \brief Unlock a mutex. + \param[in] mutex mutex object. + \return 0 on success, else negative error codes +*/ +int ethosu_mutex_unlock(void *mutex) { + osMutexId_t mutex_id = (osMutexId_t) mutex; + osStatus_t status; + int rval; + + status = osMutexRelease(mutex_id); + if (status == osOK) { + rval = 0; + } else { + rval = -1; + } + return rval; +} + +/** + \brief Create a semaphore object. + \return Pointer to a semaphore object. +*/ +void *ethosu_semaphore_create(void) { + osSemaphoreId_t sem_id; + + sem_id = osSemaphoreNew(ETHOSU_MAX_INSTANCES, 0U, NULL); + return (void *) sem_id; +} + +/** + \brief Destroy a semaphore object. + \param[in] sem semaphore object. +*/ +void ethosu_semaphore_destroy(void *sem) { + osSemaphoreId_t sem_id = (osSemaphoreId_t) sem; + osSemaphoreDelete(sem_id); +} + +/** + \brief Take a semaphore object with timeout. + \param[in] sem semaphore object. + \param[in] timeout timeout value in ticks. + \return 0 on success, else negative error codes +*/ +int ethosu_semaphore_take(void *sem, uint64_t timeout) { + osSemaphoreId_t sem_id = (osSemaphoreId_t) sem; + osStatus_t status; + int rval; + + status = osSemaphoreAcquire(sem_id, timeout); + if (status == osOK) { + rval = 0; + } else { + rval = -1; + } + return rval; +} + +/** + \brief Give a semaphore object. + \param[in] sem semaphore object. + \return 0 on success, else negative error codes +*/ +int ethosu_semaphore_give(void *sem) { + osSemaphoreId_t sem_id = (osSemaphoreId_t) sem; + osStatus_t status; + int rval; + + status = osSemaphoreRelease(sem_id); + if (status == osOK) { + rval = 0; + } else { + rval = -1; + } + return rval; +} diff --git a/Alif/DevKit-E8_ETH/Board/Corstone-320/fvp_config.txt b/Alif/DevKit-E8_ETH/Board/Corstone-320/fvp_config.txt index a7cb35e..d5f0890 100644 --- a/Alif/DevKit-E8_ETH/Board/Corstone-320/fvp_config.txt +++ b/Alif/DevKit-E8_ETH/Board/Corstone-320/fvp_config.txt @@ -1,6 +1,7 @@ # Parameters: # instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] #------------------------------------------------------------------------------ +mps4_board.subsystem.ethosu.extra_args="--fast" # (string, init-time) default = '' : To activate fast processing mode, which significantly improves the performance of the model, set this parameter to "--fast". In fast mode, NPU performance counters are not representative of counters on real hardware. We recommend you do not use any other value without instructions from Arm Technical Support. mps4_board.subsystem.ethosu.num_macs=256 # (int , init-time) default = '0x400' : Number of 8x8 MACs performed per cycle (128, 256, 512, 1024, or 2048). : [0x80:0x800] mps4_board.telnetterminal0.quiet=1 # (bool , init-time) default = '0' : Avoid output on stdout/stderr mps4_board.telnetterminal0.start_telnet=0 # (bool , init-time) default = '1' : Start telnet if nothing connected @@ -15,5 +16,4 @@ mps4_board.uart0.shutdown_on_eot=1 # (bool , init-time) defa mps4_board.v_path=./Board/Corstone-320/vsi/python/ # (string, init-time) default = '' : Specify path to python folder with scripts for both of VSI and VIO mps4_board.visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation vis_hdlcd.disable_visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation -mps4_board.subsystem.ethosu.extra_args='--fast' # (string, init-time) default = '' : To activate fast processing mode, which significantly improves the performance of the model, set this parameter to '--fast'. In fast mode, NPU performance counters are not representative of counters on real hardware. We recommend you do not use any other value without instructions from Arm Technical Support. #------------------------------------------------------------------------------ diff --git a/Alif/DevKit-E8_ETH/Board/Corstone-320/main.c b/Alif/DevKit-E8_ETH/Board/Corstone-320/main.c index 6d2b31a..009aec0 100644 --- a/Alif/DevKit-E8_ETH/Board/Corstone-320/main.c +++ b/Alif/DevKit-E8_ETH/Board/Corstone-320/main.c @@ -1,5 +1,5 @@ -/*--------------------------------------------------------------------------- - * Copyright (c) 2024 Arm Limited (or its affiliates). All rights reserved. +/* + * Copyright 2024-2026 Arm Limited and/or its affiliates. * * SPDX-License-Identifier: Apache-2.0 * @@ -14,32 +14,13 @@ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. - *---------------------------------------------------------------------------*/ + */ #include "RTE_Components.h" #include CMSIS_device_header #include "main.h" -#ifdef UART0_BASE_S_TMP -/* Workaround for UART0 CMSDK base address mismatch */ -#include "uart_cmsdk_drv.h" - -static const struct uart_cmsdk_dev_cfg_t UART0_CMSDK_DEV_CFG_S_TMP = { - .base = 0x58203000 + 0x01100000, - .default_baudrate = 115200 -}; -static struct uart_cmsdk_dev_data_t UART0_CMSDK_DEV_DATA_S_TMP = { - .state = 0, - .system_clk = 0, - .baudrate = 0 -}; -struct uart_cmsdk_dev_t UART0_CMSDK_DEV_S_TMP = { - &(UART0_CMSDK_DEV_CFG_S_TMP), - &(UART0_CMSDK_DEV_DATA_S_TMP) -}; -#endif - int main (void) { /* Initialize STDIO */ diff --git a/Alif/DevKit-E8_ETH/Board/Corstone-320/main.h b/Alif/DevKit-E8_ETH/Board/Corstone-320/main.h index 6e2048e..2b576ad 100644 --- a/Alif/DevKit-E8_ETH/Board/Corstone-320/main.h +++ b/Alif/DevKit-E8_ETH/Board/Corstone-320/main.h @@ -1,6 +1,6 @@ -/*--------------------------------------------------------------------------- - * Copyright (c) 2020-2025 Arm Limited (or its affiliates). - * All rights reserved. +/* + * Copyright 2020-2026 Arm Limited and/or its affiliates. + * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may @@ -14,7 +14,7 @@ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. - *---------------------------------------------------------------------------*/ + */ #ifndef MAIN_H__ #define MAIN_H__ diff --git a/Alif/DevKit-E8_ETH/Board/Corstone-320/retarget_stdio.c b/Alif/DevKit-E8_ETH/Board/Corstone-320/retarget_stdio.c deleted file mode 100644 index f553eed..0000000 --- a/Alif/DevKit-E8_ETH/Board/Corstone-320/retarget_stdio.c +++ /dev/null @@ -1,161 +0,0 @@ -/*--------------------------------------------------------------------------- - * Copyright (c) 2025 Arm Limited (or its affiliates). - * All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * Name: retarget_stdio.c - * Purpose: Retarget stdio to CMSIS UART - * - *---------------------------------------------------------------------------*/ - -#ifdef CMSIS_target_header -#include CMSIS_target_header -#else -#include "Driver_USART.h" -#endif - -#ifndef RETARGET_STDIO_UART -#error "RETARGET_STDIO_UART not defined!" -#endif - -/* Compile-time configuration */ -#ifndef UART_BAUDRATE -#define UART_BAUDRATE 115200 -#endif - -/* References to the external retarget functions */ -extern int stdio_init (void); -extern int stderr_putchar (int ch); -extern int stdout_putchar (int ch); -extern int stdin_getchar (void); - -/* Reference to the underlying USART driver */ -#ifndef CMSIS_target_header -extern ARM_DRIVER_USART ARM_Driver_USART_(RETARGET_STDIO_UART); -#endif -#define ptrUSART (&ARM_Driver_USART_(RETARGET_STDIO_UART)) - -/** - Initialize stdio - - \return 0 on success, or -1 on error. -*/ -int stdio_init (void) { - - if (ptrUSART->Initialize(NULL) != ARM_DRIVER_OK) { - return -1; - } - - if (ptrUSART->PowerControl(ARM_POWER_FULL) != ARM_DRIVER_OK) { - return -1; - } - - if (ptrUSART->Control(ARM_USART_MODE_ASYNCHRONOUS | - ARM_USART_DATA_BITS_8 | - ARM_USART_PARITY_NONE | - ARM_USART_STOP_BITS_1 | - ARM_USART_FLOW_CONTROL_NONE, - UART_BAUDRATE) != ARM_DRIVER_OK) { - return -1; - } - - if (ptrUSART->Control(ARM_USART_CONTROL_RX, 1U) != ARM_DRIVER_OK) { - return -1; - } - - if (ptrUSART->Control(ARM_USART_CONTROL_TX, 1U) != ARM_DRIVER_OK) { - return -1; - } - - return 0; -} - -/** - Put a character to the stderr - - \param[in] ch Character to output - \return The character written, or -1 on write error. -*/ -int stderr_putchar (int ch) { - uint8_t buf[1]; - - if (ch == '\n') { - buf[0] = (uint8_t)'\r'; - - if (ptrUSART->Send(buf, 1U) != ARM_DRIVER_OK) { - return -1; - } - - while (ptrUSART->GetStatus().tx_busy != 0U); - } - - buf[0] = (uint8_t)ch; - - if (ptrUSART->Send(buf, 1U) != ARM_DRIVER_OK) { - return -1; - } - - while (ptrUSART->GetStatus().tx_busy != 0U); - - return ch; -} - -/** - Put a character to the stdout - - \param[in] ch Character to output - \return The character written, or -1 on write error. -*/ -int stdout_putchar (int ch) { - uint8_t buf[1]; - - if (ch == '\n') { - buf[0] = (uint8_t)'\r'; - - if (ptrUSART->Send(buf, 1U) != ARM_DRIVER_OK) { - return -1; - } - - while (ptrUSART->GetStatus().tx_busy != 0U); - } - - buf[0] = (uint8_t)ch; - - if (ptrUSART->Send(buf, 1U) != ARM_DRIVER_OK) { - return -1; - } - - while (ptrUSART->GetStatus().tx_busy != 0U); - - return ch; -} - -/** - Get a character from the stdio - - \return The next character from the input, or -1 on read error. -*/ -int stdin_getchar (void) { - uint8_t buf[1]; - - if (ptrUSART->Receive(buf, 1U) != ARM_DRIVER_OK) { - return -1; - } - - while (ptrUSART->GetStatus().rx_busy != 0U); - - return (int)buf[0]; -} \ No newline at end of file diff --git a/Alif/DevKit-E8_ETH/SDS.csolution.yml b/Alif/DevKit-E8_ETH/SDS.csolution.yml index ba34b17..83da413 100644 --- a/Alif/DevKit-E8_ETH/SDS.csolution.yml +++ b/Alif/DevKit-E8_ETH/SDS.csolution.yml @@ -17,7 +17,7 @@ solution: packs: - pack: ARM::SDS@^3.1.0-0 - pack: AlifSemiconductor::Ensemble@^2.2.1-0 - - pack: ARM::SSE_320_BSP@1.1.0 + - pack: ARM::SSE_320_BSP@^2.0.0 # List different hardware targets that are used to deploy the solution. target-types: diff --git a/Alif/DevKit-E8_ETH/algorithm/config_app.h b/Alif/DevKit-E8_ETH/algorithm/config_app.h index 03f5f9f..b184603 100644 --- a/Alif/DevKit-E8_ETH/algorithm/config_app.h +++ b/Alif/DevKit-E8_ETH/algorithm/config_app.h @@ -33,9 +33,9 @@ // Activation Buffer Section Name // Define the name of the activation buffer section -// Default: ".bss.activation_buf" +// Default: "ethos_arena" #ifndef ACTIVATION_BUF_SECTION -#define ACTIVATION_BUF_SECTION ".bss.activation_buf" +#define ACTIVATION_BUF_SECTION "ethos_arena" #endif // Activation Buffer Alignment @@ -47,9 +47,9 @@ // NN Model Buffer Section Name // Define the name of the NN model buffer section -// Default: "nn_model" +// Default: "ethos_model" #ifndef NN_MODEL_BUF_SECTION -#define NN_MODEL_BUF_SECTION "nn_model" +#define NN_MODEL_BUF_SECTION "ethos_model" #endif // NN Model Buffer Alignment // Define the NN model buffer alignment in bytes diff --git a/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/Board-U55.clayer.yml b/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/Board-U55.clayer.yml index b033b5d..8d5541b 100644 --- a/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/Board-U55.clayer.yml +++ b/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/Board-U55.clayer.yml @@ -1,6 +1,6 @@ layer: type: Board - description: Board setup for AI/ML with Ethos U55 + description: Base configuration of SSE-300 FVP with Ethos U55 for-board: ARM::V2M-MPS3-SSE-300-FVP for-device: ARM::SSE-300-MPS3 @@ -12,18 +12,18 @@ layer: - STDIN - STDOUT - STDERR - - Heap: 786432 + - Heap: 98304 + consumes: + - CMSIS-RTOS2 define: - CMSIS_target_header: \"Corstone-300.h\" - - ETHOSU55 - CORSTONE300_FVP - - ARM_MODEL_USE_PMU_COUNTERS packs: - pack: ARM::CMSIS - - pack: ARM::CMSIS-Compiler@^2.1.0 - - pack: ARM::ethos-u-core-driver@^1.25.2 + - pack: ARM::CMSIS-Compiler@^2.3.0 + - pack: ARM::CMSIS-Ethos-U@^1.0.0 - pack: ARM::V2M_MPS3_SSE_300_BSP@1.5.0 components: @@ -33,9 +33,9 @@ layer: - component: CMSIS Driver:VIO - component: CMSIS-Compiler:CORE - - component: CMSIS-Compiler:STDERR:Custom - - component: CMSIS-Compiler:STDIN:Custom - - component: CMSIS-Compiler:STDOUT:Custom + - component: CMSIS-Compiler:STDERR:UART&CMSIS + - component: CMSIS-Compiler:STDIN:UART&CMSIS + - component: CMSIS-Compiler:STDOUT:UART&CMSIS - component: Device:Definition - component: Device:Startup&C Startup @@ -46,14 +46,17 @@ layer: - component: Device:Native Driver:UART - component: Machine Learning:NPU Support:Ethos-U Driver&Generic U55 + define: + - ETHOSU_MACS: 256 groups: - group: Board files: - - file: ./main.c - - file: ./main.h - - file: ./ethos_setup.c - - file: ./retarget_stdio.c + - file: main.c + - file: main.h + - file: ethos_setup.c + - file: ethosu_os_rtos2.c + - file: ethosu_dcache.c linker: - - regions: ./regions_SSE-300.h + - regions: RTE/Device/SSE-300-MPS3/regions_SSE-300.h diff --git a/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/Board-U65.clayer.yml b/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/Board-U65.clayer.yml index e0bed61..4cebf52 100644 --- a/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/Board-U65.clayer.yml +++ b/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/Board-U65.clayer.yml @@ -1,6 +1,6 @@ layer: type: Board - description: Board setup for AI/ML with Ethos U65 + description: Base configuration of SSE-300 FVP with Ethos U65 for-board: ARM::V2M-MPS3-SSE-300-FVP for-device: ARM::SSE-300-MPS3 @@ -12,18 +12,18 @@ layer: - STDIN - STDOUT - STDERR - - Heap: 786432 + - Heap: 98304 + consumes: + - CMSIS-RTOS2 define: - CMSIS_target_header: \"Corstone-300.h\" - - ETHOSU65 - CORSTONE300_FVP - - ARM_MODEL_USE_PMU_COUNTERS packs: - pack: ARM::CMSIS - - pack: ARM::CMSIS-Compiler@^2.1.0 - - pack: ARM::ethos-u-core-driver@^1.25.2 + - pack: ARM::CMSIS-Compiler@^2.3.0 + - pack: ARM::CMSIS-Ethos-U@^1.0.0 - pack: ARM::V2M_MPS3_SSE_300_BSP@1.5.0 components: @@ -33,9 +33,9 @@ layer: - component: CMSIS Driver:VIO - component: CMSIS-Compiler:CORE - - component: CMSIS-Compiler:STDERR:Custom - - component: CMSIS-Compiler:STDIN:Custom - - component: CMSIS-Compiler:STDOUT:Custom + - component: CMSIS-Compiler:STDERR:UART&CMSIS + - component: CMSIS-Compiler:STDIN:UART&CMSIS + - component: CMSIS-Compiler:STDOUT:UART&CMSIS - component: Device:Definition - component: Device:Startup&C Startup @@ -46,14 +46,17 @@ layer: - component: Device:Native Driver:UART - component: Machine Learning:NPU Support:Ethos-U Driver&Generic U65 + define: + - ETHOSU_MACS: 256 groups: - group: Board files: - - file: ./main.c - - file: ./main.h - - file: ./ethos_setup.c - - file: ./retarget_stdio.c + - file: main.c + - file: main.h + - file: ethos_setup.c + - file: ethosu_os_rtos2.c + - file: ethosu_dcache.c linker: - - regions: ./regions_SSE-300.h + - regions: RTE/Device/SSE-300-MPS3/regions_SSE-300.h diff --git a/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/Board.clayer.yml b/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/Board.clayer.yml index b7c2fe0..2fa6b04 100644 --- a/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/Board.clayer.yml +++ b/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/Board.clayer.yml @@ -1,6 +1,6 @@ layer: type: Board - description: Board setup for AI/ML + description: Base configuration of SSE-300 FVP for-board: ARM::V2M-MPS3-SSE-300-FVP for-device: ARM::SSE-300-MPS3 @@ -12,16 +12,15 @@ layer: - STDIN - STDOUT - STDERR - - Heap: 786432 + - Heap: 98304 define: - CMSIS_target_header: \"Corstone-300.h\" - CORSTONE300_FVP - - ARM_MODEL_USE_PMU_COUNTERS packs: - pack: ARM::CMSIS - - pack: ARM::CMSIS-Compiler@^2.1.0 + - pack: ARM::CMSIS-Compiler@^2.3.0 - pack: ARM::V2M_MPS3_SSE_300_BSP@1.5.0 components: @@ -31,9 +30,9 @@ layer: - component: CMSIS Driver:VIO - component: CMSIS-Compiler:CORE - - component: CMSIS-Compiler:STDERR:Custom - - component: CMSIS-Compiler:STDIN:Custom - - component: CMSIS-Compiler:STDOUT:Custom + - component: CMSIS-Compiler:STDERR:UART&CMSIS + - component: CMSIS-Compiler:STDIN:UART&CMSIS + - component: CMSIS-Compiler:STDOUT:UART&CMSIS - component: Device:Definition - component: Device:Startup&C Startup @@ -46,9 +45,8 @@ layer: groups: - group: Board files: - - file: ./main.c - - file: ./main.h - - file: ./retarget_stdio.c + - file: main.c + - file: main.h linker: - - regions: ./regions_SSE-300.h + - regions: RTE/Device/SSE-300-MPS3/regions_SSE-300.h diff --git a/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/Corstone-300.h b/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/Corstone-300.h index 8d1a416..4abb85d 100644 --- a/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/Corstone-300.h +++ b/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/Corstone-300.h @@ -1,6 +1,6 @@ -/*--------------------------------------------------------------------------- - * Copyright (c) 2025 Arm Limited (or its affiliates). - * All rights reserved. +/* + * Copyright 2025-2026 Arm Limited and/or its affiliates. + * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may @@ -14,7 +14,7 @@ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. - *---------------------------------------------------------------------------*/ + */ #ifndef CORSTONE_300_H_ #define CORSTONE_300_H_ diff --git a/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/README.md b/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/README.md index 97555a2..4b287fd 100644 --- a/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/README.md +++ b/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/README.md @@ -1,20 +1,30 @@ # Board: Arm V2M-MPS3-SSE-300-FVP -## Board Layer for Corstone-300 FVP +## Board Layers for Corstone-300 FVP -This layer works for: +These layers work for: ```yml board: ARM::V2M-MPS3-SSE-300-FVP device: ARM::SSE-300-MPS3 ``` +Select one layer matching the application's NPU requirements: + +| Layer file | Use in Application +|:---------------------|:------------------------ +| Board.clayer.yml | Without Ethos-U support +| Board-U55.clayer.yml | With Ethos-U55 support +| Board-U65.clayer.yml | With Ethos-U65 support + +Use the corresponding FVP configuration file listed below. + ### System Configuration | System Component | Setting |:------------------------|:---------------------------------- -| Heap | 768 kB (configured in linker file) -| Stack (MSP) | 32 kB (configured in linker file) +| Heap | 96 kB (configured in regions header) +| Stack (MSP) | 4 kB (configured in regions header) ### STDIO mapping @@ -41,4 +51,6 @@ interface for SDS data files using a [Virtual Streaming Interface](https://arm-s | File | Description |:-------------------|:------------- -| fvp_config.txt | Corstone-300 FVP without Ethos-U or with Ethos-U55/U65 +| fvp_config.txt | Corstone-300 FVP without Ethos-U +| fvp_config_u55.txt | Corstone-300 FVP with an Ethos-U55-256 +| fvp_config_u65.txt | Corstone-300 FVP with an Ethos-U65-256 diff --git a/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/RTE/CMSIS-Compiler/stderr_cmsis_uart_config.h b/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/RTE/CMSIS-Compiler/stderr_cmsis_uart_config.h new file mode 100644 index 0000000..d6a30a3 --- /dev/null +++ b/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/RTE/CMSIS-Compiler/stderr_cmsis_uart_config.h @@ -0,0 +1,59 @@ +/*--------------------------------------------------------------------------- + * Copyright (c) 2026 Arm Limited (or its affiliates). + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * -------------------------------------------------------------------------- + * + * Purpose: Configure STDERR to CMSIS-Driver USART retarget implementation + * Revision: V1.0.0 + * + * --------------------------------------------------------------------------*/ + +#ifndef STDERR_CMSIS_UART_CONFIG_H_ +#define STDERR_CMSIS_UART_CONFIG_H_ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// UART STDERR Buffer Size +// UART STDERR buffer is used to store STDERR data before sending it via UART +// Default: 0 (unbuffered) +#ifndef STDERR_UART_BUFFER_SIZE +#define STDERR_UART_BUFFER_SIZE 0 +#endif + +// UART STDERR Buffer Section Name +// Specify the memory section name for UART STDERR buffer +// Default: .stderr_uart_buf +#ifndef STDERR_UART_BUFFER_SECTION +#define STDERR_UART_BUFFER_SECTION ".stderr_uart_buf" +#endif + +// UART STDERR Buffer Alignment +// Define the STDERR buffer alignment in bytes +// Default: 32 +#ifndef STDERR_UART_BUFFER_ALIGNMENT +#define STDERR_UART_BUFFER_ALIGNMENT 32 +#endif + +// Convert LF to CRLF +// If enabled, LF characters are preceded by CR characters on output +// Default: 0 +#ifndef STDERR_CR_LF +#define STDERR_CR_LF 1 +#endif + +#endif /* STDERR_CMSIS_UART_CONFIG_H_ */ diff --git a/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/RTE/CMSIS-Compiler/stderr_cmsis_uart_config.h.base@1.0.0 b/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/RTE/CMSIS-Compiler/stderr_cmsis_uart_config.h.base@1.0.0 new file mode 100644 index 0000000..192648e --- /dev/null +++ b/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/RTE/CMSIS-Compiler/stderr_cmsis_uart_config.h.base@1.0.0 @@ -0,0 +1,59 @@ +/*--------------------------------------------------------------------------- + * Copyright (c) 2026 Arm Limited (or its affiliates). + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * -------------------------------------------------------------------------- + * + * Purpose: Configure STDERR to CMSIS-Driver USART retarget implementation + * Revision: V1.0.0 + * + * --------------------------------------------------------------------------*/ + +#ifndef STDERR_CMSIS_UART_CONFIG_H_ +#define STDERR_CMSIS_UART_CONFIG_H_ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// UART STDERR Buffer Size +// UART STDERR buffer is used to store STDERR data before sending it via UART +// Default: 0 (unbuffered) +#ifndef STDERR_UART_BUFFER_SIZE +#define STDERR_UART_BUFFER_SIZE 0 +#endif + +// UART STDERR Buffer Section Name +// Specify the memory section name for UART STDERR buffer +// Default: .stderr_uart_buf +#ifndef STDERR_UART_BUFFER_SECTION +#define STDERR_UART_BUFFER_SECTION ".stderr_uart_buf" +#endif + +// UART STDERR Buffer Alignment +// Define the STDERR buffer alignment in bytes +// Default: 32 +#ifndef STDERR_UART_BUFFER_ALIGNMENT +#define STDERR_UART_BUFFER_ALIGNMENT 32 +#endif + +// Convert LF to CRLF +// If enabled, LF characters are preceded by CR characters on output +// Default: 0 +#ifndef STDERR_CR_LF +#define STDERR_CR_LF 0 +#endif + +#endif /* STDERR_CMSIS_UART_CONFIG_H_ */ diff --git a/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/RTE/CMSIS-Compiler/stdin_cmsis_uart_config.h b/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/RTE/CMSIS-Compiler/stdin_cmsis_uart_config.h new file mode 100644 index 0000000..bce0ba2 --- /dev/null +++ b/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/RTE/CMSIS-Compiler/stdin_cmsis_uart_config.h @@ -0,0 +1,59 @@ +/*--------------------------------------------------------------------------- + * Copyright (c) 2026 Arm Limited (or its affiliates). + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * -------------------------------------------------------------------------- + * + * Purpose: Configure STDIN to CMSIS-Driver USART retarget implementation + * Revision: V1.0.0 + * + * --------------------------------------------------------------------------*/ + +#ifndef STDIN_CMSIS_UART_CONFIG_H_ +#define STDIN_CMSIS_UART_CONFIG_H_ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// UART STDIN Buffer Size +// UART STDIN buffer is used to store STDIN data received via UART +// Default: 64 +#ifndef STDIN_UART_BUFFER_SIZE +#define STDIN_UART_BUFFER_SIZE 64 +#endif + +// UART STDIN Buffer Section Name +// Specify the memory section name for UART STDIN buffer +// Default: .stdin_uart_buf +#ifndef STDIN_UART_BUFFER_SECTION +#define STDIN_UART_BUFFER_SECTION ".stdin_uart_buf" +#endif + +// UART STDIN Buffer Alignment +// Define the STDIN buffer alignment in bytes +// Default: 32 +#ifndef STDIN_UART_BUFFER_ALIGNMENT +#define STDIN_UART_BUFFER_ALIGNMENT 32 +#endif + +// Echo Input Characters +// If enabled, received characters are echoed to STDOUT +// Default: 0 +#ifndef STDIN_ECHO +#define STDIN_ECHO 0 +#endif + +#endif /* STDIN_CMSIS_UART_CONFIG_H_ */ diff --git a/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/RTE/CMSIS-Compiler/stdin_cmsis_uart_config.h.base@1.0.0 b/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/RTE/CMSIS-Compiler/stdin_cmsis_uart_config.h.base@1.0.0 new file mode 100644 index 0000000..bce0ba2 --- /dev/null +++ b/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/RTE/CMSIS-Compiler/stdin_cmsis_uart_config.h.base@1.0.0 @@ -0,0 +1,59 @@ +/*--------------------------------------------------------------------------- + * Copyright (c) 2026 Arm Limited (or its affiliates). + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * -------------------------------------------------------------------------- + * + * Purpose: Configure STDIN to CMSIS-Driver USART retarget implementation + * Revision: V1.0.0 + * + * --------------------------------------------------------------------------*/ + +#ifndef STDIN_CMSIS_UART_CONFIG_H_ +#define STDIN_CMSIS_UART_CONFIG_H_ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// UART STDIN Buffer Size +// UART STDIN buffer is used to store STDIN data received via UART +// Default: 64 +#ifndef STDIN_UART_BUFFER_SIZE +#define STDIN_UART_BUFFER_SIZE 64 +#endif + +// UART STDIN Buffer Section Name +// Specify the memory section name for UART STDIN buffer +// Default: .stdin_uart_buf +#ifndef STDIN_UART_BUFFER_SECTION +#define STDIN_UART_BUFFER_SECTION ".stdin_uart_buf" +#endif + +// UART STDIN Buffer Alignment +// Define the STDIN buffer alignment in bytes +// Default: 32 +#ifndef STDIN_UART_BUFFER_ALIGNMENT +#define STDIN_UART_BUFFER_ALIGNMENT 32 +#endif + +// Echo Input Characters +// If enabled, received characters are echoed to STDOUT +// Default: 0 +#ifndef STDIN_ECHO +#define STDIN_ECHO 0 +#endif + +#endif /* STDIN_CMSIS_UART_CONFIG_H_ */ diff --git a/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/RTE/CMSIS-Compiler/stdio_cmsis_uart_config.h b/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/RTE/CMSIS-Compiler/stdio_cmsis_uart_config.h new file mode 100644 index 0000000..aeeca61 --- /dev/null +++ b/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/RTE/CMSIS-Compiler/stdio_cmsis_uart_config.h @@ -0,0 +1,52 @@ +/*--------------------------------------------------------------------------- + * Copyright (c) 2026 Arm Limited (or its affiliates). + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * -------------------------------------------------------------------------- + * + * Purpose: STDIO to CMSIS Driver USART Retarget Configuration + * Revision: V1.0.0 + * + * --------------------------------------------------------------------------*/ + +#ifndef STDIO_CMSIS_UART_CONFIG_H_ +#define STDIO_CMSIS_UART_CONFIG_H_ + +#ifdef CMSIS_target_header +#include CMSIS_target_header +#else +#define RETARGET_STDIO_UART 0 +#endif + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// Connect to hardware via Driver_USART# +// Select driver control block for hardware interface +// Default: 0 +#ifndef STDIO_UART_DRIVER +#define STDIO_UART_DRIVER RETARGET_STDIO_UART +#endif + +// UART baudrate +// Specifies the baudrate for UART communication +// Common values: 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 +// Default: 115200 +#ifndef STDIO_UART_BAUDRATE +#define STDIO_UART_BAUDRATE 115200 +#endif + +#endif /* STDIO_CMSIS_UART_CONFIG_H_ */ diff --git a/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/RTE/CMSIS-Compiler/stdio_cmsis_uart_config.h.base@1.0.0 b/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/RTE/CMSIS-Compiler/stdio_cmsis_uart_config.h.base@1.0.0 new file mode 100644 index 0000000..aeeca61 --- /dev/null +++ b/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/RTE/CMSIS-Compiler/stdio_cmsis_uart_config.h.base@1.0.0 @@ -0,0 +1,52 @@ +/*--------------------------------------------------------------------------- + * Copyright (c) 2026 Arm Limited (or its affiliates). + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * -------------------------------------------------------------------------- + * + * Purpose: STDIO to CMSIS Driver USART Retarget Configuration + * Revision: V1.0.0 + * + * --------------------------------------------------------------------------*/ + +#ifndef STDIO_CMSIS_UART_CONFIG_H_ +#define STDIO_CMSIS_UART_CONFIG_H_ + +#ifdef CMSIS_target_header +#include CMSIS_target_header +#else +#define RETARGET_STDIO_UART 0 +#endif + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// Connect to hardware via Driver_USART# +// Select driver control block for hardware interface +// Default: 0 +#ifndef STDIO_UART_DRIVER +#define STDIO_UART_DRIVER RETARGET_STDIO_UART +#endif + +// UART baudrate +// Specifies the baudrate for UART communication +// Common values: 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 +// Default: 115200 +#ifndef STDIO_UART_BAUDRATE +#define STDIO_UART_BAUDRATE 115200 +#endif + +#endif /* STDIO_CMSIS_UART_CONFIG_H_ */ diff --git a/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/RTE/CMSIS-Compiler/stdout_cmsis_uart_config.h b/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/RTE/CMSIS-Compiler/stdout_cmsis_uart_config.h new file mode 100644 index 0000000..3cdc2ae --- /dev/null +++ b/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/RTE/CMSIS-Compiler/stdout_cmsis_uart_config.h @@ -0,0 +1,59 @@ +/*--------------------------------------------------------------------------- + * Copyright (c) 2026 Arm Limited (or its affiliates). + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * -------------------------------------------------------------------------- + * + * Purpose: Configure STDOUT to CMSIS-Driver USART retarget implementation + * Revision: V1.0.0 + * + * --------------------------------------------------------------------------*/ + +#ifndef STDOUT_CMSIS_UART_CONFIG_H_ +#define STDOUT_CMSIS_UART_CONFIG_H_ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// UART STDOUT Buffer Size +// UART STDOUT buffer is used to store STDOUT data before sending it via UART +// Default: 0 (unbuffered) +#ifndef STDOUT_UART_BUFFER_SIZE +#define STDOUT_UART_BUFFER_SIZE 0 +#endif + +// UART STDOUT Buffer Section Name +// Specify the memory section name for UART STDOUT buffer +// Default: .stdout_uart_buf +#ifndef STDOUT_UART_BUFFER_SECTION +#define STDOUT_UART_BUFFER_SECTION ".stdout_uart_buf" +#endif + +// UART STDOUT Buffer Alignment +// Define the buffer alignment in bytes +// Default: 32 +#ifndef STDOUT_UART_BUFFER_ALIGNMENT +#define STDOUT_UART_BUFFER_ALIGNMENT 32 +#endif + +// Convert LF to CRLF +// If enabled, LF characters are preceded by CR characters on output +// Default: 0 +#ifndef STDOUT_CR_LF +#define STDOUT_CR_LF 1 +#endif + +#endif /* STDOUT_CMSIS_UART_CONFIG_H_ */ diff --git a/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/RTE/CMSIS-Compiler/stdout_cmsis_uart_config.h.base@1.0.0 b/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/RTE/CMSIS-Compiler/stdout_cmsis_uart_config.h.base@1.0.0 new file mode 100644 index 0000000..323d217 --- /dev/null +++ b/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/RTE/CMSIS-Compiler/stdout_cmsis_uart_config.h.base@1.0.0 @@ -0,0 +1,59 @@ +/*--------------------------------------------------------------------------- + * Copyright (c) 2026 Arm Limited (or its affiliates). + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * -------------------------------------------------------------------------- + * + * Purpose: Configure STDOUT to CMSIS-Driver USART retarget implementation + * Revision: V1.0.0 + * + * --------------------------------------------------------------------------*/ + +#ifndef STDOUT_CMSIS_UART_CONFIG_H_ +#define STDOUT_CMSIS_UART_CONFIG_H_ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// UART STDOUT Buffer Size +// UART STDOUT buffer is used to store STDOUT data before sending it via UART +// Default: 0 (unbuffered) +#ifndef STDOUT_UART_BUFFER_SIZE +#define STDOUT_UART_BUFFER_SIZE 0 +#endif + +// UART STDOUT Buffer Section Name +// Specify the memory section name for UART STDOUT buffer +// Default: .stdout_uart_buf +#ifndef STDOUT_UART_BUFFER_SECTION +#define STDOUT_UART_BUFFER_SECTION ".stdout_uart_buf" +#endif + +// UART STDOUT Buffer Alignment +// Define the buffer alignment in bytes +// Default: 32 +#ifndef STDOUT_UART_BUFFER_ALIGNMENT +#define STDOUT_UART_BUFFER_ALIGNMENT 32 +#endif + +// Convert LF to CRLF +// If enabled, LF characters are preceded by CR characters on output +// Default: 0 +#ifndef STDOUT_CR_LF +#define STDOUT_CR_LF 0 +#endif + +#endif /* STDOUT_CMSIS_UART_CONFIG_H_ */ diff --git a/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/RTE/Device/SSE-300-MPS3/ac6_linker_script.sct.src b/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/RTE/Device/SSE-300-MPS3/ac6_linker_script.sct.src index 370d6b3..3576f33 100644 --- a/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/RTE/Device/SSE-300-MPS3/ac6_linker_script.sct.src +++ b/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/RTE/Device/SSE-300-MPS3/ac6_linker_script.sct.src @@ -34,7 +34,6 @@ LR_ROM0 __ROM0_BASE __ROM0_SIZE { ER_ROM0 __ROM0_BASE __ROM0_SIZE { *.o (RESET, +First) *(InRoot$$Sections) - *(+RO +XO) } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) @@ -42,6 +41,13 @@ LR_ROM0 __ROM0_BASE __ROM0_SIZE { *(Veneer$$CMSE) } #endif +} + +LR_ROM1 __ROM1_BASE __ROM1_SIZE { + + ER_ROM1 __ROM1_BASE __ROM1_SIZE { + *(+RO +XO) + } RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE) { *.o(.bss.noinit) @@ -67,11 +73,8 @@ LR_ROM0 __ROM0_BASE __ROM0_SIZE { #if __RAM1_SIZE > 0 RW_RAM1 __RAM1_BASE __RAM1_SIZE { - ; Ethos-U Cache Area - *.o (*ethos_cache_buf) - - ; NN Activation Tensor (activation buffer / tensor arena) - *.o (*activation_buf) + ; Ethos-U writable area + *.o (ethos_arena) .ANY (+RW +ZI) } @@ -90,19 +93,11 @@ LR_ROM0 __ROM0_BASE __ROM0_SIZE { #endif } -#if __ROM1_SIZE > 0 -LR_ROM1 __ROM1_BASE __ROM1_SIZE { - ER_ROM1 +0 __ROM1_SIZE { - .ANY (+RO +XO) - } -} -#endif - #if __ROM2_SIZE > 0 LR_ROM2 __ROM2_BASE __ROM2_SIZE { ER_ROM2 +0 __ROM2_SIZE { - ; NN Model Binary Representation - *.o (nn_model) + ; Ethos-U model, command stream and constants + *.o (ethos_model) .ANY (+RO +XO) } diff --git a/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/RTE/Device/SSE-300-MPS3/clang_linker_script.ld.src b/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/RTE/Device/SSE-300-MPS3/clang_linker_script.ld.src new file mode 100644 index 0000000..a64b505 --- /dev/null +++ b/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/RTE/Device/SSE-300-MPS3/clang_linker_script.ld.src @@ -0,0 +1,406 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright © 2019 Keith Packard + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED + * OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* ---------------------------------------------------------------------------- + Stack seal size definition + *----------------------------------------------------------------------------*/ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define __STACKSEAL_SIZE ( 8 ) +#else +#define __STACKSEAL_SIZE ( 0 ) +#endif + +/* ---------------------------------------------------------------------------- + Memory definition + *----------------------------------------------------------------------------*/ +MEMORY +{ + ROM0 (rx!w) : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE +#if __ROM1_SIZE > 0 + ROM1 (rx!w) : ORIGIN = __ROM1_BASE, LENGTH = __ROM1_SIZE +#endif +#if __ROM2_SIZE > 0 + ROM2 (rx!w) : ORIGIN = __ROM2_BASE, LENGTH = __ROM2_SIZE +#endif +#if __ROM3_SIZE > 0 + ROM3 (rx!w) : ORIGIN = __ROM3_BASE, LENGTH = __ROM3_SIZE +#endif + + RAM0 (w!rx) : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE +#if __RAM1_SIZE > 0 + RAM1 (w!rx) : ORIGIN = __RAM1_BASE, LENGTH = __RAM1_SIZE +#endif +#if __RAM2_SIZE > 0 + RAM2 (w!rx) : ORIGIN = __RAM2_BASE, LENGTH = __RAM2_SIZE +#endif +#if __RAM3_SIZE > 0 + RAM3 (w!rx) : ORIGIN = __RAM3_BASE, LENGTH = __RAM3_SIZE +#endif +} + +ENTRY(Reset_Handler) + +PHDRS +{ + boot PT_LOAD; + text PT_LOAD; + ram PT_LOAD; + ram_init PT_LOAD; + tls PT_TLS; +#if __RAM1_SIZE > 0 + ethos_ram PT_LOAD; +#endif +#if __ROM2_SIZE > 0 + ethos_model PT_LOAD; +#endif +} + +SECTIONS +{ + .init : { + KEEP (*(.vectors)) + + /* Disable by default + * + * *.init.enter contains a vector table provided by picolibc, + * whereas CMSIS already provides a vector table via .vectors + */ + /* + KEEP (*(.text.init.enter)) + KEEP (*(.data.init.enter)) + */ + + KEEP (*(SORT_BY_NAME(.init) SORT_BY_NAME(.init.*))) + } >ROM0 AT>ROM0 :boot + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + .veneers : + { + . = ALIGN(32); + KEEP(*(.gnu.sgstubs)) + } > ROM0 AT>ROM0 :boot +#endif + + .text : { + + /* code */ + *(.text.unlikely .text.unlikely.*) + *(.text.startup .text.startup.*) + *(.text .text.* .opd .opd.*) + *(.gnu.linkonce.t.*) + KEEP (*(.fini .fini.*)) + __text_end = .; + + PROVIDE (__etext = __text_end); + PROVIDE (_etext = __text_end); + PROVIDE (etext = __text_end); + + /* read-only data */ + *(.rdata) + *(.rodata .rodata.*) + *(.gnu.linkonce.r.*) + + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + *(.data.rel.ro .data.rel.ro.*) + *(.got .got.*) + + /* Need to pre-align so that the symbols come after padding */ + . = ALIGN(8); + + /* lists of constructors and destructors */ + PROVIDE_HIDDEN ( __bothinit_array_start = . ); + PROVIDE_HIDDEN ( __preinit_array_start = . ); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN ( __preinit_array_end = . ); + + PROVIDE_HIDDEN ( __init_array_start = . ); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array .ctors)) + PROVIDE_HIDDEN ( __init_array_end = . ); + PROVIDE_HIDDEN ( __bothinit_array_end = . ); + + PROVIDE_HIDDEN ( __fini_array_start = . ); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array .dtors)) + PROVIDE_HIDDEN ( __fini_array_end = . ); + + } >ROM1 AT>ROM1 :text + + .toc : { + *(.toc .toc.*) + } >ROM1 AT>ROM1 :text + + /* additional sections when compiling with C++ exception support */ + + .except_ordered : { + *(.gcc_except_table *.gcc_except_table.*) + KEEP (*(.eh_frame .eh_frame.*)) + *(.ARM.extab* .gnu.linkonce.armextab.*) + } >ROM1 AT>ROM1 :text + + .except_unordered : { + . = ALIGN(8); + + PROVIDE(__exidx_start = .); + *(.ARM.exidx*) + PROVIDE(__exidx_end = .); + } >ROM1 AT>ROM1 :text + + + /* + * Data values which are preserved across reset + */ + .preserve (NOLOAD) : { + PROVIDE(__preserve_start__ = .); + KEEP(*(SORT_BY_NAME(.preserve.*))) + KEEP(*(.preserve)) + PROVIDE(__preserve_end__ = .); + } >RAM0 AT>RAM0 :ram + + .data : { + *(.data .data.*) + *(.gnu.linkonce.d.*) + + /* Need to pre-align so that the symbols come after padding */ + . = ALIGN(8); + + PROVIDE( __global_pointer$ = . + 0x800 ); + *(.sdata .sdata.* .sdata2.*) + *(.gnu.linkonce.s.*) + } >RAM0 AT>ROM1 :ram_init + PROVIDE(__data_start = ADDR(.data)); + PROVIDE(__data_source = LOADADDR(.data)); + + /* Thread local initialized data. This gets + * space allocated as it is expected to be placed + * in ram to be used as a template for TLS data blocks + * allocated at runtime. We're slightly abusing that + * by placing the data in flash where it will be copied + * into the allocate ram addresses by the existing + * data initialization code in crt0 + */ + .tdata : { + *(.tdata .tdata.* .gnu.linkonce.td.*) + PROVIDE(__data_end = .); + PROVIDE(__tdata_end = .); + } >RAM0 AT>ROM1 :tls :ram_init + PROVIDE( __tls_base = ADDR(.tdata)); + PROVIDE( __tdata_start = ADDR(.tdata)); + PROVIDE( __tdata_source = LOADADDR(.tdata) ); + PROVIDE( __tdata_source_end = LOADADDR(.tdata) + SIZEOF(.tdata) ); + PROVIDE( __data_source_end = __tdata_source_end ); + PROVIDE( __tdata_size = SIZEOF(.tdata) ); + PROVIDE( __tls_align = MAX(ALIGNOF(.tdata),ALIGNOF(.tbss)) ); + + PROVIDE( __edata = __data_end ); + PROVIDE( _edata = __data_end ); + PROVIDE( edata = __data_end ); + PROVIDE( __data_size = __data_end - __data_start ); + PROVIDE( __data_source_size = __data_source_end - __data_source ); + + .tbss (NOLOAD) : { + *(.tbss .tbss.* .gnu.linkonce.tb.*) + *(.tcommon) + PROVIDE( __tls_end = . ); + PROVIDE( __tbss_end = . ); + } >RAM0 AT>RAM0 :tls :ram + PROVIDE( __bss_start = ADDR(.tbss)); + PROVIDE( __tbss_start = ADDR(.tbss)); + PROVIDE( __tbss_offset = ADDR(.tbss) - ADDR(.tdata) ); + PROVIDE( __tbss_size = SIZEOF(.tbss) ); + PROVIDE( __tls_size = __tls_end - __tls_base ); + PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) ); + PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) ); + PROVIDE( __arm64_tls_tcb_offset = MAX(16, __tls_align) ); + + /* + * The linker special cases .tbss segments which are + * identified as segments which are not loaded and are + * thread_local. + * + * For these segments, the linker does not advance 'dot' + * across them. We actually need memory allocated for tbss, + * so we create a special segment here just to make room + */ + /* + .tbss_space (NOLOAD) : { + . = ADDR(.tbss); + . = . + SIZEOF(.tbss); + } >RAM0 AT>RAM0 :ram + */ + + .bss (NOLOAD) : { + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + + /* Align the end of this section, so next can start on aligned address */ + . = ALIGN(8); + __bss_end = .; + } >RAM0 AT>RAM0 :ram + PROVIDE( __non_tls_bss_start = ADDR(.bss) ); + PROVIDE( __bss_size = __bss_end - __bss_start ); + + /* This section contains data that is not initialized during load, + or during the application's initialization sequence. */ + .noinit (NOLOAD) : { + __noinit_start__ = .; + *(.noinit) + *(.noinit.*) + + /* Align the end of this section, so next (heap) can start on aligned address */ + . = ALIGN(8); + __noinit_end__ = .; + } >RAM0 AT>RAM0 :ram + + PROVIDE( __end = . ); + PROVIDE( _end = . ); + PROVIDE( end = . ); + + /* Make the rest of memory available for heap storage */ + PROVIDE (__heap_start = __end); +#ifdef __HEAP_SIZE + PROVIDE (__heap_end = __heap_start + __HEAP_SIZE); + PROVIDE (__heap_size = __HEAP_SIZE); +#else + PROVIDE (__heap_end = __stack - __STACK_SIZE); + PROVIDE (__heap_size = __heap_end - __heap_start); +#endif + .heap (NOLOAD) : { + . += __heap_size; + } >RAM0 :ram + + /* Define a stack region to make sure it fits in memory */ + PROVIDE(__stack = ORIGIN(RAM0) + LENGTH(RAM0) - __STACKSEAL_SIZE); + PROVIDE(__stack_limit = __stack - __STACK_SIZE); + .stack (__stack_limit) (NOLOAD) : { + . += __STACK_SIZE; + } >RAM0 :ram + +#if __STACKSEAL_SIZE > 0 + PROVIDE(__stack_seal = __stack); + .stackseal (__stack) (NOLOAD) : + { + . += __STACKSEAL_SIZE; + } >RAM0 :ram +#endif + + /* Ethos-U writable area */ +#if __RAM1_SIZE > 0 + .ethos_arena (NOLOAD) : ALIGN(32) { + *(ethos_arena) + } >RAM1 AT>RAM1 :ethos_ram +#endif + + /* Ethos-U model, command stream and constants */ +#if __ROM2_SIZE > 0 + .ethos_model : ALIGN(32) { + *(ethos_model) + } >ROM2 AT>ROM2 :ethos_model +#endif + + /* Throw away C++ exception handling information */ + + /* + + /DISCARD/ : { + *(.note .note.*) + *(.eh_frame .eh_frame.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + *(.ARM.exidx*) + } + + */ + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .gnu.build.attributes : { *(.gnu.build.attributes .gnu.build.attributes.*) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1. */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions. */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2. */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2. */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line .debug_line.* .debug_line_end) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions. */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + /* DWARF 3. */ + .debug_pubtypes 0 : { *(.debug_pubtypes) } + .debug_ranges 0 : { *(.debug_ranges) } + /* DWARF 5. */ + .debug_addr 0 : { *(.debug_addr) } + .debug_line_str 0 : { *(.debug_line_str) } + .debug_loclists 0 : { *(.debug_loclists) } + .debug_macro 0 : { *(.debug_macro) } + .debug_names 0 : { *(.debug_names) } + .debug_rnglists 0 : { *(.debug_rnglists) } + .debug_str_offsets 0 : { *(.debug_str_offsets) } + .debug_sup 0 : { *(.debug_sup) } + .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) } +} +/* + * Check that sections that are copied from flash to RAM have matching + * padding, so that a single memcpy() of __data_size copies the correct bytes. + */ +ASSERT( __data_size == __data_source_size, + "ERROR: .data/.tdata flash size does not match RAM size"); diff --git a/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/RTE/Device/SSE-300-MPS3/gcc_linker_script.ld.src b/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/RTE/Device/SSE-300-MPS3/gcc_linker_script.ld.src index 2e2ef6f..9f6f1a0 100644 --- a/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/RTE/Device/SSE-300-MPS3/gcc_linker_script.ld.src +++ b/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/RTE/Device/SSE-300-MPS3/gcc_linker_script.ld.src @@ -318,8 +318,7 @@ SECTIONS .cache (NOLOAD): { . = ALIGN(32); - *(*ethos_cache_buf) /* Ethos-U Cache Area */ - *(*activation_buf) /* NN Activation Tensor (activation buffer / tensor arena) */ + *(ethos_arena) /* Ethos-U writable area */ } > RAM1 /* Initialized buffers in fast access RAM */ @@ -331,7 +330,7 @@ SECTIONS .rom2 : { - *(*nn_model) /* NN Model Binary Representation */ + *(ethos_model) /* Ethos-U model, command stream and constants */ } > ROM2 .rom3 : diff --git a/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/RTE/Device/SSE-300-MPS3/iar_linker_script.icf.src b/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/RTE/Device/SSE-300-MPS3/iar_linker_script.icf.src index ea02d53..7d05a92 100644 --- a/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/RTE/Device/SSE-300-MPS3/iar_linker_script.icf.src +++ b/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/RTE/Device/SSE-300-MPS3/iar_linker_script.icf.src @@ -42,8 +42,6 @@ define memory mem with size = 4G; define region ROM3_region = []; #endif -define region ROM_region = ROM0_region | ROM1_region | ROM2_region | ROM3_region; - #if __RAM0_SIZE > 0 define region RAM0_region = mem:[from __RAM0_BASE to (__RAM0_BASE+__RAM0_SIZE-1)]; #else @@ -68,8 +66,6 @@ define region ROM_region = ROM0_region | ROM1_region | ROM2_region | ROM3_regio define region RAM3_region = []; #endif -define region RAM_region = RAM0_region | RAM1_region | RAM2_region | RAM3_region; - do not initialize { section .noinit }; initialize by copy { readwrite }; if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) @@ -80,15 +76,37 @@ if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) place at address mem:__ROM0_BASE { readonly section .intvec }; -if (!isempty(ROM_region)) +if (!isempty(ROM1_region)) { - place in ROM_region { readonly }; + place in ROM1_region { readonly }; } -if (!isempty(RAM_region)) +if (!isempty(RAM0_region)) { define block CSTACK with alignment = 8, size = __STACK_SIZE { }; define block PROC_STACK with alignment = 8, size = 0 { }; define block HEAP with alignment = 8, size = __HEAP_SIZE { }; - place in RAM_region { readwrite, block CSTACK, block PROC_STACK, block HEAP }; + place in RAM0_region { readwrite, block PROC_STACK, block HEAP }; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + /* Reserve the stack seal immediately above the stack. */ + define block STACKSEAL with alignment = 8, size = 8 { }; + define block CSTACK_WITH_SEAL with fixed order { block CSTACK, block STACKSEAL }; + place at end of RAM0_region { block CSTACK_WITH_SEAL }; +#else + place at end of RAM0_region { block CSTACK }; +#endif } + +/* Ethos-U writable area */ +#if __RAM1_SIZE > 0 + do not initialize { section ethos_arena }; + define block ETHOS_ARENA with alignment = 32 + { section ethos_arena }; + place in RAM1_region { block ETHOS_ARENA }; +#endif + +/* Ethos-U model, command stream and constants */ +#if __ROM2_SIZE > 0 + define block ETHOS_MODEL with alignment = 32 { readonly section ethos_model }; + place in ROM2_region { block ETHOS_MODEL }; +#endif diff --git a/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/regions_SSE-300.h b/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/RTE/Device/SSE-300-MPS3/regions_SSE-300.h similarity index 100% rename from ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/regions_SSE-300.h rename to ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/RTE/Device/SSE-300-MPS3/regions_SSE-300.h diff --git a/Alif/AppKit-E7_USB/Board/Corstone-300/sse300_memmap_ns.h b/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/RTE/Device/SSE-300-MPS3/sse300_memmap_ns.h similarity index 97% rename from Alif/AppKit-E7_USB/Board/Corstone-300/sse300_memmap_ns.h rename to ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/RTE/Device/SSE-300-MPS3/sse300_memmap_ns.h index d15a465..811a1c6 100644 --- a/Alif/AppKit-E7_USB/Board/Corstone-300/sse300_memmap_ns.h +++ b/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/RTE/Device/SSE-300-MPS3/sse300_memmap_ns.h @@ -57,10 +57,10 @@ #define SRAM_VM1_NS_LIMIT (SRAM_VM1_NS_BASE + SRAM_VM1_NS_SIZE - 1) /*---------------------------------------------------------------------------*/ -/* Secure QSPI Flash Regions */ +/* Non-Secure QSPI Flash Regions */ /*---------------------------------------------------------------------------*/ -/* QSPI Flash - Secure */ +/* QSPI Flash - Non-Secure */ #define QSPI_FLASH_NS_BASE 0x28000000 #define QSPI_FLASH_NS_SIZE 0x00800000 /* 8MB */ #define QSPI_FLASH_NS_LIMIT (QSPI_FLASH_NS_BASE + QSPI_FLASH_NS_SIZE - 1) diff --git a/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/sse300_memmap_s.h b/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/RTE/Device/SSE-300-MPS3/sse300_memmap_s.h similarity index 100% rename from ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/sse300_memmap_s.h rename to ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/RTE/Device/SSE-300-MPS3/sse300_memmap_s.h diff --git a/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/ethos_setup.c b/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/ethos_setup.c index f154c77..d4033b3 100644 --- a/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/ethos_setup.c +++ b/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/ethos_setup.c @@ -1,5 +1,5 @@ -/*--------------------------------------------------------------------------- - * Copyright (c) 2025 Arm Limited (or its affiliates). All rights reserved. +/* + * Copyright 2025-2026 Arm Limited and/or its affiliates. * * SPDX-License-Identifier: Apache-2.0 * @@ -14,7 +14,7 @@ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. - *---------------------------------------------------------------------------*/ + */ #include @@ -26,18 +26,18 @@ #if defined(ETHOSU65) || defined(ETHOSU85) /* Define Ethos-U NPU cache buffer size */ -#ifndef ETHOS_CACHE_BUF_SIZE -#define ETHOS_CACHE_BUF_SIZE 393216 +#ifndef ETHOS_CACHE_SIZE +#define ETHOS_CACHE_SIZE 0 #endif /* Define Ethos-U cache buffer alignment */ -#ifndef ETHOS_CACHE_BUF_ALIGNMENT -#define ETHOS_CACHE_BUF_ALIGNMENT 32 +#ifndef ETHOS_CACHE_ALIGNMENT +#define ETHOS_CACHE_ALIGNMENT 32 #endif /* Define Ethos-U NPU cache buffer attributes */ -#ifndef ETHOS_CACHE_BUF_ATTRIBUTES -#define ETHOS_CACHE_BUF_ATTRIBUTES __attribute__((section("ethos_cache_buf"), aligned(ETHOS_CACHE_BUF_ALIGNMENT))) +#ifndef ETHOS_CACHE_ATTRIBUTES +#define ETHOS_CACHE_ATTRIBUTES __attribute__((section("ethos_cache"), aligned(ETHOS_CACHE_ALIGNMENT))) #endif #endif @@ -54,8 +54,9 @@ /* Ethos NPU driver instance. */ static struct ethosu_driver EthosDriver; -#if defined(ETHOSU65) || defined(ETHOSU85) -static uint8_t ethos_cache[ETHOS_CACHE_BUF_SIZE] ETHOS_CACHE_BUF_ATTRIBUTES; +#if (defined(ETHOSU65) || defined(ETHOSU85)) && (ETHOS_CACHE_SIZE > 0) +/* Ethos-U NPU cache buffer */ +static uint8_t ethos_cache_buf[ETHOS_CACHE_SIZE] ETHOS_CACHE_ATTRIBUTES; #endif /* @@ -76,9 +77,9 @@ void ethos_setup (void) { /* Initialize Ethos-U NPU driver. */ rval = ethosu_init(&EthosDriver, /* Ethos-U device driver */ ethos_base_addr, /* Ethos-U base address */ - #if defined(ETHOSU65) || defined(ETHOSU85) - ethos_cache, /* Cache memory pointer */ - sizeof(ethos_cache), /* Cache memory size */ + #if (defined(ETHOSU65) || defined(ETHOSU85)) && (ETHOS_CACHE_SIZE > 0) + ethos_cache_buf, /* Cache memory pointer */ + sizeof(ethos_cache_buf), /* Cache memory size */ #else 0, /* Cache memory pointer */ 0, /* Cache memory size */ diff --git a/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/ethosu_dcache.c b/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/ethosu_dcache.c new file mode 100644 index 0000000..015a9d1 --- /dev/null +++ b/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/ethosu_dcache.c @@ -0,0 +1,78 @@ +/* + * Copyright 2026 Arm Limited and/or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include + +#include "ethosu_driver.h" + +/** + \brief Cleans data-cache contents associated with buffers accessed by the NPU. + + Ensures that CPU writes to cacheable buffers are committed to memory before + the NPU starts accessing them. Non-cacheable buffers require no cache clean, + but the function ensures that all preceding memory accesses have completed + before it returns. + + \param[in] base_addr Array of buffer base addresses. + \param[in] base_addr_size Array containing the size, in bytes, of each buffer. + \param[in] num_base_addr Number of entries in the address and size arrays. +*/ +void ethosu_flush_dcache(const uint64_t *base_addr, const size_t *base_addr_size, int num_base_addr) { + + for (int i = 0; i < num_base_addr; i++) { + if ((base_addr[i] & 0x1F) != 0) { + /* Base address must be cache line aligned (32 bytes) */ + // ... + return; + } + + /* Flush data-cache for current buffer */ + // ... + // 32-bit system must cast base_addr to uint32_t* to avoid sign expansion + // CleanDCache((uint32_t *)(uint32_t)base_addr[i], base_addr_size[i]); + } +} + +/** + \brief Invalidates data-cache contents associated with buffers accessed by the NPU. + + Ensures that subsequent CPU reads observe data written by the NPU. Dirty + cache lines may be cleaned before invalidation to preserve pending CPU + writes. For non-cacheable buffers, no cache invalidation is required, + but the function ensures that all preceding memory accesses have completed + before it returns. + + \param[in] base_addr Array of buffer base addresses. + \param[in] base_addr_size Array containing the size, in bytes, of each buffer. + \param[in] num_base_addr Number of entries in the address and size arrays. +*/ +void ethosu_invalidate_dcache(const uint64_t *base_addr, const size_t *base_addr_size, int num_base_addr) { + + for (int i = 0; i < num_base_addr; i++) { + if ((base_addr[i] & 0x1F) != 0) { + /* Base address must be cache line aligned (32 bytes) */ + // ... + return; + } + + /* Invalidate data-cache for current buffer */ + // ... + // 32-bit system must cast base_addr to uint32_t* to avoid sign expansion + // InvalidateDCache((uint32_t *)(uint32_t)base_addr[i], base_addr_size[i]); + } +} diff --git a/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/ethosu_os_rtos2.c b/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/ethosu_os_rtos2.c new file mode 100644 index 0000000..fdab39b --- /dev/null +++ b/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/ethosu_os_rtos2.c @@ -0,0 +1,141 @@ +/* + * Copyright 2026 Arm Limited and/or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ethosu_driver.h" +#include "cmsis_os2.h" + +/* Maximum number of Ethos-U instances. */ +/* Used as maximum semaphore count in ethosu_semaphore_create. */ +#ifndef ETHOSU_MAX_INSTANCES +#define ETHOSU_MAX_INSTANCES 2 +#endif + +/** + \brief Create a mutex object. + \return Pointer to a mutex object. +*/ +void *ethosu_mutex_create(void) { + osMutexId_t mutex_id = osMutexNew(NULL); + return (void *) mutex_id; +} + +/** + \brief Destroy a mutex object. + \param[in] mutex mutex object. +*/ +void ethosu_mutex_destroy(void *mutex) { + osMutexId_t mutex_id = (osMutexId_t) mutex; + osMutexDelete(mutex_id); +} + +/** + \brief Lock a mutex. + \param[in] mutex mutex object. + \return 0 on success, else negative error codes +*/ +int ethosu_mutex_lock(void *mutex) { + osMutexId_t mutex_id = (osMutexId_t) mutex; + osStatus_t status; + int rval; + + status = osMutexAcquire(mutex_id, osWaitForever); + if (status == osOK) { + rval = 0; + } else { + rval = -1; + } + return rval; +} + +/** + \brief Unlock a mutex. + \param[in] mutex mutex object. + \return 0 on success, else negative error codes +*/ +int ethosu_mutex_unlock(void *mutex) { + osMutexId_t mutex_id = (osMutexId_t) mutex; + osStatus_t status; + int rval; + + status = osMutexRelease(mutex_id); + if (status == osOK) { + rval = 0; + } else { + rval = -1; + } + return rval; +} + +/** + \brief Create a semaphore object. + \return Pointer to a semaphore object. +*/ +void *ethosu_semaphore_create(void) { + osSemaphoreId_t sem_id; + + sem_id = osSemaphoreNew(ETHOSU_MAX_INSTANCES, 0U, NULL); + return (void *) sem_id; +} + +/** + \brief Destroy a semaphore object. + \param[in] sem semaphore object. +*/ +void ethosu_semaphore_destroy(void *sem) { + osSemaphoreId_t sem_id = (osSemaphoreId_t) sem; + osSemaphoreDelete(sem_id); +} + +/** + \brief Take a semaphore object with timeout. + \param[in] sem semaphore object. + \param[in] timeout timeout value in ticks. + \return 0 on success, else negative error codes +*/ +int ethosu_semaphore_take(void *sem, uint64_t timeout) { + osSemaphoreId_t sem_id = (osSemaphoreId_t) sem; + osStatus_t status; + int rval; + + status = osSemaphoreAcquire(sem_id, timeout); + if (status == osOK) { + rval = 0; + } else { + rval = -1; + } + return rval; +} + +/** + \brief Give a semaphore object. + \param[in] sem semaphore object. + \return 0 on success, else negative error codes +*/ +int ethosu_semaphore_give(void *sem) { + osSemaphoreId_t sem_id = (osSemaphoreId_t) sem; + osStatus_t status; + int rval; + + status = osSemaphoreRelease(sem_id); + if (status == osOK) { + rval = 0; + } else { + rval = -1; + } + return rval; +} diff --git a/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/fvp_config.txt b/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/fvp_config.txt index e818f72..c21ae24 100644 --- a/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/fvp_config.txt +++ b/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/fvp_config.txt @@ -1,7 +1,6 @@ # Parameters: # instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] #------------------------------------------------------------------------------ -ethosu.num_macs=256 # (int , init-time) default = '0x100' : Number of 8x8 MACs performed per cycle (32, 64, 128, or 256). mps3_board.telnetterminal0.quiet=1 # (bool , init-time) default = '0' : Avoid output on stdout/stderr mps3_board.telnetterminal0.start_telnet=0 # (bool , init-time) default = '1' : Start telnet if nothing connected mps3_board.telnetterminal1.quiet=1 # (bool , init-time) default = '0' : Avoid output on stdout/stderr diff --git a/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/fvp_config_u55.txt b/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/fvp_config_u55.txt new file mode 100644 index 0000000..ab75990 --- /dev/null +++ b/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/fvp_config_u55.txt @@ -0,0 +1,18 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +ethosu.num_macs=256 # (int , init-time) default = '0x100' : Number of 8x8 MACs performed per cycle (32, 64, 128, or 256). +mps3_board.telnetterminal0.quiet=1 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +mps3_board.telnetterminal0.start_telnet=0 # (bool , init-time) default = '1' : Start telnet if nothing connected +mps3_board.telnetterminal1.quiet=1 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +mps3_board.telnetterminal1.start_telnet=0 # (bool , init-time) default = '1' : Start telnet if nothing connected +mps3_board.telnetterminal2.quiet=1 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +mps3_board.telnetterminal2.start_telnet=0 # (bool , init-time) default = '1' : Start telnet if nothing connected +mps3_board.telnetterminal5.quiet=1 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +mps3_board.telnetterminal5.start_telnet=0 # (bool , init-time) default = '1' : Start telnet if nothing connected +mps3_board.uart0.out_file=- # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) +mps3_board.uart0.shutdown_on_eot=1 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) +mps3_board.visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation +#------------------------------------------------------------------------------ + +mps3_board.v_path=./Board/Corstone-300/vsi/python/ # Python VSI and VIO scripts diff --git a/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/fvp_config_u65.txt b/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/fvp_config_u65.txt new file mode 100644 index 0000000..ab75990 --- /dev/null +++ b/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/fvp_config_u65.txt @@ -0,0 +1,18 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +ethosu.num_macs=256 # (int , init-time) default = '0x100' : Number of 8x8 MACs performed per cycle (32, 64, 128, or 256). +mps3_board.telnetterminal0.quiet=1 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +mps3_board.telnetterminal0.start_telnet=0 # (bool , init-time) default = '1' : Start telnet if nothing connected +mps3_board.telnetterminal1.quiet=1 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +mps3_board.telnetterminal1.start_telnet=0 # (bool , init-time) default = '1' : Start telnet if nothing connected +mps3_board.telnetterminal2.quiet=1 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +mps3_board.telnetterminal2.start_telnet=0 # (bool , init-time) default = '1' : Start telnet if nothing connected +mps3_board.telnetterminal5.quiet=1 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +mps3_board.telnetterminal5.start_telnet=0 # (bool , init-time) default = '1' : Start telnet if nothing connected +mps3_board.uart0.out_file=- # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) +mps3_board.uart0.shutdown_on_eot=1 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) +mps3_board.visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation +#------------------------------------------------------------------------------ + +mps3_board.v_path=./Board/Corstone-300/vsi/python/ # Python VSI and VIO scripts diff --git a/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/main.c b/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/main.c index 69b3485..009aec0 100644 --- a/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/main.c +++ b/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/main.c @@ -1,5 +1,5 @@ -/*--------------------------------------------------------------------------- - * Copyright (c) 2024 Arm Limited (or its affiliates). All rights reserved. +/* + * Copyright 2024-2026 Arm Limited and/or its affiliates. * * SPDX-License-Identifier: Apache-2.0 * @@ -14,7 +14,7 @@ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. - *---------------------------------------------------------------------------*/ + */ #include "RTE_Components.h" #include CMSIS_device_header diff --git a/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/main.h b/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/main.h index 6e2048e..2b576ad 100644 --- a/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/main.h +++ b/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/main.h @@ -1,6 +1,6 @@ -/*--------------------------------------------------------------------------- - * Copyright (c) 2020-2025 Arm Limited (or its affiliates). - * All rights reserved. +/* + * Copyright 2020-2026 Arm Limited and/or its affiliates. + * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may @@ -14,7 +14,7 @@ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. - *---------------------------------------------------------------------------*/ + */ #ifndef MAIN_H__ #define MAIN_H__ diff --git a/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/retarget_stdio.c b/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/retarget_stdio.c deleted file mode 100644 index f553eed..0000000 --- a/ST/B-U585I-IOT02A/KeywordSpotting/Board/Corstone-300/retarget_stdio.c +++ /dev/null @@ -1,161 +0,0 @@ -/*--------------------------------------------------------------------------- - * Copyright (c) 2025 Arm Limited (or its affiliates). - * All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * Name: retarget_stdio.c - * Purpose: Retarget stdio to CMSIS UART - * - *---------------------------------------------------------------------------*/ - -#ifdef CMSIS_target_header -#include CMSIS_target_header -#else -#include "Driver_USART.h" -#endif - -#ifndef RETARGET_STDIO_UART -#error "RETARGET_STDIO_UART not defined!" -#endif - -/* Compile-time configuration */ -#ifndef UART_BAUDRATE -#define UART_BAUDRATE 115200 -#endif - -/* References to the external retarget functions */ -extern int stdio_init (void); -extern int stderr_putchar (int ch); -extern int stdout_putchar (int ch); -extern int stdin_getchar (void); - -/* Reference to the underlying USART driver */ -#ifndef CMSIS_target_header -extern ARM_DRIVER_USART ARM_Driver_USART_(RETARGET_STDIO_UART); -#endif -#define ptrUSART (&ARM_Driver_USART_(RETARGET_STDIO_UART)) - -/** - Initialize stdio - - \return 0 on success, or -1 on error. -*/ -int stdio_init (void) { - - if (ptrUSART->Initialize(NULL) != ARM_DRIVER_OK) { - return -1; - } - - if (ptrUSART->PowerControl(ARM_POWER_FULL) != ARM_DRIVER_OK) { - return -1; - } - - if (ptrUSART->Control(ARM_USART_MODE_ASYNCHRONOUS | - ARM_USART_DATA_BITS_8 | - ARM_USART_PARITY_NONE | - ARM_USART_STOP_BITS_1 | - ARM_USART_FLOW_CONTROL_NONE, - UART_BAUDRATE) != ARM_DRIVER_OK) { - return -1; - } - - if (ptrUSART->Control(ARM_USART_CONTROL_RX, 1U) != ARM_DRIVER_OK) { - return -1; - } - - if (ptrUSART->Control(ARM_USART_CONTROL_TX, 1U) != ARM_DRIVER_OK) { - return -1; - } - - return 0; -} - -/** - Put a character to the stderr - - \param[in] ch Character to output - \return The character written, or -1 on write error. -*/ -int stderr_putchar (int ch) { - uint8_t buf[1]; - - if (ch == '\n') { - buf[0] = (uint8_t)'\r'; - - if (ptrUSART->Send(buf, 1U) != ARM_DRIVER_OK) { - return -1; - } - - while (ptrUSART->GetStatus().tx_busy != 0U); - } - - buf[0] = (uint8_t)ch; - - if (ptrUSART->Send(buf, 1U) != ARM_DRIVER_OK) { - return -1; - } - - while (ptrUSART->GetStatus().tx_busy != 0U); - - return ch; -} - -/** - Put a character to the stdout - - \param[in] ch Character to output - \return The character written, or -1 on write error. -*/ -int stdout_putchar (int ch) { - uint8_t buf[1]; - - if (ch == '\n') { - buf[0] = (uint8_t)'\r'; - - if (ptrUSART->Send(buf, 1U) != ARM_DRIVER_OK) { - return -1; - } - - while (ptrUSART->GetStatus().tx_busy != 0U); - } - - buf[0] = (uint8_t)ch; - - if (ptrUSART->Send(buf, 1U) != ARM_DRIVER_OK) { - return -1; - } - - while (ptrUSART->GetStatus().tx_busy != 0U); - - return ch; -} - -/** - Get a character from the stdio - - \return The next character from the input, or -1 on read error. -*/ -int stdin_getchar (void) { - uint8_t buf[1]; - - if (ptrUSART->Receive(buf, 1U) != ARM_DRIVER_OK) { - return -1; - } - - while (ptrUSART->GetStatus().rx_busy != 0U); - - return (int)buf[0]; -} \ No newline at end of file diff --git a/ST/B-U585I-IOT02A/KeywordSpotting/SDS.csolution.yml b/ST/B-U585I-IOT02A/KeywordSpotting/SDS.csolution.yml index f69536c..02beac6 100644 --- a/ST/B-U585I-IOT02A/KeywordSpotting/SDS.csolution.yml +++ b/ST/B-U585I-IOT02A/KeywordSpotting/SDS.csolution.yml @@ -53,7 +53,7 @@ solution: debugger: name: Arm-FVP model: FVP_Corstone_SSE-300_Ethos-U55 - config-file: Board/Corstone-300/fvp_config.txt + config-file: Board/Corstone-300/fvp_config_u55.txt # List of different build configurations. build-types: diff --git a/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/Board-U55.clayer.yml b/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/Board-U55.clayer.yml index b033b5d..8d5541b 100644 --- a/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/Board-U55.clayer.yml +++ b/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/Board-U55.clayer.yml @@ -1,6 +1,6 @@ layer: type: Board - description: Board setup for AI/ML with Ethos U55 + description: Base configuration of SSE-300 FVP with Ethos U55 for-board: ARM::V2M-MPS3-SSE-300-FVP for-device: ARM::SSE-300-MPS3 @@ -12,18 +12,18 @@ layer: - STDIN - STDOUT - STDERR - - Heap: 786432 + - Heap: 98304 + consumes: + - CMSIS-RTOS2 define: - CMSIS_target_header: \"Corstone-300.h\" - - ETHOSU55 - CORSTONE300_FVP - - ARM_MODEL_USE_PMU_COUNTERS packs: - pack: ARM::CMSIS - - pack: ARM::CMSIS-Compiler@^2.1.0 - - pack: ARM::ethos-u-core-driver@^1.25.2 + - pack: ARM::CMSIS-Compiler@^2.3.0 + - pack: ARM::CMSIS-Ethos-U@^1.0.0 - pack: ARM::V2M_MPS3_SSE_300_BSP@1.5.0 components: @@ -33,9 +33,9 @@ layer: - component: CMSIS Driver:VIO - component: CMSIS-Compiler:CORE - - component: CMSIS-Compiler:STDERR:Custom - - component: CMSIS-Compiler:STDIN:Custom - - component: CMSIS-Compiler:STDOUT:Custom + - component: CMSIS-Compiler:STDERR:UART&CMSIS + - component: CMSIS-Compiler:STDIN:UART&CMSIS + - component: CMSIS-Compiler:STDOUT:UART&CMSIS - component: Device:Definition - component: Device:Startup&C Startup @@ -46,14 +46,17 @@ layer: - component: Device:Native Driver:UART - component: Machine Learning:NPU Support:Ethos-U Driver&Generic U55 + define: + - ETHOSU_MACS: 256 groups: - group: Board files: - - file: ./main.c - - file: ./main.h - - file: ./ethos_setup.c - - file: ./retarget_stdio.c + - file: main.c + - file: main.h + - file: ethos_setup.c + - file: ethosu_os_rtos2.c + - file: ethosu_dcache.c linker: - - regions: ./regions_SSE-300.h + - regions: RTE/Device/SSE-300-MPS3/regions_SSE-300.h diff --git a/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/Board-U65.clayer.yml b/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/Board-U65.clayer.yml index e0bed61..4cebf52 100644 --- a/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/Board-U65.clayer.yml +++ b/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/Board-U65.clayer.yml @@ -1,6 +1,6 @@ layer: type: Board - description: Board setup for AI/ML with Ethos U65 + description: Base configuration of SSE-300 FVP with Ethos U65 for-board: ARM::V2M-MPS3-SSE-300-FVP for-device: ARM::SSE-300-MPS3 @@ -12,18 +12,18 @@ layer: - STDIN - STDOUT - STDERR - - Heap: 786432 + - Heap: 98304 + consumes: + - CMSIS-RTOS2 define: - CMSIS_target_header: \"Corstone-300.h\" - - ETHOSU65 - CORSTONE300_FVP - - ARM_MODEL_USE_PMU_COUNTERS packs: - pack: ARM::CMSIS - - pack: ARM::CMSIS-Compiler@^2.1.0 - - pack: ARM::ethos-u-core-driver@^1.25.2 + - pack: ARM::CMSIS-Compiler@^2.3.0 + - pack: ARM::CMSIS-Ethos-U@^1.0.0 - pack: ARM::V2M_MPS3_SSE_300_BSP@1.5.0 components: @@ -33,9 +33,9 @@ layer: - component: CMSIS Driver:VIO - component: CMSIS-Compiler:CORE - - component: CMSIS-Compiler:STDERR:Custom - - component: CMSIS-Compiler:STDIN:Custom - - component: CMSIS-Compiler:STDOUT:Custom + - component: CMSIS-Compiler:STDERR:UART&CMSIS + - component: CMSIS-Compiler:STDIN:UART&CMSIS + - component: CMSIS-Compiler:STDOUT:UART&CMSIS - component: Device:Definition - component: Device:Startup&C Startup @@ -46,14 +46,17 @@ layer: - component: Device:Native Driver:UART - component: Machine Learning:NPU Support:Ethos-U Driver&Generic U65 + define: + - ETHOSU_MACS: 256 groups: - group: Board files: - - file: ./main.c - - file: ./main.h - - file: ./ethos_setup.c - - file: ./retarget_stdio.c + - file: main.c + - file: main.h + - file: ethos_setup.c + - file: ethosu_os_rtos2.c + - file: ethosu_dcache.c linker: - - regions: ./regions_SSE-300.h + - regions: RTE/Device/SSE-300-MPS3/regions_SSE-300.h diff --git a/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/Board.clayer.yml b/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/Board.clayer.yml index b7c2fe0..2fa6b04 100644 --- a/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/Board.clayer.yml +++ b/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/Board.clayer.yml @@ -1,6 +1,6 @@ layer: type: Board - description: Board setup for AI/ML + description: Base configuration of SSE-300 FVP for-board: ARM::V2M-MPS3-SSE-300-FVP for-device: ARM::SSE-300-MPS3 @@ -12,16 +12,15 @@ layer: - STDIN - STDOUT - STDERR - - Heap: 786432 + - Heap: 98304 define: - CMSIS_target_header: \"Corstone-300.h\" - CORSTONE300_FVP - - ARM_MODEL_USE_PMU_COUNTERS packs: - pack: ARM::CMSIS - - pack: ARM::CMSIS-Compiler@^2.1.0 + - pack: ARM::CMSIS-Compiler@^2.3.0 - pack: ARM::V2M_MPS3_SSE_300_BSP@1.5.0 components: @@ -31,9 +30,9 @@ layer: - component: CMSIS Driver:VIO - component: CMSIS-Compiler:CORE - - component: CMSIS-Compiler:STDERR:Custom - - component: CMSIS-Compiler:STDIN:Custom - - component: CMSIS-Compiler:STDOUT:Custom + - component: CMSIS-Compiler:STDERR:UART&CMSIS + - component: CMSIS-Compiler:STDIN:UART&CMSIS + - component: CMSIS-Compiler:STDOUT:UART&CMSIS - component: Device:Definition - component: Device:Startup&C Startup @@ -46,9 +45,8 @@ layer: groups: - group: Board files: - - file: ./main.c - - file: ./main.h - - file: ./retarget_stdio.c + - file: main.c + - file: main.h linker: - - regions: ./regions_SSE-300.h + - regions: RTE/Device/SSE-300-MPS3/regions_SSE-300.h diff --git a/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/Corstone-300.h b/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/Corstone-300.h index 8d1a416..4abb85d 100644 --- a/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/Corstone-300.h +++ b/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/Corstone-300.h @@ -1,6 +1,6 @@ -/*--------------------------------------------------------------------------- - * Copyright (c) 2025 Arm Limited (or its affiliates). - * All rights reserved. +/* + * Copyright 2025-2026 Arm Limited and/or its affiliates. + * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may @@ -14,7 +14,7 @@ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. - *---------------------------------------------------------------------------*/ + */ #ifndef CORSTONE_300_H_ #define CORSTONE_300_H_ diff --git a/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/README.md b/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/README.md index 97555a2..4b287fd 100644 --- a/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/README.md +++ b/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/README.md @@ -1,20 +1,30 @@ # Board: Arm V2M-MPS3-SSE-300-FVP -## Board Layer for Corstone-300 FVP +## Board Layers for Corstone-300 FVP -This layer works for: +These layers work for: ```yml board: ARM::V2M-MPS3-SSE-300-FVP device: ARM::SSE-300-MPS3 ``` +Select one layer matching the application's NPU requirements: + +| Layer file | Use in Application +|:---------------------|:------------------------ +| Board.clayer.yml | Without Ethos-U support +| Board-U55.clayer.yml | With Ethos-U55 support +| Board-U65.clayer.yml | With Ethos-U65 support + +Use the corresponding FVP configuration file listed below. + ### System Configuration | System Component | Setting |:------------------------|:---------------------------------- -| Heap | 768 kB (configured in linker file) -| Stack (MSP) | 32 kB (configured in linker file) +| Heap | 96 kB (configured in regions header) +| Stack (MSP) | 4 kB (configured in regions header) ### STDIO mapping @@ -41,4 +51,6 @@ interface for SDS data files using a [Virtual Streaming Interface](https://arm-s | File | Description |:-------------------|:------------- -| fvp_config.txt | Corstone-300 FVP without Ethos-U or with Ethos-U55/U65 +| fvp_config.txt | Corstone-300 FVP without Ethos-U +| fvp_config_u55.txt | Corstone-300 FVP with an Ethos-U55-256 +| fvp_config_u65.txt | Corstone-300 FVP with an Ethos-U65-256 diff --git a/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/RTE/CMSIS-Compiler/stderr_cmsis_uart_config.h b/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/RTE/CMSIS-Compiler/stderr_cmsis_uart_config.h new file mode 100644 index 0000000..d6a30a3 --- /dev/null +++ b/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/RTE/CMSIS-Compiler/stderr_cmsis_uart_config.h @@ -0,0 +1,59 @@ +/*--------------------------------------------------------------------------- + * Copyright (c) 2026 Arm Limited (or its affiliates). + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * -------------------------------------------------------------------------- + * + * Purpose: Configure STDERR to CMSIS-Driver USART retarget implementation + * Revision: V1.0.0 + * + * --------------------------------------------------------------------------*/ + +#ifndef STDERR_CMSIS_UART_CONFIG_H_ +#define STDERR_CMSIS_UART_CONFIG_H_ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// UART STDERR Buffer Size +// UART STDERR buffer is used to store STDERR data before sending it via UART +// Default: 0 (unbuffered) +#ifndef STDERR_UART_BUFFER_SIZE +#define STDERR_UART_BUFFER_SIZE 0 +#endif + +// UART STDERR Buffer Section Name +// Specify the memory section name for UART STDERR buffer +// Default: .stderr_uart_buf +#ifndef STDERR_UART_BUFFER_SECTION +#define STDERR_UART_BUFFER_SECTION ".stderr_uart_buf" +#endif + +// UART STDERR Buffer Alignment +// Define the STDERR buffer alignment in bytes +// Default: 32 +#ifndef STDERR_UART_BUFFER_ALIGNMENT +#define STDERR_UART_BUFFER_ALIGNMENT 32 +#endif + +// Convert LF to CRLF +// If enabled, LF characters are preceded by CR characters on output +// Default: 0 +#ifndef STDERR_CR_LF +#define STDERR_CR_LF 1 +#endif + +#endif /* STDERR_CMSIS_UART_CONFIG_H_ */ diff --git a/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/RTE/CMSIS-Compiler/stderr_cmsis_uart_config.h.base@1.0.0 b/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/RTE/CMSIS-Compiler/stderr_cmsis_uart_config.h.base@1.0.0 new file mode 100644 index 0000000..192648e --- /dev/null +++ b/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/RTE/CMSIS-Compiler/stderr_cmsis_uart_config.h.base@1.0.0 @@ -0,0 +1,59 @@ +/*--------------------------------------------------------------------------- + * Copyright (c) 2026 Arm Limited (or its affiliates). + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * -------------------------------------------------------------------------- + * + * Purpose: Configure STDERR to CMSIS-Driver USART retarget implementation + * Revision: V1.0.0 + * + * --------------------------------------------------------------------------*/ + +#ifndef STDERR_CMSIS_UART_CONFIG_H_ +#define STDERR_CMSIS_UART_CONFIG_H_ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// UART STDERR Buffer Size +// UART STDERR buffer is used to store STDERR data before sending it via UART +// Default: 0 (unbuffered) +#ifndef STDERR_UART_BUFFER_SIZE +#define STDERR_UART_BUFFER_SIZE 0 +#endif + +// UART STDERR Buffer Section Name +// Specify the memory section name for UART STDERR buffer +// Default: .stderr_uart_buf +#ifndef STDERR_UART_BUFFER_SECTION +#define STDERR_UART_BUFFER_SECTION ".stderr_uart_buf" +#endif + +// UART STDERR Buffer Alignment +// Define the STDERR buffer alignment in bytes +// Default: 32 +#ifndef STDERR_UART_BUFFER_ALIGNMENT +#define STDERR_UART_BUFFER_ALIGNMENT 32 +#endif + +// Convert LF to CRLF +// If enabled, LF characters are preceded by CR characters on output +// Default: 0 +#ifndef STDERR_CR_LF +#define STDERR_CR_LF 0 +#endif + +#endif /* STDERR_CMSIS_UART_CONFIG_H_ */ diff --git a/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/RTE/CMSIS-Compiler/stdin_cmsis_uart_config.h b/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/RTE/CMSIS-Compiler/stdin_cmsis_uart_config.h new file mode 100644 index 0000000..bce0ba2 --- /dev/null +++ b/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/RTE/CMSIS-Compiler/stdin_cmsis_uart_config.h @@ -0,0 +1,59 @@ +/*--------------------------------------------------------------------------- + * Copyright (c) 2026 Arm Limited (or its affiliates). + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * -------------------------------------------------------------------------- + * + * Purpose: Configure STDIN to CMSIS-Driver USART retarget implementation + * Revision: V1.0.0 + * + * --------------------------------------------------------------------------*/ + +#ifndef STDIN_CMSIS_UART_CONFIG_H_ +#define STDIN_CMSIS_UART_CONFIG_H_ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// UART STDIN Buffer Size +// UART STDIN buffer is used to store STDIN data received via UART +// Default: 64 +#ifndef STDIN_UART_BUFFER_SIZE +#define STDIN_UART_BUFFER_SIZE 64 +#endif + +// UART STDIN Buffer Section Name +// Specify the memory section name for UART STDIN buffer +// Default: .stdin_uart_buf +#ifndef STDIN_UART_BUFFER_SECTION +#define STDIN_UART_BUFFER_SECTION ".stdin_uart_buf" +#endif + +// UART STDIN Buffer Alignment +// Define the STDIN buffer alignment in bytes +// Default: 32 +#ifndef STDIN_UART_BUFFER_ALIGNMENT +#define STDIN_UART_BUFFER_ALIGNMENT 32 +#endif + +// Echo Input Characters +// If enabled, received characters are echoed to STDOUT +// Default: 0 +#ifndef STDIN_ECHO +#define STDIN_ECHO 0 +#endif + +#endif /* STDIN_CMSIS_UART_CONFIG_H_ */ diff --git a/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/RTE/CMSIS-Compiler/stdin_cmsis_uart_config.h.base@1.0.0 b/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/RTE/CMSIS-Compiler/stdin_cmsis_uart_config.h.base@1.0.0 new file mode 100644 index 0000000..bce0ba2 --- /dev/null +++ b/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/RTE/CMSIS-Compiler/stdin_cmsis_uart_config.h.base@1.0.0 @@ -0,0 +1,59 @@ +/*--------------------------------------------------------------------------- + * Copyright (c) 2026 Arm Limited (or its affiliates). + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * -------------------------------------------------------------------------- + * + * Purpose: Configure STDIN to CMSIS-Driver USART retarget implementation + * Revision: V1.0.0 + * + * --------------------------------------------------------------------------*/ + +#ifndef STDIN_CMSIS_UART_CONFIG_H_ +#define STDIN_CMSIS_UART_CONFIG_H_ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// UART STDIN Buffer Size +// UART STDIN buffer is used to store STDIN data received via UART +// Default: 64 +#ifndef STDIN_UART_BUFFER_SIZE +#define STDIN_UART_BUFFER_SIZE 64 +#endif + +// UART STDIN Buffer Section Name +// Specify the memory section name for UART STDIN buffer +// Default: .stdin_uart_buf +#ifndef STDIN_UART_BUFFER_SECTION +#define STDIN_UART_BUFFER_SECTION ".stdin_uart_buf" +#endif + +// UART STDIN Buffer Alignment +// Define the STDIN buffer alignment in bytes +// Default: 32 +#ifndef STDIN_UART_BUFFER_ALIGNMENT +#define STDIN_UART_BUFFER_ALIGNMENT 32 +#endif + +// Echo Input Characters +// If enabled, received characters are echoed to STDOUT +// Default: 0 +#ifndef STDIN_ECHO +#define STDIN_ECHO 0 +#endif + +#endif /* STDIN_CMSIS_UART_CONFIG_H_ */ diff --git a/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/RTE/CMSIS-Compiler/stdio_cmsis_uart_config.h b/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/RTE/CMSIS-Compiler/stdio_cmsis_uart_config.h new file mode 100644 index 0000000..aeeca61 --- /dev/null +++ b/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/RTE/CMSIS-Compiler/stdio_cmsis_uart_config.h @@ -0,0 +1,52 @@ +/*--------------------------------------------------------------------------- + * Copyright (c) 2026 Arm Limited (or its affiliates). + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * -------------------------------------------------------------------------- + * + * Purpose: STDIO to CMSIS Driver USART Retarget Configuration + * Revision: V1.0.0 + * + * --------------------------------------------------------------------------*/ + +#ifndef STDIO_CMSIS_UART_CONFIG_H_ +#define STDIO_CMSIS_UART_CONFIG_H_ + +#ifdef CMSIS_target_header +#include CMSIS_target_header +#else +#define RETARGET_STDIO_UART 0 +#endif + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// Connect to hardware via Driver_USART# +// Select driver control block for hardware interface +// Default: 0 +#ifndef STDIO_UART_DRIVER +#define STDIO_UART_DRIVER RETARGET_STDIO_UART +#endif + +// UART baudrate +// Specifies the baudrate for UART communication +// Common values: 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 +// Default: 115200 +#ifndef STDIO_UART_BAUDRATE +#define STDIO_UART_BAUDRATE 115200 +#endif + +#endif /* STDIO_CMSIS_UART_CONFIG_H_ */ diff --git a/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/RTE/CMSIS-Compiler/stdio_cmsis_uart_config.h.base@1.0.0 b/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/RTE/CMSIS-Compiler/stdio_cmsis_uart_config.h.base@1.0.0 new file mode 100644 index 0000000..aeeca61 --- /dev/null +++ b/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/RTE/CMSIS-Compiler/stdio_cmsis_uart_config.h.base@1.0.0 @@ -0,0 +1,52 @@ +/*--------------------------------------------------------------------------- + * Copyright (c) 2026 Arm Limited (or its affiliates). + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * -------------------------------------------------------------------------- + * + * Purpose: STDIO to CMSIS Driver USART Retarget Configuration + * Revision: V1.0.0 + * + * --------------------------------------------------------------------------*/ + +#ifndef STDIO_CMSIS_UART_CONFIG_H_ +#define STDIO_CMSIS_UART_CONFIG_H_ + +#ifdef CMSIS_target_header +#include CMSIS_target_header +#else +#define RETARGET_STDIO_UART 0 +#endif + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// Connect to hardware via Driver_USART# +// Select driver control block for hardware interface +// Default: 0 +#ifndef STDIO_UART_DRIVER +#define STDIO_UART_DRIVER RETARGET_STDIO_UART +#endif + +// UART baudrate +// Specifies the baudrate for UART communication +// Common values: 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 +// Default: 115200 +#ifndef STDIO_UART_BAUDRATE +#define STDIO_UART_BAUDRATE 115200 +#endif + +#endif /* STDIO_CMSIS_UART_CONFIG_H_ */ diff --git a/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/RTE/CMSIS-Compiler/stdout_cmsis_uart_config.h b/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/RTE/CMSIS-Compiler/stdout_cmsis_uart_config.h new file mode 100644 index 0000000..3cdc2ae --- /dev/null +++ b/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/RTE/CMSIS-Compiler/stdout_cmsis_uart_config.h @@ -0,0 +1,59 @@ +/*--------------------------------------------------------------------------- + * Copyright (c) 2026 Arm Limited (or its affiliates). + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * -------------------------------------------------------------------------- + * + * Purpose: Configure STDOUT to CMSIS-Driver USART retarget implementation + * Revision: V1.0.0 + * + * --------------------------------------------------------------------------*/ + +#ifndef STDOUT_CMSIS_UART_CONFIG_H_ +#define STDOUT_CMSIS_UART_CONFIG_H_ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// UART STDOUT Buffer Size +// UART STDOUT buffer is used to store STDOUT data before sending it via UART +// Default: 0 (unbuffered) +#ifndef STDOUT_UART_BUFFER_SIZE +#define STDOUT_UART_BUFFER_SIZE 0 +#endif + +// UART STDOUT Buffer Section Name +// Specify the memory section name for UART STDOUT buffer +// Default: .stdout_uart_buf +#ifndef STDOUT_UART_BUFFER_SECTION +#define STDOUT_UART_BUFFER_SECTION ".stdout_uart_buf" +#endif + +// UART STDOUT Buffer Alignment +// Define the buffer alignment in bytes +// Default: 32 +#ifndef STDOUT_UART_BUFFER_ALIGNMENT +#define STDOUT_UART_BUFFER_ALIGNMENT 32 +#endif + +// Convert LF to CRLF +// If enabled, LF characters are preceded by CR characters on output +// Default: 0 +#ifndef STDOUT_CR_LF +#define STDOUT_CR_LF 1 +#endif + +#endif /* STDOUT_CMSIS_UART_CONFIG_H_ */ diff --git a/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/RTE/CMSIS-Compiler/stdout_cmsis_uart_config.h.base@1.0.0 b/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/RTE/CMSIS-Compiler/stdout_cmsis_uart_config.h.base@1.0.0 new file mode 100644 index 0000000..323d217 --- /dev/null +++ b/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/RTE/CMSIS-Compiler/stdout_cmsis_uart_config.h.base@1.0.0 @@ -0,0 +1,59 @@ +/*--------------------------------------------------------------------------- + * Copyright (c) 2026 Arm Limited (or its affiliates). + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * -------------------------------------------------------------------------- + * + * Purpose: Configure STDOUT to CMSIS-Driver USART retarget implementation + * Revision: V1.0.0 + * + * --------------------------------------------------------------------------*/ + +#ifndef STDOUT_CMSIS_UART_CONFIG_H_ +#define STDOUT_CMSIS_UART_CONFIG_H_ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// UART STDOUT Buffer Size +// UART STDOUT buffer is used to store STDOUT data before sending it via UART +// Default: 0 (unbuffered) +#ifndef STDOUT_UART_BUFFER_SIZE +#define STDOUT_UART_BUFFER_SIZE 0 +#endif + +// UART STDOUT Buffer Section Name +// Specify the memory section name for UART STDOUT buffer +// Default: .stdout_uart_buf +#ifndef STDOUT_UART_BUFFER_SECTION +#define STDOUT_UART_BUFFER_SECTION ".stdout_uart_buf" +#endif + +// UART STDOUT Buffer Alignment +// Define the buffer alignment in bytes +// Default: 32 +#ifndef STDOUT_UART_BUFFER_ALIGNMENT +#define STDOUT_UART_BUFFER_ALIGNMENT 32 +#endif + +// Convert LF to CRLF +// If enabled, LF characters are preceded by CR characters on output +// Default: 0 +#ifndef STDOUT_CR_LF +#define STDOUT_CR_LF 0 +#endif + +#endif /* STDOUT_CMSIS_UART_CONFIG_H_ */ diff --git a/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/RTE/Device/SSE-300-MPS3/ac6_linker_script.sct.src b/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/RTE/Device/SSE-300-MPS3/ac6_linker_script.sct.src index 79a25e6..3576f33 100644 --- a/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/RTE/Device/SSE-300-MPS3/ac6_linker_script.sct.src +++ b/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/RTE/Device/SSE-300-MPS3/ac6_linker_script.sct.src @@ -34,7 +34,6 @@ LR_ROM0 __ROM0_BASE __ROM0_SIZE { ER_ROM0 __ROM0_BASE __ROM0_SIZE { *.o (RESET, +First) *(InRoot$$Sections) - *(+RO +XO) } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) @@ -42,6 +41,13 @@ LR_ROM0 __ROM0_BASE __ROM0_SIZE { *(Veneer$$CMSE) } #endif +} + +LR_ROM1 __ROM1_BASE __ROM1_SIZE { + + ER_ROM1 __ROM1_BASE __ROM1_SIZE { + *(+RO +XO) + } RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE) { *.o(.bss.noinit) @@ -67,11 +73,8 @@ LR_ROM0 __ROM0_BASE __ROM0_SIZE { #if __RAM1_SIZE > 0 RW_RAM1 __RAM1_BASE __RAM1_SIZE { - ; Ethos-U Cache Area - *.o (*ethos_cache_buf) - - ; NN Activation Tensor (activation buffer / tensor arena) - *.o (*activation_buf) + ; Ethos-U writable area + *.o (ethos_arena) .ANY (+RW +ZI) } @@ -90,19 +93,11 @@ LR_ROM0 __ROM0_BASE __ROM0_SIZE { #endif } -#if __ROM1_SIZE > 0 -LR_ROM1 __ROM1_BASE __ROM1_SIZE { - ER_ROM1 +0 __ROM1_SIZE { - .ANY (+RO +XO) - } -} -#endif - #if __ROM2_SIZE > 0 LR_ROM2 __ROM2_BASE __ROM2_SIZE { ER_ROM2 +0 __ROM2_SIZE { - ; NN Model Binary Representation - *.o (nn_model) + ; Ethos-U model, command stream and constants + *.o (ethos_model) .ANY (+RO +XO) } diff --git a/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/RTE/Device/SSE-300-MPS3/clang_linker_script.ld.src b/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/RTE/Device/SSE-300-MPS3/clang_linker_script.ld.src new file mode 100644 index 0000000..a64b505 --- /dev/null +++ b/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/RTE/Device/SSE-300-MPS3/clang_linker_script.ld.src @@ -0,0 +1,406 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright © 2019 Keith Packard + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED + * OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* ---------------------------------------------------------------------------- + Stack seal size definition + *----------------------------------------------------------------------------*/ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define __STACKSEAL_SIZE ( 8 ) +#else +#define __STACKSEAL_SIZE ( 0 ) +#endif + +/* ---------------------------------------------------------------------------- + Memory definition + *----------------------------------------------------------------------------*/ +MEMORY +{ + ROM0 (rx!w) : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE +#if __ROM1_SIZE > 0 + ROM1 (rx!w) : ORIGIN = __ROM1_BASE, LENGTH = __ROM1_SIZE +#endif +#if __ROM2_SIZE > 0 + ROM2 (rx!w) : ORIGIN = __ROM2_BASE, LENGTH = __ROM2_SIZE +#endif +#if __ROM3_SIZE > 0 + ROM3 (rx!w) : ORIGIN = __ROM3_BASE, LENGTH = __ROM3_SIZE +#endif + + RAM0 (w!rx) : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE +#if __RAM1_SIZE > 0 + RAM1 (w!rx) : ORIGIN = __RAM1_BASE, LENGTH = __RAM1_SIZE +#endif +#if __RAM2_SIZE > 0 + RAM2 (w!rx) : ORIGIN = __RAM2_BASE, LENGTH = __RAM2_SIZE +#endif +#if __RAM3_SIZE > 0 + RAM3 (w!rx) : ORIGIN = __RAM3_BASE, LENGTH = __RAM3_SIZE +#endif +} + +ENTRY(Reset_Handler) + +PHDRS +{ + boot PT_LOAD; + text PT_LOAD; + ram PT_LOAD; + ram_init PT_LOAD; + tls PT_TLS; +#if __RAM1_SIZE > 0 + ethos_ram PT_LOAD; +#endif +#if __ROM2_SIZE > 0 + ethos_model PT_LOAD; +#endif +} + +SECTIONS +{ + .init : { + KEEP (*(.vectors)) + + /* Disable by default + * + * *.init.enter contains a vector table provided by picolibc, + * whereas CMSIS already provides a vector table via .vectors + */ + /* + KEEP (*(.text.init.enter)) + KEEP (*(.data.init.enter)) + */ + + KEEP (*(SORT_BY_NAME(.init) SORT_BY_NAME(.init.*))) + } >ROM0 AT>ROM0 :boot + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + .veneers : + { + . = ALIGN(32); + KEEP(*(.gnu.sgstubs)) + } > ROM0 AT>ROM0 :boot +#endif + + .text : { + + /* code */ + *(.text.unlikely .text.unlikely.*) + *(.text.startup .text.startup.*) + *(.text .text.* .opd .opd.*) + *(.gnu.linkonce.t.*) + KEEP (*(.fini .fini.*)) + __text_end = .; + + PROVIDE (__etext = __text_end); + PROVIDE (_etext = __text_end); + PROVIDE (etext = __text_end); + + /* read-only data */ + *(.rdata) + *(.rodata .rodata.*) + *(.gnu.linkonce.r.*) + + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + *(.data.rel.ro .data.rel.ro.*) + *(.got .got.*) + + /* Need to pre-align so that the symbols come after padding */ + . = ALIGN(8); + + /* lists of constructors and destructors */ + PROVIDE_HIDDEN ( __bothinit_array_start = . ); + PROVIDE_HIDDEN ( __preinit_array_start = . ); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN ( __preinit_array_end = . ); + + PROVIDE_HIDDEN ( __init_array_start = . ); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array .ctors)) + PROVIDE_HIDDEN ( __init_array_end = . ); + PROVIDE_HIDDEN ( __bothinit_array_end = . ); + + PROVIDE_HIDDEN ( __fini_array_start = . ); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array .dtors)) + PROVIDE_HIDDEN ( __fini_array_end = . ); + + } >ROM1 AT>ROM1 :text + + .toc : { + *(.toc .toc.*) + } >ROM1 AT>ROM1 :text + + /* additional sections when compiling with C++ exception support */ + + .except_ordered : { + *(.gcc_except_table *.gcc_except_table.*) + KEEP (*(.eh_frame .eh_frame.*)) + *(.ARM.extab* .gnu.linkonce.armextab.*) + } >ROM1 AT>ROM1 :text + + .except_unordered : { + . = ALIGN(8); + + PROVIDE(__exidx_start = .); + *(.ARM.exidx*) + PROVIDE(__exidx_end = .); + } >ROM1 AT>ROM1 :text + + + /* + * Data values which are preserved across reset + */ + .preserve (NOLOAD) : { + PROVIDE(__preserve_start__ = .); + KEEP(*(SORT_BY_NAME(.preserve.*))) + KEEP(*(.preserve)) + PROVIDE(__preserve_end__ = .); + } >RAM0 AT>RAM0 :ram + + .data : { + *(.data .data.*) + *(.gnu.linkonce.d.*) + + /* Need to pre-align so that the symbols come after padding */ + . = ALIGN(8); + + PROVIDE( __global_pointer$ = . + 0x800 ); + *(.sdata .sdata.* .sdata2.*) + *(.gnu.linkonce.s.*) + } >RAM0 AT>ROM1 :ram_init + PROVIDE(__data_start = ADDR(.data)); + PROVIDE(__data_source = LOADADDR(.data)); + + /* Thread local initialized data. This gets + * space allocated as it is expected to be placed + * in ram to be used as a template for TLS data blocks + * allocated at runtime. We're slightly abusing that + * by placing the data in flash where it will be copied + * into the allocate ram addresses by the existing + * data initialization code in crt0 + */ + .tdata : { + *(.tdata .tdata.* .gnu.linkonce.td.*) + PROVIDE(__data_end = .); + PROVIDE(__tdata_end = .); + } >RAM0 AT>ROM1 :tls :ram_init + PROVIDE( __tls_base = ADDR(.tdata)); + PROVIDE( __tdata_start = ADDR(.tdata)); + PROVIDE( __tdata_source = LOADADDR(.tdata) ); + PROVIDE( __tdata_source_end = LOADADDR(.tdata) + SIZEOF(.tdata) ); + PROVIDE( __data_source_end = __tdata_source_end ); + PROVIDE( __tdata_size = SIZEOF(.tdata) ); + PROVIDE( __tls_align = MAX(ALIGNOF(.tdata),ALIGNOF(.tbss)) ); + + PROVIDE( __edata = __data_end ); + PROVIDE( _edata = __data_end ); + PROVIDE( edata = __data_end ); + PROVIDE( __data_size = __data_end - __data_start ); + PROVIDE( __data_source_size = __data_source_end - __data_source ); + + .tbss (NOLOAD) : { + *(.tbss .tbss.* .gnu.linkonce.tb.*) + *(.tcommon) + PROVIDE( __tls_end = . ); + PROVIDE( __tbss_end = . ); + } >RAM0 AT>RAM0 :tls :ram + PROVIDE( __bss_start = ADDR(.tbss)); + PROVIDE( __tbss_start = ADDR(.tbss)); + PROVIDE( __tbss_offset = ADDR(.tbss) - ADDR(.tdata) ); + PROVIDE( __tbss_size = SIZEOF(.tbss) ); + PROVIDE( __tls_size = __tls_end - __tls_base ); + PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) ); + PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) ); + PROVIDE( __arm64_tls_tcb_offset = MAX(16, __tls_align) ); + + /* + * The linker special cases .tbss segments which are + * identified as segments which are not loaded and are + * thread_local. + * + * For these segments, the linker does not advance 'dot' + * across them. We actually need memory allocated for tbss, + * so we create a special segment here just to make room + */ + /* + .tbss_space (NOLOAD) : { + . = ADDR(.tbss); + . = . + SIZEOF(.tbss); + } >RAM0 AT>RAM0 :ram + */ + + .bss (NOLOAD) : { + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + + /* Align the end of this section, so next can start on aligned address */ + . = ALIGN(8); + __bss_end = .; + } >RAM0 AT>RAM0 :ram + PROVIDE( __non_tls_bss_start = ADDR(.bss) ); + PROVIDE( __bss_size = __bss_end - __bss_start ); + + /* This section contains data that is not initialized during load, + or during the application's initialization sequence. */ + .noinit (NOLOAD) : { + __noinit_start__ = .; + *(.noinit) + *(.noinit.*) + + /* Align the end of this section, so next (heap) can start on aligned address */ + . = ALIGN(8); + __noinit_end__ = .; + } >RAM0 AT>RAM0 :ram + + PROVIDE( __end = . ); + PROVIDE( _end = . ); + PROVIDE( end = . ); + + /* Make the rest of memory available for heap storage */ + PROVIDE (__heap_start = __end); +#ifdef __HEAP_SIZE + PROVIDE (__heap_end = __heap_start + __HEAP_SIZE); + PROVIDE (__heap_size = __HEAP_SIZE); +#else + PROVIDE (__heap_end = __stack - __STACK_SIZE); + PROVIDE (__heap_size = __heap_end - __heap_start); +#endif + .heap (NOLOAD) : { + . += __heap_size; + } >RAM0 :ram + + /* Define a stack region to make sure it fits in memory */ + PROVIDE(__stack = ORIGIN(RAM0) + LENGTH(RAM0) - __STACKSEAL_SIZE); + PROVIDE(__stack_limit = __stack - __STACK_SIZE); + .stack (__stack_limit) (NOLOAD) : { + . += __STACK_SIZE; + } >RAM0 :ram + +#if __STACKSEAL_SIZE > 0 + PROVIDE(__stack_seal = __stack); + .stackseal (__stack) (NOLOAD) : + { + . += __STACKSEAL_SIZE; + } >RAM0 :ram +#endif + + /* Ethos-U writable area */ +#if __RAM1_SIZE > 0 + .ethos_arena (NOLOAD) : ALIGN(32) { + *(ethos_arena) + } >RAM1 AT>RAM1 :ethos_ram +#endif + + /* Ethos-U model, command stream and constants */ +#if __ROM2_SIZE > 0 + .ethos_model : ALIGN(32) { + *(ethos_model) + } >ROM2 AT>ROM2 :ethos_model +#endif + + /* Throw away C++ exception handling information */ + + /* + + /DISCARD/ : { + *(.note .note.*) + *(.eh_frame .eh_frame.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + *(.ARM.exidx*) + } + + */ + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .gnu.build.attributes : { *(.gnu.build.attributes .gnu.build.attributes.*) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1. */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions. */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2. */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2. */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line .debug_line.* .debug_line_end) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions. */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + /* DWARF 3. */ + .debug_pubtypes 0 : { *(.debug_pubtypes) } + .debug_ranges 0 : { *(.debug_ranges) } + /* DWARF 5. */ + .debug_addr 0 : { *(.debug_addr) } + .debug_line_str 0 : { *(.debug_line_str) } + .debug_loclists 0 : { *(.debug_loclists) } + .debug_macro 0 : { *(.debug_macro) } + .debug_names 0 : { *(.debug_names) } + .debug_rnglists 0 : { *(.debug_rnglists) } + .debug_str_offsets 0 : { *(.debug_str_offsets) } + .debug_sup 0 : { *(.debug_sup) } + .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) } +} +/* + * Check that sections that are copied from flash to RAM have matching + * padding, so that a single memcpy() of __data_size copies the correct bytes. + */ +ASSERT( __data_size == __data_source_size, + "ERROR: .data/.tdata flash size does not match RAM size"); diff --git a/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/RTE/Device/SSE-300-MPS3/gcc_linker_script.ld.src b/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/RTE/Device/SSE-300-MPS3/gcc_linker_script.ld.src index 2e2ef6f..9f6f1a0 100644 --- a/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/RTE/Device/SSE-300-MPS3/gcc_linker_script.ld.src +++ b/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/RTE/Device/SSE-300-MPS3/gcc_linker_script.ld.src @@ -318,8 +318,7 @@ SECTIONS .cache (NOLOAD): { . = ALIGN(32); - *(*ethos_cache_buf) /* Ethos-U Cache Area */ - *(*activation_buf) /* NN Activation Tensor (activation buffer / tensor arena) */ + *(ethos_arena) /* Ethos-U writable area */ } > RAM1 /* Initialized buffers in fast access RAM */ @@ -331,7 +330,7 @@ SECTIONS .rom2 : { - *(*nn_model) /* NN Model Binary Representation */ + *(ethos_model) /* Ethos-U model, command stream and constants */ } > ROM2 .rom3 : diff --git a/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/RTE/Device/SSE-300-MPS3/iar_linker_script.icf.src b/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/RTE/Device/SSE-300-MPS3/iar_linker_script.icf.src index ea02d53..7d05a92 100644 --- a/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/RTE/Device/SSE-300-MPS3/iar_linker_script.icf.src +++ b/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/RTE/Device/SSE-300-MPS3/iar_linker_script.icf.src @@ -42,8 +42,6 @@ define memory mem with size = 4G; define region ROM3_region = []; #endif -define region ROM_region = ROM0_region | ROM1_region | ROM2_region | ROM3_region; - #if __RAM0_SIZE > 0 define region RAM0_region = mem:[from __RAM0_BASE to (__RAM0_BASE+__RAM0_SIZE-1)]; #else @@ -68,8 +66,6 @@ define region ROM_region = ROM0_region | ROM1_region | ROM2_region | ROM3_regio define region RAM3_region = []; #endif -define region RAM_region = RAM0_region | RAM1_region | RAM2_region | RAM3_region; - do not initialize { section .noinit }; initialize by copy { readwrite }; if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) @@ -80,15 +76,37 @@ if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) place at address mem:__ROM0_BASE { readonly section .intvec }; -if (!isempty(ROM_region)) +if (!isempty(ROM1_region)) { - place in ROM_region { readonly }; + place in ROM1_region { readonly }; } -if (!isempty(RAM_region)) +if (!isempty(RAM0_region)) { define block CSTACK with alignment = 8, size = __STACK_SIZE { }; define block PROC_STACK with alignment = 8, size = 0 { }; define block HEAP with alignment = 8, size = __HEAP_SIZE { }; - place in RAM_region { readwrite, block CSTACK, block PROC_STACK, block HEAP }; + place in RAM0_region { readwrite, block PROC_STACK, block HEAP }; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + /* Reserve the stack seal immediately above the stack. */ + define block STACKSEAL with alignment = 8, size = 8 { }; + define block CSTACK_WITH_SEAL with fixed order { block CSTACK, block STACKSEAL }; + place at end of RAM0_region { block CSTACK_WITH_SEAL }; +#else + place at end of RAM0_region { block CSTACK }; +#endif } + +/* Ethos-U writable area */ +#if __RAM1_SIZE > 0 + do not initialize { section ethos_arena }; + define block ETHOS_ARENA with alignment = 32 + { section ethos_arena }; + place in RAM1_region { block ETHOS_ARENA }; +#endif + +/* Ethos-U model, command stream and constants */ +#if __ROM2_SIZE > 0 + define block ETHOS_MODEL with alignment = 32 { readonly section ethos_model }; + place in ROM2_region { block ETHOS_MODEL }; +#endif diff --git a/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/regions_SSE-300.h b/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/RTE/Device/SSE-300-MPS3/regions_SSE-300.h similarity index 100% rename from ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/regions_SSE-300.h rename to ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/RTE/Device/SSE-300-MPS3/regions_SSE-300.h diff --git a/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/sse300_memmap_ns.h b/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/RTE/Device/SSE-300-MPS3/sse300_memmap_ns.h similarity index 97% rename from ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/sse300_memmap_ns.h rename to ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/RTE/Device/SSE-300-MPS3/sse300_memmap_ns.h index d15a465..811a1c6 100644 --- a/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/sse300_memmap_ns.h +++ b/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/RTE/Device/SSE-300-MPS3/sse300_memmap_ns.h @@ -57,10 +57,10 @@ #define SRAM_VM1_NS_LIMIT (SRAM_VM1_NS_BASE + SRAM_VM1_NS_SIZE - 1) /*---------------------------------------------------------------------------*/ -/* Secure QSPI Flash Regions */ +/* Non-Secure QSPI Flash Regions */ /*---------------------------------------------------------------------------*/ -/* QSPI Flash - Secure */ +/* QSPI Flash - Non-Secure */ #define QSPI_FLASH_NS_BASE 0x28000000 #define QSPI_FLASH_NS_SIZE 0x00800000 /* 8MB */ #define QSPI_FLASH_NS_LIMIT (QSPI_FLASH_NS_BASE + QSPI_FLASH_NS_SIZE - 1) diff --git a/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/sse300_memmap_s.h b/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/RTE/Device/SSE-300-MPS3/sse300_memmap_s.h similarity index 100% rename from ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/sse300_memmap_s.h rename to ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/RTE/Device/SSE-300-MPS3/sse300_memmap_s.h diff --git a/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/ethos_setup.c b/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/ethos_setup.c index f154c77..d4033b3 100644 --- a/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/ethos_setup.c +++ b/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/ethos_setup.c @@ -1,5 +1,5 @@ -/*--------------------------------------------------------------------------- - * Copyright (c) 2025 Arm Limited (or its affiliates). All rights reserved. +/* + * Copyright 2025-2026 Arm Limited and/or its affiliates. * * SPDX-License-Identifier: Apache-2.0 * @@ -14,7 +14,7 @@ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. - *---------------------------------------------------------------------------*/ + */ #include @@ -26,18 +26,18 @@ #if defined(ETHOSU65) || defined(ETHOSU85) /* Define Ethos-U NPU cache buffer size */ -#ifndef ETHOS_CACHE_BUF_SIZE -#define ETHOS_CACHE_BUF_SIZE 393216 +#ifndef ETHOS_CACHE_SIZE +#define ETHOS_CACHE_SIZE 0 #endif /* Define Ethos-U cache buffer alignment */ -#ifndef ETHOS_CACHE_BUF_ALIGNMENT -#define ETHOS_CACHE_BUF_ALIGNMENT 32 +#ifndef ETHOS_CACHE_ALIGNMENT +#define ETHOS_CACHE_ALIGNMENT 32 #endif /* Define Ethos-U NPU cache buffer attributes */ -#ifndef ETHOS_CACHE_BUF_ATTRIBUTES -#define ETHOS_CACHE_BUF_ATTRIBUTES __attribute__((section("ethos_cache_buf"), aligned(ETHOS_CACHE_BUF_ALIGNMENT))) +#ifndef ETHOS_CACHE_ATTRIBUTES +#define ETHOS_CACHE_ATTRIBUTES __attribute__((section("ethos_cache"), aligned(ETHOS_CACHE_ALIGNMENT))) #endif #endif @@ -54,8 +54,9 @@ /* Ethos NPU driver instance. */ static struct ethosu_driver EthosDriver; -#if defined(ETHOSU65) || defined(ETHOSU85) -static uint8_t ethos_cache[ETHOS_CACHE_BUF_SIZE] ETHOS_CACHE_BUF_ATTRIBUTES; +#if (defined(ETHOSU65) || defined(ETHOSU85)) && (ETHOS_CACHE_SIZE > 0) +/* Ethos-U NPU cache buffer */ +static uint8_t ethos_cache_buf[ETHOS_CACHE_SIZE] ETHOS_CACHE_ATTRIBUTES; #endif /* @@ -76,9 +77,9 @@ void ethos_setup (void) { /* Initialize Ethos-U NPU driver. */ rval = ethosu_init(&EthosDriver, /* Ethos-U device driver */ ethos_base_addr, /* Ethos-U base address */ - #if defined(ETHOSU65) || defined(ETHOSU85) - ethos_cache, /* Cache memory pointer */ - sizeof(ethos_cache), /* Cache memory size */ + #if (defined(ETHOSU65) || defined(ETHOSU85)) && (ETHOS_CACHE_SIZE > 0) + ethos_cache_buf, /* Cache memory pointer */ + sizeof(ethos_cache_buf), /* Cache memory size */ #else 0, /* Cache memory pointer */ 0, /* Cache memory size */ diff --git a/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/ethosu_dcache.c b/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/ethosu_dcache.c new file mode 100644 index 0000000..015a9d1 --- /dev/null +++ b/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/ethosu_dcache.c @@ -0,0 +1,78 @@ +/* + * Copyright 2026 Arm Limited and/or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include + +#include "ethosu_driver.h" + +/** + \brief Cleans data-cache contents associated with buffers accessed by the NPU. + + Ensures that CPU writes to cacheable buffers are committed to memory before + the NPU starts accessing them. Non-cacheable buffers require no cache clean, + but the function ensures that all preceding memory accesses have completed + before it returns. + + \param[in] base_addr Array of buffer base addresses. + \param[in] base_addr_size Array containing the size, in bytes, of each buffer. + \param[in] num_base_addr Number of entries in the address and size arrays. +*/ +void ethosu_flush_dcache(const uint64_t *base_addr, const size_t *base_addr_size, int num_base_addr) { + + for (int i = 0; i < num_base_addr; i++) { + if ((base_addr[i] & 0x1F) != 0) { + /* Base address must be cache line aligned (32 bytes) */ + // ... + return; + } + + /* Flush data-cache for current buffer */ + // ... + // 32-bit system must cast base_addr to uint32_t* to avoid sign expansion + // CleanDCache((uint32_t *)(uint32_t)base_addr[i], base_addr_size[i]); + } +} + +/** + \brief Invalidates data-cache contents associated with buffers accessed by the NPU. + + Ensures that subsequent CPU reads observe data written by the NPU. Dirty + cache lines may be cleaned before invalidation to preserve pending CPU + writes. For non-cacheable buffers, no cache invalidation is required, + but the function ensures that all preceding memory accesses have completed + before it returns. + + \param[in] base_addr Array of buffer base addresses. + \param[in] base_addr_size Array containing the size, in bytes, of each buffer. + \param[in] num_base_addr Number of entries in the address and size arrays. +*/ +void ethosu_invalidate_dcache(const uint64_t *base_addr, const size_t *base_addr_size, int num_base_addr) { + + for (int i = 0; i < num_base_addr; i++) { + if ((base_addr[i] & 0x1F) != 0) { + /* Base address must be cache line aligned (32 bytes) */ + // ... + return; + } + + /* Invalidate data-cache for current buffer */ + // ... + // 32-bit system must cast base_addr to uint32_t* to avoid sign expansion + // InvalidateDCache((uint32_t *)(uint32_t)base_addr[i], base_addr_size[i]); + } +} diff --git a/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/ethosu_os_rtos2.c b/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/ethosu_os_rtos2.c new file mode 100644 index 0000000..fdab39b --- /dev/null +++ b/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/ethosu_os_rtos2.c @@ -0,0 +1,141 @@ +/* + * Copyright 2026 Arm Limited and/or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ethosu_driver.h" +#include "cmsis_os2.h" + +/* Maximum number of Ethos-U instances. */ +/* Used as maximum semaphore count in ethosu_semaphore_create. */ +#ifndef ETHOSU_MAX_INSTANCES +#define ETHOSU_MAX_INSTANCES 2 +#endif + +/** + \brief Create a mutex object. + \return Pointer to a mutex object. +*/ +void *ethosu_mutex_create(void) { + osMutexId_t mutex_id = osMutexNew(NULL); + return (void *) mutex_id; +} + +/** + \brief Destroy a mutex object. + \param[in] mutex mutex object. +*/ +void ethosu_mutex_destroy(void *mutex) { + osMutexId_t mutex_id = (osMutexId_t) mutex; + osMutexDelete(mutex_id); +} + +/** + \brief Lock a mutex. + \param[in] mutex mutex object. + \return 0 on success, else negative error codes +*/ +int ethosu_mutex_lock(void *mutex) { + osMutexId_t mutex_id = (osMutexId_t) mutex; + osStatus_t status; + int rval; + + status = osMutexAcquire(mutex_id, osWaitForever); + if (status == osOK) { + rval = 0; + } else { + rval = -1; + } + return rval; +} + +/** + \brief Unlock a mutex. + \param[in] mutex mutex object. + \return 0 on success, else negative error codes +*/ +int ethosu_mutex_unlock(void *mutex) { + osMutexId_t mutex_id = (osMutexId_t) mutex; + osStatus_t status; + int rval; + + status = osMutexRelease(mutex_id); + if (status == osOK) { + rval = 0; + } else { + rval = -1; + } + return rval; +} + +/** + \brief Create a semaphore object. + \return Pointer to a semaphore object. +*/ +void *ethosu_semaphore_create(void) { + osSemaphoreId_t sem_id; + + sem_id = osSemaphoreNew(ETHOSU_MAX_INSTANCES, 0U, NULL); + return (void *) sem_id; +} + +/** + \brief Destroy a semaphore object. + \param[in] sem semaphore object. +*/ +void ethosu_semaphore_destroy(void *sem) { + osSemaphoreId_t sem_id = (osSemaphoreId_t) sem; + osSemaphoreDelete(sem_id); +} + +/** + \brief Take a semaphore object with timeout. + \param[in] sem semaphore object. + \param[in] timeout timeout value in ticks. + \return 0 on success, else negative error codes +*/ +int ethosu_semaphore_take(void *sem, uint64_t timeout) { + osSemaphoreId_t sem_id = (osSemaphoreId_t) sem; + osStatus_t status; + int rval; + + status = osSemaphoreAcquire(sem_id, timeout); + if (status == osOK) { + rval = 0; + } else { + rval = -1; + } + return rval; +} + +/** + \brief Give a semaphore object. + \param[in] sem semaphore object. + \return 0 on success, else negative error codes +*/ +int ethosu_semaphore_give(void *sem) { + osSemaphoreId_t sem_id = (osSemaphoreId_t) sem; + osStatus_t status; + int rval; + + status = osSemaphoreRelease(sem_id); + if (status == osOK) { + rval = 0; + } else { + rval = -1; + } + return rval; +} diff --git a/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/fvp_config.txt b/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/fvp_config.txt index e818f72..c21ae24 100644 --- a/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/fvp_config.txt +++ b/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/fvp_config.txt @@ -1,7 +1,6 @@ # Parameters: # instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] #------------------------------------------------------------------------------ -ethosu.num_macs=256 # (int , init-time) default = '0x100' : Number of 8x8 MACs performed per cycle (32, 64, 128, or 256). mps3_board.telnetterminal0.quiet=1 # (bool , init-time) default = '0' : Avoid output on stdout/stderr mps3_board.telnetterminal0.start_telnet=0 # (bool , init-time) default = '1' : Start telnet if nothing connected mps3_board.telnetterminal1.quiet=1 # (bool , init-time) default = '0' : Avoid output on stdout/stderr diff --git a/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/fvp_config_u55.txt b/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/fvp_config_u55.txt new file mode 100644 index 0000000..ab75990 --- /dev/null +++ b/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/fvp_config_u55.txt @@ -0,0 +1,18 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +ethosu.num_macs=256 # (int , init-time) default = '0x100' : Number of 8x8 MACs performed per cycle (32, 64, 128, or 256). +mps3_board.telnetterminal0.quiet=1 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +mps3_board.telnetterminal0.start_telnet=0 # (bool , init-time) default = '1' : Start telnet if nothing connected +mps3_board.telnetterminal1.quiet=1 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +mps3_board.telnetterminal1.start_telnet=0 # (bool , init-time) default = '1' : Start telnet if nothing connected +mps3_board.telnetterminal2.quiet=1 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +mps3_board.telnetterminal2.start_telnet=0 # (bool , init-time) default = '1' : Start telnet if nothing connected +mps3_board.telnetterminal5.quiet=1 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +mps3_board.telnetterminal5.start_telnet=0 # (bool , init-time) default = '1' : Start telnet if nothing connected +mps3_board.uart0.out_file=- # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) +mps3_board.uart0.shutdown_on_eot=1 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) +mps3_board.visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation +#------------------------------------------------------------------------------ + +mps3_board.v_path=./Board/Corstone-300/vsi/python/ # Python VSI and VIO scripts diff --git a/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/fvp_config_u65.txt b/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/fvp_config_u65.txt new file mode 100644 index 0000000..ab75990 --- /dev/null +++ b/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/fvp_config_u65.txt @@ -0,0 +1,18 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +ethosu.num_macs=256 # (int , init-time) default = '0x100' : Number of 8x8 MACs performed per cycle (32, 64, 128, or 256). +mps3_board.telnetterminal0.quiet=1 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +mps3_board.telnetterminal0.start_telnet=0 # (bool , init-time) default = '1' : Start telnet if nothing connected +mps3_board.telnetterminal1.quiet=1 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +mps3_board.telnetterminal1.start_telnet=0 # (bool , init-time) default = '1' : Start telnet if nothing connected +mps3_board.telnetterminal2.quiet=1 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +mps3_board.telnetterminal2.start_telnet=0 # (bool , init-time) default = '1' : Start telnet if nothing connected +mps3_board.telnetterminal5.quiet=1 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +mps3_board.telnetterminal5.start_telnet=0 # (bool , init-time) default = '1' : Start telnet if nothing connected +mps3_board.uart0.out_file=- # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) +mps3_board.uart0.shutdown_on_eot=1 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) +mps3_board.visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation +#------------------------------------------------------------------------------ + +mps3_board.v_path=./Board/Corstone-300/vsi/python/ # Python VSI and VIO scripts diff --git a/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/main.c b/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/main.c index 69b3485..009aec0 100644 --- a/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/main.c +++ b/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/main.c @@ -1,5 +1,5 @@ -/*--------------------------------------------------------------------------- - * Copyright (c) 2024 Arm Limited (or its affiliates). All rights reserved. +/* + * Copyright 2024-2026 Arm Limited and/or its affiliates. * * SPDX-License-Identifier: Apache-2.0 * @@ -14,7 +14,7 @@ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. - *---------------------------------------------------------------------------*/ + */ #include "RTE_Components.h" #include CMSIS_device_header diff --git a/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/main.h b/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/main.h index 6e2048e..2b576ad 100644 --- a/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/main.h +++ b/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/main.h @@ -1,6 +1,6 @@ -/*--------------------------------------------------------------------------- - * Copyright (c) 2020-2025 Arm Limited (or its affiliates). - * All rights reserved. +/* + * Copyright 2020-2026 Arm Limited and/or its affiliates. + * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may @@ -14,7 +14,7 @@ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. - *---------------------------------------------------------------------------*/ + */ #ifndef MAIN_H__ #define MAIN_H__ diff --git a/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/retarget_stdio.c b/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/retarget_stdio.c deleted file mode 100644 index e1d15f6..0000000 --- a/ST/B-U585I-IOT02A/MotionRecognition/Board/Corstone-300/retarget_stdio.c +++ /dev/null @@ -1,161 +0,0 @@ -/*--------------------------------------------------------------------------- - * Copyright (c) 2025 Arm Limited (or its affiliates). - * All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * Name: retarget_stdio.c - * Purpose: Retarget stdio to CMSIS UART - * - *---------------------------------------------------------------------------*/ - -#ifdef CMSIS_target_header -#include CMSIS_target_header -#else -#include "Driver_USART.h" -#endif - -#ifndef RETARGET_STDIO_UART -#error "RETARGET_STDIO_UART not defined!" -#endif - -/* Compile-time configuration */ -#ifndef UART_BAUDRATE -#define UART_BAUDRATE 115200 -#endif - -/* References to the external retarget functions */ -extern int stdio_init (void); -extern int stderr_putchar (int ch); -extern int stdout_putchar (int ch); -extern int stdin_getchar (void); - -/* Reference to the underlying USART driver */ -#ifndef CMSIS_target_header -extern ARM_DRIVER_USART ARM_Driver_USART_(RETARGET_STDIO_UART); -#endif -#define ptrUSART (&ARM_Driver_USART_(RETARGET_STDIO_UART)) - -/** - Initialize stdio - - \return 0 on success, or -1 on error. -*/ -int stdio_init (void) { - - if (ptrUSART->Initialize(NULL) != ARM_DRIVER_OK) { - return -1; - } - - if (ptrUSART->PowerControl(ARM_POWER_FULL) != ARM_DRIVER_OK) { - return -1; - } - - if (ptrUSART->Control(ARM_USART_MODE_ASYNCHRONOUS | - ARM_USART_DATA_BITS_8 | - ARM_USART_PARITY_NONE | - ARM_USART_STOP_BITS_1 | - ARM_USART_FLOW_CONTROL_NONE, - UART_BAUDRATE) != ARM_DRIVER_OK) { - return -1; - } - - if (ptrUSART->Control(ARM_USART_CONTROL_RX, 1U) != ARM_DRIVER_OK) { - return -1; - } - - if (ptrUSART->Control(ARM_USART_CONTROL_TX, 1U) != ARM_DRIVER_OK) { - return -1; - } - - return 0; -} - -/** - Put a character to the stderr - - \param[in] ch Character to output - \return The character written, or -1 on write error. -*/ -int stderr_putchar (int ch) { - uint8_t buf[1]; - - if (ch == '\n') { - buf[0] = (uint8_t)'\r'; - - if (ptrUSART->Send(buf, 1U) != ARM_DRIVER_OK) { - return -1; - } - - while (ptrUSART->GetStatus().tx_busy != 0U); - } - - buf[0] = (uint8_t)ch; - - if (ptrUSART->Send(buf, 1U) != ARM_DRIVER_OK) { - return -1; - } - - while (ptrUSART->GetStatus().tx_busy != 0U); - - return ch; -} - -/** - Put a character to the stdout - - \param[in] ch Character to output - \return The character written, or -1 on write error. -*/ -int stdout_putchar (int ch) { - uint8_t buf[1]; - - if (ch == '\n') { - buf[0] = (uint8_t)'\r'; - - if (ptrUSART->Send(buf, 1U) != ARM_DRIVER_OK) { - return -1; - } - - while (ptrUSART->GetStatus().tx_busy != 0U); - } - - buf[0] = (uint8_t)ch; - - if (ptrUSART->Send(buf, 1U) != ARM_DRIVER_OK) { - return -1; - } - - while (ptrUSART->GetStatus().tx_busy != 0U); - - return ch; -} - -/** - Get a character from the stdio - - \return The next character from the input, or -1 on read error. -*/ -int stdin_getchar (void) { - uint8_t buf[1]; - - if (ptrUSART->Receive(buf, 1U) != ARM_DRIVER_OK) { - return -1; - } - - while (ptrUSART->GetStatus().rx_busy != 0U); - - return (int)buf[0]; -} diff --git a/ST/B-U585I-IOT02A/MotionRecognition/SDS.csolution.yml b/ST/B-U585I-IOT02A/MotionRecognition/SDS.csolution.yml index f69536c..02beac6 100644 --- a/ST/B-U585I-IOT02A/MotionRecognition/SDS.csolution.yml +++ b/ST/B-U585I-IOT02A/MotionRecognition/SDS.csolution.yml @@ -53,7 +53,7 @@ solution: debugger: name: Arm-FVP model: FVP_Corstone_SSE-300_Ethos-U55 - config-file: Board/Corstone-300/fvp_config.txt + config-file: Board/Corstone-300/fvp_config_u55.txt # List of different build configurations. build-types: